diff options
author | Jesse Brandeburg <jesse.brandeburg@intel.com> | 2007-04-26 12:43:20 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-04-28 11:01:07 -0400 |
commit | 27345bb684140f5f306963e0d6e25a60c7857dfe (patch) | |
tree | 42e1b2f807e980623d3fe131a57a801473051138 | |
parent | 948cd43fed7c7d919fa30e0609b2b5852c4503ef (diff) |
e100: Optionally use I/O mode only to access register space
It appears that some systems still like e100 better if it uses
I/O access mode. Setting the new parameter use_io=1 will cause
all driver instances to use io mapping to access the register
space on the e100 device.
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r-- | drivers/net/e100.c | 72 |
1 files changed, 39 insertions, 33 deletions
diff --git a/drivers/net/e100.c b/drivers/net/e100.c index 135617c5941f..61696637a21e 100644 --- a/drivers/net/e100.c +++ b/drivers/net/e100.c | |||
@@ -159,7 +159,7 @@ | |||
159 | 159 | ||
160 | #define DRV_NAME "e100" | 160 | #define DRV_NAME "e100" |
161 | #define DRV_EXT "-NAPI" | 161 | #define DRV_EXT "-NAPI" |
162 | #define DRV_VERSION "3.5.17-k2"DRV_EXT | 162 | #define DRV_VERSION "3.5.17-k4"DRV_EXT |
163 | #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" | 163 | #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" |
164 | #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation" | 164 | #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation" |
165 | #define PFX DRV_NAME ": " | 165 | #define PFX DRV_NAME ": " |
@@ -174,10 +174,13 @@ MODULE_VERSION(DRV_VERSION); | |||
174 | 174 | ||
175 | static int debug = 3; | 175 | static int debug = 3; |
176 | static int eeprom_bad_csum_allow = 0; | 176 | static int eeprom_bad_csum_allow = 0; |
177 | static int use_io = 0; | ||
177 | module_param(debug, int, 0); | 178 | module_param(debug, int, 0); |
178 | module_param(eeprom_bad_csum_allow, int, 0); | 179 | module_param(eeprom_bad_csum_allow, int, 0); |
180 | module_param(use_io, int, 0); | ||
179 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | 181 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); |
180 | MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums"); | 182 | MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums"); |
183 | MODULE_PARM_DESC(use_io, "Force use of i/o access mode"); | ||
181 | #define DPRINTK(nlevel, klevel, fmt, args...) \ | 184 | #define DPRINTK(nlevel, klevel, fmt, args...) \ |
182 | (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \ | 185 | (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \ |
183 | printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \ | 186 | printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \ |
@@ -584,7 +587,7 @@ static inline void e100_write_flush(struct nic *nic) | |||
584 | { | 587 | { |
585 | /* Flush previous PCI writes through intermediate bridges | 588 | /* Flush previous PCI writes through intermediate bridges |
586 | * by doing a benign read */ | 589 | * by doing a benign read */ |
587 | (void)readb(&nic->csr->scb.status); | 590 | (void)ioread8(&nic->csr->scb.status); |
588 | } | 591 | } |
589 | 592 | ||
590 | static void e100_enable_irq(struct nic *nic) | 593 | static void e100_enable_irq(struct nic *nic) |
@@ -592,7 +595,7 @@ static void e100_enable_irq(struct nic *nic) | |||
592 | unsigned long flags; | 595 | unsigned long flags; |
593 | 596 | ||
594 | spin_lock_irqsave(&nic->cmd_lock, flags); | 597 | spin_lock_irqsave(&nic->cmd_lock, flags); |
595 | writeb(irq_mask_none, &nic->csr->scb.cmd_hi); | 598 | iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi); |
596 | e100_write_flush(nic); | 599 | e100_write_flush(nic); |
597 | spin_unlock_irqrestore(&nic->cmd_lock, flags); | 600 | spin_unlock_irqrestore(&nic->cmd_lock, flags); |
598 | } | 601 | } |
@@ -602,7 +605,7 @@ static void e100_disable_irq(struct nic *nic) | |||
602 | unsigned long flags; | 605 | unsigned long flags; |
603 | 606 | ||
604 | spin_lock_irqsave(&nic->cmd_lock, flags); | 607 | spin_lock_irqsave(&nic->cmd_lock, flags); |
605 | writeb(irq_mask_all, &nic->csr->scb.cmd_hi); | 608 | iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi); |
606 | e100_write_flush(nic); | 609 | e100_write_flush(nic); |
607 | spin_unlock_irqrestore(&nic->cmd_lock, flags); | 610 | spin_unlock_irqrestore(&nic->cmd_lock, flags); |
608 | } | 611 | } |
@@ -611,11 +614,11 @@ static void e100_hw_reset(struct nic *nic) | |||
611 | { | 614 | { |
612 | /* Put CU and RU into idle with a selective reset to get | 615 | /* Put CU and RU into idle with a selective reset to get |
613 | * device off of PCI bus */ | 616 | * device off of PCI bus */ |
614 | writel(selective_reset, &nic->csr->port); | 617 | iowrite32(selective_reset, &nic->csr->port); |
615 | e100_write_flush(nic); udelay(20); | 618 | e100_write_flush(nic); udelay(20); |
616 | 619 | ||
617 | /* Now fully reset device */ | 620 | /* Now fully reset device */ |
618 | writel(software_reset, &nic->csr->port); | 621 | iowrite32(software_reset, &nic->csr->port); |
619 | e100_write_flush(nic); udelay(20); | 622 | e100_write_flush(nic); udelay(20); |
620 | 623 | ||
621 | /* Mask off our interrupt line - it's unmasked after reset */ | 624 | /* Mask off our interrupt line - it's unmasked after reset */ |
@@ -632,7 +635,7 @@ static int e100_self_test(struct nic *nic) | |||
632 | nic->mem->selftest.signature = 0; | 635 | nic->mem->selftest.signature = 0; |
633 | nic->mem->selftest.result = 0xFFFFFFFF; | 636 | nic->mem->selftest.result = 0xFFFFFFFF; |
634 | 637 | ||
635 | writel(selftest | dma_addr, &nic->csr->port); | 638 | iowrite32(selftest | dma_addr, &nic->csr->port); |
636 | e100_write_flush(nic); | 639 | e100_write_flush(nic); |
637 | /* Wait 10 msec for self-test to complete */ | 640 | /* Wait 10 msec for self-test to complete */ |
638 | msleep(10); | 641 | msleep(10); |
@@ -670,23 +673,23 @@ static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data) | |||
670 | for(j = 0; j < 3; j++) { | 673 | for(j = 0; j < 3; j++) { |
671 | 674 | ||
672 | /* Chip select */ | 675 | /* Chip select */ |
673 | writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo); | 676 | iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo); |
674 | e100_write_flush(nic); udelay(4); | 677 | e100_write_flush(nic); udelay(4); |
675 | 678 | ||
676 | for(i = 31; i >= 0; i--) { | 679 | for(i = 31; i >= 0; i--) { |
677 | ctrl = (cmd_addr_data[j] & (1 << i)) ? | 680 | ctrl = (cmd_addr_data[j] & (1 << i)) ? |
678 | eecs | eedi : eecs; | 681 | eecs | eedi : eecs; |
679 | writeb(ctrl, &nic->csr->eeprom_ctrl_lo); | 682 | iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo); |
680 | e100_write_flush(nic); udelay(4); | 683 | e100_write_flush(nic); udelay(4); |
681 | 684 | ||
682 | writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo); | 685 | iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo); |
683 | e100_write_flush(nic); udelay(4); | 686 | e100_write_flush(nic); udelay(4); |
684 | } | 687 | } |
685 | /* Wait 10 msec for cmd to complete */ | 688 | /* Wait 10 msec for cmd to complete */ |
686 | msleep(10); | 689 | msleep(10); |
687 | 690 | ||
688 | /* Chip deselect */ | 691 | /* Chip deselect */ |
689 | writeb(0, &nic->csr->eeprom_ctrl_lo); | 692 | iowrite8(0, &nic->csr->eeprom_ctrl_lo); |
690 | e100_write_flush(nic); udelay(4); | 693 | e100_write_flush(nic); udelay(4); |
691 | } | 694 | } |
692 | }; | 695 | }; |
@@ -702,21 +705,21 @@ static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr) | |||
702 | cmd_addr_data = ((op_read << *addr_len) | addr) << 16; | 705 | cmd_addr_data = ((op_read << *addr_len) | addr) << 16; |
703 | 706 | ||
704 | /* Chip select */ | 707 | /* Chip select */ |
705 | writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo); | 708 | iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo); |
706 | e100_write_flush(nic); udelay(4); | 709 | e100_write_flush(nic); udelay(4); |
707 | 710 | ||
708 | /* Bit-bang to read word from eeprom */ | 711 | /* Bit-bang to read word from eeprom */ |
709 | for(i = 31; i >= 0; i--) { | 712 | for(i = 31; i >= 0; i--) { |
710 | ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs; | 713 | ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs; |
711 | writeb(ctrl, &nic->csr->eeprom_ctrl_lo); | 714 | iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo); |
712 | e100_write_flush(nic); udelay(4); | 715 | e100_write_flush(nic); udelay(4); |
713 | 716 | ||
714 | writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo); | 717 | iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo); |
715 | e100_write_flush(nic); udelay(4); | 718 | e100_write_flush(nic); udelay(4); |
716 | 719 | ||
717 | /* Eeprom drives a dummy zero to EEDO after receiving | 720 | /* Eeprom drives a dummy zero to EEDO after receiving |
718 | * complete address. Use this to adjust addr_len. */ | 721 | * complete address. Use this to adjust addr_len. */ |
719 | ctrl = readb(&nic->csr->eeprom_ctrl_lo); | 722 | ctrl = ioread8(&nic->csr->eeprom_ctrl_lo); |
720 | if(!(ctrl & eedo) && i > 16) { | 723 | if(!(ctrl & eedo) && i > 16) { |
721 | *addr_len -= (i - 16); | 724 | *addr_len -= (i - 16); |
722 | i = 17; | 725 | i = 17; |
@@ -726,7 +729,7 @@ static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr) | |||
726 | } | 729 | } |
727 | 730 | ||
728 | /* Chip deselect */ | 731 | /* Chip deselect */ |
729 | writeb(0, &nic->csr->eeprom_ctrl_lo); | 732 | iowrite8(0, &nic->csr->eeprom_ctrl_lo); |
730 | e100_write_flush(nic); udelay(4); | 733 | e100_write_flush(nic); udelay(4); |
731 | 734 | ||
732 | return le16_to_cpu(data); | 735 | return le16_to_cpu(data); |
@@ -797,7 +800,7 @@ static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr) | |||
797 | 800 | ||
798 | /* Previous command is accepted when SCB clears */ | 801 | /* Previous command is accepted when SCB clears */ |
799 | for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) { | 802 | for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) { |
800 | if(likely(!readb(&nic->csr->scb.cmd_lo))) | 803 | if(likely(!ioread8(&nic->csr->scb.cmd_lo))) |
801 | break; | 804 | break; |
802 | cpu_relax(); | 805 | cpu_relax(); |
803 | if(unlikely(i > E100_WAIT_SCB_FAST)) | 806 | if(unlikely(i > E100_WAIT_SCB_FAST)) |
@@ -809,8 +812,8 @@ static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr) | |||
809 | } | 812 | } |
810 | 813 | ||
811 | if(unlikely(cmd != cuc_resume)) | 814 | if(unlikely(cmd != cuc_resume)) |
812 | writel(dma_addr, &nic->csr->scb.gen_ptr); | 815 | iowrite32(dma_addr, &nic->csr->scb.gen_ptr); |
813 | writeb(cmd, &nic->csr->scb.cmd_lo); | 816 | iowrite8(cmd, &nic->csr->scb.cmd_lo); |
814 | 817 | ||
815 | err_unlock: | 818 | err_unlock: |
816 | spin_unlock_irqrestore(&nic->cmd_lock, flags); | 819 | spin_unlock_irqrestore(&nic->cmd_lock, flags); |
@@ -888,7 +891,7 @@ static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data) | |||
888 | */ | 891 | */ |
889 | spin_lock_irqsave(&nic->mdio_lock, flags); | 892 | spin_lock_irqsave(&nic->mdio_lock, flags); |
890 | for (i = 100; i; --i) { | 893 | for (i = 100; i; --i) { |
891 | if (readl(&nic->csr->mdi_ctrl) & mdi_ready) | 894 | if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready) |
892 | break; | 895 | break; |
893 | udelay(20); | 896 | udelay(20); |
894 | } | 897 | } |
@@ -898,11 +901,11 @@ static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data) | |||
898 | spin_unlock_irqrestore(&nic->mdio_lock, flags); | 901 | spin_unlock_irqrestore(&nic->mdio_lock, flags); |
899 | return 0; /* No way to indicate timeout error */ | 902 | return 0; /* No way to indicate timeout error */ |
900 | } | 903 | } |
901 | writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl); | 904 | iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl); |
902 | 905 | ||
903 | for (i = 0; i < 100; i++) { | 906 | for (i = 0; i < 100; i++) { |
904 | udelay(20); | 907 | udelay(20); |
905 | if ((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready) | 908 | if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready) |
906 | break; | 909 | break; |
907 | } | 910 | } |
908 | spin_unlock_irqrestore(&nic->mdio_lock, flags); | 911 | spin_unlock_irqrestore(&nic->mdio_lock, flags); |
@@ -1311,7 +1314,7 @@ static inline int e100_exec_cb_wait(struct nic *nic, struct sk_buff *skb, | |||
1311 | } | 1314 | } |
1312 | 1315 | ||
1313 | /* ack any interupts, something could have been set */ | 1316 | /* ack any interupts, something could have been set */ |
1314 | writeb(~0, &nic->csr->scb.stat_ack); | 1317 | iowrite8(~0, &nic->csr->scb.stat_ack); |
1315 | 1318 | ||
1316 | /* if the command failed, or is not OK, notify and return */ | 1319 | /* if the command failed, or is not OK, notify and return */ |
1317 | if (!counter || !(cb->status & cpu_to_le16(cb_ok))) { | 1320 | if (!counter || !(cb->status & cpu_to_le16(cb_ok))) { |
@@ -1573,7 +1576,7 @@ static void e100_watchdog(unsigned long data) | |||
1573 | * accidentally, due to hardware that shares a register between the | 1576 | * accidentally, due to hardware that shares a register between the |
1574 | * interrupt mask bit and the SW Interrupt generation bit */ | 1577 | * interrupt mask bit and the SW Interrupt generation bit */ |
1575 | spin_lock_irq(&nic->cmd_lock); | 1578 | spin_lock_irq(&nic->cmd_lock); |
1576 | writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi); | 1579 | iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi); |
1577 | e100_write_flush(nic); | 1580 | e100_write_flush(nic); |
1578 | spin_unlock_irq(&nic->cmd_lock); | 1581 | spin_unlock_irq(&nic->cmd_lock); |
1579 | 1582 | ||
@@ -1902,7 +1905,7 @@ static irqreturn_t e100_intr(int irq, void *dev_id) | |||
1902 | { | 1905 | { |
1903 | struct net_device *netdev = dev_id; | 1906 | struct net_device *netdev = dev_id; |
1904 | struct nic *nic = netdev_priv(netdev); | 1907 | struct nic *nic = netdev_priv(netdev); |
1905 | u8 stat_ack = readb(&nic->csr->scb.stat_ack); | 1908 | u8 stat_ack = ioread8(&nic->csr->scb.stat_ack); |
1906 | 1909 | ||
1907 | DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack); | 1910 | DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack); |
1908 | 1911 | ||
@@ -1911,7 +1914,7 @@ static irqreturn_t e100_intr(int irq, void *dev_id) | |||
1911 | return IRQ_NONE; | 1914 | return IRQ_NONE; |
1912 | 1915 | ||
1913 | /* Ack interrupt(s) */ | 1916 | /* Ack interrupt(s) */ |
1914 | writeb(stat_ack, &nic->csr->scb.stat_ack); | 1917 | iowrite8(stat_ack, &nic->csr->scb.stat_ack); |
1915 | 1918 | ||
1916 | if(likely(netif_rx_schedule_prep(netdev))) { | 1919 | if(likely(netif_rx_schedule_prep(netdev))) { |
1917 | e100_disable_irq(nic); | 1920 | e100_disable_irq(nic); |
@@ -2053,7 +2056,7 @@ static void e100_tx_timeout_task(struct work_struct *work) | |||
2053 | struct net_device *netdev = nic->netdev; | 2056 | struct net_device *netdev = nic->netdev; |
2054 | 2057 | ||
2055 | DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n", | 2058 | DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n", |
2056 | readb(&nic->csr->scb.status)); | 2059 | ioread8(&nic->csr->scb.status)); |
2057 | e100_down(netdev_priv(netdev)); | 2060 | e100_down(netdev_priv(netdev)); |
2058 | e100_up(netdev_priv(netdev)); | 2061 | e100_up(netdev_priv(netdev)); |
2059 | } | 2062 | } |
@@ -2176,9 +2179,9 @@ static void e100_get_regs(struct net_device *netdev, | |||
2176 | int i; | 2179 | int i; |
2177 | 2180 | ||
2178 | regs->version = (1 << 24) | nic->rev_id; | 2181 | regs->version = (1 << 24) | nic->rev_id; |
2179 | buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 | | 2182 | buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 | |
2180 | readb(&nic->csr->scb.cmd_lo) << 16 | | 2183 | ioread8(&nic->csr->scb.cmd_lo) << 16 | |
2181 | readw(&nic->csr->scb.status); | 2184 | ioread16(&nic->csr->scb.status); |
2182 | for(i = E100_PHY_REGS; i >= 0; i--) | 2185 | for(i = E100_PHY_REGS; i >= 0; i--) |
2183 | buff[1 + E100_PHY_REGS - i] = | 2186 | buff[1 + E100_PHY_REGS - i] = |
2184 | mdio_read(netdev, nic->mii.phy_id, i); | 2187 | mdio_read(netdev, nic->mii.phy_id, i); |
@@ -2550,7 +2553,10 @@ static int __devinit e100_probe(struct pci_dev *pdev, | |||
2550 | SET_MODULE_OWNER(netdev); | 2553 | SET_MODULE_OWNER(netdev); |
2551 | SET_NETDEV_DEV(netdev, &pdev->dev); | 2554 | SET_NETDEV_DEV(netdev, &pdev->dev); |
2552 | 2555 | ||
2553 | nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr)); | 2556 | if (use_io) |
2557 | DPRINTK(PROBE, INFO, "using i/o access mode\n"); | ||
2558 | |||
2559 | nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr)); | ||
2554 | if(!nic->csr) { | 2560 | if(!nic->csr) { |
2555 | DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n"); | 2561 | DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n"); |
2556 | err = -ENOMEM; | 2562 | err = -ENOMEM; |
@@ -2627,7 +2633,7 @@ static int __devinit e100_probe(struct pci_dev *pdev, | |||
2627 | 2633 | ||
2628 | DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, " | 2634 | DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, " |
2629 | "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n", | 2635 | "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n", |
2630 | (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, | 2636 | (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0), pdev->irq, |
2631 | netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2], | 2637 | netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2], |
2632 | netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]); | 2638 | netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]); |
2633 | 2639 | ||
@@ -2636,7 +2642,7 @@ static int __devinit e100_probe(struct pci_dev *pdev, | |||
2636 | err_out_free: | 2642 | err_out_free: |
2637 | e100_free(nic); | 2643 | e100_free(nic); |
2638 | err_out_iounmap: | 2644 | err_out_iounmap: |
2639 | iounmap(nic->csr); | 2645 | pci_iounmap(pdev, nic->csr); |
2640 | err_out_free_res: | 2646 | err_out_free_res: |
2641 | pci_release_regions(pdev); | 2647 | pci_release_regions(pdev); |
2642 | err_out_disable_pdev: | 2648 | err_out_disable_pdev: |