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authorSriram <srk@ti.com>2009-10-06 22:44:30 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-13 15:02:53 -0400
commit0fe7463a35aadfaf22d1ca58325ab3851b8d757c (patch)
treea61b3d59ebc28c3eea7134680e250d2ddd261a40
parentdaf9df6d8d0f5a4a406632d4da027655d065d3ba (diff)
TI DaVinci EMAC: Clear statistics register properly.
The mechanism to clear the statistics register is dependent on the status of GMIIEN bit in MAC control register. If the GMIIEN bit is set, the stats registers are write to decrement. If the GMIIEN bit is cleared, the stats registers are plain read/write registers. The stats register clearing operation must take into account the current state of GMIIEN as it can be cleared when the interface is brought down. With existing implementation logic, querying for interface stats when the interface is down, can corrupt the statistics counters. This patch examines the GMIIEN bit status in MAC_CONTROL register before choosing an appropriate mask for clearing stats registers. Signed-off-by: Sriramakrishnan <srk@ti.com> Acked-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/davinci_emac.c36
1 files changed, 24 insertions, 12 deletions
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 65a2d0ba64e2..f72c56dec33c 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -333,6 +333,9 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
333#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) 333#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
334#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) 334#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
335 335
336/* EMAC Stats Clear Mask */
337#define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
338
336/** net_buf_obj: EMAC network bufferdata structure 339/** net_buf_obj: EMAC network bufferdata structure
337 * 340 *
338 * EMAC network buffer data structure 341 * EMAC network buffer data structure
@@ -2548,40 +2551,49 @@ static int emac_dev_stop(struct net_device *ndev)
2548static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) 2551static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2549{ 2552{
2550 struct emac_priv *priv = netdev_priv(ndev); 2553 struct emac_priv *priv = netdev_priv(ndev);
2554 u32 mac_control;
2555 u32 stats_clear_mask;
2551 2556
2552 /* update emac hardware stats and reset the registers*/ 2557 /* update emac hardware stats and reset the registers*/
2553 2558
2559 mac_control = emac_read(EMAC_MACCONTROL);
2560
2561 if (mac_control & EMAC_MACCONTROL_GMIIEN)
2562 stats_clear_mask = EMAC_STATS_CLR_MASK;
2563 else
2564 stats_clear_mask = 0;
2565
2554 priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES); 2566 priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2555 emac_write(EMAC_RXMCASTFRAMES, EMAC_ALL_MULTI_REG_VALUE); 2567 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
2556 2568
2557 priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) + 2569 priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2558 emac_read(EMAC_TXSINGLECOLL) + 2570 emac_read(EMAC_TXSINGLECOLL) +
2559 emac_read(EMAC_TXMULTICOLL)); 2571 emac_read(EMAC_TXMULTICOLL));
2560 emac_write(EMAC_TXCOLLISION, EMAC_ALL_MULTI_REG_VALUE); 2572 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2561 emac_write(EMAC_TXSINGLECOLL, EMAC_ALL_MULTI_REG_VALUE); 2573 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2562 emac_write(EMAC_TXMULTICOLL, EMAC_ALL_MULTI_REG_VALUE); 2574 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
2563 2575
2564 priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + 2576 priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2565 emac_read(EMAC_RXJABBER) + 2577 emac_read(EMAC_RXJABBER) +
2566 emac_read(EMAC_RXUNDERSIZED)); 2578 emac_read(EMAC_RXUNDERSIZED));
2567 emac_write(EMAC_RXOVERSIZED, EMAC_ALL_MULTI_REG_VALUE); 2579 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2568 emac_write(EMAC_RXJABBER, EMAC_ALL_MULTI_REG_VALUE); 2580 emac_write(EMAC_RXJABBER, stats_clear_mask);
2569 emac_write(EMAC_RXUNDERSIZED, EMAC_ALL_MULTI_REG_VALUE); 2581 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
2570 2582
2571 priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + 2583 priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2572 emac_read(EMAC_RXMOFOVERRUNS)); 2584 emac_read(EMAC_RXMOFOVERRUNS));
2573 emac_write(EMAC_RXSOFOVERRUNS, EMAC_ALL_MULTI_REG_VALUE); 2585 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2574 emac_write(EMAC_RXMOFOVERRUNS, EMAC_ALL_MULTI_REG_VALUE); 2586 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
2575 2587
2576 priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); 2588 priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2577 emac_write(EMAC_RXDMAOVERRUNS, EMAC_ALL_MULTI_REG_VALUE); 2589 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
2578 2590
2579 priv->net_dev_stats.tx_carrier_errors += 2591 priv->net_dev_stats.tx_carrier_errors +=
2580 emac_read(EMAC_TXCARRIERSENSE); 2592 emac_read(EMAC_TXCARRIERSENSE);
2581 emac_write(EMAC_TXCARRIERSENSE, EMAC_ALL_MULTI_REG_VALUE); 2593 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2582 2594
2583 priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); 2595 priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2584 emac_write(EMAC_TXUNDERRUN, EMAC_ALL_MULTI_REG_VALUE); 2596 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2585 2597
2586 return &priv->net_dev_stats; 2598 return &priv->net_dev_stats;
2587} 2599}