[MIPS] Early check for SMTC kernel on non-MT processor

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 52 insertions, 0 deletions

diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-mips/kernel-entry-init.h
new file mode 100644
index 000000000000..0b793e7bf67e
--- /dev/null
+++ b/include/asm-mips/mach-mips/kernel-entry-init.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Chris Dearman (chris@mips.com)
+ * Copyright (C) 2007 Mips Technologies, Inc.
+ */
+#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+
+        .macro  kernel_entry_setup
+#ifdef CONFIG_MIPS_MT_SMTC
+        mfc0    t0, CP0_CONFIG
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 1
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 2
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 3
+        and     t0, 1<<2
+        bnez    t0, 0f
+9:
+        /* Assume we came from YAMON... */
+        PTR_LA  v0, 0x9fc00534  /* YAMON print */
+        lw      v0, (v0)
+        move    a0, zero
+        PTR_LA  a1, nonmt_processor
+        jal     v0
+
+        PTR_LA  v0, 0x9fc00520  /* YAMON exit */
+        lw      v0, (v0)
+        li      a0, 1
+        jal     v0
+
+1:      b       1b
+
+        __INITDATA
+nonmt_processor:
+        .asciz  "SMTC kernel requires the MT ASE to run\n"
+        __FINIT
+0:
+#endif
+        .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */