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authorMagnus Damm <damm@opensource.se>2010-05-11 09:29:17 -0400
committerPaul Mundt <lethal@linux-sh.org>2010-05-13 04:39:07 -0400
commitd28bdf05f72238d626c8d06b61049f6df8d78e70 (patch)
treea158ade083c1fd373b0f024b1b98c697f147d1e2
parent441c2440aba2efd8d0f48a5e3357deec92283d62 (diff)
sh: move sh asm/clock.h contents to linux/sh_clk.h V2
This patch is V2 of the clock framework move from arch/sh/include/asm/clock.h to include/linux/sh_clk.h and updates the include paths for files that will be shared between SH and SH-Mobile ARM. The file asm/clock.h is still kept in this version, this to depend on as few files as possible at this point. We keep SH specific stuff in there. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat
-rw-r--r--arch/sh/include/asm/clock.h147
-rw-r--r--include/linux/sh_clk.h151
2 files changed, 152 insertions, 146 deletions
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 35d219616110..f387e5caee16 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -1,158 +1,13 @@
1#ifndef __ASM_SH_CLOCK_H 1#ifndef __ASM_SH_CLOCK_H
2#define __ASM_SH_CLOCK_H 2#define __ASM_SH_CLOCK_H
3 3
4#include <linux/list.h> 4#include <linux/sh_clk.h>
5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
7#include <linux/clk.h>
8#include <linux/err.h>
9
10struct clk;
11
12struct clk_ops {
13 void (*init)(struct clk *clk);
14 int (*enable)(struct clk *clk);
15 void (*disable)(struct clk *clk);
16 unsigned long (*recalc)(struct clk *clk);
17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
18 int (*set_parent)(struct clk *clk, struct clk *parent);
19 long (*round_rate)(struct clk *clk, unsigned long rate);
20};
21
22struct clk {
23 struct list_head node;
24 const char *name;
25 int id;
26
27 struct clk *parent;
28 struct clk_ops *ops;
29
30 struct list_head children;
31 struct list_head sibling; /* node for children */
32
33 int usecount;
34
35 unsigned long rate;
36 unsigned long flags;
37
38 void __iomem *enable_reg;
39 unsigned int enable_bit;
40
41 unsigned long arch_flags;
42 void *priv;
43 struct dentry *dentry;
44 struct cpufreq_frequency_table *freq_table;
45};
46
47#define CLK_ENABLE_ON_INIT (1 << 0)
48 5
49/* Should be defined by processor-specific code */ 6/* Should be defined by processor-specific code */
50void __deprecated arch_init_clk_ops(struct clk_ops **, int type); 7void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
51int __init arch_clk_init(void); 8int __init arch_clk_init(void);
52 9
53/* arch/sh/kernel/cpu/clock.c */
54int clk_init(void);
55unsigned long followparent_recalc(struct clk *);
56void recalculate_root_clocks(void);
57void propagate_rate(struct clk *);
58int clk_reparent(struct clk *child, struct clk *parent);
59int clk_register(struct clk *);
60void clk_unregister(struct clk *);
61
62/* arch/sh/kernel/cpu/clock-cpg.c */ 10/* arch/sh/kernel/cpu/clock-cpg.c */
63int __init __deprecated cpg_clk_init(void); 11int __init __deprecated cpg_clk_init(void);
64 12
65/* the exported API, in addition to clk_set_rate */
66/**
67 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
68 * @clk: clock source
69 * @rate: desired clock rate in Hz
70 * @algo_id: algorithm id to be passed down to ops->set_rate
71 *
72 * Returns success (0) or negative errno.
73 */
74int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
75
76enum clk_sh_algo_id {
77 NO_CHANGE = 0,
78
79 IUS_N1_N1,
80 IUS_322,
81 IUS_522,
82 IUS_N11,
83
84 SB_N1,
85
86 SB3_N1,
87 SB3_32,
88 SB3_43,
89 SB3_54,
90
91 BP_N1,
92
93 IP_N1,
94};
95
96struct clk_div_mult_table {
97 unsigned int *divisors;
98 unsigned int nr_divisors;
99 unsigned int *multipliers;
100 unsigned int nr_multipliers;
101};
102
103struct cpufreq_frequency_table;
104void clk_rate_table_build(struct clk *clk,
105 struct cpufreq_frequency_table *freq_table,
106 int nr_freqs,
107 struct clk_div_mult_table *src_table,
108 unsigned long *bitmap);
109
110long clk_rate_table_round(struct clk *clk,
111 struct cpufreq_frequency_table *freq_table,
112 unsigned long rate);
113
114int clk_rate_table_find(struct clk *clk,
115 struct cpufreq_frequency_table *freq_table,
116 unsigned long rate);
117
118#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
119{ \
120 .parent = _parent, \
121 .enable_reg = (void __iomem *)_enable_reg, \
122 .enable_bit = _enable_bit, \
123 .flags = _flags, \
124}
125
126int sh_clk_mstp32_register(struct clk *clks, int nr);
127
128#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
129{ \
130 .parent = _parent, \
131 .enable_reg = (void __iomem *)_reg, \
132 .enable_bit = _shift, \
133 .arch_flags = _div_bitmap, \
134 .flags = _flags, \
135}
136
137struct clk_div4_table {
138 struct clk_div_mult_table *div_mult_table;
139 void (*kick)(struct clk *clk);
140};
141
142int sh_clk_div4_register(struct clk *clks, int nr,
143 struct clk_div4_table *table);
144int sh_clk_div4_enable_register(struct clk *clks, int nr,
145 struct clk_div4_table *table);
146int sh_clk_div4_reparent_register(struct clk *clks, int nr,
147 struct clk_div4_table *table);
148
149#define SH_CLK_DIV6(_parent, _reg, _flags) \
150{ \
151 .parent = _parent, \
152 .enable_reg = (void __iomem *)_reg, \
153 .flags = _flags, \
154}
155
156int sh_clk_div6_register(struct clk *clks, int nr);
157
158#endif /* __ASM_SH_CLOCK_H */ 13#endif /* __ASM_SH_CLOCK_H */
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
new file mode 100644
index 000000000000..de911451c216
--- /dev/null
+++ b/include/linux/sh_clk.h
@@ -0,0 +1,151 @@
1#ifndef __SH_CLOCK_H
2#define __SH_CLOCK_H
3
4#include <linux/list.h>
5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
7#include <linux/clk.h>
8#include <linux/err.h>
9
10struct clk;
11
12struct clk_ops {
13 void (*init)(struct clk *clk);
14 int (*enable)(struct clk *clk);
15 void (*disable)(struct clk *clk);
16 unsigned long (*recalc)(struct clk *clk);
17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
18 int (*set_parent)(struct clk *clk, struct clk *parent);
19 long (*round_rate)(struct clk *clk, unsigned long rate);
20};
21
22struct clk {
23 struct list_head node;
24 const char *name;
25 int id;
26
27 struct clk *parent;
28 struct clk_ops *ops;
29
30 struct list_head children;
31 struct list_head sibling; /* node for children */
32
33 int usecount;
34
35 unsigned long rate;
36 unsigned long flags;
37
38 void __iomem *enable_reg;
39 unsigned int enable_bit;
40
41 unsigned long arch_flags;
42 void *priv;
43 struct dentry *dentry;
44 struct cpufreq_frequency_table *freq_table;
45};
46
47#define CLK_ENABLE_ON_INIT (1 << 0)
48
49/* arch/sh/kernel/cpu/clock.c */
50int clk_init(void);
51unsigned long followparent_recalc(struct clk *);
52void recalculate_root_clocks(void);
53void propagate_rate(struct clk *);
54int clk_reparent(struct clk *child, struct clk *parent);
55int clk_register(struct clk *);
56void clk_unregister(struct clk *);
57
58/* the exported API, in addition to clk_set_rate */
59/**
60 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
61 * @clk: clock source
62 * @rate: desired clock rate in Hz
63 * @algo_id: algorithm id to be passed down to ops->set_rate
64 *
65 * Returns success (0) or negative errno.
66 */
67int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
68
69enum clk_sh_algo_id {
70 NO_CHANGE = 0,
71
72 IUS_N1_N1,
73 IUS_322,
74 IUS_522,
75 IUS_N11,
76
77 SB_N1,
78
79 SB3_N1,
80 SB3_32,
81 SB3_43,
82 SB3_54,
83
84 BP_N1,
85
86 IP_N1,
87};
88
89struct clk_div_mult_table {
90 unsigned int *divisors;
91 unsigned int nr_divisors;
92 unsigned int *multipliers;
93 unsigned int nr_multipliers;
94};
95
96struct cpufreq_frequency_table;
97void clk_rate_table_build(struct clk *clk,
98 struct cpufreq_frequency_table *freq_table,
99 int nr_freqs,
100 struct clk_div_mult_table *src_table,
101 unsigned long *bitmap);
102
103long clk_rate_table_round(struct clk *clk,
104 struct cpufreq_frequency_table *freq_table,
105 unsigned long rate);
106
107int clk_rate_table_find(struct clk *clk,
108 struct cpufreq_frequency_table *freq_table,
109 unsigned long rate);
110
111#define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
112{ \
113 .parent = _parent, \
114 .enable_reg = (void __iomem *)_enable_reg, \
115 .enable_bit = _enable_bit, \
116 .flags = _flags, \
117}
118
119int sh_clk_mstp32_register(struct clk *clks, int nr);
120
121#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
122{ \
123 .parent = _parent, \
124 .enable_reg = (void __iomem *)_reg, \
125 .enable_bit = _shift, \
126 .arch_flags = _div_bitmap, \
127 .flags = _flags, \
128}
129
130struct clk_div4_table {
131 struct clk_div_mult_table *div_mult_table;
132 void (*kick)(struct clk *clk);
133};
134
135int sh_clk_div4_register(struct clk *clks, int nr,
136 struct clk_div4_table *table);
137int sh_clk_div4_enable_register(struct clk *clks, int nr,
138 struct clk_div4_table *table);
139int sh_clk_div4_reparent_register(struct clk *clks, int nr,
140 struct clk_div4_table *table);
141
142#define SH_CLK_DIV6(_parent, _reg, _flags) \
143{ \
144 .parent = _parent, \
145 .enable_reg = (void __iomem *)_reg, \
146 .flags = _flags, \
147}
148
149int sh_clk_div6_register(struct clk *clks, int nr);
150
151#endif /* __SH_CLOCK_H */
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