diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-03-27 17:42:13 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-05-06 18:20:51 -0400 |
commit | b7d41d6d580743b1fed1b9560d948c9ef58564bd (patch) | |
tree | a16260415dcd3b1cc476f84e8f283f68e321ba2d | |
parent | 6f550dc08369ee0bc6402963c377e65f0f2e3b71 (diff) |
V4L/DVB: mx1-camera: compile fix
This fixes a regression of
7d58289 (mx1: prefix SOC specific defines with MX1_ and deprecate old names)
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r-- | arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | 8 | ||||
-rw-r--r-- | drivers/media/video/mx1_camera.c | 8 |
2 files changed, 10 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h index 07be8ad7ec37..7c4870bd5a21 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | |||
@@ -31,7 +31,13 @@ | |||
31 | #define DMA_MODE_WRITE 1 | 31 | #define DMA_MODE_WRITE 1 |
32 | #define DMA_MODE_MASK 1 | 32 | #define DMA_MODE_MASK 1 |
33 | 33 | ||
34 | #define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR) | 34 | #define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset)) |
35 | |||
36 | /* DMA Interrupt Mask Register */ | ||
37 | #define MX1_DMA_DIMR MX1_DMA_REG(0x08) | ||
38 | |||
39 | /* Channel Control Register */ | ||
40 | #define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6)) | ||
35 | 41 | ||
36 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | 42 | #define IMX_DMA_MEMSIZE_32 (0 << 4) |
37 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | 43 | #define IMX_DMA_MEMSIZE_8 (1 << 4) |
diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c index 3c8ebfcb742e..34a66019190e 100644 --- a/drivers/media/video/mx1_camera.c +++ b/drivers/media/video/mx1_camera.c | |||
@@ -49,8 +49,6 @@ | |||
49 | /* | 49 | /* |
50 | * CSI registers | 50 | * CSI registers |
51 | */ | 51 | */ |
52 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | ||
53 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | ||
54 | #define CSICR1 0x00 /* CSI Control Register 1 */ | 52 | #define CSICR1 0x00 /* CSI Control Register 1 */ |
55 | #define CSISR 0x08 /* CSI Status Register */ | 53 | #define CSISR 0x08 /* CSI Status Register */ |
56 | #define CSIRXR 0x10 /* CSI RxFIFO Register */ | 54 | #define CSIRXR 0x10 /* CSI RxFIFO Register */ |
@@ -784,7 +782,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev) | |||
784 | pcdev); | 782 | pcdev); |
785 | 783 | ||
786 | imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO, | 784 | imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO, |
787 | IMX_DMA_MEMSIZE_32, DMA_REQ_CSI_R, 0); | 785 | IMX_DMA_MEMSIZE_32, MX1_DMA_REQ_CSI_R, 0); |
788 | /* burst length : 16 words = 64 bytes */ | 786 | /* burst length : 16 words = 64 bytes */ |
789 | imx_dma_config_burstlen(pcdev->dma_chan, 0); | 787 | imx_dma_config_burstlen(pcdev->dma_chan, 0); |
790 | 788 | ||
@@ -798,8 +796,8 @@ static int __init mx1_camera_probe(struct platform_device *pdev) | |||
798 | set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end - | 796 | set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end - |
799 | &mx1_camera_sof_fiq_start); | 797 | &mx1_camera_sof_fiq_start); |
800 | 798 | ||
801 | regs.ARM_r8 = DMA_BASE + DMA_DIMR; | 799 | regs.ARM_r8 = (long)MX1_DMA_DIMR; |
802 | regs.ARM_r9 = DMA_BASE + DMA_CCR(pcdev->dma_chan); | 800 | regs.ARM_r9 = (long)MX1_DMA_CCR(pcdev->dma_chan); |
803 | regs.ARM_r10 = (long)pcdev->base + CSICR1; | 801 | regs.ARM_r10 = (long)pcdev->base + CSICR1; |
804 | regs.ARM_fp = (long)pcdev->base + CSISR; | 802 | regs.ARM_fp = (long)pcdev->base + CSISR; |
805 | regs.ARM_sp = 1 << pcdev->dma_chan; | 803 | regs.ARM_sp = 1 << pcdev->dma_chan; |