diff options
author | Michael Chan <mchan@broadcom.com> | 2005-04-21 20:07:04 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2005-04-21 20:07:04 -0400 |
commit | 314fba348e1f64a30b53d3cff5d96872424e8498 (patch) | |
tree | 0f167465d14b4d8e6170097651eced60ab48be95 | |
parent | 7d0c41ef89dad9008edf1c3c0022721ebad39999 (diff) |
[TG3]: Setup proper GPIO settings
Setup proper GPIO settings in tp->grc_local_ctrl before calling
tg3_set_power() state in tg3_get_invariants() and after chip reset.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/tg3.c | 34 |
1 files changed, 28 insertions, 6 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index dd036c011c14..742340aebf7e 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -5336,10 +5336,23 @@ static int tg3_reset_hw(struct tg3 *tp) | |||
5336 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); | 5336 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
5337 | udelay(40); | 5337 | udelay(40); |
5338 | 5338 | ||
5339 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | 5339 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
5340 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | 5340 | * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the |
5341 | * register to preserve the GPIO settings for LOMs. The GPIOs, | ||
5342 | * whether used as inputs or outputs, are set by boot code after | ||
5343 | * reset. | ||
5344 | */ | ||
5345 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | ||
5346 | u32 gpio_mask; | ||
5347 | |||
5348 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 | | ||
5349 | GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2; | ||
5350 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; | ||
5351 | |||
5352 | /* GPIO1 must be driven high for eeprom write protect */ | ||
5341 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | 5353 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
5342 | GRC_LCLCTRL_GPIO_OUTPUT1); | 5354 | GRC_LCLCTRL_GPIO_OUTPUT1); |
5355 | } | ||
5343 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | 5356 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
5344 | udelay(100); | 5357 | udelay(100); |
5345 | 5358 | ||
@@ -7430,8 +7443,8 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |||
7430 | } | 7443 | } |
7431 | 7444 | ||
7432 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | 7445 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
7433 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | 7446 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
7434 | GRC_LCLCTRL_GPIO_OE1); | 7447 | ~GRC_LCLCTRL_GPIO_OUTPUT1); |
7435 | udelay(40); | 7448 | udelay(40); |
7436 | } | 7449 | } |
7437 | 7450 | ||
@@ -7477,8 +7490,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |||
7477 | } | 7490 | } |
7478 | 7491 | ||
7479 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | 7492 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
7480 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | 7493 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
7481 | GRC_LCLCTRL_GPIO_OE1 | GRC_LCLCTRL_GPIO_OUTPUT1); | ||
7482 | udelay(40); | 7494 | udelay(40); |
7483 | } | 7495 | } |
7484 | 7496 | ||
@@ -8045,6 +8057,16 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
8045 | */ | 8057 | */ |
8046 | tg3_get_eeprom_hw_cfg(tp); | 8058 | tg3_get_eeprom_hw_cfg(tp); |
8047 | 8059 | ||
8060 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). | ||
8061 | * GPIO1 driven high will bring 5700's external PHY out of reset. | ||
8062 | * It is also used as eeprom write protect on LOMs. | ||
8063 | */ | ||
8064 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | ||
8065 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | ||
8066 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | ||
8067 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | ||
8068 | GRC_LCLCTRL_GPIO_OUTPUT1); | ||
8069 | |||
8048 | /* Force the chip into D0. */ | 8070 | /* Force the chip into D0. */ |
8049 | err = tg3_set_power_state(tp, 0); | 8071 | err = tg3_set_power_state(tp, 0); |
8050 | if (err) { | 8072 | if (err) { |