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authorAlexander Duyck <alexander.h.duyck@intel.com>2012-06-22 02:46:33 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2012-07-17 21:56:50 -0400
commit4ae63730bb420610cb99ed152d6daa35236cc9e9 (patch)
treee99f652b8840d68ca9b0499c8cffd2ad0d7ad1fe
parentac802f5dfe56139a288df50c89c820412863cd8a (diff)
ixgbe: Update the logic for ixgbe_cache_ring_dcb and DCB RSS configuration
This change cleans up some of the logic in an attempt to try and simplify things for how we are configuring DCB w/ RSS. In this patch I basically did 3 things. I updated the logic for getting the first register index. I applied the fact that all TCs get the same number of queues to simplify the looping logic in caching the DCB ring register. Finally I updated how we configure the RQTC register to match the fact that all TCs are assigned the same number of queues. Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c80
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_main.c12
2 files changed, 42 insertions, 50 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
index c03d771c5eb9..4c3822f04bb9 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
@@ -42,42 +42,37 @@ static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
42 42
43 switch (hw->mac.type) { 43 switch (hw->mac.type) {
44 case ixgbe_mac_82598EB: 44 case ixgbe_mac_82598EB:
45 *tx = tc << 2; 45 /* TxQs/TC: 4 RxQs/TC: 8 */
46 *rx = tc << 3; 46 *tx = tc << 2; /* 0, 4, 8, 12, 16, 20, 24, 28 */
47 *rx = tc << 3; /* 0, 8, 16, 24, 32, 40, 48, 56 */
47 break; 48 break;
48 case ixgbe_mac_82599EB: 49 case ixgbe_mac_82599EB:
49 case ixgbe_mac_X540: 50 case ixgbe_mac_X540:
50 if (num_tcs > 4) { 51 if (num_tcs > 4) {
51 if (tc < 3) { 52 /*
52 *tx = tc << 5; 53 * TCs : TC0/1 TC2/3 TC4-7
53 *rx = tc << 4; 54 * TxQs/TC: 32 16 8
54 } else if (tc < 5) { 55 * RxQs/TC: 16 16 16
55 *tx = ((tc + 2) << 4); 56 */
56 *rx = tc << 4; 57 *rx = tc << 4;
57 } else if (tc < num_tcs) { 58 if (tc < 3)
58 *tx = ((tc + 8) << 3); 59 *tx = tc << 5; /* 0, 32, 64 */
59 *rx = tc << 4; 60 else if (tc < 5)
60 } 61 *tx = (tc + 2) << 4; /* 80, 96 */
62 else
63 *tx = (tc + 8) << 3; /* 104, 112, 120 */
61 } else { 64 } else {
62 *rx = tc << 5; 65 /*
63 switch (tc) { 66 * TCs : TC0 TC1 TC2/3
64 case 0: 67 * TxQs/TC: 64 32 16
65 *tx = 0; 68 * RxQs/TC: 32 32 32
66 break; 69 */
67 case 1: 70 *rx = tc << 5;
68 *tx = 64; 71 if (tc < 2)
69 break; 72 *tx = tc << 6; /* 0, 64 */
70 case 2: 73 else
71 *tx = 96; 74 *tx = (tc + 4) << 4; /* 96, 112 */
72 break;
73 case 3:
74 *tx = 112;
75 break;
76 default:
77 break;
78 }
79 } 75 }
80 break;
81 default: 76 default:
82 break; 77 break;
83 } 78 }
@@ -90,25 +85,26 @@ static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
90 * Cache the descriptor ring offsets for DCB to the assigned rings. 85 * Cache the descriptor ring offsets for DCB to the assigned rings.
91 * 86 *
92 **/ 87 **/
93static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) 88static bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
94{ 89{
95 struct net_device *dev = adapter->netdev; 90 struct net_device *dev = adapter->netdev;
96 int i, j, k; 91 unsigned int tx_idx, rx_idx;
92 int tc, offset, rss_i, i;
97 u8 num_tcs = netdev_get_num_tc(dev); 93 u8 num_tcs = netdev_get_num_tc(dev);
98 94
99 if (!num_tcs) 95 /* verify we have DCB queueing enabled before proceeding */
96 if (num_tcs <= 1)
100 return false; 97 return false;
101 98
102 for (i = 0, k = 0; i < num_tcs; i++) { 99 rss_i = adapter->ring_feature[RING_F_RSS].indices;
103 unsigned int tx_s, rx_s;
104 u16 count = dev->tc_to_txq[i].count;
105 100
106 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); 101 for (tc = 0, offset = 0; tc < num_tcs; tc++, offset += rss_i) {
107 for (j = 0; j < count; j++, k++) { 102 ixgbe_get_first_reg_idx(adapter, tc, &tx_idx, &rx_idx);
108 adapter->tx_ring[k]->reg_idx = tx_s + j; 103 for (i = 0; i < rss_i; i++, tx_idx++, rx_idx++) {
109 adapter->rx_ring[k]->reg_idx = rx_s + j; 104 adapter->tx_ring[offset + i]->reg_idx = tx_idx;
110 adapter->tx_ring[k]->dcb_tc = i; 105 adapter->rx_ring[offset + i]->reg_idx = rx_idx;
111 adapter->rx_ring[k]->dcb_tc = i; 106 adapter->tx_ring[offset + i]->dcb_tc = tc;
107 adapter->rx_ring[offset + i]->dcb_tc = tc;
112 } 108 }
113 } 109 }
114 110
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 7f2aa220501e..32c8cd649cb0 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -3608,20 +3608,16 @@ static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3608 3608
3609 /* Enable RSS Hash per TC */ 3609 /* Enable RSS Hash per TC */
3610 if (hw->mac.type != ixgbe_mac_82598EB) { 3610 if (hw->mac.type != ixgbe_mac_82598EB) {
3611 int i; 3611 u32 msb = 0;
3612 u32 reg = 0; 3612 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3613 u8 msb = 0;
3614 u8 rss_i = adapter->netdev->tc_to_txq[0].count - 1;
3615 3613
3616 while (rss_i) { 3614 while (rss_i) {
3617 msb++; 3615 msb++;
3618 rss_i >>= 1; 3616 rss_i >>= 1;
3619 } 3617 }
3620 3618
3621 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 3619 /* write msb to all 8 TCs in one write */
3622 reg |= msb << IXGBE_RQTC_SHIFT_TC(i); 3620 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3623
3624 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3625 } 3621 }
3626} 3622}
3627#endif 3623#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-13 22:21:53 -0400