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authorLinus Torvalds <torvalds@linux-foundation.org>2011-08-01 12:13:48 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-08-01 12:13:48 -0400
commit4a2d732f5d1a2adf38a5baaa2f27094024be65e9 (patch)
treefbc8e050fb8f8d66fbb676746888080841882def
parent965e32b18d6b6bbcb79f4a7308fc8bdb4d03e813 (diff)
parent867f503d580eafbcc342141bae53cf6a27d413b1 (diff)
Merge branch 'gpio/next' of git://git.secretlab.ca/git/linux-2.6
* 'gpio/next' of git://git.secretlab.ca/git/linux-2.6: gpio_msm: Move Qualcomm MSM v2 gpio driver into drivers gpio_msm: Move Qualcomm v6 MSM driver into drivers msm: gpio: Fold register defs into C file msm: gpiomux: Move public API to public header msm: gpio: Remove ifdefs on gpio chip registers msm: gpio: Remove chip-specific register definitions msm: Remove chip-ifdefs for GPIO io mappings msm: gpio: Remove unsupported devices gpio: ab8500: fix MODULE_ALIAS for ab8500 of/gpio: export of_gpio_simple_xlate
Diffstat
-rw-r--r--arch/arm/mach-msm/Kconfig4
-rw-r--r--arch/arm/mach-msm/Makefile8
-rw-r--r--arch/arm/mach-msm/gpio.c376
-rw-r--r--arch/arm/mach-msm/gpio_hw.h278
-rw-r--r--arch/arm/mach-msm/gpiomux.h17
-rw-r--r--arch/arm/mach-msm/include/mach/msm_gpiomux.h38
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x00.h10
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x30.h10
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h10
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h2
-rw-r--r--arch/arm/mach-msm/io.c12
-rw-r--r--drivers/gpio/Kconfig16
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/gpio-ab8500.c2
-rw-r--r--drivers/gpio/gpio-msm-v1.c636
-rw-r--r--drivers/gpio/gpio-msm-v2.c (renamed from arch/arm/mach-msm/gpio-v2.c)4
-rw-r--r--drivers/of/gpio.c5
-rw-r--r--include/linux/of_gpio.h9
18 files changed, 732 insertions, 707 deletions
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 888e92502e15..ebde97f5d5f0 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -11,6 +11,7 @@ config ARCH_MSM7X00A
11 select MSM_SMD 11 select MSM_SMD
12 select MSM_SMD_PKG3 12 select MSM_SMD_PKG3
13 select CPU_V6 13 select CPU_V6
14 select GPIO_MSM_V1
14 select MSM_PROC_COMM 15 select MSM_PROC_COMM
15 select HAS_MSM_DEBUG_UART_PHYS 16 select HAS_MSM_DEBUG_UART_PHYS
16 17
@@ -22,6 +23,7 @@ config ARCH_MSM7X30
22 select MSM_VIC 23 select MSM_VIC
23 select CPU_V7 24 select CPU_V7
24 select MSM_GPIOMUX 25 select MSM_GPIOMUX
26 select GPIO_MSM_V1
25 select MSM_PROC_COMM 27 select MSM_PROC_COMM
26 select HAS_MSM_DEBUG_UART_PHYS 28 select HAS_MSM_DEBUG_UART_PHYS
27 29
@@ -33,6 +35,7 @@ config ARCH_QSD8X50
33 select MSM_VIC 35 select MSM_VIC
34 select CPU_V7 36 select CPU_V7
35 select MSM_GPIOMUX 37 select MSM_GPIOMUX
38 select GPIO_MSM_V1
36 select MSM_PROC_COMM 39 select MSM_PROC_COMM
37 select HAS_MSM_DEBUG_UART_PHYS 40 select HAS_MSM_DEBUG_UART_PHYS
38 41
@@ -44,6 +47,7 @@ config ARCH_MSM8X60
44 select ARM_GIC 47 select ARM_GIC
45 select CPU_V7 48 select CPU_V7
46 select MSM_V2_TLMM 49 select MSM_V2_TLMM
50 select GPIO_MSM_V2
47 select MSM_GPIOMUX 51 select MSM_GPIOMUX
48 select MSM_SCM if SMP 52 select MSM_SCM if SMP
49 53
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index b70658c5ae00..4285dfd80b6f 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -29,11 +29,3 @@ obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o
29obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o 29obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
30obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o 30obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
31obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o 31obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
32ifdef CONFIG_MSM_V2_TLMM
33ifndef CONFIG_ARCH_MSM8960
34# TODO: TLMM Mapping issues need to be resolved
35obj-y += gpio-v2.o
36endif
37else
38obj-y += gpio.o
39endif
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
deleted file mode 100644
index 5ea273b00da8..000000000000
--- a/arch/arm/mach-msm/gpio.c
+++ /dev/null
@@ -1,376 +0,0 @@
1/* linux/arch/arm/mach-msm/gpio.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/bitops.h>
18#include <linux/gpio.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/module.h>
23#include "gpio_hw.h"
24#include "gpiomux.h"
25
26#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
27
28#define MSM_GPIO_BANK(bank, first, last) \
29 { \
30 .regs = { \
31 .out = MSM_GPIO_OUT_##bank, \
32 .in = MSM_GPIO_IN_##bank, \
33 .int_status = MSM_GPIO_INT_STATUS_##bank, \
34 .int_clear = MSM_GPIO_INT_CLEAR_##bank, \
35 .int_en = MSM_GPIO_INT_EN_##bank, \
36 .int_edge = MSM_GPIO_INT_EDGE_##bank, \
37 .int_pos = MSM_GPIO_INT_POS_##bank, \
38 .oe = MSM_GPIO_OE_##bank, \
39 }, \
40 .chip = { \
41 .base = (first), \
42 .ngpio = (last) - (first) + 1, \
43 .get = msm_gpio_get, \
44 .set = msm_gpio_set, \
45 .direction_input = msm_gpio_direction_input, \
46 .direction_output = msm_gpio_direction_output, \
47 .to_irq = msm_gpio_to_irq, \
48 .request = msm_gpio_request, \
49 .free = msm_gpio_free, \
50 } \
51 }
52
53#define MSM_GPIO_BROKEN_INT_CLEAR 1
54
55struct msm_gpio_regs {
56 void __iomem *out;
57 void __iomem *in;
58 void __iomem *int_status;
59 void __iomem *int_clear;
60 void __iomem *int_en;
61 void __iomem *int_edge;
62 void __iomem *int_pos;
63 void __iomem *oe;
64};
65
66struct msm_gpio_chip {
67 spinlock_t lock;
68 struct gpio_chip chip;
69 struct msm_gpio_regs regs;
70#if MSM_GPIO_BROKEN_INT_CLEAR
71 unsigned int_status_copy;
72#endif
73 unsigned int both_edge_detect;
74 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
75};
76
77static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
78 unsigned offset, unsigned on)
79{
80 unsigned mask = BIT(offset);
81 unsigned val;
82
83 val = readl(msm_chip->regs.out);
84 if (on)
85 writel(val | mask, msm_chip->regs.out);
86 else
87 writel(val & ~mask, msm_chip->regs.out);
88 return 0;
89}
90
91static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
92{
93 int loop_limit = 100;
94 unsigned pol, val, val2, intstat;
95 do {
96 val = readl(msm_chip->regs.in);
97 pol = readl(msm_chip->regs.int_pos);
98 pol = (pol & ~msm_chip->both_edge_detect) |
99 (~val & msm_chip->both_edge_detect);
100 writel(pol, msm_chip->regs.int_pos);
101 intstat = readl(msm_chip->regs.int_status);
102 val2 = readl(msm_chip->regs.in);
103 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
104 return;
105 } while (loop_limit-- > 0);
106 printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
107 "failed to reach stable state %x != %x\n", val, val2);
108}
109
110static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
111 unsigned offset)
112{
113 unsigned bit = BIT(offset);
114
115#if MSM_GPIO_BROKEN_INT_CLEAR
116 /* Save interrupts that already triggered before we loose them. */
117 /* Any interrupt that triggers between the read of int_status */
118 /* and the write to int_clear will still be lost though. */
119 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
120 msm_chip->int_status_copy &= ~bit;
121#endif
122 writel(bit, msm_chip->regs.int_clear);
123 msm_gpio_update_both_edge_detect(msm_chip);
124 return 0;
125}
126
127static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
128{
129 struct msm_gpio_chip *msm_chip;
130 unsigned long irq_flags;
131
132 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
133 spin_lock_irqsave(&msm_chip->lock, irq_flags);
134 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
135 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
136 return 0;
137}
138
139static int
140msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
141{
142 struct msm_gpio_chip *msm_chip;
143 unsigned long irq_flags;
144
145 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
146 spin_lock_irqsave(&msm_chip->lock, irq_flags);
147 msm_gpio_write(msm_chip, offset, value);
148 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
149 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
150 return 0;
151}
152
153static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
154{
155 struct msm_gpio_chip *msm_chip;
156
157 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
158 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
159}
160
161static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
162{
163 struct msm_gpio_chip *msm_chip;
164 unsigned long irq_flags;
165
166 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
167 spin_lock_irqsave(&msm_chip->lock, irq_flags);
168 msm_gpio_write(msm_chip, offset, value);
169 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
170}
171
172static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
173{
174 return MSM_GPIO_TO_INT(chip->base + offset);
175}
176
177#ifdef CONFIG_MSM_GPIOMUX
178static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
179{
180 return msm_gpiomux_get(chip->base + offset);
181}
182
183static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
184{
185 msm_gpiomux_put(chip->base + offset);
186}
187#else
188#define msm_gpio_request NULL
189#define msm_gpio_free NULL
190#endif
191
192struct msm_gpio_chip msm_gpio_chips[] = {
193#if defined(CONFIG_ARCH_MSM7X00A)
194 MSM_GPIO_BANK(0, 0, 15),
195 MSM_GPIO_BANK(1, 16, 42),
196 MSM_GPIO_BANK(2, 43, 67),
197 MSM_GPIO_BANK(3, 68, 94),
198 MSM_GPIO_BANK(4, 95, 106),
199 MSM_GPIO_BANK(5, 107, 121),
200#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27)
201 MSM_GPIO_BANK(0, 0, 15),
202 MSM_GPIO_BANK(1, 16, 42),
203 MSM_GPIO_BANK(2, 43, 67),
204 MSM_GPIO_BANK(3, 68, 94),
205 MSM_GPIO_BANK(4, 95, 106),
206 MSM_GPIO_BANK(5, 107, 132),
207#elif defined(CONFIG_ARCH_MSM7X30)
208 MSM_GPIO_BANK(0, 0, 15),
209 MSM_GPIO_BANK(1, 16, 43),
210 MSM_GPIO_BANK(2, 44, 67),
211 MSM_GPIO_BANK(3, 68, 94),
212 MSM_GPIO_BANK(4, 95, 106),
213 MSM_GPIO_BANK(5, 107, 133),
214 MSM_GPIO_BANK(6, 134, 150),
215 MSM_GPIO_BANK(7, 151, 181),
216#elif defined(CONFIG_ARCH_QSD8X50)
217 MSM_GPIO_BANK(0, 0, 15),
218 MSM_GPIO_BANK(1, 16, 42),
219 MSM_GPIO_BANK(2, 43, 67),
220 MSM_GPIO_BANK(3, 68, 94),
221 MSM_GPIO_BANK(4, 95, 103),
222 MSM_GPIO_BANK(5, 104, 121),
223 MSM_GPIO_BANK(6, 122, 152),
224 MSM_GPIO_BANK(7, 153, 164),
225#endif
226};
227
228static void msm_gpio_irq_ack(struct irq_data *d)
229{
230 unsigned long irq_flags;
231 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
232 spin_lock_irqsave(&msm_chip->lock, irq_flags);
233 msm_gpio_clear_detect_status(msm_chip,
234 d->irq - gpio_to_irq(msm_chip->chip.base));
235 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
236}
237
238static void msm_gpio_irq_mask(struct irq_data *d)
239{
240 unsigned long irq_flags;
241 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
242 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
243
244 spin_lock_irqsave(&msm_chip->lock, irq_flags);
245 /* level triggered interrupts are also latched */
246 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
247 msm_gpio_clear_detect_status(msm_chip, offset);
248 msm_chip->int_enable[0] &= ~BIT(offset);
249 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
250 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
251}
252
253static void msm_gpio_irq_unmask(struct irq_data *d)
254{
255 unsigned long irq_flags;
256 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
257 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
258
259 spin_lock_irqsave(&msm_chip->lock, irq_flags);
260 /* level triggered interrupts are also latched */
261 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
262 msm_gpio_clear_detect_status(msm_chip, offset);
263 msm_chip->int_enable[0] |= BIT(offset);
264 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
265 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
266}
267
268static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
269{
270 unsigned long irq_flags;
271 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
272 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
273
274 spin_lock_irqsave(&msm_chip->lock, irq_flags);
275
276 if (on)
277 msm_chip->int_enable[1] |= BIT(offset);
278 else
279 msm_chip->int_enable[1] &= ~BIT(offset);
280
281 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
282 return 0;
283}
284
285static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
286{
287 unsigned long irq_flags;
288 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
289 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
290 unsigned val, mask = BIT(offset);
291
292 spin_lock_irqsave(&msm_chip->lock, irq_flags);
293 val = readl(msm_chip->regs.int_edge);
294 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
295 writel(val | mask, msm_chip->regs.int_edge);
296 __irq_set_handler_locked(d->irq, handle_edge_irq);
297 } else {
298 writel(val & ~mask, msm_chip->regs.int_edge);
299 __irq_set_handler_locked(d->irq, handle_level_irq);
300 }
301 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
302 msm_chip->both_edge_detect |= mask;
303 msm_gpio_update_both_edge_detect(msm_chip);
304 } else {
305 msm_chip->both_edge_detect &= ~mask;
306 val = readl(msm_chip->regs.int_pos);
307 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
308 writel(val | mask, msm_chip->regs.int_pos);
309 else
310 writel(val & ~mask, msm_chip->regs.int_pos);
311 }
312 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
313 return 0;
314}
315
316static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
317{
318 int i, j, mask;
319 unsigned val;
320
321 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
322 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
323 val = readl(msm_chip->regs.int_status);
324 val &= msm_chip->int_enable[0];
325 while (val) {
326 mask = val & -val;
327 j = fls(mask) - 1;
328 /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
329 __func__, v, m, j, msm_chip->chip.start + j,
330 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
331 val &= ~mask;
332 generic_handle_irq(FIRST_GPIO_IRQ +
333 msm_chip->chip.base + j);
334 }
335 }
336 desc->irq_data.chip->irq_ack(&desc->irq_data);
337}
338
339static struct irq_chip msm_gpio_irq_chip = {
340 .name = "msmgpio",
341 .irq_ack = msm_gpio_irq_ack,
342 .irq_mask = msm_gpio_irq_mask,
343 .irq_unmask = msm_gpio_irq_unmask,
344 .irq_set_wake = msm_gpio_irq_set_wake,
345 .irq_set_type = msm_gpio_irq_set_type,
346};
347
348static int __init msm_init_gpio(void)
349{
350 int i, j = 0;
351
352 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
353 if (i - FIRST_GPIO_IRQ >=
354 msm_gpio_chips[j].chip.base +
355 msm_gpio_chips[j].chip.ngpio)
356 j++;
357 irq_set_chip_data(i, &msm_gpio_chips[j]);
358 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
359 handle_edge_irq);
360 set_irq_flags(i, IRQF_VALID);
361 }
362
363 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
364 spin_lock_init(&msm_gpio_chips[i].lock);
365 writel(0, msm_gpio_chips[i].regs.int_en);
366 gpiochip_add(&msm_gpio_chips[i].chip);
367 }
368
369 irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
370 irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
371 irq_set_irq_wake(INT_GPIO_GROUP1, 1);
372 irq_set_irq_wake(INT_GPIO_GROUP2, 2);
373 return 0;
374}
375
376postcore_initcall(msm_init_gpio);
diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h
deleted file mode 100644
index 6b5066038baa..000000000000
--- a/arch/arm/mach-msm/gpio_hw.h
+++ /dev/null
@@ -1,278 +0,0 @@
1/* arch/arm/mach-msm/gpio_hw.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
19#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
20
21#include <mach/msm_iomap.h>
22
23/* see 80-VA736-2 Rev C pp 695-751
24**
25** These are actually the *shadow* gpio registers, since the
26** real ones (which allow full access) are only available to the
27** ARM9 side of the world.
28**
29** Since the _BASE need to be page-aligned when we're mapping them
30** to virtual addresses, adjust for the additional offset in these
31** macros.
32*/
33
34#if defined(CONFIG_ARCH_MSM7X30)
35#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
36#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
37#else
38#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
39#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
40#endif
41
42#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
43 defined(CONFIG_ARCH_MSM7X27)
44
45/* output value */
46#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
47#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
48#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
49#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
50#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
51#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */
52
53/* same pin map as above, output enable */
54#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
55#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
56#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
57#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
58#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
59#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
60
61/* same pin map as above, input read */
62#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
63#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
64#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
65#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
66#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
67#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
68
69/* same pin map as above, 1=edge 0=level interrup */
70#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
71#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
72#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
73#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
74#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
75#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
76
77/* same pin map as above, 1=positive 0=negative */
78#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
79#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
80#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
81#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
82#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
83#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
84
85/* same pin map as above, interrupt enable */
86#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
87#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
88#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
89#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
90#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
91#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
92
93/* same pin map as above, write 1 to clear interrupt */
94#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
95#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
96#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
97#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
98#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
99#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
100
101/* same pin map as above, 1=interrupt pending */
102#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
103#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
104#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
105#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
106#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
107#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
108
109#endif
110
111#if defined(CONFIG_ARCH_QSD8X50)
112/* output value */
113#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
114#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
115#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
116#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
117#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */
118#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */
119#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */
120#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */
121
122/* same pin map as above, output enable */
123#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20)
124#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
125#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24)
126#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28)
127#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C)
128#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30)
129#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34)
130#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38)
131
132/* same pin map as above, input read */
133#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50)
134#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
135#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54)
136#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58)
137#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C)
138#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60)
139#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64)
140#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68)
141
142/* same pin map as above, 1=edge 0=level interrup */
143#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70)
144#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
145#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74)
146#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78)
147#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C)
148#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80)
149#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84)
150#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88)
151
152/* same pin map as above, 1=positive 0=negative */
153#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90)
154#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
155#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94)
156#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98)
157#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C)
158#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0)
159#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4)
160#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8)
161
162/* same pin map as above, interrupt enable */
163#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0)
164#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
165#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4)
166#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8)
167#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC)
168#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0)
169#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4)
170#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8)
171
172/* same pin map as above, write 1 to clear interrupt */
173#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0)
174#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
175#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4)
176#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8)
177#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC)
178#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0)
179#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4)
180#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8)
181
182/* same pin map as above, 1=interrupt pending */
183#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0)
184#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
185#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4)
186#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8)
187#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC)
188#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100)
189#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104)
190#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108)
191
192#endif
193
194#if defined(CONFIG_ARCH_MSM7X30)
195
196/* output value */
197#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
198#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
199#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
200#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
201#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
202#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
203#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
204#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
205
206/* same pin map as above, output enable */
207#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
208#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
209#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
210#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
211#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
212#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
213#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
214#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218)
215
216/* same pin map as above, input read */
217#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
218#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
219#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
220#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
221#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
222#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
223#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
224#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
225
226/* same pin map as above, 1=edge 0=level interrup */
227#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
228#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
229#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
230#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
231#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
232#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
233#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
234#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
235
236/* same pin map as above, 1=positive 0=negative */
237#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
238#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
239#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
240#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
241#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
242#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
243#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
244#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
245
246/* same pin map as above, interrupt enable */
247#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
248#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
249#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
250#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
251#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
252#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
253#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
254#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
255
256/* same pin map as above, write 1 to clear interrupt */
257#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
258#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
259#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
260#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
261#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
262#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
263#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
264#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
265
266/* same pin map as above, 1=interrupt pending */
267#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
268#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
269#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
270#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
271#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
272#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
273#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
274#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
275
276#endif
277
278#endif
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h
index b178d9cb742f..00459f6ee13c 100644
--- a/arch/arm/mach-msm/gpiomux.h
+++ b/arch/arm/mach-msm/gpiomux.h
@@ -19,6 +19,7 @@
19 19
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21#include <linux/errno.h> 21#include <linux/errno.h>
22#include <mach/msm_gpiomux.h>
22 23
23#if defined(CONFIG_MSM_V2_TLMM) 24#if defined(CONFIG_MSM_V2_TLMM)
24#include "gpiomux-v2.h" 25#include "gpiomux-v2.h"
@@ -71,12 +72,6 @@ enum {
71 */ 72 */
72extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS]; 73extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
73 74
74/* Increment a gpio's reference count, possibly activating the line. */
75int __must_check msm_gpiomux_get(unsigned gpio);
76
77/* Decrement a gpio's reference count, possibly suspending the line. */
78int msm_gpiomux_put(unsigned gpio);
79
80/* Install a new configuration to the gpio line. To avoid overwriting 75/* Install a new configuration to the gpio line. To avoid overwriting
81 * a configuration, leave the VALID bit out. 76 * a configuration, leave the VALID bit out.
82 */ 77 */
@@ -94,16 +89,6 @@ int msm_gpiomux_write(unsigned gpio,
94 */ 89 */
95void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val); 90void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val);
96#else 91#else
97static inline int __must_check msm_gpiomux_get(unsigned gpio)
98{
99 return -ENOSYS;
100}
101
102static inline int msm_gpiomux_put(unsigned gpio)
103{
104 return -ENOSYS;
105}
106
107static inline int msm_gpiomux_write(unsigned gpio, 92static inline int msm_gpiomux_write(unsigned gpio,
108 gpiomux_config_t active, 93 gpiomux_config_t active,
109 gpiomux_config_t suspended) 94 gpiomux_config_t suspended)
diff --git a/arch/arm/mach-msm/include/mach/msm_gpiomux.h b/arch/arm/mach-msm/include/mach/msm_gpiomux.h
new file mode 100644
index 000000000000..0c7d3936e02f
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_gpiomux.h
@@ -0,0 +1,38 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _LINUX_MSM_GPIOMUX_H
14#define _LINUX_MSM_GPIOMUX_H
15
16#ifdef CONFIG_MSM_GPIOMUX
17
18/* Increment a gpio's reference count, possibly activating the line. */
19int __must_check msm_gpiomux_get(unsigned gpio);
20
21/* Decrement a gpio's reference count, possibly suspending the line. */
22int msm_gpiomux_put(unsigned gpio);
23
24#else
25
26static inline int __must_check msm_gpiomux_get(unsigned gpio)
27{
28 return -ENOSYS;
29}
30
31static inline int msm_gpiomux_put(unsigned gpio)
32{
33 return -ENOSYS;
34}
35
36#endif
37
38#endif /* _LINUX_MSM_GPIOMUX_H */
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 8f99d97615a0..94fe9fe6feb3 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -55,13 +55,11 @@
55#define MSM_DMOV_PHYS 0xA9700000 55#define MSM_DMOV_PHYS 0xA9700000
56#define MSM_DMOV_SIZE SZ_4K 56#define MSM_DMOV_SIZE SZ_4K
57 57
58#define MSM_GPIO1_BASE IOMEM(0xE0003000) 58#define MSM7X00_GPIO1_PHYS 0xA9200000
59#define MSM_GPIO1_PHYS 0xA9200000 59#define MSM7X00_GPIO1_SIZE SZ_4K
60#define MSM_GPIO1_SIZE SZ_4K
61 60
62#define MSM_GPIO2_BASE IOMEM(0xE0004000) 61#define MSM7X00_GPIO2_PHYS 0xA9300000
63#define MSM_GPIO2_PHYS 0xA9300000 62#define MSM7X00_GPIO2_SIZE SZ_4K
64#define MSM_GPIO2_SIZE SZ_4K
65 63
66#define MSM_CLK_CTL_BASE IOMEM(0xE0005000) 64#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
67#define MSM_CLK_CTL_PHYS 0xA8600000 65#define MSM_CLK_CTL_PHYS 0xA8600000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 4d84be15955e..37694442d1bd 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -46,13 +46,11 @@
46#define MSM_DMOV_PHYS 0xAC400000 46#define MSM_DMOV_PHYS 0xAC400000
47#define MSM_DMOV_SIZE SZ_4K 47#define MSM_DMOV_SIZE SZ_4K
48 48
49#define MSM_GPIO1_BASE IOMEM(0xE0003000) 49#define MSM7X30_GPIO1_PHYS 0xAC001000
50#define MSM_GPIO1_PHYS 0xAC001000 50#define MSM7X30_GPIO1_SIZE SZ_4K
51#define MSM_GPIO1_SIZE SZ_4K
52 51
53#define MSM_GPIO2_BASE IOMEM(0xE0004000) 52#define MSM7X30_GPIO2_PHYS 0xAC101000
54#define MSM_GPIO2_PHYS 0xAC101000 53#define MSM7X30_GPIO2_SIZE SZ_4K
55#define MSM_GPIO2_SIZE SZ_4K
56 54
57#define MSM_CLK_CTL_BASE IOMEM(0xE0005000) 55#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
58#define MSM_CLK_CTL_PHYS 0xAB800000 56#define MSM_CLK_CTL_PHYS 0xAB800000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index d4143201999f..d67cd73316f4 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -46,13 +46,11 @@
46#define MSM_DMOV_PHYS 0xA9700000 46#define MSM_DMOV_PHYS 0xA9700000
47#define MSM_DMOV_SIZE SZ_4K 47#define MSM_DMOV_SIZE SZ_4K
48 48
49#define MSM_GPIO1_BASE IOMEM(0xE0003000) 49#define QSD8X50_GPIO1_PHYS 0xA9000000
50#define MSM_GPIO1_PHYS 0xA9000000 50#define QSD8X50_GPIO1_SIZE SZ_4K
51#define MSM_GPIO1_SIZE SZ_4K
52 51
53#define MSM_GPIO2_BASE IOMEM(0xE0004000) 52#define QSD8X50_GPIO2_PHYS 0xA9100000
54#define MSM_GPIO2_PHYS 0xA9100000 53#define QSD8X50_GPIO2_SIZE SZ_4K
55#define MSM_GPIO2_SIZE SZ_4K
56 54
57#define MSM_CLK_CTL_BASE IOMEM(0xE0005000) 55#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
58#define MSM_CLK_CTL_PHYS 0xA8600000 56#define MSM_CLK_CTL_PHYS 0xA8600000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 2f494b6a9d0a..4ded15238b60 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -61,5 +61,7 @@
61#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) 61#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
62#define MSM_TMR_BASE IOMEM(0xF0200000) 62#define MSM_TMR_BASE IOMEM(0xF0200000)
63#define MSM_TMR0_BASE IOMEM(0xF0201000) 63#define MSM_TMR0_BASE IOMEM(0xF0201000)
64#define MSM_GPIO1_BASE IOMEM(0xE0003000)
65#define MSM_GPIO2_BASE IOMEM(0xE0004000)
64 66
65#endif 67#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index cec6ed1c91d3..140ddbbc3a8a 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -43,8 +43,8 @@ static struct map_desc msm_io_desc[] __initdata = {
43 MSM_DEVICE(VIC), 43 MSM_DEVICE(VIC),
44 MSM_CHIP_DEVICE(CSR, MSM7X00), 44 MSM_CHIP_DEVICE(CSR, MSM7X00),
45 MSM_DEVICE(DMOV), 45 MSM_DEVICE(DMOV),
46 MSM_DEVICE(GPIO1), 46 MSM_CHIP_DEVICE(GPIO1, MSM7X00),
47 MSM_DEVICE(GPIO2), 47 MSM_CHIP_DEVICE(GPIO2, MSM7X00),
48 MSM_DEVICE(CLK_CTL), 48 MSM_DEVICE(CLK_CTL),
49#ifdef CONFIG_MSM_DEBUG_UART 49#ifdef CONFIG_MSM_DEBUG_UART
50 MSM_DEVICE(DEBUG_UART), 50 MSM_DEVICE(DEBUG_UART),
@@ -76,8 +76,8 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
76 MSM_DEVICE(VIC), 76 MSM_DEVICE(VIC),
77 MSM_CHIP_DEVICE(CSR, QSD8X50), 77 MSM_CHIP_DEVICE(CSR, QSD8X50),
78 MSM_DEVICE(DMOV), 78 MSM_DEVICE(DMOV),
79 MSM_DEVICE(GPIO1), 79 MSM_CHIP_DEVICE(GPIO1, QSD8X50),
80 MSM_DEVICE(GPIO2), 80 MSM_CHIP_DEVICE(GPIO2, QSD8X50),
81 MSM_DEVICE(CLK_CTL), 81 MSM_DEVICE(CLK_CTL),
82 MSM_DEVICE(SIRC), 82 MSM_DEVICE(SIRC),
83 MSM_DEVICE(SCPLL), 83 MSM_DEVICE(SCPLL),
@@ -135,8 +135,8 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
135 MSM_DEVICE(VIC), 135 MSM_DEVICE(VIC),
136 MSM_CHIP_DEVICE(CSR, MSM7X30), 136 MSM_CHIP_DEVICE(CSR, MSM7X30),
137 MSM_DEVICE(DMOV), 137 MSM_DEVICE(DMOV),
138 MSM_DEVICE(GPIO1), 138 MSM_CHIP_DEVICE(GPIO1, MSM7X30),
139 MSM_DEVICE(GPIO2), 139 MSM_CHIP_DEVICE(GPIO2, MSM7X30),
140 MSM_DEVICE(CLK_CTL), 140 MSM_DEVICE(CLK_CTL),
141 MSM_DEVICE(CLK_CTL_SH2), 141 MSM_DEVICE(CLK_CTL_SH2),
142 MSM_DEVICE(AD5), 142 MSM_DEVICE(AD5),
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 6778f56a4c64..d539efd96d4b 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -103,6 +103,22 @@ config GPIO_MPC5200
103 def_bool y 103 def_bool y
104 depends on PPC_MPC52xx 104 depends on PPC_MPC52xx
105 105
106config GPIO_MSM_V1
107 tristate "Qualcomm MSM GPIO v1"
108 depends on GPIOLIB && ARCH_MSM
109 help
110 Say yes here to support the GPIO interface on ARM v6 based
111 Qualcomm MSM chips. Most of the pins on the MSM can be
112 selected for GPIO, and are controlled by this driver.
113
114config GPIO_MSM_V2
115 tristate "Qualcomm MSM GPIO v2"
116 depends on GPIOLIB && ARCH_MSM
117 help
118 Say yes here to support the GPIO interface on ARM v7 based
119 Qualcomm MSM chips. Most of the pins on the MSM can be
120 selected for GPIO, and are controlled by this driver.
121
106config GPIO_MXC 122config GPIO_MXC
107 def_bool y 123 def_bool y
108 depends on ARCH_MXC 124 depends on ARCH_MXC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4b81d4e1e709..9588948c96f0 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,8 @@ obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
27obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o 27obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o
28obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o 28obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
29obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o 29obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
30obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
31obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
30obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o 32obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
31obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o 33obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
32obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o 34obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
diff --git a/drivers/gpio/gpio-ab8500.c b/drivers/gpio/gpio-ab8500.c
index ed795e64eea7..050c05d91896 100644
--- a/drivers/gpio/gpio-ab8500.c
+++ b/drivers/gpio/gpio-ab8500.c
@@ -516,5 +516,5 @@ module_exit(ab8500_gpio_exit);
516 516
517MODULE_AUTHOR("BIBEK BASU <bibek.basu@stericsson.com>"); 517MODULE_AUTHOR("BIBEK BASU <bibek.basu@stericsson.com>");
518MODULE_DESCRIPTION("Driver allows to use AB8500 unused pins to be used as GPIO"); 518MODULE_DESCRIPTION("Driver allows to use AB8500 unused pins to be used as GPIO");
519MODULE_ALIAS("AB8500 GPIO driver"); 519MODULE_ALIAS("platform:ab8500-gpio");
520MODULE_LICENSE("GPL v2"); 520MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-msm-v1.c b/drivers/gpio/gpio-msm-v1.c
new file mode 100644
index 000000000000..52a4d4286eba
--- /dev/null
+++ b/drivers/gpio/gpio-msm-v1.c
@@ -0,0 +1,636 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/bitops.h>
17#include <linux/gpio.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22#include <mach/cpu.h>
23#include <mach/msm_gpiomux.h>
24#include <mach/msm_iomap.h>
25
26/* see 80-VA736-2 Rev C pp 695-751
27**
28** These are actually the *shadow* gpio registers, since the
29** real ones (which allow full access) are only available to the
30** ARM9 side of the world.
31**
32** Since the _BASE need to be page-aligned when we're mapping them
33** to virtual addresses, adjust for the additional offset in these
34** macros.
35*/
36
37#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
38#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
39#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
40#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
41
42/*
43 * MSM7X00 registers
44 */
45/* output value */
46#define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
47#define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
48#define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
49#define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
50#define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */
51#define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */
52
53/* same pin map as above, output enable */
54#define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10)
55#define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
56#define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14)
57#define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18)
58#define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C)
59#define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54)
60
61/* same pin map as above, input read */
62#define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34)
63#define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
64#define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38)
65#define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C)
66#define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40)
67#define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44)
68
69/* same pin map as above, 1=edge 0=level interrup */
70#define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60)
71#define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
72#define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64)
73#define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68)
74#define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C)
75#define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0)
76
77/* same pin map as above, 1=positive 0=negative */
78#define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70)
79#define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
80#define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74)
81#define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78)
82#define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C)
83#define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC)
84
85/* same pin map as above, interrupt enable */
86#define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80)
87#define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
88#define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84)
89#define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88)
90#define MSM7X00_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0x8C)
91#define MSM7X00_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xB8)
92
93/* same pin map as above, write 1 to clear interrupt */
94#define MSM7X00_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0x90)
95#define MSM7X00_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
96#define MSM7X00_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0x94)
97#define MSM7X00_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0x98)
98#define MSM7X00_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0x9C)
99#define MSM7X00_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xB4)
100
101/* same pin map as above, 1=interrupt pending */
102#define MSM7X00_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xA0)
103#define MSM7X00_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
104#define MSM7X00_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xA4)
105#define MSM7X00_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xA8)
106#define MSM7X00_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xAC)
107#define MSM7X00_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0xB0)
108
109/*
110 * QSD8X50 registers
111 */
112/* output value */
113#define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
114#define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
115#define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
116#define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
117#define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */
118#define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */
119#define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */
120#define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */
121
122/* same pin map as above, output enable */
123#define QSD8X50_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x20)
124#define QSD8X50_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
125#define QSD8X50_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x24)
126#define QSD8X50_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x28)
127#define QSD8X50_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x2C)
128#define QSD8X50_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x30)
129#define QSD8X50_GPIO_OE_6 MSM_GPIO1_SHADOW_REG(0x34)
130#define QSD8X50_GPIO_OE_7 MSM_GPIO1_SHADOW_REG(0x38)
131
132/* same pin map as above, input read */
133#define QSD8X50_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x50)
134#define QSD8X50_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
135#define QSD8X50_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x54)
136#define QSD8X50_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x58)
137#define QSD8X50_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x5C)
138#define QSD8X50_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x60)
139#define QSD8X50_GPIO_IN_6 MSM_GPIO1_SHADOW_REG(0x64)
140#define QSD8X50_GPIO_IN_7 MSM_GPIO1_SHADOW_REG(0x68)
141
142/* same pin map as above, 1=edge 0=level interrup */
143#define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70)
144#define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
145#define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74)
146#define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78)
147#define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C)
148#define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80)
149#define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84)
150#define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88)
151
152/* same pin map as above, 1=positive 0=negative */
153#define QSD8X50_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x90)
154#define QSD8X50_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
155#define QSD8X50_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x94)
156#define QSD8X50_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x98)
157#define QSD8X50_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x9C)
158#define QSD8X50_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xA0)
159#define QSD8X50_GPIO_INT_POS_6 MSM_GPIO1_SHADOW_REG(0xA4)
160#define QSD8X50_GPIO_INT_POS_7 MSM_GPIO1_SHADOW_REG(0xA8)
161
162/* same pin map as above, interrupt enable */
163#define QSD8X50_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0xB0)
164#define QSD8X50_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
165#define QSD8X50_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0xB4)
166#define QSD8X50_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0xB8)
167#define QSD8X50_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0xBC)
168#define QSD8X50_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xC0)
169#define QSD8X50_GPIO_INT_EN_6 MSM_GPIO1_SHADOW_REG(0xC4)
170#define QSD8X50_GPIO_INT_EN_7 MSM_GPIO1_SHADOW_REG(0xC8)
171
172/* same pin map as above, write 1 to clear interrupt */
173#define QSD8X50_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0xD0)
174#define QSD8X50_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
175#define QSD8X50_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0xD4)
176#define QSD8X50_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0xD8)
177#define QSD8X50_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0xDC)
178#define QSD8X50_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xE0)
179#define QSD8X50_GPIO_INT_CLEAR_6 MSM_GPIO1_SHADOW_REG(0xE4)
180#define QSD8X50_GPIO_INT_CLEAR_7 MSM_GPIO1_SHADOW_REG(0xE8)
181
182/* same pin map as above, 1=interrupt pending */
183#define QSD8X50_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xF0)
184#define QSD8X50_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
185#define QSD8X50_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xF4)
186#define QSD8X50_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xF8)
187#define QSD8X50_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xFC)
188#define QSD8X50_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0x100)
189#define QSD8X50_GPIO_INT_STATUS_6 MSM_GPIO1_SHADOW_REG(0x104)
190#define QSD8X50_GPIO_INT_STATUS_7 MSM_GPIO1_SHADOW_REG(0x108)
191
192/*
193 * MSM7X30 registers
194 */
195/* output value */
196#define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
197#define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
198#define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
199#define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
200#define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
201#define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
202#define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
203#define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
204
205/* same pin map as above, output enable */
206#define MSM7X30_GPIO_OE_0 MSM_GPIO1_REG(0x10)
207#define MSM7X30_GPIO_OE_1 MSM_GPIO2_REG(0x08)
208#define MSM7X30_GPIO_OE_2 MSM_GPIO1_REG(0x14)
209#define MSM7X30_GPIO_OE_3 MSM_GPIO1_REG(0x18)
210#define MSM7X30_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
211#define MSM7X30_GPIO_OE_5 MSM_GPIO1_REG(0x54)
212#define MSM7X30_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
213#define MSM7X30_GPIO_OE_7 MSM_GPIO1_REG(0x218)
214
215/* same pin map as above, input read */
216#define MSM7X30_GPIO_IN_0 MSM_GPIO1_REG(0x34)
217#define MSM7X30_GPIO_IN_1 MSM_GPIO2_REG(0x20)
218#define MSM7X30_GPIO_IN_2 MSM_GPIO1_REG(0x38)
219#define MSM7X30_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
220#define MSM7X30_GPIO_IN_4 MSM_GPIO1_REG(0x40)
221#define MSM7X30_GPIO_IN_5 MSM_GPIO1_REG(0x44)
222#define MSM7X30_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
223#define MSM7X30_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
224
225/* same pin map as above, 1=edge 0=level interrup */
226#define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
227#define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
228#define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
229#define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
230#define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
231#define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
232#define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
233#define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
234
235/* same pin map as above, 1=positive 0=negative */
236#define MSM7X30_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
237#define MSM7X30_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
238#define MSM7X30_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
239#define MSM7X30_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
240#define MSM7X30_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
241#define MSM7X30_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
242#define MSM7X30_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
243#define MSM7X30_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
244
245/* same pin map as above, interrupt enable */
246#define MSM7X30_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
247#define MSM7X30_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
248#define MSM7X30_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
249#define MSM7X30_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
250#define MSM7X30_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
251#define MSM7X30_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
252#define MSM7X30_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
253#define MSM7X30_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
254
255/* same pin map as above, write 1 to clear interrupt */
256#define MSM7X30_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
257#define MSM7X30_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
258#define MSM7X30_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
259#define MSM7X30_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
260#define MSM7X30_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
261#define MSM7X30_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
262#define MSM7X30_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
263#define MSM7X30_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
264
265/* same pin map as above, 1=interrupt pending */
266#define MSM7X30_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
267#define MSM7X30_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
268#define MSM7X30_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
269#define MSM7X30_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
270#define MSM7X30_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
271#define MSM7X30_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
272#define MSM7X30_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
273#define MSM7X30_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
274
275#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
276
277#define MSM_GPIO_BANK(soc, bank, first, last) \
278 { \
279 .regs = { \
280 .out = soc##_GPIO_OUT_##bank, \
281 .in = soc##_GPIO_IN_##bank, \
282 .int_status = soc##_GPIO_INT_STATUS_##bank, \
283 .int_clear = soc##_GPIO_INT_CLEAR_##bank, \
284 .int_en = soc##_GPIO_INT_EN_##bank, \
285 .int_edge = soc##_GPIO_INT_EDGE_##bank, \
286 .int_pos = soc##_GPIO_INT_POS_##bank, \
287 .oe = soc##_GPIO_OE_##bank, \
288 }, \
289 .chip = { \
290 .base = (first), \
291 .ngpio = (last) - (first) + 1, \
292 .get = msm_gpio_get, \
293 .set = msm_gpio_set, \
294 .direction_input = msm_gpio_direction_input, \
295 .direction_output = msm_gpio_direction_output, \
296 .to_irq = msm_gpio_to_irq, \
297 .request = msm_gpio_request, \
298 .free = msm_gpio_free, \
299 } \
300 }
301
302#define MSM_GPIO_BROKEN_INT_CLEAR 1
303
304struct msm_gpio_regs {
305 void __iomem *out;
306 void __iomem *in;
307 void __iomem *int_status;
308 void __iomem *int_clear;
309 void __iomem *int_en;
310 void __iomem *int_edge;
311 void __iomem *int_pos;
312 void __iomem *oe;
313};
314
315struct msm_gpio_chip {
316 spinlock_t lock;
317 struct gpio_chip chip;
318 struct msm_gpio_regs regs;
319#if MSM_GPIO_BROKEN_INT_CLEAR
320 unsigned int_status_copy;
321#endif
322 unsigned int both_edge_detect;
323 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
324};
325
326static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
327 unsigned offset, unsigned on)
328{
329 unsigned mask = BIT(offset);
330 unsigned val;
331
332 val = readl(msm_chip->regs.out);
333 if (on)
334 writel(val | mask, msm_chip->regs.out);
335 else
336 writel(val & ~mask, msm_chip->regs.out);
337 return 0;
338}
339
340static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
341{
342 int loop_limit = 100;
343 unsigned pol, val, val2, intstat;
344 do {
345 val = readl(msm_chip->regs.in);
346 pol = readl(msm_chip->regs.int_pos);
347 pol = (pol & ~msm_chip->both_edge_detect) |
348 (~val & msm_chip->both_edge_detect);
349 writel(pol, msm_chip->regs.int_pos);
350 intstat = readl(msm_chip->regs.int_status);
351 val2 = readl(msm_chip->regs.in);
352 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
353 return;
354 } while (loop_limit-- > 0);
355 printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
356 "failed to reach stable state %x != %x\n", val, val2);
357}
358
359static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
360 unsigned offset)
361{
362 unsigned bit = BIT(offset);
363
364#if MSM_GPIO_BROKEN_INT_CLEAR
365 /* Save interrupts that already triggered before we loose them. */
366 /* Any interrupt that triggers between the read of int_status */
367 /* and the write to int_clear will still be lost though. */
368 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
369 msm_chip->int_status_copy &= ~bit;
370#endif
371 writel(bit, msm_chip->regs.int_clear);
372 msm_gpio_update_both_edge_detect(msm_chip);
373 return 0;
374}
375
376static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
377{
378 struct msm_gpio_chip *msm_chip;
379 unsigned long irq_flags;
380
381 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
382 spin_lock_irqsave(&msm_chip->lock, irq_flags);
383 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
384 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
385 return 0;
386}
387
388static int
389msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
390{
391 struct msm_gpio_chip *msm_chip;
392 unsigned long irq_flags;
393
394 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
395 spin_lock_irqsave(&msm_chip->lock, irq_flags);
396 msm_gpio_write(msm_chip, offset, value);
397 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
398 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
399 return 0;
400}
401
402static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
403{
404 struct msm_gpio_chip *msm_chip;
405
406 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
407 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
408}
409
410static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
411{
412 struct msm_gpio_chip *msm_chip;
413 unsigned long irq_flags;
414
415 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
416 spin_lock_irqsave(&msm_chip->lock, irq_flags);
417 msm_gpio_write(msm_chip, offset, value);
418 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
419}
420
421static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
422{
423 return MSM_GPIO_TO_INT(chip->base + offset);
424}
425
426#ifdef CONFIG_MSM_GPIOMUX
427static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
428{
429 return msm_gpiomux_get(chip->base + offset);
430}
431
432static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
433{
434 msm_gpiomux_put(chip->base + offset);
435}
436#else
437#define msm_gpio_request NULL
438#define msm_gpio_free NULL
439#endif
440
441static struct msm_gpio_chip *msm_gpio_chips;
442static int msm_gpio_count;
443
444static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = {
445 MSM_GPIO_BANK(MSM7X00, 0, 0, 15),
446 MSM_GPIO_BANK(MSM7X00, 1, 16, 42),
447 MSM_GPIO_BANK(MSM7X00, 2, 43, 67),
448 MSM_GPIO_BANK(MSM7X00, 3, 68, 94),
449 MSM_GPIO_BANK(MSM7X00, 4, 95, 106),
450 MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
451};
452
453static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
454 MSM_GPIO_BANK(MSM7X30, 0, 0, 15),
455 MSM_GPIO_BANK(MSM7X30, 1, 16, 43),
456 MSM_GPIO_BANK(MSM7X30, 2, 44, 67),
457 MSM_GPIO_BANK(MSM7X30, 3, 68, 94),
458 MSM_GPIO_BANK(MSM7X30, 4, 95, 106),
459 MSM_GPIO_BANK(MSM7X30, 5, 107, 133),
460 MSM_GPIO_BANK(MSM7X30, 6, 134, 150),
461 MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
462};
463
464static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
465 MSM_GPIO_BANK(QSD8X50, 0, 0, 15),
466 MSM_GPIO_BANK(QSD8X50, 1, 16, 42),
467 MSM_GPIO_BANK(QSD8X50, 2, 43, 67),
468 MSM_GPIO_BANK(QSD8X50, 3, 68, 94),
469 MSM_GPIO_BANK(QSD8X50, 4, 95, 103),
470 MSM_GPIO_BANK(QSD8X50, 5, 104, 121),
471 MSM_GPIO_BANK(QSD8X50, 6, 122, 152),
472 MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
473};
474
475static void msm_gpio_irq_ack(struct irq_data *d)
476{
477 unsigned long irq_flags;
478 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
479 spin_lock_irqsave(&msm_chip->lock, irq_flags);
480 msm_gpio_clear_detect_status(msm_chip,
481 d->irq - gpio_to_irq(msm_chip->chip.base));
482 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
483}
484
485static void msm_gpio_irq_mask(struct irq_data *d)
486{
487 unsigned long irq_flags;
488 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
489 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
490
491 spin_lock_irqsave(&msm_chip->lock, irq_flags);
492 /* level triggered interrupts are also latched */
493 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
494 msm_gpio_clear_detect_status(msm_chip, offset);
495 msm_chip->int_enable[0] &= ~BIT(offset);
496 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
497 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
498}
499
500static void msm_gpio_irq_unmask(struct irq_data *d)
501{
502 unsigned long irq_flags;
503 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
504 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
505
506 spin_lock_irqsave(&msm_chip->lock, irq_flags);
507 /* level triggered interrupts are also latched */
508 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
509 msm_gpio_clear_detect_status(msm_chip, offset);
510 msm_chip->int_enable[0] |= BIT(offset);
511 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
512 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
513}
514
515static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
516{
517 unsigned long irq_flags;
518 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
519 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
520
521 spin_lock_irqsave(&msm_chip->lock, irq_flags);
522
523 if (on)
524 msm_chip->int_enable[1] |= BIT(offset);
525 else
526 msm_chip->int_enable[1] &= ~BIT(offset);
527
528 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
529 return 0;
530}
531
532static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
533{
534 unsigned long irq_flags;
535 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
536 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
537 unsigned val, mask = BIT(offset);
538
539 spin_lock_irqsave(&msm_chip->lock, irq_flags);
540 val = readl(msm_chip->regs.int_edge);
541 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
542 writel(val | mask, msm_chip->regs.int_edge);
543 __irq_set_handler_locked(d->irq, handle_edge_irq);
544 } else {
545 writel(val & ~mask, msm_chip->regs.int_edge);
546 __irq_set_handler_locked(d->irq, handle_level_irq);
547 }
548 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
549 msm_chip->both_edge_detect |= mask;
550 msm_gpio_update_both_edge_detect(msm_chip);
551 } else {
552 msm_chip->both_edge_detect &= ~mask;
553 val = readl(msm_chip->regs.int_pos);
554 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
555 writel(val | mask, msm_chip->regs.int_pos);
556 else
557 writel(val & ~mask, msm_chip->regs.int_pos);
558 }
559 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
560 return 0;
561}
562
563static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
564{
565 int i, j, mask;
566 unsigned val;
567
568 for (i = 0; i < msm_gpio_count; i++) {
569 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
570 val = readl(msm_chip->regs.int_status);
571 val &= msm_chip->int_enable[0];
572 while (val) {
573 mask = val & -val;
574 j = fls(mask) - 1;
575 /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
576 __func__, v, m, j, msm_chip->chip.start + j,
577 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
578 val &= ~mask;
579 generic_handle_irq(FIRST_GPIO_IRQ +
580 msm_chip->chip.base + j);
581 }
582 }
583 desc->irq_data.chip->irq_ack(&desc->irq_data);
584}
585
586static struct irq_chip msm_gpio_irq_chip = {
587 .name = "msmgpio",
588 .irq_ack = msm_gpio_irq_ack,
589 .irq_mask = msm_gpio_irq_mask,
590 .irq_unmask = msm_gpio_irq_unmask,
591 .irq_set_wake = msm_gpio_irq_set_wake,
592 .irq_set_type = msm_gpio_irq_set_type,
593};
594
595static int __init msm_init_gpio(void)
596{
597 int i, j = 0;
598
599 if (cpu_is_msm7x01()) {
600 msm_gpio_chips = msm_gpio_chips_msm7x01;
601 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x01);
602 } else if (cpu_is_msm7x30()) {
603 msm_gpio_chips = msm_gpio_chips_msm7x30;
604 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x30);
605 } else if (cpu_is_qsd8x50()) {
606 msm_gpio_chips = msm_gpio_chips_qsd8x50;
607 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_qsd8x50);
608 } else {
609 return 0;
610 }
611
612 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
613 if (i - FIRST_GPIO_IRQ >=
614 msm_gpio_chips[j].chip.base +
615 msm_gpio_chips[j].chip.ngpio)
616 j++;
617 irq_set_chip_data(i, &msm_gpio_chips[j]);
618 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
619 handle_edge_irq);
620 set_irq_flags(i, IRQF_VALID);
621 }
622
623 for (i = 0; i < msm_gpio_count; i++) {
624 spin_lock_init(&msm_gpio_chips[i].lock);
625 writel(0, msm_gpio_chips[i].regs.int_en);
626 gpiochip_add(&msm_gpio_chips[i].chip);
627 }
628
629 irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
630 irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
631 irq_set_irq_wake(INT_GPIO_GROUP1, 1);
632 irq_set_irq_wake(INT_GPIO_GROUP2, 2);
633 return 0;
634}
635
636postcore_initcall(msm_init_gpio);
diff --git a/arch/arm/mach-msm/gpio-v2.c b/drivers/gpio/gpio-msm-v2.c
index cc9c4fd7cccc..5cb1227d69cf 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/drivers/gpio/gpio-msm-v2.c
@@ -1,4 +1,4 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 4 * it under the terms of the GNU General Public License version 2 and
@@ -30,8 +30,8 @@
30 30
31#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
32 32
33#include <mach/msm_gpiomux.h>
33#include <mach/msm_iomap.h> 34#include <mach/msm_iomap.h>
34#include "gpiomux.h"
35 35
36/* Bits of interest in the GPIO_IN_OUT register. 36/* Bits of interest in the GPIO_IN_OUT register.
37 */ 37 */
diff --git a/drivers/of/gpio.c b/drivers/of/gpio.c
index 3007662ac614..ef0105fa52b1 100644
--- a/drivers/of/gpio.c
+++ b/drivers/of/gpio.c
@@ -127,8 +127,8 @@ EXPORT_SYMBOL(of_gpio_count);
127 * gpio chips. This function performs only one sanity check: whether gpio 127 * gpio chips. This function performs only one sanity check: whether gpio
128 * is less than ngpios (that is specified in the gpio_chip). 128 * is less than ngpios (that is specified in the gpio_chip).
129 */ 129 */
130static int of_gpio_simple_xlate(struct gpio_chip *gc, struct device_node *np, 130int of_gpio_simple_xlate(struct gpio_chip *gc, struct device_node *np,
131 const void *gpio_spec, u32 *flags) 131 const void *gpio_spec, u32 *flags)
132{ 132{
133 const __be32 *gpio = gpio_spec; 133 const __be32 *gpio = gpio_spec;
134 const u32 n = be32_to_cpup(gpio); 134 const u32 n = be32_to_cpup(gpio);
@@ -152,6 +152,7 @@ static int of_gpio_simple_xlate(struct gpio_chip *gc, struct device_node *np,
152 152
153 return n; 153 return n;
154} 154}
155EXPORT_SYMBOL(of_gpio_simple_xlate);
155 156
156/** 157/**
157 * of_mm_gpiochip_add - Add memory mapped GPIO chip (bank) 158 * of_mm_gpiochip_add - Add memory mapped GPIO chip (bank)
diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
index aec8025c786a..52280a2b5e63 100644
--- a/include/linux/of_gpio.h
+++ b/include/linux/of_gpio.h
@@ -57,6 +57,8 @@ extern int of_mm_gpiochip_add(struct device_node *np,
57extern void of_gpiochip_add(struct gpio_chip *gc); 57extern void of_gpiochip_add(struct gpio_chip *gc);
58extern void of_gpiochip_remove(struct gpio_chip *gc); 58extern void of_gpiochip_remove(struct gpio_chip *gc);
59extern struct gpio_chip *of_node_to_gpiochip(struct device_node *np); 59extern struct gpio_chip *of_node_to_gpiochip(struct device_node *np);
60extern int of_gpio_simple_xlate(struct gpio_chip *gc, struct device_node *np,
61 const void *gpio_spec, u32 *flags);
60 62
61#else /* CONFIG_OF_GPIO */ 63#else /* CONFIG_OF_GPIO */
62 64
@@ -72,6 +74,13 @@ static inline unsigned int of_gpio_count(struct device_node *np)
72 return 0; 74 return 0;
73} 75}
74 76
77static inline int of_gpio_simple_xlate(struct gpio_chip *gc,
78 struct device_node *np,
79 const void *gpio_spec, u32 *flags)
80{
81 return -ENOSYS;
82}
83
75static inline void of_gpiochip_add(struct gpio_chip *gc) { } 84static inline void of_gpiochip_add(struct gpio_chip *gc) { }
76static inline void of_gpiochip_remove(struct gpio_chip *gc) { } 85static inline void of_gpiochip_remove(struct gpio_chip *gc) { }
77 86
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 09:34:15 -0500