diff options
author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2007-08-09 19:09:38 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2007-10-12 18:03:15 -0400 |
commit | 40730d1042c595b1e84b28e40021f2c1377b4f8b (patch) | |
tree | 4995209dcdcd8f28ab2df412f7673481065391dd | |
parent | 9fe8164536c4fa6e630c706c667a2c6e8456d143 (diff) |
pciehp: minor cleanups for pciehp_hpc.c
Minor cleanups for pciehp_hpc.c. The 80 column rules, removing
unnecessary lines, and so on.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r-- | drivers/pci/hotplug/pciehp_hpc.c | 47 |
1 files changed, 26 insertions, 21 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 2e501f73c3b6..06d025b8b13f 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c | |||
@@ -203,7 +203,7 @@ static void int_poll_timeout(unsigned long data) | |||
203 | 203 | ||
204 | init_timer(&ctrl->poll_timer); | 204 | init_timer(&ctrl->poll_timer); |
205 | if (!pciehp_poll_time) | 205 | if (!pciehp_poll_time) |
206 | pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ | 206 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
207 | 207 | ||
208 | start_int_poll_timer(ctrl, pciehp_poll_time); | 208 | start_int_poll_timer(ctrl, pciehp_poll_time); |
209 | } | 209 | } |
@@ -320,7 +320,6 @@ static int hpc_check_lnk_status(struct controller *ctrl) | |||
320 | return retval; | 320 | return retval; |
321 | } | 321 | } |
322 | 322 | ||
323 | |||
324 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | 323 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
325 | { | 324 | { |
326 | struct controller *ctrl = slot->ctrl; | 325 | struct controller *ctrl = slot->ctrl; |
@@ -392,7 +391,6 @@ static int hpc_get_power_status(struct slot *slot, u8 *status) | |||
392 | return retval; | 391 | return retval; |
393 | } | 392 | } |
394 | 393 | ||
395 | |||
396 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | 394 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
397 | { | 395 | { |
398 | struct controller *ctrl = slot->ctrl; | 396 | struct controller *ctrl = slot->ctrl; |
@@ -513,7 +511,6 @@ static int hpc_set_attention_status(struct slot *slot, u8 value) | |||
513 | return rc; | 511 | return rc; |
514 | } | 512 | } |
515 | 513 | ||
516 | |||
517 | static void hpc_set_green_led_on(struct slot *slot) | 514 | static void hpc_set_green_led_on(struct slot *slot) |
518 | { | 515 | { |
519 | struct controller *ctrl = slot->ctrl; | 516 | struct controller *ctrl = slot->ctrl; |
@@ -695,8 +692,8 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) | |||
695 | return IRQ_NONE; | 692 | return IRQ_NONE; |
696 | } | 693 | } |
697 | 694 | ||
698 | intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED | | 695 | intr_detect = (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | |
699 | PRSN_DETECT_CHANGED | CMD_COMPLETED ); | 696 | MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | CMD_COMPLETED); |
700 | 697 | ||
701 | intr_loc = slot_status & intr_detect; | 698 | intr_loc = slot_status & intr_detect; |
702 | 699 | ||
@@ -718,7 +715,8 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) | |||
718 | 715 | ||
719 | dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n", | 716 | dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n", |
720 | __FUNCTION__, temp_word); | 717 | __FUNCTION__, temp_word); |
721 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; | 718 | temp_word = (temp_word & ~HP_INTR_ENABLE & |
719 | ~CMD_CMPL_INTR_ENABLE) | 0x00; | ||
722 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); | 720 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
723 | if (rc) { | 721 | if (rc) { |
724 | err("%s: Cannot write to SLOTCTRL register\n", | 722 | err("%s: Cannot write to SLOTCTRL register\n", |
@@ -819,7 +817,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) | |||
819 | return IRQ_HANDLED; | 817 | return IRQ_HANDLED; |
820 | } | 818 | } |
821 | 819 | ||
822 | static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | 820 | static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
823 | { | 821 | { |
824 | struct controller *ctrl = slot->ctrl; | 822 | struct controller *ctrl = slot->ctrl; |
825 | enum pcie_link_speed lnk_speed; | 823 | enum pcie_link_speed lnk_speed; |
@@ -847,7 +845,8 @@ static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |||
847 | return retval; | 845 | return retval; |
848 | } | 846 | } |
849 | 847 | ||
850 | static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value) | 848 | static int hpc_get_max_lnk_width(struct slot *slot, |
849 | enum pcie_link_width *value) | ||
851 | { | 850 | { |
852 | struct controller *ctrl = slot->ctrl; | 851 | struct controller *ctrl = slot->ctrl; |
853 | enum pcie_link_width lnk_wdth; | 852 | enum pcie_link_width lnk_wdth; |
@@ -896,7 +895,7 @@ static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value | |||
896 | return retval; | 895 | return retval; |
897 | } | 896 | } |
898 | 897 | ||
899 | static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | 898 | static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
900 | { | 899 | { |
901 | struct controller *ctrl = slot->ctrl; | 900 | struct controller *ctrl = slot->ctrl; |
902 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; | 901 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
@@ -924,7 +923,8 @@ static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |||
924 | return retval; | 923 | return retval; |
925 | } | 924 | } |
926 | 925 | ||
927 | static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value) | 926 | static int hpc_get_cur_lnk_width(struct slot *slot, |
927 | enum pcie_link_width *value) | ||
928 | { | 928 | { |
929 | struct controller *ctrl = slot->ctrl; | 929 | struct controller *ctrl = slot->ctrl; |
930 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | 930 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
@@ -1067,8 +1067,6 @@ int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) | |||
1067 | } | 1067 | } |
1068 | #endif | 1068 | #endif |
1069 | 1069 | ||
1070 | |||
1071 | |||
1072 | int pcie_init(struct controller * ctrl, struct pcie_device *dev) | 1070 | int pcie_init(struct controller * ctrl, struct pcie_device *dev) |
1073 | { | 1071 | { |
1074 | int rc; | 1072 | int rc; |
@@ -1103,9 +1101,11 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev) | |||
1103 | dbg("%s: CAPREG offset %x cap_reg %x\n", | 1101 | dbg("%s: CAPREG offset %x cap_reg %x\n", |
1104 | __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg); | 1102 | __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg); |
1105 | 1103 | ||
1106 | if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040) | 1104 | if (((cap_reg & SLOT_IMPL) == 0) || |
1105 | (((cap_reg & DEV_PORT_TYPE) != 0x0040) | ||
1107 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { | 1106 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { |
1108 | dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__); | 1107 | dbg("%s : This is not a root port or the port is not " |
1108 | "connected to a slot\n", __FUNCTION__); | ||
1109 | goto abort_free_ctlr; | 1109 | goto abort_free_ctlr; |
1110 | } | 1110 | } |
1111 | 1111 | ||
@@ -1138,14 +1138,15 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev) | |||
1138 | dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n", | 1138 | dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n", |
1139 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | 1139 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1140 | 1140 | ||
1141 | for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) | 1141 | for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) |
1142 | if (pci_resource_len(pdev, rc) > 0) | 1142 | if (pci_resource_len(pdev, rc) > 0) |
1143 | dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc, | 1143 | dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc, |
1144 | (unsigned long long)pci_resource_start(pdev, rc), | 1144 | (unsigned long long)pci_resource_start(pdev, rc), |
1145 | (unsigned long long)pci_resource_len(pdev, rc)); | 1145 | (unsigned long long)pci_resource_len(pdev, rc)); |
1146 | 1146 | ||
1147 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, | 1147 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1148 | pdev->subsystem_vendor, pdev->subsystem_device); | 1148 | pdev->vendor, pdev->device, |
1149 | pdev->subsystem_vendor, pdev->subsystem_device); | ||
1149 | 1150 | ||
1150 | mutex_init(&ctrl->crit_sect); | 1151 | mutex_init(&ctrl->crit_sect); |
1151 | mutex_init(&ctrl->ctrl_lock); | 1152 | mutex_init(&ctrl->ctrl_lock); |
@@ -1169,7 +1170,8 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev) | |||
1169 | 1170 | ||
1170 | dbg("%s: SLOTCTRL %x value read %x\n", | 1171 | dbg("%s: SLOTCTRL %x value read %x\n", |
1171 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word); | 1172 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word); |
1172 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; | 1173 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | |
1174 | 0x00; | ||
1173 | 1175 | ||
1174 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); | 1176 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1175 | if (rc) { | 1177 | if (rc) { |
@@ -1247,7 +1249,10 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev) | |||
1247 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; | 1249 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; |
1248 | } | 1250 | } |
1249 | 1251 | ||
1250 | /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ | 1252 | /* |
1253 | * Unmask Hot-plug Interrupt Enable for the interrupt | ||
1254 | * notification mechanism case. | ||
1255 | */ | ||
1251 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); | 1256 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1252 | if (rc) { | 1257 | if (rc) { |
1253 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); | 1258 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); |
@@ -1279,7 +1284,7 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev) | |||
1279 | 1284 | ||
1280 | return 0; | 1285 | return 0; |
1281 | 1286 | ||
1282 | /* We end up here for the many possible ways to fail this API. */ | 1287 | /* We end up here for the many possible ways to fail this API. */ |
1283 | abort_disable_intr: | 1288 | abort_disable_intr: |
1284 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); | 1289 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1285 | if (!rc) { | 1290 | if (!rc) { |