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authorFabio Estevam <festevam@gmail.com>2010-12-15 19:31:28 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2010-12-16 16:37:48 -0500
commit0247a7bcd4273fa10c4aba9b3f567c659bab2d2b (patch)
tree78316e82037bad3cbfcb329f240181671b6b0f7e
parent2c8245c4990e75d86ab30bb0af9bb90cbe04985d (diff)
USB: ehci-mxc: Setup portsc register prior to accessing OTG viewport
In order to read/write to the i.MX OTG viewport register it is necessary to setup the PORTSCx register first. By default i.MX OTG port is configured for USB serial PHY. In order to use a ULPI PHY the PORTSCx register needs to be configured properly. commit 724c852 (USB: ehci/mxc: compile fix) placed the PORTSC setup after the OTG viewport is accessed and this causes ULPI read/write to fail. Revert the PORTSC setup order. Tested on a MX31PDK board with a ISP1504 transceiver: ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver mxc-ehci mxc-ehci.0: initializing i.MX USB Controller ULPI transceiver vendor/product ID 0x04cc/0x1504 Found NXP ISP1504 ULPI transceiver. ULPI integrity check: passed. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/usb/host/ehci-mxc.c26
1 files changed, 14 insertions, 12 deletions
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index f6e5d44c06b6..535dcae7949f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -36,14 +36,8 @@ struct ehci_mxc_priv {
36static int ehci_mxc_setup(struct usb_hcd *hcd) 36static int ehci_mxc_setup(struct usb_hcd *hcd)
37{ 37{
38 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 38 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
39 struct device *dev = hcd->self.controller;
40 struct mxc_usbh_platform_data *pdata = dev_get_platdata(dev);
41 int retval; 39 int retval;
42 40
43 /* EHCI registers start at offset 0x100 */
44 ehci->caps = hcd->regs + 0x100;
45 ehci->regs = hcd->regs + 0x100 +
46 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
47 dbg_hcs_params(ehci, "reset"); 41 dbg_hcs_params(ehci, "reset");
48 dbg_hcc_params(ehci, "reset"); 42 dbg_hcc_params(ehci, "reset");
49 43
@@ -65,12 +59,6 @@ static int ehci_mxc_setup(struct usb_hcd *hcd)
65 59
66 ehci_reset(ehci); 60 ehci_reset(ehci);
67 61
68 /* set up the PORTSCx register */
69 ehci_writel(ehci, pdata->portsc, &ehci->regs->port_status[0]);
70
71 /* is this really needed? */
72 msleep(10);
73
74 ehci_port_power(ehci, 0); 62 ehci_port_power(ehci, 0);
75 return 0; 63 return 0;
76} 64}
@@ -128,6 +116,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
128 int irq, ret; 116 int irq, ret;
129 struct ehci_mxc_priv *priv; 117 struct ehci_mxc_priv *priv;
130 struct device *dev = &pdev->dev; 118 struct device *dev = &pdev->dev;
119 struct ehci_hcd *ehci;
131 120
132 dev_info(&pdev->dev, "initializing i.MX USB Controller\n"); 121 dev_info(&pdev->dev, "initializing i.MX USB Controller\n");
133 122
@@ -204,6 +193,19 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
204 if (ret < 0) 193 if (ret < 0)
205 goto err_init; 194 goto err_init;
206 195
196 ehci = hcd_to_ehci(hcd);
197
198 /* EHCI registers start at offset 0x100 */
199 ehci->caps = hcd->regs + 0x100;
200 ehci->regs = hcd->regs + 0x100 +
201 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
202
203 /* set up the PORTSCx register */
204 ehci_writel(ehci, pdata->portsc, &ehci->regs->port_status[0]);
205
206 /* is this really needed? */
207 msleep(10);
208
207 /* Initialize the transceiver */ 209 /* Initialize the transceiver */
208 if (pdata->otg) { 210 if (pdata->otg) {
209 pdata->otg->io_priv = hcd->regs + ULPI_VIEWPORT_OFFSET; 211 pdata->otg->io_priv = hcd->regs + ULPI_VIEWPORT_OFFSET;