diff options
author | Jeremy Fitzhardinge <jeremy@goop.org> | 2008-07-10 19:22:56 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-07-11 09:44:57 -0400 |
commit | 8d28aab59fe939be40efae870ced0b05caa259fb (patch) | |
tree | 63cbe1eb47521a9005d98c695d44c4ab480730d3 | |
parent | 3d0decc4f49e8645cd6369b02ed076bebd3d61ad (diff) |
x86_64: add pseudo-features for 32-bit compat syscall
Add pseudo-feature bits to describe whether the CPU supports sysenter
and/or syscall from ia32-compat userspace. This removes a hardcoded
test in vdso32-setup.
Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
-rw-r--r-- | arch/x86/kernel/cpu/centaur_64.c | 2 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/common_64.c | 3 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/intel_64.c | 2 | ||||
-rw-r--r-- | include/asm-x86/cpufeature.h | 4 |
4 files changed, 9 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/centaur_64.c b/arch/x86/kernel/cpu/centaur_64.c index 13526fd5cce1..2026d2119cdb 100644 --- a/arch/x86/kernel/cpu/centaur_64.c +++ b/arch/x86/kernel/cpu/centaur_64.c | |||
@@ -10,6 +10,8 @@ static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c) | |||
10 | { | 10 | { |
11 | if (c->x86 == 0x6 && c->x86_model >= 0xf) | 11 | if (c->x86 == 0x6 && c->x86_model >= 0xf) |
12 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | 12 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
13 | |||
14 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | ||
13 | } | 15 | } |
14 | 16 | ||
15 | static void __cpuinit init_centaur(struct cpuinfo_x86 *c) | 17 | static void __cpuinit init_centaur(struct cpuinfo_x86 *c) |
diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c index 751850235291..36537ab9e56a 100644 --- a/arch/x86/kernel/cpu/common_64.c +++ b/arch/x86/kernel/cpu/common_64.c | |||
@@ -314,6 +314,9 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c) | |||
314 | if (c->extended_cpuid_level >= 0x80000007) | 314 | if (c->extended_cpuid_level >= 0x80000007) |
315 | c->x86_power = cpuid_edx(0x80000007); | 315 | c->x86_power = cpuid_edx(0x80000007); |
316 | 316 | ||
317 | /* Assume all 64-bit CPUs support 32-bit syscall */ | ||
318 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | ||
319 | |||
317 | if (c->x86_vendor != X86_VENDOR_UNKNOWN && | 320 | if (c->x86_vendor != X86_VENDOR_UNKNOWN && |
318 | cpu_devs[c->x86_vendor]->c_early_init) | 321 | cpu_devs[c->x86_vendor]->c_early_init) |
319 | cpu_devs[c->x86_vendor]->c_early_init(c); | 322 | cpu_devs[c->x86_vendor]->c_early_init(c); |
diff --git a/arch/x86/kernel/cpu/intel_64.c b/arch/x86/kernel/cpu/intel_64.c index fcb1cc9d75ca..02f773399e39 100644 --- a/arch/x86/kernel/cpu/intel_64.c +++ b/arch/x86/kernel/cpu/intel_64.c | |||
@@ -12,6 +12,8 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) | |||
12 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || | 12 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
13 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | 13 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) |
14 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | 14 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
15 | |||
16 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | ||
15 | } | 17 | } |
16 | 18 | ||
17 | /* | 19 | /* |
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 84a56da397b1..75ef959db329 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h | |||
@@ -74,8 +74,8 @@ | |||
74 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ | 74 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
75 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | 75 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
76 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | 76 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
77 | /* 14 free */ | 77 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ |
78 | /* 15 free */ | 78 | #define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ |
79 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ | 79 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ |
80 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ | 80 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ |
81 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ | 81 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ |