diff options
author | Ed Lin <ed.lin@promise.com> | 2007-05-10 00:50:37 -0400 |
---|---|---|
committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-16 12:40:51 -0400 |
commit | 69f4a513911455670d3322fb5252b437c0485707 (patch) | |
tree | 15343daad98d417ed1e498a7792e6d08200a614d | |
parent | e0b2e597d5dd8c4f3778545f65c29a9c6aba0e3a (diff) |
[SCSI] stex: extend hard reset wait time
During hard bus reset of st_shasta controllers, 1 ms is not enough for
16-port controllers, although it's good for 8-port controllers. Extend the
wait time to 100 ms to allow bus resets finish successfully.
Signed-off-by: Ed Lin <ed.lin@promise.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
-rw-r--r-- | drivers/scsi/stex.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c index 96dcbac9545e..81dd3b740daf 100644 --- a/drivers/scsi/stex.c +++ b/drivers/scsi/stex.c | |||
@@ -1041,7 +1041,12 @@ static void stex_hard_reset(struct st_hba *hba) | |||
1041 | pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); | 1041 | pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); |
1042 | pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; | 1042 | pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; |
1043 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); | 1043 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); |
1044 | msleep(1); | 1044 | |
1045 | /* | ||
1046 | * 1 ms may be enough for 8-port controllers. But 16-port controllers | ||
1047 | * require more time to finish bus reset. Use 100 ms here for safety | ||
1048 | */ | ||
1049 | msleep(100); | ||
1045 | pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; | 1050 | pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
1046 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); | 1051 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); |
1047 | 1052 | ||