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authorMichael Krufky <mkrufky@linuxtv.org>2008-01-01 20:52:09 -0500
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-01-25 16:04:35 -0500
commit255b5113b4ed683898a24e381155c081f03411f7 (patch)
tree7deff2cb03c7d7c4209f4a826d8bda96e0a8447a
parentdec9ccceef9bfd5f3cccc79e90b09f6c31ed3279 (diff)
V4L/DVB (6960): tda18271: add support for NXP TDA18271HD/C2
Tested successfully with QAM256 digital cable. Analog television is limping, needs more work. Signed-off-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat
-rw-r--r--drivers/media/dvb/frontends/tda18271-fe.c885
-rw-r--r--drivers/media/dvb/frontends/tda18271-priv.h72
-rw-r--r--drivers/media/dvb/frontends/tda18271-tables.c932
-rw-r--r--drivers/media/video/tda8290.c2
4 files changed, 1779 insertions, 112 deletions
diff --git a/drivers/media/dvb/frontends/tda18271-fe.c b/drivers/media/dvb/frontends/tda18271-fe.c
index 2c873ae6e8c1..4b53baf12efc 100644
--- a/drivers/media/dvb/frontends/tda18271-fe.c
+++ b/drivers/media/dvb/frontends/tda18271-fe.c
@@ -71,7 +71,7 @@ static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
71 71
72/*---------------------------------------------------------------------*/ 72/*---------------------------------------------------------------------*/
73 73
74static void tda18271_dump_regs(struct dvb_frontend *fe) 74static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
75{ 75{
76 struct tda18271_priv *priv = fe->tuner_priv; 76 struct tda18271_priv *priv = fe->tuner_priv;
77 unsigned char *regs = priv->tda18271_regs; 77 unsigned char *regs = priv->tda18271_regs;
@@ -93,6 +93,37 @@ static void tda18271_dump_regs(struct dvb_frontend *fe)
93 tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]); 93 tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
94 tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]); 94 tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
95 tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]); 95 tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
96
97 /* only dump extended regs if DBG_ADV is set */
98 if (!(tda18271_debug & DBG_ADV))
99 return;
100
101 /* W indicates write-only registers.
102 * Register dump for write-only registers shows last value written. */
103
104 tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
105 tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
106 tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
107 tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
108 tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
109 tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
110 tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
111 tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
112 tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
113 tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
114 tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
115 tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
116 tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
117 tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
118 tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
119 tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
120 tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
121 tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
122 tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
123 tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
124 tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
125 tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
126 tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
96} 127}
97 128
98static void tda18271_read_regs(struct dvb_frontend *fe) 129static void tda18271_read_regs(struct dvb_frontend *fe)
@@ -119,7 +150,45 @@ static void tda18271_read_regs(struct dvb_frontend *fe)
119 tda_err("ERROR: i2c_transfer returned: %d\n", ret); 150 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
120 151
121 if (tda18271_debug & DBG_REG) 152 if (tda18271_debug & DBG_REG)
122 tda18271_dump_regs(fe); 153 tda18271_dump_regs(fe, 0);
154}
155
156static void tda18271_read_extended(struct dvb_frontend *fe)
157{
158 struct tda18271_priv *priv = fe->tuner_priv;
159 unsigned char *regs = priv->tda18271_regs;
160 unsigned char regdump[TDA18271_NUM_REGS];
161 unsigned char buf = 0x00;
162 int ret, i;
163 struct i2c_msg msg[] = {
164 { .addr = priv->i2c_addr, .flags = 0,
165 .buf = &buf, .len = 1 },
166 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
167 .buf = regdump, .len = TDA18271_NUM_REGS }
168 };
169
170 tda18271_i2c_gate_ctrl(fe, 1);
171
172 /* read all registers */
173 ret = i2c_transfer(priv->i2c_adap, msg, 2);
174
175 tda18271_i2c_gate_ctrl(fe, 0);
176
177 if (ret != 2)
178 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
179
180 for (i = 0; i <= TDA18271_NUM_REGS; i++) {
181 /* don't update write-only registers */
182 if ((i != R_EB9) &&
183 (i != R_EB16) &&
184 (i != R_EB17) &&
185 (i != R_EB19) &&
186 (i != R_EB20))
187 regs[i] = regdump[i];
188 }
189
190 if (tda18271_debug & DBG_REG)
191 tda18271_dump_regs(fe, 1);
123} 192}
124 193
125static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len) 194static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
@@ -160,7 +229,15 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
160 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr); 229 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr);
161 230
162 /* initialize registers */ 231 /* initialize registers */
163 regs[R_ID] = 0x83; 232 switch (priv->id) {
233 case TDA18271HDC1:
234 regs[R_ID] = 0x83;
235 break;
236 case TDA18271HDC2:
237 regs[R_ID] = 0x84;
238 break;
239 };
240
164 regs[R_TM] = 0x08; 241 regs[R_TM] = 0x08;
165 regs[R_PL] = 0x80; 242 regs[R_PL] = 0x80;
166 regs[R_EP1] = 0xc6; 243 regs[R_EP1] = 0xc6;
@@ -176,7 +253,16 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
176 regs[R_MD1] = 0x00; 253 regs[R_MD1] = 0x00;
177 regs[R_MD2] = 0x00; 254 regs[R_MD2] = 0x00;
178 regs[R_MD3] = 0x00; 255 regs[R_MD3] = 0x00;
179 regs[R_EB1] = 0xff; 256
257 switch (priv->id) {
258 case TDA18271HDC1:
259 regs[R_EB1] = 0xff;
260 break;
261 case TDA18271HDC2:
262 regs[R_EB1] = 0xfc;
263 break;
264 };
265
180 regs[R_EB2] = 0x01; 266 regs[R_EB2] = 0x01;
181 regs[R_EB3] = 0x84; 267 regs[R_EB3] = 0x84;
182 regs[R_EB4] = 0x41; 268 regs[R_EB4] = 0x41;
@@ -187,21 +273,49 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
187 regs[R_EB9] = 0x00; 273 regs[R_EB9] = 0x00;
188 regs[R_EB10] = 0x00; 274 regs[R_EB10] = 0x00;
189 regs[R_EB11] = 0x96; 275 regs[R_EB11] = 0x96;
190 regs[R_EB12] = 0x0f; 276
277 switch (priv->id) {
278 case TDA18271HDC1:
279 regs[R_EB12] = 0x0f;
280 break;
281 case TDA18271HDC2:
282 regs[R_EB12] = 0x33;
283 break;
284 };
285
191 regs[R_EB13] = 0xc1; 286 regs[R_EB13] = 0xc1;
192 regs[R_EB14] = 0x00; 287 regs[R_EB14] = 0x00;
193 regs[R_EB15] = 0x8f; 288 regs[R_EB15] = 0x8f;
194 regs[R_EB16] = 0x00; 289 regs[R_EB16] = 0x00;
195 regs[R_EB17] = 0x00; 290 regs[R_EB17] = 0x00;
196 regs[R_EB18] = 0x00; 291
292 switch (priv->id) {
293 case TDA18271HDC1:
294 regs[R_EB18] = 0x00;
295 break;
296 case TDA18271HDC2:
297 regs[R_EB18] = 0x8c;
298 break;
299 };
300
197 regs[R_EB19] = 0x00; 301 regs[R_EB19] = 0x00;
198 regs[R_EB20] = 0x20; 302 regs[R_EB20] = 0x20;
199 regs[R_EB21] = 0x33; 303
304 switch (priv->id) {
305 case TDA18271HDC1:
306 regs[R_EB21] = 0x33;
307 break;
308 case TDA18271HDC2:
309 regs[R_EB21] = 0xb3;
310 break;
311 };
312
200 regs[R_EB22] = 0x48; 313 regs[R_EB22] = 0x48;
201 regs[R_EB23] = 0xb0; 314 regs[R_EB23] = 0xb0;
202 315
203 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS); 316 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
204 /* setup AGC1 & AGC2 */ 317
318 /* setup agc1 gain */
205 regs[R_EB17] = 0x00; 319 regs[R_EB17] = 0x00;
206 tda18271_write_regs(fe, R_EB17, 1); 320 tda18271_write_regs(fe, R_EB17, 1);
207 regs[R_EB17] = 0x03; 321 regs[R_EB17] = 0x03;
@@ -211,14 +325,17 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
211 regs[R_EB17] = 0x4c; 325 regs[R_EB17] = 0x4c;
212 tda18271_write_regs(fe, R_EB17, 1); 326 tda18271_write_regs(fe, R_EB17, 1);
213 327
214 regs[R_EB20] = 0xa0; 328 /* setup agc2 gain */
215 tda18271_write_regs(fe, R_EB20, 1); 329 if ((priv->id) == TDA18271HDC1) {
216 regs[R_EB20] = 0xa7; 330 regs[R_EB20] = 0xa0;
217 tda18271_write_regs(fe, R_EB20, 1); 331 tda18271_write_regs(fe, R_EB20, 1);
218 regs[R_EB20] = 0xe7; 332 regs[R_EB20] = 0xa7;
219 tda18271_write_regs(fe, R_EB20, 1); 333 tda18271_write_regs(fe, R_EB20, 1);
220 regs[R_EB20] = 0xec; 334 regs[R_EB20] = 0xe7;
221 tda18271_write_regs(fe, R_EB20, 1); 335 tda18271_write_regs(fe, R_EB20, 1);
336 regs[R_EB20] = 0xec;
337 tda18271_write_regs(fe, R_EB20, 1);
338 }
222 339
223 /* image rejection calibration */ 340 /* image rejection calibration */
224 341
@@ -235,103 +352,102 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
235 regs[R_MD2] = 0x08; 352 regs[R_MD2] = 0x08;
236 regs[R_MD3] = 0x00; 353 regs[R_MD3] = 0x00;
237 354
238 tda18271_write_regs(fe, R_EP3, 11); 355 switch (priv->id) {
356 case TDA18271HDC1:
357 tda18271_write_regs(fe, R_EP3, 11);
358 break;
359 case TDA18271HDC2:
360 tda18271_write_regs(fe, R_EP3, 12);
361 break;
362 };
363
364 if ((priv->id) == TDA18271HDC2) {
365 /* main pll cp source on */
366 regs[R_EB4] = 0x61;
367 tda18271_write_regs(fe, R_EB4, 1);
368 msleep(1);
369
370 /* main pll cp source off */
371 regs[R_EB4] = 0x41;
372 tda18271_write_regs(fe, R_EB4, 1);
373 }
374
239 msleep(5); /* pll locking */ 375 msleep(5); /* pll locking */
240 376
241 regs[R_EP1] = 0xc6; 377 /* launch detector */
242 tda18271_write_regs(fe, R_EP1, 1); 378 tda18271_write_regs(fe, R_EP1, 1);
243 msleep(5); /* wanted low measurement */ 379 msleep(5); /* wanted low measurement */
244 380
245 regs[R_EP3] = 0x1f;
246 regs[R_EP4] = 0x66;
247 regs[R_EP5] = 0x85; 381 regs[R_EP5] = 0x85;
248 regs[R_CPD] = 0xcb; 382 regs[R_CPD] = 0xcb;
249 regs[R_CD1] = 0x66; 383 regs[R_CD1] = 0x66;
250 regs[R_CD2] = 0x70; 384 regs[R_CD2] = 0x70;
251 regs[R_CD3] = 0x00;
252 385
253 tda18271_write_regs(fe, R_EP3, 7); 386 tda18271_write_regs(fe, R_EP3, 7);
254 msleep(5); /* pll locking */ 387 msleep(5); /* pll locking */
255 388
256 regs[R_EP2] = 0xdf; 389 /* launch optimization algorithm */
257 tda18271_write_regs(fe, R_EP2, 1); 390 tda18271_write_regs(fe, R_EP2, 1);
258 msleep(30); /* image low optimization completion */ 391 msleep(30); /* image low optimization completion */
259 392
260 /* mid-band */ 393 /* mid-band */
261 regs[R_EP3] = 0x1f;
262 regs[R_EP4] = 0x66;
263 regs[R_EP5] = 0x82; 394 regs[R_EP5] = 0x82;
264 regs[R_CPD] = 0xa8; 395 regs[R_CPD] = 0xa8;
265 regs[R_CD1] = 0x66;
266 regs[R_CD2] = 0x00; 396 regs[R_CD2] = 0x00;
267 regs[R_CD3] = 0x00;
268 regs[R_MPD] = 0xa9; 397 regs[R_MPD] = 0xa9;
269 regs[R_MD1] = 0x73; 398 regs[R_MD1] = 0x73;
270 regs[R_MD2] = 0x1a; 399 regs[R_MD2] = 0x1a;
271 regs[R_MD3] = 0x00;
272 400
273 tda18271_write_regs(fe, R_EP3, 11); 401 tda18271_write_regs(fe, R_EP3, 11);
274 msleep(5); /* pll locking */ 402 msleep(5); /* pll locking */
275 403
276 regs[R_EP1] = 0xc6;
277 tda18271_write_regs(fe, R_EP1, 1); 404 tda18271_write_regs(fe, R_EP1, 1);
278 msleep(5); /* wanted mid measurement */ 405 msleep(5); /* wanted mid measurement */
279 406
280 regs[R_EP3] = 0x1f;
281 regs[R_EP4] = 0x66;
282 regs[R_EP5] = 0x86; 407 regs[R_EP5] = 0x86;
283 regs[R_CPD] = 0xa8; 408 regs[R_CPD] = 0xa8;
284 regs[R_CD1] = 0x66; 409 regs[R_CD1] = 0x66;
285 regs[R_CD2] = 0xa0; 410 regs[R_CD2] = 0xa0;
286 regs[R_CD3] = 0x00;
287 411
288 tda18271_write_regs(fe, R_EP3, 7); 412 tda18271_write_regs(fe, R_EP3, 7);
289 msleep(5); /* pll locking */ 413 msleep(5); /* pll locking */
290 414
291 regs[R_EP2] = 0xdf; 415 /* launch optimization algorithm */
292 tda18271_write_regs(fe, R_EP2, 1); 416 tda18271_write_regs(fe, R_EP2, 1);
293 msleep(30); /* image mid optimization completion */ 417 msleep(30); /* image mid optimization completion */
294 418
295 /* high-band */ 419 /* high-band */
296 regs[R_EP3] = 0x1f;
297 regs[R_EP4] = 0x66;
298 regs[R_EP5] = 0x83; 420 regs[R_EP5] = 0x83;
299 regs[R_CPD] = 0x98; 421 regs[R_CPD] = 0x98;
300 regs[R_CD1] = 0x65; 422 regs[R_CD1] = 0x65;
301 regs[R_CD2] = 0x00; 423 regs[R_CD2] = 0x00;
302 regs[R_CD3] = 0x00;
303 regs[R_MPD] = 0x99; 424 regs[R_MPD] = 0x99;
304 regs[R_MD1] = 0x71; 425 regs[R_MD1] = 0x71;
305 regs[R_MD2] = 0xcd; 426 regs[R_MD2] = 0xcd;
306 regs[R_MD3] = 0x00;
307 427
308 tda18271_write_regs(fe, R_EP3, 11); 428 tda18271_write_regs(fe, R_EP3, 11);
309 msleep(5); /* pll locking */ 429 msleep(5); /* pll locking */
310 430
311 regs[R_EP1] = 0xc6; 431 /* launch detector */
312 tda18271_write_regs(fe, R_EP1, 1); 432 tda18271_write_regs(fe, R_EP1, 1);
313 msleep(5); /* wanted high measurement */ 433 msleep(5); /* wanted high measurement */
314 434
315 regs[R_EP3] = 0x1f;
316 regs[R_EP4] = 0x66;
317 regs[R_EP5] = 0x87; 435 regs[R_EP5] = 0x87;
318 regs[R_CPD] = 0x98;
319 regs[R_CD1] = 0x65; 436 regs[R_CD1] = 0x65;
320 regs[R_CD2] = 0x50; 437 regs[R_CD2] = 0x50;
321 regs[R_CD3] = 0x00;
322 438
323 tda18271_write_regs(fe, R_EP3, 7); 439 tda18271_write_regs(fe, R_EP3, 7);
324 msleep(5); /* pll locking */ 440 msleep(5); /* pll locking */
325 441
326 regs[R_EP2] = 0xdf; 442 /* launch optimization algorithm */
327
328 tda18271_write_regs(fe, R_EP2, 1); 443 tda18271_write_regs(fe, R_EP2, 1);
329 msleep(30); /* image high optimization completion */ 444 msleep(30); /* image high optimization completion */
330 445
446 /* return to normal mode */
331 regs[R_EP4] = 0x64; 447 regs[R_EP4] = 0x64;
332 tda18271_write_regs(fe, R_EP4, 1); 448 tda18271_write_regs(fe, R_EP4, 1);
333 449
334 regs[R_EP1] = 0xc6; 450 /* synchronize */
335 tda18271_write_regs(fe, R_EP1, 1); 451 tda18271_write_regs(fe, R_EP1, 1);
336 452
337 return 0; 453 return 0;
@@ -359,7 +475,7 @@ static int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
359 u8 d, pd; 475 u8 d, pd;
360 u32 div; 476 u32 div;
361 477
362 int ret = tda18271_lookup_pll_map(MAIN_PLL, &freq, &pd, &d); 478 int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
363 if (ret < 0) 479 if (ret < 0)
364 goto fail; 480 goto fail;
365 481
@@ -391,7 +507,7 @@ static int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
391 u8 d, pd; 507 u8 d, pd;
392 u32 div; 508 u32 div;
393 509
394 int ret = tda18271_lookup_pll_map(CAL_PLL, &freq, &pd, &d); 510 int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
395 if (ret < 0) 511 if (ret < 0)
396 goto fail; 512 goto fail;
397 513
@@ -413,7 +529,7 @@ static int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
413 unsigned char *regs = priv->tda18271_regs; 529 unsigned char *regs = priv->tda18271_regs;
414 u8 val; 530 u8 val;
415 531
416 int ret = tda18271_lookup_map(BP_FILTER, freq, &val); 532 int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
417 if (ret < 0) 533 if (ret < 0)
418 goto fail; 534 goto fail;
419 535
@@ -430,7 +546,7 @@ static int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
430 unsigned char *regs = priv->tda18271_regs; 546 unsigned char *regs = priv->tda18271_regs;
431 u8 val; 547 u8 val;
432 548
433 int ret = tda18271_lookup_map(RF_CAL_KMCO, freq, &val); 549 int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
434 if (ret < 0) 550 if (ret < 0)
435 goto fail; 551 goto fail;
436 552
@@ -447,7 +563,7 @@ static int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
447 unsigned char *regs = priv->tda18271_regs; 563 unsigned char *regs = priv->tda18271_regs;
448 u8 val; 564 u8 val;
449 565
450 int ret = tda18271_lookup_map(RF_BAND, freq, &val); 566 int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
451 if (ret < 0) 567 if (ret < 0)
452 goto fail; 568 goto fail;
453 569
@@ -464,7 +580,7 @@ static int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
464 unsigned char *regs = priv->tda18271_regs; 580 unsigned char *regs = priv->tda18271_regs;
465 u8 val; 581 u8 val;
466 582
467 int ret = tda18271_lookup_map(GAIN_TAPER, freq, &val); 583 int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
468 if (ret < 0) 584 if (ret < 0)
469 goto fail; 585 goto fail;
470 586
@@ -481,7 +597,7 @@ static int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
481 unsigned char *regs = priv->tda18271_regs; 597 unsigned char *regs = priv->tda18271_regs;
482 u8 val; 598 u8 val;
483 599
484 int ret = tda18271_lookup_map(IR_MEASURE, freq, &val); 600 int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
485 if (ret < 0) 601 if (ret < 0)
486 goto fail; 602 goto fail;
487 603
@@ -498,7 +614,7 @@ static int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
498 unsigned char *regs = priv->tda18271_regs; 614 unsigned char *regs = priv->tda18271_regs;
499 u8 val; 615 u8 val;
500 616
501 int ret = tda18271_lookup_map(RF_CAL, freq, &val); 617 int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val);
502 if (ret < 0) 618 if (ret < 0)
503 goto fail; 619 goto fail;
504 620
@@ -507,8 +623,581 @@ fail:
507 return ret; 623 return ret;
508} 624}
509 625
510static int tda18271_tune(struct dvb_frontend *fe, 626/* ------------------------------------------------------------------ */
511 u32 ifc, u32 freq, u32 bw, u8 std) 627
628static int tda18271_channel_configuration(struct dvb_frontend *fe,
629 u32 ifc, u32 freq, u32 bw, u8 std)
630{
631 struct tda18271_priv *priv = fe->tuner_priv;
632 unsigned char *regs = priv->tda18271_regs;
633 u32 N;
634
635 /* update TV broadcast parameters */
636
637 /* set standard */
638 regs[R_EP3] &= ~0x1f; /* clear std bits */
639 regs[R_EP3] |= std;
640
641 /* set cal mode to normal */
642 regs[R_EP4] &= ~0x03;
643
644 /* update IF output level & IF notch frequency */
645 regs[R_EP4] &= ~0x1c; /* clear if level bits */
646
647 switch (priv->mode) {
648 case TDA18271_ANALOG:
649 regs[R_MPD] &= ~0x80; /* IF notch = 0 */
650 break;
651 case TDA18271_DIGITAL:
652 regs[R_EP4] |= 0x04; /* IF level = 1 */
653 regs[R_MPD] |= 0x80; /* IF notch = 1 */
654 break;
655 }
656 regs[R_EP4] &= ~0x80; /* FM_RFn: turn this bit on only for fm radio */
657
658 /* update RF_TOP / IF_TOP */
659 switch (priv->mode) {
660 case TDA18271_ANALOG:
661 regs[R_EB22] = 0x2c;
662 break;
663 case TDA18271_DIGITAL:
664 regs[R_EB22] = 0x37;
665 break;
666 }
667 tda18271_write_regs(fe, R_EB22, 1);
668
669 /* --------------------------------------------------------------- */
670
671 /* disable Power Level Indicator */
672 regs[R_EP1] |= 0x40;
673
674 /* frequency dependent parameters */
675
676 tda18271_calc_ir_measure(fe, &freq);
677
678 tda18271_calc_bp_filter(fe, &freq);
679
680 tda18271_calc_rf_band(fe, &freq);
681
682 tda18271_calc_gain_taper(fe, &freq);
683
684 /* --------------------------------------------------------------- */
685
686 /* dual tuner and agc1 extra configuration */
687
688 /* main vco when Master, cal vco when slave */
689 regs[R_EB1] |= 0x04; /* FIXME: assumes master */
690
691 /* agc1 always active */
692 regs[R_EB1] &= ~0x02;
693
694 /* agc1 has priority on agc2 */
695 regs[R_EB1] &= ~0x01;
696
697 tda18271_write_regs(fe, R_EB1, 1);
698
699 /* --------------------------------------------------------------- */
700
701 N = freq + ifc;
702
703 /* FIXME: assumes master */
704 tda18271_calc_main_pll(fe, N);
705 tda18271_write_regs(fe, R_MPD, 4);
706
707 tda18271_write_regs(fe, R_TM, 7);
708
709 /* main pll charge pump source */
710 regs[R_EB4] |= 0x20;
711 tda18271_write_regs(fe, R_EB4, 1);
712
713 msleep(1);
714
715 /* normal operation for the main pll */
716 regs[R_EB4] &= ~0x20;
717 tda18271_write_regs(fe, R_EB4, 1);
718
719 msleep(5);
720
721 return 0;
722}
723
724static int tda18271_read_thermometer(struct dvb_frontend *fe)
725{
726 struct tda18271_priv *priv = fe->tuner_priv;
727 unsigned char *regs = priv->tda18271_regs;
728 int tm;
729
730 /* switch thermometer on */
731 regs[R_TM] |= 0x10;
732 tda18271_write_regs(fe, R_TM, 1);
733
734 /* read thermometer info */
735 tda18271_read_regs(fe);
736
737 if ((((regs[R_TM] & 0x0f) == 0x00) && ((regs[R_TM] & 0x20) == 0x20)) ||
738 (((regs[R_TM] & 0x0f) == 0x08) && ((regs[R_TM] & 0x20) == 0x00))) {
739
740 if ((regs[R_TM] & 0x20) == 0x20)
741 regs[R_TM] &= ~0x20;
742 else
743 regs[R_TM] |= 0x20;
744
745 tda18271_write_regs(fe, R_TM, 1);
746
747 msleep(10); /* temperature sensing */
748
749 /* read thermometer info */
750 tda18271_read_regs(fe);
751 }
752
753 tm = tda18271_lookup_thermometer(fe);
754
755 /* switch thermometer off */
756 regs[R_TM] &= ~0x10;
757 tda18271_write_regs(fe, R_TM, 1);
758
759 /* set CAL mode to normal */
760 regs[R_EP4] &= ~0x03;
761 tda18271_write_regs(fe, R_EP4, 1);
762
763 return tm;
764}
765
766static int tda18271_rf_tracking_filters_correction(struct dvb_frontend *fe,
767 u32 freq, int tm_rfcal)
768{
769 struct tda18271_priv *priv = fe->tuner_priv;
770 struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
771 unsigned char *regs = priv->tda18271_regs;
772 int tm_current, rfcal_comp, approx, i;
773 u8 dc_over_dt, rf_tab;
774
775 /* power up */
776 regs[R_EP3] &= ~0xe0; /* sm = 0, sm_lt = 0, sm_xt = 0 */
777 tda18271_write_regs(fe, R_EP3, 1);
778
779 /* read die current temperature */
780 tm_current = tda18271_read_thermometer(fe);
781
782 /* frequency dependent parameters */
783
784 tda18271_calc_rf_cal(fe, &freq);
785 rf_tab = regs[R_EB14];
786
787 i = tda18271_lookup_rf_band(fe, &freq, NULL);
788 if (i < 0)
789 return -EINVAL;
790
791 if ((0 == map[i].rf3) || (freq / 1000 < map[i].rf2)) {
792 approx = map[i].rf_a1 *
793 (freq / 1000 - map[i].rf1) + map[i].rf_b1 + rf_tab;
794 } else {
795 approx = map[i].rf_a2 *
796 (freq / 1000 - map[i].rf2) + map[i].rf_b2 + rf_tab;
797 }
798
799 if (approx < 0)
800 approx = 0;
801 if (approx > 255)
802 approx = 255;
803
804 tda18271_lookup_map(fe, RF_CAL_DC_OVER_DT, &freq, &dc_over_dt);
805
806 /* calculate temperature compensation */
807 rfcal_comp = dc_over_dt * (tm_current - tm_rfcal);
808
809 regs[R_EB14] = approx + rfcal_comp;
810 tda18271_write_regs(fe, R_EB14, 1);
811
812 return 0;
813}
814
815static int tda18271_por(struct dvb_frontend *fe)
816{
817 struct tda18271_priv *priv = fe->tuner_priv;
818 unsigned char *regs = priv->tda18271_regs;
819
820 /* power up detector 1 */
821 regs[R_EB12] &= ~0x20;
822 tda18271_write_regs(fe, R_EB12, 1);
823
824 regs[R_EB18] &= ~0x80; /* turn agc1 loop on */
825 regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
826 tda18271_write_regs(fe, R_EB18, 1);
827
828 regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */
829
830 /* POR mode */
831 regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */
832 regs[R_EP3] |= 0x80; /* sm = 1, sm_lt = 0, sm_xt = 0 */
833 tda18271_write_regs(fe, R_EP3, 1);
834
835 /* disable 1.5 MHz low pass filter */
836 regs[R_EB23] &= ~0x04; /* forcelp_fc2_en = 0 */
837 regs[R_EB23] &= ~0x02; /* XXX: lp_fc[2] = 0 */
838 tda18271_write_regs(fe, R_EB21, 3);
839
840 return 0;
841}
842
843static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq)
844{
845 struct tda18271_priv *priv = fe->tuner_priv;
846 unsigned char *regs = priv->tda18271_regs;
847 u32 N;
848
849 /* set CAL mode to normal */
850 regs[R_EP4] &= ~0x03;
851 tda18271_write_regs(fe, R_EP4, 1);
852
853 /* switch off agc1 */
854 regs[R_EP3] |= 0x40; /* sm_lt = 1 */
855
856 regs[R_EB18] |= 0x03; /* set agc1_gain to 15 dB */
857 tda18271_write_regs(fe, R_EB18, 1);
858
859 /* frequency dependent parameters */
860
861 tda18271_calc_bp_filter(fe, &freq);
862 tda18271_calc_gain_taper(fe, &freq);
863 tda18271_calc_rf_band(fe, &freq);
864 tda18271_calc_km(fe, &freq);
865
866 tda18271_write_regs(fe, R_EP1, 3);
867 tda18271_write_regs(fe, R_EB13, 1);
868
869 /* main pll charge pump source */
870 regs[R_EB4] |= 0x20;
871 tda18271_write_regs(fe, R_EB4, 1);
872
873 /* cal pll charge pump source */
874 regs[R_EB7] |= 0x20;
875 tda18271_write_regs(fe, R_EB7, 1);
876
877 /* force dcdc converter to 0 V */
878 regs[R_EB14] = 0x00;
879 tda18271_write_regs(fe, R_EB14, 1);
880
881 /* disable plls lock */
882 regs[R_EB20] &= ~0x20;
883 tda18271_write_regs(fe, R_EB20, 1);
884
885 /* set CAL mode to RF tracking filter calibration */
886 regs[R_EP4] |= 0x03;
887 tda18271_write_regs(fe, R_EP4, 2);
888
889 /* --------------------------------------------------------------- */
890
891 /* set the internal calibration signal */
892 N = freq;
893
894 tda18271_calc_main_pll(fe, N);
895 tda18271_write_regs(fe, R_MPD, 4);
896
897 /* downconvert internal calibration */
898 N += 1000000;
899
900 tda18271_calc_main_pll(fe, N);
901 tda18271_write_regs(fe, R_MPD, 4);
902
903 msleep(5);
904
905 tda18271_write_regs(fe, R_EP2, 1);
906 tda18271_write_regs(fe, R_EP1, 1);
907 tda18271_write_regs(fe, R_EP2, 1);
908 tda18271_write_regs(fe, R_EP1, 1);
909
910 /* --------------------------------------------------------------- */
911
912 /* normal operation for the main pll */
913 regs[R_EB4] &= ~0x20;
914 tda18271_write_regs(fe, R_EB4, 1);
915
916 /* normal operation for the cal pll */
917 regs[R_EB7] &= ~0x20;
918 tda18271_write_regs(fe, R_EB7, 1);
919
920 msleep(5); /* plls locking */
921
922 /* launch the rf tracking filters calibration */
923 regs[R_EB20] |= 0x20;
924 tda18271_write_regs(fe, R_EB20, 1);
925
926 msleep(60); /* calibration */
927
928 /* --------------------------------------------------------------- */
929
930 /* set CAL mode to normal */
931 regs[R_EP4] &= ~0x03;
932
933 /* switch on agc1 */
934 regs[R_EP3] &= ~0x40; /* sm_lt = 0 */
935
936 regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
937 tda18271_write_regs(fe, R_EB18, 1);
938
939 tda18271_write_regs(fe, R_EP3, 2);
940
941 /* synchronization */
942 tda18271_write_regs(fe, R_EP1, 1);
943
944 /* get calibration result */
945 tda18271_read_extended(fe);
946
947 return regs[R_EB14];
948}
949
950static int tda18271_powerscan(struct dvb_frontend *fe,
951 u32 *freq_in, u32 *freq_out)
952{
953 struct tda18271_priv *priv = fe->tuner_priv;
954 unsigned char *regs = priv->tda18271_regs;
955 int sgn, bcal, count, wait;
956 u8 cid_target;
957 u16 count_limit;
958 u32 freq;
959
960 freq = *freq_in;
961
962 tda18271_calc_rf_band(fe, &freq);
963 tda18271_calc_rf_cal(fe, &freq);
964 tda18271_calc_gain_taper(fe, &freq);
965 tda18271_lookup_cid_target(fe, &freq, &cid_target, &count_limit);
966
967 tda18271_write_regs(fe, R_EP2, 1);
968 tda18271_write_regs(fe, R_EB14, 1);
969
970 /* downconvert frequency */
971 freq += 1000000;
972
973 tda18271_calc_main_pll(fe, freq);
974 tda18271_write_regs(fe, R_MPD, 4);
975
976 msleep(5); /* pll locking */
977
978 /* detection mode */
979 regs[R_EP4] &= ~0x03;
980 regs[R_EP4] |= 0x01;
981 tda18271_write_regs(fe, R_EP4, 1);
982
983 /* launch power detection measurement */
984 tda18271_write_regs(fe, R_EP2, 1);
985
986 /* read power detection info, stored in EB10 */
987 tda18271_read_extended(fe);
988
989 /* algorithm initialization */
990 sgn = 1;
991 *freq_out = *freq_in;
992 bcal = 0;
993 count = 0;
994 wait = false;
995
996 while ((regs[R_EB10] & 0x3f) < cid_target) {
997 /* downconvert updated freq to 1 MHz */
998 freq = *freq_in + (sgn * count) + 1000000;
999
1000 tda18271_calc_main_pll(fe, freq);
1001 tda18271_write_regs(fe, R_MPD, 4);
1002
1003 if (wait) {
1004 msleep(5); /* pll locking */
1005 wait = false;
1006 } else
1007 udelay(100); /* pll locking */
1008
1009 /* launch power detection measurement */
1010 tda18271_write_regs(fe, R_EP2, 1);
1011
1012 /* read power detection info, stored in EB10 */
1013 tda18271_read_extended(fe);
1014
1015 count += 200;
1016
1017 if (count < count_limit)
1018 continue;
1019
1020 if (sgn <= 0)
1021 break;
1022
1023 sgn = -1 * sgn;
1024 count = 200;
1025 wait = true;
1026 }
1027
1028 if ((regs[R_EB10] & 0x3f) >= cid_target) {
1029 bcal = 1;
1030 *freq_out = freq - 1000000;
1031 } else
1032 bcal = 0;
1033
1034 tda_dbg("bcal = %d, freq_in = %d, freq_out = %d (freq = %d)\n",
1035 bcal, *freq_in, *freq_out, freq);
1036
1037 return bcal;
1038}
1039
1040static int tda18271_powerscan_init(struct dvb_frontend *fe)
1041{
1042 struct tda18271_priv *priv = fe->tuner_priv;
1043 unsigned char *regs = priv->tda18271_regs;
1044
1045 /* set standard to digital */
1046 regs[R_EP3] &= ~0x1f; /* clear std bits */
1047 regs[R_EP3] |= 0x12;
1048
1049 /* set cal mode to normal */
1050 regs[R_EP4] &= ~0x03;
1051
1052 /* update IF output level & IF notch frequency */
1053 regs[R_EP4] &= ~0x1c; /* clear if level bits */
1054
1055 tda18271_write_regs(fe, R_EP3, 2);
1056
1057 regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
1058 tda18271_write_regs(fe, R_EB18, 1);
1059
1060 regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */
1061
1062 /* 1.5 MHz low pass filter */
1063 regs[R_EB23] |= 0x04; /* forcelp_fc2_en = 1 */
1064 regs[R_EB23] |= 0x02; /* lp_fc[2] = 1 */
1065
1066 tda18271_write_regs(fe, R_EB21, 3);
1067
1068 return 0;
1069}
1070
1071static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq)
1072{
1073 struct tda18271_priv *priv = fe->tuner_priv;
1074 struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
1075 unsigned char *regs = priv->tda18271_regs;
1076 int bcal, rf, i;
1077#define RF1 0
1078#define RF2 1
1079#define RF3 2
1080 u32 rf_default[3];
1081 u32 rf_freq[3];
1082 u8 prog_cal[3];
1083 u8 prog_tab[3];
1084
1085 i = tda18271_lookup_rf_band(fe, &freq, NULL);
1086
1087 if (i < 0)
1088 return i;
1089
1090 rf_default[RF1] = 1000 * map[i].rf1_def;
1091 rf_default[RF2] = 1000 * map[i].rf2_def;
1092 rf_default[RF3] = 1000 * map[i].rf3_def;
1093
1094 for (rf = RF1; rf <= RF3; rf++) {
1095 if (0 == rf_default[rf])
1096 return 0;
1097 tda_dbg("freq = %d, rf = %d\n", freq, rf);
1098
1099 /* look for optimized calibration frequency */
1100 bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]);
1101
1102 tda18271_calc_rf_cal(fe, &rf_freq[rf]);
1103 prog_tab[rf] = regs[R_EB14];
1104
1105 if (1 == bcal)
1106 prog_cal[rf] = tda18271_calibrate_rf(fe, rf_freq[rf]);
1107 else
1108 prog_cal[rf] = prog_tab[rf];
1109
1110 switch (rf) {
1111 case RF1:
1112 map[i].rf_a1 = 0;
1113 map[i].rf_b1 = prog_cal[RF1] - prog_tab[RF1];
1114 map[i].rf1 = rf_freq[RF1] / 1000;
1115 break;
1116 case RF2:
1117 map[i].rf_a1 = (prog_cal[RF2] - prog_tab[RF2] -
1118 prog_cal[RF1] + prog_tab[RF1]) /
1119 ((rf_freq[RF2] - rf_freq[RF1]) / 1000);
1120 map[i].rf2 = rf_freq[RF2] / 1000;
1121 break;
1122 case RF3:
1123 map[i].rf_a2 = (prog_cal[RF3] - prog_tab[RF3] -
1124 prog_cal[RF2] + prog_tab[RF2]) /
1125 ((rf_freq[RF3] - rf_freq[RF2]) / 1000);
1126 map[i].rf_b2 = prog_cal[RF2] - prog_tab[RF2];
1127 map[i].rf3 = rf_freq[RF3] / 1000;
1128 break;
1129 default:
1130 BUG();
1131 }
1132 }
1133
1134 return 0;
1135}
1136
1137static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe,
1138 int *tm_rfcal)
1139{
1140 struct tda18271_priv *priv = fe->tuner_priv;
1141 unsigned int i;
1142
1143 tda_info("tda18271: performing RF tracking filter calibration\n");
1144
1145 /* wait for die temperature stabilization */
1146 msleep(200);
1147
1148 tda18271_powerscan_init(fe);
1149
1150 /* rf band calibration */
1151 for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++)
1152 tda18271_rf_tracking_filters_init(fe, 1000 *
1153 priv->rf_cal_state[i].rfmax);
1154
1155 *tm_rfcal = tda18271_read_thermometer(fe);
1156
1157 return 0;
1158}
1159
1160/* ------------------------------------------------------------------ */
1161
1162static int tda18271_init_cal(struct dvb_frontend *fe, int *tm)
1163{
1164 struct tda18271_priv *priv = fe->tuner_priv;
1165
1166 if (priv->cal_initialized)
1167 return 0;
1168
1169 /* initialization */
1170 tda18271_init(fe);
1171
1172 tda18271_calc_rf_filter_curve(fe, tm);
1173
1174 tda18271_por(fe);
1175
1176 priv->cal_initialized = true;
1177
1178 return 0;
1179}
1180
1181static int tda18271c2_tune(struct dvb_frontend *fe,
1182 u32 ifc, u32 freq, u32 bw, u8 std)
1183{
1184 int tm = 0;
1185
1186 tda_dbg("freq = %d, ifc = %d\n", freq, ifc);
1187
1188 tda18271_init_cal(fe, &tm);
1189
1190 tda18271_rf_tracking_filters_correction(fe, freq, tm);
1191
1192 tda18271_channel_configuration(fe, ifc, freq, bw, std);
1193
1194 return 0;
1195}
1196
1197/* ------------------------------------------------------------------ */
1198
1199static int tda18271c1_tune(struct dvb_frontend *fe,
1200 u32 ifc, u32 freq, u32 bw, u8 std)
512{ 1201{
513 struct tda18271_priv *priv = fe->tuner_priv; 1202 struct tda18271_priv *priv = fe->tuner_priv;
514 unsigned char *regs = priv->tda18271_regs; 1203 unsigned char *regs = priv->tda18271_regs;
@@ -520,7 +1209,7 @@ static int tda18271_tune(struct dvb_frontend *fe,
520 1209
521 /* RF tracking filter calibration */ 1210 /* RF tracking filter calibration */
522 1211
523 /* calculate BP_Filter */ 1212 /* calculate bp filter */
524 tda18271_calc_bp_filter(fe, &freq); 1213 tda18271_calc_bp_filter(fe, &freq);
525 tda18271_write_regs(fe, R_EP1, 1); 1214 tda18271_write_regs(fe, R_EP1, 1);
526 1215
@@ -537,10 +1226,10 @@ static int tda18271_tune(struct dvb_frontend *fe,
537 regs[R_EB20] = 0xcc; 1226 regs[R_EB20] = 0xcc;
538 tda18271_write_regs(fe, R_EB20, 1); 1227 tda18271_write_regs(fe, R_EB20, 1);
539 1228
540 /* set CAL mode to RF tracking filter calibration */ 1229 /* set cal mode to RF tracking filter calibration */
541 regs[R_EP4] |= 0x03; 1230 regs[R_EP4] |= 0x03;
542 1231
543 /* calculate CAL PLL */ 1232 /* calculate cal pll */
544 1233
545 switch (priv->mode) { 1234 switch (priv->mode) {
546 case TDA18271_ANALOG: 1235 case TDA18271_ANALOG:
@@ -553,7 +1242,7 @@ static int tda18271_tune(struct dvb_frontend *fe,
553 1242
554 tda18271_calc_cal_pll(fe, N); 1243 tda18271_calc_cal_pll(fe, N);
555 1244
556 /* calculate MAIN PLL */ 1245 /* calculate main pll */
557 1246
558 switch (priv->mode) { 1247 switch (priv->mode) {
559 case TDA18271_ANALOG: 1248 case TDA18271_ANALOG:
@@ -569,14 +1258,14 @@ static int tda18271_tune(struct dvb_frontend *fe,
569 tda18271_write_regs(fe, R_EP3, 11); 1258 tda18271_write_regs(fe, R_EP3, 11);
570 msleep(5); /* RF tracking filter calibration initialization */ 1259 msleep(5); /* RF tracking filter calibration initialization */
571 1260
572 /* search for K,M,CO for RF Calibration */ 1261 /* search for K,M,CO for RF calibration */
573 tda18271_calc_km(fe, &freq); 1262 tda18271_calc_km(fe, &freq);
574 tda18271_write_regs(fe, R_EB13, 1); 1263 tda18271_write_regs(fe, R_EB13, 1);
575 1264
576 /* search for RF_BAND */ 1265 /* search for rf band */
577 tda18271_calc_rf_band(fe, &freq); 1266 tda18271_calc_rf_band(fe, &freq);
578 1267
579 /* search for Gain_Taper */ 1268 /* search for gain taper */
580 tda18271_calc_gain_taper(fe, &freq); 1269 tda18271_calc_gain_taper(fe, &freq);
581 1270
582 tda18271_write_regs(fe, R_EP2, 1); 1271 tda18271_write_regs(fe, R_EP2, 1);
@@ -660,10 +1349,13 @@ static int tda18271_set_params(struct dvb_frontend *fe,
660 struct dvb_frontend_parameters *params) 1349 struct dvb_frontend_parameters *params)
661{ 1350{
662 struct tda18271_priv *priv = fe->tuner_priv; 1351 struct tda18271_priv *priv = fe->tuner_priv;
1352 struct tda18271_std_map *std_map = priv->std;
663 u8 std; 1353 u8 std;
664 u32 bw, sgIF = 0; 1354 u32 bw, sgIF = 0;
665 u32 freq = params->frequency; 1355 u32 freq = params->frequency;
666 1356
1357 BUG_ON(!priv->tune || !priv->std);
1358
667 priv->mode = TDA18271_DIGITAL; 1359 priv->mode = TDA18271_DIGITAL;
668 1360
669 /* see table 22 */ 1361 /* see table 22 */
@@ -671,13 +1363,13 @@ static int tda18271_set_params(struct dvb_frontend *fe,
671 switch (params->u.vsb.modulation) { 1363 switch (params->u.vsb.modulation) {
672 case VSB_8: 1364 case VSB_8:
673 case VSB_16: 1365 case VSB_16:
674 std = 0x1b; /* device-specific (spec says 0x1c) */ 1366 std = std_map->atsc_6.std_bits;
675 sgIF = 5380000; 1367 sgIF = std_map->atsc_6.if_freq;
676 break; 1368 break;
677 case QAM_64: 1369 case QAM_64:
678 case QAM_256: 1370 case QAM_256:
679 std = 0x18; /* device-specific (spec says 0x1d) */ 1371 std = std_map->qam_6.std_bits;
680 sgIF = 4000000; 1372 sgIF = std_map->qam_6.if_freq;
681 break; 1373 break;
682 default: 1374 default:
683 tda_warn("modulation not set!\n"); 1375 tda_warn("modulation not set!\n");
@@ -691,19 +1383,19 @@ static int tda18271_set_params(struct dvb_frontend *fe,
691 } else if (fe->ops.info.type == FE_OFDM) { 1383 } else if (fe->ops.info.type == FE_OFDM) {
692 switch (params->u.ofdm.bandwidth) { 1384 switch (params->u.ofdm.bandwidth) {
693 case BANDWIDTH_6_MHZ: 1385 case BANDWIDTH_6_MHZ:
694 std = 0x1b; /* device-specific (spec says 0x1c) */
695 bw = 6000000; 1386 bw = 6000000;
696 sgIF = 3300000; 1387 std = std_map->dvbt_6.std_bits;
1388 sgIF = std_map->dvbt_6.if_freq;
697 break; 1389 break;
698 case BANDWIDTH_7_MHZ: 1390 case BANDWIDTH_7_MHZ:
699 std = 0x19; /* device-specific (spec says 0x1d) */
700 bw = 7000000; 1391 bw = 7000000;
701 sgIF = 3800000; 1392 std = std_map->dvbt_7.std_bits;
1393 sgIF = std_map->dvbt_7.if_freq;
702 break; 1394 break;
703 case BANDWIDTH_8_MHZ: 1395 case BANDWIDTH_8_MHZ:
704 std = 0x1a; /* device-specific (spec says 0x1e) */
705 bw = 8000000; 1396 bw = 8000000;
706 sgIF = 4300000; 1397 std = std_map->dvbt_8.std_bits;
1398 sgIF = std_map->dvbt_8.if_freq;
707 break; 1399 break;
708 default: 1400 default:
709 tda_warn("bandwidth not set!\n"); 1401 tda_warn("bandwidth not set!\n");
@@ -714,57 +1406,59 @@ static int tda18271_set_params(struct dvb_frontend *fe,
714 return -EINVAL; 1406 return -EINVAL;
715 } 1407 }
716 1408
717 return tda18271_tune(fe, sgIF, freq, bw, std); 1409 return priv->tune(fe, sgIF, freq, bw, std);
718} 1410}
719 1411
720static int tda18271_set_analog_params(struct dvb_frontend *fe, 1412static int tda18271_set_analog_params(struct dvb_frontend *fe,
721 struct analog_parameters *params) 1413 struct analog_parameters *params)
722{ 1414{
723 struct tda18271_priv *priv = fe->tuner_priv; 1415 struct tda18271_priv *priv = fe->tuner_priv;
1416 struct tda18271_std_map *std_map = priv->std;
724 char *mode; 1417 char *mode;
725 u8 std; 1418 u8 std;
726 u32 sgIF, freq = params->frequency * 62500; 1419 u32 sgIF, freq = params->frequency * 62500;
727 1420
1421 BUG_ON(!priv->tune || !priv->std);
1422
728 priv->mode = TDA18271_ANALOG; 1423 priv->mode = TDA18271_ANALOG;
729 1424
730 /* see table 22 */
731 if (params->std & V4L2_STD_MN) { 1425 if (params->std & V4L2_STD_MN) {
732 std = 0x0d; 1426 std = std_map->atv_mn.std_bits;
733 sgIF = 5750000; 1427 sgIF = std_map->atv_mn.if_freq;
734 mode = "MN"; 1428 mode = "MN";
735 } else if (params->std & V4L2_STD_B) { 1429 } else if (params->std & V4L2_STD_B) {
736 std = 0x0e; 1430 std = std_map->atv_b.std_bits;
737 sgIF = 6750000; 1431 sgIF = std_map->atv_b.if_freq;
738 mode = "B"; 1432 mode = "B";
739 } else if (params->std & V4L2_STD_GH) { 1433 } else if (params->std & V4L2_STD_GH) {
740 std = 0x0f; 1434 std = std_map->atv_gh.std_bits;
741 sgIF = 7750000; 1435 sgIF = std_map->atv_gh.if_freq;
742 mode = "GH"; 1436 mode = "GH";
743 } else if (params->std & V4L2_STD_PAL_I) { 1437 } else if (params->std & V4L2_STD_PAL_I) {
744 std = 0x0f; 1438 std = std_map->atv_i.std_bits;
745 sgIF = 7750000; 1439 sgIF = std_map->atv_i.if_freq;
746 mode = "I"; 1440 mode = "I";
747 } else if (params->std & V4L2_STD_DK) { 1441 } else if (params->std & V4L2_STD_DK) {
748 std = 0x0f; 1442 std = std_map->atv_dk.std_bits;
749 sgIF = 7750000; 1443 sgIF = std_map->atv_dk.if_freq;
750 mode = "DK"; 1444 mode = "DK";
751 } else if (params->std & V4L2_STD_SECAM_L) { 1445 } else if (params->std & V4L2_STD_SECAM_L) {
752 std = 0x0f; 1446 std = std_map->atv_l.std_bits;
753 sgIF = 7750000; 1447 sgIF = std_map->atv_l.if_freq;
754 mode = "L"; 1448 mode = "L";
755 } else if (params->std & V4L2_STD_SECAM_LC) { 1449 } else if (params->std & V4L2_STD_SECAM_LC) {
756 std = 0x0f; 1450 std = std_map->atv_lc.std_bits;
757 sgIF = 1250000; 1451 sgIF = std_map->atv_lc.if_freq;
758 mode = "L'"; 1452 mode = "L'";
759 } else { 1453 } else {
760 std = 0x0f; 1454 std = std_map->atv_i.std_bits;
761 sgIF = 7750000; 1455 sgIF = std_map->atv_i.if_freq;
762 mode = "xx"; 1456 mode = "xx";
763 } 1457 }
764 1458
765 tda_dbg("setting tda18271 to system %s\n", mode); 1459 tda_dbg("setting tda18271 to system %s\n", mode);
766 1460
767 return tda18271_tune(fe, sgIF, freq, 0, std); 1461 return priv->tune(fe, sgIF, freq, 0, std);
768} 1462}
769 1463
770static int tda18271_release(struct dvb_frontend *fe) 1464static int tda18271_release(struct dvb_frontend *fe)
@@ -800,10 +1494,13 @@ static int tda18271_get_id(struct dvb_frontend *fe)
800 switch (regs[R_ID] & 0x7f) { 1494 switch (regs[R_ID] & 0x7f) {
801 case 3: 1495 case 3:
802 name = "TDA18271HD/C1"; 1496 name = "TDA18271HD/C1";
1497 priv->id = TDA18271HDC1;
1498 priv->tune = tda18271c1_tune;
803 break; 1499 break;
804 case 4: 1500 case 4:
805 name = "TDA18271HD/C2"; 1501 name = "TDA18271HD/C2";
806 ret = -EPROTONOSUPPORT; 1502 priv->id = TDA18271HDC2;
1503 priv->tune = tda18271c2_tune;
807 break; 1504 break;
808 default: 1505 default:
809 name = "Unknown device"; 1506 name = "Unknown device";
@@ -846,12 +1543,16 @@ struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
846 priv->i2c_addr = addr; 1543 priv->i2c_addr = addr;
847 priv->i2c_adap = i2c; 1544 priv->i2c_adap = i2c;
848 priv->gate = gate; 1545 priv->gate = gate;
1546 priv->cal_initialized = false;
849 1547
850 fe->tuner_priv = priv; 1548 fe->tuner_priv = priv;
851 1549
852 if (tda18271_get_id(fe) < 0) 1550 if (tda18271_get_id(fe) < 0)
853 goto fail; 1551 goto fail;
854 1552
1553 if (tda18271_assign_map_layout(fe) < 0)
1554 goto fail;
1555
855 memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops, 1556 memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
856 sizeof(struct dvb_tuner_ops)); 1557 sizeof(struct dvb_tuner_ops));
857 1558
@@ -866,7 +1567,7 @@ EXPORT_SYMBOL_GPL(tda18271_attach);
866MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver"); 1567MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
867MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>"); 1568MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
868MODULE_LICENSE("GPL"); 1569MODULE_LICENSE("GPL");
869MODULE_VERSION("0.1"); 1570MODULE_VERSION("0.2");
870 1571
871/* 1572/*
872 * Overrides for Emacs so that we follow Linus's tabbing style. 1573 * Overrides for Emacs so that we follow Linus's tabbing style.
diff --git a/drivers/media/dvb/frontends/tda18271-priv.h b/drivers/media/dvb/frontends/tda18271-priv.h
index 912b81e0c765..8552c6ae0d1f 100644
--- a/drivers/media/dvb/frontends/tda18271-priv.h
+++ b/drivers/media/dvb/frontends/tda18271-priv.h
@@ -69,11 +69,54 @@
69 69
70/*---------------------------------------------------------------------*/ 70/*---------------------------------------------------------------------*/
71 71
72struct tda18271_rf_tracking_filter_cal {
73 u32 rfmax;
74 u8 rfband;
75 u32 rf1_def;
76 u32 rf2_def;
77 u32 rf3_def;
78 u32 rf1;
79 u32 rf2;
80 u32 rf3;
81 int rf_a1;
82 int rf_b1;
83 int rf_a2;
84 int rf_b2;
85};
86
87struct tda18271_std_map_item {
88 u32 if_freq;
89 u8 std_bits;
90};
91
92struct tda18271_std_map {
93 struct tda18271_std_map_item atv_b;
94 struct tda18271_std_map_item atv_dk;
95 struct tda18271_std_map_item atv_gh;
96 struct tda18271_std_map_item atv_i;
97 struct tda18271_std_map_item atv_l;
98 struct tda18271_std_map_item atv_lc;
99 struct tda18271_std_map_item atv_mn;
100 struct tda18271_std_map_item atsc_6;
101 struct tda18271_std_map_item dvbt_6;
102 struct tda18271_std_map_item dvbt_7;
103 struct tda18271_std_map_item dvbt_8;
104 struct tda18271_std_map_item qam_6;
105 struct tda18271_std_map_item qam_8;
106};
107
72enum tda18271_mode { 108enum tda18271_mode {
73 TDA18271_ANALOG, 109 TDA18271_ANALOG,
74 TDA18271_DIGITAL, 110 TDA18271_DIGITAL,
75}; 111};
76 112
113struct tda18271_map_layout;
114
115enum tda18271_ver {
116 TDA18271HDC1,
117 TDA18271HDC2,
118};
119
77struct tda18271_priv { 120struct tda18271_priv {
78 u8 i2c_addr; 121 u8 i2c_addr;
79 struct i2c_adapter *i2c_adap; 122 struct i2c_adapter *i2c_adap;
@@ -81,6 +124,16 @@ struct tda18271_priv {
81 124
82 enum tda18271_mode mode; 125 enum tda18271_mode mode;
83 enum tda18271_i2c_gate gate; 126 enum tda18271_i2c_gate gate;
127 enum tda18271_ver id;
128
129 unsigned int cal_initialized:1;
130
131 struct tda18271_std_map *std;
132 struct tda18271_map_layout *maps;
133 struct tda18271_rf_tracking_filter_cal rf_cal_state[8];
134
135 int (*tune) (struct dvb_frontend *fe,
136 u32 ifc, u32 freq, u32 bw, u8 std);
84 137
85 u32 frequency; 138 u32 frequency;
86 u32 bandwidth; 139 u32 bandwidth;
@@ -93,6 +146,7 @@ extern int tda18271_debug;
93#define DBG_INFO 1 146#define DBG_INFO 1
94#define DBG_MAP 2 147#define DBG_MAP 2
95#define DBG_REG 4 148#define DBG_REG 4
149#define DBG_ADV 8
96 150
97#define tda_printk(kern, fmt, arg...) \ 151#define tda_printk(kern, fmt, arg...) \
98 printk(kern "%s: " fmt, __FUNCTION__, ##arg) 152 printk(kern "%s: " fmt, __FUNCTION__, ##arg)
@@ -117,17 +171,31 @@ enum tda18271_map_type {
117 /* tda18271_map */ 171 /* tda18271_map */
118 RF_CAL, 172 RF_CAL,
119 RF_CAL_KMCO, 173 RF_CAL_KMCO,
174 RF_CAL_DC_OVER_DT,
120 BP_FILTER, 175 BP_FILTER,
121 RF_BAND, 176 RF_BAND,
122 GAIN_TAPER, 177 GAIN_TAPER,
123 IR_MEASURE, 178 IR_MEASURE,
124}; 179};
125 180
126extern int tda18271_lookup_pll_map(enum tda18271_map_type map_type, 181extern int tda18271_lookup_pll_map(struct dvb_frontend *fe,
182 enum tda18271_map_type map_type,
127 u32 *freq, u8 *post_div, u8 *div); 183 u32 *freq, u8 *post_div, u8 *div);
128extern int tda18271_lookup_map(enum tda18271_map_type map_type, 184extern int tda18271_lookup_map(struct dvb_frontend *fe,
185 enum tda18271_map_type map_type,
129 u32 *freq, u8 *val); 186 u32 *freq, u8 *val);
130 187
188extern int tda18271_lookup_thermometer(struct dvb_frontend *fe);
189
190extern int tda18271_lookup_rf_band(struct dvb_frontend *fe,
191 u32 *freq, u8 *rf_band);
192
193extern int tda18271_lookup_cid_target(struct dvb_frontend *fe,
194 u32 *freq, u8 *cid_target,
195 u16 *count_limit);
196
197extern int tda18271_assign_map_layout(struct dvb_frontend *fe);
198
131#endif /* __TDA18271_PRIV_H__ */ 199#endif /* __TDA18271_PRIV_H__ */
132 200
133/* 201/*
diff --git a/drivers/media/dvb/frontends/tda18271-tables.c b/drivers/media/dvb/frontends/tda18271-tables.c
index f8202c40b046..3042e5c873ef 100644
--- a/drivers/media/dvb/frontends/tda18271-tables.c
+++ b/drivers/media/dvb/frontends/tda18271-tables.c
@@ -33,7 +33,7 @@ struct tda18271_map {
33 33
34/*---------------------------------------------------------------------*/ 34/*---------------------------------------------------------------------*/
35 35
36static struct tda18271_pll_map tda18271_main_pll[] = { 36static struct tda18271_pll_map tda18271c1_main_pll[] = {
37 { .lomax = 32000, .pd = 0x5f, .d = 0xf0 }, 37 { .lomax = 32000, .pd = 0x5f, .d = 0xf0 },
38 { .lomax = 35000, .pd = 0x5e, .d = 0xe0 }, 38 { .lomax = 35000, .pd = 0x5e, .d = 0xe0 },
39 { .lomax = 37000, .pd = 0x5d, .d = 0xd0 }, 39 { .lomax = 37000, .pd = 0x5d, .d = 0xd0 },
@@ -77,7 +77,51 @@ static struct tda18271_pll_map tda18271_main_pll[] = {
77 { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */ 77 { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */
78}; 78};
79 79
80static struct tda18271_pll_map tda18271_cal_pll[] = { 80static struct tda18271_pll_map tda18271c2_main_pll[] = {
81 { .lomax = 33125, .pd = 0x57, .d = 0xf0 },
82 { .lomax = 35500, .pd = 0x56, .d = 0xe0 },
83 { .lomax = 38188, .pd = 0x55, .d = 0xd0 },
84 { .lomax = 41375, .pd = 0x54, .d = 0xc0 },
85 { .lomax = 45125, .pd = 0x53, .d = 0xb0 },
86 { .lomax = 49688, .pd = 0x52, .d = 0xa0 },
87 { .lomax = 55188, .pd = 0x51, .d = 0x90 },
88 { .lomax = 62125, .pd = 0x50, .d = 0x80 },
89 { .lomax = 66250, .pd = 0x47, .d = 0x78 },
90 { .lomax = 71000, .pd = 0x46, .d = 0x70 },
91 { .lomax = 76375, .pd = 0x45, .d = 0x68 },
92 { .lomax = 82750, .pd = 0x44, .d = 0x60 },
93 { .lomax = 90250, .pd = 0x43, .d = 0x58 },
94 { .lomax = 99375, .pd = 0x42, .d = 0x50 },
95 { .lomax = 110375, .pd = 0x41, .d = 0x48 },
96 { .lomax = 124250, .pd = 0x40, .d = 0x40 },
97 { .lomax = 132500, .pd = 0x37, .d = 0x3c },
98 { .lomax = 142000, .pd = 0x36, .d = 0x38 },
99 { .lomax = 152750, .pd = 0x35, .d = 0x34 },
100 { .lomax = 165500, .pd = 0x34, .d = 0x30 },
101 { .lomax = 180500, .pd = 0x33, .d = 0x2c },
102 { .lomax = 198750, .pd = 0x32, .d = 0x28 },
103 { .lomax = 220750, .pd = 0x31, .d = 0x24 },
104 { .lomax = 248500, .pd = 0x30, .d = 0x20 },
105 { .lomax = 265000, .pd = 0x27, .d = 0x1e },
106 { .lomax = 284000, .pd = 0x26, .d = 0x1c },
107 { .lomax = 305500, .pd = 0x25, .d = 0x1a },
108 { .lomax = 331000, .pd = 0x24, .d = 0x18 },
109 { .lomax = 361000, .pd = 0x23, .d = 0x16 },
110 { .lomax = 397500, .pd = 0x22, .d = 0x14 },
111 { .lomax = 441500, .pd = 0x21, .d = 0x12 },
112 { .lomax = 497000, .pd = 0x20, .d = 0x10 },
113 { .lomax = 530000, .pd = 0x17, .d = 0x0f },
114 { .lomax = 568000, .pd = 0x16, .d = 0x0e },
115 { .lomax = 611000, .pd = 0x15, .d = 0x0d },
116 { .lomax = 662000, .pd = 0x14, .d = 0x0c },
117 { .lomax = 722000, .pd = 0x13, .d = 0x0b },
118 { .lomax = 795000, .pd = 0x12, .d = 0x0a },
119 { .lomax = 883000, .pd = 0x11, .d = 0x09 },
120 { .lomax = 994000, .pd = 0x10, .d = 0x08 },
121 { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */
122};
123
124static struct tda18271_pll_map tda18271c1_cal_pll[] = {
81 { .lomax = 33000, .pd = 0xdd, .d = 0xd0 }, 125 { .lomax = 33000, .pd = 0xdd, .d = 0xd0 },
82 { .lomax = 36000, .pd = 0xdc, .d = 0xc0 }, 126 { .lomax = 36000, .pd = 0xdc, .d = 0xc0 },
83 { .lomax = 40000, .pd = 0xdb, .d = 0xb0 }, 127 { .lomax = 40000, .pd = 0xdb, .d = 0xb0 },
@@ -116,6 +160,44 @@ static struct tda18271_pll_map tda18271_cal_pll[] = {
116 { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */ 160 { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */
117}; 161};
118 162
163static struct tda18271_pll_map tda18271c2_cal_pll[] = {
164 { .lomax = 33813, .pd = 0xdd, .d = 0xd0 },
165 { .lomax = 36625, .pd = 0xdc, .d = 0xc0 },
166 { .lomax = 39938, .pd = 0xdb, .d = 0xb0 },
167 { .lomax = 43938, .pd = 0xda, .d = 0xa0 },
168 { .lomax = 48813, .pd = 0xd9, .d = 0x90 },
169 { .lomax = 54938, .pd = 0xd8, .d = 0x80 },
170 { .lomax = 62813, .pd = 0xd3, .d = 0x70 },
171 { .lomax = 67625, .pd = 0xcd, .d = 0x68 },
172 { .lomax = 73250, .pd = 0xcc, .d = 0x60 },
173 { .lomax = 79875, .pd = 0xcb, .d = 0x58 },
174 { .lomax = 87875, .pd = 0xca, .d = 0x50 },
175 { .lomax = 97625, .pd = 0xc9, .d = 0x48 },
176 { .lomax = 109875, .pd = 0xc8, .d = 0x40 },
177 { .lomax = 125625, .pd = 0xc3, .d = 0x38 },
178 { .lomax = 135250, .pd = 0xbd, .d = 0x34 },
179 { .lomax = 146500, .pd = 0xbc, .d = 0x30 },
180 { .lomax = 159750, .pd = 0xbb, .d = 0x2c },
181 { .lomax = 175750, .pd = 0xba, .d = 0x28 },
182 { .lomax = 195250, .pd = 0xb9, .d = 0x24 },
183 { .lomax = 219750, .pd = 0xb8, .d = 0x20 },
184 { .lomax = 251250, .pd = 0xb3, .d = 0x1c },
185 { .lomax = 270500, .pd = 0xad, .d = 0x1a },
186 { .lomax = 293000, .pd = 0xac, .d = 0x18 },
187 { .lomax = 319500, .pd = 0xab, .d = 0x16 },
188 { .lomax = 351500, .pd = 0xaa, .d = 0x14 },
189 { .lomax = 390500, .pd = 0xa9, .d = 0x12 },
190 { .lomax = 439500, .pd = 0xa8, .d = 0x10 },
191 { .lomax = 502500, .pd = 0xa3, .d = 0x0e },
192 { .lomax = 541000, .pd = 0x9d, .d = 0x0d },
193 { .lomax = 586000, .pd = 0x9c, .d = 0x0c },
194 { .lomax = 639000, .pd = 0x9b, .d = 0x0b },
195 { .lomax = 703000, .pd = 0x9a, .d = 0x0a },
196 { .lomax = 781000, .pd = 0x99, .d = 0x09 },
197 { .lomax = 879000, .pd = 0x98, .d = 0x08 },
198 { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */
199};
200
119static struct tda18271_map tda18271_bp_filter[] = { 201static struct tda18271_map tda18271_bp_filter[] = {
120 { .rfmax = 62000, .val = 0x00 }, 202 { .rfmax = 62000, .val = 0x00 },
121 { .rfmax = 84000, .val = 0x01 }, 203 { .rfmax = 84000, .val = 0x01 },
@@ -127,7 +209,7 @@ static struct tda18271_map tda18271_bp_filter[] = {
127 { .rfmax = 0, .val = 0x00 }, /* end */ 209 { .rfmax = 0, .val = 0x00 }, /* end */
128}; 210};
129 211
130static struct tda18271_map tda18271_km[] = { 212static struct tda18271_map tda18271c1_km[] = {
131 { .rfmax = 61100, .val = 0x74 }, 213 { .rfmax = 61100, .val = 0x74 },
132 { .rfmax = 350000, .val = 0x40 }, 214 { .rfmax = 350000, .val = 0x40 },
133 { .rfmax = 720000, .val = 0x30 }, 215 { .rfmax = 720000, .val = 0x30 },
@@ -135,6 +217,15 @@ static struct tda18271_map tda18271_km[] = {
135 { .rfmax = 0, .val = 0x00 }, /* end */ 217 { .rfmax = 0, .val = 0x00 }, /* end */
136}; 218};
137 219
220static struct tda18271_map tda18271c2_km[] = {
221 { .rfmax = 47900, .val = 0x38 },
222 { .rfmax = 61100, .val = 0x44 },
223 { .rfmax = 350000, .val = 0x30 },
224 { .rfmax = 720000, .val = 0x24 },
225 { .rfmax = 865000, .val = 0x3c },
226 { .rfmax = 0, .val = 0x00 }, /* end */
227};
228
138static struct tda18271_map tda18271_rf_band[] = { 229static struct tda18271_map tda18271_rf_band[] = {
139 { .rfmax = 47900, .val = 0x00 }, 230 { .rfmax = 47900, .val = 0x00 },
140 { .rfmax = 61100, .val = 0x01 }, 231 { .rfmax = 61100, .val = 0x01 },
@@ -236,7 +327,7 @@ static struct tda18271_map tda18271_gain_taper[] = {
236 { .rfmax = 0, .val = 0x00 }, /* end */ 327 { .rfmax = 0, .val = 0x00 }, /* end */
237}; 328};
238 329
239static struct tda18271_map tda18271_rf_cal[] = { 330static struct tda18271_map tda18271c1_rf_cal[] = {
240 { .rfmax = 41000, .val = 0x1e }, 331 { .rfmax = 41000, .val = 0x1e },
241 { .rfmax = 43000, .val = 0x30 }, 332 { .rfmax = 43000, .val = 0x30 },
242 { .rfmax = 45000, .val = 0x43 }, 333 { .rfmax = 45000, .val = 0x43 },
@@ -257,6 +348,446 @@ static struct tda18271_map tda18271_rf_cal[] = {
257 { .rfmax = 0, .val = 0x00 }, /* end */ 348 { .rfmax = 0, .val = 0x00 }, /* end */
258}; 349};
259 350
351static struct tda18271_map tda18271c2_rf_cal[] = {
352 { .rfmax = 41000, .val = 0x0f },
353 { .rfmax = 43000, .val = 0x1c },
354 { .rfmax = 45000, .val = 0x2f },
355 { .rfmax = 46000, .val = 0x39 },
356 { .rfmax = 47000, .val = 0x40 },
357 { .rfmax = 47900, .val = 0x50 },
358 { .rfmax = 49100, .val = 0x16 },
359 { .rfmax = 50000, .val = 0x18 },
360 { .rfmax = 51000, .val = 0x20 },
361 { .rfmax = 53000, .val = 0x28 },
362 { .rfmax = 55000, .val = 0x2b },
363 { .rfmax = 56000, .val = 0x32 },
364 { .rfmax = 57000, .val = 0x35 },
365 { .rfmax = 58000, .val = 0x3e },
366 { .rfmax = 59000, .val = 0x43 },
367 { .rfmax = 60000, .val = 0x4e },
368 { .rfmax = 61100, .val = 0x55 },
369 { .rfmax = 63000, .val = 0x0f },
370 { .rfmax = 64000, .val = 0x11 },
371 { .rfmax = 65000, .val = 0x12 },
372 { .rfmax = 66000, .val = 0x15 },
373 { .rfmax = 67000, .val = 0x16 },
374 { .rfmax = 68000, .val = 0x17 },
375 { .rfmax = 70000, .val = 0x19 },
376 { .rfmax = 71000, .val = 0x1c },
377 { .rfmax = 72000, .val = 0x1d },
378 { .rfmax = 73000, .val = 0x1f },
379 { .rfmax = 74000, .val = 0x20 },
380 { .rfmax = 75000, .val = 0x21 },
381 { .rfmax = 76000, .val = 0x24 },
382 { .rfmax = 77000, .val = 0x25 },
383 { .rfmax = 78000, .val = 0x27 },
384 { .rfmax = 80000, .val = 0x28 },
385 { .rfmax = 81000, .val = 0x29 },
386 { .rfmax = 82000, .val = 0x2d },
387 { .rfmax = 83000, .val = 0x2e },
388 { .rfmax = 84000, .val = 0x2f },
389 { .rfmax = 85000, .val = 0x31 },
390 { .rfmax = 86000, .val = 0x33 },
391 { .rfmax = 87000, .val = 0x34 },
392 { .rfmax = 88000, .val = 0x35 },
393 { .rfmax = 89000, .val = 0x37 },
394 { .rfmax = 90000, .val = 0x38 },
395 { .rfmax = 91000, .val = 0x39 },
396 { .rfmax = 93000, .val = 0x3c },
397 { .rfmax = 94000, .val = 0x3e },
398 { .rfmax = 95000, .val = 0x3f },
399 { .rfmax = 96000, .val = 0x40 },
400 { .rfmax = 97000, .val = 0x42 },
401 { .rfmax = 99000, .val = 0x45 },
402 { .rfmax = 100000, .val = 0x46 },
403 { .rfmax = 102000, .val = 0x48 },
404 { .rfmax = 103000, .val = 0x4a },
405 { .rfmax = 105000, .val = 0x4d },
406 { .rfmax = 106000, .val = 0x4e },
407 { .rfmax = 107000, .val = 0x50 },
408 { .rfmax = 108000, .val = 0x51 },
409 { .rfmax = 110000, .val = 0x54 },
410 { .rfmax = 111000, .val = 0x56 },
411 { .rfmax = 112000, .val = 0x57 },
412 { .rfmax = 113000, .val = 0x58 },
413 { .rfmax = 114000, .val = 0x59 },
414 { .rfmax = 115000, .val = 0x5c },
415 { .rfmax = 116000, .val = 0x5d },
416 { .rfmax = 117000, .val = 0x5f },
417 { .rfmax = 119000, .val = 0x60 },
418 { .rfmax = 120000, .val = 0x64 },
419 { .rfmax = 121000, .val = 0x65 },
420 { .rfmax = 122000, .val = 0x66 },
421 { .rfmax = 123000, .val = 0x68 },
422 { .rfmax = 124000, .val = 0x69 },
423 { .rfmax = 125000, .val = 0x6c },
424 { .rfmax = 126000, .val = 0x6d },
425 { .rfmax = 127000, .val = 0x6e },
426 { .rfmax = 128000, .val = 0x70 },
427 { .rfmax = 129000, .val = 0x71 },
428 { .rfmax = 130000, .val = 0x75 },
429 { .rfmax = 131000, .val = 0x77 },
430 { .rfmax = 132000, .val = 0x78 },
431 { .rfmax = 133000, .val = 0x7b },
432 { .rfmax = 134000, .val = 0x7e },
433 { .rfmax = 135000, .val = 0x81 },
434 { .rfmax = 136000, .val = 0x82 },
435 { .rfmax = 137000, .val = 0x87 },
436 { .rfmax = 138000, .val = 0x88 },
437 { .rfmax = 139000, .val = 0x8d },
438 { .rfmax = 140000, .val = 0x8e },
439 { .rfmax = 141000, .val = 0x91 },
440 { .rfmax = 142000, .val = 0x95 },
441 { .rfmax = 143000, .val = 0x9a },
442 { .rfmax = 144000, .val = 0x9d },
443 { .rfmax = 145000, .val = 0xa1 },
444 { .rfmax = 146000, .val = 0xa2 },
445 { .rfmax = 147000, .val = 0xa4 },
446 { .rfmax = 148000, .val = 0xa9 },
447 { .rfmax = 149000, .val = 0xae },
448 { .rfmax = 150000, .val = 0xb0 },
449 { .rfmax = 151000, .val = 0xb1 },
450 { .rfmax = 152000, .val = 0xb7 },
451 { .rfmax = 153000, .val = 0xbd },
452 { .rfmax = 154000, .val = 0x20 },
453 { .rfmax = 155000, .val = 0x22 },
454 { .rfmax = 156000, .val = 0x24 },
455 { .rfmax = 157000, .val = 0x25 },
456 { .rfmax = 158000, .val = 0x27 },
457 { .rfmax = 159000, .val = 0x29 },
458 { .rfmax = 160000, .val = 0x2c },
459 { .rfmax = 161000, .val = 0x2d },
460 { .rfmax = 163000, .val = 0x2e },
461 { .rfmax = 164000, .val = 0x2f },
462 { .rfmax = 165000, .val = 0x30 },
463 { .rfmax = 166000, .val = 0x11 },
464 { .rfmax = 167000, .val = 0x12 },
465 { .rfmax = 168000, .val = 0x13 },
466 { .rfmax = 169000, .val = 0x14 },
467 { .rfmax = 170000, .val = 0x15 },
468 { .rfmax = 172000, .val = 0x16 },
469 { .rfmax = 173000, .val = 0x17 },
470 { .rfmax = 174000, .val = 0x18 },
471 { .rfmax = 175000, .val = 0x1a },
472 { .rfmax = 176000, .val = 0x1b },
473 { .rfmax = 178000, .val = 0x1d },
474 { .rfmax = 179000, .val = 0x1e },
475 { .rfmax = 180000, .val = 0x1f },
476 { .rfmax = 181000, .val = 0x20 },
477 { .rfmax = 182000, .val = 0x21 },
478 { .rfmax = 183000, .val = 0x22 },
479 { .rfmax = 184000, .val = 0x24 },
480 { .rfmax = 185000, .val = 0x25 },
481 { .rfmax = 186000, .val = 0x26 },
482 { .rfmax = 187000, .val = 0x27 },
483 { .rfmax = 188000, .val = 0x29 },
484 { .rfmax = 189000, .val = 0x2a },
485 { .rfmax = 190000, .val = 0x2c },
486 { .rfmax = 191000, .val = 0x2d },
487 { .rfmax = 192000, .val = 0x2e },
488 { .rfmax = 193000, .val = 0x2f },
489 { .rfmax = 194000, .val = 0x30 },
490 { .rfmax = 195000, .val = 0x33 },
491 { .rfmax = 196000, .val = 0x35 },
492 { .rfmax = 198000, .val = 0x36 },
493 { .rfmax = 200000, .val = 0x38 },
494 { .rfmax = 201000, .val = 0x3c },
495 { .rfmax = 202000, .val = 0x3d },
496 { .rfmax = 203500, .val = 0x3e },
497 { .rfmax = 206000, .val = 0x0e },
498 { .rfmax = 208000, .val = 0x0f },
499 { .rfmax = 212000, .val = 0x10 },
500 { .rfmax = 216000, .val = 0x11 },
501 { .rfmax = 217000, .val = 0x12 },
502 { .rfmax = 218000, .val = 0x13 },
503 { .rfmax = 220000, .val = 0x14 },
504 { .rfmax = 222000, .val = 0x15 },
505 { .rfmax = 225000, .val = 0x16 },
506 { .rfmax = 228000, .val = 0x17 },
507 { .rfmax = 231000, .val = 0x18 },
508 { .rfmax = 234000, .val = 0x19 },
509 { .rfmax = 235000, .val = 0x1a },
510 { .rfmax = 236000, .val = 0x1b },
511 { .rfmax = 237000, .val = 0x1c },
512 { .rfmax = 240000, .val = 0x1d },
513 { .rfmax = 242000, .val = 0x1f },
514 { .rfmax = 247000, .val = 0x20 },
515 { .rfmax = 249000, .val = 0x21 },
516 { .rfmax = 252000, .val = 0x22 },
517 { .rfmax = 253000, .val = 0x23 },
518 { .rfmax = 254000, .val = 0x24 },
519 { .rfmax = 256000, .val = 0x25 },
520 { .rfmax = 259000, .val = 0x26 },
521 { .rfmax = 262000, .val = 0x27 },
522 { .rfmax = 264000, .val = 0x28 },
523 { .rfmax = 267000, .val = 0x29 },
524 { .rfmax = 269000, .val = 0x2a },
525 { .rfmax = 271000, .val = 0x2b },
526 { .rfmax = 273000, .val = 0x2c },
527 { .rfmax = 275000, .val = 0x2d },
528 { .rfmax = 277000, .val = 0x2e },
529 { .rfmax = 279000, .val = 0x2f },
530 { .rfmax = 282000, .val = 0x30 },
531 { .rfmax = 284000, .val = 0x31 },
532 { .rfmax = 286000, .val = 0x32 },
533 { .rfmax = 287000, .val = 0x33 },
534 { .rfmax = 290000, .val = 0x34 },
535 { .rfmax = 293000, .val = 0x35 },
536 { .rfmax = 295000, .val = 0x36 },
537 { .rfmax = 297000, .val = 0x37 },
538 { .rfmax = 300000, .val = 0x38 },
539 { .rfmax = 303000, .val = 0x39 },
540 { .rfmax = 305000, .val = 0x3a },
541 { .rfmax = 306000, .val = 0x3b },
542 { .rfmax = 307000, .val = 0x3c },
543 { .rfmax = 310000, .val = 0x3d },
544 { .rfmax = 312000, .val = 0x3e },
545 { .rfmax = 315000, .val = 0x3f },
546 { .rfmax = 318000, .val = 0x40 },
547 { .rfmax = 320000, .val = 0x41 },
548 { .rfmax = 323000, .val = 0x42 },
549 { .rfmax = 324000, .val = 0x43 },
550 { .rfmax = 325000, .val = 0x44 },
551 { .rfmax = 327000, .val = 0x45 },
552 { .rfmax = 331000, .val = 0x46 },
553 { .rfmax = 334000, .val = 0x47 },
554 { .rfmax = 337000, .val = 0x48 },
555 { .rfmax = 339000, .val = 0x49 },
556 { .rfmax = 340000, .val = 0x4a },
557 { .rfmax = 341000, .val = 0x4b },
558 { .rfmax = 343000, .val = 0x4c },
559 { .rfmax = 345000, .val = 0x4d },
560 { .rfmax = 349000, .val = 0x4e },
561 { .rfmax = 352000, .val = 0x4f },
562 { .rfmax = 353000, .val = 0x50 },
563 { .rfmax = 355000, .val = 0x51 },
564 { .rfmax = 357000, .val = 0x52 },
565 { .rfmax = 359000, .val = 0x53 },
566 { .rfmax = 361000, .val = 0x54 },
567 { .rfmax = 362000, .val = 0x55 },
568 { .rfmax = 364000, .val = 0x56 },
569 { .rfmax = 368000, .val = 0x57 },
570 { .rfmax = 370000, .val = 0x58 },
571 { .rfmax = 372000, .val = 0x59 },
572 { .rfmax = 375000, .val = 0x5a },
573 { .rfmax = 376000, .val = 0x5b },
574 { .rfmax = 377000, .val = 0x5c },
575 { .rfmax = 379000, .val = 0x5d },
576 { .rfmax = 382000, .val = 0x5e },
577 { .rfmax = 384000, .val = 0x5f },
578 { .rfmax = 385000, .val = 0x60 },
579 { .rfmax = 386000, .val = 0x61 },
580 { .rfmax = 388000, .val = 0x62 },
581 { .rfmax = 390000, .val = 0x63 },
582 { .rfmax = 393000, .val = 0x64 },
583 { .rfmax = 394000, .val = 0x65 },
584 { .rfmax = 396000, .val = 0x66 },
585 { .rfmax = 397000, .val = 0x67 },
586 { .rfmax = 398000, .val = 0x68 },
587 { .rfmax = 400000, .val = 0x69 },
588 { .rfmax = 402000, .val = 0x6a },
589 { .rfmax = 403000, .val = 0x6b },
590 { .rfmax = 407000, .val = 0x6c },
591 { .rfmax = 408000, .val = 0x6d },
592 { .rfmax = 409000, .val = 0x6e },
593 { .rfmax = 410000, .val = 0x6f },
594 { .rfmax = 411000, .val = 0x70 },
595 { .rfmax = 412000, .val = 0x71 },
596 { .rfmax = 413000, .val = 0x72 },
597 { .rfmax = 414000, .val = 0x73 },
598 { .rfmax = 417000, .val = 0x74 },
599 { .rfmax = 418000, .val = 0x75 },
600 { .rfmax = 420000, .val = 0x76 },
601 { .rfmax = 422000, .val = 0x77 },
602 { .rfmax = 423000, .val = 0x78 },
603 { .rfmax = 424000, .val = 0x79 },
604 { .rfmax = 427000, .val = 0x7a },
605 { .rfmax = 428000, .val = 0x7b },
606 { .rfmax = 429000, .val = 0x7d },
607 { .rfmax = 432000, .val = 0x7f },
608 { .rfmax = 434000, .val = 0x80 },
609 { .rfmax = 435000, .val = 0x81 },
610 { .rfmax = 436000, .val = 0x83 },
611 { .rfmax = 437000, .val = 0x84 },
612 { .rfmax = 438000, .val = 0x85 },
613 { .rfmax = 439000, .val = 0x86 },
614 { .rfmax = 440000, .val = 0x87 },
615 { .rfmax = 441000, .val = 0x88 },
616 { .rfmax = 442000, .val = 0x89 },
617 { .rfmax = 445000, .val = 0x8a },
618 { .rfmax = 446000, .val = 0x8b },
619 { .rfmax = 447000, .val = 0x8c },
620 { .rfmax = 448000, .val = 0x8e },
621 { .rfmax = 449000, .val = 0x8f },
622 { .rfmax = 450000, .val = 0x90 },
623 { .rfmax = 452000, .val = 0x91 },
624 { .rfmax = 453000, .val = 0x93 },
625 { .rfmax = 454000, .val = 0x94 },
626 { .rfmax = 456000, .val = 0x96 },
627 { .rfmax = 457000, .val = 0x98 },
628 { .rfmax = 461000, .val = 0x11 },
629 { .rfmax = 468000, .val = 0x12 },
630 { .rfmax = 472000, .val = 0x13 },
631 { .rfmax = 473000, .val = 0x14 },
632 { .rfmax = 474000, .val = 0x15 },
633 { .rfmax = 481000, .val = 0x16 },
634 { .rfmax = 486000, .val = 0x17 },
635 { .rfmax = 491000, .val = 0x18 },
636 { .rfmax = 498000, .val = 0x19 },
637 { .rfmax = 499000, .val = 0x1a },
638 { .rfmax = 501000, .val = 0x1b },
639 { .rfmax = 506000, .val = 0x1c },
640 { .rfmax = 511000, .val = 0x1d },
641 { .rfmax = 516000, .val = 0x1e },
642 { .rfmax = 520000, .val = 0x1f },
643 { .rfmax = 521000, .val = 0x20 },
644 { .rfmax = 525000, .val = 0x21 },
645 { .rfmax = 529000, .val = 0x22 },
646 { .rfmax = 533000, .val = 0x23 },
647 { .rfmax = 539000, .val = 0x24 },
648 { .rfmax = 541000, .val = 0x25 },
649 { .rfmax = 547000, .val = 0x26 },
650 { .rfmax = 549000, .val = 0x27 },
651 { .rfmax = 551000, .val = 0x28 },
652 { .rfmax = 556000, .val = 0x29 },
653 { .rfmax = 561000, .val = 0x2a },
654 { .rfmax = 563000, .val = 0x2b },
655 { .rfmax = 565000, .val = 0x2c },
656 { .rfmax = 569000, .val = 0x2d },
657 { .rfmax = 571000, .val = 0x2e },
658 { .rfmax = 577000, .val = 0x2f },
659 { .rfmax = 580000, .val = 0x30 },
660 { .rfmax = 582000, .val = 0x31 },
661 { .rfmax = 584000, .val = 0x32 },
662 { .rfmax = 588000, .val = 0x33 },
663 { .rfmax = 591000, .val = 0x34 },
664 { .rfmax = 596000, .val = 0x35 },
665 { .rfmax = 598000, .val = 0x36 },
666 { .rfmax = 603000, .val = 0x37 },
667 { .rfmax = 604000, .val = 0x38 },
668 { .rfmax = 606000, .val = 0x39 },
669 { .rfmax = 612000, .val = 0x3a },
670 { .rfmax = 615000, .val = 0x3b },
671 { .rfmax = 617000, .val = 0x3c },
672 { .rfmax = 621000, .val = 0x3d },
673 { .rfmax = 622000, .val = 0x3e },
674 { .rfmax = 625000, .val = 0x3f },
675 { .rfmax = 632000, .val = 0x40 },
676 { .rfmax = 633000, .val = 0x41 },
677 { .rfmax = 634000, .val = 0x42 },
678 { .rfmax = 642000, .val = 0x43 },
679 { .rfmax = 643000, .val = 0x44 },
680 { .rfmax = 647000, .val = 0x45 },
681 { .rfmax = 650000, .val = 0x46 },
682 { .rfmax = 652000, .val = 0x47 },
683 { .rfmax = 657000, .val = 0x48 },
684 { .rfmax = 661000, .val = 0x49 },
685 { .rfmax = 662000, .val = 0x4a },
686 { .rfmax = 665000, .val = 0x4b },
687 { .rfmax = 667000, .val = 0x4c },
688 { .rfmax = 670000, .val = 0x4d },
689 { .rfmax = 673000, .val = 0x4e },
690 { .rfmax = 676000, .val = 0x4f },
691 { .rfmax = 677000, .val = 0x50 },
692 { .rfmax = 681000, .val = 0x51 },
693 { .rfmax = 683000, .val = 0x52 },
694 { .rfmax = 686000, .val = 0x53 },
695 { .rfmax = 688000, .val = 0x54 },
696 { .rfmax = 689000, .val = 0x55 },
697 { .rfmax = 691000, .val = 0x56 },
698 { .rfmax = 695000, .val = 0x57 },
699 { .rfmax = 698000, .val = 0x58 },
700 { .rfmax = 703000, .val = 0x59 },
701 { .rfmax = 704000, .val = 0x5a },
702 { .rfmax = 705000, .val = 0x5b },
703 { .rfmax = 707000, .val = 0x5c },
704 { .rfmax = 710000, .val = 0x5d },
705 { .rfmax = 712000, .val = 0x5e },
706 { .rfmax = 717000, .val = 0x5f },
707 { .rfmax = 718000, .val = 0x60 },
708 { .rfmax = 721000, .val = 0x61 },
709 { .rfmax = 722000, .val = 0x62 },
710 { .rfmax = 723000, .val = 0x63 },
711 { .rfmax = 725000, .val = 0x64 },
712 { .rfmax = 727000, .val = 0x65 },
713 { .rfmax = 730000, .val = 0x66 },
714 { .rfmax = 732000, .val = 0x67 },
715 { .rfmax = 735000, .val = 0x68 },
716 { .rfmax = 740000, .val = 0x69 },
717 { .rfmax = 741000, .val = 0x6a },
718 { .rfmax = 742000, .val = 0x6b },
719 { .rfmax = 743000, .val = 0x6c },
720 { .rfmax = 745000, .val = 0x6d },
721 { .rfmax = 747000, .val = 0x6e },
722 { .rfmax = 748000, .val = 0x6f },
723 { .rfmax = 750000, .val = 0x70 },
724 { .rfmax = 752000, .val = 0x71 },
725 { .rfmax = 754000, .val = 0x72 },
726 { .rfmax = 757000, .val = 0x73 },
727 { .rfmax = 758000, .val = 0x74 },
728 { .rfmax = 760000, .val = 0x75 },
729 { .rfmax = 763000, .val = 0x76 },
730 { .rfmax = 764000, .val = 0x77 },
731 { .rfmax = 766000, .val = 0x78 },
732 { .rfmax = 767000, .val = 0x79 },
733 { .rfmax = 768000, .val = 0x7a },
734 { .rfmax = 773000, .val = 0x7b },
735 { .rfmax = 774000, .val = 0x7c },
736 { .rfmax = 776000, .val = 0x7d },
737 { .rfmax = 777000, .val = 0x7e },
738 { .rfmax = 778000, .val = 0x7f },
739 { .rfmax = 779000, .val = 0x80 },
740 { .rfmax = 781000, .val = 0x81 },
741 { .rfmax = 783000, .val = 0x82 },
742 { .rfmax = 784000, .val = 0x83 },
743 { .rfmax = 785000, .val = 0x84 },
744 { .rfmax = 786000, .val = 0x85 },
745 { .rfmax = 793000, .val = 0x86 },
746 { .rfmax = 794000, .val = 0x87 },
747 { .rfmax = 795000, .val = 0x88 },
748 { .rfmax = 797000, .val = 0x89 },
749 { .rfmax = 799000, .val = 0x8a },
750 { .rfmax = 801000, .val = 0x8b },
751 { .rfmax = 802000, .val = 0x8c },
752 { .rfmax = 803000, .val = 0x8d },
753 { .rfmax = 804000, .val = 0x8e },
754 { .rfmax = 810000, .val = 0x90 },
755 { .rfmax = 811000, .val = 0x91 },
756 { .rfmax = 812000, .val = 0x92 },
757 { .rfmax = 814000, .val = 0x93 },
758 { .rfmax = 816000, .val = 0x94 },
759 { .rfmax = 817000, .val = 0x96 },
760 { .rfmax = 818000, .val = 0x97 },
761 { .rfmax = 820000, .val = 0x98 },
762 { .rfmax = 821000, .val = 0x99 },
763 { .rfmax = 822000, .val = 0x9a },
764 { .rfmax = 828000, .val = 0x9b },
765 { .rfmax = 829000, .val = 0x9d },
766 { .rfmax = 830000, .val = 0x9f },
767 { .rfmax = 831000, .val = 0xa0 },
768 { .rfmax = 833000, .val = 0xa1 },
769 { .rfmax = 835000, .val = 0xa2 },
770 { .rfmax = 836000, .val = 0xa3 },
771 { .rfmax = 837000, .val = 0xa4 },
772 { .rfmax = 838000, .val = 0xa6 },
773 { .rfmax = 840000, .val = 0xa8 },
774 { .rfmax = 842000, .val = 0xa9 },
775 { .rfmax = 845000, .val = 0xaa },
776 { .rfmax = 846000, .val = 0xab },
777 { .rfmax = 847000, .val = 0xad },
778 { .rfmax = 848000, .val = 0xae },
779 { .rfmax = 852000, .val = 0xaf },
780 { .rfmax = 853000, .val = 0xb0 },
781 { .rfmax = 858000, .val = 0xb1 },
782 { .rfmax = 860000, .val = 0xb2 },
783 { .rfmax = 861000, .val = 0xb3 },
784 { .rfmax = 862000, .val = 0xb4 },
785 { .rfmax = 863000, .val = 0xb6 },
786 { .rfmax = 864000, .val = 0xb8 },
787 { .rfmax = 865000, .val = 0xb9 },
788 { .rfmax = 0, .val = 0x00 }, /* end */
789};
790
260static struct tda18271_map tda18271_ir_measure[] = { 791static struct tda18271_map tda18271_ir_measure[] = {
261 { .rfmax = 30000, .val = 4 }, 792 { .rfmax = 30000, .val = 4 },
262 { .rfmax = 200000, .val = 5 }, 793 { .rfmax = 200000, .val = 5 },
@@ -265,23 +796,293 @@ static struct tda18271_map tda18271_ir_measure[] = {
265 { .rfmax = 0, .val = 0 }, /* end */ 796 { .rfmax = 0, .val = 0 }, /* end */
266}; 797};
267 798
799static struct tda18271_map tda18271_rf_cal_dc_over_dt[] = {
800 { .rfmax = 47900, .val = 0x00 },
801 { .rfmax = 55000, .val = 0x00 },
802 { .rfmax = 61100, .val = 0x0a },
803 { .rfmax = 64000, .val = 0x0a },
804 { .rfmax = 82000, .val = 0x14 },
805 { .rfmax = 84000, .val = 0x19 },
806 { .rfmax = 119000, .val = 0x1c },
807 { .rfmax = 124000, .val = 0x20 },
808 { .rfmax = 129000, .val = 0x2a },
809 { .rfmax = 134000, .val = 0x32 },
810 { .rfmax = 139000, .val = 0x39 },
811 { .rfmax = 144000, .val = 0x3e },
812 { .rfmax = 149000, .val = 0x3f },
813 { .rfmax = 152600, .val = 0x40 },
814 { .rfmax = 154000, .val = 0x40 },
815 { .rfmax = 164700, .val = 0x41 },
816 { .rfmax = 203500, .val = 0x32 },
817 { .rfmax = 353000, .val = 0x19 },
818 { .rfmax = 356000, .val = 0x1a },
819 { .rfmax = 359000, .val = 0x1b },
820 { .rfmax = 363000, .val = 0x1c },
821 { .rfmax = 366000, .val = 0x1d },
822 { .rfmax = 369000, .val = 0x1e },
823 { .rfmax = 373000, .val = 0x1f },
824 { .rfmax = 376000, .val = 0x20 },
825 { .rfmax = 379000, .val = 0x21 },
826 { .rfmax = 383000, .val = 0x22 },
827 { .rfmax = 386000, .val = 0x23 },
828 { .rfmax = 389000, .val = 0x24 },
829 { .rfmax = 393000, .val = 0x25 },
830 { .rfmax = 396000, .val = 0x26 },
831 { .rfmax = 399000, .val = 0x27 },
832 { .rfmax = 402000, .val = 0x28 },
833 { .rfmax = 404000, .val = 0x29 },
834 { .rfmax = 407000, .val = 0x2a },
835 { .rfmax = 409000, .val = 0x2b },
836 { .rfmax = 412000, .val = 0x2c },
837 { .rfmax = 414000, .val = 0x2d },
838 { .rfmax = 417000, .val = 0x2e },
839 { .rfmax = 419000, .val = 0x2f },
840 { .rfmax = 422000, .val = 0x30 },
841 { .rfmax = 424000, .val = 0x31 },
842 { .rfmax = 427000, .val = 0x32 },
843 { .rfmax = 429000, .val = 0x33 },
844 { .rfmax = 432000, .val = 0x34 },
845 { .rfmax = 434000, .val = 0x35 },
846 { .rfmax = 437000, .val = 0x36 },
847 { .rfmax = 439000, .val = 0x37 },
848 { .rfmax = 442000, .val = 0x38 },
849 { .rfmax = 444000, .val = 0x39 },
850 { .rfmax = 447000, .val = 0x3a },
851 { .rfmax = 449000, .val = 0x3b },
852 { .rfmax = 457800, .val = 0x3c },
853 { .rfmax = 465000, .val = 0x0f },
854 { .rfmax = 477000, .val = 0x12 },
855 { .rfmax = 483000, .val = 0x14 },
856 { .rfmax = 502000, .val = 0x19 },
857 { .rfmax = 508000, .val = 0x1b },
858 { .rfmax = 519000, .val = 0x1c },
859 { .rfmax = 522000, .val = 0x1d },
860 { .rfmax = 524000, .val = 0x1e },
861 { .rfmax = 534000, .val = 0x1f },
862 { .rfmax = 549000, .val = 0x20 },
863 { .rfmax = 554000, .val = 0x22 },
864 { .rfmax = 584000, .val = 0x24 },
865 { .rfmax = 589000, .val = 0x26 },
866 { .rfmax = 658000, .val = 0x27 },
867 { .rfmax = 664000, .val = 0x2c },
868 { .rfmax = 669000, .val = 0x2d },
869 { .rfmax = 699000, .val = 0x2e },
870 { .rfmax = 704000, .val = 0x30 },
871 { .rfmax = 709000, .val = 0x31 },
872 { .rfmax = 714000, .val = 0x32 },
873 { .rfmax = 724000, .val = 0x33 },
874 { .rfmax = 729000, .val = 0x36 },
875 { .rfmax = 739000, .val = 0x38 },
876 { .rfmax = 744000, .val = 0x39 },
877 { .rfmax = 749000, .val = 0x3b },
878 { .rfmax = 754000, .val = 0x3c },
879 { .rfmax = 759000, .val = 0x3d },
880 { .rfmax = 764000, .val = 0x3e },
881 { .rfmax = 769000, .val = 0x3f },
882 { .rfmax = 774000, .val = 0x40 },
883 { .rfmax = 779000, .val = 0x41 },
884 { .rfmax = 784000, .val = 0x43 },
885 { .rfmax = 789000, .val = 0x46 },
886 { .rfmax = 794000, .val = 0x48 },
887 { .rfmax = 799000, .val = 0x4b },
888 { .rfmax = 804000, .val = 0x4f },
889 { .rfmax = 809000, .val = 0x54 },
890 { .rfmax = 814000, .val = 0x59 },
891 { .rfmax = 819000, .val = 0x5d },
892 { .rfmax = 824000, .val = 0x61 },
893 { .rfmax = 829000, .val = 0x68 },
894 { .rfmax = 834000, .val = 0x6e },
895 { .rfmax = 839000, .val = 0x75 },
896 { .rfmax = 844000, .val = 0x7e },
897 { .rfmax = 849000, .val = 0x82 },
898 { .rfmax = 854000, .val = 0x84 },
899 { .rfmax = 859000, .val = 0x8f },
900 { .rfmax = 865000, .val = 0x9a },
901 { .rfmax = 0, .val = 0x00 }, /* end */
902};
903
904/*---------------------------------------------------------------------*/
905
906struct tda18271_thermo_map {
907 u8 d;
908 u8 r0;
909 u8 r1;
910};
911
912static struct tda18271_thermo_map tda18271_thermometer[] = {
913 { .d = 0x00, .r0 = 60, .r1 = 92 },
914 { .d = 0x01, .r0 = 62, .r1 = 94 },
915 { .d = 0x02, .r0 = 66, .r1 = 98 },
916 { .d = 0x03, .r0 = 64, .r1 = 96 },
917 { .d = 0x04, .r0 = 74, .r1 = 106 },
918 { .d = 0x05, .r0 = 72, .r1 = 104 },
919 { .d = 0x06, .r0 = 68, .r1 = 100 },
920 { .d = 0x07, .r0 = 70, .r1 = 102 },
921 { .d = 0x08, .r0 = 90, .r1 = 122 },
922 { .d = 0x09, .r0 = 88, .r1 = 120 },
923 { .d = 0x0a, .r0 = 84, .r1 = 116 },
924 { .d = 0x0b, .r0 = 86, .r1 = 118 },
925 { .d = 0x0c, .r0 = 76, .r1 = 108 },
926 { .d = 0x0d, .r0 = 78, .r1 = 110 },
927 { .d = 0x0e, .r0 = 82, .r1 = 114 },
928 { .d = 0x0f, .r0 = 80, .r1 = 112 },
929 { .d = 0x00, .r0 = 0, .r1 = 0 }, /* end */
930};
931
932int tda18271_lookup_thermometer(struct dvb_frontend *fe)
933{
934 struct tda18271_priv *priv = fe->tuner_priv;
935 unsigned char *regs = priv->tda18271_regs;
936 int val, i = 0;
937
938 while (tda18271_thermometer[i].d < (regs[R_TM] & 0x0f)) {
939 if (tda18271_thermometer[i + 1].d == 0)
940 break;
941 i++;
942 }
943
944 if ((regs[R_TM] & 0x20) == 0x20)
945 val = tda18271_thermometer[i].r1;
946 else
947 val = tda18271_thermometer[i].r0;
948
949 tda_map("(%d) tm = %d\n", i, val);
950
951 return val;
952}
953
954/*---------------------------------------------------------------------*/
955
956struct tda18271_cid_target_map {
957 u32 rfmax;
958 u8 target;
959 u16 limit;
960};
961
962static struct tda18271_cid_target_map tda18271_cid_target[] = {
963 { .rfmax = 46000, .target = 0x04, .limit = 1800 },
964 { .rfmax = 52200, .target = 0x0a, .limit = 1500 },
965 { .rfmax = 79100, .target = 0x01, .limit = 4000 },
966 { .rfmax = 136800, .target = 0x18, .limit = 4000 },
967 { .rfmax = 156700, .target = 0x18, .limit = 4000 },
968 { .rfmax = 156700, .target = 0x18, .limit = 4000 },
969 { .rfmax = 186250, .target = 0x0a, .limit = 4000 },
970 { .rfmax = 230000, .target = 0x0a, .limit = 4000 },
971 { .rfmax = 345000, .target = 0x18, .limit = 4000 },
972 { .rfmax = 426000, .target = 0x0e, .limit = 4000 },
973 { .rfmax = 489500, .target = 0x1e, .limit = 4000 },
974 { .rfmax = 697500, .target = 0x32, .limit = 4000 },
975 { .rfmax = 842000, .target = 0x3a, .limit = 4000 },
976 { .rfmax = 0, .target = 0x00, .limit = 0 }, /* end */
977};
978
979int tda18271_lookup_cid_target(struct dvb_frontend *fe,
980 u32 *freq, u8 *cid_target, u16 *count_limit)
981{
982 int i = 0;
983
984 while ((tda18271_cid_target[i].rfmax * 1000) < *freq) {
985 if (tda18271_cid_target[i + 1].rfmax == 0)
986 break;
987 i++;
988 }
989 *cid_target = tda18271_cid_target[i].target;
990 *count_limit = tda18271_cid_target[i].limit;
991
992 tda_map("(%d) cid_target = %02x, count_limit = %d\n", i,
993 tda18271_cid_target[i].target, tda18271_cid_target[i].limit);
994
995 return 0;
996}
997
998/*---------------------------------------------------------------------*/
999
1000static struct tda18271_rf_tracking_filter_cal tda18271_rf_band_template[] = {
1001 { .rfmax = 47900, .rfband = 0x00,
1002 .rf1_def = 46000, .rf2_def = 0, .rf3_def = 0 },
1003 { .rfmax = 61100, .rfband = 0x01,
1004 .rf1_def = 52200, .rf2_def = 0, .rf3_def = 0 },
1005 { .rfmax = 152600, .rfband = 0x02,
1006 .rf1_def = 70100, .rf2_def = 136800, .rf3_def = 0 },
1007 { .rfmax = 164700, .rfband = 0x03,
1008 .rf1_def = 156700, .rf2_def = 0, .rf3_def = 0 },
1009 { .rfmax = 203500, .rfband = 0x04,
1010 .rf1_def = 186250, .rf2_def = 0, .rf3_def = 0 },
1011 { .rfmax = 457800, .rfband = 0x05,
1012 .rf1_def = 230000, .rf2_def = 345000, .rf3_def = 426000 },
1013 { .rfmax = 865000, .rfband = 0x06,
1014 .rf1_def = 489500, .rf2_def = 697500, .rf3_def = 842000 },
1015 { .rfmax = 0, .rfband = 0x00,
1016 .rf1_def = 0, .rf2_def = 0, .rf3_def = 0 }, /* end */
1017};
1018
1019int tda18271_lookup_rf_band(struct dvb_frontend *fe, u32 *freq, u8 *rf_band)
1020{
1021 struct tda18271_priv *priv = fe->tuner_priv;
1022 struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
1023 int i = 0;
1024
1025 while ((map[i].rfmax * 1000) < *freq) {
1026 if (tda18271_debug & DBG_ADV)
1027 tda_map("(%d) rfmax = %d < freq = %d, "
1028 "rf1_def = %d, rf2_def = %d, rf3_def = %d, "
1029 "rf1 = %d, rf2 = %d, rf3 = %d, "
1030 "rf_a1 = %d, rf_a2 = %d, "
1031 "rf_b1 = %d, rf_b2 = %d\n",
1032 i, map[i].rfmax * 1000, *freq,
1033 map[i].rf1_def, map[i].rf2_def, map[i].rf3_def,
1034 map[i].rf1, map[i].rf2, map[i].rf3,
1035 map[i].rf_a1, map[i].rf_a2,
1036 map[i].rf_b1, map[i].rf_b2);
1037 if (map[i].rfmax == 0)
1038 return -EINVAL;
1039 i++;
1040 }
1041 if (rf_band)
1042 *rf_band = map[i].rfband;
1043
1044 tda_map("(%d) rf_band = %02x\n", i, map[i].rfband);
1045
1046 return i;
1047}
1048
268/*---------------------------------------------------------------------*/ 1049/*---------------------------------------------------------------------*/
269 1050
270int tda18271_lookup_pll_map(enum tda18271_map_type map_type, 1051struct tda18271_map_layout {
1052 struct tda18271_pll_map *main_pll;
1053 struct tda18271_pll_map *cal_pll;
1054
1055 struct tda18271_map *rf_cal;
1056 struct tda18271_map *rf_cal_kmco;
1057 struct tda18271_map *rf_cal_dc_over_dt;
1058
1059 struct tda18271_map *bp_filter;
1060 struct tda18271_map *rf_band;
1061 struct tda18271_map *gain_taper;
1062 struct tda18271_map *ir_measure;
1063};
1064
1065/*---------------------------------------------------------------------*/
1066
1067int tda18271_lookup_pll_map(struct dvb_frontend *fe,
1068 enum tda18271_map_type map_type,
271 u32 *freq, u8 *post_div, u8 *div) 1069 u32 *freq, u8 *post_div, u8 *div)
272{ 1070{
1071 struct tda18271_priv *priv = fe->tuner_priv;
273 struct tda18271_pll_map *map = NULL; 1072 struct tda18271_pll_map *map = NULL;
274 unsigned int i = 0; 1073 unsigned int i = 0;
275 char *map_name; 1074 char *map_name;
276 int ret = 0; 1075 int ret = 0;
277 1076
1077 BUG_ON(!priv->maps);
1078
278 switch (map_type) { 1079 switch (map_type) {
279 case MAIN_PLL: 1080 case MAIN_PLL:
280 map = tda18271_main_pll; 1081 map = priv->maps->main_pll;
281 map_name = "main_pll"; 1082 map_name = "main_pll";
282 break; 1083 break;
283 case CAL_PLL: 1084 case CAL_PLL:
284 map = tda18271_cal_pll; 1085 map = priv->maps->cal_pll;
285 map_name = "cal_pll"; 1086 map_name = "cal_pll";
286 break; 1087 break;
287 default: 1088 default:
@@ -308,44 +1109,53 @@ int tda18271_lookup_pll_map(enum tda18271_map_type map_type,
308 *post_div = map[i].pd; 1109 *post_div = map[i].pd;
309 *div = map[i].d; 1110 *div = map[i].d;
310 1111
311 tda_map("%s: post div = 0x%02x, div = 0x%02x\n", 1112 tda_map("(%d) %s: post div = 0x%02x, div = 0x%02x\n",
312 map_name, *post_div, *div); 1113 i, map_name, *post_div, *div);
313fail: 1114fail:
314 return ret; 1115 return ret;
315} 1116}
316 1117
317int tda18271_lookup_map(enum tda18271_map_type map_type, u32 *freq, u8 *val) 1118int tda18271_lookup_map(struct dvb_frontend *fe,
1119 enum tda18271_map_type map_type,
1120 u32 *freq, u8 *val)
318{ 1121{
1122 struct tda18271_priv *priv = fe->tuner_priv;
319 struct tda18271_map *map = NULL; 1123 struct tda18271_map *map = NULL;
320 unsigned int i = 0; 1124 unsigned int i = 0;
321 char *map_name; 1125 char *map_name;
322 int ret = 0; 1126 int ret = 0;
323 1127
1128 BUG_ON(!priv->maps);
1129
324 switch (map_type) { 1130 switch (map_type) {
325 case BP_FILTER: 1131 case BP_FILTER:
326 map = tda18271_bp_filter; 1132 map = priv->maps->bp_filter;
327 map_name = "bp_filter"; 1133 map_name = "bp_filter";
328 break; 1134 break;
329 case RF_CAL_KMCO: 1135 case RF_CAL_KMCO:
330 map = tda18271_km; 1136 map = priv->maps->rf_cal_kmco;
331 map_name = "km"; 1137 map_name = "km";
332 break; 1138 break;
333 case RF_BAND: 1139 case RF_BAND:
334 map = tda18271_rf_band; 1140 map = priv->maps->rf_band;
335 map_name = "rf_band"; 1141 map_name = "rf_band";
336 break; 1142 break;
337 case GAIN_TAPER: 1143 case GAIN_TAPER:
338 map = tda18271_gain_taper; 1144 map = priv->maps->gain_taper;
339 map_name = "gain_taper"; 1145 map_name = "gain_taper";
340 break; 1146 break;
341 case RF_CAL: 1147 case RF_CAL:
342 map = tda18271_rf_cal; 1148 map = priv->maps->rf_cal;
343 map_name = "rf_cal"; 1149 map_name = "rf_cal";
344 break; 1150 break;
345 case IR_MEASURE: 1151 case IR_MEASURE:
346 map = tda18271_ir_measure; 1152 map = priv->maps->ir_measure;
347 map_name = "ir_measure"; 1153 map_name = "ir_measure";
348 break; 1154 break;
1155 case RF_CAL_DC_OVER_DT:
1156 map = priv->maps->rf_cal_dc_over_dt;
1157 map_name = "rf_cal_dc_over_dt";
1158 break;
349 default: 1159 default:
350 /* we should never get here */ 1160 /* we should never get here */
351 map_name = "undefined"; 1161 map_name = "undefined";
@@ -369,11 +1179,99 @@ int tda18271_lookup_map(enum tda18271_map_type map_type, u32 *freq, u8 *val)
369 } 1179 }
370 *val = map[i].val; 1180 *val = map[i].val;
371 1181
372 tda_map("%s: 0x%02x\n", map_name, *val); 1182 tda_map("(%d) %s: 0x%02x\n", i, map_name, *val);
373fail: 1183fail:
374 return ret; 1184 return ret;
375} 1185}
376 1186
1187/*---------------------------------------------------------------------*/
1188
1189static struct tda18271_std_map tda18271c1_std_map = {
1190 .atv_b = { .if_freq = 6750000, .std_bits = 0x0e },
1191 .atv_dk = { .if_freq = 7750000, .std_bits = 0x0f },
1192 .atv_gh = { .if_freq = 7750000, .std_bits = 0x0f },
1193 .atv_i = { .if_freq = 7750000, .std_bits = 0x0f },
1194 .atv_l = { .if_freq = 7750000, .std_bits = 0x0f },
1195 .atv_lc = { .if_freq = 1250000, .std_bits = 0x0f },
1196 .atv_mn = { .if_freq = 5750000, .std_bits = 0x0d },
1197 .atsc_6 = { .if_freq = 5380000, .std_bits = 0x1b },
1198 .dvbt_6 = { .if_freq = 3300000, .std_bits = 0x1b },
1199 .dvbt_7 = { .if_freq = 3800000, .std_bits = 0x19 },
1200 .dvbt_8 = { .if_freq = 4300000, .std_bits = 0x1a },
1201 .qam_6 = { .if_freq = 4000000, .std_bits = 0x18 },
1202 .qam_8 = { .if_freq = 5000000, .std_bits = 0x1f },
1203};
1204
1205static struct tda18271_std_map tda18271c2_std_map = {
1206 .atv_b = { .if_freq = 6000000, .std_bits = 0x0d },
1207 .atv_dk = { .if_freq = 6900000, .std_bits = 0x0e },
1208 .atv_gh = { .if_freq = 7100000, .std_bits = 0x0e },
1209 .atv_i = { .if_freq = 7250000, .std_bits = 0x0e },
1210 .atv_l = { .if_freq = 6900000, .std_bits = 0x0e },
1211 .atv_lc = { .if_freq = 1250000, .std_bits = 0x0e },
1212 .atv_mn = { .if_freq = 5400000, .std_bits = 0x0c },
1213 .atsc_6 = { .if_freq = 5380000, .std_bits = 0x1b },
1214 .dvbt_6 = { .if_freq = 3300000, .std_bits = 0x1c },
1215 .dvbt_7 = { .if_freq = 3500000, .std_bits = 0x1c },
1216 .dvbt_8 = { .if_freq = 4000000, .std_bits = 0x1d },
1217 .qam_6 = { .if_freq = 4000000, .std_bits = 0x1d },
1218 .qam_8 = { .if_freq = 5000000, .std_bits = 0x1f },
1219};
1220
1221/*---------------------------------------------------------------------*/
1222
1223static struct tda18271_map_layout tda18271c1_map_layout = {
1224 .main_pll = tda18271c1_main_pll,
1225 .cal_pll = tda18271c1_cal_pll,
1226
1227 .rf_cal = tda18271c1_rf_cal,
1228 .rf_cal_kmco = tda18271c1_km,
1229
1230 .bp_filter = tda18271_bp_filter,
1231 .rf_band = tda18271_rf_band,
1232 .gain_taper = tda18271_gain_taper,
1233 .ir_measure = tda18271_ir_measure,
1234};
1235
1236static struct tda18271_map_layout tda18271c2_map_layout = {
1237 .main_pll = tda18271c2_main_pll,
1238 .cal_pll = tda18271c2_cal_pll,
1239
1240 .rf_cal = tda18271c2_rf_cal,
1241 .rf_cal_kmco = tda18271c2_km,
1242
1243 .rf_cal_dc_over_dt = tda18271_rf_cal_dc_over_dt,
1244
1245 .bp_filter = tda18271_bp_filter,
1246 .rf_band = tda18271_rf_band,
1247 .gain_taper = tda18271_gain_taper,
1248 .ir_measure = tda18271_ir_measure,
1249};
1250
1251int tda18271_assign_map_layout(struct dvb_frontend *fe)
1252{
1253 struct tda18271_priv *priv = fe->tuner_priv;
1254 int ret = 0;
1255
1256 switch (priv->id) {
1257 case TDA18271HDC1:
1258 priv->maps = &tda18271c1_map_layout;
1259 priv->std = &tda18271c1_std_map;
1260 break;
1261 case TDA18271HDC2:
1262 priv->maps = &tda18271c2_map_layout;
1263 priv->std = &tda18271c2_std_map;
1264 break;
1265 default:
1266 ret = -EINVAL;
1267 break;
1268 }
1269 memcpy(priv->rf_cal_state, &tda18271_rf_band_template,
1270 sizeof(tda18271_rf_band_template));
1271
1272 return ret;
1273}
1274
377/* 1275/*
378 * Overrides for Emacs so that we follow Linus's tabbing style. 1276 * Overrides for Emacs so that we follow Linus's tabbing style.
379 * --------------------------------------------------------------------------- 1277 * ---------------------------------------------------------------------------
diff --git a/drivers/media/video/tda8290.c b/drivers/media/video/tda8290.c
index bb62d5629af2..54d261a2f25a 100644
--- a/drivers/media/video/tda8290.c
+++ b/drivers/media/video/tda8290.c
@@ -570,7 +570,7 @@ static int tda829x_find_tuner(struct dvb_frontend *fe)
570 return -EREMOTEIO; 570 return -EREMOTEIO;
571 } 571 }
572 572
573 if (data == 0x83) { 573 if ((data == 0x83) || (data == 0x84)) {
574 priv->ver |= TDA18271; 574 priv->ver |= TDA18271;
575 tda18271_attach(fe, priv->tda827x_addr, 575 tda18271_attach(fe, priv->tda827x_addr,
576 priv->i2c_props.adap, 576 priv->i2c_props.adap,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 17:44:41 -0500