[POWERPC] Fix IPIC pending register assignments

This patch fixes the assignment of pending registers to IRQ numbers for the IPIC; the code previously assigned all IRQs to the high pending word regardless of which word the interrupt belonged to. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
author: Scott Wood <scottwood@freescale.com> 2006-09-21 14:10:51 -0400
committer: Paul Mackerras <paulus@samba.org> 2006-09-22 01:19:58 -0400
commit: ed709d134deeaea7925a3d748b33ca7e58cc683d (patch)
tree: 9d42ba6363e933273011e6c31d834b950ea8cad8
parent: 7d452c326c2ac879aced884411a0fe3ba75d9c87 (diff)
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 70e707785d49..0251b7c68d0e 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -210,7 +210,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 4,
        },
        [64] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SIFCR_L,
@@ -218,7 +218,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 0,
        },
        [65] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SIFCR_L,
@@ -226,7 +226,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 1,
        },
        [66] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SIFCR_L,
@@ -234,7 +234,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 2,
        },
        [67] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_A,
                .force  = IPIC_SIFCR_L,
@@ -242,7 +242,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 3,
        },
        [68] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SIFCR_L,
@@ -250,7 +250,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 0,
        },
        [69] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SIFCR_L,
@@ -258,7 +258,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 1,
        },
        [70] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SIFCR_L,
@@ -266,7 +266,7 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 2,
        },
        [71] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = IPIC_SMPRR_B,
                .force  = IPIC_SIFCR_L,
@@ -274,91 +274,91 @@ static struct ipic_info ipic_info[] = {
                .prio_mask = 3,
        },
        [72] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 8,
        },
        [73] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 9,
        },
        [74] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 10,
        },
        [75] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 11,
        },
        [76] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 12,
        },
        [77] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 13,
        },
        [78] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 14,
        },
        [79] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 15,
        },
        [80] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 16,
        },
        [84] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 20,
        },
        [85] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 21,
        },
        [90] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
                .bit    = 26,
        },
        [91] = {
-                .pend   = IPIC_SIPNR_H,
+                .pend   = IPIC_SIPNR_L,
                .mask   = IPIC_SIMSR_L,
                .prio   = 0,
                .force  = IPIC_SIFCR_L,
author	Scott Wood <scottwood@freescale.com>	2006-09-21 14:10:51 -0400
committer	Paul Mackerras <paulus@samba.org>	2006-09-22 01:19:58 -0400
commit	ed709d134deeaea7925a3d748b33ca7e58cc683d (patch)
tree	9d42ba6363e933273011e6c31d834b950ea8cad8
parent	7d452c326c2ac879aced884411a0fe3ba75d9c87 (diff)

diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index 70e707785d49..0251b7c68d0e 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c
@@ -210,7 +210,7 @@ static struct ipic_info ipic_info[] = {
210	.prio_mask = 4,	210	.prio_mask = 4,
211	},	211	},
212	[64] = {	212	[64] = {
213	.pend = IPIC_SIPNR_H,	213	.pend = IPIC_SIPNR_L,
214	.mask = IPIC_SIMSR_L,	214	.mask = IPIC_SIMSR_L,
215	.prio = IPIC_SMPRR_A,	215	.prio = IPIC_SMPRR_A,
216	.force = IPIC_SIFCR_L,	216	.force = IPIC_SIFCR_L,
@@ -218,7 +218,7 @@ static struct ipic_info ipic_info[] = {
218	.prio_mask = 0,	218	.prio_mask = 0,
219	},	219	},
220	[65] = {	220	[65] = {
221	.pend = IPIC_SIPNR_H,	221	.pend = IPIC_SIPNR_L,
222	.mask = IPIC_SIMSR_L,	222	.mask = IPIC_SIMSR_L,
223	.prio = IPIC_SMPRR_A,	223	.prio = IPIC_SMPRR_A,
224	.force = IPIC_SIFCR_L,	224	.force = IPIC_SIFCR_L,
@@ -226,7 +226,7 @@ static struct ipic_info ipic_info[] = {
226	.prio_mask = 1,	226	.prio_mask = 1,
227	},	227	},
228	[66] = {	228	[66] = {
229	.pend = IPIC_SIPNR_H,	229	.pend = IPIC_SIPNR_L,
230	.mask = IPIC_SIMSR_L,	230	.mask = IPIC_SIMSR_L,
231	.prio = IPIC_SMPRR_A,	231	.prio = IPIC_SMPRR_A,
232	.force = IPIC_SIFCR_L,	232	.force = IPIC_SIFCR_L,
@@ -234,7 +234,7 @@ static struct ipic_info ipic_info[] = {
234	.prio_mask = 2,	234	.prio_mask = 2,
235	},	235	},
236	[67] = {	236	[67] = {
237	.pend = IPIC_SIPNR_H,	237	.pend = IPIC_SIPNR_L,
238	.mask = IPIC_SIMSR_L,	238	.mask = IPIC_SIMSR_L,
239	.prio = IPIC_SMPRR_A,	239	.prio = IPIC_SMPRR_A,
240	.force = IPIC_SIFCR_L,	240	.force = IPIC_SIFCR_L,
@@ -242,7 +242,7 @@ static struct ipic_info ipic_info[] = {
242	.prio_mask = 3,	242	.prio_mask = 3,
243	},	243	},
244	[68] = {	244	[68] = {
245	.pend = IPIC_SIPNR_H,	245	.pend = IPIC_SIPNR_L,
246	.mask = IPIC_SIMSR_L,	246	.mask = IPIC_SIMSR_L,
247	.prio = IPIC_SMPRR_B,	247	.prio = IPIC_SMPRR_B,
248	.force = IPIC_SIFCR_L,	248	.force = IPIC_SIFCR_L,
@@ -250,7 +250,7 @@ static struct ipic_info ipic_info[] = {
250	.prio_mask = 0,	250	.prio_mask = 0,
251	},	251	},
252	[69] = {	252	[69] = {
253	.pend = IPIC_SIPNR_H,	253	.pend = IPIC_SIPNR_L,
254	.mask = IPIC_SIMSR_L,	254	.mask = IPIC_SIMSR_L,
255	.prio = IPIC_SMPRR_B,	255	.prio = IPIC_SMPRR_B,
256	.force = IPIC_SIFCR_L,	256	.force = IPIC_SIFCR_L,
@@ -258,7 +258,7 @@ static struct ipic_info ipic_info[] = {
258	.prio_mask = 1,	258	.prio_mask = 1,
259	},	259	},
260	[70] = {	260	[70] = {
261	.pend = IPIC_SIPNR_H,	261	.pend = IPIC_SIPNR_L,
262	.mask = IPIC_SIMSR_L,	262	.mask = IPIC_SIMSR_L,
263	.prio = IPIC_SMPRR_B,	263	.prio = IPIC_SMPRR_B,
264	.force = IPIC_SIFCR_L,	264	.force = IPIC_SIFCR_L,
@@ -266,7 +266,7 @@ static struct ipic_info ipic_info[] = {
266	.prio_mask = 2,	266	.prio_mask = 2,
267	},	267	},
268	[71] = {	268	[71] = {
269	.pend = IPIC_SIPNR_H,	269	.pend = IPIC_SIPNR_L,
270	.mask = IPIC_SIMSR_L,	270	.mask = IPIC_SIMSR_L,
271	.prio = IPIC_SMPRR_B,	271	.prio = IPIC_SMPRR_B,
272	.force = IPIC_SIFCR_L,	272	.force = IPIC_SIFCR_L,
@@ -274,91 +274,91 @@ static struct ipic_info ipic_info[] = {
274	.prio_mask = 3,	274	.prio_mask = 3,
275	},	275	},
276	[72] = {	276	[72] = {
277	.pend = IPIC_SIPNR_H,	277	.pend = IPIC_SIPNR_L,
278	.mask = IPIC_SIMSR_L,	278	.mask = IPIC_SIMSR_L,
279	.prio = 0,	279	.prio = 0,
280	.force = IPIC_SIFCR_L,	280	.force = IPIC_SIFCR_L,
281	.bit = 8,	281	.bit = 8,
282	},	282	},
283	[73] = {	283	[73] = {
284	.pend = IPIC_SIPNR_H,	284	.pend = IPIC_SIPNR_L,
285	.mask = IPIC_SIMSR_L,	285	.mask = IPIC_SIMSR_L,
286	.prio = 0,	286	.prio = 0,
287	.force = IPIC_SIFCR_L,	287	.force = IPIC_SIFCR_L,
288	.bit = 9,	288	.bit = 9,
289	},	289	},
290	[74] = {	290	[74] = {
291	.pend = IPIC_SIPNR_H,	291	.pend = IPIC_SIPNR_L,
292	.mask = IPIC_SIMSR_L,	292	.mask = IPIC_SIMSR_L,
293	.prio = 0,	293	.prio = 0,
294	.force = IPIC_SIFCR_L,	294	.force = IPIC_SIFCR_L,
295	.bit = 10,	295	.bit = 10,
296	},	296	},
297	[75] = {	297	[75] = {
298	.pend = IPIC_SIPNR_H,	298	.pend = IPIC_SIPNR_L,
299	.mask = IPIC_SIMSR_L,	299	.mask = IPIC_SIMSR_L,
300	.prio = 0,	300	.prio = 0,
301	.force = IPIC_SIFCR_L,	301	.force = IPIC_SIFCR_L,
302	.bit = 11,	302	.bit = 11,
303	},	303	},
304	[76] = {	304	[76] = {
305	.pend = IPIC_SIPNR_H,	305	.pend = IPIC_SIPNR_L,
306	.mask = IPIC_SIMSR_L,	306	.mask = IPIC_SIMSR_L,
307	.prio = 0,	307	.prio = 0,
308	.force = IPIC_SIFCR_L,	308	.force = IPIC_SIFCR_L,
309	.bit = 12,	309	.bit = 12,
310	},	310	},
311	[77] = {	311	[77] = {
312	.pend = IPIC_SIPNR_H,	312	.pend = IPIC_SIPNR_L,
313	.mask = IPIC_SIMSR_L,	313	.mask = IPIC_SIMSR_L,
314	.prio = 0,	314	.prio = 0,
315	.force = IPIC_SIFCR_L,	315	.force = IPIC_SIFCR_L,
316	.bit = 13,	316	.bit = 13,
317	},	317	},
318	[78] = {	318	[78] = {
319	.pend = IPIC_SIPNR_H,	319	.pend = IPIC_SIPNR_L,
320	.mask = IPIC_SIMSR_L,	320	.mask = IPIC_SIMSR_L,
321	.prio = 0,	321	.prio = 0,
322	.force = IPIC_SIFCR_L,	322	.force = IPIC_SIFCR_L,
323	.bit = 14,	323	.bit = 14,
324	},	324	},
325	[79] = {	325	[79] = {
326	.pend = IPIC_SIPNR_H,	326	.pend = IPIC_SIPNR_L,
327	.mask = IPIC_SIMSR_L,	327	.mask = IPIC_SIMSR_L,
328	.prio = 0,	328	.prio = 0,
329	.force = IPIC_SIFCR_L,	329	.force = IPIC_SIFCR_L,
330	.bit = 15,	330	.bit = 15,
331	},	331	},
332	[80] = {	332	[80] = {
333	.pend = IPIC_SIPNR_H,	333	.pend = IPIC_SIPNR_L,
334	.mask = IPIC_SIMSR_L,	334	.mask = IPIC_SIMSR_L,
335	.prio = 0,	335	.prio = 0,
336	.force = IPIC_SIFCR_L,	336	.force = IPIC_SIFCR_L,
337	.bit = 16,	337	.bit = 16,
338	},	338	},
339	[84] = {	339	[84] = {
340	.pend = IPIC_SIPNR_H,	340	.pend = IPIC_SIPNR_L,
341	.mask = IPIC_SIMSR_L,	341	.mask = IPIC_SIMSR_L,
342	.prio = 0,	342	.prio = 0,
343	.force = IPIC_SIFCR_L,	343	.force = IPIC_SIFCR_L,
344	.bit = 20,	344	.bit = 20,
345	},	345	},
346	[85] = {	346	[85] = {
347	.pend = IPIC_SIPNR_H,	347	.pend = IPIC_SIPNR_L,
348	.mask = IPIC_SIMSR_L,	348	.mask = IPIC_SIMSR_L,
349	.prio = 0,	349	.prio = 0,
350	.force = IPIC_SIFCR_L,	350	.force = IPIC_SIFCR_L,
351	.bit = 21,	351	.bit = 21,
352	},	352	},
353	[90] = {	353	[90] = {
354	.pend = IPIC_SIPNR_H,	354	.pend = IPIC_SIPNR_L,
355	.mask = IPIC_SIMSR_L,	355	.mask = IPIC_SIMSR_L,
356	.prio = 0,	356	.prio = 0,
357	.force = IPIC_SIFCR_L,	357	.force = IPIC_SIFCR_L,
358	.bit = 26,	358	.bit = 26,
359	},	359	},
360	[91] = {	360	[91] = {
361	.pend = IPIC_SIPNR_H,	361	.pend = IPIC_SIPNR_L,
362	.mask = IPIC_SIMSR_L,	362	.mask = IPIC_SIMSR_L,
363	.prio = 0,	363	.prio = 0,
364	.force = IPIC_SIFCR_L,	364	.force = IPIC_SIFCR_L,