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authorPaul Walmsley <paul@pwsan.com>2008-03-18 05:02:28 -0400
committerTony Lindgren <tony@atomide.com>2008-04-14 13:29:39 -0400
commitd83b079f0f5c6f5ef34976330b904509a53ff1ec (patch)
tree2382b00fa19e32d6aa2ef1ddbcc5befb5dbf35c8
parenta16e97037b518533569a778f0e997704e5c43796 (diff)
ARM: OMAP2: Remove old PRCM register access code
Remove old PRCM register access code that is no longer needed. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/pm-domain.c299
-rw-r--r--arch/arm/mach-omap2/prcm-regs.h497
3 files changed, 1 insertions, 797 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index a3b2507fcc58..2eabadc81083 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -7,7 +7,7 @@ obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
7 devices.o serial.o gpmc.o timer-gp.o 7 devices.o serial.o gpmc.o timer-gp.o
8 8
9# Power Management 9# Power Management
10obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o 10obj-$(CONFIG_PM) += pm.o sleep.o
11 11
12# Clock framework 12# Clock framework
13obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o 13obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c
deleted file mode 100644
index 2494091a078b..000000000000
--- a/arch/arm/mach-omap2/pm-domain.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/pm-domain.c
3 *
4 * Power domain functions for OMAP2
5 *
6 * Copyright (C) 2006 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
8 *
9 * Some code based on earlier OMAP2 sample PM code
10 * Copyright (C) 2005 Texas Instruments, Inc.
11 * Richard Woodruff <r-woodruff2@ti.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/clk.h>
21
22#include <asm/io.h>
23
24#include "prcm-regs.h"
25
26/* Power domain offsets */
27#define PM_MPU_OFFSET 0x100
28#define PM_CORE_OFFSET 0x200
29#define PM_GFX_OFFSET 0x300
30#define PM_WKUP_OFFSET 0x400 /* Autoidle only */
31#define PM_PLL_OFFSET 0x500 /* Autoidle only */
32#define PM_DSP_OFFSET 0x800
33#define PM_MDM_OFFSET 0xc00
34
35/* Power domain wake-up dependency control register */
36#define PM_WKDEP_OFFSET 0xc8
37#define EN_MDM (1 << 5)
38#define EN_WKUP (1 << 4)
39#define EN_GFX (1 << 3)
40#define EN_DSP (1 << 2)
41#define EN_MPU (1 << 1)
42#define EN_CORE (1 << 0)
43
44/* Core power domain state transition control register */
45#define PM_PWSTCTRL_OFFSET 0xe0
46#define FORCESTATE (1 << 18) /* Only for DSP & GFX */
47#define MEM4RETSTATE (1 << 6)
48#define MEM3RETSTATE (1 << 5)
49#define MEM2RETSTATE (1 << 4)
50#define MEM1RETSTATE (1 << 3)
51#define LOGICRETSTATE (1 << 2) /* Logic is retained */
52#define POWERSTATE_OFF 0x3
53#define POWERSTATE_RETENTION 0x1
54#define POWERSTATE_ON 0x0
55
56/* Power domain state register */
57#define PM_PWSTST_OFFSET 0xe4
58
59/* Hardware supervised state transition control register */
60#define CM_CLKSTCTRL_OFFSET 0x48
61#define AUTOSTAT_MPU (1 << 0) /* MPU */
62#define AUTOSTAT_DSS (1 << 2) /* Core */
63#define AUTOSTAT_L4 (1 << 1) /* Core */
64#define AUTOSTAT_L3 (1 << 0) /* Core */
65#define AUTOSTAT_GFX (1 << 0) /* GFX */
66#define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */
67#define AUTOSTAT_DSP (1 << 0) /* DSP */
68#define AUTOSTAT_MDM (1 << 0) /* MDM */
69
70/* Automatic control of interface clock idling */
71#define CM_AUTOIDLE1_OFFSET 0x30
72#define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */
73#define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */
74#define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */
75#define AUTO_54M(x) (((x) & 0x3) << 6)
76#define AUTO_96M(x) (((x) & 0x3) << 2)
77#define AUTO_DPLL(x) (((x) & 0x3) << 0)
78#define AUTO_STOPPED 0x3
79#define AUTO_BYPASS_FAST 0x2 /* DPLL only */
80#define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */
81#define AUTO_DISABLED 0x0
82
83/* Voltage control PRCM_VOLTCTRL bits */
84#define AUTO_EXTVOLT (1 << 15)
85#define FORCE_EXTVOLT (1 << 14)
86#define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
87#define MEMRETCTRL (1 << 8)
88#define SETRET_LEVEL(x) (((x) & 0x3) << 6)
89#define VOLT_LEVEL(x) (((x) & 0x3) << 0)
90
91#define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE)
92#define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r))
93#define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
94
95static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
96{
97 return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
98}
99
100static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
101{
102 prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
103}
104
105static u32 pmdomain_get_powerstate(int domain_offset)
106{
107 return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
108}
109
110static void pmdomain_set_powerstate(u32 state, int domain_offset)
111{
112 prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
113}
114
115static u32 pmdomain_get_clock_autocontrol(int domain_offset)
116{
117 return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
118}
119
120static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
121{
122 prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
123}
124
125static u32 pmdomain_get_clock_autoidle1(int domain_offset)
126{
127 return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
128}
129
130/* Core domain only */
131static u32 pmdomain_get_clock_autoidle2(int domain_offset)
132{
133 return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
134}
135
136/* Core domain only */
137static u32 pmdomain_get_clock_autoidle3(int domain_offset)
138{
139 return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
140}
141
142/* Core domain only */
143static u32 pmdomain_get_clock_autoidle4(int domain_offset)
144{
145 return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
146}
147
148static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
149{
150 prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
151}
152
153/* Core domain only */
154static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
155{
156 prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
157}
158
159/* Core domain only */
160static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
161{
162 prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
163}
164
165/* Core domain only */
166static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
167{
168 prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
169}
170
171/*
172 * Configures power management domains to idle clocks automatically.
173 */
174void pmdomain_set_autoidle(void)
175{
176 u32 val;
177
178 /* Set PLL auto stop for 54M, 96M & DPLL */
179 pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
180 AUTO_96M(AUTO_STOPPED) |
181 AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
182
183 /* External clock input control
184 * REVISIT: Should this be in clock framework?
185 */
186 PRCM_CLKSRC_CTRL |= (0x3 << 3);
187
188 /* Configure number of 32KHz clock cycles for sys_clk */
189 PRCM_CLKSSETUP = 0x00ff;
190
191 /* Configure automatic voltage transition */
192 PRCM_VOLTSETUP = 0;
193 val = PRCM_VOLTCTRL;
194 val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
195 val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
196 PRCM_VOLTCTRL = val;
197
198 /* Disable emulation tools functional clock */
199 PRCM_CLKEMUL_CTRL = 0x0;
200
201 /* Set core memory retention state */
202 val = pmdomain_get_powerstate(PM_CORE_OFFSET);
203 if (cpu_is_omap2420()) {
204 val &= ~(0x7 << 3);
205 val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
206 } else {
207 val &= ~(0xf << 3);
208 val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
209 MEM1RETSTATE);
210 }
211 pmdomain_set_powerstate(val, PM_CORE_OFFSET);
212
213 /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
214 val = SMS_SYSCONFIG;
215 val &= ~(0x3 << 3);
216 val |= (0x2 << 3) | (1 << 0);
217 SMS_SYSCONFIG |= val;
218
219 val = SDRC_SYSCONFIG;
220 val &= ~(0x3 << 3);
221 val |= (0x2 << 3);
222 SDRC_SYSCONFIG = val;
223
224 /* Configure L3 interface for smart idle.
225 * REVISIT: Enable autoidle bit0 ?
226 */
227 val = GPMC_SYSCONFIG;
228 val &= ~(0x3 << 3);
229 val |= (0x2 << 3) | (1 << 0);
230 GPMC_SYSCONFIG = val;
231
232 pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
233 PM_MPU_OFFSET);
234 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
235 if (!cpu_is_omap2420())
236 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
237
238 /* Assume suspend function has saved the state for DSP and GFX */
239 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
240 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
241
242#if 0
243 /* REVISIT: Internal USB needs special handling */
244 force_standby_usb();
245 if (cpu_is_omap2430())
246 force_hsmmc();
247 sdram_self_refresh_on_idle_req(1);
248#endif
249
250 /* Enable clock auto control for all domains.
251 * Note that CORE domain includes also DSS, L4 & L3.
252 */
253 pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
254 pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
255 pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
256 PM_CORE_OFFSET);
257 if (cpu_is_omap2420())
258 pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
259 PM_DSP_OFFSET);
260 else {
261 pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
262 pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
263 }
264
265 /* Enable clock autoidle for all domains */
266 pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
267 if (cpu_is_omap2420()) {
268 pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
269 pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
270 pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
271 } else {
272 pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
273 pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
274 pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
275 pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
276 }
277 pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
278 pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
279}
280
281/*
282 * Initializes power domains by removing wake-up dependencies and powering
283 * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
284 * must re-enable DSP and GFX when used.
285 */
286void __init pmdomain_init(void)
287{
288 /* Remove all domain wakeup dependencies */
289 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
290 pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
291 pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
292 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
293 if (cpu_is_omap2430())
294 pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
295
296 /* Power down DSP and GFX */
297 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
298 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
299}
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
deleted file mode 100644
index c7f6cfa0b485..000000000000
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ /dev/null
@@ -1,497 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/prcm-regs.h
3 *
4 * OMAP24XX Power Reset and Clock Management (PRCM) registers
5 *
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
24#define __ARCH_ARM_MACH_OMAP2_PRCM_H
25
26#ifdef CONFIG_ARCH_OMAP2420
27#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
28#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
29#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000)
30#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
31#endif
32
33#ifdef CONFIG_ARCH_OMAP2430
34#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
35#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
36#define OMAP24XX_SDRC_BASE (0x6D000000)
37#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
38#endif
39
40/* SET_PERFORMANCE_LEVEL PARAMETERS */
41#define PRCM_HALF_SPEED 1
42#define PRCM_FULL_SPEED 2
43
44#ifndef __ASSEMBLER__
45
46#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
47
48#define PRCM_REVISION PRCM_REG32(0x000)
49#define PRCM_SYSCONFIG PRCM_REG32(0x010)
50#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
51#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
52#define PRCM_VOLTCTRL PRCM_REG32(0x050)
53#define PRCM_VOLTST PRCM_REG32(0x054)
54#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
55#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
56#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
57#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
58#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
59#define PRCM_VOLTSETUP PRCM_REG32(0x090)
60#define PRCM_CLKSSETUP PRCM_REG32(0x094)
61#define PRCM_POLCTRL PRCM_REG32(0x098)
62
63/* GENERAL PURPOSE */
64#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
65#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
66#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
67#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
68#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
69#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
70#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
71#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
72#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
73#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
74#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
75#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
76#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
77#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
78#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
79#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
80#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
81#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
82#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
83#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
84
85/* MPU */
86#define CM_CLKSEL_MPU PRCM_REG32(0x140)
87#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
88#define RM_RSTST_MPU PRCM_REG32(0x158)
89#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
90#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
91#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
92#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
93#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
94#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
95
96/* CORE */
97#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
98#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
99#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
100#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
101#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
102#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
103#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
104#define CM_IDLEST1_CORE PRCM_REG32(0x220)
105#define CM_IDLEST2_CORE PRCM_REG32(0x224)
106#define CM_IDLEST3_CORE PRCM_REG32(0x228)
107#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
108#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
109#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
110#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
111#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
112#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
113#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
114#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
115#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
116#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
117#define PM_WKST1_CORE PRCM_REG32(0x2B0)
118#define PM_WKST2_CORE PRCM_REG32(0x2B4)
119#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
120#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
121#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
122
123/* GFX */
124#define CM_FCLKEN_GFX PRCM_REG32(0x300)
125#define CM_ICLKEN_GFX PRCM_REG32(0x310)
126#define CM_IDLEST_GFX PRCM_REG32(0x320)
127#define CM_CLKSEL_GFX PRCM_REG32(0x340)
128#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
129#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
130#define RM_RSTST_GFX PRCM_REG32(0x358)
131#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
132#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
133#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
134
135/* WAKE-UP */
136#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
137#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
138#define CM_IDLEST_WKUP PRCM_REG32(0x420)
139#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
140#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
141#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
142#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
143#define RM_RSTST_WKUP PRCM_REG32(0x458)
144#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
145#define PM_WKST_WKUP PRCM_REG32(0x4B0)
146
147/* CLOCKS */
148#define CM_CLKEN_PLL PRCM_REG32(0x500)
149#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
150#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
151#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
152#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
153
154/* DSP */
155#define CM_FCLKEN_DSP PRCM_REG32(0x800)
156#define CM_ICLKEN_DSP PRCM_REG32(0x810)
157#define CM_IDLEST_DSP PRCM_REG32(0x820)
158#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
159#define CM_CLKSEL_DSP PRCM_REG32(0x840)
160#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
161#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
162#define RM_RSTST_DSP PRCM_REG32(0x858)
163#define PM_WKEN_DSP PRCM_REG32(0x8A0)
164#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
165#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
166#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
167#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
168#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
169
170/* IVA */
171#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
172#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
173
174/* Modem on 2430 */
175#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
176#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
177#define CM_IDLEST_MDM PRCM_REG32(0xC20)
178#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
179#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
180#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
181#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
182#define RM_RSTST_MDM PRCM_REG32(0xC58)
183#define PM_WKEN_MDM PRCM_REG32(0xCA0)
184#define PM_WKST_MDM PRCM_REG32(0xCB0)
185#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
186#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
187#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
188
189#define OMAP24XX_L4_IO_BASE 0x48000000
190
191#define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000)
192#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
193
194#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
195#define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset))
196
197/* FIXME: Move these to timer code */
198#define GPT1_BASE (0x48028000)
199#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
200
201/* Misc sysconfig */
202#define DISPC_SYSCONFIG DISP_REG32(0x410)
203#define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000)
204#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
205#define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10)
206#define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
207
208#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10)
209#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C)
210#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C)
211#define GPMC_SYSCONFIG GPMC_REG32(0x010)
212#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
213#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
214#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
215#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
216#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10)
217#define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000)
218#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10)
219#define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010)
220
221/* rkw - good cannidates for PM_ to start what nm was trying */
222#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000)
223#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000)
224#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000)
225#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000)
226#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000)
227#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000)
228#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000)
229#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000)
230#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000)
231#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000)
232#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000)
233
234/* FIXME: Move these to timer code */
235#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
236#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
237#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
238#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
239#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
240#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
241#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
242#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
243#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
244#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
245#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
246#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
247
248/* FIXME: Move these to gpio code */
249#define OMAP24XX_GPIO_BASE 0x48018000
250#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
251
252#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10))
253#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10))
254#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10))
255#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10))
256
257#if defined(CONFIG_ARCH_OMAP243X)
258#define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10))
259#endif
260
261/* GP TIMER 1 */
262#define GPTIMER1_TISTAT GPT1_REG32(0x014)
263#define GPTIMER1_TISR GPT1_REG32(0x018)
264#define GPTIMER1_TIER GPT1_REG32(0x01C)
265#define GPTIMER1_TWER GPT1_REG32(0x020)
266#define GPTIMER1_TCLR GPT1_REG32(0x024)
267#define GPTIMER1_TCRR GPT1_REG32(0x028)
268#define GPTIMER1_TLDR GPT1_REG32(0x02C)
269#define GPTIMER1_TTGR GPT1_REG32(0x030)
270#define GPTIMER1_TWPS GPT1_REG32(0x034)
271#define GPTIMER1_TMAR GPT1_REG32(0x038)
272#define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
273#define GPTIMER1_TSICR GPT1_REG32(0x040)
274#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
275
276/* rkw -- base fix up please... */
277#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
278
279/* SDRC */
280#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
281#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
282#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
283#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
284#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
285#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
286
287/* GPIO 1 */
288#define GPIO1_BASE GPIOX_BASE(1)
289#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
290#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
291#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
292#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
293#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
294#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
295#define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
296#define GPIO1_DATAIN GPIO1_REG32(0x038)
297#define GPIO1_OE GPIO1_REG32(0x034)
298#define GPIO1_DATAOUT GPIO1_REG32(0x03C)
299
300/* GPIO2 */
301#define GPIO2_BASE GPIOX_BASE(2)
302#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
303#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
304#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
305#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
306#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
307#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
308#define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
309#define GPIO2_DATAIN GPIO2_REG32(0x038)
310#define GPIO2_OE GPIO2_REG32(0x034)
311#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
312#define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050)
313#define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054)
314
315/* GPIO 3 */
316#define GPIO3_BASE GPIOX_BASE(3)
317#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
318#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
319#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
320#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
321#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
322#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
323#define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
324#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
325#define GPIO3_DATAIN GPIO3_REG32(0x038)
326#define GPIO3_OE GPIO3_REG32(0x034)
327#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
328#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
329#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
330#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
331#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
332
333/* GPIO 4 */
334#define GPIO4_BASE GPIOX_BASE(4)
335#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
336#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
337#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
338#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
339#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
340#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
341#define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
342#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
343#define GPIO4_DATAIN GPIO4_REG32(0x038)
344#define GPIO4_OE GPIO4_REG32(0x034)
345#define GPIO4_DATAOUT GPIO4_REG32(0x03C)
346#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
347#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
348
349#if defined(CONFIG_ARCH_OMAP243X)
350/* GPIO 5 */
351#define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset)))
352#define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C)
353#define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018)
354#define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C)
355#define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028)
356#define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020)
357#define GPIO5_RISINGDETECT GPIO5_REG32(0x048)
358#define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C)
359#define GPIO5_DATAIN GPIO5_REG32(0x038)
360#define GPIO5_OE GPIO5_REG32(0x034)
361#define GPIO5_DATAOUT GPIO5_REG32(0x03C)
362#define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050)
363#define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054)
364#endif
365
366/* IO CONFIG */
367#define OMAP24XX_CTRL_BASE (L4_24XX_BASE)
368#define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset))
369
370#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
371#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
372#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
373#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
374#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
375#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
376#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */
377#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
378#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
379#define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */
380#define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */
381
382/* CONTROL */
383#define CONTROL_DEVCONF CONTROL_REG32(0x274)
384#define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8)
385
386/* INTERRUPT CONTROLLER */
387#define INTC_BASE ((L4_24XX_BASE) + 0xfe000)
388#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
389
390#define INTC1_U_BASE INTC_REG32(0x000)
391#define INTC_MIR0 INTC_REG32(0x084)
392#define INTC_MIR_SET0 INTC_REG32(0x08C)
393#define INTC_MIR_CLEAR0 INTC_REG32(0x088)
394#define INTC_ISR_CLEAR0 INTC_REG32(0x094)
395#define INTC_MIR1 INTC_REG32(0x0A4)
396#define INTC_MIR_SET1 INTC_REG32(0x0AC)
397#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
398#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
399#define INTC_MIR2 INTC_REG32(0x0C4)
400#define INTC_MIR_SET2 INTC_REG32(0x0CC)
401#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
402#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
403#define INTC_SIR_IRQ INTC_REG32(0x040)
404#define INTC_CONTROL INTC_REG32(0x048)
405#define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */
406#define INTC_ILR30 INTC_REG32(0x178)
407#define INTC_ILR31 INTC_REG32(0x17C)
408#define INTC_ILR32 INTC_REG32(0x180)
409#define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */
410#define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */
411
412/* RAM FIREWALL */
413#define RAMFW_BASE (0x68005000)
414#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
415
416#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
417#define RAMFW_READPERM0 RAMFW_REG32(0x050)
418#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
419
420/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
421//#define DEBUG_BOARD_LED_REGISTER 0x04000014
422
423/* GPMC CS0 */
424#define GPMC_CONFIG1_0 GPMC_REG32(0x060)
425#define GPMC_CONFIG2_0 GPMC_REG32(0x064)
426#define GPMC_CONFIG3_0 GPMC_REG32(0x068)
427#define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
428#define GPMC_CONFIG5_0 GPMC_REG32(0x070)
429#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
430#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
431
432/* GPMC CS1 */
433#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
434#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
435#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
436#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
437#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
438#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
439#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
440
441/* GPMC CS3 */
442#define GPMC_CONFIG1_3 GPMC_REG32(0x0F0)
443#define GPMC_CONFIG2_3 GPMC_REG32(0x0F4)
444#define GPMC_CONFIG3_3 GPMC_REG32(0x0F8)
445#define GPMC_CONFIG4_3 GPMC_REG32(0x0FC)
446#define GPMC_CONFIG5_3 GPMC_REG32(0x100)
447#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
448#define GPMC_CONFIG7_3 GPMC_REG32(0x108)
449
450/* DSS */
451#define DSS_CONTROL DISP_REG32(0x040)
452#define DISPC_CONTROL DISP_REG32(0x440)
453#define DISPC_SYSSTATUS DISP_REG32(0x414)
454#define DISPC_IRQSTATUS DISP_REG32(0x418)
455#define DISPC_IRQENABLE DISP_REG32(0x41C)
456#define DISPC_CONFIG DISP_REG32(0x444)
457#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
458#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
459#define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
460#define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
461#define DISPC_LINE_NUMBER DISP_REG32(0x460)
462#define DISPC_TIMING_H DISP_REG32(0x464)
463#define DISPC_TIMING_V DISP_REG32(0x468)
464#define DISPC_POL_FREQ DISP_REG32(0x46C)
465#define DISPC_DIVISOR DISP_REG32(0x470)
466#define DISPC_SIZE_DIG DISP_REG32(0x478)
467#define DISPC_SIZE_LCD DISP_REG32(0x47C)
468#define DISPC_GFX_BA0 DISP_REG32(0x480)
469#define DISPC_GFX_BA1 DISP_REG32(0x484)
470#define DISPC_GFX_POSITION DISP_REG32(0x488)
471#define DISPC_GFX_SIZE DISP_REG32(0x48C)
472#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
473#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
474#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
475#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
476#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
477#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
478#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
479#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
480#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
481
482/* HSUSB Suspend */
483#define HSUSB_CTRL __REG8(0x480AC001)
484#define USBOTG_POWER __REG32(0x480AC000)
485
486/* HS MMC */
487#define MMCHS1_SYSCONFIG __REG32(0x4809C010)
488#define MMCHS2_SYSCONFIG __REG32(0x480b4010)
489
490#endif /* __ASSEMBLER__ */
491
492#endif
493
494
495
496
497
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-05 09:05:33 -0500