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authorColin Cross <ccross@android.com>2010-07-09 18:13:52 -0400
committerColin Cross <ccross@android.com>2010-10-21 21:11:41 -0400
commitc5f04b8d10a73f2a016d6815d64dd5eebc734097 (patch)
tree54b6fd1ed295d7e9c5c85fce7c9767f1eced6569
parent460907bc26f5565aced3cf35a10e3579c671ef50 (diff)
[ARM] tegra: pinmux: add safe values, move tegra2, add suspend
- the reset values for some pin groups in the tegra pin mux can result in functional errors due to conflicting with actively-configured pin groups muxing from the same controller. this change adds a known safe, non- conflicting mux for every pin group, which can be used on platforms where the pin group is not routed to any peripheral - also add each pin group's I/O voltage rail, to enable platform code to map from the pin groups used by each interface to the regulators used for dynamic voltage control - add routines to individually configure the tristate, pin mux and pull- ups for a pingroup_config array, so that it is possible to program individual values at run-time without modifying other values. this allows driver power-management code to reprogram individual interfaces into lower power states during idle / suspend, or to reprogram the pin mux to support multiple physical busses per internal controller (e.g., sharing a single I2C or SPI controller across multiple pin groups) - move chip-specific data like pingroups and drive-pingroups out of the common code and into chip-specific code - fix debug output for group with no pullups - add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE will automatically select a mux setting that is guaranteed not to conflict with any of the hardware blocks. Signed-off-by: Gary King <gking@nvidia.com>
Diffstat
-rw-r--r--arch/arm/mach-tegra/Makefile1
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-t2.h174
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h210
-rw-r--r--arch/arm/mach-tegra/pinmux-t2-tables.c260
-rw-r--r--arch/arm/mach-tegra/pinmux.c354
5 files changed, 603 insertions, 396 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0a975b5fe493..87d065e65113 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,6 +7,7 @@ obj-y += gpio.o
7obj-y += pinmux.o 7obj-y += pinmux.o
8obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o 8obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o
9obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 9obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o
10obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o 11obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o
11obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 12obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
12 13
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
new file mode 100644
index 000000000000..e5b9d740f973
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
@@ -0,0 +1,174 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_PINMUX_T2_H
18#define __MACH_TEGRA_PINMUX_T2_H
19
20enum tegra_pingroup {
21 TEGRA_PINGROUP_ATA = 0,
22 TEGRA_PINGROUP_ATB,
23 TEGRA_PINGROUP_ATC,
24 TEGRA_PINGROUP_ATD,
25 TEGRA_PINGROUP_ATE,
26 TEGRA_PINGROUP_CDEV1,
27 TEGRA_PINGROUP_CDEV2,
28 TEGRA_PINGROUP_CRTP,
29 TEGRA_PINGROUP_CSUS,
30 TEGRA_PINGROUP_DAP1,
31 TEGRA_PINGROUP_DAP2,
32 TEGRA_PINGROUP_DAP3,
33 TEGRA_PINGROUP_DAP4,
34 TEGRA_PINGROUP_DDC,
35 TEGRA_PINGROUP_DTA,
36 TEGRA_PINGROUP_DTB,
37 TEGRA_PINGROUP_DTC,
38 TEGRA_PINGROUP_DTD,
39 TEGRA_PINGROUP_DTE,
40 TEGRA_PINGROUP_DTF,
41 TEGRA_PINGROUP_GMA,
42 TEGRA_PINGROUP_GMB,
43 TEGRA_PINGROUP_GMC,
44 TEGRA_PINGROUP_GMD,
45 TEGRA_PINGROUP_GME,
46 TEGRA_PINGROUP_GPU,
47 TEGRA_PINGROUP_GPU7,
48 TEGRA_PINGROUP_GPV,
49 TEGRA_PINGROUP_HDINT,
50 TEGRA_PINGROUP_I2CP,
51 TEGRA_PINGROUP_IRRX,
52 TEGRA_PINGROUP_IRTX,
53 TEGRA_PINGROUP_KBCA,
54 TEGRA_PINGROUP_KBCB,
55 TEGRA_PINGROUP_KBCC,
56 TEGRA_PINGROUP_KBCD,
57 TEGRA_PINGROUP_KBCE,
58 TEGRA_PINGROUP_KBCF,
59 TEGRA_PINGROUP_LCSN,
60 TEGRA_PINGROUP_LD0,
61 TEGRA_PINGROUP_LD1,
62 TEGRA_PINGROUP_LD10,
63 TEGRA_PINGROUP_LD11,
64 TEGRA_PINGROUP_LD12,
65 TEGRA_PINGROUP_LD13,
66 TEGRA_PINGROUP_LD14,
67 TEGRA_PINGROUP_LD15,
68 TEGRA_PINGROUP_LD16,
69 TEGRA_PINGROUP_LD17,
70 TEGRA_PINGROUP_LD2,
71 TEGRA_PINGROUP_LD3,
72 TEGRA_PINGROUP_LD4,
73 TEGRA_PINGROUP_LD5,
74 TEGRA_PINGROUP_LD6,
75 TEGRA_PINGROUP_LD7,
76 TEGRA_PINGROUP_LD8,
77 TEGRA_PINGROUP_LD9,
78 TEGRA_PINGROUP_LDC,
79 TEGRA_PINGROUP_LDI,
80 TEGRA_PINGROUP_LHP0,
81 TEGRA_PINGROUP_LHP1,
82 TEGRA_PINGROUP_LHP2,
83 TEGRA_PINGROUP_LHS,
84 TEGRA_PINGROUP_LM0,
85 TEGRA_PINGROUP_LM1,
86 TEGRA_PINGROUP_LPP,
87 TEGRA_PINGROUP_LPW0,
88 TEGRA_PINGROUP_LPW1,
89 TEGRA_PINGROUP_LPW2,
90 TEGRA_PINGROUP_LSC0,
91 TEGRA_PINGROUP_LSC1,
92 TEGRA_PINGROUP_LSCK,
93 TEGRA_PINGROUP_LSDA,
94 TEGRA_PINGROUP_LSDI,
95 TEGRA_PINGROUP_LSPI,
96 TEGRA_PINGROUP_LVP0,
97 TEGRA_PINGROUP_LVP1,
98 TEGRA_PINGROUP_LVS,
99 TEGRA_PINGROUP_OWC,
100 TEGRA_PINGROUP_PMC,
101 TEGRA_PINGROUP_PTA,
102 TEGRA_PINGROUP_RM,
103 TEGRA_PINGROUP_SDB,
104 TEGRA_PINGROUP_SDC,
105 TEGRA_PINGROUP_SDD,
106 TEGRA_PINGROUP_SDIO1,
107 TEGRA_PINGROUP_SLXA,
108 TEGRA_PINGROUP_SLXC,
109 TEGRA_PINGROUP_SLXD,
110 TEGRA_PINGROUP_SLXK,
111 TEGRA_PINGROUP_SPDI,
112 TEGRA_PINGROUP_SPDO,
113 TEGRA_PINGROUP_SPIA,
114 TEGRA_PINGROUP_SPIB,
115 TEGRA_PINGROUP_SPIC,
116 TEGRA_PINGROUP_SPID,
117 TEGRA_PINGROUP_SPIE,
118 TEGRA_PINGROUP_SPIF,
119 TEGRA_PINGROUP_SPIG,
120 TEGRA_PINGROUP_SPIH,
121 TEGRA_PINGROUP_UAA,
122 TEGRA_PINGROUP_UAB,
123 TEGRA_PINGROUP_UAC,
124 TEGRA_PINGROUP_UAD,
125 TEGRA_PINGROUP_UCA,
126 TEGRA_PINGROUP_UCB,
127 TEGRA_PINGROUP_UDA,
128 /* these pin groups only have pullup and pull down control */
129 TEGRA_PINGROUP_CK32,
130 TEGRA_PINGROUP_DDRC,
131 TEGRA_PINGROUP_PMCA,
132 TEGRA_PINGROUP_PMCB,
133 TEGRA_PINGROUP_PMCC,
134 TEGRA_PINGROUP_PMCD,
135 TEGRA_PINGROUP_PMCE,
136 TEGRA_PINGROUP_XM2C,
137 TEGRA_PINGROUP_XM2D,
138 TEGRA_MAX_PINGROUP,
139};
140
141enum tegra_drive_pingroup {
142 TEGRA_DRIVE_PINGROUP_AO1 = 0,
143 TEGRA_DRIVE_PINGROUP_AO2,
144 TEGRA_DRIVE_PINGROUP_AT1,
145 TEGRA_DRIVE_PINGROUP_AT2,
146 TEGRA_DRIVE_PINGROUP_CDEV1,
147 TEGRA_DRIVE_PINGROUP_CDEV2,
148 TEGRA_DRIVE_PINGROUP_CSUS,
149 TEGRA_DRIVE_PINGROUP_DAP1,
150 TEGRA_DRIVE_PINGROUP_DAP2,
151 TEGRA_DRIVE_PINGROUP_DAP3,
152 TEGRA_DRIVE_PINGROUP_DAP4,
153 TEGRA_DRIVE_PINGROUP_DBG,
154 TEGRA_DRIVE_PINGROUP_LCD1,
155 TEGRA_DRIVE_PINGROUP_LCD2,
156 TEGRA_DRIVE_PINGROUP_SDMMC2,
157 TEGRA_DRIVE_PINGROUP_SDMMC3,
158 TEGRA_DRIVE_PINGROUP_SPI,
159 TEGRA_DRIVE_PINGROUP_UAA,
160 TEGRA_DRIVE_PINGROUP_UAB,
161 TEGRA_DRIVE_PINGROUP_UART2,
162 TEGRA_DRIVE_PINGROUP_UART3,
163 TEGRA_DRIVE_PINGROUP_VI1,
164 TEGRA_DRIVE_PINGROUP_VI2,
165 TEGRA_DRIVE_PINGROUP_XM2A,
166 TEGRA_DRIVE_PINGROUP_XM2C,
167 TEGRA_DRIVE_PINGROUP_XM2D,
168 TEGRA_DRIVE_PINGROUP_XM2CLK,
169 TEGRA_DRIVE_PINGROUP_MEMCOMP,
170 TEGRA_MAX_DRIVE_PINGROUP,
171};
172
173#endif
174
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index 41c8ce5b7c27..defd8775defa 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -17,126 +17,11 @@
17#ifndef __MACH_TEGRA_PINMUX_H 17#ifndef __MACH_TEGRA_PINMUX_H
18#define __MACH_TEGRA_PINMUX_H 18#define __MACH_TEGRA_PINMUX_H
19 19
20enum tegra_pingroup { 20#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
21 TEGRA_PINGROUP_ATA = 0, 21#include "pinmux-t2.h"
22 TEGRA_PINGROUP_ATB, 22#else
23 TEGRA_PINGROUP_ATC, 23#error "Undefined Tegra architecture"
24 TEGRA_PINGROUP_ATD, 24#endif
25 TEGRA_PINGROUP_ATE,
26 TEGRA_PINGROUP_CDEV1,
27 TEGRA_PINGROUP_CDEV2,
28 TEGRA_PINGROUP_CRTP,
29 TEGRA_PINGROUP_CSUS,
30 TEGRA_PINGROUP_DAP1,
31 TEGRA_PINGROUP_DAP2,
32 TEGRA_PINGROUP_DAP3,
33 TEGRA_PINGROUP_DAP4,
34 TEGRA_PINGROUP_DDC,
35 TEGRA_PINGROUP_DTA,
36 TEGRA_PINGROUP_DTB,
37 TEGRA_PINGROUP_DTC,
38 TEGRA_PINGROUP_DTD,
39 TEGRA_PINGROUP_DTE,
40 TEGRA_PINGROUP_DTF,
41 TEGRA_PINGROUP_GMA,
42 TEGRA_PINGROUP_GMB,
43 TEGRA_PINGROUP_GMC,
44 TEGRA_PINGROUP_GMD,
45 TEGRA_PINGROUP_GME,
46 TEGRA_PINGROUP_GPU,
47 TEGRA_PINGROUP_GPU7,
48 TEGRA_PINGROUP_GPV,
49 TEGRA_PINGROUP_HDINT,
50 TEGRA_PINGROUP_I2CP,
51 TEGRA_PINGROUP_IRRX,
52 TEGRA_PINGROUP_IRTX,
53 TEGRA_PINGROUP_KBCA,
54 TEGRA_PINGROUP_KBCB,
55 TEGRA_PINGROUP_KBCC,
56 TEGRA_PINGROUP_KBCD,
57 TEGRA_PINGROUP_KBCE,
58 TEGRA_PINGROUP_KBCF,
59 TEGRA_PINGROUP_LCSN,
60 TEGRA_PINGROUP_LD0,
61 TEGRA_PINGROUP_LD1,
62 TEGRA_PINGROUP_LD10,
63 TEGRA_PINGROUP_LD11,
64 TEGRA_PINGROUP_LD12,
65 TEGRA_PINGROUP_LD13,
66 TEGRA_PINGROUP_LD14,
67 TEGRA_PINGROUP_LD15,
68 TEGRA_PINGROUP_LD16,
69 TEGRA_PINGROUP_LD17,
70 TEGRA_PINGROUP_LD2,
71 TEGRA_PINGROUP_LD3,
72 TEGRA_PINGROUP_LD4,
73 TEGRA_PINGROUP_LD5,
74 TEGRA_PINGROUP_LD6,
75 TEGRA_PINGROUP_LD7,
76 TEGRA_PINGROUP_LD8,
77 TEGRA_PINGROUP_LD9,
78 TEGRA_PINGROUP_LDC,
79 TEGRA_PINGROUP_LDI,
80 TEGRA_PINGROUP_LHP0,
81 TEGRA_PINGROUP_LHP1,
82 TEGRA_PINGROUP_LHP2,
83 TEGRA_PINGROUP_LHS,
84 TEGRA_PINGROUP_LM0,
85 TEGRA_PINGROUP_LM1,
86 TEGRA_PINGROUP_LPP,
87 TEGRA_PINGROUP_LPW0,
88 TEGRA_PINGROUP_LPW1,
89 TEGRA_PINGROUP_LPW2,
90 TEGRA_PINGROUP_LSC0,
91 TEGRA_PINGROUP_LSC1,
92 TEGRA_PINGROUP_LSCK,
93 TEGRA_PINGROUP_LSDA,
94 TEGRA_PINGROUP_LSDI,
95 TEGRA_PINGROUP_LSPI,
96 TEGRA_PINGROUP_LVP0,
97 TEGRA_PINGROUP_LVP1,
98 TEGRA_PINGROUP_LVS,
99 TEGRA_PINGROUP_OWC,
100 TEGRA_PINGROUP_PMC,
101 TEGRA_PINGROUP_PTA,
102 TEGRA_PINGROUP_RM,
103 TEGRA_PINGROUP_SDB,
104 TEGRA_PINGROUP_SDC,
105 TEGRA_PINGROUP_SDD,
106 TEGRA_PINGROUP_SDIO1,
107 TEGRA_PINGROUP_SLXA,
108 TEGRA_PINGROUP_SLXC,
109 TEGRA_PINGROUP_SLXD,
110 TEGRA_PINGROUP_SLXK,
111 TEGRA_PINGROUP_SPDI,
112 TEGRA_PINGROUP_SPDO,
113 TEGRA_PINGROUP_SPIA,
114 TEGRA_PINGROUP_SPIB,
115 TEGRA_PINGROUP_SPIC,
116 TEGRA_PINGROUP_SPID,
117 TEGRA_PINGROUP_SPIE,
118 TEGRA_PINGROUP_SPIF,
119 TEGRA_PINGROUP_SPIG,
120 TEGRA_PINGROUP_SPIH,
121 TEGRA_PINGROUP_UAA,
122 TEGRA_PINGROUP_UAB,
123 TEGRA_PINGROUP_UAC,
124 TEGRA_PINGROUP_UAD,
125 TEGRA_PINGROUP_UCA,
126 TEGRA_PINGROUP_UCB,
127 TEGRA_PINGROUP_UDA,
128 /* these pin groups only have pullup and pull down control */
129 TEGRA_PINGROUP_CK32,
130 TEGRA_PINGROUP_DDRC,
131 TEGRA_PINGROUP_PMCA,
132 TEGRA_PINGROUP_PMCB,
133 TEGRA_PINGROUP_PMCC,
134 TEGRA_PINGROUP_PMCD,
135 TEGRA_PINGROUP_PMCE,
136 TEGRA_PINGROUP_XM2C,
137 TEGRA_PINGROUP_XM2D,
138 TEGRA_MAX_PINGROUP,
139};
140 25
141enum tegra_mux_func { 26enum tegra_mux_func {
142 TEGRA_MUX_RSVD = 0x8000, 27 TEGRA_MUX_RSVD = 0x8000,
@@ -205,6 +90,7 @@ enum tegra_mux_func {
205 TEGRA_MUX_VI, 90 TEGRA_MUX_VI,
206 TEGRA_MUX_VI_SENSOR_CLK, 91 TEGRA_MUX_VI_SENSOR_CLK,
207 TEGRA_MUX_XIO, 92 TEGRA_MUX_XIO,
93 TEGRA_MUX_SAFE,
208 TEGRA_MAX_MUX, 94 TEGRA_MAX_MUX,
209}; 95};
210 96
@@ -219,6 +105,18 @@ enum tegra_tristate {
219 TEGRA_TRI_TRISTATE = 1, 105 TEGRA_TRI_TRISTATE = 1,
220}; 106};
221 107
108enum tegra_vddio {
109 TEGRA_VDDIO_BB = 0,
110 TEGRA_VDDIO_LCD,
111 TEGRA_VDDIO_VI,
112 TEGRA_VDDIO_UART,
113 TEGRA_VDDIO_DDR,
114 TEGRA_VDDIO_NAND,
115 TEGRA_VDDIO_SYS,
116 TEGRA_VDDIO_AUDIO,
117 TEGRA_VDDIO_SD,
118};
119
222struct tegra_pingroup_config { 120struct tegra_pingroup_config {
223 enum tegra_pingroup pingroup; 121 enum tegra_pingroup pingroup;
224 enum tegra_mux_func func; 122 enum tegra_mux_func func;
@@ -270,38 +168,6 @@ enum tegra_pull_strength {
270 TEGRA_MAX_PULL, 168 TEGRA_MAX_PULL,
271}; 169};
272 170
273enum tegra_drive_pingroup {
274 TEGRA_DRIVE_PINGROUP_AO1 = 0,
275 TEGRA_DRIVE_PINGROUP_AO2,
276 TEGRA_DRIVE_PINGROUP_AT1,
277 TEGRA_DRIVE_PINGROUP_AT2,
278 TEGRA_DRIVE_PINGROUP_CDEV1,
279 TEGRA_DRIVE_PINGROUP_CDEV2,
280 TEGRA_DRIVE_PINGROUP_CSUS,
281 TEGRA_DRIVE_PINGROUP_DAP1,
282 TEGRA_DRIVE_PINGROUP_DAP2,
283 TEGRA_DRIVE_PINGROUP_DAP3,
284 TEGRA_DRIVE_PINGROUP_DAP4,
285 TEGRA_DRIVE_PINGROUP_DBG,
286 TEGRA_DRIVE_PINGROUP_LCD1,
287 TEGRA_DRIVE_PINGROUP_LCD2,
288 TEGRA_DRIVE_PINGROUP_SDMMC2,
289 TEGRA_DRIVE_PINGROUP_SDMMC3,
290 TEGRA_DRIVE_PINGROUP_SPI,
291 TEGRA_DRIVE_PINGROUP_UAA,
292 TEGRA_DRIVE_PINGROUP_UAB,
293 TEGRA_DRIVE_PINGROUP_UART2,
294 TEGRA_DRIVE_PINGROUP_UART3,
295 TEGRA_DRIVE_PINGROUP_VI1,
296 TEGRA_DRIVE_PINGROUP_VI2,
297 TEGRA_DRIVE_PINGROUP_XM2A,
298 TEGRA_DRIVE_PINGROUP_XM2C,
299 TEGRA_DRIVE_PINGROUP_XM2D,
300 TEGRA_DRIVE_PINGROUP_XM2CLK,
301 TEGRA_DRIVE_PINGROUP_MEMCOMP,
302 TEGRA_MAX_DRIVE_PINGROUP,
303};
304
305enum tegra_drive { 171enum tegra_drive {
306 TEGRA_DRIVE_DIV_8 = 0, 172 TEGRA_DRIVE_DIV_8 = 0,
307 TEGRA_DRIVE_DIV_4, 173 TEGRA_DRIVE_DIV_4,
@@ -331,18 +197,44 @@ struct tegra_drive_pingroup_config {
331 enum tegra_slew slew_falling; 197 enum tegra_slew slew_falling;
332}; 198};
333 199
334int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func); 200struct tegra_drive_pingroup_desc {
335int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate); 201 const char *name;
336int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, enum tegra_pullupdown pupd); 202 s16 reg;
203};
204
205struct tegra_pingroup_desc {
206 const char *name;
207 int funcs[4];
208 int func_safe;
209 int vddio;
210 s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
211 s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
212 s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
213 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
214 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
215 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
216};
217
218extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
219extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
337 220
338void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup, 221int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
339 enum tegra_mux_func func, enum tegra_pullupdown pupd,
340 enum tegra_tristate tristate); 222 enum tegra_tristate tristate);
223int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
224 enum tegra_pullupdown pupd);
341 225
342void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len); 226void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
227 int len);
343 228
344void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, 229void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
345 int len); 230 int len);
346 231void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
232 int len);
233void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
234 int len);
235void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
236 int len, enum tegra_tristate tristate);
237void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
238 int len, enum tegra_pullupdown pupd);
347#endif 239#endif
348 240
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c
new file mode 100644
index 000000000000..a6ea34e782dc
--- /dev/null
+++ b/arch/arm/mach-tegra/pinmux-t2-tables.c
@@ -0,0 +1,260 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-t2-tables.c
3 *
4 * Common pinmux configurations for Tegra 2 SoCs
5 *
6 * Copyright (C) 2010 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/spinlock.h>
26#include <linux/io.h>
27#include <linux/init.h>
28#include <linux/string.h>
29
30#include <mach/iomap.h>
31#include <mach/pinmux.h>
32
33#define DRIVE_PINGROUP(pg_name, r) \
34 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
35 .name = #pg_name, \
36 .reg = r \
37 }
38
39const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
40 DRIVE_PINGROUP(AO1, 0x868),
41 DRIVE_PINGROUP(AO2, 0x86c),
42 DRIVE_PINGROUP(AT1, 0x870),
43 DRIVE_PINGROUP(AT2, 0x874),
44 DRIVE_PINGROUP(CDEV1, 0x878),
45 DRIVE_PINGROUP(CDEV2, 0x87c),
46 DRIVE_PINGROUP(CSUS, 0x880),
47 DRIVE_PINGROUP(DAP1, 0x884),
48 DRIVE_PINGROUP(DAP2, 0x888),
49 DRIVE_PINGROUP(DAP3, 0x88c),
50 DRIVE_PINGROUP(DAP4, 0x890),
51 DRIVE_PINGROUP(DBG, 0x894),
52 DRIVE_PINGROUP(LCD1, 0x898),
53 DRIVE_PINGROUP(LCD2, 0x89c),
54 DRIVE_PINGROUP(SDMMC2, 0x8a0),
55 DRIVE_PINGROUP(SDMMC3, 0x8a4),
56 DRIVE_PINGROUP(SPI, 0x8a8),
57 DRIVE_PINGROUP(UAA, 0x8ac),
58 DRIVE_PINGROUP(UAB, 0x8b0),
59 DRIVE_PINGROUP(UART2, 0x8b4),
60 DRIVE_PINGROUP(UART3, 0x8b8),
61 DRIVE_PINGROUP(VI1, 0x8bc),
62 DRIVE_PINGROUP(VI2, 0x8c0),
63 DRIVE_PINGROUP(XM2A, 0x8c4),
64 DRIVE_PINGROUP(XM2C, 0x8c8),
65 DRIVE_PINGROUP(XM2D, 0x8cc),
66 DRIVE_PINGROUP(XM2CLK, 0x8d0),
67 DRIVE_PINGROUP(MEMCOMP, 0x8d4),
68};
69
70#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \
71 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
72 [TEGRA_PINGROUP_ ## pg_name] = { \
73 .name = #pg_name, \
74 .vddio = TEGRA_VDDIO_ ## vdd, \
75 .funcs = { \
76 TEGRA_MUX_ ## f0, \
77 TEGRA_MUX_ ## f1, \
78 TEGRA_MUX_ ## f2, \
79 TEGRA_MUX_ ## f3, \
80 }, \
81 .func_safe = TEGRA_MUX_ ## f_safe, \
82 .tri_reg = tri_r, \
83 .tri_bit = tri_b, \
84 .mux_reg = mux_r, \
85 .mux_bit = mux_b, \
86 .pupd_reg = pupd_r, \
87 .pupd_bit = pupd_b, \
88 }
89
90const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
91 PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
92 PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
93 PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
94 PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6),
95 PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8),
96 PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0),
97 PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2),
98 PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24),
99 PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24),
100 PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10),
101 PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12),
102 PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14),
103 PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16),
104 PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28),
105 PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18),
106 PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20),
107 PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22),
108 PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24),
109 PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26),
110 PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28),
111 PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20),
112 PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22),
113 PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24),
114 PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26),
115 PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24),
116 PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20),
117 PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6),
118 PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30),
119 PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22),
120 PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2),
121 PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22),
122 PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20),
123 PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8),
124 PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10),
125 PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12),
126 PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14),
127 PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2),
128 PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0),
129 PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20),
130 PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12),
131 PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12),
132 PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12),
133 PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12),
134 PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12),
135 PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12),
136 PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12),
137 PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12),
138 PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12),
139 PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12),
140 PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12),
141 PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12),
142 PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12),
143 PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12),
144 PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12),
145 PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12),
146 PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12),
147 PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12),
148 PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20),
149 PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18),
150 PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16),
151 PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14),
152 PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14),
153 PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22),
154 PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22),
155 PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22),
156 PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18),
157 PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20),
158 PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20),
159 PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20),
160 PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22),
161 PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20),
162 PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20),
163 PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20),
164 PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20),
165 PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22),
166 PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22),
167 PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16),
168 PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22),
169 PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30),
170 PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
171 PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4),
172 PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0),
173 PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1),
174 PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28),
175 PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30),
176 PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18),
177 PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22),
178 PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26),
179 PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28),
180 PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30),
181 PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16),
182 PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18),
183 PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4),
184 PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6),
185 PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8),
186 PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10),
187 PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12),
188 PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14),
189 PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16),
190 PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18),
191 PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0),
192 PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2),
193 PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4),
194 PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6),
195 PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8),
196 PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10),
197 PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16),
198 /* these pin groups only have pullup and pull down control */
199 PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14),
200 PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26),
201 PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4),
202 PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6),
203 PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8),
204 PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10),
205 PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12),
206 PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
207 PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
208};
209
210#ifdef CONFIG_PM
211#define TRISTATE_REG_A 0x14
212#define TRISTATE_REG_NUM 4
213#define PIN_MUX_CTL_REG_A 0x80
214#define PIN_MUX_CTL_REG_NUM 8
215#define PULLUPDOWN_REG_A 0xa0
216#define PULLUPDOWN_REG_NUM 5
217
218static u32 pinmux_reg[TRISTATE_REG_NUM + PIN_MUX_CTL_REG_NUM +
219 PULLUPDOWN_REG_NUM];
220
221static inline unsigned long pg_readl(unsigned long offset)
222{
223 return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
224}
225
226static inline void pg_writel(unsigned long value, unsigned long offset)
227{
228 writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
229}
230
231void tegra_pinmux_suspend(void)
232{
233 unsigned int i;
234 u32 *ctx = pinmux_reg;
235
236 for (i = 0; i < TRISTATE_REG_NUM; i++)
237 *ctx++ = pg_readl(TRISTATE_REG_A + i*4);
238
239 for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++)
240 *ctx++ = pg_readl(PIN_MUX_CTL_REG_A + i*4);
241
242 for (i = 0; i < PULLUPDOWN_REG_NUM; i++)
243 *ctx++ = pg_readl(PULLUPDOWN_REG_A + i*4);
244}
245
246void tegra_pinmux_resume(void)
247{
248 unsigned int i;
249 u32 *ctx = pinmux_reg;
250
251 for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++)
252 pg_writel(*ctx++, PIN_MUX_CTL_REG_A + i*4);
253
254 for (i = 0; i < PULLUPDOWN_REG_NUM; i++)
255 pg_writel(*ctx++, PULLUPDOWN_REG_A + i*4);
256
257 for (i = 0; i < TRISTATE_REG_NUM; i++)
258 pg_writel(*ctx++, TRISTATE_REG_A + i*4);
259}
260#endif
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 13ae10237e84..f80d507671bc 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -14,7 +14,8 @@
14 * 14 *
15 */ 15 */
16 16
17 17#include <linux/init.h>
18#include <linux/module.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/errno.h> 20#include <linux/errno.h>
20#include <linux/spinlock.h> 21#include <linux/spinlock.h>
@@ -23,21 +24,6 @@
23#include <mach/iomap.h> 24#include <mach/iomap.h>
24#include <mach/pinmux.h> 25#include <mach/pinmux.h>
25 26
26
27#define TEGRA_TRI_STATE(x) (0x14 + (4 * (x)))
28#define TEGRA_PP_MUX_CTL(x) (0x80 + (4 * (x)))
29#define TEGRA_PP_PU_PD(x) (0xa0 + (4 * (x)))
30
31#define REG_A 0
32#define REG_B 1
33#define REG_C 2
34#define REG_D 3
35#define REG_E 4
36#define REG_F 5
37#define REG_G 6
38
39#define REG_N -1
40
41#define HSM_EN(reg) (((reg) >> 2) & 0x1) 27#define HSM_EN(reg) (((reg) >> 2) & 0x1)
42#define SCHMT_EN(reg) (((reg) >> 3) & 0x1) 28#define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
43#define LPMD(reg) (((reg) >> 4) & 0x3) 29#define LPMD(reg) (((reg) >> 4) & 0x3)
@@ -46,154 +32,8 @@
46#define SLWR(reg) (((reg) >> 28) & 0x3) 32#define SLWR(reg) (((reg) >> 28) & 0x3)
47#define SLWF(reg) (((reg) >> 30) & 0x3) 33#define SLWF(reg) (((reg) >> 30) & 0x3)
48 34
49struct tegra_pingroup_desc { 35static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
50 const char *name; 36static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
51 int funcs[4];
52 s8 tri_reg; /* offset into the TRISTATE_REG_* register bank */
53 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
54 s8 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
55 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
56 s8 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
57 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
58};
59
60#define PINGROUP(pg_name, f0, f1, f2, f3, \
61 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
62 [TEGRA_PINGROUP_ ## pg_name] = { \
63 .name = #pg_name, \
64 .funcs = { \
65 TEGRA_MUX_ ## f0, \
66 TEGRA_MUX_ ## f1, \
67 TEGRA_MUX_ ## f2, \
68 TEGRA_MUX_ ## f3, \
69 }, \
70 .tri_reg = REG_ ## tri_r, \
71 .tri_bit = tri_b, \
72 .mux_reg = REG_ ## mux_r, \
73 .mux_bit = mux_b, \
74 .pupd_reg = REG_ ## pupd_r, \
75 .pupd_bit = pupd_b, \
76 }
77
78static const struct tegra_pingroup_desc pingroups[TEGRA_MAX_PINGROUP] = {
79 PINGROUP(ATA, IDE, NAND, GMI, RSVD, A, 0, A, 24, A, 0),
80 PINGROUP(ATB, IDE, NAND, GMI, SDIO4, A, 1, A, 16, A, 2),
81 PINGROUP(ATC, IDE, NAND, GMI, SDIO4, A, 2, A, 22, A, 4),
82 PINGROUP(ATD, IDE, NAND, GMI, SDIO4, A, 3, A, 20, A, 6),
83 PINGROUP(ATE, IDE, NAND, GMI, RSVD, B, 25, A, 12, A, 8),
84 PINGROUP(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, A, 4, C, 2, C, 0),
85 PINGROUP(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, A, 5, C, 4, C, 2),
86 PINGROUP(CRTP, CRT, RSVD, RSVD, RSVD, D, 14, G, 20, B, 24),
87 PINGROUP(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, A, 6, C, 6, D, 24),
88 PINGROUP(DAP1, DAP1, RSVD, GMI, SDIO2, A, 7, C, 20, A, 10),
89 PINGROUP(DAP2, DAP2, TWC, RSVD, GMI, A, 8, C, 22, A, 12),
90 PINGROUP(DAP3, DAP3, RSVD, RSVD, RSVD, A, 9, C, 24, A, 14),
91 PINGROUP(DAP4, DAP4, RSVD, GMI, RSVD, A, 10, C, 26, A, 16),
92 PINGROUP(DDC, I2C2, RSVD, RSVD, RSVD, B, 31, C, 0, E, 28),
93 PINGROUP(DTA, RSVD, SDIO2, VI, RSVD, A, 11, B, 20, A, 18),
94 PINGROUP(DTB, RSVD, RSVD, VI, SPI1, A, 12, B, 22, A, 20),
95 PINGROUP(DTC, RSVD, RSVD, VI, RSVD, A, 13, B, 26, A, 22),
96 PINGROUP(DTD, RSVD, SDIO2, VI, RSVD, A, 14, B, 28, A, 24),
97 PINGROUP(DTE, RSVD, RSVD, VI, SPI1, A, 15, B, 30, A, 26),
98 PINGROUP(DTF, I2C3, RSVD, VI, RSVD, D, 12, G, 30, A, 28),
99 PINGROUP(GMA, UARTE, SPI3, GMI, SDIO4, A, 28, B, 0, E, 20),
100 PINGROUP(GMB, IDE, NAND, GMI, GMI_INT, B, 29, C, 28, E, 22),
101 PINGROUP(GMC, UARTD, SPI4, GMI, SFLASH, A, 29, B, 2, E, 24),
102 PINGROUP(GMD, RSVD, NAND, GMI, SFLASH, B, 30, C, 30, E, 26),
103 PINGROUP(GME, RSVD, DAP5, GMI, SDIO4, B, 0, D, 0, C, 24),
104 PINGROUP(GPU, PWM, UARTA, GMI, RSVD, A, 16, D, 4, B, 20),
105 PINGROUP(GPU7, RTCK, RSVD, RSVD, RSVD, D, 11, G, 28, B, 6),
106 PINGROUP(GPV, PCIE, RSVD, RSVD, RSVD, A, 17, D, 2, A, 30),
107 PINGROUP(HDINT, HDMI, RSVD, RSVD, RSVD, C, 23, B, 4, D, 22),
108 PINGROUP(I2CP, I2C, RSVD, RSVD, RSVD, A, 18, C, 8, B, 2),
109 PINGROUP(IRRX, UARTA, UARTB, GMI, SPI4, A, 20, C, 18, C, 22),
110 PINGROUP(IRTX, UARTA, UARTB, GMI, SPI4, A, 19, C, 16, C, 20),
111 PINGROUP(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL, A, 22, C, 10, B, 8),
112 PINGROUP(KBCB, KBC, NAND, SDIO2, MIO, A, 21, C, 12, B, 10),
113 PINGROUP(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL, B, 26, C, 14, B, 12),
114 PINGROUP(KBCD, KBC, NAND, SDIO2, MIO, D, 10, G, 26, B, 14),
115 PINGROUP(KBCE, KBC, NAND, OWR, RSVD, A, 26, A, 28, E, 2),
116 PINGROUP(KBCF, KBC, NAND, TRACE, MIO, A, 27, A, 26, E, 0),
117 PINGROUP(LCSN, DISPLAYA, DISPLAYB, SPI3, RSVD, C, 31, E, 12, D, 20),
118 PINGROUP(LD0, DISPLAYA, DISPLAYB, XIO, RSVD, C, 0, F, 0, D, 12),
119 PINGROUP(LD1, DISPLAYA, DISPLAYB, XIO, RSVD, C, 1, F, 2, D, 12),
120 PINGROUP(LD10, DISPLAYA, DISPLAYB, XIO, RSVD, C, 10, F, 20, D, 12),
121 PINGROUP(LD11, DISPLAYA, DISPLAYB, XIO, RSVD, C, 11, F, 22, D, 12),
122 PINGROUP(LD12, DISPLAYA, DISPLAYB, XIO, RSVD, C, 12, F, 24, D, 12),
123 PINGROUP(LD13, DISPLAYA, DISPLAYB, XIO, RSVD, C, 13, F, 26, D, 12),
124 PINGROUP(LD14, DISPLAYA, DISPLAYB, XIO, RSVD, C, 14, F, 28, D, 12),
125 PINGROUP(LD15, DISPLAYA, DISPLAYB, XIO, RSVD, C, 15, F, 30, D, 12),
126 PINGROUP(LD16, DISPLAYA, DISPLAYB, XIO, RSVD, C, 16, G, 0, D, 12),
127 PINGROUP(LD17, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 17, G, 2, D, 12),
128 PINGROUP(LD2, DISPLAYA, DISPLAYB, XIO, RSVD, C, 2, F, 4, D, 12),
129 PINGROUP(LD3, DISPLAYA, DISPLAYB, XIO, RSVD, C, 3, F, 6, D, 12),
130 PINGROUP(LD4, DISPLAYA, DISPLAYB, XIO, RSVD, C, 4, F, 8, D, 12),
131 PINGROUP(LD5, DISPLAYA, DISPLAYB, XIO, RSVD, C, 5, F, 10, D, 12),
132 PINGROUP(LD6, DISPLAYA, DISPLAYB, XIO, RSVD, C, 6, F, 12, D, 12),
133 PINGROUP(LD7, DISPLAYA, DISPLAYB, XIO, RSVD, C, 7, F, 14, D, 12),
134 PINGROUP(LD8, DISPLAYA, DISPLAYB, XIO, RSVD, C, 8, F, 16, D, 12),
135 PINGROUP(LD9, DISPLAYA, DISPLAYB, XIO, RSVD, C, 9, F, 18, D, 12),
136 PINGROUP(LDC, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 30, E, 14, D, 20),
137 PINGROUP(LDI, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 6, G, 16, D, 18),
138 PINGROUP(LHP0, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 18, G, 10, D, 16),
139 PINGROUP(LHP1, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 19, G, 4, D, 14),
140 PINGROUP(LHP2, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 20, G, 6, D, 14),
141 PINGROUP(LHS, DISPLAYA, DISPLAYB, XIO, RSVD, D, 7, E, 22, D, 22),
142 PINGROUP(LM0, DISPLAYA, DISPLAYB, SPI3, RSVD, C, 24, E, 26, D, 22),
143 PINGROUP(LM1, DISPLAYA, DISPLAYB, RSVD, CRT, C, 25, E, 28, D, 22),
144 PINGROUP(LPP, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 8, G, 14, D, 18),
145 PINGROUP(LPW0, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 3, E, 0, D, 20),
146 PINGROUP(LPW1, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 4, E, 2, D, 20),
147 PINGROUP(LPW2, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 5, E, 4, D, 20),
148 PINGROUP(LSC0, DISPLAYA, DISPLAYB, XIO, RSVD, C, 27, E, 18, D, 22),
149 PINGROUP(LSC1, DISPLAYA, DISPLAYB, SPI3, HDMI, C, 28, E, 20, D, 20),
150 PINGROUP(LSCK, DISPLAYA, DISPLAYB, SPI3, HDMI, C, 29, E, 16, D, 20),
151 PINGROUP(LSDA, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 1, E, 8, D, 20),
152 PINGROUP(LSDI, DISPLAYA, DISPLAYB, SPI3, RSVD, D, 2, E, 6, D, 20),
153 PINGROUP(LSPI, DISPLAYA, DISPLAYB, XIO, HDMI, D, 0, E, 10, D, 22),
154 PINGROUP(LVP0, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 21, E, 30, D, 22),
155 PINGROUP(LVP1, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 22, G, 8, D, 16),
156 PINGROUP(LVS, DISPLAYA, DISPLAYB, XIO, RSVD, C, 26, E, 24, D, 22),
157 PINGROUP(OWC, OWR, RSVD, RSVD, RSVD, A, 31, B, 8, E, 30),
158 PINGROUP(PMC, PWR_ON, PWR_INTR, RSVD, RSVD, A, 23, G, 18, N, -1),
159 PINGROUP(PTA, I2C2, HDMI, GMI, RSVD, A, 24, G, 22, B, 4),
160 PINGROUP(RM, I2C, RSVD, RSVD, RSVD, A, 25, A, 14, B, 0),
161 PINGROUP(SDB, UARTA, PWM, SDIO3, SPI2, D, 15, D, 10, N, -1),
162 PINGROUP(SDC, PWM, TWC, SDIO3, SPI3, B, 1, D, 12, D, 28),
163 PINGROUP(SDD, UARTA, PWM, SDIO3, SPI3, B, 2, D, 14, D, 30),
164 PINGROUP(SDIO1, SDIO1, RSVD, UARTE, UARTA, A, 30, A, 30, E, 18),
165 PINGROUP(SLXA, PCIE, SPI4, SDIO3, SPI2, B, 3, B, 6, B, 22),
166 PINGROUP(SLXC, SPDIF, SPI4, SDIO3, SPI2, B, 5, B, 10, B, 26),
167 PINGROUP(SLXD, SPDIF, SPI4, SDIO3, SPI2, B, 6, B, 12, B, 28),
168 PINGROUP(SLXK, PCIE, SPI4, SDIO3, SPI2, B, 7, B, 14, B, 30),
169 PINGROUP(SPDI, SPDIF, RSVD, I2C, SDIO2, B, 8, D, 8, B, 16),
170 PINGROUP(SPDO, SPDIF, RSVD, I2C, SDIO2, B, 9, D, 6, B, 18),
171 PINGROUP(SPIA, SPI1, SPI2, SPI3, GMI, B, 10, D, 30, C, 4),
172 PINGROUP(SPIB, SPI1, SPI2, SPI3, GMI, B, 11, D, 28, C, 6),
173 PINGROUP(SPIC, SPI1, SPI2, SPI3, GMI, B, 12, D, 26, C, 8),
174 PINGROUP(SPID, SPI2, SPI1, SPI2_ALT, GMI, B, 13, D, 24, C, 10),
175 PINGROUP(SPIE, SPI2, SPI1, SPI2_ALT, GMI, B, 14, D, 22, C, 12),
176 PINGROUP(SPIF, SPI3, SPI1, SPI2, RSVD, B, 15, D, 20, C, 14),
177 PINGROUP(SPIG, SPI3, SPI2, SPI2_ALT, I2C, B, 16, D, 18, C, 16),
178 PINGROUP(SPIH, SPI3, SPI2, SPI2_ALT, I2C, B, 17, D, 16, C, 18),
179 PINGROUP(UAA, SPI3, MIPI_HS, UARTA, ULPI, B, 18, A, 0, D, 0),
180 PINGROUP(UAB, SPI2, MIPI_HS, UARTA, ULPI, B, 19, A, 2, D, 2),
181 PINGROUP(UAC, OWR, RSVD, RSVD, RSVD, B, 20, A, 4, D, 4),
182 PINGROUP(UAD, IRDA, SPDIF, UARTA, SPI4, B, 21, A, 6, D, 6),
183 PINGROUP(UCA, UARTC, RSVD, GMI, RSVD, B, 22, B, 16, D, 8),
184 PINGROUP(UCB, UARTC, PWM, GMI, RSVD, B, 23, B, 18, D, 10),
185 PINGROUP(UDA, SPI1, RSVD, UARTD, ULPI, D, 13, A, 8, E, 16),
186 /* these pin groups only have pullup and pull down control */
187 PINGROUP(CK32, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 14),
188 PINGROUP(DDRC, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, D, 26),
189 PINGROUP(PMCA, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 4),
190 PINGROUP(PMCB, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 6),
191 PINGROUP(PMCC, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 8),
192 PINGROUP(PMCD, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 10),
193 PINGROUP(PMCE, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 12),
194 PINGROUP(XM2C, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, C, 30),
195 PINGROUP(XM2D, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, C, 28),
196};
197 37
198static char *tegra_mux_names[TEGRA_MAX_MUX] = { 38static char *tegra_mux_names[TEGRA_MAX_MUX] = {
199 [TEGRA_MUX_AHB_CLK] = "AHB_CLK", 39 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
@@ -256,48 +96,7 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = {
256 [TEGRA_MUX_VI] = "VI", 96 [TEGRA_MUX_VI] = "VI",
257 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", 97 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
258 [TEGRA_MUX_XIO] = "XIO", 98 [TEGRA_MUX_XIO] = "XIO",
259}; 99 [TEGRA_MUX_SAFE] = "<safe>",
260
261struct tegra_drive_pingroup_desc {
262 const char *name;
263 s16 reg;
264};
265
266#define DRIVE_PINGROUP(pg_name, r) \
267 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
268 .name = #pg_name, \
269 .reg = r \
270 }
271
272static const struct tegra_drive_pingroup_desc drive_pingroups[TEGRA_MAX_PINGROUP] = {
273 DRIVE_PINGROUP(AO1, 0x868),
274 DRIVE_PINGROUP(AO2, 0x86c),
275 DRIVE_PINGROUP(AT1, 0x870),
276 DRIVE_PINGROUP(AT2, 0x874),
277 DRIVE_PINGROUP(CDEV1, 0x878),
278 DRIVE_PINGROUP(CDEV2, 0x87c),
279 DRIVE_PINGROUP(CSUS, 0x880),
280 DRIVE_PINGROUP(DAP1, 0x884),
281 DRIVE_PINGROUP(DAP2, 0x888),
282 DRIVE_PINGROUP(DAP3, 0x88c),
283 DRIVE_PINGROUP(DAP4, 0x890),
284 DRIVE_PINGROUP(DBG, 0x894),
285 DRIVE_PINGROUP(LCD1, 0x898),
286 DRIVE_PINGROUP(LCD2, 0x89c),
287 DRIVE_PINGROUP(SDMMC2, 0x8a0),
288 DRIVE_PINGROUP(SDMMC3, 0x8a4),
289 DRIVE_PINGROUP(SPI, 0x8a8),
290 DRIVE_PINGROUP(UAA, 0x8ac),
291 DRIVE_PINGROUP(UAB, 0x8b0),
292 DRIVE_PINGROUP(UART2, 0x8b4),
293 DRIVE_PINGROUP(UART3, 0x8b8),
294 DRIVE_PINGROUP(VI1, 0x8bc),
295 DRIVE_PINGROUP(VI2, 0x8c0),
296 DRIVE_PINGROUP(XM2A, 0x8c4),
297 DRIVE_PINGROUP(XM2C, 0x8c8),
298 DRIVE_PINGROUP(XM2D, 0x8cc),
299 DRIVE_PINGROUP(XM2CLK, 0x8d0),
300 DRIVE_PINGROUP(MEMCOMP, 0x8d4),
301}; 100};
302 101
303static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = { 102static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
@@ -381,22 +180,27 @@ static inline void pg_writel(unsigned long value, unsigned long offset)
381 writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); 180 writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
382} 181}
383 182
384int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func) 183static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
385{ 184{
386 int mux = -1; 185 int mux = -1;
387 int i; 186 int i;
388 unsigned long reg; 187 unsigned long reg;
389 unsigned long flags; 188 unsigned long flags;
189 enum tegra_pingroup pg = config->pingroup;
190 enum tegra_mux_func func = config->func;
390 191
391 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 192 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
392 return -ERANGE; 193 return -ERANGE;
393 194
394 if (pingroups[pg].mux_reg == REG_N) 195 if (pingroups[pg].mux_reg < 0)
395 return -EINVAL; 196 return -EINVAL;
396 197
397 if (func < 0) 198 if (func < 0)
398 return -ERANGE; 199 return -ERANGE;
399 200
201 if (func == TEGRA_MUX_SAFE)
202 func = pingroups[pg].func_safe;
203
400 if (func & TEGRA_MUX_RSVD) { 204 if (func & TEGRA_MUX_RSVD) {
401 mux = func & 0x3; 205 mux = func & 0x3;
402 } else { 206 } else {
@@ -413,10 +217,10 @@ int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func)
413 217
414 spin_lock_irqsave(&mux_lock, flags); 218 spin_lock_irqsave(&mux_lock, flags);
415 219
416 reg = pg_readl(TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg)); 220 reg = pg_readl(pingroups[pg].mux_reg);
417 reg &= ~(0x3 << pingroups[pg].mux_bit); 221 reg &= ~(0x3 << pingroups[pg].mux_bit);
418 reg |= mux << pingroups[pg].mux_bit; 222 reg |= mux << pingroups[pg].mux_bit;
419 pg_writel(reg, TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg)); 223 pg_writel(reg, pingroups[pg].mux_reg);
420 224
421 spin_unlock_irqrestore(&mux_lock, flags); 225 spin_unlock_irqrestore(&mux_lock, flags);
422 226
@@ -432,16 +236,16 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
432 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 236 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
433 return -ERANGE; 237 return -ERANGE;
434 238
435 if (pingroups[pg].tri_reg == REG_N) 239 if (pingroups[pg].tri_reg < 0)
436 return -EINVAL; 240 return -EINVAL;
437 241
438 spin_lock_irqsave(&mux_lock, flags); 242 spin_lock_irqsave(&mux_lock, flags);
439 243
440 reg = pg_readl(TEGRA_TRI_STATE(pingroups[pg].tri_reg)); 244 reg = pg_readl(pingroups[pg].tri_reg);
441 reg &= ~(0x1 << pingroups[pg].tri_bit); 245 reg &= ~(0x1 << pingroups[pg].tri_bit);
442 if (tristate) 246 if (tristate)
443 reg |= 1 << pingroups[pg].tri_bit; 247 reg |= 1 << pingroups[pg].tri_bit;
444 pg_writel(reg, TEGRA_TRI_STATE(pingroups[pg].tri_reg)); 248 pg_writel(reg, pingroups[pg].tri_reg);
445 249
446 spin_unlock_irqrestore(&mux_lock, flags); 250 spin_unlock_irqrestore(&mux_lock, flags);
447 251
@@ -457,7 +261,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
457 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 261 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
458 return -ERANGE; 262 return -ERANGE;
459 263
460 if (pingroups[pg].pupd_reg == REG_N) 264 if (pingroups[pg].pupd_reg < 0)
461 return -EINVAL; 265 return -EINVAL;
462 266
463 if (pupd != TEGRA_PUPD_NORMAL && 267 if (pupd != TEGRA_PUPD_NORMAL &&
@@ -468,38 +272,39 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
468 272
469 spin_lock_irqsave(&mux_lock, flags); 273 spin_lock_irqsave(&mux_lock, flags);
470 274
471 reg = pg_readl(TEGRA_PP_PU_PD(pingroups[pg].pupd_reg)); 275 reg = pg_readl(pingroups[pg].pupd_reg);
472 reg &= ~(0x3 << pingroups[pg].pupd_bit); 276 reg &= ~(0x3 << pingroups[pg].pupd_bit);
473 reg |= pupd << pingroups[pg].pupd_bit; 277 reg |= pupd << pingroups[pg].pupd_bit;
474 pg_writel(reg, TEGRA_PP_PU_PD(pingroups[pg].pupd_reg)); 278 pg_writel(reg, pingroups[pg].pupd_reg);
475 279
476 spin_unlock_irqrestore(&mux_lock, flags); 280 spin_unlock_irqrestore(&mux_lock, flags);
477 281
478 return 0; 282 return 0;
479} 283}
480 284
481void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup, 285static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
482 enum tegra_mux_func func,
483 enum tegra_pullupdown pupd,
484 enum tegra_tristate tristate)
485{ 286{
287 enum tegra_pingroup pingroup = config->pingroup;
288 enum tegra_mux_func func = config->func;
289 enum tegra_pullupdown pupd = config->pupd;
290 enum tegra_tristate tristate = config->tristate;
486 int err; 291 int err;
487 292
488 if (pingroups[pingroup].mux_reg != REG_N) { 293 if (pingroups[pingroup].mux_reg >= 0) {
489 err = tegra_pinmux_set_func(pingroup, func); 294 err = tegra_pinmux_set_func(config);
490 if (err < 0) 295 if (err < 0)
491 pr_err("pinmux: can't set pingroup %s func to %s: %d\n", 296 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
492 pingroup_name(pingroup), func_name(func), err); 297 pingroup_name(pingroup), func_name(func), err);
493 } 298 }
494 299
495 if (pingroups[pingroup].pupd_reg != REG_N) { 300 if (pingroups[pingroup].pupd_reg >= 0) {
496 err = tegra_pinmux_set_pullupdown(pingroup, pupd); 301 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
497 if (err < 0) 302 if (err < 0)
498 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n", 303 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
499 pingroup_name(pingroup), pupd_name(pupd), err); 304 pingroup_name(pingroup), pupd_name(pupd), err);
500 } 305 }
501 306
502 if (pingroups[pingroup].tri_reg != REG_N) { 307 if (pingroups[pingroup].tri_reg >= 0) {
503 err = tegra_pinmux_set_tristate(pingroup, tristate); 308 err = tegra_pinmux_set_tristate(pingroup, tristate);
504 if (err < 0) 309 if (err < 0)
505 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n", 310 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
@@ -507,17 +312,12 @@ void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
507 } 312 }
508} 313}
509 314
510 315void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
511
512void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len)
513{ 316{
514 int i; 317 int i;
515 318
516 for (i = 0; i < len; i++) 319 for (i = 0; i < len; i++)
517 tegra_pinmux_config_pingroup(config[i].pingroup, 320 tegra_pinmux_config_pingroup(&config[i]);
518 config[i].func,
519 config[i].pupd,
520 config[i].tristate);
521} 321}
522 322
523static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) 323static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
@@ -784,6 +584,86 @@ void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
784 config[i].slew_falling); 584 config[i].slew_falling);
785} 585}
786 586
587void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
588 int len)
589{
590 int i;
591 struct tegra_pingroup_config c;
592
593 for (i = 0; i < len; i++) {
594 int err;
595 c = config[i];
596 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
597 WARN_ON(1);
598 continue;
599 }
600 c.func = pingroups[c.pingroup].func_safe;
601 err = tegra_pinmux_set_func(&c);
602 if (err < 0)
603 pr_err("%s: tegra_pinmux_set_func returned %d setting "
604 "%s to %s\n", __func__, err,
605 pingroup_name(c.pingroup), func_name(c.func));
606 }
607}
608
609void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
610 int len)
611{
612 int i;
613
614 for (i = 0; i < len; i++) {
615 int err;
616 if (config[i].pingroup < 0 ||
617 config[i].pingroup >= TEGRA_MAX_PINGROUP) {
618 WARN_ON(1);
619 continue;
620 }
621 err = tegra_pinmux_set_func(&config[i]);
622 if (err < 0)
623 pr_err("%s: tegra_pinmux_set_func returned %d setting "
624 "%s to %s\n", __func__, err,
625 pingroup_name(config[i].pingroup),
626 func_name(config[i].func));
627 }
628}
629
630void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
631 int len, enum tegra_tristate tristate)
632{
633 int i;
634 int err;
635 enum tegra_pingroup pingroup;
636
637 for (i = 0; i < len; i++) {
638 pingroup = config[i].pingroup;
639 if (pingroups[pingroup].tri_reg >= 0) {
640 err = tegra_pinmux_set_tristate(pingroup, tristate);
641 if (err < 0)
642 pr_err("pinmux: can't set pingroup %s tristate"
643 " to %s: %d\n", pingroup_name(pingroup),
644 tri_name(tristate), err);
645 }
646 }
647}
648
649void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
650 int len, enum tegra_pullupdown pupd)
651{
652 int i;
653 int err;
654 enum tegra_pingroup pingroup;
655
656 for (i = 0; i < len; i++) {
657 pingroup = config[i].pingroup;
658 if (pingroups[pingroup].pupd_reg >= 0) {
659 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
660 if (err < 0)
661 pr_err("pinmux: can't set pingroup %s pullupdown"
662 " to %s: %d\n", pingroup_name(pingroup),
663 pupd_name(pupd), err);
664 }
665 }
666}
787 667
788#ifdef CONFIG_DEBUG_FS 668#ifdef CONFIG_DEBUG_FS
789 669
@@ -812,11 +692,11 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
812 len = strlen(pingroups[i].name); 692 len = strlen(pingroups[i].name);
813 dbg_pad_field(s, 5 - len); 693 dbg_pad_field(s, 5 - len);
814 694
815 if (pingroups[i].mux_reg == REG_N) { 695 if (pingroups[i].mux_reg < 0) {
816 seq_printf(s, "TEGRA_MUX_NONE"); 696 seq_printf(s, "TEGRA_MUX_NONE");
817 len = strlen("NONE"); 697 len = strlen("NONE");
818 } else { 698 } else {
819 mux = (pg_readl(TEGRA_PP_MUX_CTL(pingroups[i].mux_reg)) >> 699 mux = (pg_readl(pingroups[i].mux_reg) >>
820 pingroups[i].mux_bit) & 0x3; 700 pingroups[i].mux_bit) & 0x3;
821 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) { 701 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
822 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1); 702 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
@@ -829,21 +709,21 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
829 } 709 }
830 dbg_pad_field(s, 13-len); 710 dbg_pad_field(s, 13-len);
831 711
832 if (pingroups[i].mux_reg == REG_N) { 712 if (pingroups[i].pupd_reg < 0) {
833 seq_printf(s, "TEGRA_PUPD_NORMAL"); 713 seq_printf(s, "TEGRA_PUPD_NORMAL");
834 len = strlen("NORMAL"); 714 len = strlen("NORMAL");
835 } else { 715 } else {
836 pupd = (pg_readl(TEGRA_PP_PU_PD(pingroups[i].pupd_reg)) >> 716 pupd = (pg_readl(pingroups[i].pupd_reg) >>
837 pingroups[i].pupd_bit) & 0x3; 717 pingroups[i].pupd_bit) & 0x3;
838 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd)); 718 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
839 len = strlen(pupd_name(pupd)); 719 len = strlen(pupd_name(pupd));
840 } 720 }
841 dbg_pad_field(s, 9 - len); 721 dbg_pad_field(s, 9 - len);
842 722
843 if (pingroups[i].tri_reg == REG_N) { 723 if (pingroups[i].tri_reg < 0) {
844 seq_printf(s, "TEGRA_TRI_NORMAL"); 724 seq_printf(s, "TEGRA_TRI_NORMAL");
845 } else { 725 } else {
846 tri = (pg_readl(TEGRA_TRI_STATE(pingroups[i].tri_reg)) >> 726 tri = (pg_readl(pingroups[i].tri_reg) >>
847 pingroups[i].tri_bit) & 0x1; 727 pingroups[i].tri_bit) & 0x1;
848 728
849 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri)); 729 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-19 19:56:46 -0500