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authorLinus Torvalds <torvalds@linux-foundation.org>2010-05-25 15:03:17 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-05-25 15:03:17 -0400
commitc19eb8f0d1bd442ed1aff0b413dd822620771c29 (patch)
tree607a1a99f24c484e68e60526c03a518c5f3799b5
parent99765cc7e393c8637abaaf0c73f28ec63370d35c (diff)
parent724b62b5f73e7d17c737ddb879e0543c886b20ce (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: arch/m68knommu/platform/68360/commproc.c: Checkpatch cleanup arch/m68knommu/mm/fault.c: Checkpatch cleanup m68knommu: improve short help of m68knommu/Kconfig/RAMSIZE for '0' case m68knommu: remove un-used mcfsmc.h m68knommu: add smc91x support for ColdFire NETtel boards m68knommu: add smc91x support to ColdFire 5249 platform m68knommu: remove size limit on non-MMU TASK_SIZE m68knommu: fix broken use of BUAD_TABLE_SIZE in 68328serial driver m68knommu: Coldfire QSPI platform support
Diffstat
-rw-r--r--arch/m68k/include/asm/m520xsim.h1
-rw-r--r--arch/m68k/include/asm/m523xsim.h5
-rw-r--r--arch/m68k/include/asm/m5249sim.h2
-rw-r--r--arch/m68k/include/asm/m527xsim.h7
-rw-r--r--arch/m68k/include/asm/m528xsim.h67
-rw-r--r--arch/m68k/include/asm/m532xsim.h1
-rw-r--r--arch/m68k/include/asm/mcfqspi.h64
-rw-r--r--arch/m68k/include/asm/mcfsmc.h187
-rw-r--r--arch/m68k/include/asm/processor.h4
-rw-r--r--arch/m68knommu/Kconfig2
-rw-r--r--arch/m68knommu/mm/fault.c10
-rw-r--r--arch/m68knommu/platform/520x/config.c149
-rw-r--r--arch/m68knommu/platform/523x/config.c170
-rw-r--r--arch/m68knommu/platform/5249/config.c215
-rw-r--r--arch/m68knommu/platform/527x/config.c182
-rw-r--r--arch/m68knommu/platform/528x/config.c137
-rw-r--r--arch/m68knommu/platform/5307/Makefile4
-rw-r--r--arch/m68knommu/platform/5307/nettel.c153
-rw-r--r--arch/m68knommu/platform/532x/config.c124
-rw-r--r--arch/m68knommu/platform/68360/commproc.c4
20 files changed, 1226 insertions, 262 deletions
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index ed2b69b96805..db824a4b136e 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -113,6 +113,7 @@
113 113
114#define MCF_GPIO_PAR_UART (0xA4036) 114#define MCF_GPIO_PAR_UART (0xA4036)
115#define MCF_GPIO_PAR_FECI2C (0xA4033) 115#define MCF_GPIO_PAR_FECI2C (0xA4033)
116#define MCF_GPIO_PAR_QSPI (0xA4034)
116#define MCF_GPIO_PAR_FEC (0xA4038) 117#define MCF_GPIO_PAR_FEC (0xA4038)
117 118
118#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 119#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index a34894cf8e6f..e8d06b24a48e 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -127,5 +127,10 @@
127#define MCFGPIO_IRQ_MAX 8 127#define MCFGPIO_IRQ_MAX 8
128#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 128#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
129 129
130/*
131 * Pin Assignment
132*/
133#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
134#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
130/****************************************************************************/ 135/****************************************************************************/
131#endif /* m523xsim_h */ 136#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 14bce877ed88..79b7b402f3c9 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -69,10 +69,12 @@
69#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 69#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
70#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 70#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
72#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
72 73
73/* 74/*
74 * Define system peripheral IRQ usage. 75 * Define system peripheral IRQ usage.
75 */ 76 */
77#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
76#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 78#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
77#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 79#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
78 80
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 453356d72d80..1feb46f108ce 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -31,6 +31,7 @@
31#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 31#define MCFINT_UART0 13 /* Interrupt number for UART0 */
32#define MCFINT_UART1 14 /* Interrupt number for UART1 */ 32#define MCFINT_UART1 14 /* Interrupt number for UART1 */
33#define MCFINT_UART2 15 /* Interrupt number for UART2 */ 33#define MCFINT_UART2 15 /* Interrupt number for UART2 */
34#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
34#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 35#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
35 36
36/* 37/*
@@ -120,6 +121,9 @@
120#define MCFGPIO_PIN_MAX 100 121#define MCFGPIO_PIN_MAX 100
121#define MCFGPIO_IRQ_MAX 8 122#define MCFGPIO_IRQ_MAX 8
122#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 123#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
124
125#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
126#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
123#endif 127#endif
124 128
125#ifdef CONFIG_M5275 129#ifdef CONFIG_M5275
@@ -212,6 +216,8 @@
212#define MCFGPIO_PIN_MAX 148 216#define MCFGPIO_PIN_MAX 148
213#define MCFGPIO_IRQ_MAX 8 217#define MCFGPIO_IRQ_MAX 8
214#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 218#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
219
220#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
215#endif 221#endif
216 222
217/* 223/*
@@ -223,6 +229,7 @@
223#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 229#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
224 230
225 231
232
226/* 233/*
227 * GPIO pins setups to enable the UARTs. 234 * GPIO pins setups to enable the UARTs.
228 */ 235 */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index e2ad1f42b657..891cbedad972 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -29,6 +29,7 @@
29 29
30#define MCFINT_VECBASE 64 /* Vector base number */ 30#define MCFINT_VECBASE 64 /* Vector base number */
31#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 31#define MCFINT_UART0 13 /* Interrupt number for UART0 */
32#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
32#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ 33#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
33 34
34/* 35/*
@@ -249,70 +250,4 @@
249#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge 250#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
250 251
251 252
252
253/*********************************************************************
254*
255* Queued Serial Peripheral Interface (QSPI) Module
256*
257*********************************************************************/
258/* Derek - 21 Feb 2005 */
259/* change to the format used in I2C */
260/* Read/Write access macros for general use */
261#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340
262#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344
263#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348
264#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C
265#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350
266#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354
267#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354
268
269/* Bit level definitions and macros */
270#define MCF5282_QSPI_QMR_MSTR (0x8000)
271#define MCF5282_QSPI_QMR_DOHIE (0x4000)
272#define MCF5282_QSPI_QMR_BITS_16 (0x0000)
273#define MCF5282_QSPI_QMR_BITS_8 (0x2000)
274#define MCF5282_QSPI_QMR_BITS_9 (0x2400)
275#define MCF5282_QSPI_QMR_BITS_10 (0x2800)
276#define MCF5282_QSPI_QMR_BITS_11 (0x2C00)
277#define MCF5282_QSPI_QMR_BITS_12 (0x3000)
278#define MCF5282_QSPI_QMR_BITS_13 (0x3400)
279#define MCF5282_QSPI_QMR_BITS_14 (0x3800)
280#define MCF5282_QSPI_QMR_BITS_15 (0x3C00)
281#define MCF5282_QSPI_QMR_CPOL (0x0200)
282#define MCF5282_QSPI_QMR_CPHA (0x0100)
283#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF))
284
285#define MCF5282_QSPI_QDLYR_SPE (0x80)
286#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
287#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
288
289#define MCF5282_QSPI_QWR_HALT (0x8000)
290#define MCF5282_QSPI_QWR_WREN (0x4000)
291#define MCF5282_QSPI_QWR_WRTO (0x2000)
292#define MCF5282_QSPI_QWR_CSIV (0x1000)
293#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
294#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
295#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F))
296
297#define MCF5282_QSPI_QIR_WCEFB (0x8000)
298#define MCF5282_QSPI_QIR_ABRTB (0x4000)
299#define MCF5282_QSPI_QIR_ABRTL (0x1000)
300#define MCF5282_QSPI_QIR_WCEFE (0x0800)
301#define MCF5282_QSPI_QIR_ABRTE (0x0400)
302#define MCF5282_QSPI_QIR_SPIFE (0x0100)
303#define MCF5282_QSPI_QIR_WCEF (0x0008)
304#define MCF5282_QSPI_QIR_ABRT (0x0004)
305#define MCF5282_QSPI_QIR_SPIF (0x0001)
306
307#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F))
308
309#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00))
310#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8)
311#define MCF5282_QSPI_QCR_CONT (0x8000)
312#define MCF5282_QSPI_QCR_BITSE (0x4000)
313#define MCF5282_QSPI_QCR_DT (0x2000)
314#define MCF5282_QSPI_QCR_DSCK (0x1000)
315#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8)
316
317/****************************************************************************/
318#endif /* m528xsim_h */ 253#endif /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 36bf15aec9ae..c4bf1c81e3cf 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -17,6 +17,7 @@
17#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 17#define MCFINT_UART0 26 /* Interrupt number for UART0 */
18#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 18#define MCFINT_UART1 27 /* Interrupt number for UART1 */
19#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 19#define MCFINT_UART2 28 /* Interrupt number for UART2 */
20#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
20 21
21#define MCF_WTM_WCR MCF_REG16(0xFC098000) 22#define MCF_WTM_WCR MCF_REG16(0xFC098000)
22 23
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
new file mode 100644
index 000000000000..39d90d51111d
--- /dev/null
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -0,0 +1,64 @@
1/*
2 * Definitions for Freescale Coldfire QSPI module
3 *
4 * Copyright 2010 Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19*/
20
21#ifndef mcfqspi_h
22#define mcfqspi_h
23
24#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
25#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
26#elif defined(CONFIG_M5249)
27#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
28#elif defined(CONFIG_M520x) || defined(CONFIG_M532x)
29#define MCFQSPI_IOBASE 0xFC058000
30#endif
31#define MCFQSPI_IOSIZE 0x40
32
33/**
34 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
35 * @setup: setup the control; allocate gpio's, etc. May be NULL.
36 * @teardown: finish with the control; free gpio's, etc. May be NULL.
37 * @select: output the signals to select the device. Can not be NULL.
38 * @deselect: output the signals to deselect the device. Can not be NULL.
39 *
40 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
41 * platforms are required to supply a mcfqspi_cs_control as a part of the
42 * platform data for each QSPI master controller. Only the select and
43 * deselect functions are required.
44*/
45struct mcfqspi_cs_control {
46 int (*setup)(struct mcfqspi_cs_control *);
47 void (*teardown)(struct mcfqspi_cs_control *);
48 void (*select)(struct mcfqspi_cs_control *, u8, bool);
49 void (*deselect)(struct mcfqspi_cs_control *, u8, bool);
50};
51
52/**
53 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
54 * @bus_num: board specific identifier for this qspi driver.
55 * @num_chipselects: number of chip selects supported by this qspi driver.
56 * @cs_control: platform dependent chip select control.
57*/
58struct mcfqspi_platform_data {
59 s16 bus_num;
60 u16 num_chipselect;
61 struct mcfqspi_cs_control *cs_control;
62};
63
64#endif /* mcfqspi_h */
diff --git a/arch/m68k/include/asm/mcfsmc.h b/arch/m68k/include/asm/mcfsmc.h
deleted file mode 100644
index 527bea5d6788..000000000000
--- a/arch/m68k/include/asm/mcfsmc.h
+++ /dev/null
@@ -1,187 +0,0 @@
1/****************************************************************************/
2
3/*
4 * mcfsmc.h -- SMC ethernet support for ColdFire environments.
5 *
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef mcfsmc_h
12#define mcfsmc_h
13/****************************************************************************/
14
15/*
16 * None of the current ColdFire targets that use the SMC91x111
17 * allow 8 bit accesses. So this code is 16bit access only.
18 */
19
20
21#undef outb
22#undef inb
23#undef outw
24#undef outwd
25#undef inw
26#undef outl
27#undef inl
28
29#undef outsb
30#undef outsw
31#undef outsl
32#undef insb
33#undef insw
34#undef insl
35
36/*
37 * Re-defines for ColdFire environment... The SMC part is
38 * mapped into memory space, so remap the PC-style in/out
39 * routines to handle that.
40 */
41#define outb smc_outb
42#define inb smc_inb
43#define outw smc_outw
44#define outwd smc_outwd
45#define inw smc_inw
46#define outl smc_outl
47#define inl smc_inl
48
49#define outsb smc_outsb
50#define outsw smc_outsw
51#define outsl smc_outsl
52#define insb smc_insb
53#define insw smc_insw
54#define insl smc_insl
55
56
57static inline int smc_inb(unsigned int addr)
58{
59 register unsigned short w;
60 w = *((volatile unsigned short *) (addr & ~0x1));
61 return(((addr & 0x1) ? w : (w >> 8)) & 0xff);
62}
63
64static inline void smc_outw(unsigned int val, unsigned int addr)
65{
66 *((volatile unsigned short *) addr) = (val << 8) | (val >> 8);
67}
68
69static inline int smc_inw(unsigned int addr)
70{
71 register unsigned short w;
72 w = *((volatile unsigned short *) addr);
73 return(((w << 8) | (w >> 8)) & 0xffff);
74}
75
76static inline void smc_outl(unsigned long val, unsigned int addr)
77{
78 *((volatile unsigned long *) addr) =
79 ((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) |
80 ((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff);
81}
82
83static inline void smc_outwd(unsigned int val, unsigned int addr)
84{
85 *((volatile unsigned short *) addr) = val;
86}
87
88
89/*
90 * The rep* functions are used to feed the data port with
91 * raw data. So we do not byte swap them when copying.
92 */
93
94static inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len)
95{
96 volatile unsigned short *rp;
97 unsigned short *buf, *ebuf;
98
99 buf = (unsigned short *) vbuf;
100 rp = (volatile unsigned short *) addr;
101
102 /* Copy as words for as long as possible */
103 for (ebuf = buf + (len >> 1); (buf < ebuf); )
104 *buf++ = *rp;
105
106 /* Lastly, handle left over byte */
107 if (len & 0x1)
108 *((unsigned char *) buf) = (*rp >> 8) & 0xff;
109}
110
111static inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len)
112{
113 volatile unsigned short *rp;
114 unsigned short *buf, *ebuf;
115
116 buf = (unsigned short *) vbuf;
117 rp = (volatile unsigned short *) addr;
118 for (ebuf = buf + len; (buf < ebuf); )
119 *buf++ = *rp;
120}
121
122static inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len)
123{
124 volatile unsigned long *rp;
125 unsigned long *buf, *ebuf;
126
127 buf = (unsigned long *) vbuf;
128 rp = (volatile unsigned long *) addr;
129 for (ebuf = buf + len; (buf < ebuf); )
130 *buf++ = *rp;
131}
132
133static inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len)
134{
135 volatile unsigned short *rp;
136 unsigned short *buf, *ebuf;
137
138 buf = (unsigned short *) vbuf;
139 rp = (volatile unsigned short *) addr;
140 for (ebuf = buf + len; (buf < ebuf); )
141 *rp = *buf++;
142}
143
144static inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len)
145{
146 volatile unsigned long *rp;
147 unsigned long *buf, *ebuf;
148
149 buf = (unsigned long *) vbuf;
150 rp = (volatile unsigned long *) addr;
151 for (ebuf = buf + len; (buf < ebuf); )
152 *rp = *buf++;
153}
154
155
156#ifdef CONFIG_NETtel
157/*
158 * Re-map the address space of at least one of the SMC ethernet
159 * parts. Both parts power up decoding the same address, so we
160 * need to move one of them first, before doing enything else.
161 *
162 * We also increase the number of wait states for this part by one.
163 */
164
165void smc_remap(unsigned int ioaddr)
166{
167 static int once = 0;
168 extern unsigned short ppdata;
169 if (once++ == 0) {
170 *((volatile unsigned short *)MCFSIM_PADDR) = 0x00ec;
171 ppdata |= 0x0080;
172 *((volatile unsigned short *)MCFSIM_PADAT) = ppdata;
173 outw(0x0001, ioaddr + BANK_SELECT);
174 outw(0x0001, ioaddr + BANK_SELECT);
175 outw(0x0067, ioaddr + BASE);
176
177 ppdata &= ~0x0080;
178 *((volatile unsigned short *)MCFSIM_PADAT) = ppdata;
179 }
180
181 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180;
182}
183
184#endif
185
186/****************************************************************************/
187#endif /* mcfsmc_h */
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
index cbd3d4751dd2..7a6a7590cc02 100644
--- a/arch/m68k/include/asm/processor.h
+++ b/arch/m68k/include/asm/processor.h
@@ -44,11 +44,15 @@ static inline void wrusp(unsigned long usp)
44 * User space process size: 3.75GB. This is hardcoded into a few places, 44 * User space process size: 3.75GB. This is hardcoded into a few places,
45 * so don't change it unless you know what you are doing. 45 * so don't change it unless you know what you are doing.
46 */ 46 */
47#ifdef CONFIG_MMU
47#ifndef CONFIG_SUN3 48#ifndef CONFIG_SUN3
48#define TASK_SIZE (0xF0000000UL) 49#define TASK_SIZE (0xF0000000UL)
49#else 50#else
50#define TASK_SIZE (0x0E000000UL) 51#define TASK_SIZE (0x0E000000UL)
51#endif 52#endif
53#else
54#define TASK_SIZE (0xFFFFFFFFUL)
55#endif
52 56
53#ifdef __KERNEL__ 57#ifdef __KERNEL__
54#define STACK_TOP TASK_SIZE 58#define STACK_TOP TASK_SIZE
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 064f5913db1a..efeb6033fc17 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -566,7 +566,7 @@ config RAMBASE
566 processor address space. 566 processor address space.
567 567
568config RAMSIZE 568config RAMSIZE
569 hex "Size of RAM (in bytes)" 569 hex "Size of RAM (in bytes), or 0 for automatic"
570 default "0x400000" 570 default "0x400000"
571 help 571 help
572 Define the size of the system RAM. If you select 0 then the 572 Define the size of the system RAM. If you select 0 then the
diff --git a/arch/m68knommu/mm/fault.c b/arch/m68knommu/mm/fault.c
index 6f6673cb5829..bc05cf74d9c0 100644
--- a/arch/m68knommu/mm/fault.c
+++ b/arch/m68knommu/mm/fault.c
@@ -2,7 +2,7 @@
2 * linux/arch/m68knommu/mm/fault.c 2 * linux/arch/m68knommu/mm/fault.c
3 * 3 *
4 * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, 4 * Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
5 * Copyright (C) 2000 Lineo, Inc. (www.lineo.com) 5 * Copyright (C) 2000 Lineo, Inc. (www.lineo.com)
6 * 6 *
7 * Based on: 7 * Based on:
8 * 8 *
@@ -36,7 +36,7 @@ asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
36 unsigned long error_code) 36 unsigned long error_code)
37{ 37{
38#ifdef DEBUG 38#ifdef DEBUG
39 printk (KERN_DEBUG "regs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld\n", 39 printk(KERN_DEBUG "regs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld\n",
40 regs->sr, regs->pc, address, error_code); 40 regs->sr, regs->pc, address, error_code);
41#endif 41#endif
42 42
@@ -44,11 +44,11 @@ asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
44 * Oops. The kernel tried to access some bad page. We'll have to 44 * Oops. The kernel tried to access some bad page. We'll have to
45 * terminate things with extreme prejudice. 45 * terminate things with extreme prejudice.
46 */ 46 */
47 if ((unsigned long) address < PAGE_SIZE) { 47 if ((unsigned long) address < PAGE_SIZE)
48 printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference"); 48 printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
49 } else 49 else
50 printk(KERN_ALERT "Unable to handle kernel access"); 50 printk(KERN_ALERT "Unable to handle kernel access");
51 printk(KERN_ALERT " at virtual address %08lx\n",address); 51 printk(KERN_ALERT " at virtual address %08lx\n", address);
52 die_if_kernel("Oops", regs, error_code); 52 die_if_kernel("Oops", regs, error_code);
53 do_exit(SIGKILL); 53 do_exit(SIGKILL);
54 54
diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c
index 92614de42cd3..71d2ba474c63 100644
--- a/arch/m68knommu/platform/520x/config.c
+++ b/arch/m68knommu/platform/520x/config.c
@@ -15,10 +15,13 @@
15#include <linux/param.h> 15#include <linux/param.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/spi/spi.h>
19#include <linux/gpio.h>
18#include <asm/machdep.h> 20#include <asm/machdep.h>
19#include <asm/coldfire.h> 21#include <asm/coldfire.h>
20#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
21#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
24#include <asm/mcfqspi.h>
22 25
23/***************************************************************************/ 26/***************************************************************************/
24 27
@@ -74,9 +77,152 @@ static struct platform_device m520x_fec = {
74 .resource = m520x_fec_resources, 77 .resource = m520x_fec_resources,
75}; 78};
76 79
80#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
81static struct resource m520x_qspi_resources[] = {
82 {
83 .start = MCFQSPI_IOBASE,
84 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 {
88 .start = MCFINT_VECBASE + MCFINT_QSPI,
89 .end = MCFINT_VECBASE + MCFINT_QSPI,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94#define MCFQSPI_CS0 62
95#define MCFQSPI_CS1 63
96#define MCFQSPI_CS2 44
97
98static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
99{
100 int status;
101
102 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
103 if (status) {
104 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
105 goto fail0;
106 }
107 status = gpio_direction_output(MCFQSPI_CS0, 1);
108 if (status) {
109 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
110 goto fail1;
111 }
112
113 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
114 if (status) {
115 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
116 goto fail1;
117 }
118 status = gpio_direction_output(MCFQSPI_CS1, 1);
119 if (status) {
120 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
121 goto fail2;
122 }
123
124 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
125 if (status) {
126 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
127 goto fail2;
128 }
129 status = gpio_direction_output(MCFQSPI_CS2, 1);
130 if (status) {
131 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
132 goto fail3;
133 }
134
135 return 0;
136
137fail3:
138 gpio_free(MCFQSPI_CS2);
139fail2:
140 gpio_free(MCFQSPI_CS1);
141fail1:
142 gpio_free(MCFQSPI_CS0);
143fail0:
144 return status;
145}
146
147static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control)
148{
149 gpio_free(MCFQSPI_CS2);
150 gpio_free(MCFQSPI_CS1);
151 gpio_free(MCFQSPI_CS0);
152}
153
154static void m520x_cs_select(struct mcfqspi_cs_control *cs_control,
155 u8 chip_select, bool cs_high)
156{
157 switch (chip_select) {
158 case 0:
159 gpio_set_value(MCFQSPI_CS0, cs_high);
160 break;
161 case 1:
162 gpio_set_value(MCFQSPI_CS1, cs_high);
163 break;
164 case 2:
165 gpio_set_value(MCFQSPI_CS2, cs_high);
166 break;
167 }
168}
169
170static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control,
171 u8 chip_select, bool cs_high)
172{
173 switch (chip_select) {
174 case 0:
175 gpio_set_value(MCFQSPI_CS0, !cs_high);
176 break;
177 case 1:
178 gpio_set_value(MCFQSPI_CS1, !cs_high);
179 break;
180 case 2:
181 gpio_set_value(MCFQSPI_CS2, !cs_high);
182 break;
183 }
184}
185
186static struct mcfqspi_cs_control m520x_cs_control = {
187 .setup = m520x_cs_setup,
188 .teardown = m520x_cs_teardown,
189 .select = m520x_cs_select,
190 .deselect = m520x_cs_deselect,
191};
192
193static struct mcfqspi_platform_data m520x_qspi_data = {
194 .bus_num = 0,
195 .num_chipselect = 3,
196 .cs_control = &m520x_cs_control,
197};
198
199static struct platform_device m520x_qspi = {
200 .name = "mcfqspi",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(m520x_qspi_resources),
203 .resource = m520x_qspi_resources,
204 .dev.platform_data = &m520x_qspi_data,
205};
206
207static void __init m520x_qspi_init(void)
208{
209 u16 par;
210 /* setup Port QS for QSPI with gpio CS control */
211 writeb(0x3f, MCF_IPSBAR + MCF_GPIO_PAR_QSPI);
212 /* make U1CTS and U2RTS gpio for cs_control */
213 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
214 par &= 0x00ff;
215 writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
216}
217#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
218
219
77static struct platform_device *m520x_devices[] __initdata = { 220static struct platform_device *m520x_devices[] __initdata = {
78 &m520x_uart, 221 &m520x_uart,
79 &m520x_fec, 222 &m520x_fec,
223#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
224 &m520x_qspi,
225#endif
80}; 226};
81 227
82/***************************************************************************/ 228/***************************************************************************/
@@ -147,6 +293,9 @@ void __init config_BSP(char *commandp, int size)
147 mach_reset = m520x_cpu_reset; 293 mach_reset = m520x_cpu_reset;
148 m520x_uarts_init(); 294 m520x_uarts_init();
149 m520x_fec_init(); 295 m520x_fec_init();
296#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
297 m520x_qspi_init();
298#endif
150} 299}
151 300
152/***************************************************************************/ 301/***************************************************************************/
diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68knommu/platform/523x/config.c
index 6ba84f2aa397..8980f6d7715a 100644
--- a/arch/m68knommu/platform/523x/config.c
+++ b/arch/m68knommu/platform/523x/config.c
@@ -16,10 +16,13 @@
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
19#include <asm/machdep.h> 21#include <asm/machdep.h>
20#include <asm/coldfire.h> 22#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 23#include <asm/mcfsim.h>
22#include <asm/mcfuart.h> 24#include <asm/mcfuart.h>
25#include <asm/mcfqspi.h>
23 26
24/***************************************************************************/ 27/***************************************************************************/
25 28
@@ -75,9 +78,173 @@ static struct platform_device m523x_fec = {
75 .resource = m523x_fec_resources, 78 .resource = m523x_fec_resources,
76}; 79};
77 80
81#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
82static struct resource m523x_qspi_resources[] = {
83 {
84 .start = MCFQSPI_IOBASE,
85 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
86 .flags = IORESOURCE_MEM,
87 },
88 {
89 .start = MCFINT_VECBASE + MCFINT_QSPI,
90 .end = MCFINT_VECBASE + MCFINT_QSPI,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95#define MCFQSPI_CS0 91
96#define MCFQSPI_CS1 92
97#define MCFQSPI_CS2 103
98#define MCFQSPI_CS3 99
99
100static int m523x_cs_setup(struct mcfqspi_cs_control *cs_control)
101{
102 int status;
103
104 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
105 if (status) {
106 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
107 goto fail0;
108 }
109 status = gpio_direction_output(MCFQSPI_CS0, 1);
110 if (status) {
111 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
112 goto fail1;
113 }
114
115 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
116 if (status) {
117 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
118 goto fail1;
119 }
120 status = gpio_direction_output(MCFQSPI_CS1, 1);
121 if (status) {
122 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
123 goto fail2;
124 }
125
126 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
127 if (status) {
128 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
129 goto fail2;
130 }
131 status = gpio_direction_output(MCFQSPI_CS2, 1);
132 if (status) {
133 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
134 goto fail3;
135 }
136
137 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
138 if (status) {
139 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
140 goto fail3;
141 }
142 status = gpio_direction_output(MCFQSPI_CS3, 1);
143 if (status) {
144 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
145 goto fail4;
146 }
147
148 return 0;
149
150fail4:
151 gpio_free(MCFQSPI_CS3);
152fail3:
153 gpio_free(MCFQSPI_CS2);
154fail2:
155 gpio_free(MCFQSPI_CS1);
156fail1:
157 gpio_free(MCFQSPI_CS0);
158fail0:
159 return status;
160}
161
162static void m523x_cs_teardown(struct mcfqspi_cs_control *cs_control)
163{
164 gpio_free(MCFQSPI_CS3);
165 gpio_free(MCFQSPI_CS2);
166 gpio_free(MCFQSPI_CS1);
167 gpio_free(MCFQSPI_CS0);
168}
169
170static void m523x_cs_select(struct mcfqspi_cs_control *cs_control,
171 u8 chip_select, bool cs_high)
172{
173 switch (chip_select) {
174 case 0:
175 gpio_set_value(MCFQSPI_CS0, cs_high);
176 break;
177 case 1:
178 gpio_set_value(MCFQSPI_CS1, cs_high);
179 break;
180 case 2:
181 gpio_set_value(MCFQSPI_CS2, cs_high);
182 break;
183 case 3:
184 gpio_set_value(MCFQSPI_CS3, cs_high);
185 break;
186 }
187}
188
189static void m523x_cs_deselect(struct mcfqspi_cs_control *cs_control,
190 u8 chip_select, bool cs_high)
191{
192 switch (chip_select) {
193 case 0:
194 gpio_set_value(MCFQSPI_CS0, !cs_high);
195 break;
196 case 1:
197 gpio_set_value(MCFQSPI_CS1, !cs_high);
198 break;
199 case 2:
200 gpio_set_value(MCFQSPI_CS2, !cs_high);
201 break;
202 case 3:
203 gpio_set_value(MCFQSPI_CS3, !cs_high);
204 break;
205 }
206}
207
208static struct mcfqspi_cs_control m523x_cs_control = {
209 .setup = m523x_cs_setup,
210 .teardown = m523x_cs_teardown,
211 .select = m523x_cs_select,
212 .deselect = m523x_cs_deselect,
213};
214
215static struct mcfqspi_platform_data m523x_qspi_data = {
216 .bus_num = 0,
217 .num_chipselect = 4,
218 .cs_control = &m523x_cs_control,
219};
220
221static struct platform_device m523x_qspi = {
222 .name = "mcfqspi",
223 .id = 0,
224 .num_resources = ARRAY_SIZE(m523x_qspi_resources),
225 .resource = m523x_qspi_resources,
226 .dev.platform_data = &m523x_qspi_data,
227};
228
229static void __init m523x_qspi_init(void)
230{
231 u16 par;
232
233 /* setup QSPS pins for QSPI with gpio CS control */
234 writeb(0x1f, MCFGPIO_PAR_QSPI);
235 /* and CS2 & CS3 as gpio */
236 par = readw(MCFGPIO_PAR_TIMER);
237 par &= 0x3f3f;
238 writew(par, MCFGPIO_PAR_TIMER);
239}
240#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
241
78static struct platform_device *m523x_devices[] __initdata = { 242static struct platform_device *m523x_devices[] __initdata = {
79 &m523x_uart, 243 &m523x_uart,
80 &m523x_fec, 244 &m523x_fec,
245#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
246 &m523x_qspi,
247#endif
81}; 248};
82 249
83/***************************************************************************/ 250/***************************************************************************/
@@ -114,6 +281,9 @@ void __init config_BSP(char *commandp, int size)
114static int __init init_BSP(void) 281static int __init init_BSP(void)
115{ 282{
116 m523x_fec_init(); 283 m523x_fec_init();
284#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
285 m523x_qspi_init();
286#endif
117 platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices)); 287 platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices));
118 return 0; 288 return 0;
119} 289}
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 646f5ba462fc..ceb31e5744a6 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -12,10 +12,13 @@
12#include <linux/param.h> 12#include <linux/param.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/spi/spi.h>
16#include <linux/gpio.h>
15#include <asm/machdep.h> 17#include <asm/machdep.h>
16#include <asm/coldfire.h> 18#include <asm/coldfire.h>
17#include <asm/mcfsim.h> 19#include <asm/mcfsim.h>
18#include <asm/mcfuart.h> 20#include <asm/mcfuart.h>
21#include <asm/mcfqspi.h>
19 22
20/***************************************************************************/ 23/***************************************************************************/
21 24
@@ -37,8 +40,196 @@ static struct platform_device m5249_uart = {
37 .dev.platform_data = m5249_uart_platform, 40 .dev.platform_data = m5249_uart_platform,
38}; 41};
39 42
43#ifdef CONFIG_M5249C3
44
45static struct resource m5249_smc91x_resources[] = {
46 {
47 .start = 0xe0000300,
48 .end = 0xe0000300 + 0x100,
49 .flags = IORESOURCE_MEM,
50 },
51 {
52 .start = MCFINTC2_GPIOIRQ6,
53 .end = MCFINTC2_GPIOIRQ6,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58static struct platform_device m5249_smc91x = {
59 .name = "smc91x",
60 .id = 0,
61 .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
62 .resource = m5249_smc91x_resources,
63};
64
65#endif /* CONFIG_M5249C3 */
66
67#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
68static struct resource m5249_qspi_resources[] = {
69 {
70 .start = MCFQSPI_IOBASE,
71 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .start = MCF_IRQ_QSPI,
76 .end = MCF_IRQ_QSPI,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81#define MCFQSPI_CS0 29
82#define MCFQSPI_CS1 24
83#define MCFQSPI_CS2 21
84#define MCFQSPI_CS3 22
85
86static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control)
87{
88 int status;
89
90 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
91 if (status) {
92 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
93 goto fail0;
94 }
95 status = gpio_direction_output(MCFQSPI_CS0, 1);
96 if (status) {
97 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
98 goto fail1;
99 }
100
101 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
102 if (status) {
103 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
104 goto fail1;
105 }
106 status = gpio_direction_output(MCFQSPI_CS1, 1);
107 if (status) {
108 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
109 goto fail2;
110 }
111
112 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
113 if (status) {
114 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
115 goto fail2;
116 }
117 status = gpio_direction_output(MCFQSPI_CS2, 1);
118 if (status) {
119 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
120 goto fail3;
121 }
122
123 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
124 if (status) {
125 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
126 goto fail3;
127 }
128 status = gpio_direction_output(MCFQSPI_CS3, 1);
129 if (status) {
130 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
131 goto fail4;
132 }
133
134 return 0;
135
136fail4:
137 gpio_free(MCFQSPI_CS3);
138fail3:
139 gpio_free(MCFQSPI_CS2);
140fail2:
141 gpio_free(MCFQSPI_CS1);
142fail1:
143 gpio_free(MCFQSPI_CS0);
144fail0:
145 return status;
146}
147
148static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control)
149{
150 gpio_free(MCFQSPI_CS3);
151 gpio_free(MCFQSPI_CS2);
152 gpio_free(MCFQSPI_CS1);
153 gpio_free(MCFQSPI_CS0);
154}
155
156static void m5249_cs_select(struct mcfqspi_cs_control *cs_control,
157 u8 chip_select, bool cs_high)
158{
159 switch (chip_select) {
160 case 0:
161 gpio_set_value(MCFQSPI_CS0, cs_high);
162 break;
163 case 1:
164 gpio_set_value(MCFQSPI_CS1, cs_high);
165 break;
166 case 2:
167 gpio_set_value(MCFQSPI_CS2, cs_high);
168 break;
169 case 3:
170 gpio_set_value(MCFQSPI_CS3, cs_high);
171 break;
172 }
173}
174
175static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control,
176 u8 chip_select, bool cs_high)
177{
178 switch (chip_select) {
179 case 0:
180 gpio_set_value(MCFQSPI_CS0, !cs_high);
181 break;
182 case 1:
183 gpio_set_value(MCFQSPI_CS1, !cs_high);
184 break;
185 case 2:
186 gpio_set_value(MCFQSPI_CS2, !cs_high);
187 break;
188 case 3:
189 gpio_set_value(MCFQSPI_CS3, !cs_high);
190 break;
191 }
192}
193
194static struct mcfqspi_cs_control m5249_cs_control = {
195 .setup = m5249_cs_setup,
196 .teardown = m5249_cs_teardown,
197 .select = m5249_cs_select,
198 .deselect = m5249_cs_deselect,
199};
200
201static struct mcfqspi_platform_data m5249_qspi_data = {
202 .bus_num = 0,
203 .num_chipselect = 4,
204 .cs_control = &m5249_cs_control,
205};
206
207static struct platform_device m5249_qspi = {
208 .name = "mcfqspi",
209 .id = 0,
210 .num_resources = ARRAY_SIZE(m5249_qspi_resources),
211 .resource = m5249_qspi_resources,
212 .dev.platform_data = &m5249_qspi_data,
213};
214
215static void __init m5249_qspi_init(void)
216{
217 /* QSPI irq setup */
218 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
219 MCF_MBAR + MCFSIM_QSPIICR);
220 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
221}
222#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
223
224
40static struct platform_device *m5249_devices[] __initdata = { 225static struct platform_device *m5249_devices[] __initdata = {
41 &m5249_uart, 226 &m5249_uart,
227#ifdef CONFIG_M5249C3
228 &m5249_smc91x,
229#endif
230#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
231 &m5249_qspi,
232#endif
42}; 233};
43 234
44/***************************************************************************/ 235/***************************************************************************/
@@ -67,6 +258,24 @@ static void __init m5249_uarts_init(void)
67 258
68/***************************************************************************/ 259/***************************************************************************/
69 260
261#ifdef CONFIG_M5249C3
262
263static void __init m5249_smc91x_init(void)
264{
265 u32 gpio;
266
267 /* Set the GPIO line as interrupt source for smc91x device */
268 gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
269 writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
270
271 gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
272 writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
273}
274
275#endif /* CONFIG_M5249C3 */
276
277/***************************************************************************/
278
70static void __init m5249_timers_init(void) 279static void __init m5249_timers_init(void)
71{ 280{
72 /* Timer1 is always used as system timer */ 281 /* Timer1 is always used as system timer */
@@ -100,6 +309,12 @@ void __init config_BSP(char *commandp, int size)
100 mach_reset = m5249_cpu_reset; 309 mach_reset = m5249_cpu_reset;
101 m5249_timers_init(); 310 m5249_timers_init();
102 m5249_uarts_init(); 311 m5249_uarts_init();
312#ifdef CONFIG_M5249C3
313 m5249_smc91x_init();
314#endif
315#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
316 m5249_qspi_init();
317#endif
103} 318}
104 319
105/***************************************************************************/ 320/***************************************************************************/
diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c
index fa51be172830..3d9c35c98b98 100644
--- a/arch/m68knommu/platform/527x/config.c
+++ b/arch/m68knommu/platform/527x/config.c
@@ -16,10 +16,13 @@
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/spi/spi.h>
20#include <linux/gpio.h>
19#include <asm/machdep.h> 21#include <asm/machdep.h>
20#include <asm/coldfire.h> 22#include <asm/coldfire.h>
21#include <asm/mcfsim.h> 23#include <asm/mcfsim.h>
22#include <asm/mcfuart.h> 24#include <asm/mcfuart.h>
25#include <asm/mcfqspi.h>
23 26
24/***************************************************************************/ 27/***************************************************************************/
25 28
@@ -106,12 +109,188 @@ static struct platform_device m527x_fec[] = {
106 }, 109 },
107}; 110};
108 111
112#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
113static struct resource m527x_qspi_resources[] = {
114 {
115 .start = MCFQSPI_IOBASE,
116 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
117 .flags = IORESOURCE_MEM,
118 },
119 {
120 .start = MCFINT_VECBASE + MCFINT_QSPI,
121 .end = MCFINT_VECBASE + MCFINT_QSPI,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126#if defined(CONFIG_M5271)
127#define MCFQSPI_CS0 91
128#define MCFQSPI_CS1 92
129#define MCFQSPI_CS2 99
130#define MCFQSPI_CS3 103
131#elif defined(CONFIG_M5275)
132#define MCFQSPI_CS0 59
133#define MCFQSPI_CS1 60
134#define MCFQSPI_CS2 61
135#define MCFQSPI_CS3 62
136#endif
137
138static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control)
139{
140 int status;
141
142 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
143 if (status) {
144 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
145 goto fail0;
146 }
147 status = gpio_direction_output(MCFQSPI_CS0, 1);
148 if (status) {
149 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
150 goto fail1;
151 }
152
153 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
154 if (status) {
155 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
156 goto fail1;
157 }
158 status = gpio_direction_output(MCFQSPI_CS1, 1);
159 if (status) {
160 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
161 goto fail2;
162 }
163
164 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
165 if (status) {
166 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
167 goto fail2;
168 }
169 status = gpio_direction_output(MCFQSPI_CS2, 1);
170 if (status) {
171 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
172 goto fail3;
173 }
174
175 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
176 if (status) {
177 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
178 goto fail3;
179 }
180 status = gpio_direction_output(MCFQSPI_CS3, 1);
181 if (status) {
182 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
183 goto fail4;
184 }
185
186 return 0;
187
188fail4:
189 gpio_free(MCFQSPI_CS3);
190fail3:
191 gpio_free(MCFQSPI_CS2);
192fail2:
193 gpio_free(MCFQSPI_CS1);
194fail1:
195 gpio_free(MCFQSPI_CS0);
196fail0:
197 return status;
198}
199
200static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control)
201{
202 gpio_free(MCFQSPI_CS3);
203 gpio_free(MCFQSPI_CS2);
204 gpio_free(MCFQSPI_CS1);
205 gpio_free(MCFQSPI_CS0);
206}
207
208static void m527x_cs_select(struct mcfqspi_cs_control *cs_control,
209 u8 chip_select, bool cs_high)
210{
211 switch (chip_select) {
212 case 0:
213 gpio_set_value(MCFQSPI_CS0, cs_high);
214 break;
215 case 1:
216 gpio_set_value(MCFQSPI_CS1, cs_high);
217 break;
218 case 2:
219 gpio_set_value(MCFQSPI_CS2, cs_high);
220 break;
221 case 3:
222 gpio_set_value(MCFQSPI_CS3, cs_high);
223 break;
224 }
225}
226
227static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control,
228 u8 chip_select, bool cs_high)
229{
230 switch (chip_select) {
231 case 0:
232 gpio_set_value(MCFQSPI_CS0, !cs_high);
233 break;
234 case 1:
235 gpio_set_value(MCFQSPI_CS1, !cs_high);
236 break;
237 case 2:
238 gpio_set_value(MCFQSPI_CS2, !cs_high);
239 break;
240 case 3:
241 gpio_set_value(MCFQSPI_CS3, !cs_high);
242 break;
243 }
244}
245
246static struct mcfqspi_cs_control m527x_cs_control = {
247 .setup = m527x_cs_setup,
248 .teardown = m527x_cs_teardown,
249 .select = m527x_cs_select,
250 .deselect = m527x_cs_deselect,
251};
252
253static struct mcfqspi_platform_data m527x_qspi_data = {
254 .bus_num = 0,
255 .num_chipselect = 4,
256 .cs_control = &m527x_cs_control,
257};
258
259static struct platform_device m527x_qspi = {
260 .name = "mcfqspi",
261 .id = 0,
262 .num_resources = ARRAY_SIZE(m527x_qspi_resources),
263 .resource = m527x_qspi_resources,
264 .dev.platform_data = &m527x_qspi_data,
265};
266
267static void __init m527x_qspi_init(void)
268{
269#if defined(CONFIG_M5271)
270 u16 par;
271
272 /* setup QSPS pins for QSPI with gpio CS control */
273 writeb(0x1f, MCFGPIO_PAR_QSPI);
274 /* and CS2 & CS3 as gpio */
275 par = readw(MCFGPIO_PAR_TIMER);
276 par &= 0x3f3f;
277 writew(par, MCFGPIO_PAR_TIMER);
278#elif defined(CONFIG_M5275)
279 /* setup QSPS pins for QSPI with gpio CS control */
280 writew(0x003e, MCFGPIO_PAR_QSPI);
281#endif
282}
283#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
284
109static struct platform_device *m527x_devices[] __initdata = { 285static struct platform_device *m527x_devices[] __initdata = {
110 &m527x_uart, 286 &m527x_uart,
111 &m527x_fec[0], 287 &m527x_fec[0],
112#ifdef CONFIG_FEC2 288#ifdef CONFIG_FEC2
113 &m527x_fec[1], 289 &m527x_fec[1],
114#endif 290#endif
291#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
292 &m527x_qspi,
293#endif
115}; 294};
116 295
117/***************************************************************************/ 296/***************************************************************************/
@@ -187,6 +366,9 @@ void __init config_BSP(char *commandp, int size)
187 mach_reset = m527x_cpu_reset; 366 mach_reset = m527x_cpu_reset;
188 m527x_uarts_init(); 367 m527x_uarts_init();
189 m527x_fec_init(); 368 m527x_fec_init();
369#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
370 m527x_qspi_init();
371#endif
190} 372}
191 373
192/***************************************************************************/ 374/***************************************************************************/
diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c
index 6e608d1836f1..76b743343bfa 100644
--- a/arch/m68knommu/platform/528x/config.c
+++ b/arch/m68knommu/platform/528x/config.c
@@ -17,10 +17,13 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/spi/spi.h>
21#include <linux/gpio.h>
20#include <asm/machdep.h> 22#include <asm/machdep.h>
21#include <asm/coldfire.h> 23#include <asm/coldfire.h>
22#include <asm/mcfsim.h> 24#include <asm/mcfsim.h>
23#include <asm/mcfuart.h> 25#include <asm/mcfuart.h>
26#include <asm/mcfqspi.h>
24 27
25/***************************************************************************/ 28/***************************************************************************/
26 29
@@ -76,10 +79,141 @@ static struct platform_device m528x_fec = {
76 .resource = m528x_fec_resources, 79 .resource = m528x_fec_resources,
77}; 80};
78 81
82#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
83static struct resource m528x_qspi_resources[] = {
84 {
85 .start = MCFQSPI_IOBASE,
86 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .start = MCFINT_VECBASE + MCFINT_QSPI,
91 .end = MCFINT_VECBASE + MCFINT_QSPI,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96#define MCFQSPI_CS0 147
97#define MCFQSPI_CS1 148
98#define MCFQSPI_CS2 149
99#define MCFQSPI_CS3 150
100
101static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
102{
103 int status;
104
105 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
106 if (status) {
107 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
108 goto fail0;
109 }
110 status = gpio_direction_output(MCFQSPI_CS0, 1);
111 if (status) {
112 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
113 goto fail1;
114 }
115
116 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
117 if (status) {
118 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
119 goto fail1;
120 }
121 status = gpio_direction_output(MCFQSPI_CS1, 1);
122 if (status) {
123 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
124 goto fail2;
125 }
126
127 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
128 if (status) {
129 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
130 goto fail2;
131 }
132 status = gpio_direction_output(MCFQSPI_CS2, 1);
133 if (status) {
134 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
135 goto fail3;
136 }
137
138 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
139 if (status) {
140 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
141 goto fail3;
142 }
143 status = gpio_direction_output(MCFQSPI_CS3, 1);
144 if (status) {
145 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
146 goto fail4;
147 }
148
149 return 0;
150
151fail4:
152 gpio_free(MCFQSPI_CS3);
153fail3:
154 gpio_free(MCFQSPI_CS2);
155fail2:
156 gpio_free(MCFQSPI_CS1);
157fail1:
158 gpio_free(MCFQSPI_CS0);
159fail0:
160 return status;
161}
162
163static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
164{
165 gpio_free(MCFQSPI_CS3);
166 gpio_free(MCFQSPI_CS2);
167 gpio_free(MCFQSPI_CS1);
168 gpio_free(MCFQSPI_CS0);
169}
170
171static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
172 u8 chip_select, bool cs_high)
173{
174 gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
175}
176
177static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
178 u8 chip_select, bool cs_high)
179{
180 gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
181}
182
183static struct mcfqspi_cs_control m528x_cs_control = {
184 .setup = m528x_cs_setup,
185 .teardown = m528x_cs_teardown,
186 .select = m528x_cs_select,
187 .deselect = m528x_cs_deselect,
188};
189
190static struct mcfqspi_platform_data m528x_qspi_data = {
191 .bus_num = 0,
192 .num_chipselect = 4,
193 .cs_control = &m528x_cs_control,
194};
195
196static struct platform_device m528x_qspi = {
197 .name = "mcfqspi",
198 .id = 0,
199 .num_resources = ARRAY_SIZE(m528x_qspi_resources),
200 .resource = m528x_qspi_resources,
201 .dev.platform_data = &m528x_qspi_data,
202};
203
204static void __init m528x_qspi_init(void)
205{
206 /* setup Port QS for QSPI with gpio CS control */
207 __raw_writeb(0x07, MCFGPIO_PQSPAR);
208}
209#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
79 210
80static struct platform_device *m528x_devices[] __initdata = { 211static struct platform_device *m528x_devices[] __initdata = {
81 &m528x_uart, 212 &m528x_uart,
82 &m528x_fec, 213 &m528x_fec,
214#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
215 &m528x_qspi,
216#endif
83}; 217};
84 218
85/***************************************************************************/ 219/***************************************************************************/
@@ -174,6 +308,9 @@ static int __init init_BSP(void)
174 mach_reset = m528x_cpu_reset; 308 mach_reset = m528x_cpu_reset;
175 m528x_uarts_init(); 309 m528x_uarts_init();
176 m528x_fec_init(); 310 m528x_fec_init();
311#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
312 m528x_qspi_init();
313#endif
177 platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices)); 314 platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
178 return 0; 315 return 0;
179} 316}
diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68knommu/platform/5307/Makefile
index 667db6598451..6de526976828 100644
--- a/arch/m68knommu/platform/5307/Makefile
+++ b/arch/m68knommu/platform/5307/Makefile
@@ -14,5 +14,7 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y += config.o gpio.o 17obj-y += config.o gpio.o
18obj-$(CONFIG_NETtel) += nettel.o
19obj-$(CONFIG_CLEOPATRA) += nettel.o
18 20
diff --git a/arch/m68knommu/platform/5307/nettel.c b/arch/m68knommu/platform/5307/nettel.c
new file mode 100644
index 000000000000..e925ea4602f8
--- /dev/null
+++ b/arch/m68knommu/platform/5307/nettel.c
@@ -0,0 +1,153 @@
1/***************************************************************************/
2
3/*
4 * nettel.c -- startup code support for the NETtel boards
5 *
6 * Copyright (C) 2009, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/coldfire.h>
17#include <asm/mcfsim.h>
18#include <asm/nettel.h>
19
20/***************************************************************************/
21
22/*
23 * Define the IO and interrupt resources of the 2 SMC9196 interfaces.
24 */
25#define NETTEL_SMC0_ADDR 0x30600300
26#define NETTEL_SMC0_IRQ 29
27
28#define NETTEL_SMC1_ADDR 0x30600000
29#define NETTEL_SMC1_IRQ 27
30
31/*
32 * We need some access into the SMC9196 registers. Define those registers
33 * we will need here (including the smc91x.h doesn't seem to give us these
34 * in a simple form).
35 */
36#define SMC91xx_BANKSELECT 14
37#define SMC91xx_BASEADDR 2
38#define SMC91xx_BASEMAC 4
39
40/***************************************************************************/
41
42static struct resource nettel_smc91x_0_resources[] = {
43 {
44 .start = NETTEL_SMC0_ADDR,
45 .end = NETTEL_SMC0_ADDR + 0x20,
46 .flags = IORESOURCE_MEM,
47 },
48 {
49 .start = NETTEL_SMC0_IRQ,
50 .end = NETTEL_SMC0_IRQ,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct resource nettel_smc91x_1_resources[] = {
56 {
57 .start = NETTEL_SMC1_ADDR,
58 .end = NETTEL_SMC1_ADDR + 0x20,
59 .flags = IORESOURCE_MEM,
60 },
61 {
62 .start = NETTEL_SMC1_IRQ,
63 .end = NETTEL_SMC1_IRQ,
64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68static struct platform_device nettel_smc91x[] = {
69 {
70 .name = "smc91x",
71 .id = 0,
72 .num_resources = ARRAY_SIZE(nettel_smc91x_0_resources),
73 .resource = nettel_smc91x_0_resources,
74 },
75 {
76 .name = "smc91x",
77 .id = 1,
78 .num_resources = ARRAY_SIZE(nettel_smc91x_1_resources),
79 .resource = nettel_smc91x_1_resources,
80 },
81};
82
83static struct platform_device *nettel_devices[] __initdata = {
84 &nettel_smc91x[0],
85 &nettel_smc91x[1],
86};
87
88/***************************************************************************/
89
90static u8 nettel_macdefault[] __initdata = {
91 0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01,
92};
93
94/*
95 * Set flash contained MAC address into SMC9196 core. Make sure the flash
96 * MAC address is sane, and not an empty flash. If no good use the Moreton
97 * Bay default MAC address instead.
98 */
99
100static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr)
101{
102 u16 *macp;
103
104 macp = (u16 *) flashaddr;
105 if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff))
106 macp = (u16 *) &nettel_macdefault[0];
107
108 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
109 writew(macp[0], ioaddr + SMC91xx_BASEMAC);
110 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
111 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
112}
113
114/***************************************************************************/
115
116/*
117 * Re-map the address space of at least one of the SMC ethernet
118 * parts. Both parts power up decoding the same address, so we
119 * need to move one of them first, before doing anything else.
120 */
121
122static void __init nettel_smc91x_init(void)
123{
124 writew(0x00ec, MCF_MBAR + MCFSIM_PADDR);
125 mcf_setppdata(0, 0x0080);
126 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
127 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
128 mcf_setppdata(0x0080, 0);
129
130 /* Set correct chip select timing for SMC9196 accesses */
131 writew(0x1180, MCF_MBAR + MCFSIM_CSCR3);
132
133 /* Set the SMC interrupts to be auto-vectored */
134 mcf_autovector(NETTEL_SMC0_IRQ);
135 mcf_autovector(NETTEL_SMC1_IRQ);
136
137 /* Set MAC addresses from flash for both interfaces */
138 nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000);
139 nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006);
140}
141
142/***************************************************************************/
143
144static int __init init_nettel(void)
145{
146 nettel_smc91x_init();
147 platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices));
148 return 0;
149}
150
151arch_initcall(init_nettel);
152
153/***************************************************************************/
diff --git a/arch/m68knommu/platform/532x/config.c b/arch/m68knommu/platform/532x/config.c
index d632948e64e5..ca51323f957b 100644
--- a/arch/m68knommu/platform/532x/config.c
+++ b/arch/m68knommu/platform/532x/config.c
@@ -21,12 +21,15 @@
21#include <linux/param.h> 21#include <linux/param.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/spi/spi.h>
25#include <linux/gpio.h>
24#include <asm/machdep.h> 26#include <asm/machdep.h>
25#include <asm/coldfire.h> 27#include <asm/coldfire.h>
26#include <asm/mcfsim.h> 28#include <asm/mcfsim.h>
27#include <asm/mcfuart.h> 29#include <asm/mcfuart.h>
28#include <asm/mcfdma.h> 30#include <asm/mcfdma.h>
29#include <asm/mcfwdebug.h> 31#include <asm/mcfwdebug.h>
32#include <asm/mcfqspi.h>
30 33
31/***************************************************************************/ 34/***************************************************************************/
32 35
@@ -82,9 +85,127 @@ static struct platform_device m532x_fec = {
82 .resource = m532x_fec_resources, 85 .resource = m532x_fec_resources,
83}; 86};
84 87
88#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
89static struct resource m532x_qspi_resources[] = {
90 {
91 .start = MCFQSPI_IOBASE,
92 .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .start = MCFINT_VECBASE + MCFINT_QSPI,
97 .end = MCFINT_VECBASE + MCFINT_QSPI,
98 .flags = IORESOURCE_IRQ,
99 },
100};
101
102#define MCFQSPI_CS0 84
103#define MCFQSPI_CS1 85
104#define MCFQSPI_CS2 86
105
106static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control)
107{
108 int status;
109
110 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
111 if (status) {
112 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
113 goto fail0;
114 }
115 status = gpio_direction_output(MCFQSPI_CS0, 1);
116 if (status) {
117 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
118 goto fail1;
119 }
120
121 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
122 if (status) {
123 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
124 goto fail1;
125 }
126 status = gpio_direction_output(MCFQSPI_CS1, 1);
127 if (status) {
128 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
129 goto fail2;
130 }
131
132 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
133 if (status) {
134 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
135 goto fail2;
136 }
137 status = gpio_direction_output(MCFQSPI_CS2, 1);
138 if (status) {
139 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
140 goto fail3;
141 }
142
143 return 0;
144
145fail3:
146 gpio_free(MCFQSPI_CS2);
147fail2:
148 gpio_free(MCFQSPI_CS1);
149fail1:
150 gpio_free(MCFQSPI_CS0);
151fail0:
152 return status;
153}
154
155static void m532x_cs_teardown(struct mcfqspi_cs_control *cs_control)
156{
157 gpio_free(MCFQSPI_CS2);
158 gpio_free(MCFQSPI_CS1);
159 gpio_free(MCFQSPI_CS0);
160}
161
162static void m532x_cs_select(struct mcfqspi_cs_control *cs_control,
163 u8 chip_select, bool cs_high)
164{
165 gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
166}
167
168static void m532x_cs_deselect(struct mcfqspi_cs_control *cs_control,
169 u8 chip_select, bool cs_high)
170{
171 gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
172}
173
174static struct mcfqspi_cs_control m532x_cs_control = {
175 .setup = m532x_cs_setup,
176 .teardown = m532x_cs_teardown,
177 .select = m532x_cs_select,
178 .deselect = m532x_cs_deselect,
179};
180
181static struct mcfqspi_platform_data m532x_qspi_data = {
182 .bus_num = 0,
183 .num_chipselect = 3,
184 .cs_control = &m532x_cs_control,
185};
186
187static struct platform_device m532x_qspi = {
188 .name = "mcfqspi",
189 .id = 0,
190 .num_resources = ARRAY_SIZE(m532x_qspi_resources),
191 .resource = m532x_qspi_resources,
192 .dev.platform_data = &m532x_qspi_data,
193};
194
195static void __init m532x_qspi_init(void)
196{
197 /* setup QSPS pins for QSPI with gpio CS control */
198 writew(0x01f0, MCF_GPIO_PAR_QSPI);
199}
200#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
201
202
85static struct platform_device *m532x_devices[] __initdata = { 203static struct platform_device *m532x_devices[] __initdata = {
86 &m532x_uart, 204 &m532x_uart,
87 &m532x_fec, 205 &m532x_fec,
206#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
207 &m532x_qspi,
208#endif
88}; 209};
89 210
90/***************************************************************************/ 211/***************************************************************************/
@@ -158,6 +279,9 @@ static int __init init_BSP(void)
158{ 279{
159 m532x_uarts_init(); 280 m532x_uarts_init();
160 m532x_fec_init(); 281 m532x_fec_init();
282#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
283 m532x_qspi_init();
284#endif
161 platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices)); 285 platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices));
162 return 0; 286 return 0;
163} 287}
diff --git a/arch/m68knommu/platform/68360/commproc.c b/arch/m68knommu/platform/68360/commproc.c
index 6acb8d294cb6..f27e688c404e 100644
--- a/arch/m68knommu/platform/68360/commproc.c
+++ b/arch/m68knommu/platform/68360/commproc.c
@@ -110,7 +110,7 @@ void m360_cpm_reset()
110 /* pte = find_pte(&init_mm, host_page_addr); */ 110 /* pte = find_pte(&init_mm, host_page_addr); */
111 /* pte_val(*pte) |= _PAGE_NO_CACHE; */ 111 /* pte_val(*pte) |= _PAGE_NO_CACHE; */
112 /* flush_tlb_page(current->mm->mmap, host_buffer); */ 112 /* flush_tlb_page(current->mm->mmap, host_buffer); */
113 113
114 /* Tell everyone where the comm processor resides. 114 /* Tell everyone where the comm processor resides.
115 */ 115 */
116/* cpmp = (cpm360_t *)commproc; */ 116/* cpmp = (cpm360_t *)commproc; */
@@ -191,7 +191,7 @@ cpm_interrupt(int irq, void * dev, struct pt_regs * regs)
191 */ 191 */
192 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr |= (1 << vec); 192 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr |= (1 << vec);
193#endif 193#endif
194 194
195} 195}
196 196
197/* The CPM can generate the error interrupt when there is a race condition 197/* The CPM can generate the error interrupt when there is a race condition
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 13:16:30 -0500