sh: Fix up the SH-3 build for recent TLB changes.

While the MMUCR.URB and ITLB/UTLB differentiation works fine for all SH-4
and later TLBs, these features are absent on SH-3. This splits out
local_flush_tlb_all() in to SH-4 and PTEAEX copies while restoring the
old SH-3 one, subsequently fixing up the build.

This will probably want some further reordering and tidying in the
future, but that's out of scope at present.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

4 files changed, 75 insertions, 28 deletions

diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
index bdd0982b56ee..b71db6af8060 100644
--- a/arch/sh/mm/tlb-pteaex.c
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -77,3 +77,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
         back_to_cached();
 }
+
+void local_flush_tlb_all(void)
+{
+        unsigned long flags, status;
+        int i;
+
+        /*
+         * Flush all the TLB.
+         */
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        status = __raw_readl(MMUCR);
+        status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
+
+        if (status == 0)
+                status = MMUCR_URB_NENTRIES;
+
+        for (i = 0; i < status; i++)
+                __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
+
+        for (i = 0; i < 4; i++)
+                __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
+
+        back_to_cached();
+        ctrl_barrier();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index 4f5f7cbdd508..7a940dbfc2e9 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -77,3 +77,22 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         for (i = 0; i < ways; i++)
                 __raw_writel(data, addr + (i << 8));
 }
+
+void local_flush_tlb_all(void)
+{
+        unsigned long flags, status;
+
+        /*
+         * Flush all the TLB.
+         *
+         * Write to the MMU control register's bit:
+         *      TF-bit for SH-3, TI-bit for SH-4.
+         *      It's same position, bit #2.
+         */
+        local_irq_save(flags);
+        status = __raw_readl(MMUCR);
+        status |= 0x04;
+        __raw_writel(status, MMUCR);
+        ctrl_barrier();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index ccac77f504a8..cfdf7930d294 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -80,3 +80,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         __raw_writel(data, addr);
         back_to_cached();
 }
+
+void local_flush_tlb_all(void)
+{
+        unsigned long flags, status;
+        int i;
+
+        /*
+         * Flush all the TLB.
+         */
+        local_irq_save(flags);
+        jump_to_uncached();
+
+        status = __raw_readl(MMUCR);
+        status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
+
+        if (status == 0)
+                status = MMUCR_URB_NENTRIES;
+
+        for (i = 0; i < status; i++)
+                __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
+
+        for (i = 0; i < 4; i++)
+                __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
+
+        back_to_cached();
+        ctrl_barrier();
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c
index 77dc5efa7127..3fbe03ce8fe3 100644
--- a/arch/sh/mm/tlbflush_32.c
+++ b/arch/sh/mm/tlbflush_32.c
@@ -119,31 +119,3 @@ void local_flush_tlb_mm(struct mm_struct *mm)
                 local_irq_restore(flags);
         }
 }
-
-void local_flush_tlb_all(void)
-{
-        unsigned long flags, status;
-        int i;
-
-        /*
-         * Flush all the TLB.
-         */
-        local_irq_save(flags);
-        jump_to_uncached();
-
-        status = __raw_readl(MMUCR);
-        status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
-
-        if (status == 0)
-                status = MMUCR_URB_NENTRIES;
-
-        for (i = 0; i < status; i++)
-                __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
-
-        for (i = 0; i < 4; i++)
-                __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
-
-        back_to_cached();
-        ctrl_barrier();
-        local_irq_restore(flags);
-}