diff options
| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-11-13 12:04:03 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-11-13 12:04:03 -0500 |
| commit | a7fe77161da48a74c60dc19fc4ca3a73ab761d37 (patch) | |
| tree | 0fa3e785f7dd9d9bfcd3866a47a428984329a845 | |
| parent | 9104476e4efbef8a8e32d48ced583603ff32a2db (diff) | |
| parent | 6548d83a37a570b0050e60565937bbb582545d96 (diff) | |
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
[POWERPC] Silence an annoying boot message
[POWERPC] Fix early btext debug on PowerMac
[POWERPC] Demote clockevent printk to KERN_DEBUG
[POWERPC] Fix CONFIG_SMP=n build error on ppc64
[POWERPC] Avoid unpaired stwcx. on some processors
[POWERPC] Fix oops related to 4xx flush_tlb_page modification
[POWERPC] cpm: Fix a couple minor issues in cpm_common.c.
[POWERPC] Add -mno-spe for ARCH=powerpc builds
| -rw-r--r-- | arch/powerpc/Makefile | 3 | ||||
| -rw-r--r-- | arch/powerpc/kernel/btext.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/kernel/entry_32.S | 6 | ||||
| -rw-r--r-- | arch/powerpc/kernel/time.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/mm/init_64.c | 16 | ||||
| -rw-r--r-- | arch/powerpc/mm/tlb_64.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/sysdev/cpm_common.c | 4 | ||||
| -rw-r--r-- | arch/ppc/kernel/entry.S | 6 | ||||
| -rw-r--r-- | include/asm-powerpc/cputable.h | 22 | ||||
| -rw-r--r-- | include/asm-powerpc/tlbflush.h | 4 |
10 files changed, 38 insertions, 31 deletions
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 4e165342210a..bd87626c1f60 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile | |||
| @@ -107,6 +107,9 @@ endif | |||
| 107 | # No AltiVec instruction when building kernel | 107 | # No AltiVec instruction when building kernel |
| 108 | KBUILD_CFLAGS += $(call cc-option,-mno-altivec) | 108 | KBUILD_CFLAGS += $(call cc-option,-mno-altivec) |
| 109 | 109 | ||
| 110 | # No SPE instruction when building kernel | ||
| 111 | KBUILD_CFLAGS += $(call cc-option,-mno-spe) | ||
| 112 | |||
| 110 | # Enable unit-at-a-time mode when possible. It shrinks the | 113 | # Enable unit-at-a-time mode when possible. It shrinks the |
| 111 | # kernel considerably. | 114 | # kernel considerably. |
| 112 | KBUILD_CFLAGS += $(call cc-option,-funit-at-a-time) | 115 | KBUILD_CFLAGS += $(call cc-option,-funit-at-a-time) |
diff --git a/arch/powerpc/kernel/btext.c b/arch/powerpc/kernel/btext.c index 3ef51fb6f107..9c74fdf29eec 100644 --- a/arch/powerpc/kernel/btext.c +++ b/arch/powerpc/kernel/btext.c | |||
| @@ -186,7 +186,9 @@ int btext_initialize(struct device_node *np) | |||
| 186 | pitch = *prop; | 186 | pitch = *prop; |
| 187 | if (pitch == 1) | 187 | if (pitch == 1) |
| 188 | pitch = 0x1000; | 188 | pitch = 0x1000; |
| 189 | prop = of_get_property(np, "address", NULL); | 189 | prop = of_get_property(np, "linux,bootx-addr", NULL); |
| 190 | if (prop == NULL) | ||
| 191 | prop = of_get_property(np, "address", NULL); | ||
| 190 | if (prop) | 192 | if (prop) |
| 191 | address = *prop; | 193 | address = *prop; |
| 192 | 194 | ||
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index a7572cf464bd..69a91bd46115 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S | |||
| @@ -251,6 +251,9 @@ syscall_exit_cont: | |||
| 251 | bne- 2f | 251 | bne- 2f |
| 252 | 1: | 252 | 1: |
| 253 | #endif /* CONFIG_44x */ | 253 | #endif /* CONFIG_44x */ |
| 254 | BEGIN_FTR_SECTION | ||
| 255 | lwarx r7,0,r1 | ||
| 256 | END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) | ||
| 254 | stwcx. r0,0,r1 /* to clear the reservation */ | 257 | stwcx. r0,0,r1 /* to clear the reservation */ |
| 255 | lwz r4,_LINK(r1) | 258 | lwz r4,_LINK(r1) |
| 256 | lwz r5,_CCR(r1) | 259 | lwz r5,_CCR(r1) |
| @@ -717,6 +720,9 @@ restore: | |||
| 717 | mtctr r11 | 720 | mtctr r11 |
| 718 | 721 | ||
| 719 | PPC405_ERR77(0,r1) | 722 | PPC405_ERR77(0,r1) |
| 723 | BEGIN_FTR_SECTION | ||
| 724 | lwarx r11,0,r1 | ||
| 725 | END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) | ||
| 720 | stwcx. r0,0,r1 /* to clear the reservation */ | 726 | stwcx. r0,0,r1 /* to clear the reservation */ |
| 721 | 727 | ||
| 722 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) | 728 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) |
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 4beb6329dfb7..c0d77723ba11 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c | |||
| @@ -829,7 +829,7 @@ static void register_decrementer_clockevent(int cpu) | |||
| 829 | *dec = decrementer_clockevent; | 829 | *dec = decrementer_clockevent; |
| 830 | dec->cpumask = cpumask_of_cpu(cpu); | 830 | dec->cpumask = cpumask_of_cpu(cpu); |
| 831 | 831 | ||
| 832 | printk(KERN_INFO "clockevent: %s mult[%lx] shift[%d] cpu[%d]\n", | 832 | printk(KERN_DEBUG "clockevent: %s mult[%lx] shift[%d] cpu[%d]\n", |
| 833 | dec->name, dec->mult, dec->shift, cpu); | 833 | dec->name, dec->mult, dec->shift, cpu); |
| 834 | 834 | ||
| 835 | clockevents_register_device(dec); | 835 | clockevents_register_device(dec); |
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c index d9c82d3d6482..c0f5cff77035 100644 --- a/arch/powerpc/mm/init_64.c +++ b/arch/powerpc/mm/init_64.c | |||
| @@ -19,8 +19,6 @@ | |||
| 19 | * | 19 | * |
| 20 | */ | 20 | */ |
| 21 | 21 | ||
| 22 | #undef DEBUG | ||
| 23 | |||
| 24 | #include <linux/signal.h> | 22 | #include <linux/signal.h> |
| 25 | #include <linux/sched.h> | 23 | #include <linux/sched.h> |
| 26 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
| @@ -66,12 +64,6 @@ | |||
| 66 | 64 | ||
| 67 | #include "mmu_decl.h" | 65 | #include "mmu_decl.h" |
| 68 | 66 | ||
| 69 | #ifdef DEBUG | ||
| 70 | #define DBG(fmt...) printk(fmt) | ||
| 71 | #else | ||
| 72 | #define DBG(fmt...) | ||
| 73 | #endif | ||
| 74 | |||
| 75 | #if PGTABLE_RANGE > USER_VSID_RANGE | 67 | #if PGTABLE_RANGE > USER_VSID_RANGE |
| 76 | #warning Limited user VSID range means pagetable space is wasted | 68 | #warning Limited user VSID range means pagetable space is wasted |
| 77 | #endif | 69 | #endif |
| @@ -175,8 +167,8 @@ void pgtable_cache_init(void) | |||
| 175 | int size = pgtable_cache_size[i]; | 167 | int size = pgtable_cache_size[i]; |
| 176 | const char *name = pgtable_cache_name[i]; | 168 | const char *name = pgtable_cache_name[i]; |
| 177 | 169 | ||
| 178 | DBG("Allocating page table cache %s (#%d) " | 170 | pr_debug("Allocating page table cache %s (#%d) " |
| 179 | "for size: %08x...\n", name, i, size); | 171 | "for size: %08x...\n", name, i, size); |
| 180 | pgtable_cache[i] = kmem_cache_create(name, | 172 | pgtable_cache[i] = kmem_cache_create(name, |
| 181 | size, size, | 173 | size, size, |
| 182 | SLAB_PANIC, | 174 | SLAB_PANIC, |
| @@ -239,8 +231,8 @@ int __meminit vmemmap_populate(struct page *start_page, | |||
| 239 | if (!p) | 231 | if (!p) |
| 240 | return -ENOMEM; | 232 | return -ENOMEM; |
| 241 | 233 | ||
| 242 | printk(KERN_WARNING "vmemmap %08lx allocated at %p, " | 234 | pr_debug("vmemmap %08lx allocated at %p, physical %08lx.\n", |
| 243 | "physical %08lx.\n", start, p, __pa(p)); | 235 | start, p, __pa(p)); |
| 244 | 236 | ||
| 245 | mapped = htab_bolt_mapping(start, start + page_size, | 237 | mapped = htab_bolt_mapping(start, start + page_size, |
| 246 | __pa(p), mode_rw, mmu_linear_psize, | 238 | __pa(p), mode_rw, mmu_linear_psize, |
diff --git a/arch/powerpc/mm/tlb_64.c b/arch/powerpc/mm/tlb_64.c index eafbca52bff9..e2d867ce1c7e 100644 --- a/arch/powerpc/mm/tlb_64.c +++ b/arch/powerpc/mm/tlb_64.c | |||
| @@ -54,12 +54,10 @@ unsigned long pte_freelist_forced_free; | |||
| 54 | ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \ | 54 | ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \ |
| 55 | / sizeof(pgtable_free_t)) | 55 | / sizeof(pgtable_free_t)) |
| 56 | 56 | ||
| 57 | #ifdef CONFIG_SMP | ||
| 58 | static void pte_free_smp_sync(void *arg) | 57 | static void pte_free_smp_sync(void *arg) |
| 59 | { | 58 | { |
| 60 | /* Do nothing, just ensure we sync with all CPUs */ | 59 | /* Do nothing, just ensure we sync with all CPUs */ |
| 61 | } | 60 | } |
| 62 | #endif | ||
| 63 | 61 | ||
| 64 | /* This is only called when we are critically out of memory | 62 | /* This is only called when we are critically out of memory |
| 65 | * (and fail to get a page in pte_free_tlb). | 63 | * (and fail to get a page in pte_free_tlb). |
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c index 66c8ad4cfce6..165981c87786 100644 --- a/arch/powerpc/sysdev/cpm_common.c +++ b/arch/powerpc/sysdev/cpm_common.c | |||
| @@ -77,8 +77,6 @@ int __init cpm_muram_init(void) | |||
| 77 | int i = 0; | 77 | int i = 0; |
| 78 | int ret = 0; | 78 | int ret = 0; |
| 79 | 79 | ||
| 80 | printk("cpm_muram_init\n"); | ||
| 81 | |||
| 82 | spin_lock_init(&cpm_muram_lock); | 80 | spin_lock_init(&cpm_muram_lock); |
| 83 | /* initialize the info header */ | 81 | /* initialize the info header */ |
| 84 | rh_init(&cpm_muram_info, 1, | 82 | rh_init(&cpm_muram_info, 1, |
| @@ -193,7 +191,7 @@ void __iomem *cpm_muram_addr(unsigned long offset) | |||
| 193 | EXPORT_SYMBOL(cpm_muram_addr); | 191 | EXPORT_SYMBOL(cpm_muram_addr); |
| 194 | 192 | ||
| 195 | /** | 193 | /** |
| 196 | * cpm_muram_phys - turn a muram virtual address into a DMA address | 194 | * cpm_muram_dma - turn a muram virtual address into a DMA address |
| 197 | * @offset: virtual address from cpm_muram_addr() to convert | 195 | * @offset: virtual address from cpm_muram_addr() to convert |
| 198 | */ | 196 | */ |
| 199 | dma_addr_t cpm_muram_dma(void __iomem *addr) | 197 | dma_addr_t cpm_muram_dma(void __iomem *addr) |
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S index b19bfef2034d..59e77eb63338 100644 --- a/arch/ppc/kernel/entry.S +++ b/arch/ppc/kernel/entry.S | |||
| @@ -251,6 +251,9 @@ syscall_exit_cont: | |||
| 251 | bne- 2f | 251 | bne- 2f |
| 252 | 1: | 252 | 1: |
| 253 | #endif /* CONFIG_44x */ | 253 | #endif /* CONFIG_44x */ |
| 254 | BEGIN_FTR_SECTION | ||
| 255 | lwarx r7,0,r1 | ||
| 256 | END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) | ||
| 254 | stwcx. r0,0,r1 /* to clear the reservation */ | 257 | stwcx. r0,0,r1 /* to clear the reservation */ |
| 255 | lwz r4,_LINK(r1) | 258 | lwz r4,_LINK(r1) |
| 256 | lwz r5,_CCR(r1) | 259 | lwz r5,_CCR(r1) |
| @@ -713,6 +716,9 @@ restore: | |||
| 713 | mtctr r11 | 716 | mtctr r11 |
| 714 | 717 | ||
| 715 | PPC405_ERR77(0,r1) | 718 | PPC405_ERR77(0,r1) |
| 719 | BEGIN_FTR_SECTION | ||
| 720 | lwarx r11,0,r1 | ||
| 721 | END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) | ||
| 716 | stwcx. r0,0,r1 /* to clear the reservation */ | 722 | stwcx. r0,0,r1 /* to clear the reservation */ |
| 717 | 723 | ||
| 718 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) | 724 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) |
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 9d74338e3dec..4525c784dfd0 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
| @@ -138,6 +138,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 138 | #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) | 138 | #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) |
| 139 | #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) | 139 | #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) |
| 140 | #define CPU_FTR_SPE ASM_CONST(0x0000000002000000) | 140 | #define CPU_FTR_SPE ASM_CONST(0x0000000002000000) |
| 141 | #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000) | ||
| 141 | 142 | ||
| 142 | /* | 143 | /* |
| 143 | * Add the 64-bit processor unique features in the top half of the word; | 144 | * Add the 64-bit processor unique features in the top half of the word; |
| @@ -261,25 +262,25 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 261 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ | 262 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ |
| 262 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 263 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 263 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 264 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 264 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 265 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
| 265 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ | 266 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ |
| 266 | CPU_FTR_USE_TB | \ | 267 | CPU_FTR_USE_TB | \ |
| 267 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 268 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 268 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 269 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 269 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 270 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| 270 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 271 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
| 271 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ | 272 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ |
| 272 | CPU_FTR_USE_TB | \ | 273 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
| 273 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 274 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 274 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 275 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 275 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 276 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 276 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ | 277 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ |
| 277 | CPU_FTR_USE_TB | \ | 278 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
| 278 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ | 279 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
| 279 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ | 280 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ |
| 280 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 281 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 281 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ | 282 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ |
| 282 | CPU_FTR_USE_TB | \ | 283 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
| 283 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 284 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 284 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 285 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 285 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 286 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| @@ -289,31 +290,32 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, | |||
| 289 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 290 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 290 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 291 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 291 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 292 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 292 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 293 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
| 293 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ | 294 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ |
| 294 | CPU_FTR_USE_TB | \ | 295 | CPU_FTR_USE_TB | \ |
| 295 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 296 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 296 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 297 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 297 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 298 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 298 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) | 299 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ |
| 300 | CPU_FTR_NEED_PAIRED_STWCX) | ||
| 299 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ | 301 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ |
| 300 | CPU_FTR_USE_TB | \ | 302 | CPU_FTR_USE_TB | \ |
| 301 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 303 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 302 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 304 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 303 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 305 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 304 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 306 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
| 305 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ | 307 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ |
| 306 | CPU_FTR_USE_TB | \ | 308 | CPU_FTR_USE_TB | \ |
| 307 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 309 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 308 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 310 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 309 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 311 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 310 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 312 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
| 311 | #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ | 313 | #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ |
| 312 | CPU_FTR_USE_TB | \ | 314 | CPU_FTR_USE_TB | \ |
| 313 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 315 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 314 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 316 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 315 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 317 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 316 | CPU_FTR_PPC_LE) | 318 | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
| 317 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ | 319 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ |
| 318 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) | 320 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) |
| 319 | #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ | 321 | #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ |
diff --git a/include/asm-powerpc/tlbflush.h b/include/asm-powerpc/tlbflush.h index e7b4c0d298ae..5c9108147644 100644 --- a/include/asm-powerpc/tlbflush.h +++ b/include/asm-powerpc/tlbflush.h | |||
| @@ -44,13 +44,13 @@ static inline void flush_tlb_mm(struct mm_struct *mm) | |||
| 44 | static inline void flush_tlb_page(struct vm_area_struct *vma, | 44 | static inline void flush_tlb_page(struct vm_area_struct *vma, |
| 45 | unsigned long vmaddr) | 45 | unsigned long vmaddr) |
| 46 | { | 46 | { |
| 47 | _tlbie(vmaddr, vma->vm_mm->context.id); | 47 | _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0); |
| 48 | } | 48 | } |
| 49 | 49 | ||
| 50 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, | 50 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, |
| 51 | unsigned long vmaddr) | 51 | unsigned long vmaddr) |
| 52 | { | 52 | { |
| 53 | _tlbie(vmaddr, vma->vm_mm->context.id); | 53 | _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0); |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | static inline void flush_tlb_range(struct vm_area_struct *vma, | 56 | static inline void flush_tlb_range(struct vm_area_struct *vma, |
