diff options
| author | Grant Likely <grant.likely@secretlab.ca> | 2008-04-29 09:19:07 -0400 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2008-04-29 09:19:07 -0400 |
| commit | a2884f37b6fe0074df70ebeb3a6c54201267663c (patch) | |
| tree | 5a4eec613f670d05a380d9190ae521aa480e4652 | |
| parent | 8f3ba2dc811228213bcbdc2c8b389a8d6fa66c09 (diff) | |
[POWERPC] mpc5200: Switch mpc5200 dts files to dts-v1 format
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| -rw-r--r-- | arch/powerpc/boot/dts/cm5200.dts | 98 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/lite5200.dts | 132 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/lite5200b.dts | 146 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/motionpro.dts | 118 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/tqm5200.dts | 80 |
5 files changed, 286 insertions, 288 deletions
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts index c6ca6319e4f7..2f74cc4e093e 100644 --- a/arch/powerpc/boot/dts/cm5200.dts +++ b/arch/powerpc/boot/dts/cm5200.dts | |||
| @@ -10,11 +10,7 @@ | |||
| 10 | * option) any later version. | 10 | * option) any later version. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /* | 13 | /dts-v1/; |
| 14 | * WARNING: Do not depend on this tree layout remaining static just yet. | ||
| 15 | * The MPC5200 device tree conventions are still in flux | ||
| 16 | * Keep an eye on the linuxppc-dev mailing list for more details | ||
| 17 | */ | ||
| 18 | 14 | ||
| 19 | / { | 15 | / { |
| 20 | model = "schindler,cm5200"; | 16 | model = "schindler,cm5200"; |
| @@ -29,10 +25,10 @@ | |||
| 29 | PowerPC,5200@0 { | 25 | PowerPC,5200@0 { |
| 30 | device_type = "cpu"; | 26 | device_type = "cpu"; |
| 31 | reg = <0>; | 27 | reg = <0>; |
| 32 | d-cache-line-size = <20>; | 28 | d-cache-line-size = <32>; |
| 33 | i-cache-line-size = <20>; | 29 | i-cache-line-size = <32>; |
| 34 | d-cache-size = <4000>; // L1, 16K | 30 | d-cache-size = <0x4000>; // L1, 16K |
| 35 | i-cache-size = <4000>; // L1, 16K | 31 | i-cache-size = <0x4000>; // L1, 16K |
| 36 | timebase-frequency = <0>; // from bootloader | 32 | timebase-frequency = <0>; // from bootloader |
| 37 | bus-frequency = <0>; // from bootloader | 33 | bus-frequency = <0>; // from bootloader |
| 38 | clock-frequency = <0>; // from bootloader | 34 | clock-frequency = <0>; // from bootloader |
| @@ -41,34 +37,34 @@ | |||
| 41 | 37 | ||
| 42 | memory { | 38 | memory { |
| 43 | device_type = "memory"; | 39 | device_type = "memory"; |
| 44 | reg = <00000000 04000000>; // 64MB | 40 | reg = <0x00000000 0x04000000>; // 64MB |
| 45 | }; | 41 | }; |
| 46 | 42 | ||
| 47 | soc5200@f0000000 { | 43 | soc5200@f0000000 { |
| 48 | #address-cells = <1>; | 44 | #address-cells = <1>; |
| 49 | #size-cells = <1>; | 45 | #size-cells = <1>; |
| 50 | compatible = "fsl,mpc5200b-immr"; | 46 | compatible = "fsl,mpc5200b-immr"; |
| 51 | ranges = <0 f0000000 0000c000>; | 47 | ranges = <0 0xf0000000 0x0000c000>; |
| 52 | reg = <f0000000 00000100>; | 48 | reg = <0xf0000000 0x00000100>; |
| 53 | bus-frequency = <0>; // from bootloader | 49 | bus-frequency = <0>; // from bootloader |
| 54 | system-frequency = <0>; // from bootloader | 50 | system-frequency = <0>; // from bootloader |
| 55 | 51 | ||
| 56 | cdm@200 { | 52 | cdm@200 { |
| 57 | compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; | 53 | compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; |
| 58 | reg = <200 38>; | 54 | reg = <0x200 0x38>; |
| 59 | }; | 55 | }; |
| 60 | 56 | ||
| 61 | mpc5200_pic: pic@500 { | 57 | mpc5200_pic: interrupt-controller@500 { |
| 62 | // 5200 interrupts are encoded into two levels; | 58 | // 5200 interrupts are encoded into two levels; |
| 63 | interrupt-controller; | 59 | interrupt-controller; |
| 64 | #interrupt-cells = <3>; | 60 | #interrupt-cells = <3>; |
| 65 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; | 61 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; |
| 66 | reg = <500 80>; | 62 | reg = <0x500 0x80>; |
| 67 | }; | 63 | }; |
| 68 | 64 | ||
| 69 | timer@600 { // General Purpose Timer | 65 | timer@600 { // General Purpose Timer |
| 70 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 66 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 71 | reg = <600 10>; | 67 | reg = <0x600 0x10>; |
| 72 | interrupts = <1 9 0>; | 68 | interrupts = <1 9 0>; |
| 73 | interrupt-parent = <&mpc5200_pic>; | 69 | interrupt-parent = <&mpc5200_pic>; |
| 74 | fsl,has-wdt; | 70 | fsl,has-wdt; |
| @@ -76,108 +72,108 @@ | |||
| 76 | 72 | ||
| 77 | timer@610 { // General Purpose Timer | 73 | timer@610 { // General Purpose Timer |
| 78 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 74 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 79 | reg = <610 10>; | 75 | reg = <0x610 0x10>; |
| 80 | interrupts = <1 a 0>; | 76 | interrupts = <1 10 0>; |
| 81 | interrupt-parent = <&mpc5200_pic>; | 77 | interrupt-parent = <&mpc5200_pic>; |
| 82 | }; | 78 | }; |
| 83 | 79 | ||
| 84 | timer@620 { // General Purpose Timer | 80 | timer@620 { // General Purpose Timer |
| 85 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 81 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 86 | reg = <620 10>; | 82 | reg = <0x620 0x10>; |
| 87 | interrupts = <1 b 0>; | 83 | interrupts = <1 11 0>; |
| 88 | interrupt-parent = <&mpc5200_pic>; | 84 | interrupt-parent = <&mpc5200_pic>; |
| 89 | }; | 85 | }; |
| 90 | 86 | ||
| 91 | timer@630 { // General Purpose Timer | 87 | timer@630 { // General Purpose Timer |
| 92 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 88 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 93 | reg = <630 10>; | 89 | reg = <0x630 0x10>; |
| 94 | interrupts = <1 c 0>; | 90 | interrupts = <1 12 0>; |
| 95 | interrupt-parent = <&mpc5200_pic>; | 91 | interrupt-parent = <&mpc5200_pic>; |
| 96 | }; | 92 | }; |
| 97 | 93 | ||
| 98 | timer@640 { // General Purpose Timer | 94 | timer@640 { // General Purpose Timer |
| 99 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 95 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 100 | reg = <640 10>; | 96 | reg = <0x640 0x10>; |
| 101 | interrupts = <1 d 0>; | 97 | interrupts = <1 13 0>; |
| 102 | interrupt-parent = <&mpc5200_pic>; | 98 | interrupt-parent = <&mpc5200_pic>; |
| 103 | }; | 99 | }; |
| 104 | 100 | ||
| 105 | timer@650 { // General Purpose Timer | 101 | timer@650 { // General Purpose Timer |
| 106 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 102 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 107 | reg = <650 10>; | 103 | reg = <0x650 0x10>; |
| 108 | interrupts = <1 e 0>; | 104 | interrupts = <1 14 0>; |
| 109 | interrupt-parent = <&mpc5200_pic>; | 105 | interrupt-parent = <&mpc5200_pic>; |
| 110 | }; | 106 | }; |
| 111 | 107 | ||
| 112 | timer@660 { // General Purpose Timer | 108 | timer@660 { // General Purpose Timer |
| 113 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 109 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 114 | reg = <660 10>; | 110 | reg = <0x660 0x10>; |
| 115 | interrupts = <1 f 0>; | 111 | interrupts = <1 15 0>; |
| 116 | interrupt-parent = <&mpc5200_pic>; | 112 | interrupt-parent = <&mpc5200_pic>; |
| 117 | }; | 113 | }; |
| 118 | 114 | ||
| 119 | timer@670 { // General Purpose Timer | 115 | timer@670 { // General Purpose Timer |
| 120 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 116 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 121 | reg = <670 10>; | 117 | reg = <0x670 0x10>; |
| 122 | interrupts = <1 10 0>; | 118 | interrupts = <1 16 0>; |
| 123 | interrupt-parent = <&mpc5200_pic>; | 119 | interrupt-parent = <&mpc5200_pic>; |
| 124 | }; | 120 | }; |
| 125 | 121 | ||
| 126 | rtc@800 { // Real time clock | 122 | rtc@800 { // Real time clock |
| 127 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; | 123 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; |
| 128 | reg = <800 100>; | 124 | reg = <0x800 0x100>; |
| 129 | interrupts = <1 5 0 1 6 0>; | 125 | interrupts = <1 5 0 1 6 0>; |
| 130 | interrupt-parent = <&mpc5200_pic>; | 126 | interrupt-parent = <&mpc5200_pic>; |
| 131 | }; | 127 | }; |
| 132 | 128 | ||
| 133 | gpio@b00 { | 129 | gpio@b00 { |
| 134 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; | 130 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; |
| 135 | reg = <b00 40>; | 131 | reg = <0xb00 0x40>; |
| 136 | interrupts = <1 7 0>; | 132 | interrupts = <1 7 0>; |
| 137 | interrupt-parent = <&mpc5200_pic>; | 133 | interrupt-parent = <&mpc5200_pic>; |
| 138 | }; | 134 | }; |
| 139 | 135 | ||
| 140 | gpio@c00 { | 136 | gpio@c00 { |
| 141 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; | 137 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; |
| 142 | reg = <c00 40>; | 138 | reg = <0xc00 0x40>; |
| 143 | interrupts = <1 8 0 0 3 0>; | 139 | interrupts = <1 8 0 0 3 0>; |
| 144 | interrupt-parent = <&mpc5200_pic>; | 140 | interrupt-parent = <&mpc5200_pic>; |
| 145 | }; | 141 | }; |
| 146 | 142 | ||
| 147 | spi@f00 { | 143 | spi@f00 { |
| 148 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | 144 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
| 149 | reg = <f00 20>; | 145 | reg = <0xf00 0x20>; |
| 150 | interrupts = <2 d 0 2 e 0>; | 146 | interrupts = <2 13 0 2 14 0>; |
| 151 | interrupt-parent = <&mpc5200_pic>; | 147 | interrupt-parent = <&mpc5200_pic>; |
| 152 | }; | 148 | }; |
| 153 | 149 | ||
| 154 | usb@1000 { | 150 | usb@1000 { |
| 155 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; | 151 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; |
| 156 | reg = <1000 ff>; | 152 | reg = <0x1000 0xff>; |
| 157 | interrupts = <2 6 0>; | 153 | interrupts = <2 6 0>; |
| 158 | interrupt-parent = <&mpc5200_pic>; | 154 | interrupt-parent = <&mpc5200_pic>; |
| 159 | }; | 155 | }; |
| 160 | 156 | ||
| 161 | dma-controller@1200 { | 157 | dma-controller@1200 { |
| 162 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; | 158 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; |
| 163 | reg = <1200 80>; | 159 | reg = <0x1200 0x80>; |
| 164 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 | 160 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
| 165 | 3 4 0 3 5 0 3 6 0 3 7 0 | 161 | 3 4 0 3 5 0 3 6 0 3 7 0 |
| 166 | 3 8 0 3 9 0 3 a 0 3 b 0 | 162 | 3 8 0 3 9 0 3 10 0 3 11 0 |
| 167 | 3 c 0 3 d 0 3 e 0 3 f 0>; | 163 | 3 12 0 3 13 0 3 14 0 3 15 0>; |
| 168 | interrupt-parent = <&mpc5200_pic>; | 164 | interrupt-parent = <&mpc5200_pic>; |
| 169 | }; | 165 | }; |
| 170 | 166 | ||
| 171 | xlb@1f00 { | 167 | xlb@1f00 { |
| 172 | compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; | 168 | compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; |
| 173 | reg = <1f00 100>; | 169 | reg = <0x1f00 0x100>; |
| 174 | }; | 170 | }; |
| 175 | 171 | ||
| 176 | serial@2000 { // PSC1 | 172 | serial@2000 { // PSC1 |
| 177 | device_type = "serial"; | 173 | device_type = "serial"; |
| 178 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 174 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| 179 | port-number = <0>; // Logical port assignment | 175 | port-number = <0>; // Logical port assignment |
| 180 | reg = <2000 100>; | 176 | reg = <0x2000 0x100>; |
| 181 | interrupts = <2 1 0>; | 177 | interrupts = <2 1 0>; |
| 182 | interrupt-parent = <&mpc5200_pic>; | 178 | interrupt-parent = <&mpc5200_pic>; |
| 183 | }; | 179 | }; |
| @@ -186,7 +182,7 @@ | |||
| 186 | device_type = "serial"; | 182 | device_type = "serial"; |
| 187 | compatible = "fsl,mpc5200-psc-uart"; | 183 | compatible = "fsl,mpc5200-psc-uart"; |
| 188 | port-number = <1>; // Logical port assignment | 184 | port-number = <1>; // Logical port assignment |
| 189 | reg = <2200 100>; | 185 | reg = <0x2200 0x100>; |
| 190 | interrupts = <2 2 0>; | 186 | interrupts = <2 2 0>; |
| 191 | interrupt-parent = <&mpc5200_pic>; | 187 | interrupt-parent = <&mpc5200_pic>; |
| 192 | }; | 188 | }; |
| @@ -195,7 +191,7 @@ | |||
| 195 | device_type = "serial"; | 191 | device_type = "serial"; |
| 196 | compatible = "fsl,mpc5200-psc-uart"; | 192 | compatible = "fsl,mpc5200-psc-uart"; |
| 197 | port-number = <2>; // Logical port assignment | 193 | port-number = <2>; // Logical port assignment |
| 198 | reg = <2400 100>; | 194 | reg = <0x2400 0x100>; |
| 199 | interrupts = <2 3 0>; | 195 | interrupts = <2 3 0>; |
| 200 | interrupt-parent = <&mpc5200_pic>; | 196 | interrupt-parent = <&mpc5200_pic>; |
| 201 | }; | 197 | }; |
| @@ -204,7 +200,7 @@ | |||
| 204 | device_type = "serial"; | 200 | device_type = "serial"; |
| 205 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 201 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| 206 | port-number = <5>; // Logical port assignment | 202 | port-number = <5>; // Logical port assignment |
| 207 | reg = <2c00 100>; | 203 | reg = <0x2c00 0x100>; |
| 208 | interrupts = <2 4 0>; | 204 | interrupts = <2 4 0>; |
| 209 | interrupt-parent = <&mpc5200_pic>; | 205 | interrupt-parent = <&mpc5200_pic>; |
| 210 | }; | 206 | }; |
| @@ -212,7 +208,7 @@ | |||
| 212 | ethernet@3000 { | 208 | ethernet@3000 { |
| 213 | device_type = "network"; | 209 | device_type = "network"; |
| 214 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; | 210 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; |
| 215 | reg = <3000 400>; | 211 | reg = <0x3000 0x400>; |
| 216 | local-mac-address = [ 00 00 00 00 00 00 ]; | 212 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 217 | interrupts = <2 5 0>; | 213 | interrupts = <2 5 0>; |
| 218 | interrupt-parent = <&mpc5200_pic>; | 214 | interrupt-parent = <&mpc5200_pic>; |
| @@ -223,7 +219,7 @@ | |||
| 223 | #address-cells = <1>; | 219 | #address-cells = <1>; |
| 224 | #size-cells = <0>; | 220 | #size-cells = <0>; |
| 225 | compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; | 221 | compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; |
| 226 | reg = <3000 400>; // fec range, since we need to setup fec interrupts | 222 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts |
| 227 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. | 223 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
| 228 | interrupt-parent = <&mpc5200_pic>; | 224 | interrupt-parent = <&mpc5200_pic>; |
| 229 | 225 | ||
| @@ -237,15 +233,15 @@ | |||
| 237 | #address-cells = <1>; | 233 | #address-cells = <1>; |
| 238 | #size-cells = <0>; | 234 | #size-cells = <0>; |
| 239 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | 235 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
| 240 | reg = <3d40 40>; | 236 | reg = <0x3d40 0x40>; |
| 241 | interrupts = <2 10 0>; | 237 | interrupts = <2 16 0>; |
| 242 | interrupt-parent = <&mpc5200_pic>; | 238 | interrupt-parent = <&mpc5200_pic>; |
| 243 | fsl5200-clocking; | 239 | fsl5200-clocking; |
| 244 | }; | 240 | }; |
| 245 | 241 | ||
| 246 | sram@8000 { | 242 | sram@8000 { |
| 247 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; | 243 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; |
| 248 | reg = <8000 4000>; | 244 | reg = <0x8000 0x4000>; |
| 249 | }; | 245 | }; |
| 250 | }; | 246 | }; |
| 251 | 247 | ||
| @@ -254,12 +250,12 @@ | |||
| 254 | compatible = "fsl,lpb"; | 250 | compatible = "fsl,lpb"; |
| 255 | #address-cells = <2>; | 251 | #address-cells = <2>; |
| 256 | #size-cells = <1>; | 252 | #size-cells = <1>; |
| 257 | ranges = <0 0 fc000000 2000000>; | 253 | ranges = <0 0 0xfc000000 0x2000000>; |
| 258 | 254 | ||
| 259 | // 16-bit flash device at LocalPlus Bus CS0 | 255 | // 16-bit flash device at LocalPlus Bus CS0 |
| 260 | flash@0,0 { | 256 | flash@0,0 { |
| 261 | compatible = "cfi-flash"; | 257 | compatible = "cfi-flash"; |
| 262 | reg = <0 0 2000000>; | 258 | reg = <0 0 0x2000000>; |
| 263 | bank-width = <2>; | 259 | bank-width = <2>; |
| 264 | device-width = <2>; | 260 | device-width = <2>; |
| 265 | #size-cells = <1>; | 261 | #size-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts index 09b4e16154d6..2cf9a8768f44 100644 --- a/arch/powerpc/boot/dts/lite5200.dts +++ b/arch/powerpc/boot/dts/lite5200.dts | |||
| @@ -10,6 +10,8 @@ | |||
| 10 | * option) any later version. | 10 | * option) any later version. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | ||
| 14 | |||
| 13 | / { | 15 | / { |
| 14 | model = "fsl,lite5200"; | 16 | model = "fsl,lite5200"; |
| 15 | compatible = "fsl,lite5200"; | 17 | compatible = "fsl,lite5200"; |
| @@ -23,10 +25,10 @@ | |||
| 23 | PowerPC,5200@0 { | 25 | PowerPC,5200@0 { |
| 24 | device_type = "cpu"; | 26 | device_type = "cpu"; |
| 25 | reg = <0>; | 27 | reg = <0>; |
| 26 | d-cache-line-size = <20>; | 28 | d-cache-line-size = <32>; |
| 27 | i-cache-line-size = <20>; | 29 | i-cache-line-size = <32>; |
| 28 | d-cache-size = <4000>; // L1, 16K | 30 | d-cache-size = <0x4000>; // L1, 16K |
| 29 | i-cache-size = <4000>; // L1, 16K | 31 | i-cache-size = <0x4000>; // L1, 16K |
| 30 | timebase-frequency = <0>; // from bootloader | 32 | timebase-frequency = <0>; // from bootloader |
| 31 | bus-frequency = <0>; // from bootloader | 33 | bus-frequency = <0>; // from bootloader |
| 32 | clock-frequency = <0>; // from bootloader | 34 | clock-frequency = <0>; // from bootloader |
| @@ -35,21 +37,21 @@ | |||
| 35 | 37 | ||
| 36 | memory { | 38 | memory { |
| 37 | device_type = "memory"; | 39 | device_type = "memory"; |
| 38 | reg = <00000000 04000000>; // 64MB | 40 | reg = <0x00000000 0x04000000>; // 64MB |
| 39 | }; | 41 | }; |
| 40 | 42 | ||
| 41 | soc5200@f0000000 { | 43 | soc5200@f0000000 { |
| 42 | #address-cells = <1>; | 44 | #address-cells = <1>; |
| 43 | #size-cells = <1>; | 45 | #size-cells = <1>; |
| 44 | compatible = "fsl,mpc5200-immr"; | 46 | compatible = "fsl,mpc5200-immr"; |
| 45 | ranges = <0 f0000000 0000c000>; | 47 | ranges = <0 0xf0000000 0x0000c000>; |
| 46 | reg = <f0000000 00000100>; | 48 | reg = <0xf0000000 0x00000100>; |
| 47 | bus-frequency = <0>; // from bootloader | 49 | bus-frequency = <0>; // from bootloader |
| 48 | system-frequency = <0>; // from bootloader | 50 | system-frequency = <0>; // from bootloader |
| 49 | 51 | ||
| 50 | cdm@200 { | 52 | cdm@200 { |
| 51 | compatible = "fsl,mpc5200-cdm"; | 53 | compatible = "fsl,mpc5200-cdm"; |
| 52 | reg = <200 38>; | 54 | reg = <0x200 0x38>; |
| 53 | }; | 55 | }; |
| 54 | 56 | ||
| 55 | mpc5200_pic: interrupt-controller@500 { | 57 | mpc5200_pic: interrupt-controller@500 { |
| @@ -58,13 +60,13 @@ | |||
| 58 | #interrupt-cells = <3>; | 60 | #interrupt-cells = <3>; |
| 59 | device_type = "interrupt-controller"; | 61 | device_type = "interrupt-controller"; |
| 60 | compatible = "fsl,mpc5200-pic"; | 62 | compatible = "fsl,mpc5200-pic"; |
| 61 | reg = <500 80>; | 63 | reg = <0x500 0x80>; |
| 62 | }; | 64 | }; |
| 63 | 65 | ||
| 64 | timer@600 { // General Purpose Timer | 66 | timer@600 { // General Purpose Timer |
| 65 | compatible = "fsl,mpc5200-gpt"; | 67 | compatible = "fsl,mpc5200-gpt"; |
| 66 | cell-index = <0>; | 68 | cell-index = <0>; |
| 67 | reg = <600 10>; | 69 | reg = <0x600 0x10>; |
| 68 | interrupts = <1 9 0>; | 70 | interrupts = <1 9 0>; |
| 69 | interrupt-parent = <&mpc5200_pic>; | 71 | interrupt-parent = <&mpc5200_pic>; |
| 70 | fsl,has-wdt; | 72 | fsl,has-wdt; |
| @@ -73,63 +75,63 @@ | |||
| 73 | timer@610 { // General Purpose Timer | 75 | timer@610 { // General Purpose Timer |
| 74 | compatible = "fsl,mpc5200-gpt"; | 76 | compatible = "fsl,mpc5200-gpt"; |
| 75 | cell-index = <1>; | 77 | cell-index = <1>; |
| 76 | reg = <610 10>; | 78 | reg = <0x610 0x10>; |
| 77 | interrupts = <1 a 0>; | 79 | interrupts = <1 10 0>; |
| 78 | interrupt-parent = <&mpc5200_pic>; | 80 | interrupt-parent = <&mpc5200_pic>; |
| 79 | }; | 81 | }; |
| 80 | 82 | ||
| 81 | timer@620 { // General Purpose Timer | 83 | timer@620 { // General Purpose Timer |
| 82 | compatible = "fsl,mpc5200-gpt"; | 84 | compatible = "fsl,mpc5200-gpt"; |
| 83 | cell-index = <2>; | 85 | cell-index = <2>; |
| 84 | reg = <620 10>; | 86 | reg = <0x620 0x10>; |
| 85 | interrupts = <1 b 0>; | 87 | interrupts = <1 11 0>; |
| 86 | interrupt-parent = <&mpc5200_pic>; | 88 | interrupt-parent = <&mpc5200_pic>; |
| 87 | }; | 89 | }; |
| 88 | 90 | ||
| 89 | timer@630 { // General Purpose Timer | 91 | timer@630 { // General Purpose Timer |
| 90 | compatible = "fsl,mpc5200-gpt"; | 92 | compatible = "fsl,mpc5200-gpt"; |
| 91 | cell-index = <3>; | 93 | cell-index = <3>; |
| 92 | reg = <630 10>; | 94 | reg = <0x630 0x10>; |
| 93 | interrupts = <1 c 0>; | 95 | interrupts = <1 12 0>; |
| 94 | interrupt-parent = <&mpc5200_pic>; | 96 | interrupt-parent = <&mpc5200_pic>; |
| 95 | }; | 97 | }; |
| 96 | 98 | ||
| 97 | timer@640 { // General Purpose Timer | 99 | timer@640 { // General Purpose Timer |
| 98 | compatible = "fsl,mpc5200-gpt"; | 100 | compatible = "fsl,mpc5200-gpt"; |
| 99 | cell-index = <4>; | 101 | cell-index = <4>; |
| 100 | reg = <640 10>; | 102 | reg = <0x640 0x10>; |
| 101 | interrupts = <1 d 0>; | 103 | interrupts = <1 13 0>; |
| 102 | interrupt-parent = <&mpc5200_pic>; | 104 | interrupt-parent = <&mpc5200_pic>; |
| 103 | }; | 105 | }; |
| 104 | 106 | ||
| 105 | timer@650 { // General Purpose Timer | 107 | timer@650 { // General Purpose Timer |
| 106 | compatible = "fsl,mpc5200-gpt"; | 108 | compatible = "fsl,mpc5200-gpt"; |
| 107 | cell-index = <5>; | 109 | cell-index = <5>; |
| 108 | reg = <650 10>; | 110 | reg = <0x650 0x10>; |
| 109 | interrupts = <1 e 0>; | 111 | interrupts = <1 14 0>; |
| 110 | interrupt-parent = <&mpc5200_pic>; | 112 | interrupt-parent = <&mpc5200_pic>; |
| 111 | }; | 113 | }; |
| 112 | 114 | ||
| 113 | timer@660 { // General Purpose Timer | 115 | timer@660 { // General Purpose Timer |
| 114 | compatible = "fsl,mpc5200-gpt"; | 116 | compatible = "fsl,mpc5200-gpt"; |
| 115 | cell-index = <6>; | 117 | cell-index = <6>; |
| 116 | reg = <660 10>; | 118 | reg = <0x660 0x10>; |
| 117 | interrupts = <1 f 0>; | 119 | interrupts = <1 15 0>; |
| 118 | interrupt-parent = <&mpc5200_pic>; | 120 | interrupt-parent = <&mpc5200_pic>; |
| 119 | }; | 121 | }; |
| 120 | 122 | ||
| 121 | timer@670 { // General Purpose Timer | 123 | timer@670 { // General Purpose Timer |
| 122 | compatible = "fsl,mpc5200-gpt"; | 124 | compatible = "fsl,mpc5200-gpt"; |
| 123 | cell-index = <7>; | 125 | cell-index = <7>; |
| 124 | reg = <670 10>; | 126 | reg = <0x670 0x10>; |
| 125 | interrupts = <1 10 0>; | 127 | interrupts = <1 16 0>; |
| 126 | interrupt-parent = <&mpc5200_pic>; | 128 | interrupt-parent = <&mpc5200_pic>; |
| 127 | }; | 129 | }; |
| 128 | 130 | ||
| 129 | rtc@800 { // Real time clock | 131 | rtc@800 { // Real time clock |
| 130 | compatible = "fsl,mpc5200-rtc"; | 132 | compatible = "fsl,mpc5200-rtc"; |
| 131 | device_type = "rtc"; | 133 | device_type = "rtc"; |
| 132 | reg = <800 100>; | 134 | reg = <0x800 0x100>; |
| 133 | interrupts = <1 5 0 1 6 0>; | 135 | interrupts = <1 5 0 1 6 0>; |
| 134 | interrupt-parent = <&mpc5200_pic>; | 136 | interrupt-parent = <&mpc5200_pic>; |
| 135 | }; | 137 | }; |
| @@ -137,43 +139,43 @@ | |||
| 137 | can@900 { | 139 | can@900 { |
| 138 | compatible = "fsl,mpc5200-mscan"; | 140 | compatible = "fsl,mpc5200-mscan"; |
| 139 | cell-index = <0>; | 141 | cell-index = <0>; |
| 140 | interrupts = <2 11 0>; | 142 | interrupts = <2 17 0>; |
| 141 | interrupt-parent = <&mpc5200_pic>; | 143 | interrupt-parent = <&mpc5200_pic>; |
| 142 | reg = <900 80>; | 144 | reg = <0x900 0x80>; |
| 143 | }; | 145 | }; |
| 144 | 146 | ||
| 145 | can@980 { | 147 | can@980 { |
| 146 | compatible = "fsl,mpc5200-mscan"; | 148 | compatible = "fsl,mpc5200-mscan"; |
| 147 | cell-index = <1>; | 149 | cell-index = <1>; |
| 148 | interrupts = <2 12 0>; | 150 | interrupts = <2 18 0>; |
| 149 | interrupt-parent = <&mpc5200_pic>; | 151 | interrupt-parent = <&mpc5200_pic>; |
| 150 | reg = <980 80>; | 152 | reg = <0x980 0x80>; |
| 151 | }; | 153 | }; |
| 152 | 154 | ||
| 153 | gpio@b00 { | 155 | gpio@b00 { |
| 154 | compatible = "fsl,mpc5200-gpio"; | 156 | compatible = "fsl,mpc5200-gpio"; |
| 155 | reg = <b00 40>; | 157 | reg = <0xb00 0x40>; |
| 156 | interrupts = <1 7 0>; | 158 | interrupts = <1 7 0>; |
| 157 | interrupt-parent = <&mpc5200_pic>; | 159 | interrupt-parent = <&mpc5200_pic>; |
| 158 | }; | 160 | }; |
| 159 | 161 | ||
| 160 | gpio@c00 { | 162 | gpio@c00 { |
| 161 | compatible = "fsl,mpc5200-gpio-wkup"; | 163 | compatible = "fsl,mpc5200-gpio-wkup"; |
| 162 | reg = <c00 40>; | 164 | reg = <0xc00 0x40>; |
| 163 | interrupts = <1 8 0 0 3 0>; | 165 | interrupts = <1 8 0 0 3 0>; |
| 164 | interrupt-parent = <&mpc5200_pic>; | 166 | interrupt-parent = <&mpc5200_pic>; |
| 165 | }; | 167 | }; |
| 166 | 168 | ||
| 167 | spi@f00 { | 169 | spi@f00 { |
| 168 | compatible = "fsl,mpc5200-spi"; | 170 | compatible = "fsl,mpc5200-spi"; |
| 169 | reg = <f00 20>; | 171 | reg = <0xf00 0x20>; |
| 170 | interrupts = <2 d 0 2 e 0>; | 172 | interrupts = <2 13 0 2 14 0>; |
| 171 | interrupt-parent = <&mpc5200_pic>; | 173 | interrupt-parent = <&mpc5200_pic>; |
| 172 | }; | 174 | }; |
| 173 | 175 | ||
| 174 | usb@1000 { | 176 | usb@1000 { |
| 175 | compatible = "fsl,mpc5200-ohci","ohci-be"; | 177 | compatible = "fsl,mpc5200-ohci","ohci-be"; |
| 176 | reg = <1000 ff>; | 178 | reg = <0x1000 0xff>; |
| 177 | interrupts = <2 6 0>; | 179 | interrupts = <2 6 0>; |
| 178 | interrupt-parent = <&mpc5200_pic>; | 180 | interrupt-parent = <&mpc5200_pic>; |
| 179 | }; | 181 | }; |
| @@ -181,17 +183,17 @@ | |||
| 181 | dma-controller@1200 { | 183 | dma-controller@1200 { |
| 182 | device_type = "dma-controller"; | 184 | device_type = "dma-controller"; |
| 183 | compatible = "fsl,mpc5200-bestcomm"; | 185 | compatible = "fsl,mpc5200-bestcomm"; |
| 184 | reg = <1200 80>; | 186 | reg = <0x1200 0x80>; |
| 185 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 | 187 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
| 186 | 3 4 0 3 5 0 3 6 0 3 7 0 | 188 | 3 4 0 3 5 0 3 6 0 3 7 0 |
| 187 | 3 8 0 3 9 0 3 a 0 3 b 0 | 189 | 3 8 0 3 9 0 3 10 0 3 11 0 |
| 188 | 3 c 0 3 d 0 3 e 0 3 f 0>; | 190 | 3 12 0 3 13 0 3 14 0 3 15 0>; |
| 189 | interrupt-parent = <&mpc5200_pic>; | 191 | interrupt-parent = <&mpc5200_pic>; |
| 190 | }; | 192 | }; |
| 191 | 193 | ||
| 192 | xlb@1f00 { | 194 | xlb@1f00 { |
| 193 | compatible = "fsl,mpc5200-xlb"; | 195 | compatible = "fsl,mpc5200-xlb"; |
| 194 | reg = <1f00 100>; | 196 | reg = <0x1f00 0x100>; |
| 195 | }; | 197 | }; |
| 196 | 198 | ||
| 197 | serial@2000 { // PSC1 | 199 | serial@2000 { // PSC1 |
| @@ -199,7 +201,7 @@ | |||
| 199 | compatible = "fsl,mpc5200-psc-uart"; | 201 | compatible = "fsl,mpc5200-psc-uart"; |
| 200 | port-number = <0>; // Logical port assignment | 202 | port-number = <0>; // Logical port assignment |
| 201 | cell-index = <0>; | 203 | cell-index = <0>; |
| 202 | reg = <2000 100>; | 204 | reg = <0x2000 0x100>; |
| 203 | interrupts = <2 1 0>; | 205 | interrupts = <2 1 0>; |
| 204 | interrupt-parent = <&mpc5200_pic>; | 206 | interrupt-parent = <&mpc5200_pic>; |
| 205 | }; | 207 | }; |
| @@ -208,7 +210,7 @@ | |||
| 208 | //ac97@2200 { // PSC2 | 210 | //ac97@2200 { // PSC2 |
| 209 | // compatible = "fsl,mpc5200-psc-ac97"; | 211 | // compatible = "fsl,mpc5200-psc-ac97"; |
| 210 | // cell-index = <1>; | 212 | // cell-index = <1>; |
| 211 | // reg = <2200 100>; | 213 | // reg = <0x2200 0x100>; |
| 212 | // interrupts = <2 2 0>; | 214 | // interrupts = <2 2 0>; |
| 213 | // interrupt-parent = <&mpc5200_pic>; | 215 | // interrupt-parent = <&mpc5200_pic>; |
| 214 | //}; | 216 | //}; |
| @@ -217,7 +219,7 @@ | |||
| 217 | //i2s@2400 { // PSC3 | 219 | //i2s@2400 { // PSC3 |
| 218 | // compatible = "fsl,mpc5200-psc-i2s"; | 220 | // compatible = "fsl,mpc5200-psc-i2s"; |
| 219 | // cell-index = <2>; | 221 | // cell-index = <2>; |
| 220 | // reg = <2400 100>; | 222 | // reg = <0x2400 0x100>; |
| 221 | // interrupts = <2 3 0>; | 223 | // interrupts = <2 3 0>; |
| 222 | // interrupt-parent = <&mpc5200_pic>; | 224 | // interrupt-parent = <&mpc5200_pic>; |
| 223 | //}; | 225 | //}; |
| @@ -227,8 +229,8 @@ | |||
| 227 | // device_type = "serial"; | 229 | // device_type = "serial"; |
| 228 | // compatible = "fsl,mpc5200-psc-uart"; | 230 | // compatible = "fsl,mpc5200-psc-uart"; |
| 229 | // cell-index = <3>; | 231 | // cell-index = <3>; |
| 230 | // reg = <2600 100>; | 232 | // reg = <0x2600 0x100>; |
| 231 | // interrupts = <2 b 0>; | 233 | // interrupts = <2 11 0>; |
| 232 | // interrupt-parent = <&mpc5200_pic>; | 234 | // interrupt-parent = <&mpc5200_pic>; |
| 233 | //}; | 235 | //}; |
| 234 | 236 | ||
| @@ -237,8 +239,8 @@ | |||
| 237 | // device_type = "serial"; | 239 | // device_type = "serial"; |
| 238 | // compatible = "fsl,mpc5200-psc-uart"; | 240 | // compatible = "fsl,mpc5200-psc-uart"; |
| 239 | // cell-index = <4>; | 241 | // cell-index = <4>; |
| 240 | // reg = <2800 100>; | 242 | // reg = <0x2800 0x100>; |
| 241 | // interrupts = <2 c 0>; | 243 | // interrupts = <2 12 0>; |
| 242 | // interrupt-parent = <&mpc5200_pic>; | 244 | // interrupt-parent = <&mpc5200_pic>; |
| 243 | //}; | 245 | //}; |
| 244 | 246 | ||
| @@ -246,7 +248,7 @@ | |||
| 246 | //spi@2c00 { // PSC6 | 248 | //spi@2c00 { // PSC6 |
| 247 | // compatible = "fsl,mpc5200-psc-spi"; | 249 | // compatible = "fsl,mpc5200-psc-spi"; |
| 248 | // cell-index = <5>; | 250 | // cell-index = <5>; |
| 249 | // reg = <2c00 100>; | 251 | // reg = <0x2c00 0x100>; |
| 250 | // interrupts = <2 4 0>; | 252 | // interrupts = <2 4 0>; |
| 251 | // interrupt-parent = <&mpc5200_pic>; | 253 | // interrupt-parent = <&mpc5200_pic>; |
| 252 | //}; | 254 | //}; |
| @@ -254,7 +256,7 @@ | |||
| 254 | ethernet@3000 { | 256 | ethernet@3000 { |
| 255 | device_type = "network"; | 257 | device_type = "network"; |
| 256 | compatible = "fsl,mpc5200-fec"; | 258 | compatible = "fsl,mpc5200-fec"; |
| 257 | reg = <3000 800>; | 259 | reg = <0x3000 0x400>; |
| 258 | local-mac-address = [ 00 00 00 00 00 00 ]; | 260 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 259 | interrupts = <2 5 0>; | 261 | interrupts = <2 5 0>; |
| 260 | interrupt-parent = <&mpc5200_pic>; | 262 | interrupt-parent = <&mpc5200_pic>; |
| @@ -265,11 +267,11 @@ | |||
| 265 | #address-cells = <1>; | 267 | #address-cells = <1>; |
| 266 | #size-cells = <0>; | 268 | #size-cells = <0>; |
| 267 | compatible = "fsl,mpc5200-mdio"; | 269 | compatible = "fsl,mpc5200-mdio"; |
| 268 | reg = <3000 400>; // fec range, since we need to setup fec interrupts | 270 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts |
| 269 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. | 271 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
| 270 | interrupt-parent = <&mpc5200_pic>; | 272 | interrupt-parent = <&mpc5200_pic>; |
| 271 | 273 | ||
| 272 | phy0:ethernet-phy@1 { | 274 | phy0: ethernet-phy@1 { |
| 273 | device_type = "ethernet-phy"; | 275 | device_type = "ethernet-phy"; |
| 274 | reg = <1>; | 276 | reg = <1>; |
| 275 | }; | 277 | }; |
| @@ -278,7 +280,7 @@ | |||
| 278 | ata@3a00 { | 280 | ata@3a00 { |
| 279 | device_type = "ata"; | 281 | device_type = "ata"; |
| 280 | compatible = "fsl,mpc5200-ata"; | 282 | compatible = "fsl,mpc5200-ata"; |
| 281 | reg = <3a00 100>; | 283 | reg = <0x3a00 0x100>; |
| 282 | interrupts = <2 7 0>; | 284 | interrupts = <2 7 0>; |
| 283 | interrupt-parent = <&mpc5200_pic>; | 285 | interrupt-parent = <&mpc5200_pic>; |
| 284 | }; | 286 | }; |
| @@ -288,8 +290,8 @@ | |||
| 288 | #size-cells = <0>; | 290 | #size-cells = <0>; |
| 289 | compatible = "fsl,mpc5200-i2c","fsl-i2c"; | 291 | compatible = "fsl,mpc5200-i2c","fsl-i2c"; |
| 290 | cell-index = <0>; | 292 | cell-index = <0>; |
| 291 | reg = <3d00 40>; | 293 | reg = <0x3d00 0x40>; |
| 292 | interrupts = <2 f 0>; | 294 | interrupts = <2 15 0>; |
| 293 | interrupt-parent = <&mpc5200_pic>; | 295 | interrupt-parent = <&mpc5200_pic>; |
| 294 | fsl5200-clocking; | 296 | fsl5200-clocking; |
| 295 | }; | 297 | }; |
| @@ -299,14 +301,14 @@ | |||
| 299 | #size-cells = <0>; | 301 | #size-cells = <0>; |
| 300 | compatible = "fsl,mpc5200-i2c","fsl-i2c"; | 302 | compatible = "fsl,mpc5200-i2c","fsl-i2c"; |
| 301 | cell-index = <1>; | 303 | cell-index = <1>; |
| 302 | reg = <3d40 40>; | 304 | reg = <0x3d40 0x40>; |
| 303 | interrupts = <2 10 0>; | 305 | interrupts = <2 16 0>; |
| 304 | interrupt-parent = <&mpc5200_pic>; | 306 | interrupt-parent = <&mpc5200_pic>; |
| 305 | fsl5200-clocking; | 307 | fsl5200-clocking; |
| 306 | }; | 308 | }; |
| 307 | sram@8000 { | 309 | sram@8000 { |
| 308 | compatible = "fsl,mpc5200-sram","sram"; | 310 | compatible = "fsl,mpc5200-sram","sram"; |
| 309 | reg = <8000 4000>; | 311 | reg = <0x8000 0x4000>; |
| 310 | }; | 312 | }; |
| 311 | }; | 313 | }; |
| 312 | 314 | ||
| @@ -316,18 +318,18 @@ | |||
| 316 | #address-cells = <3>; | 318 | #address-cells = <3>; |
| 317 | device_type = "pci"; | 319 | device_type = "pci"; |
| 318 | compatible = "fsl,mpc5200-pci"; | 320 | compatible = "fsl,mpc5200-pci"; |
| 319 | reg = <f0000d00 100>; | 321 | reg = <0xf0000d00 0x100>; |
| 320 | interrupt-map-mask = <f800 0 0 7>; | 322 | interrupt-map-mask = <0xf800 0 0 7>; |
| 321 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 | 323 | interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 |
| 322 | c000 0 0 2 &mpc5200_pic 0 0 3 | 324 | 0xc000 0 0 2 &mpc5200_pic 0 0 3 |
| 323 | c000 0 0 3 &mpc5200_pic 0 0 3 | 325 | 0xc000 0 0 3 &mpc5200_pic 0 0 3 |
| 324 | c000 0 0 4 &mpc5200_pic 0 0 3>; | 326 | 0xc000 0 0 4 &mpc5200_pic 0 0 3>; |
| 325 | clock-frequency = <0>; // From boot loader | 327 | clock-frequency = <0>; // From boot loader |
| 326 | interrupts = <2 8 0 2 9 0 2 a 0>; | 328 | interrupts = <2 8 0 2 9 0 2 10 0>; |
| 327 | interrupt-parent = <&mpc5200_pic>; | 329 | interrupt-parent = <&mpc5200_pic>; |
| 328 | bus-range = <0 0>; | 330 | bus-range = <0 0>; |
| 329 | ranges = <42000000 0 80000000 80000000 0 20000000 | 331 | ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 |
| 330 | 02000000 0 a0000000 a0000000 0 10000000 | 332 | 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 |
| 331 | 01000000 0 00000000 b0000000 0 01000000>; | 333 | 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; |
| 332 | }; | 334 | }; |
| 333 | }; | 335 | }; |
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts index 2e9bc397ae9a..7bd5b9c399b8 100644 --- a/arch/powerpc/boot/dts/lite5200b.dts +++ b/arch/powerpc/boot/dts/lite5200b.dts | |||
| @@ -10,11 +10,7 @@ | |||
| 10 | * option) any later version. | 10 | * option) any later version. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /* | 13 | /dts-v1/; |
| 14 | * WARNING: Do not depend on this tree layout remaining static just yet. | ||
| 15 | * The MPC5200 device tree conventions are still in flux | ||
| 16 | * Keep an eye on the linuxppc-dev mailing list for more details | ||
| 17 | */ | ||
| 18 | 14 | ||
| 19 | / { | 15 | / { |
| 20 | model = "fsl,lite5200b"; | 16 | model = "fsl,lite5200b"; |
| @@ -29,10 +25,10 @@ | |||
| 29 | PowerPC,5200@0 { | 25 | PowerPC,5200@0 { |
| 30 | device_type = "cpu"; | 26 | device_type = "cpu"; |
| 31 | reg = <0>; | 27 | reg = <0>; |
| 32 | d-cache-line-size = <20>; | 28 | d-cache-line-size = <32>; |
| 33 | i-cache-line-size = <20>; | 29 | i-cache-line-size = <32>; |
| 34 | d-cache-size = <4000>; // L1, 16K | 30 | d-cache-size = <0x4000>; // L1, 16K |
| 35 | i-cache-size = <4000>; // L1, 16K | 31 | i-cache-size = <0x4000>; // L1, 16K |
| 36 | timebase-frequency = <0>; // from bootloader | 32 | timebase-frequency = <0>; // from bootloader |
| 37 | bus-frequency = <0>; // from bootloader | 33 | bus-frequency = <0>; // from bootloader |
| 38 | clock-frequency = <0>; // from bootloader | 34 | clock-frequency = <0>; // from bootloader |
| @@ -41,21 +37,21 @@ | |||
| 41 | 37 | ||
| 42 | memory { | 38 | memory { |
| 43 | device_type = "memory"; | 39 | device_type = "memory"; |
| 44 | reg = <00000000 10000000>; // 256MB | 40 | reg = <0x00000000 0x10000000>; // 256MB |
| 45 | }; | 41 | }; |
| 46 | 42 | ||
| 47 | soc5200@f0000000 { | 43 | soc5200@f0000000 { |
| 48 | #address-cells = <1>; | 44 | #address-cells = <1>; |
| 49 | #size-cells = <1>; | 45 | #size-cells = <1>; |
| 50 | compatible = "fsl,mpc5200b-immr"; | 46 | compatible = "fsl,mpc5200b-immr"; |
| 51 | ranges = <0 f0000000 0000c000>; | 47 | ranges = <0 0xf0000000 0x0000c000>; |
| 52 | reg = <f0000000 00000100>; | 48 | reg = <0xf0000000 0x00000100>; |
| 53 | bus-frequency = <0>; // from bootloader | 49 | bus-frequency = <0>; // from bootloader |
| 54 | system-frequency = <0>; // from bootloader | 50 | system-frequency = <0>; // from bootloader |
| 55 | 51 | ||
| 56 | cdm@200 { | 52 | cdm@200 { |
| 57 | compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; | 53 | compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; |
| 58 | reg = <200 38>; | 54 | reg = <0x200 0x38>; |
| 59 | }; | 55 | }; |
| 60 | 56 | ||
| 61 | mpc5200_pic: interrupt-controller@500 { | 57 | mpc5200_pic: interrupt-controller@500 { |
| @@ -64,13 +60,13 @@ | |||
| 64 | #interrupt-cells = <3>; | 60 | #interrupt-cells = <3>; |
| 65 | device_type = "interrupt-controller"; | 61 | device_type = "interrupt-controller"; |
| 66 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; | 62 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; |
| 67 | reg = <500 80>; | 63 | reg = <0x500 0x80>; |
| 68 | }; | 64 | }; |
| 69 | 65 | ||
| 70 | timer@600 { // General Purpose Timer | 66 | timer@600 { // General Purpose Timer |
| 71 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 67 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 72 | cell-index = <0>; | 68 | cell-index = <0>; |
| 73 | reg = <600 10>; | 69 | reg = <0x600 0x10>; |
| 74 | interrupts = <1 9 0>; | 70 | interrupts = <1 9 0>; |
| 75 | interrupt-parent = <&mpc5200_pic>; | 71 | interrupt-parent = <&mpc5200_pic>; |
| 76 | fsl,has-wdt; | 72 | fsl,has-wdt; |
| @@ -79,63 +75,63 @@ | |||
| 79 | timer@610 { // General Purpose Timer | 75 | timer@610 { // General Purpose Timer |
| 80 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 76 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 81 | cell-index = <1>; | 77 | cell-index = <1>; |
| 82 | reg = <610 10>; | 78 | reg = <0x610 0x10>; |
| 83 | interrupts = <1 a 0>; | 79 | interrupts = <1 10 0>; |
| 84 | interrupt-parent = <&mpc5200_pic>; | 80 | interrupt-parent = <&mpc5200_pic>; |
| 85 | }; | 81 | }; |
| 86 | 82 | ||
| 87 | timer@620 { // General Purpose Timer | 83 | timer@620 { // General Purpose Timer |
| 88 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 84 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 89 | cell-index = <2>; | 85 | cell-index = <2>; |
| 90 | reg = <620 10>; | 86 | reg = <0x620 0x10>; |
| 91 | interrupts = <1 b 0>; | 87 | interrupts = <1 11 0>; |
| 92 | interrupt-parent = <&mpc5200_pic>; | 88 | interrupt-parent = <&mpc5200_pic>; |
| 93 | }; | 89 | }; |
| 94 | 90 | ||
| 95 | timer@630 { // General Purpose Timer | 91 | timer@630 { // General Purpose Timer |
| 96 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 92 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 97 | cell-index = <3>; | 93 | cell-index = <3>; |
| 98 | reg = <630 10>; | 94 | reg = <0x630 0x10>; |
| 99 | interrupts = <1 c 0>; | 95 | interrupts = <1 12 0>; |
| 100 | interrupt-parent = <&mpc5200_pic>; | 96 | interrupt-parent = <&mpc5200_pic>; |
| 101 | }; | 97 | }; |
| 102 | 98 | ||
| 103 | timer@640 { // General Purpose Timer | 99 | timer@640 { // General Purpose Timer |
| 104 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 100 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 105 | cell-index = <4>; | 101 | cell-index = <4>; |
| 106 | reg = <640 10>; | 102 | reg = <0x640 0x10>; |
| 107 | interrupts = <1 d 0>; | 103 | interrupts = <1 13 0>; |
| 108 | interrupt-parent = <&mpc5200_pic>; | 104 | interrupt-parent = <&mpc5200_pic>; |
| 109 | }; | 105 | }; |
| 110 | 106 | ||
| 111 | timer@650 { // General Purpose Timer | 107 | timer@650 { // General Purpose Timer |
| 112 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 108 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 113 | cell-index = <5>; | 109 | cell-index = <5>; |
| 114 | reg = <650 10>; | 110 | reg = <0x650 0x10>; |
| 115 | interrupts = <1 e 0>; | 111 | interrupts = <1 14 0>; |
| 116 | interrupt-parent = <&mpc5200_pic>; | 112 | interrupt-parent = <&mpc5200_pic>; |
| 117 | }; | 113 | }; |
| 118 | 114 | ||
| 119 | timer@660 { // General Purpose Timer | 115 | timer@660 { // General Purpose Timer |
| 120 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 116 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 121 | cell-index = <6>; | 117 | cell-index = <6>; |
| 122 | reg = <660 10>; | 118 | reg = <0x660 0x10>; |
| 123 | interrupts = <1 f 0>; | 119 | interrupts = <1 15 0>; |
| 124 | interrupt-parent = <&mpc5200_pic>; | 120 | interrupt-parent = <&mpc5200_pic>; |
| 125 | }; | 121 | }; |
| 126 | 122 | ||
| 127 | timer@670 { // General Purpose Timer | 123 | timer@670 { // General Purpose Timer |
| 128 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 124 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 129 | cell-index = <7>; | 125 | cell-index = <7>; |
| 130 | reg = <670 10>; | 126 | reg = <0x670 0x10>; |
| 131 | interrupts = <1 10 0>; | 127 | interrupts = <1 16 0>; |
| 132 | interrupt-parent = <&mpc5200_pic>; | 128 | interrupt-parent = <&mpc5200_pic>; |
| 133 | }; | 129 | }; |
| 134 | 130 | ||
| 135 | rtc@800 { // Real time clock | 131 | rtc@800 { // Real time clock |
| 136 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; | 132 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; |
| 137 | device_type = "rtc"; | 133 | device_type = "rtc"; |
| 138 | reg = <800 100>; | 134 | reg = <0x800 0x100>; |
| 139 | interrupts = <1 5 0 1 6 0>; | 135 | interrupts = <1 5 0 1 6 0>; |
| 140 | interrupt-parent = <&mpc5200_pic>; | 136 | interrupt-parent = <&mpc5200_pic>; |
| 141 | }; | 137 | }; |
| @@ -143,43 +139,43 @@ | |||
| 143 | can@900 { | 139 | can@900 { |
| 144 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; | 140 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
| 145 | cell-index = <0>; | 141 | cell-index = <0>; |
| 146 | interrupts = <2 11 0>; | 142 | interrupts = <2 17 0>; |
| 147 | interrupt-parent = <&mpc5200_pic>; | 143 | interrupt-parent = <&mpc5200_pic>; |
| 148 | reg = <900 80>; | 144 | reg = <0x900 0x80>; |
| 149 | }; | 145 | }; |
| 150 | 146 | ||
| 151 | can@980 { | 147 | can@980 { |
| 152 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; | 148 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
| 153 | cell-index = <1>; | 149 | cell-index = <1>; |
| 154 | interrupts = <2 12 0>; | 150 | interrupts = <2 18 0>; |
| 155 | interrupt-parent = <&mpc5200_pic>; | 151 | interrupt-parent = <&mpc5200_pic>; |
| 156 | reg = <980 80>; | 152 | reg = <0x980 0x80>; |
| 157 | }; | 153 | }; |
| 158 | 154 | ||
| 159 | gpio@b00 { | 155 | gpio@b00 { |
| 160 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; | 156 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; |
| 161 | reg = <b00 40>; | 157 | reg = <0xb00 0x40>; |
| 162 | interrupts = <1 7 0>; | 158 | interrupts = <1 7 0>; |
| 163 | interrupt-parent = <&mpc5200_pic>; | 159 | interrupt-parent = <&mpc5200_pic>; |
| 164 | }; | 160 | }; |
| 165 | 161 | ||
| 166 | gpio@c00 { | 162 | gpio@c00 { |
| 167 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; | 163 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; |
| 168 | reg = <c00 40>; | 164 | reg = <0xc00 0x40>; |
| 169 | interrupts = <1 8 0 0 3 0>; | 165 | interrupts = <1 8 0 0 3 0>; |
| 170 | interrupt-parent = <&mpc5200_pic>; | 166 | interrupt-parent = <&mpc5200_pic>; |
| 171 | }; | 167 | }; |
| 172 | 168 | ||
| 173 | spi@f00 { | 169 | spi@f00 { |
| 174 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | 170 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
| 175 | reg = <f00 20>; | 171 | reg = <0xf00 0x20>; |
| 176 | interrupts = <2 d 0 2 e 0>; | 172 | interrupts = <2 13 0 2 14 0>; |
| 177 | interrupt-parent = <&mpc5200_pic>; | 173 | interrupt-parent = <&mpc5200_pic>; |
| 178 | }; | 174 | }; |
| 179 | 175 | ||
| 180 | usb@1000 { | 176 | usb@1000 { |
| 181 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; | 177 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; |
| 182 | reg = <1000 ff>; | 178 | reg = <0x1000 0xff>; |
| 183 | interrupts = <2 6 0>; | 179 | interrupts = <2 6 0>; |
| 184 | interrupt-parent = <&mpc5200_pic>; | 180 | interrupt-parent = <&mpc5200_pic>; |
| 185 | }; | 181 | }; |
| @@ -187,17 +183,17 @@ | |||
| 187 | dma-controller@1200 { | 183 | dma-controller@1200 { |
| 188 | device_type = "dma-controller"; | 184 | device_type = "dma-controller"; |
| 189 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; | 185 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; |
| 190 | reg = <1200 80>; | 186 | reg = <0x1200 0x80>; |
| 191 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 | 187 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
| 192 | 3 4 0 3 5 0 3 6 0 3 7 0 | 188 | 3 4 0 3 5 0 3 6 0 3 7 0 |
| 193 | 3 8 0 3 9 0 3 a 0 3 b 0 | 189 | 3 8 0 3 9 0 3 10 0 3 11 0 |
| 194 | 3 c 0 3 d 0 3 e 0 3 f 0>; | 190 | 3 12 0 3 13 0 3 14 0 3 15 0>; |
| 195 | interrupt-parent = <&mpc5200_pic>; | 191 | interrupt-parent = <&mpc5200_pic>; |
| 196 | }; | 192 | }; |
| 197 | 193 | ||
| 198 | xlb@1f00 { | 194 | xlb@1f00 { |
| 199 | compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; | 195 | compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; |
| 200 | reg = <1f00 100>; | 196 | reg = <0x1f00 0x100>; |
| 201 | }; | 197 | }; |
| 202 | 198 | ||
| 203 | serial@2000 { // PSC1 | 199 | serial@2000 { // PSC1 |
| @@ -205,7 +201,7 @@ | |||
| 205 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 201 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| 206 | port-number = <0>; // Logical port assignment | 202 | port-number = <0>; // Logical port assignment |
| 207 | cell-index = <0>; | 203 | cell-index = <0>; |
| 208 | reg = <2000 100>; | 204 | reg = <0x2000 0x100>; |
| 209 | interrupts = <2 1 0>; | 205 | interrupts = <2 1 0>; |
| 210 | interrupt-parent = <&mpc5200_pic>; | 206 | interrupt-parent = <&mpc5200_pic>; |
| 211 | }; | 207 | }; |
| @@ -214,7 +210,7 @@ | |||
| 214 | //ac97@2200 { // PSC2 | 210 | //ac97@2200 { // PSC2 |
| 215 | // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; | 211 | // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; |
| 216 | // cell-index = <1>; | 212 | // cell-index = <1>; |
| 217 | // reg = <2200 100>; | 213 | // reg = <0x2200 0x100>; |
| 218 | // interrupts = <2 2 0>; | 214 | // interrupts = <2 2 0>; |
| 219 | // interrupt-parent = <&mpc5200_pic>; | 215 | // interrupt-parent = <&mpc5200_pic>; |
| 220 | //}; | 216 | //}; |
| @@ -223,7 +219,7 @@ | |||
| 223 | //i2s@2400 { // PSC3 | 219 | //i2s@2400 { // PSC3 |
| 224 | // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible | 220 | // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible |
| 225 | // cell-index = <2>; | 221 | // cell-index = <2>; |
| 226 | // reg = <2400 100>; | 222 | // reg = <0x2400 0x100>; |
| 227 | // interrupts = <2 3 0>; | 223 | // interrupts = <2 3 0>; |
| 228 | // interrupt-parent = <&mpc5200_pic>; | 224 | // interrupt-parent = <&mpc5200_pic>; |
| 229 | //}; | 225 | //}; |
| @@ -233,8 +229,8 @@ | |||
| 233 | // device_type = "serial"; | 229 | // device_type = "serial"; |
| 234 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 230 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| 235 | // cell-index = <3>; | 231 | // cell-index = <3>; |
| 236 | // reg = <2600 100>; | 232 | // reg = <0x2600 0x100>; |
| 237 | // interrupts = <2 b 0>; | 233 | // interrupts = <2 11 0>; |
| 238 | // interrupt-parent = <&mpc5200_pic>; | 234 | // interrupt-parent = <&mpc5200_pic>; |
| 239 | //}; | 235 | //}; |
| 240 | 236 | ||
| @@ -243,8 +239,8 @@ | |||
| 243 | // device_type = "serial"; | 239 | // device_type = "serial"; |
| 244 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 240 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| 245 | // cell-index = <4>; | 241 | // cell-index = <4>; |
| 246 | // reg = <2800 100>; | 242 | // reg = <0x2800 0x100>; |
| 247 | // interrupts = <2 c 0>; | 243 | // interrupts = <2 12 0>; |
| 248 | // interrupt-parent = <&mpc5200_pic>; | 244 | // interrupt-parent = <&mpc5200_pic>; |
| 249 | //}; | 245 | //}; |
| 250 | 246 | ||
| @@ -252,7 +248,7 @@ | |||
| 252 | //spi@2c00 { // PSC6 | 248 | //spi@2c00 { // PSC6 |
| 253 | // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; | 249 | // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; |
| 254 | // cell-index = <5>; | 250 | // cell-index = <5>; |
| 255 | // reg = <2c00 100>; | 251 | // reg = <0x2c00 0x100>; |
| 256 | // interrupts = <2 4 0>; | 252 | // interrupts = <2 4 0>; |
| 257 | // interrupt-parent = <&mpc5200_pic>; | 253 | // interrupt-parent = <&mpc5200_pic>; |
| 258 | //}; | 254 | //}; |
| @@ -260,7 +256,7 @@ | |||
| 260 | ethernet@3000 { | 256 | ethernet@3000 { |
| 261 | device_type = "network"; | 257 | device_type = "network"; |
| 262 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; | 258 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; |
| 263 | reg = <3000 400>; | 259 | reg = <0x3000 0x400>; |
| 264 | local-mac-address = [ 00 00 00 00 00 00 ]; | 260 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 265 | interrupts = <2 5 0>; | 261 | interrupts = <2 5 0>; |
| 266 | interrupt-parent = <&mpc5200_pic>; | 262 | interrupt-parent = <&mpc5200_pic>; |
| @@ -271,11 +267,11 @@ | |||
| 271 | #address-cells = <1>; | 267 | #address-cells = <1>; |
| 272 | #size-cells = <0>; | 268 | #size-cells = <0>; |
| 273 | compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; | 269 | compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; |
| 274 | reg = <3000 400>; // fec range, since we need to setup fec interrupts | 270 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts |
| 275 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. | 271 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
| 276 | interrupt-parent = <&mpc5200_pic>; | 272 | interrupt-parent = <&mpc5200_pic>; |
| 277 | 273 | ||
| 278 | phy0:ethernet-phy@0 { | 274 | phy0: ethernet-phy@0 { |
| 279 | device_type = "ethernet-phy"; | 275 | device_type = "ethernet-phy"; |
| 280 | reg = <0>; | 276 | reg = <0>; |
| 281 | }; | 277 | }; |
| @@ -284,7 +280,7 @@ | |||
| 284 | ata@3a00 { | 280 | ata@3a00 { |
| 285 | device_type = "ata"; | 281 | device_type = "ata"; |
| 286 | compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; | 282 | compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; |
| 287 | reg = <3a00 100>; | 283 | reg = <0x3a00 0x100>; |
| 288 | interrupts = <2 7 0>; | 284 | interrupts = <2 7 0>; |
| 289 | interrupt-parent = <&mpc5200_pic>; | 285 | interrupt-parent = <&mpc5200_pic>; |
| 290 | }; | 286 | }; |
| @@ -294,8 +290,8 @@ | |||
| 294 | #size-cells = <0>; | 290 | #size-cells = <0>; |
| 295 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | 291 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
| 296 | cell-index = <0>; | 292 | cell-index = <0>; |
| 297 | reg = <3d00 40>; | 293 | reg = <0x3d00 0x40>; |
| 298 | interrupts = <2 f 0>; | 294 | interrupts = <2 15 0>; |
| 299 | interrupt-parent = <&mpc5200_pic>; | 295 | interrupt-parent = <&mpc5200_pic>; |
| 300 | fsl5200-clocking; | 296 | fsl5200-clocking; |
| 301 | }; | 297 | }; |
| @@ -305,14 +301,14 @@ | |||
| 305 | #size-cells = <0>; | 301 | #size-cells = <0>; |
| 306 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | 302 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
| 307 | cell-index = <1>; | 303 | cell-index = <1>; |
| 308 | reg = <3d40 40>; | 304 | reg = <0x3d40 0x40>; |
| 309 | interrupts = <2 10 0>; | 305 | interrupts = <2 16 0>; |
| 310 | interrupt-parent = <&mpc5200_pic>; | 306 | interrupt-parent = <&mpc5200_pic>; |
| 311 | fsl5200-clocking; | 307 | fsl5200-clocking; |
| 312 | }; | 308 | }; |
| 313 | sram@8000 { | 309 | sram@8000 { |
| 314 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; | 310 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; |
| 315 | reg = <8000 4000>; | 311 | reg = <0x8000 0x4000>; |
| 316 | }; | 312 | }; |
| 317 | }; | 313 | }; |
| 318 | 314 | ||
| @@ -322,23 +318,23 @@ | |||
| 322 | #address-cells = <3>; | 318 | #address-cells = <3>; |
| 323 | device_type = "pci"; | 319 | device_type = "pci"; |
| 324 | compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; | 320 | compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; |
| 325 | reg = <f0000d00 100>; | 321 | reg = <0xf0000d00 0x100>; |
| 326 | interrupt-map-mask = <f800 0 0 7>; | 322 | interrupt-map-mask = <0xf800 0 0 7>; |
| 327 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot | 323 | interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot |
| 328 | c000 0 0 2 &mpc5200_pic 1 1 3 | 324 | 0xc000 0 0 2 &mpc5200_pic 1 1 3 |
| 329 | c000 0 0 3 &mpc5200_pic 1 2 3 | 325 | 0xc000 0 0 3 &mpc5200_pic 1 2 3 |
| 330 | c000 0 0 4 &mpc5200_pic 1 3 3 | 326 | 0xc000 0 0 4 &mpc5200_pic 1 3 3 |
| 331 | 327 | ||
| 332 | c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot | 328 | 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot |
| 333 | c800 0 0 2 &mpc5200_pic 1 2 3 | 329 | 0xc800 0 0 2 &mpc5200_pic 1 2 3 |
| 334 | c800 0 0 3 &mpc5200_pic 1 3 3 | 330 | 0xc800 0 0 3 &mpc5200_pic 1 3 3 |
| 335 | c800 0 0 4 &mpc5200_pic 0 0 3>; | 331 | 0xc800 0 0 4 &mpc5200_pic 0 0 3>; |
| 336 | clock-frequency = <0>; // From boot loader | 332 | clock-frequency = <0>; // From boot loader |
| 337 | interrupts = <2 8 0 2 9 0 2 a 0>; | 333 | interrupts = <2 8 0 2 9 0 2 10 0>; |
| 338 | interrupt-parent = <&mpc5200_pic>; | 334 | interrupt-parent = <&mpc5200_pic>; |
| 339 | bus-range = <0 0>; | 335 | bus-range = <0 0>; |
| 340 | ranges = <42000000 0 80000000 80000000 0 20000000 | 336 | ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 |
| 341 | 02000000 0 a0000000 a0000000 0 10000000 | 337 | 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 |
| 342 | 01000000 0 00000000 b0000000 0 01000000>; | 338 | 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; |
| 343 | }; | 339 | }; |
| 344 | }; | 340 | }; |
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts index 2b0dde058f8e..9e3c921be164 100644 --- a/arch/powerpc/boot/dts/motionpro.dts +++ b/arch/powerpc/boot/dts/motionpro.dts | |||
| @@ -10,6 +10,8 @@ | |||
| 10 | * option) any later version. | 10 | * option) any later version. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | ||
| 14 | |||
| 13 | / { | 15 | / { |
| 14 | model = "promess,motionpro"; | 16 | model = "promess,motionpro"; |
| 15 | compatible = "promess,motionpro"; | 17 | compatible = "promess,motionpro"; |
| @@ -23,10 +25,10 @@ | |||
| 23 | PowerPC,5200@0 { | 25 | PowerPC,5200@0 { |
| 24 | device_type = "cpu"; | 26 | device_type = "cpu"; |
| 25 | reg = <0>; | 27 | reg = <0>; |
| 26 | d-cache-line-size = <20>; | 28 | d-cache-line-size = <32>; |
| 27 | i-cache-line-size = <20>; | 29 | i-cache-line-size = <32>; |
| 28 | d-cache-size = <4000>; // L1, 16K | 30 | d-cache-size = <0x4000>; // L1, 16K |
| 29 | i-cache-size = <4000>; // L1, 16K | 31 | i-cache-size = <0x4000>; // L1, 16K |
| 30 | timebase-frequency = <0>; // from bootloader | 32 | timebase-frequency = <0>; // from bootloader |
| 31 | bus-frequency = <0>; // from bootloader | 33 | bus-frequency = <0>; // from bootloader |
| 32 | clock-frequency = <0>; // from bootloader | 34 | clock-frequency = <0>; // from bootloader |
| @@ -35,21 +37,21 @@ | |||
| 35 | 37 | ||
| 36 | memory { | 38 | memory { |
| 37 | device_type = "memory"; | 39 | device_type = "memory"; |
| 38 | reg = <00000000 04000000>; // 64MB | 40 | reg = <0x00000000 0x04000000>; // 64MB |
| 39 | }; | 41 | }; |
| 40 | 42 | ||
| 41 | soc5200@f0000000 { | 43 | soc5200@f0000000 { |
| 42 | #address-cells = <1>; | 44 | #address-cells = <1>; |
| 43 | #size-cells = <1>; | 45 | #size-cells = <1>; |
| 44 | compatible = "fsl,mpc5200b-immr"; | 46 | compatible = "fsl,mpc5200b-immr"; |
| 45 | ranges = <0 f0000000 0000c000>; | 47 | ranges = <0 0xf0000000 0x0000c000>; |
| 46 | reg = <f0000000 00000100>; | 48 | reg = <0xf0000000 0x00000100>; |
| 47 | bus-frequency = <0>; // from bootloader | 49 | bus-frequency = <0>; // from bootloader |
| 48 | system-frequency = <0>; // from bootloader | 50 | system-frequency = <0>; // from bootloader |
| 49 | 51 | ||
| 50 | cdm@200 { | 52 | cdm@200 { |
| 51 | compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; | 53 | compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; |
| 52 | reg = <200 38>; | 54 | reg = <0x200 0x38>; |
| 53 | }; | 55 | }; |
| 54 | 56 | ||
| 55 | mpc5200_pic: interrupt-controller@500 { | 57 | mpc5200_pic: interrupt-controller@500 { |
| @@ -57,12 +59,12 @@ | |||
| 57 | interrupt-controller; | 59 | interrupt-controller; |
| 58 | #interrupt-cells = <3>; | 60 | #interrupt-cells = <3>; |
| 59 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; | 61 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; |
| 60 | reg = <500 80>; | 62 | reg = <0x500 0x80>; |
| 61 | }; | 63 | }; |
| 62 | 64 | ||
| 63 | timer@600 { // General Purpose Timer | 65 | timer@600 { // General Purpose Timer |
| 64 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 66 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 65 | reg = <600 10>; | 67 | reg = <0x600 0x10>; |
| 66 | interrupts = <1 9 0>; | 68 | interrupts = <1 9 0>; |
| 67 | interrupt-parent = <&mpc5200_pic>; | 69 | interrupt-parent = <&mpc5200_pic>; |
| 68 | fsl,has-wdt; | 70 | fsl,has-wdt; |
| @@ -70,118 +72,118 @@ | |||
| 70 | 72 | ||
| 71 | timer@610 { // General Purpose Timer | 73 | timer@610 { // General Purpose Timer |
| 72 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 74 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 73 | reg = <610 10>; | 75 | reg = <0x610 0x10>; |
| 74 | interrupts = <1 a 0>; | 76 | interrupts = <1 10 0>; |
| 75 | interrupt-parent = <&mpc5200_pic>; | 77 | interrupt-parent = <&mpc5200_pic>; |
| 76 | }; | 78 | }; |
| 77 | 79 | ||
| 78 | timer@620 { // General Purpose Timer | 80 | timer@620 { // General Purpose Timer |
| 79 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 81 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 80 | reg = <620 10>; | 82 | reg = <0x620 0x10>; |
| 81 | interrupts = <1 b 0>; | 83 | interrupts = <1 11 0>; |
| 82 | interrupt-parent = <&mpc5200_pic>; | 84 | interrupt-parent = <&mpc5200_pic>; |
| 83 | }; | 85 | }; |
| 84 | 86 | ||
| 85 | timer@630 { // General Purpose Timer | 87 | timer@630 { // General Purpose Timer |
| 86 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 88 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 87 | reg = <630 10>; | 89 | reg = <0x630 0x10>; |
| 88 | interrupts = <1 c 0>; | 90 | interrupts = <1 12 0>; |
| 89 | interrupt-parent = <&mpc5200_pic>; | 91 | interrupt-parent = <&mpc5200_pic>; |
| 90 | }; | 92 | }; |
| 91 | 93 | ||
| 92 | timer@640 { // General Purpose Timer | 94 | timer@640 { // General Purpose Timer |
| 93 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 95 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 94 | reg = <640 10>; | 96 | reg = <0x640 0x10>; |
| 95 | interrupts = <1 d 0>; | 97 | interrupts = <1 13 0>; |
| 96 | interrupt-parent = <&mpc5200_pic>; | 98 | interrupt-parent = <&mpc5200_pic>; |
| 97 | }; | 99 | }; |
| 98 | 100 | ||
| 99 | timer@650 { // General Purpose Timer | 101 | timer@650 { // General Purpose Timer |
| 100 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 102 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| 101 | reg = <650 10>; | 103 | reg = <0x650 0x10>; |
| 102 | interrupts = <1 e 0>; | 104 | interrupts = <1 14 0>; |
| 103 | interrupt-parent = <&mpc5200_pic>; | 105 | interrupt-parent = <&mpc5200_pic>; |
| 104 | }; | 106 | }; |
| 105 | 107 | ||
| 106 | motionpro-led@660 { // Motion-PRO status LED | 108 | motionpro-led@660 { // Motion-PRO status LED |
| 107 | compatible = "promess,motionpro-led"; | 109 | compatible = "promess,motionpro-led"; |
| 108 | label = "motionpro-statusled"; | 110 | label = "motionpro-statusled"; |
| 109 | reg = <660 10>; | 111 | reg = <0x660 0x10>; |
| 110 | interrupts = <1 f 0>; | 112 | interrupts = <1 15 0>; |
| 111 | interrupt-parent = <&mpc5200_pic>; | 113 | interrupt-parent = <&mpc5200_pic>; |
| 112 | blink-delay = <64>; // 100 msec | 114 | blink-delay = <100>; // 100 msec |
| 113 | }; | 115 | }; |
| 114 | 116 | ||
| 115 | motionpro-led@670 { // Motion-PRO ready LED | 117 | motionpro-led@670 { // Motion-PRO ready LED |
| 116 | compatible = "promess,motionpro-led"; | 118 | compatible = "promess,motionpro-led"; |
| 117 | label = "motionpro-readyled"; | 119 | label = "motionpro-readyled"; |
| 118 | reg = <670 10>; | 120 | reg = <0x670 0x10>; |
| 119 | interrupts = <1 10 0>; | 121 | interrupts = <1 16 0>; |
| 120 | interrupt-parent = <&mpc5200_pic>; | 122 | interrupt-parent = <&mpc5200_pic>; |
| 121 | }; | 123 | }; |
| 122 | 124 | ||
| 123 | rtc@800 { // Real time clock | 125 | rtc@800 { // Real time clock |
| 124 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; | 126 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; |
| 125 | reg = <800 100>; | 127 | reg = <0x800 0x100>; |
| 126 | interrupts = <1 5 0 1 6 0>; | 128 | interrupts = <1 5 0 1 6 0>; |
| 127 | interrupt-parent = <&mpc5200_pic>; | 129 | interrupt-parent = <&mpc5200_pic>; |
| 128 | }; | 130 | }; |
| 129 | 131 | ||
| 130 | mscan@980 { | 132 | can@980 { |
| 131 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; | 133 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
| 132 | interrupts = <2 12 0>; | 134 | interrupts = <2 18 0>; |
| 133 | interrupt-parent = <&mpc5200_pic>; | 135 | interrupt-parent = <&mpc5200_pic>; |
| 134 | reg = <980 80>; | 136 | reg = <0x980 0x80>; |
| 135 | }; | 137 | }; |
| 136 | 138 | ||
| 137 | gpio@b00 { | 139 | gpio@b00 { |
| 138 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; | 140 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; |
| 139 | reg = <b00 40>; | 141 | reg = <0xb00 0x40>; |
| 140 | interrupts = <1 7 0>; | 142 | interrupts = <1 7 0>; |
| 141 | interrupt-parent = <&mpc5200_pic>; | 143 | interrupt-parent = <&mpc5200_pic>; |
| 142 | }; | 144 | }; |
| 143 | 145 | ||
| 144 | gpio@c00 { | 146 | gpio@c00 { |
| 145 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; | 147 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; |
| 146 | reg = <c00 40>; | 148 | reg = <0xc00 0x40>; |
| 147 | interrupts = <1 8 0 0 3 0>; | 149 | interrupts = <1 8 0 0 3 0>; |
| 148 | interrupt-parent = <&mpc5200_pic>; | 150 | interrupt-parent = <&mpc5200_pic>; |
| 149 | }; | 151 | }; |
| 150 | 152 | ||
| 151 | spi@f00 { | 153 | spi@f00 { |
| 152 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | 154 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
| 153 | reg = <f00 20>; | 155 | reg = <0xf00 0x20>; |
| 154 | interrupts = <2 d 0 2 e 0>; | 156 | interrupts = <2 13 0 2 14 0>; |
| 155 | interrupt-parent = <&mpc5200_pic>; | 157 | interrupt-parent = <&mpc5200_pic>; |
| 156 | }; | 158 | }; |
| 157 | 159 | ||
| 158 | usb@1000 { | 160 | usb@1000 { |
| 159 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; | 161 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; |
| 160 | reg = <1000 ff>; | 162 | reg = <0x1000 0xff>; |
| 161 | interrupts = <2 6 0>; | 163 | interrupts = <2 6 0>; |
| 162 | interrupt-parent = <&mpc5200_pic>; | 164 | interrupt-parent = <&mpc5200_pic>; |
| 163 | }; | 165 | }; |
| 164 | 166 | ||
| 165 | dma-controller@1200 { | 167 | dma-controller@1200 { |
| 166 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; | 168 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; |
| 167 | reg = <1200 80>; | 169 | reg = <0x1200 0x80>; |
| 168 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 | 170 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
| 169 | 3 4 0 3 5 0 3 6 0 3 7 0 | 171 | 3 4 0 3 5 0 3 6 0 3 7 0 |
| 170 | 3 8 0 3 9 0 3 a 0 3 b 0 | 172 | 3 8 0 3 9 0 3 10 0 3 11 0 |
| 171 | 3 c 0 3 d 0 3 e 0 3 f 0>; | 173 | 3 12 0 3 13 0 3 14 0 3 15 0>; |
| 172 | interrupt-parent = <&mpc5200_pic>; | 174 | interrupt-parent = <&mpc5200_pic>; |
| 173 | }; | 175 | }; |
| 174 | 176 | ||
| 175 | xlb@1f00 { | 177 | xlb@1f00 { |
| 176 | compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; | 178 | compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; |
| 177 | reg = <1f00 100>; | 179 | reg = <0x1f00 0x100>; |
| 178 | }; | 180 | }; |
| 179 | 181 | ||
| 180 | serial@2000 { // PSC1 | 182 | serial@2000 { // PSC1 |
| 181 | device_type = "serial"; | 183 | device_type = "serial"; |
| 182 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 184 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| 183 | port-number = <0>; // Logical port assignment | 185 | port-number = <0>; // Logical port assignment |
| 184 | reg = <2000 100>; | 186 | reg = <0x2000 0x100>; |
| 185 | interrupts = <2 1 0>; | 187 | interrupts = <2 1 0>; |
| 186 | interrupt-parent = <&mpc5200_pic>; | 188 | interrupt-parent = <&mpc5200_pic>; |
| 187 | }; | 189 | }; |
| @@ -190,7 +192,7 @@ | |||
| 190 | spi@2200 { // PSC2 | 192 | spi@2200 { // PSC2 |
| 191 | compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; | 193 | compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; |
| 192 | cell-index = <1>; | 194 | cell-index = <1>; |
| 193 | reg = <2200 100>; | 195 | reg = <0x2200 0x100>; |
| 194 | interrupts = <2 2 0>; | 196 | interrupts = <2 2 0>; |
| 195 | interrupt-parent = <&mpc5200_pic>; | 197 | interrupt-parent = <&mpc5200_pic>; |
| 196 | }; | 198 | }; |
| @@ -200,15 +202,15 @@ | |||
| 200 | device_type = "serial"; | 202 | device_type = "serial"; |
| 201 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 203 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| 202 | port-number = <4>; // Logical port assignment | 204 | port-number = <4>; // Logical port assignment |
| 203 | reg = <2800 100>; | 205 | reg = <0x2800 0x100>; |
| 204 | interrupts = <2 c 0>; | 206 | interrupts = <2 12 0>; |
| 205 | interrupt-parent = <&mpc5200_pic>; | 207 | interrupt-parent = <&mpc5200_pic>; |
| 206 | }; | 208 | }; |
| 207 | 209 | ||
| 208 | ethernet@3000 { | 210 | ethernet@3000 { |
| 209 | device_type = "network"; | 211 | device_type = "network"; |
| 210 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; | 212 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; |
| 211 | reg = <3000 400>; | 213 | reg = <0x3000 0x400>; |
| 212 | local-mac-address = [ 00 00 00 00 00 00 ]; | 214 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 213 | interrupts = <2 5 0>; | 215 | interrupts = <2 5 0>; |
| 214 | interrupt-parent = <&mpc5200_pic>; | 216 | interrupt-parent = <&mpc5200_pic>; |
| @@ -219,7 +221,7 @@ | |||
| 219 | #address-cells = <1>; | 221 | #address-cells = <1>; |
| 220 | #size-cells = <0>; | 222 | #size-cells = <0>; |
| 221 | compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; | 223 | compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; |
| 222 | reg = <3000 400>; // fec range, since we need to setup fec interrupts | 224 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts |
| 223 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. | 225 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
| 224 | interrupt-parent = <&mpc5200_pic>; | 226 | interrupt-parent = <&mpc5200_pic>; |
| 225 | 227 | ||
| @@ -231,7 +233,7 @@ | |||
| 231 | 233 | ||
| 232 | ata@3a00 { | 234 | ata@3a00 { |
| 233 | compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; | 235 | compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; |
| 234 | reg = <3a00 100>; | 236 | reg = <0x3a00 0x100>; |
| 235 | interrupts = <2 7 0>; | 237 | interrupts = <2 7 0>; |
| 236 | interrupt-parent = <&mpc5200_pic>; | 238 | interrupt-parent = <&mpc5200_pic>; |
| 237 | }; | 239 | }; |
| @@ -240,21 +242,21 @@ | |||
| 240 | #address-cells = <1>; | 242 | #address-cells = <1>; |
| 241 | #size-cells = <0>; | 243 | #size-cells = <0>; |
| 242 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | 244 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
| 243 | reg = <3d40 40>; | 245 | reg = <0x3d40 0x40>; |
| 244 | interrupts = <2 10 0>; | 246 | interrupts = <2 16 0>; |
| 245 | interrupt-parent = <&mpc5200_pic>; | 247 | interrupt-parent = <&mpc5200_pic>; |
| 246 | fsl5200-clocking; | 248 | fsl5200-clocking; |
| 247 | 249 | ||
| 248 | rtc@68 { | 250 | rtc@68 { |
| 249 | device_type = "rtc"; | 251 | device_type = "rtc"; |
| 250 | compatible = "dallas,ds1339"; | 252 | compatible = "dallas,ds1339"; |
| 251 | reg = <68>; | 253 | reg = <0x68>; |
| 252 | }; | 254 | }; |
| 253 | }; | 255 | }; |
| 254 | 256 | ||
| 255 | sram@8000 { | 257 | sram@8000 { |
| 256 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; | 258 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; |
| 257 | reg = <8000 4000>; | 259 | reg = <0x8000 0x4000>; |
| 258 | }; | 260 | }; |
| 259 | }; | 261 | }; |
| 260 | 262 | ||
| @@ -262,15 +264,15 @@ | |||
| 262 | compatible = "fsl,lpb"; | 264 | compatible = "fsl,lpb"; |
| 263 | #address-cells = <2>; | 265 | #address-cells = <2>; |
| 264 | #size-cells = <1>; | 266 | #size-cells = <1>; |
| 265 | ranges = <0 0 ff000000 01000000 | 267 | ranges = <0 0 0xff000000 0x01000000 |
| 266 | 1 0 50000000 00010000 | 268 | 1 0 0x50000000 0x00010000 |
| 267 | 2 0 50010000 00010000 | 269 | 2 0 0x50010000 0x00010000 |
| 268 | 3 0 50020000 00010000>; | 270 | 3 0 0x50020000 0x00010000>; |
| 269 | 271 | ||
| 270 | // 8-bit DualPort SRAM on LocalPlus Bus CS1 | 272 | // 8-bit DualPort SRAM on LocalPlus Bus CS1 |
| 271 | kollmorgen@1,0 { | 273 | kollmorgen@1,0 { |
| 272 | compatible = "promess,motionpro-kollmorgen"; | 274 | compatible = "promess,motionpro-kollmorgen"; |
| 273 | reg = <1 0 10000>; | 275 | reg = <1 0 0x10000>; |
| 274 | interrupts = <1 1 0>; | 276 | interrupts = <1 1 0>; |
| 275 | interrupt-parent = <&mpc5200_pic>; | 277 | interrupt-parent = <&mpc5200_pic>; |
| 276 | }; | 278 | }; |
| @@ -278,13 +280,13 @@ | |||
| 278 | // 8-bit board CPLD on LocalPlus Bus CS2 | 280 | // 8-bit board CPLD on LocalPlus Bus CS2 |
| 279 | cpld@2,0 { | 281 | cpld@2,0 { |
| 280 | compatible = "promess,motionpro-cpld"; | 282 | compatible = "promess,motionpro-cpld"; |
| 281 | reg = <2 0 10000>; | 283 | reg = <2 0 0x10000>; |
| 282 | }; | 284 | }; |
| 283 | 285 | ||
| 284 | // 8-bit custom Anybus Module on LocalPlus Bus CS3 | 286 | // 8-bit custom Anybus Module on LocalPlus Bus CS3 |
| 285 | anybus@3,0 { | 287 | anybus@3,0 { |
| 286 | compatible = "promess,motionpro-anybus"; | 288 | compatible = "promess,motionpro-anybus"; |
| 287 | reg = <3 0 10000>; | 289 | reg = <3 0 0x10000>; |
| 288 | }; | 290 | }; |
| 289 | pro_module_general@3,0 { | 291 | pro_module_general@3,0 { |
| 290 | compatible = "promess,pro_module_general"; | 292 | compatible = "promess,pro_module_general"; |
| @@ -292,13 +294,13 @@ | |||
| 292 | }; | 294 | }; |
| 293 | pro_module_dio@3,800 { | 295 | pro_module_dio@3,800 { |
| 294 | compatible = "promess,pro_module_dio"; | 296 | compatible = "promess,pro_module_dio"; |
| 295 | reg = <3 800 2>; | 297 | reg = <3 0x800 2>; |
| 296 | }; | 298 | }; |
| 297 | 299 | ||
| 298 | // 16-bit flash device at LocalPlus Bus CS0 | 300 | // 16-bit flash device at LocalPlus Bus CS0 |
| 299 | flash@0,0 { | 301 | flash@0,0 { |
| 300 | compatible = "cfi-flash"; | 302 | compatible = "cfi-flash"; |
| 301 | reg = <0 0 01000000>; | 303 | reg = <0 0 0x01000000>; |
| 302 | bank-width = <2>; | 304 | bank-width = <2>; |
| 303 | device-width = <2>; | 305 | device-width = <2>; |
| 304 | #size-cells = <1>; | 306 | #size-cells = <1>; |
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts index 65bcea6a0173..773a68e00058 100644 --- a/arch/powerpc/boot/dts/tqm5200.dts +++ b/arch/powerpc/boot/dts/tqm5200.dts | |||
| @@ -10,6 +10,8 @@ | |||
| 10 | * option) any later version. | 10 | * option) any later version. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /dts-v1/; | ||
| 14 | |||
| 13 | / { | 15 | / { |
| 14 | model = "tqc,tqm5200"; | 16 | model = "tqc,tqm5200"; |
| 15 | compatible = "tqc,tqm5200"; | 17 | compatible = "tqc,tqm5200"; |
| @@ -23,10 +25,10 @@ | |||
| 23 | PowerPC,5200@0 { | 25 | PowerPC,5200@0 { |
| 24 | device_type = "cpu"; | 26 | device_type = "cpu"; |
| 25 | reg = <0>; | 27 | reg = <0>; |
| 26 | d-cache-line-size = <20>; | 28 | d-cache-line-size = <32>; |
| 27 | i-cache-line-size = <20>; | 29 | i-cache-line-size = <32>; |
| 28 | d-cache-size = <4000>; // L1, 16K | 30 | d-cache-size = <0x4000>; // L1, 16K |
| 29 | i-cache-size = <4000>; // L1, 16K | 31 | i-cache-size = <0x4000>; // L1, 16K |
| 30 | timebase-frequency = <0>; // from bootloader | 32 | timebase-frequency = <0>; // from bootloader |
| 31 | bus-frequency = <0>; // from bootloader | 33 | bus-frequency = <0>; // from bootloader |
| 32 | clock-frequency = <0>; // from bootloader | 34 | clock-frequency = <0>; // from bootloader |
| @@ -35,21 +37,21 @@ | |||
| 35 | 37 | ||
| 36 | memory { | 38 | memory { |
| 37 | device_type = "memory"; | 39 | device_type = "memory"; |
| 38 | reg = <00000000 04000000>; // 64MB | 40 | reg = <0x00000000 0x04000000>; // 64MB |
| 39 | }; | 41 | }; |
| 40 | 42 | ||
| 41 | soc5200@f0000000 { | 43 | soc5200@f0000000 { |
| 42 | #address-cells = <1>; | 44 | #address-cells = <1>; |
| 43 | #size-cells = <1>; | 45 | #size-cells = <1>; |
| 44 | compatible = "fsl,mpc5200-immr"; | 46 | compatible = "fsl,mpc5200-immr"; |
| 45 | ranges = <0 f0000000 0000c000>; | 47 | ranges = <0 0xf0000000 0x0000c000>; |
| 46 | reg = <f0000000 00000100>; | 48 | reg = <0xf0000000 0x00000100>; |
| 47 | bus-frequency = <0>; // from bootloader | 49 | bus-frequency = <0>; // from bootloader |
| 48 | system-frequency = <0>; // from bootloader | 50 | system-frequency = <0>; // from bootloader |
| 49 | 51 | ||
| 50 | cdm@200 { | 52 | cdm@200 { |
| 51 | compatible = "fsl,mpc5200-cdm"; | 53 | compatible = "fsl,mpc5200-cdm"; |
| 52 | reg = <200 38>; | 54 | reg = <0x200 0x38>; |
| 53 | }; | 55 | }; |
| 54 | 56 | ||
| 55 | mpc5200_pic: interrupt-controller@500 { | 57 | mpc5200_pic: interrupt-controller@500 { |
| @@ -57,12 +59,12 @@ | |||
| 57 | interrupt-controller; | 59 | interrupt-controller; |
| 58 | #interrupt-cells = <3>; | 60 | #interrupt-cells = <3>; |
| 59 | compatible = "fsl,mpc5200-pic"; | 61 | compatible = "fsl,mpc5200-pic"; |
| 60 | reg = <500 80>; | 62 | reg = <0x500 0x80>; |
| 61 | }; | 63 | }; |
| 62 | 64 | ||
| 63 | timer@600 { // General Purpose Timer | 65 | timer@600 { // General Purpose Timer |
| 64 | compatible = "fsl,mpc5200-gpt"; | 66 | compatible = "fsl,mpc5200-gpt"; |
| 65 | reg = <600 10>; | 67 | reg = <0x600 0x10>; |
| 66 | interrupts = <1 9 0>; | 68 | interrupts = <1 9 0>; |
| 67 | interrupt-parent = <&mpc5200_pic>; | 69 | interrupt-parent = <&mpc5200_pic>; |
| 68 | fsl,has-wdt; | 70 | fsl,has-wdt; |
| @@ -70,38 +72,38 @@ | |||
| 70 | 72 | ||
| 71 | gpio@b00 { | 73 | gpio@b00 { |
| 72 | compatible = "fsl,mpc5200-gpio"; | 74 | compatible = "fsl,mpc5200-gpio"; |
| 73 | reg = <b00 40>; | 75 | reg = <0xb00 0x40>; |
| 74 | interrupts = <1 7 0>; | 76 | interrupts = <1 7 0>; |
| 75 | interrupt-parent = <&mpc5200_pic>; | 77 | interrupt-parent = <&mpc5200_pic>; |
| 76 | }; | 78 | }; |
| 77 | 79 | ||
| 78 | usb@1000 { | 80 | usb@1000 { |
| 79 | compatible = "fsl,mpc5200-ohci","ohci-be"; | 81 | compatible = "fsl,mpc5200-ohci","ohci-be"; |
| 80 | reg = <1000 ff>; | 82 | reg = <0x1000 0xff>; |
| 81 | interrupts = <2 6 0>; | 83 | interrupts = <2 6 0>; |
| 82 | interrupt-parent = <&mpc5200_pic>; | 84 | interrupt-parent = <&mpc5200_pic>; |
| 83 | }; | 85 | }; |
| 84 | 86 | ||
| 85 | dma-controller@1200 { | 87 | dma-controller@1200 { |
| 86 | compatible = "fsl,mpc5200-bestcomm"; | 88 | compatible = "fsl,mpc5200-bestcomm"; |
| 87 | reg = <1200 80>; | 89 | reg = <0x1200 0x80>; |
| 88 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 | 90 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
| 89 | 3 4 0 3 5 0 3 6 0 3 7 0 | 91 | 3 4 0 3 5 0 3 6 0 3 7 0 |
| 90 | 3 8 0 3 9 0 3 a 0 3 b 0 | 92 | 3 8 0 3 9 0 3 10 0 3 11 0 |
| 91 | 3 c 0 3 d 0 3 e 0 3 f 0>; | 93 | 3 12 0 3 13 0 3 14 0 3 15 0>; |
| 92 | interrupt-parent = <&mpc5200_pic>; | 94 | interrupt-parent = <&mpc5200_pic>; |
| 93 | }; | 95 | }; |
| 94 | 96 | ||
| 95 | xlb@1f00 { | 97 | xlb@1f00 { |
| 96 | compatible = "fsl,mpc5200-xlb"; | 98 | compatible = "fsl,mpc5200-xlb"; |
| 97 | reg = <1f00 100>; | 99 | reg = <0x1f00 0x100>; |
| 98 | }; | 100 | }; |
| 99 | 101 | ||
| 100 | serial@2000 { // PSC1 | 102 | serial@2000 { // PSC1 |
| 101 | device_type = "serial"; | 103 | device_type = "serial"; |
| 102 | compatible = "fsl,mpc5200-psc-uart"; | 104 | compatible = "fsl,mpc5200-psc-uart"; |
| 103 | port-number = <0>; // Logical port assignment | 105 | port-number = <0>; // Logical port assignment |
| 104 | reg = <2000 100>; | 106 | reg = <0x2000 0x100>; |
| 105 | interrupts = <2 1 0>; | 107 | interrupts = <2 1 0>; |
| 106 | interrupt-parent = <&mpc5200_pic>; | 108 | interrupt-parent = <&mpc5200_pic>; |
| 107 | }; | 109 | }; |
| @@ -110,7 +112,7 @@ | |||
| 110 | device_type = "serial"; | 112 | device_type = "serial"; |
| 111 | compatible = "fsl,mpc5200-psc-uart"; | 113 | compatible = "fsl,mpc5200-psc-uart"; |
| 112 | port-number = <1>; // Logical port assignment | 114 | port-number = <1>; // Logical port assignment |
| 113 | reg = <2200 100>; | 115 | reg = <0x2200 0x100>; |
| 114 | interrupts = <2 2 0>; | 116 | interrupts = <2 2 0>; |
| 115 | interrupt-parent = <&mpc5200_pic>; | 117 | interrupt-parent = <&mpc5200_pic>; |
| 116 | }; | 118 | }; |
| @@ -119,7 +121,7 @@ | |||
| 119 | device_type = "serial"; | 121 | device_type = "serial"; |
| 120 | compatible = "fsl,mpc5200-psc-uart"; | 122 | compatible = "fsl,mpc5200-psc-uart"; |
| 121 | port-number = <2>; // Logical port assignment | 123 | port-number = <2>; // Logical port assignment |
| 122 | reg = <2400 100>; | 124 | reg = <0x2400 0x100>; |
| 123 | interrupts = <2 3 0>; | 125 | interrupts = <2 3 0>; |
| 124 | interrupt-parent = <&mpc5200_pic>; | 126 | interrupt-parent = <&mpc5200_pic>; |
| 125 | }; | 127 | }; |
| @@ -127,7 +129,7 @@ | |||
| 127 | ethernet@3000 { | 129 | ethernet@3000 { |
| 128 | device_type = "network"; | 130 | device_type = "network"; |
| 129 | compatible = "fsl,mpc5200-fec"; | 131 | compatible = "fsl,mpc5200-fec"; |
| 130 | reg = <3000 400>; | 132 | reg = <0x3000 0x400>; |
| 131 | local-mac-address = [ 00 00 00 00 00 00 ]; | 133 | local-mac-address = [ 00 00 00 00 00 00 ]; |
| 132 | interrupts = <2 5 0>; | 134 | interrupts = <2 5 0>; |
| 133 | interrupt-parent = <&mpc5200_pic>; | 135 | interrupt-parent = <&mpc5200_pic>; |
| @@ -137,8 +139,8 @@ | |||
| 137 | mdio@3000 { | 139 | mdio@3000 { |
| 138 | #address-cells = <1>; | 140 | #address-cells = <1>; |
| 139 | #size-cells = <0>; | 141 | #size-cells = <0>; |
| 140 | compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; | 142 | compatible = "fsl,mpc5200-mdio"; |
| 141 | reg = <3000 400>; // fec range, since we need to setup fec interrupts | 143 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts |
| 142 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. | 144 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
| 143 | interrupt-parent = <&mpc5200_pic>; | 145 | interrupt-parent = <&mpc5200_pic>; |
| 144 | 146 | ||
| @@ -150,7 +152,7 @@ | |||
| 150 | 152 | ||
| 151 | ata@3a00 { | 153 | ata@3a00 { |
| 152 | compatible = "fsl,mpc5200-ata"; | 154 | compatible = "fsl,mpc5200-ata"; |
| 153 | reg = <3a00 100>; | 155 | reg = <0x3a00 0x100>; |
| 154 | interrupts = <2 7 0>; | 156 | interrupts = <2 7 0>; |
| 155 | interrupt-parent = <&mpc5200_pic>; | 157 | interrupt-parent = <&mpc5200_pic>; |
| 156 | }; | 158 | }; |
| @@ -159,21 +161,21 @@ | |||
| 159 | #address-cells = <1>; | 161 | #address-cells = <1>; |
| 160 | #size-cells = <0>; | 162 | #size-cells = <0>; |
| 161 | compatible = "fsl,mpc5200-i2c","fsl-i2c"; | 163 | compatible = "fsl,mpc5200-i2c","fsl-i2c"; |
| 162 | reg = <3d40 40>; | 164 | reg = <0x3d40 0x40>; |
| 163 | interrupts = <2 10 0>; | 165 | interrupts = <2 16 0>; |
| 164 | interrupt-parent = <&mpc5200_pic>; | 166 | interrupt-parent = <&mpc5200_pic>; |
| 165 | fsl5200-clocking; | 167 | fsl5200-clocking; |
| 166 | 168 | ||
| 167 | rtc@68 { | 169 | rtc@68 { |
| 168 | device_type = "rtc"; | 170 | device_type = "rtc"; |
| 169 | compatible = "dallas,ds1307"; | 171 | compatible = "dallas,ds1307"; |
| 170 | reg = <68>; | 172 | reg = <0x68>; |
| 171 | }; | 173 | }; |
| 172 | }; | 174 | }; |
| 173 | 175 | ||
| 174 | sram@8000 { | 176 | sram@8000 { |
| 175 | compatible = "fsl,mpc5200-sram"; | 177 | compatible = "fsl,mpc5200-sram"; |
| 176 | reg = <8000 4000>; | 178 | reg = <0x8000 0x4000>; |
| 177 | }; | 179 | }; |
| 178 | }; | 180 | }; |
| 179 | 181 | ||
| @@ -182,11 +184,11 @@ | |||
| 182 | compatible = "fsl,lpb"; | 184 | compatible = "fsl,lpb"; |
| 183 | #address-cells = <2>; | 185 | #address-cells = <2>; |
| 184 | #size-cells = <1>; | 186 | #size-cells = <1>; |
| 185 | ranges = <0 0 fc000000 02000000>; | 187 | ranges = <0 0 0xfc000000 0x02000000>; |
| 186 | 188 | ||
| 187 | flash@0,0 { | 189 | flash@0,0 { |
| 188 | compatible = "cfi-flash"; | 190 | compatible = "cfi-flash"; |
| 189 | reg = <0 0 02000000>; | 191 | reg = <0 0 0x02000000>; |
| 190 | bank-width = <4>; | 192 | bank-width = <4>; |
| 191 | device-width = <2>; | 193 | device-width = <2>; |
| 192 | #size-cells = <1>; | 194 | #size-cells = <1>; |
| @@ -200,18 +202,18 @@ | |||
| 200 | #address-cells = <3>; | 202 | #address-cells = <3>; |
| 201 | device_type = "pci"; | 203 | device_type = "pci"; |
| 202 | compatible = "fsl,mpc5200-pci"; | 204 | compatible = "fsl,mpc5200-pci"; |
| 203 | reg = <f0000d00 100>; | 205 | reg = <0xf0000d00 0x100>; |
| 204 | interrupt-map-mask = <f800 0 0 7>; | 206 | interrupt-map-mask = <0xf800 0 0 7>; |
| 205 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 | 207 | interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 |
| 206 | c000 0 0 2 &mpc5200_pic 0 0 3 | 208 | 0xc000 0 0 2 &mpc5200_pic 0 0 3 |
| 207 | c000 0 0 3 &mpc5200_pic 0 0 3 | 209 | 0xc000 0 0 3 &mpc5200_pic 0 0 3 |
| 208 | c000 0 0 4 &mpc5200_pic 0 0 3>; | 210 | 0xc000 0 0 4 &mpc5200_pic 0 0 3>; |
| 209 | clock-frequency = <0>; // From boot loader | 211 | clock-frequency = <0>; // From boot loader |
| 210 | interrupts = <2 8 0 2 9 0 2 a 0>; | 212 | interrupts = <2 8 0 2 9 0 2 10 0>; |
| 211 | interrupt-parent = <&mpc5200_pic>; | 213 | interrupt-parent = <&mpc5200_pic>; |
| 212 | bus-range = <0 0>; | 214 | bus-range = <0 0>; |
| 213 | ranges = <42000000 0 80000000 80000000 0 10000000 | 215 | ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 |
| 214 | 02000000 0 90000000 90000000 0 10000000 | 216 | 0x02000000 0 0x90000000 0x90000000 0 0x10000000 |
| 215 | 01000000 0 00000000 a0000000 0 01000000>; | 217 | 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; |
| 216 | }; | 218 | }; |
| 217 | }; | 219 | }; |
