diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2006-03-16 09:10:20 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-03-16 09:10:20 -0500 |
| commit | 9e7714d08061a77d3d2ec9a6ef6fd571a534fc7f (patch) | |
| tree | e279d51b007c5f3d6b4cf157c1fada7ea7fe39da | |
| parent | 243f196d572822214bb86522f28b30e096d67414 (diff) | |
[ARM] 3367/1: CLCD mode no longer supported on the RealView boards
Patch from Catalin Marinas
Chosing of the CLCD RGB mode is no longer possible via the SYS_CLCD
register on the RealView boards. Instead, this configuration is done in the
CLCD primecell control register directly.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/mach-realview/core.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 4303d988c4bf..d13270c5d7cd 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -202,11 +202,6 @@ struct clk realview_clcd_clk = { | |||
| 202 | /* | 202 | /* |
| 203 | * CLCD support. | 203 | * CLCD support. |
| 204 | */ | 204 | */ |
| 205 | #define SYS_CLCD_MODE_MASK (3 << 0) | ||
| 206 | #define SYS_CLCD_MODE_888 (0 << 0) | ||
| 207 | #define SYS_CLCD_MODE_5551 (1 << 0) | ||
| 208 | #define SYS_CLCD_MODE_565_RLSB (2 << 0) | ||
| 209 | #define SYS_CLCD_MODE_565_BLSB (3 << 0) | ||
| 210 | #define SYS_CLCD_NLCDIOON (1 << 2) | 205 | #define SYS_CLCD_NLCDIOON (1 << 2) |
| 211 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) | 206 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) |
| 212 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) | 207 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) |
| @@ -360,29 +355,10 @@ static void realview_clcd_enable(struct clcd_fb *fb) | |||
| 360 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | 355 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
| 361 | u32 val; | 356 | u32 val; |
| 362 | 357 | ||
| 363 | val = readl(sys_clcd); | ||
| 364 | val &= ~SYS_CLCD_MODE_MASK; | ||
| 365 | |||
| 366 | switch (fb->fb.var.green.length) { | ||
| 367 | case 5: | ||
| 368 | val |= SYS_CLCD_MODE_5551; | ||
| 369 | break; | ||
| 370 | case 6: | ||
| 371 | val |= SYS_CLCD_MODE_565_RLSB; | ||
| 372 | break; | ||
| 373 | case 8: | ||
| 374 | val |= SYS_CLCD_MODE_888; | ||
| 375 | break; | ||
| 376 | } | ||
| 377 | |||
| 378 | /* | ||
| 379 | * Set the MUX | ||
| 380 | */ | ||
| 381 | writel(val, sys_clcd); | ||
| 382 | |||
| 383 | /* | 358 | /* |
| 384 | * And now enable the PSUs | 359 | * Enable the PSUs |
| 385 | */ | 360 | */ |
| 361 | val = readl(sys_clcd); | ||
| 386 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | 362 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
| 387 | writel(val, sys_clcd); | 363 | writel(val, sys_clcd); |
| 388 | } | 364 | } |
