Merge HEAD from master.kernel.org:/home/rmk/linux-2.6-arm.git

6 files changed, 213 insertions, 39 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e85097bceff4..4bf0e8737e1f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -635,10 +635,6 @@ config PM
           and the Battery Powered Linux mini-HOWTO, available from
           <http://www.tldp.org/docs.html#howto>.
 
-          Note that, even if you say N here, Linux on the x86 architecture
-          will issue the hlt instruction if nothing is to be done, thereby
-          sending the processor to sleep and saving power.
-
 config APM
         tristate "Advanced Power Management Emulation"
         depends on PM
@@ -650,12 +646,6 @@ config APM
           battery status information, and user-space programs will receive
           notification of APM "events" (e.g. battery status change).
 
-          If you select "Y" here, you can disable actual use of the APM
-          BIOS by passing the "apm=off" option to the kernel at boot time.
-
-          Note that the APM support is almost completely disabled for
-          machines with more than one CPU.
-
           In order to use APM, you will need supporting software. For location
           and more information, read <file:Documentation/pm.txt> and the
           Battery Powered Linux mini-HOWTO, available from
@@ -665,39 +655,12 @@ config APM
           manpage ("man 8 hdparm") for that), and it doesn't turn off
           VESA-compliant "green" monitors.
 
-          This driver does not support the TI 4000M TravelMate and the ACER
-          486/DX4/75 because they don't have compliant BIOSes. Many "green"
-          desktop machines also don't have compliant BIOSes, and this driver
-          may cause those machines to panic during the boot phase.
-
           Generally, if you don't have a battery in your machine, there isn't
           much point in using this driver and you should say N. If you get
           random kernel OOPSes or reboots that don't seem to be related to
           anything, try disabling/enabling this option (or disabling/enabling
           APM in your BIOS).
 
-          Some other things you should try when experiencing seemingly random,
-          "weird" problems:
-
-          1) make sure that you have enough swap space and that it is
-          enabled.
-          2) pass the "no-hlt" option to the kernel
-          3) switch on floating point emulation in the kernel and pass
-          the "no387" option to the kernel
-          4) pass the "floppy=nodma" option to the kernel
-          5) pass the "mem=4M" option to the kernel (thereby disabling
-          all but the first 4 MB of RAM)
-          6) make sure that the CPU is not over clocked.
-          7) read the sig11 FAQ at <http://www.bitwizard.nl/sig11/>
-          8) disable the cache from your BIOS settings
-          9) install a fan for the video card or exchange video RAM
-          10) install a better fan for the CPU
-          11) exchange RAM chips
-          12) exchange the motherboard.
-
-          To compile this driver as a module, choose M here: the
-          module will be called apm.
-
 endmenu
 
 source "net/Kconfig"
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 692af6b5e8ff..666ba393575b 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,6 +1,9 @@
 config ICST525
         bool
 
+config ARM_GIC
+        bool
+
 config ICST307
         bool
 
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 11f20a43ee3a..a87886564b19 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -4,6 +4,7 @@
 
 obj-y                           += rtctime.o
 obj-$(CONFIG_ARM_AMBA)          += amba.o
+obj-$(CONFIG_ARM_GIC)           += gic.o
 obj-$(CONFIG_ICST525)           += icst525.o
 obj-$(CONFIG_ICST307)           += icst307.o
 obj-$(CONFIG_SA1111)            += sa1111.o
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
new file mode 100644
index 000000000000..51dbf5489b6b
--- /dev/null
+++ b/arch/arm/common/gic.c
@@ -0,0 +1,166 @@
+/*
+ *  linux/arch/arm/common/gic.c
+ *
+ *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Interrupt architecture for the GIC:
+ *
+ * o There is one Interrupt Distributor, which receives interrupts
+ *   from system devices and sends them to the Interrupt Controllers.
+ *
+ * o There is one CPU Interface per CPU, which sends interrupts sent
+ *   by the Distributor, and interrupts generated locally, to the
+ *   associated CPU.
+ *
+ * Note that IRQs 0-31 are special - they are local to each CPU.
+ * As such, the enable set/clear, pending set/clear and active bit
+ * registers are banked per-cpu for these sources.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/smp.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/mach/irq.h>
+#include <asm/hardware/gic.h>
+
+static void __iomem *gic_dist_base;
+static void __iomem *gic_cpu_base;
+
+/*
+ * Routines to acknowledge, disable and enable interrupts
+ *
+ * Linux assumes that when we're done with an interrupt we need to
+ * unmask it, in the same way we need to unmask an interrupt when
+ * we first enable it.
+ *
+ * The GIC has a seperate notion of "end of interrupt" to re-enable
+ * an interrupt after handling, in order to support hardware
+ * prioritisation.
+ *
+ * We can make the GIC behave in the way that Linux expects by making
+ * our "acknowledge" routine disable the interrupt, then mark it as
+ * complete.
+ */
+static void gic_ack_irq(unsigned int irq)
+{
+        u32 mask = 1 << (irq % 32);
+        writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
+        writel(irq, gic_cpu_base + GIC_CPU_EOI);
+}
+
+static void gic_mask_irq(unsigned int irq)
+{
+        u32 mask = 1 << (irq % 32);
+        writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
+}
+
+static void gic_unmask_irq(unsigned int irq)
+{
+        u32 mask = 1 << (irq % 32);
+        writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
+}
+
+static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu)
+{
+        void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
+        unsigned int shift = (irq % 4) * 8;
+        u32 val;
+
+        val = readl(reg) & ~(0xff << shift);
+        val |= 1 << (cpu + shift);
+        writel(val, reg);
+}
+
+static struct irqchip gic_chip = {
+        .ack            = gic_ack_irq,
+        .mask           = gic_mask_irq,
+        .unmask         = gic_unmask_irq,
+#ifdef CONFIG_SMP
+        .set_cpu        = gic_set_cpu,
+#endif
+};
+
+void __init gic_dist_init(void __iomem *base)
+{
+        unsigned int max_irq, i;
+        u32 cpumask = 1 << smp_processor_id();
+
+        cpumask |= cpumask << 8;
+        cpumask |= cpumask << 16;
+
+        gic_dist_base = base;
+
+        writel(0, base + GIC_DIST_CTRL);
+
+        /*
+         * Find out how many interrupts are supported.
+         */
+        max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
+        max_irq = (max_irq + 1) * 32;
+
+        /*
+         * The GIC only supports up to 1020 interrupt sources.
+         * Limit this to either the architected maximum, or the
+         * platform maximum.
+         */
+        if (max_irq > max(1020, NR_IRQS))
+                max_irq = max(1020, NR_IRQS);
+
+        /*
+         * Set all global interrupts to be level triggered, active low.
+         */
+        for (i = 32; i < max_irq; i += 16)
+                writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
+
+        /*
+         * Set all global interrupts to this CPU only.
+         */
+        for (i = 32; i < max_irq; i += 4)
+                writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+
+        /*
+         * Set priority on all interrupts.
+         */
+        for (i = 0; i < max_irq; i += 4)
+                writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
+
+        /*
+         * Disable all interrupts.
+         */
+        for (i = 0; i < max_irq; i += 32)
+                writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+
+        /*
+         * Setup the Linux IRQ subsystem.
+         */
+        for (i = 29; i < max_irq; i++) {
+                set_irq_chip(i, &gic_chip);
+                set_irq_handler(i, do_level_IRQ);
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+        }
+
+        writel(1, base + GIC_DIST_CTRL);
+}
+
+void __cpuinit gic_cpu_init(void __iomem *base)
+{
+        gic_cpu_base = base;
+        writel(0xf0, base + GIC_CPU_PRIMASK);
+        writel(1, base + GIC_CPU_CTRL);
+}
+
+#ifdef CONFIG_SMP
+void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
+{
+        unsigned long map = *cpus_addr(cpumask);
+
+        writel(map << 16 | irq, gic_dist_base + GIC_DIST_SOFTINT);
+}
+#endif
diff --git a/fs/adfs/adfs.h b/fs/adfs/adfs.h
index 63f5df9afb71..fd528433de43 100644
--- a/fs/adfs/adfs.h
+++ b/fs/adfs/adfs.h
@@ -97,7 +97,7 @@ extern int adfs_dir_update(struct super_block *sb, struct object_info *obj);
 extern struct inode_operations adfs_file_inode_operations;
 extern struct file_operations adfs_file_operations;
 
-extern inline __u32 signed_asl(__u32 val, signed int shift)
+static inline __u32 signed_asl(__u32 val, signed int shift)
 {
         if (shift >= 0)
                 val <<= shift;
@@ -112,7 +112,7 @@ extern inline __u32 signed_asl(__u32 val, signed int shift)
  *
  * The root directory ID should always be looked up in the map [3.4]
  */
-extern inline int
+static inline int
 __adfs_block_map(struct super_block *sb, unsigned int object_id,
                  unsigned int block)
 {
diff --git a/include/asm-arm/hardware/gic.h b/include/asm-arm/hardware/gic.h
new file mode 100644
index 000000000000..3fa5eb70f64e
--- /dev/null
+++ b/include/asm-arm/hardware/gic.h
@@ -0,0 +1,41 @@
+/*
+ *  linux/include/asm-arm/hardware/gic.h
+ *
+ *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_HARDWARE_GIC_H
+#define __ASM_ARM_HARDWARE_GIC_H
+
+#include <linux/compiler.h>
+
+#define GIC_CPU_CTRL                    0x00
+#define GIC_CPU_PRIMASK                 0x04
+#define GIC_CPU_BINPOINT                0x08
+#define GIC_CPU_INTACK                  0x0c
+#define GIC_CPU_EOI                     0x10
+#define GIC_CPU_RUNNINGPRI              0x14
+#define GIC_CPU_HIGHPRI                 0x18
+
+#define GIC_DIST_CTRL                   0x000
+#define GIC_DIST_CTR                    0x004
+#define GIC_DIST_ENABLE_SET             0x100
+#define GIC_DIST_ENABLE_CLEAR           0x180
+#define GIC_DIST_PENDING_SET            0x200
+#define GIC_DIST_PENDING_CLEAR          0x280
+#define GIC_DIST_ACTIVE_BIT             0x300
+#define GIC_DIST_PRI                    0x400
+#define GIC_DIST_TARGET                 0x800
+#define GIC_DIST_CONFIG                 0xc00
+#define GIC_DIST_SOFTINT                0xf00
+
+#ifndef __ASSEMBLY__
+void gic_dist_init(void __iomem *base);
+void gic_cpu_init(void __iomem *base);
+void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
+#endif
+
+#endif