diff options
| author | Michal Simek <monstr@monstr.eu> | 2010-06-22 15:18:57 -0400 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2010-08-04 04:45:16 -0400 |
| commit | 958063e67b775bc1be85eb3761c85202597a87aa (patch) | |
| tree | c3d13d27732ee7fa5a71633a2579f8798b1983d8 | |
| parent | 0e41c90908881a1b8205c66a66becec7d8d4eb4a (diff) | |
microblaze: Remove nop after MSRCLR/SET, MTS, MFS instructions
We need to save instruction and the latest Microblaze shouldn't
have any problem with it.
Signed-off-by: Michal Simek <monstr@monstr.eu>
| -rw-r--r-- | arch/microblaze/kernel/entry.S | 51 |
1 files changed, 0 insertions, 51 deletions
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S index bf6b2b122485..397754cd31c9 100644 --- a/arch/microblaze/kernel/entry.S +++ b/arch/microblaze/kernel/entry.S | |||
| @@ -49,138 +49,106 @@ | |||
| 49 | #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR | 49 | #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR |
| 50 | .macro clear_bip | 50 | .macro clear_bip |
| 51 | msrclr r0, MSR_BIP | 51 | msrclr r0, MSR_BIP |
| 52 | nop | ||
| 53 | .endm | 52 | .endm |
| 54 | 53 | ||
| 55 | .macro set_bip | 54 | .macro set_bip |
| 56 | msrset r0, MSR_BIP | 55 | msrset r0, MSR_BIP |
| 57 | nop | ||
| 58 | .endm | 56 | .endm |
| 59 | 57 | ||
| 60 | .macro clear_eip | 58 | .macro clear_eip |
| 61 | msrclr r0, MSR_EIP | 59 | msrclr r0, MSR_EIP |
| 62 | nop | ||
| 63 | .endm | 60 | .endm |
| 64 | 61 | ||
| 65 | .macro set_ee | 62 | .macro set_ee |
| 66 | msrset r0, MSR_EE | 63 | msrset r0, MSR_EE |
| 67 | nop | ||
| 68 | .endm | 64 | .endm |
| 69 | 65 | ||
| 70 | .macro disable_irq | 66 | .macro disable_irq |
| 71 | msrclr r0, MSR_IE | 67 | msrclr r0, MSR_IE |
| 72 | nop | ||
| 73 | .endm | 68 | .endm |
| 74 | 69 | ||
| 75 | .macro enable_irq | 70 | .macro enable_irq |
| 76 | msrset r0, MSR_IE | 71 | msrset r0, MSR_IE |
| 77 | nop | ||
| 78 | .endm | 72 | .endm |
| 79 | 73 | ||
| 80 | .macro set_ums | 74 | .macro set_ums |
| 81 | msrset r0, MSR_UMS | 75 | msrset r0, MSR_UMS |
| 82 | nop | ||
| 83 | msrclr r0, MSR_VMS | 76 | msrclr r0, MSR_VMS |
| 84 | nop | ||
| 85 | .endm | 77 | .endm |
| 86 | 78 | ||
| 87 | .macro set_vms | 79 | .macro set_vms |
| 88 | msrclr r0, MSR_UMS | 80 | msrclr r0, MSR_UMS |
| 89 | nop | ||
| 90 | msrset r0, MSR_VMS | 81 | msrset r0, MSR_VMS |
| 91 | nop | ||
| 92 | .endm | 82 | .endm |
| 93 | 83 | ||
| 94 | .macro clear_ums | 84 | .macro clear_ums |
| 95 | msrclr r0, MSR_UMS | 85 | msrclr r0, MSR_UMS |
| 96 | nop | ||
| 97 | .endm | 86 | .endm |
| 98 | 87 | ||
| 99 | .macro clear_vms_ums | 88 | .macro clear_vms_ums |
| 100 | msrclr r0, MSR_VMS | MSR_UMS | 89 | msrclr r0, MSR_VMS | MSR_UMS |
| 101 | nop | ||
| 102 | .endm | 90 | .endm |
| 103 | #else | 91 | #else |
| 104 | .macro clear_bip | 92 | .macro clear_bip |
| 105 | mfs r11, rmsr | 93 | mfs r11, rmsr |
| 106 | nop | ||
| 107 | andi r11, r11, ~MSR_BIP | 94 | andi r11, r11, ~MSR_BIP |
| 108 | mts rmsr, r11 | 95 | mts rmsr, r11 |
| 109 | nop | ||
| 110 | .endm | 96 | .endm |
| 111 | 97 | ||
| 112 | .macro set_bip | 98 | .macro set_bip |
| 113 | mfs r11, rmsr | 99 | mfs r11, rmsr |
| 114 | nop | ||
| 115 | ori r11, r11, MSR_BIP | 100 | ori r11, r11, MSR_BIP |
| 116 | mts rmsr, r11 | 101 | mts rmsr, r11 |
| 117 | nop | ||
| 118 | .endm | 102 | .endm |
| 119 | 103 | ||
| 120 | .macro clear_eip | 104 | .macro clear_eip |
| 121 | mfs r11, rmsr | 105 | mfs r11, rmsr |
| 122 | nop | ||
| 123 | andi r11, r11, ~MSR_EIP | 106 | andi r11, r11, ~MSR_EIP |
| 124 | mts rmsr, r11 | 107 | mts rmsr, r11 |
| 125 | nop | ||
| 126 | .endm | 108 | .endm |
| 127 | 109 | ||
| 128 | .macro set_ee | 110 | .macro set_ee |
| 129 | mfs r11, rmsr | 111 | mfs r11, rmsr |
| 130 | nop | ||
| 131 | ori r11, r11, MSR_EE | 112 | ori r11, r11, MSR_EE |
| 132 | mts rmsr, r11 | 113 | mts rmsr, r11 |
| 133 | nop | ||
| 134 | .endm | 114 | .endm |
| 135 | 115 | ||
| 136 | .macro disable_irq | 116 | .macro disable_irq |
| 137 | mfs r11, rmsr | 117 | mfs r11, rmsr |
| 138 | nop | ||
| 139 | andi r11, r11, ~MSR_IE | 118 | andi r11, r11, ~MSR_IE |
| 140 | mts rmsr, r11 | 119 | mts rmsr, r11 |
| 141 | nop | ||
| 142 | .endm | 120 | .endm |
| 143 | 121 | ||
| 144 | .macro enable_irq | 122 | .macro enable_irq |
| 145 | mfs r11, rmsr | 123 | mfs r11, rmsr |
| 146 | nop | ||
| 147 | ori r11, r11, MSR_IE | 124 | ori r11, r11, MSR_IE |
| 148 | mts rmsr, r11 | 125 | mts rmsr, r11 |
| 149 | nop | ||
| 150 | .endm | 126 | .endm |
| 151 | 127 | ||
| 152 | .macro set_ums | 128 | .macro set_ums |
| 153 | mfs r11, rmsr | 129 | mfs r11, rmsr |
| 154 | nop | ||
| 155 | ori r11, r11, MSR_VMS | 130 | ori r11, r11, MSR_VMS |
| 156 | andni r11, r11, MSR_UMS | 131 | andni r11, r11, MSR_UMS |
| 157 | mts rmsr, r11 | 132 | mts rmsr, r11 |
| 158 | nop | ||
| 159 | .endm | 133 | .endm |
| 160 | 134 | ||
| 161 | .macro set_vms | 135 | .macro set_vms |
| 162 | mfs r11, rmsr | 136 | mfs r11, rmsr |
| 163 | nop | ||
| 164 | ori r11, r11, MSR_VMS | 137 | ori r11, r11, MSR_VMS |
| 165 | andni r11, r11, MSR_UMS | 138 | andni r11, r11, MSR_UMS |
| 166 | mts rmsr, r11 | 139 | mts rmsr, r11 |
| 167 | nop | ||
| 168 | .endm | 140 | .endm |
| 169 | 141 | ||
| 170 | .macro clear_ums | 142 | .macro clear_ums |
| 171 | mfs r11, rmsr | 143 | mfs r11, rmsr |
| 172 | nop | ||
| 173 | andni r11, r11, MSR_UMS | 144 | andni r11, r11, MSR_UMS |
| 174 | mts rmsr,r11 | 145 | mts rmsr,r11 |
| 175 | nop | ||
| 176 | .endm | 146 | .endm |
| 177 | 147 | ||
| 178 | .macro clear_vms_ums | 148 | .macro clear_vms_ums |
| 179 | mfs r11, rmsr | 149 | mfs r11, rmsr |
| 180 | nop | ||
| 181 | andni r11, r11, (MSR_VMS|MSR_UMS) | 150 | andni r11, r11, (MSR_VMS|MSR_UMS) |
| 182 | mts rmsr,r11 | 151 | mts rmsr,r11 |
| 183 | nop | ||
| 184 | .endm | 152 | .endm |
| 185 | #endif | 153 | #endif |
| 186 | 154 | ||
| @@ -233,13 +201,11 @@ | |||
| 233 | swi r30, r1, PTO+PT_R30; \ | 201 | swi r30, r1, PTO+PT_R30; \ |
| 234 | swi r31, r1, PTO+PT_R31; /* Save current task reg */ \ | 202 | swi r31, r1, PTO+PT_R31; /* Save current task reg */ \ |
| 235 | mfs r11, rmsr; /* save MSR */ \ | 203 | mfs r11, rmsr; /* save MSR */ \ |
| 236 | nop; \ | ||
| 237 | swi r11, r1, PTO+PT_MSR; | 204 | swi r11, r1, PTO+PT_MSR; |
| 238 | 205 | ||
| 239 | #define RESTORE_REGS \ | 206 | #define RESTORE_REGS \ |
| 240 | lwi r11, r1, PTO+PT_MSR; \ | 207 | lwi r11, r1, PTO+PT_MSR; \ |
| 241 | mts rmsr , r11; \ | 208 | mts rmsr , r11; \ |
| 242 | nop; \ | ||
| 243 | lwi r2, r1, PTO+PT_R2; /* restore SDA */ \ | 209 | lwi r2, r1, PTO+PT_R2; /* restore SDA */ \ |
| 244 | lwi r3, r1, PTO+PT_R3; \ | 210 | lwi r3, r1, PTO+PT_R3; \ |
| 245 | lwi r4, r1, PTO+PT_R4; \ | 211 | lwi r4, r1, PTO+PT_R4; \ |
| @@ -273,7 +239,6 @@ | |||
| 273 | swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* save stack */ \ | 239 | swi r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* save stack */ \ |
| 274 | /* See if already in kernel mode.*/ \ | 240 | /* See if already in kernel mode.*/ \ |
| 275 | mfs r1, rmsr; \ | 241 | mfs r1, rmsr; \ |
| 276 | nop; \ | ||
| 277 | andi r1, r1, MSR_UMS; \ | 242 | andi r1, r1, MSR_UMS; \ |
| 278 | bnei r1, 1f; \ | 243 | bnei r1, 1f; \ |
| 279 | /* Kernel-mode state save. */ \ | 244 | /* Kernel-mode state save. */ \ |
| @@ -518,11 +483,8 @@ C_ENTRY(full_exception_trap): | |||
| 518 | /* where the trap should return need -8 to adjust for rtsd r15, 8 */ | 483 | /* where the trap should return need -8 to adjust for rtsd r15, 8 */ |
| 519 | addik r15, r0, ret_from_exc - 8 | 484 | addik r15, r0, ret_from_exc - 8 |
| 520 | mfs r6, resr | 485 | mfs r6, resr |
| 521 | nop | ||
| 522 | mfs r7, rfsr; /* save FSR */ | 486 | mfs r7, rfsr; /* save FSR */ |
| 523 | nop | ||
| 524 | mts rfsr, r0; /* Clear sticky fsr */ | 487 | mts rfsr, r0; /* Clear sticky fsr */ |
| 525 | nop | ||
| 526 | rted r0, full_exception | 488 | rted r0, full_exception |
| 527 | addik r5, r1, PTO /* parameter struct pt_regs * regs */ | 489 | addik r5, r1, PTO /* parameter struct pt_regs * regs */ |
| 528 | 490 | ||
| @@ -555,9 +517,7 @@ C_ENTRY(unaligned_data_trap): | |||
| 555 | /* where the trap should return need -8 to adjust for rtsd r15, 8 */ | 517 | /* where the trap should return need -8 to adjust for rtsd r15, 8 */ |
| 556 | addik r15, r0, ret_from_exc-8 | 518 | addik r15, r0, ret_from_exc-8 |
| 557 | mfs r3, resr /* ESR */ | 519 | mfs r3, resr /* ESR */ |
| 558 | nop | ||
| 559 | mfs r4, rear /* EAR */ | 520 | mfs r4, rear /* EAR */ |
| 560 | nop | ||
| 561 | rtbd r0, _unaligned_data_exception | 521 | rtbd r0, _unaligned_data_exception |
| 562 | addik r7, r1, PTO /* parameter struct pt_regs * regs */ | 522 | addik r7, r1, PTO /* parameter struct pt_regs * regs */ |
| 563 | 523 | ||
| @@ -587,9 +547,7 @@ C_ENTRY(page_fault_data_trap): | |||
| 587 | /* where the trap should return need -8 to adjust for rtsd r15, 8 */ | 547 | /* where the trap should return need -8 to adjust for rtsd r15, 8 */ |
| 588 | addik r15, r0, ret_from_exc-8 | 548 | addik r15, r0, ret_from_exc-8 |
| 589 | mfs r6, rear /* parameter unsigned long address */ | 549 | mfs r6, rear /* parameter unsigned long address */ |
| 590 | nop | ||
| 591 | mfs r7, resr /* parameter unsigned long error_code */ | 550 | mfs r7, resr /* parameter unsigned long error_code */ |
| 592 | nop | ||
| 593 | rted r0, do_page_fault | 551 | rted r0, do_page_fault |
| 594 | addik r5, r1, PTO /* parameter struct pt_regs * regs */ | 552 | addik r5, r1, PTO /* parameter struct pt_regs * regs */ |
| 595 | 553 | ||
| @@ -601,7 +559,6 @@ C_ENTRY(page_fault_instr_trap): | |||
| 601 | /* where the trap should return need -8 to adjust for rtsd r15, 8 */ | 559 | /* where the trap should return need -8 to adjust for rtsd r15, 8 */ |
| 602 | addik r15, r0, ret_from_exc-8 | 560 | addik r15, r0, ret_from_exc-8 |
| 603 | mfs r6, rear /* parameter unsigned long address */ | 561 | mfs r6, rear /* parameter unsigned long address */ |
| 604 | nop | ||
| 605 | ori r7, r0, 0 /* parameter unsigned long error_code */ | 562 | ori r7, r0, 0 /* parameter unsigned long error_code */ |
| 606 | rted r0, do_page_fault | 563 | rted r0, do_page_fault |
| 607 | addik r5, r1, PTO /* parameter struct pt_regs * regs */ | 564 | addik r5, r1, PTO /* parameter struct pt_regs * regs */ |
| @@ -936,16 +893,12 @@ ENTRY(_switch_to) | |||
| 936 | swi r30, r11, CC_R30 | 893 | swi r30, r11, CC_R30 |
| 937 | /* special purpose registers */ | 894 | /* special purpose registers */ |
| 938 | mfs r12, rmsr | 895 | mfs r12, rmsr |
| 939 | nop | ||
| 940 | swi r12, r11, CC_MSR | 896 | swi r12, r11, CC_MSR |
| 941 | mfs r12, rear | 897 | mfs r12, rear |
| 942 | nop | ||
| 943 | swi r12, r11, CC_EAR | 898 | swi r12, r11, CC_EAR |
| 944 | mfs r12, resr | 899 | mfs r12, resr |
| 945 | nop | ||
| 946 | swi r12, r11, CC_ESR | 900 | swi r12, r11, CC_ESR |
| 947 | mfs r12, rfsr | 901 | mfs r12, rfsr |
| 948 | nop | ||
| 949 | swi r12, r11, CC_FSR | 902 | swi r12, r11, CC_FSR |
| 950 | 903 | ||
| 951 | /* update r31, the current-give me pointer to task which will be next */ | 904 | /* update r31, the current-give me pointer to task which will be next */ |
| @@ -984,10 +937,8 @@ ENTRY(_switch_to) | |||
| 984 | /* special purpose registers */ | 937 | /* special purpose registers */ |
| 985 | lwi r12, r11, CC_FSR | 938 | lwi r12, r11, CC_FSR |
| 986 | mts rfsr, r12 | 939 | mts rfsr, r12 |
| 987 | nop | ||
| 988 | lwi r12, r11, CC_MSR | 940 | lwi r12, r11, CC_MSR |
| 989 | mts rmsr, r12 | 941 | mts rmsr, r12 |
| 990 | nop | ||
| 991 | 942 | ||
| 992 | rtsd r15, 8 | 943 | rtsd r15, 8 |
| 993 | nop | 944 | nop |
| @@ -997,10 +948,8 @@ ENTRY(_reset) | |||
| 997 | 948 | ||
| 998 | ENTRY(_break) | 949 | ENTRY(_break) |
| 999 | mfs r5, rmsr | 950 | mfs r5, rmsr |
| 1000 | nop | ||
| 1001 | swi r5, r0, 0x250 + TOPHYS(r0_ram) | 951 | swi r5, r0, 0x250 + TOPHYS(r0_ram) |
| 1002 | mfs r5, resr | 952 | mfs r5, resr |
| 1003 | nop | ||
| 1004 | swi r5, r0, 0x254 + TOPHYS(r0_ram) | 953 | swi r5, r0, 0x254 + TOPHYS(r0_ram) |
| 1005 | bri 0 | 954 | bri 0 |
| 1006 | 955 | ||
