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authorLinus Torvalds <torvalds@linux-foundation.org>2010-09-27 15:32:36 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-09-27 15:32:36 -0400
commit6e029fe3737b022610ededf9e70ee84fb2bdc045 (patch)
tree0fc7a86e17014907d32e1b6dcb3b8b310b495870
parent26d1e7ced7a51c9ebcff058a9671513fe1fe05b1 (diff)
parent2de59fea8b3095d1df4c729fda041625930aab4f (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits) ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tile ARM: 6409/1: davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE ARM: 6408/1: omap: Map only available sram memory ARM: 6407/1: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries ARM: pxa: remove pr_<level> uses of KERN_<level> ARM: pxa168fb: clear enable bit when not active ARM: pxa: fix cpu_is_pxa*() not expanding to zero when not configured ARM: pxa168: fix corrected reset vector ARM: pxa: Use PIO for PI2C communication on Palm27x ARM: pxa: Fix Vpac270 gpio_power for MMC ARM: 6401/1: plug a race in the alignment trap handler ARM: 6406/1: at91sam9g45: fix i2c bus speed leds: leds-ns2: fix locking ARM: dove: fix __io() definition to use bus based offset dmaengine: fix interrupt clearing for mv_xor ARM: kirkwood: Unbreak PCIe I/O port ARM: Fix build error when using KCONFIG_CONFIG ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasing ARM: 6400/1: at91: fix arch_gettimeoffset fallout ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARM ...
Diffstat
-rw-r--r--arch/arm/Kconfig27
-rw-r--r--arch/arm/boot/compressed/Makefile2
-rw-r--r--arch/arm/include/asm/pgtable.h4
-rw-r--r--arch/arm/kernel/entry-common.S2
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c4
-rw-r--r--arch/arm/mach-davinci/dm355.c3
-rw-r--r--arch/arm/mach-davinci/dm365.c3
-rw-r--r--arch/arm/mach-davinci/dm644x.c3
-rw-r--r--arch/arm/mach-davinci/dm646x.c3
-rw-r--r--arch/arm/mach-dove/include/mach/io.h6
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h2
-rw-r--r--arch/arm/mach-kirkwood/pcie.c4
-rw-r--r--arch/arm/mach-mmp/include/mach/system.h7
-rw-r--r--arch/arm/mach-pxa/cpufreq-pxa2xx.c3
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h12
-rw-r--r--arch/arm/mach-pxa/palm27x.c6
-rw-r--r--arch/arm/mach-pxa/vpac270.c1
-rw-r--r--arch/arm/mach-u300/include/mach/gpio.h3
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c8
-rw-r--r--arch/arm/mm/alignment.c19
-rw-r--r--arch/arm/mm/mmu.c31
-rw-r--r--arch/arm/mm/proc-v7.S62
-rw-r--r--arch/arm/plat-nomadik/timer.c33
-rw-r--r--arch/arm/plat-omap/sram.c25
-rw-r--r--drivers/dma/mv_xor.c2
-rw-r--r--drivers/leds/leds-ns2.c9
-rw-r--r--drivers/video/pxa168fb.c4
27 files changed, 207 insertions, 81 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 553b7cf17bfb..88c97bc7a6f5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -271,7 +271,6 @@ config ARCH_AT91
271 bool "Atmel AT91" 271 bool "Atmel AT91"
272 select ARCH_REQUIRE_GPIOLIB 272 select ARCH_REQUIRE_GPIOLIB
273 select HAVE_CLK 273 select HAVE_CLK
274 select ARCH_USES_GETTIMEOFFSET
275 help 274 help
276 This enables support for systems based on the Atmel AT91RM9200, 275 This enables support for systems based on the Atmel AT91RM9200,
277 AT91SAM9 and AT91CAP9 processors. 276 AT91SAM9 and AT91CAP9 processors.
@@ -1051,6 +1050,32 @@ config ARM_ERRATA_460075
1051 ACTLR register. Note that setting specific bits in the ACTLR register 1050 ACTLR register. Note that setting specific bits in the ACTLR register
1052 may not be available in non-secure mode. 1051 may not be available in non-secure mode.
1053 1052
1053config ARM_ERRATA_742230
1054 bool "ARM errata: DMB operation may be faulty"
1055 depends on CPU_V7 && SMP
1056 help
1057 This option enables the workaround for the 742230 Cortex-A9
1058 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1059 between two write operations may not ensure the correct visibility
1060 ordering of the two writes. This workaround sets a specific bit in
1061 the diagnostic register of the Cortex-A9 which causes the DMB
1062 instruction to behave as a DSB, ensuring the correct behaviour of
1063 the two writes.
1064
1065config ARM_ERRATA_742231
1066 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1067 depends on CPU_V7 && SMP
1068 help
1069 This option enables the workaround for the 742231 Cortex-A9
1070 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1071 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1072 accessing some data located in the same cache line, may get corrupted
1073 data due to bad handling of the address hazard when the line gets
1074 replaced from one of the CPUs at the same time as another CPU is
1075 accessing it. This workaround sets specific bits in the diagnostic
1076 register of the Cortex-A9 which reduces the linefill issuing
1077 capabilities of the processor.
1078
1054config PL310_ERRATA_588369 1079config PL310_ERRATA_588369
1055 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1080 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1056 depends on CACHE_L2X0 && ARCH_OMAP4 1081 depends on CACHE_L2X0 && ARCH_OMAP4
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index b23f6bc46cfa..65a7c1c588a9 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -116,5 +116,5 @@ CFLAGS_font.o := -Dstatic=
116$(obj)/font.c: $(FONTC) 116$(obj)/font.c: $(FONTC)
117 $(call cmd,shipped) 117 $(call cmd,shipped)
118 118
119$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config 119$(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG)
120 @sed "$(SEDFLAGS)" < $< > $@ 120 @sed "$(SEDFLAGS)" < $< > $@
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index ab68cf1ef80f..e90b167ea848 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -317,6 +317,10 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
317#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 317#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
318#define pgprot_dmacoherent(prot) \ 318#define pgprot_dmacoherent(prot) \
319 __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE) 319 __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
320#define __HAVE_PHYS_MEM_ACCESS_PROT
321struct file;
322extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
323 unsigned long size, pgprot_t vma_prot);
320#else 324#else
321#define pgprot_dmacoherent(prot) \ 325#define pgprot_dmacoherent(prot) \
322 __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED) 326 __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 1b560825e1cf..7885722bdf4e 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -48,6 +48,8 @@ work_pending:
48 beq no_work_pending 48 beq no_work_pending
49 mov r0, sp @ 'regs' 49 mov r0, sp @ 'regs'
50 mov r2, why @ 'syscall' 50 mov r2, why @ 'syscall'
51 tst r1, #_TIF_SIGPENDING @ delivering a signal?
52 movne why, #0 @ prevent further restarts
51 bl do_notify_resume 53 bl do_notify_resume
52 b ret_slow_syscall @ Check work again 54 b ret_slow_syscall @ Check work again
53 55
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 5e71ccd5e7d3..1276babf84d5 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -426,7 +426,7 @@ static struct i2c_gpio_platform_data pdata_i2c0 = {
426 .sda_is_open_drain = 1, 426 .sda_is_open_drain = 1,
427 .scl_pin = AT91_PIN_PA21, 427 .scl_pin = AT91_PIN_PA21,
428 .scl_is_open_drain = 1, 428 .scl_is_open_drain = 1,
429 .udelay = 2, /* ~100 kHz */ 429 .udelay = 5, /* ~100 kHz */
430}; 430};
431 431
432static struct platform_device at91sam9g45_twi0_device = { 432static struct platform_device at91sam9g45_twi0_device = {
@@ -440,7 +440,7 @@ static struct i2c_gpio_platform_data pdata_i2c1 = {
440 .sda_is_open_drain = 1, 440 .sda_is_open_drain = 1,
441 .scl_pin = AT91_PIN_PB11, 441 .scl_pin = AT91_PIN_PB11,
442 .scl_is_open_drain = 1, 442 .scl_is_open_drain = 1,
443 .udelay = 2, /* ~100 kHz */ 443 .udelay = 5, /* ~100 kHz */
444}; 444};
445 445
446static struct platform_device at91sam9g45_twi1_device = { 446static struct platform_device at91sam9g45_twi1_device = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 3d996b659ff4..9be261beae7d 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -769,8 +769,7 @@ static struct map_desc dm355_io_desc[] = {
769 .virtual = SRAM_VIRT, 769 .virtual = SRAM_VIRT,
770 .pfn = __phys_to_pfn(0x00010000), 770 .pfn = __phys_to_pfn(0x00010000),
771 .length = SZ_32K, 771 .length = SZ_32K,
772 /* MT_MEMORY_NONCACHED requires supersection alignment */ 772 .type = MT_MEMORY_NONCACHED,
773 .type = MT_DEVICE,
774 }, 773 },
775}; 774};
776 775
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 6b6f4c643709..7781e35daec3 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -969,8 +969,7 @@ static struct map_desc dm365_io_desc[] = {
969 .virtual = SRAM_VIRT, 969 .virtual = SRAM_VIRT,
970 .pfn = __phys_to_pfn(0x00010000), 970 .pfn = __phys_to_pfn(0x00010000),
971 .length = SZ_32K, 971 .length = SZ_32K,
972 /* MT_MEMORY_NONCACHED requires supersection alignment */ 972 .type = MT_MEMORY_NONCACHED,
973 .type = MT_DEVICE,
974 }, 973 },
975}; 974};
976 975
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 40fec315c99a..5e5b0a7831fb 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -653,8 +653,7 @@ static struct map_desc dm644x_io_desc[] = {
653 .virtual = SRAM_VIRT, 653 .virtual = SRAM_VIRT,
654 .pfn = __phys_to_pfn(0x00008000), 654 .pfn = __phys_to_pfn(0x00008000),
655 .length = SZ_16K, 655 .length = SZ_16K,
656 /* MT_MEMORY_NONCACHED requires supersection alignment */ 656 .type = MT_MEMORY_NONCACHED,
657 .type = MT_DEVICE,
658 }, 657 },
659}; 658};
660 659
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index e4a3df1872ac..26e8a9c7f50b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -737,8 +737,7 @@ static struct map_desc dm646x_io_desc[] = {
737 .virtual = SRAM_VIRT, 737 .virtual = SRAM_VIRT,
738 .pfn = __phys_to_pfn(0x00010000), 738 .pfn = __phys_to_pfn(0x00010000),
739 .length = SZ_32K, 739 .length = SZ_32K,
740 /* MT_MEMORY_NONCACHED requires supersection alignment */ 740 .type = MT_MEMORY_NONCACHED,
741 .type = MT_DEVICE,
742 }, 741 },
743}; 742};
744 743
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
index 3b3e4721ce2e..eb4936ff90ad 100644
--- a/arch/arm/mach-dove/include/mach/io.h
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -13,8 +13,8 @@
13 13
14#define IO_SPACE_LIMIT 0xffffffff 14#define IO_SPACE_LIMIT 0xffffffff
15 15
16#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\ 16#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
17 DOVE_PCIE0_IO_VIRT_BASE)) 17 DOVE_PCIE0_IO_VIRT_BASE))
18#define __mem_pci(a) (a) 18#define __mem_pci(a) (a)
19 19
20#endif 20#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 93fc2ec95e76..6e924b398919 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -38,7 +38,7 @@
38 38
39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
40#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 40#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
41#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00000000 41#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000
42#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M 42#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
43 43
44#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 44#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 55e7f00836b7..513ad3102d7c 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -117,7 +117,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
117 * IORESOURCE_IO 117 * IORESOURCE_IO
118 */ 118 */
119 pp->res[0].name = "PCIe 0 I/O Space"; 119 pp->res[0].name = "PCIe 0 I/O Space";
120 pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE; 120 pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
121 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; 121 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
122 pp->res[0].flags = IORESOURCE_IO; 122 pp->res[0].flags = IORESOURCE_IO;
123 123
@@ -139,7 +139,7 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
139 * IORESOURCE_IO 139 * IORESOURCE_IO
140 */ 140 */
141 pp->res[0].name = "PCIe 1 I/O Space"; 141 pp->res[0].name = "PCIe 1 I/O Space";
142 pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE; 142 pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
143 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; 143 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
144 pp->res[0].flags = IORESOURCE_IO; 144 pp->res[0].flags = IORESOURCE_IO;
145 145
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
index 4f5b0e0ce6cf..1a8a25edb1b4 100644
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -9,6 +9,8 @@
9#ifndef __ASM_MACH_SYSTEM_H 9#ifndef __ASM_MACH_SYSTEM_H
10#define __ASM_MACH_SYSTEM_H 10#define __ASM_MACH_SYSTEM_H
11 11
12#include <mach/cputype.h>
13
12static inline void arch_idle(void) 14static inline void arch_idle(void)
13{ 15{
14 cpu_do_idle(); 16 cpu_do_idle();
@@ -16,6 +18,9 @@ static inline void arch_idle(void)
16 18
17static inline void arch_reset(char mode, const char *cmd) 19static inline void arch_reset(char mode, const char *cmd)
18{ 20{
19 cpu_reset(0); 21 if (cpu_is_pxa168())
22 cpu_reset(0xffff0000);
23 else
24 cpu_reset(0);
20} 25}
21#endif /* __ASM_MACH_SYSTEM_H */ 26#endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 50d5939a78f1..58093d9e07be 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -312,8 +312,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
312 freqs.cpu = policy->cpu; 312 freqs.cpu = policy->cpu;
313 313
314 if (freq_debug) 314 if (freq_debug)
315 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, " 315 pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
316 "(SDRAM %d Mhz)\n",
317 freqs.new / 1000, (pxa_freq_settings[idx].div2) ? 316 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
318 (new_freq_mem / 2000) : (new_freq_mem / 1000)); 317 (new_freq_mem / 2000) : (new_freq_mem / 1000));
319 318
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 428cc7bda9a4..814f1458a06a 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -264,23 +264,35 @@
264 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x 264 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
265 * == 0x3 for pxa300/pxa310/pxa320 265 * == 0x3 for pxa300/pxa310/pxa320
266 */ 266 */
267#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
267#define __cpu_is_pxa2xx(id) \ 268#define __cpu_is_pxa2xx(id) \
268 ({ \ 269 ({ \
269 unsigned int _id = (id) >> 13 & 0x7; \ 270 unsigned int _id = (id) >> 13 & 0x7; \
270 _id <= 0x2; \ 271 _id <= 0x2; \
271 }) 272 })
273#else
274#define __cpu_is_pxa2xx(id) (0)
275#endif
272 276
277#ifdef CONFIG_PXA3xx
273#define __cpu_is_pxa3xx(id) \ 278#define __cpu_is_pxa3xx(id) \
274 ({ \ 279 ({ \
275 unsigned int _id = (id) >> 13 & 0x7; \ 280 unsigned int _id = (id) >> 13 & 0x7; \
276 _id == 0x3; \ 281 _id == 0x3; \
277 }) 282 })
283#else
284#define __cpu_is_pxa3xx(id) (0)
285#endif
278 286
287#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
279#define __cpu_is_pxa93x(id) \ 288#define __cpu_is_pxa93x(id) \
280 ({ \ 289 ({ \
281 unsigned int _id = (id) >> 4 & 0xfff; \ 290 unsigned int _id = (id) >> 4 & 0xfff; \
282 _id == 0x683 || _id == 0x693; \ 291 _id == 0x683 || _id == 0x693; \
283 }) 292 })
293#else
294#define __cpu_is_pxa93x(id) (0)
295#endif
284 296
285#define cpu_is_pxa2xx() \ 297#define cpu_is_pxa2xx() \
286 ({ \ 298 ({ \
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index 77ad6d34ab5b..405b92a29793 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -469,9 +469,13 @@ static struct i2c_board_info __initdata palm27x_pi2c_board_info[] = {
469 }, 469 },
470}; 470};
471 471
472static struct i2c_pxa_platform_data palm27x_i2c_power_info = {
473 .use_pio = 1,
474};
475
472void __init palm27x_pmic_init(void) 476void __init palm27x_pmic_init(void)
473{ 477{
474 i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info)); 478 i2c_register_board_info(1, ARRAY_AND_SIZE(palm27x_pi2c_board_info));
475 pxa27x_set_i2c_power_info(NULL); 479 pxa27x_set_i2c_power_info(&palm27x_i2c_power_info);
476} 480}
477#endif 481#endif
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index c9b747cedea8..37d6173bbb66 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -240,6 +240,7 @@ static void __init vpac270_onenand_init(void) {}
240#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) 240#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
241static struct pxamci_platform_data vpac270_mci_platform_data = { 241static struct pxamci_platform_data vpac270_mci_platform_data = {
242 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, 242 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
243 .gpio_power = -1,
243 .gpio_card_detect = GPIO53_VPAC270_SD_DETECT_N, 244 .gpio_card_detect = GPIO53_VPAC270_SD_DETECT_N,
244 .gpio_card_ro = GPIO52_VPAC270_SD_READONLY, 245 .gpio_card_ro = GPIO52_VPAC270_SD_READONLY,
245 .detect_delay_ms = 200, 246 .detect_delay_ms = 200,
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
index 7b1fc984abb6..d5a71abcbaea 100644
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -273,6 +273,9 @@ extern void gpio_pullup(unsigned gpio, int value);
273extern int gpio_get_value(unsigned gpio); 273extern int gpio_get_value(unsigned gpio);
274extern void gpio_set_value(unsigned gpio, int value); 274extern void gpio_set_value(unsigned gpio, int value);
275 275
276#define gpio_get_value_cansleep gpio_get_value
277#define gpio_set_value_cansleep gpio_set_value
278
276/* wrappers to sleep-enable the previous two functions */ 279/* wrappers to sleep-enable the previous two functions */
277static inline unsigned gpio_to_irq(unsigned gpio) 280static inline unsigned gpio_to_irq(unsigned gpio)
278{ 281{
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 577df6cccb08..efb127022d42 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -227,7 +227,13 @@ static void ct_ca9x4_init(void)
227 int i; 227 int i;
228 228
229#ifdef CONFIG_CACHE_L2X0 229#ifdef CONFIG_CACHE_L2X0
230 l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff); 230 void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
231
232 /* set RAM latencies to 1 cycle for this core tile. */
233 writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
234 writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
235
236 l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
231#endif 237#endif
232 238
233 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 239 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index d073b64ae87e..724ba3bce72c 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -885,8 +885,23 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
885 885
886 if (ai_usermode & UM_SIGNAL) 886 if (ai_usermode & UM_SIGNAL)
887 force_sig(SIGBUS, current); 887 force_sig(SIGBUS, current);
888 else 888 else {
889 set_cr(cr_no_alignment); 889 /*
890 * We're about to disable the alignment trap and return to
891 * user space. But if an interrupt occurs before actually
892 * reaching user space, then the IRQ vector entry code will
893 * notice that we were still in kernel space and therefore
894 * the alignment trap won't be re-enabled in that case as it
895 * is presumed to be always on from kernel space.
896 * Let's prevent that race by disabling interrupts here (they
897 * are disabled on the way back to user space anyway in
898 * entry-common.S) and disable the alignment trap only if
899 * there is no work pending for this thread.
900 */
901 raw_local_irq_disable();
902 if (!(current_thread_info()->flags & _TIF_WORK_MASK))
903 set_cr(cr_no_alignment);
904 }
890 905
891 return 0; 906 return 0;
892} 907}
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6e1c4f6a2b3f..6a3a2d0cd6db 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -15,6 +15,7 @@
15#include <linux/nodemask.h> 15#include <linux/nodemask.h>
16#include <linux/memblock.h> 16#include <linux/memblock.h>
17#include <linux/sort.h> 17#include <linux/sort.h>
18#include <linux/fs.h>
18 19
19#include <asm/cputype.h> 20#include <asm/cputype.h>
20#include <asm/sections.h> 21#include <asm/sections.h>
@@ -246,6 +247,9 @@ static struct mem_type mem_types[] = {
246 .domain = DOMAIN_USER, 247 .domain = DOMAIN_USER,
247 }, 248 },
248 [MT_MEMORY] = { 249 [MT_MEMORY] = {
250 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
251 L_PTE_USER | L_PTE_EXEC,
252 .prot_l1 = PMD_TYPE_TABLE,
249 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 253 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
250 .domain = DOMAIN_KERNEL, 254 .domain = DOMAIN_KERNEL,
251 }, 255 },
@@ -254,6 +258,9 @@ static struct mem_type mem_types[] = {
254 .domain = DOMAIN_KERNEL, 258 .domain = DOMAIN_KERNEL,
255 }, 259 },
256 [MT_MEMORY_NONCACHED] = { 260 [MT_MEMORY_NONCACHED] = {
261 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
262 L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
263 .prot_l1 = PMD_TYPE_TABLE,
257 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 264 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
258 .domain = DOMAIN_KERNEL, 265 .domain = DOMAIN_KERNEL,
259 }, 266 },
@@ -411,9 +418,12 @@ static void __init build_mem_type_table(void)
411 * Enable CPU-specific coherency if supported. 418 * Enable CPU-specific coherency if supported.
412 * (Only available on XSC3 at the moment.) 419 * (Only available on XSC3 at the moment.)
413 */ 420 */
414 if (arch_is_coherent() && cpu_is_xsc3()) 421 if (arch_is_coherent() && cpu_is_xsc3()) {
415 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 422 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
416 423 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
424 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
425 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
426 }
417 /* 427 /*
418 * ARMv6 and above have extended page tables. 428 * ARMv6 and above have extended page tables.
419 */ 429 */
@@ -438,7 +448,9 @@ static void __init build_mem_type_table(void)
438 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 448 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
439 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 449 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
440 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 450 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
451 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
441 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; 452 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
453 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
442#endif 454#endif
443 } 455 }
444 456
@@ -475,6 +487,8 @@ static void __init build_mem_type_table(void)
475 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 487 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
476 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 488 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
477 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; 489 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
490 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
491 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
478 mem_types[MT_ROM].prot_sect |= cp->pmd; 492 mem_types[MT_ROM].prot_sect |= cp->pmd;
479 493
480 switch (cp->pmd) { 494 switch (cp->pmd) {
@@ -498,6 +512,19 @@ static void __init build_mem_type_table(void)
498 } 512 }
499} 513}
500 514
515#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
516pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
517 unsigned long size, pgprot_t vma_prot)
518{
519 if (!pfn_valid(pfn))
520 return pgprot_noncached(vma_prot);
521 else if (file->f_flags & O_SYNC)
522 return pgprot_writecombine(vma_prot);
523 return vma_prot;
524}
525EXPORT_SYMBOL(phys_mem_access_prot);
526#endif
527
501#define vectors_base() (vectors_high() ? 0xffff0000 : 0) 528#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
502 529
503static void __init *early_alloc(unsigned long sz) 530static void __init *early_alloc(unsigned long sz)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d99ee9..7563ff0141bd 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -186,13 +186,14 @@ cpu_v7_name:
186 * It is assumed that: 186 * It is assumed that:
187 * - cache type register is implemented 187 * - cache type register is implemented
188 */ 188 */
189__v7_setup: 189__v7_ca9mp_setup:
190#ifdef CONFIG_SMP 190#ifdef CONFIG_SMP
191 mrc p15, 0, r0, c1, c0, 1 191 mrc p15, 0, r0, c1, c0, 1
192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and 193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
195#endif 195#endif
196__v7_setup:
196 adr r12, __v7_setup_stack @ the local stack 197 adr r12, __v7_setup_stack @ the local stack
197 stmia r12, {r0-r5, r7, r9, r11, lr} 198 stmia r12, {r0-r5, r7, r9, r11, lr}
198 bl v7_flush_dcache_all 199 bl v7_flush_dcache_all
@@ -201,11 +202,16 @@ __v7_setup:
201 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 202 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
202 and r10, r0, #0xff000000 @ ARM? 203 and r10, r0, #0xff000000 @ ARM?
203 teq r10, #0x41000000 204 teq r10, #0x41000000
204 bne 2f 205 bne 3f
205 and r5, r0, #0x00f00000 @ variant 206 and r5, r0, #0x00f00000 @ variant
206 and r6, r0, #0x0000000f @ revision 207 and r6, r0, #0x0000000f @ revision
207 orr r0, r6, r5, lsr #20-4 @ combine variant and revision 208 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
209 ubfx r0, r0, #4, #12 @ primary part number
208 210
211 /* Cortex-A8 Errata */
212 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
213 teq r0, r10
214 bne 2f
209#ifdef CONFIG_ARM_ERRATA_430973 215#ifdef CONFIG_ARM_ERRATA_430973
210 teq r5, #0x00100000 @ only present in r1p* 216 teq r5, #0x00100000 @ only present in r1p*
211 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 217 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
@@ -213,21 +219,42 @@ __v7_setup:
213 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 219 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
214#endif 220#endif
215#ifdef CONFIG_ARM_ERRATA_458693 221#ifdef CONFIG_ARM_ERRATA_458693
216 teq r0, #0x20 @ only present in r2p0 222 teq r6, #0x20 @ only present in r2p0
217 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 223 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
218 orreq r10, r10, #(1 << 5) @ set L1NEON to 1 224 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
219 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 225 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
220 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 226 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
221#endif 227#endif
222#ifdef CONFIG_ARM_ERRATA_460075 228#ifdef CONFIG_ARM_ERRATA_460075
223 teq r0, #0x20 @ only present in r2p0 229 teq r6, #0x20 @ only present in r2p0
224 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 230 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
225 tsteq r10, #1 << 22 231 tsteq r10, #1 << 22
226 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 232 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
227 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 233 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
228#endif 234#endif
235 b 3f
236
237 /* Cortex-A9 Errata */
2382: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
239 teq r0, r10
240 bne 3f
241#ifdef CONFIG_ARM_ERRATA_742230
242 cmp r6, #0x22 @ only present up to r2p2
243 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
244 orrle r10, r10, #1 << 4 @ set bit #4
245 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
246#endif
247#ifdef CONFIG_ARM_ERRATA_742231
248 teq r6, #0x20 @ present in r2p0
249 teqne r6, #0x21 @ present in r2p1
250 teqne r6, #0x22 @ present in r2p2
251 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
252 orreq r10, r10, #1 << 12 @ set bit #12
253 orreq r10, r10, #1 << 22 @ set bit #22
254 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
255#endif
229 256
2302: mov r10, #0 2573: mov r10, #0
231#ifdef HARVARD_CACHE 258#ifdef HARVARD_CACHE
232 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 259 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
233#endif 260#endif
@@ -323,6 +350,29 @@ cpu_elf_name:
323 350
324 .section ".proc.info.init", #alloc, #execinstr 351 .section ".proc.info.init", #alloc, #execinstr
325 352
353 .type __v7_ca9mp_proc_info, #object
354__v7_ca9mp_proc_info:
355 .long 0x410fc090 @ Required ID value
356 .long 0xff0ffff0 @ Mask for ID
357 .long PMD_TYPE_SECT | \
358 PMD_SECT_AP_WRITE | \
359 PMD_SECT_AP_READ | \
360 PMD_FLAGS
361 .long PMD_TYPE_SECT | \
362 PMD_SECT_XN | \
363 PMD_SECT_AP_WRITE | \
364 PMD_SECT_AP_READ
365 b __v7_ca9mp_setup
366 .long cpu_arch_name
367 .long cpu_elf_name
368 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
369 .long cpu_v7_name
370 .long v7_processor_functions
371 .long v7wbi_tlb_fns
372 .long v6_user_fns
373 .long v7_cache_fns
374 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
375
326 /* 376 /*
327 * Match any ARMv7 processor core. 377 * Match any ARMv7 processor core.
328 */ 378 */
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index ea3ca86c5283..aedf9c1d645e 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-nomadik/timer.c 2 * linux/arch/arm/plat-nomadik/timer.c
3 * 3 *
4 * Copyright (C) 2008 STMicroelectronics 4 * Copyright (C) 2008 STMicroelectronics
5 * Copyright (C) 2010 Alessandro Rubini 5 * Copyright (C) 2010 Alessandro Rubini
@@ -75,7 +75,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
75 cr = readl(mtu_base + MTU_CR(1)); 75 cr = readl(mtu_base + MTU_CR(1));
76 writel(0, mtu_base + MTU_LR(1)); 76 writel(0, mtu_base + MTU_LR(1));
77 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1)); 77 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
78 writel(0x2, mtu_base + MTU_IMSC); 78 writel(1 << 1, mtu_base + MTU_IMSC);
79 break; 79 break;
80 case CLOCK_EVT_MODE_SHUTDOWN: 80 case CLOCK_EVT_MODE_SHUTDOWN:
81 case CLOCK_EVT_MODE_UNUSED: 81 case CLOCK_EVT_MODE_UNUSED:
@@ -131,25 +131,23 @@ void __init nmdk_timer_init(void)
131{ 131{
132 unsigned long rate; 132 unsigned long rate;
133 struct clk *clk0; 133 struct clk *clk0;
134 struct clk *clk1; 134 u32 cr = MTU_CRn_32BITS;
135 u32 cr;
136 135
137 clk0 = clk_get_sys("mtu0", NULL); 136 clk0 = clk_get_sys("mtu0", NULL);
138 BUG_ON(IS_ERR(clk0)); 137 BUG_ON(IS_ERR(clk0));
139 138
140 clk1 = clk_get_sys("mtu1", NULL);
141 BUG_ON(IS_ERR(clk1));
142
143 clk_enable(clk0); 139 clk_enable(clk0);
144 clk_enable(clk1);
145 140
146 /* 141 /*
147 * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500: 142 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
148 * use a divide-by-16 counter if it's more than 16MHz 143 * for ux500.
144 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
145 * At 32 MHz, the timer (with 32 bit counter) can be programmed
146 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
147 * with 16 gives too low timer resolution.
149 */ 148 */
150 cr = MTU_CRn_32BITS;;
151 rate = clk_get_rate(clk0); 149 rate = clk_get_rate(clk0);
152 if (rate > 16 << 20) { 150 if (rate > 32000000) {
153 rate /= 16; 151 rate /= 16;
154 cr |= MTU_CRn_PRESCALE_16; 152 cr |= MTU_CRn_PRESCALE_16;
155 } else { 153 } else {
@@ -170,15 +168,8 @@ void __init nmdk_timer_init(void)
170 pr_err("timer: failed to initialize clock source %s\n", 168 pr_err("timer: failed to initialize clock source %s\n",
171 nmdk_clksrc.name); 169 nmdk_clksrc.name);
172 170
173 /* Timer 1 is used for events, fix according to rate */ 171 /* Timer 1 is used for events */
174 cr = MTU_CRn_32BITS; 172
175 rate = clk_get_rate(clk1);
176 if (rate > 16 << 20) {
177 rate /= 16;
178 cr |= MTU_CRn_PRESCALE_16;
179 } else {
180 cr |= MTU_CRn_PRESCALE_1;
181 }
182 clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE); 173 clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
183 174
184 writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ 175 writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 226b2e858d6c..10b3b4c63372 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -220,20 +220,7 @@ void __init omap_map_sram(void)
220 if (omap_sram_size == 0) 220 if (omap_sram_size == 0)
221 return; 221 return;
222 222
223 if (cpu_is_omap24xx()) {
224 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
225
226 base = OMAP2_SRAM_PA;
227 base = ROUND_DOWN(base, PAGE_SIZE);
228 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
229 }
230
231 if (cpu_is_omap34xx()) { 223 if (cpu_is_omap34xx()) {
232 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
233 base = OMAP3_SRAM_PA;
234 base = ROUND_DOWN(base, PAGE_SIZE);
235 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
236
237 /* 224 /*
238 * SRAM must be marked as non-cached on OMAP3 since the 225 * SRAM must be marked as non-cached on OMAP3 since the
239 * CORE DPLL M2 divider change code (in SRAM) runs with the 226 * CORE DPLL M2 divider change code (in SRAM) runs with the
@@ -244,13 +231,11 @@ void __init omap_map_sram(void)
244 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; 231 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
245 } 232 }
246 233
247 if (cpu_is_omap44xx()) { 234 omap_sram_io_desc[0].virtual = omap_sram_base;
248 omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA; 235 base = omap_sram_start;
249 base = OMAP4_SRAM_PA; 236 base = ROUND_DOWN(base, PAGE_SIZE);
250 base = ROUND_DOWN(base, PAGE_SIZE); 237 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
251 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 238 omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
252 }
253 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
254 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); 239 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
255 240
256 printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n", 241 printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 86c5ae9fde34..411d5bf50fc4 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -162,7 +162,7 @@ static int mv_is_err_intr(u32 intr_cause)
162 162
163static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) 163static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
164{ 164{
165 u32 val = (1 << (1 + (chan->idx * 16))); 165 u32 val = ~(1 << (chan->idx * 16));
166 dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val); 166 dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
167 __raw_writel(val, XOR_INTR_CAUSE(chan)); 167 __raw_writel(val, XOR_INTR_CAUSE(chan));
168} 168}
diff --git a/drivers/leds/leds-ns2.c b/drivers/leds/leds-ns2.c
index 74dce4ba0262..350eb34f049c 100644
--- a/drivers/leds/leds-ns2.c
+++ b/drivers/leds/leds-ns2.c
@@ -81,7 +81,7 @@ static int ns2_led_get_mode(struct ns2_led_data *led_dat,
81 int cmd_level; 81 int cmd_level;
82 int slow_level; 82 int slow_level;
83 83
84 read_lock(&led_dat->rw_lock); 84 read_lock_irq(&led_dat->rw_lock);
85 85
86 cmd_level = gpio_get_value(led_dat->cmd); 86 cmd_level = gpio_get_value(led_dat->cmd);
87 slow_level = gpio_get_value(led_dat->slow); 87 slow_level = gpio_get_value(led_dat->slow);
@@ -95,7 +95,7 @@ static int ns2_led_get_mode(struct ns2_led_data *led_dat,
95 } 95 }
96 } 96 }
97 97
98 read_unlock(&led_dat->rw_lock); 98 read_unlock_irq(&led_dat->rw_lock);
99 99
100 return ret; 100 return ret;
101} 101}
@@ -104,8 +104,9 @@ static void ns2_led_set_mode(struct ns2_led_data *led_dat,
104 enum ns2_led_modes mode) 104 enum ns2_led_modes mode)
105{ 105{
106 int i; 106 int i;
107 unsigned long flags;
107 108
108 write_lock(&led_dat->rw_lock); 109 write_lock_irqsave(&led_dat->rw_lock, flags);
109 110
110 for (i = 0; i < ARRAY_SIZE(ns2_led_modval); i++) { 111 for (i = 0; i < ARRAY_SIZE(ns2_led_modval); i++) {
111 if (mode == ns2_led_modval[i].mode) { 112 if (mode == ns2_led_modval[i].mode) {
@@ -116,7 +117,7 @@ static void ns2_led_set_mode(struct ns2_led_data *led_dat,
116 } 117 }
117 } 118 }
118 119
119 write_unlock(&led_dat->rw_lock); 120 write_unlock_irqrestore(&led_dat->rw_lock, flags);
120} 121}
121 122
122static void ns2_led_set(struct led_classdev *led_cdev, 123static void ns2_led_set(struct led_classdev *led_cdev,
diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c
index 5d786bd3e304..a31a77ff6f3d 100644
--- a/drivers/video/pxa168fb.c
+++ b/drivers/video/pxa168fb.c
@@ -298,8 +298,8 @@ static void set_dma_control0(struct pxa168fb_info *fbi)
298 * Set bit to enable graphics DMA. 298 * Set bit to enable graphics DMA.
299 */ 299 */
300 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); 300 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
301 x |= fbi->active ? 0x00000100 : 0; 301 x &= ~CFG_GRA_ENA_MASK;
302 fbi->active = 0; 302 x |= fbi->active ? CFG_GRA_ENA(1) : CFG_GRA_ENA(0);
303 303
304 /* 304 /*
305 * If we are in a pseudo-color mode, we need to enable 305 * If we are in a pseudo-color mode, we need to enable
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 05:51:38 -0500