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authorKukjin Kim <kgene.kim@samsung.com>2010-09-08 03:23:05 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-18 05:33:03 -0400
commit5dd33d89f4700990e00731a971754ecb08ab7022 (patch)
tree29ce0642e6af90d92477db7c276c99e0956b41d8
parent2853a0efc3031dec88b47bbc50b8a6b3fe9e3cac (diff)
ARM: S5P64X0: Move GPIO support files for merge S5P64X0
This patch moves S5P6440 GPIO support files from mach-s5p6440 into the new mach-s5p64x0 for merge S5P6440 and S5P6450 SocS. NOTE: Not supported S5P6450 GPIO yet. Will be supported soon. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-s5p6440/include/mach/gpio.h80
-rw-r--r--arch/arm/mach-s5p64x0/gpio.c (renamed from arch/arm/mach-s5p6440/gpio.c)99
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/gpio.h139
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h (renamed from arch/arm/mach-s5p6440/include/mach/regs-gpio.h)28
4 files changed, 208 insertions, 138 deletions
diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h
deleted file mode 100644
index 21783834f2a2..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/gpio.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22#define S5P6440_GPIO_A_NR (6)
23#define S5P6440_GPIO_B_NR (7)
24#define S5P6440_GPIO_C_NR (8)
25#define S5P6440_GPIO_F_NR (2)
26#define S5P6440_GPIO_G_NR (7)
27#define S5P6440_GPIO_H_NR (10)
28#define S5P6440_GPIO_I_NR (16)
29#define S5P6440_GPIO_J_NR (12)
30#define S5P6440_GPIO_N_NR (16)
31#define S5P6440_GPIO_P_NR (8)
32#define S5P6440_GPIO_R_NR (15)
33
34/* GPIO bank numbers */
35
36/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
37 * space for debugging purposes so that any accidental
38 * change from one gpio bank to another can be caught.
39*/
40#define S5P6440_GPIO_NEXT(__gpio) \
41 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
42
43enum s5p_gpio_number {
44 S5P6440_GPIO_A_START = 0,
45 S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A),
46 S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B),
47 S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C),
48 S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F),
49 S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G),
50 S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H),
51 S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I),
52 S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J),
53 S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N),
54 S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P),
55};
56
57/* S5P6440 GPIO number definitions. */
58#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
59#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
60#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
61#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
62#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
63#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
64#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
65#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
66#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
67#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
68#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
69
70/* the end of the S5P6440 specific gpios */
71#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
72#define S3C_GPIO_END S5P6440_GPIO_END
73
74/* define the number of gpios we need to the one after the GPR() range */
75#define ARCH_NR_GPIOS (S5P6440_GPR(S5P6440_GPIO_R_NR) + \
76 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
77
78#include <asm-generic/gpio.h>
79
80#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p64x0/gpio.c
index 8bf6e0ce51c9..131eefe0c9f2 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p64x0/gpio.c
@@ -1,14 +1,14 @@
1/* arch/arm/mach-s5p6440/gpio.c 1/* linux/arch/arm/mach-s5p64x0/gpio.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - GPIOlib support 6 * S5P64X0 - GPIOlib support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11*/
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/irq.h> 14#include <linux/irq.h>
@@ -22,26 +22,29 @@
22#include <plat/gpio-cfg.h> 22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h> 23#include <plat/gpio-cfg-helpers.h>
24 24
25/* GPIO bank summary: 25/* To be implemented S5P6450 GPIO */
26* 26
27* Bank GPIOs Style SlpCon ExtInt Group 27/*
28* A 6 4Bit Yes 1 28 * S5P6440 GPIO bank summary:
29* B 7 4Bit Yes 1 29 *
30* C 8 4Bit Yes 2 30 * Bank GPIOs Style SlpCon ExtInt Group
31* F 2 2Bit Yes 4 [1] 31 * A 6 4Bit Yes 1
32* G 7 4Bit Yes 5 32 * B 7 4Bit Yes 1
33* H 10 4Bit[2] Yes 6 33 * C 8 4Bit Yes 2
34* I 16 2Bit Yes None 34 * F 2 2Bit Yes 4 [1]
35* J 12 2Bit Yes None 35 * G 7 4Bit Yes 5
36* N 16 2Bit No IRQ_EINT 36 * H 10 4Bit[2] Yes 6
37* P 8 2Bit Yes 8 37 * I 16 2Bit Yes None
38* R 15 4Bit[2] Yes 8 38 * J 12 2Bit Yes None
39* 39 * N 16 2Bit No IRQ_EINT
40* [1] BANKF pins 14,15 do not form part of the external interrupt sources 40 * P 8 2Bit Yes 8
41* [2] BANK has two control registers, GPxCON0 and GPxCON1 41 * R 15 4Bit[2] Yes 8
42*/ 42 *
43 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
44 * [2] BANK has two control registers, GPxCON0 and GPxCON1
45 */
43 46
44static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, 47static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
45 unsigned int offset) 48 unsigned int offset)
46{ 49{
47 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); 50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -77,7 +80,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
77 return 0; 80 return 0;
78} 81}
79 82
80static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, 83static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
81 unsigned int offset, int value) 84 unsigned int offset, int value)
82{ 85{
83 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); 86 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -124,7 +127,7 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
124 return 0; 127 return 0;
125} 128}
126 129
127int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, 130int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
128 unsigned int off, unsigned int cfg) 131 unsigned int off, unsigned int cfg)
129{ 132{
130 void __iomem *reg = chip->base; 133 void __iomem *reg = chip->base;
@@ -167,14 +170,14 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
167 return 0; 170 return 0;
168} 171}
169 172
170static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = { 173static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
171 { 174 {
172 .cfg_eint = 0, 175 .cfg_eint = 0,
173 }, { 176 }, {
174 .cfg_eint = 7, 177 .cfg_eint = 7,
175 }, { 178 }, {
176 .cfg_eint = 3, 179 .cfg_eint = 3,
177 .set_config = s5p6440_gpio_setcfg_4bit_rbank, 180 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
178 }, { 181 }, {
179 .cfg_eint = 0, 182 .cfg_eint = 0,
180 .set_config = s3c_gpio_setcfg_s3c24xx, 183 .set_config = s3c_gpio_setcfg_s3c24xx,
@@ -193,7 +196,7 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
193static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { 196static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
194 { 197 {
195 .base = S5P6440_GPA_BASE, 198 .base = S5P6440_GPA_BASE,
196 .config = &s5p6440_gpio_cfgs[1], 199 .config = &s5p64x0_gpio_cfgs[1],
197 .chip = { 200 .chip = {
198 .base = S5P6440_GPA(0), 201 .base = S5P6440_GPA(0),
199 .ngpio = S5P6440_GPIO_A_NR, 202 .ngpio = S5P6440_GPIO_A_NR,
@@ -201,7 +204,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
201 }, 204 },
202 }, { 205 }, {
203 .base = S5P6440_GPB_BASE, 206 .base = S5P6440_GPB_BASE,
204 .config = &s5p6440_gpio_cfgs[1], 207 .config = &s5p64x0_gpio_cfgs[1],
205 .chip = { 208 .chip = {
206 .base = S5P6440_GPB(0), 209 .base = S5P6440_GPB(0),
207 .ngpio = S5P6440_GPIO_B_NR, 210 .ngpio = S5P6440_GPIO_B_NR,
@@ -209,7 +212,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
209 }, 212 },
210 }, { 213 }, {
211 .base = S5P6440_GPC_BASE, 214 .base = S5P6440_GPC_BASE,
212 .config = &s5p6440_gpio_cfgs[1], 215 .config = &s5p64x0_gpio_cfgs[1],
213 .chip = { 216 .chip = {
214 .base = S5P6440_GPC(0), 217 .base = S5P6440_GPC(0),
215 .ngpio = S5P6440_GPIO_C_NR, 218 .ngpio = S5P6440_GPIO_C_NR,
@@ -217,7 +220,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
217 }, 220 },
218 }, { 221 }, {
219 .base = S5P6440_GPG_BASE, 222 .base = S5P6440_GPG_BASE,
220 .config = &s5p6440_gpio_cfgs[1], 223 .config = &s5p64x0_gpio_cfgs[1],
221 .chip = { 224 .chip = {
222 .base = S5P6440_GPG(0), 225 .base = S5P6440_GPG(0),
223 .ngpio = S5P6440_GPIO_G_NR, 226 .ngpio = S5P6440_GPIO_G_NR,
@@ -229,7 +232,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
229static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { 232static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
230 { 233 {
231 .base = S5P6440_GPH_BASE + 0x4, 234 .base = S5P6440_GPH_BASE + 0x4,
232 .config = &s5p6440_gpio_cfgs[1], 235 .config = &s5p64x0_gpio_cfgs[1],
233 .chip = { 236 .chip = {
234 .base = S5P6440_GPH(0), 237 .base = S5P6440_GPH(0),
235 .ngpio = S5P6440_GPIO_H_NR, 238 .ngpio = S5P6440_GPIO_H_NR,
@@ -238,10 +241,10 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
238 }, 241 },
239}; 242};
240 243
241static struct s3c_gpio_chip gpio_rbank_4bit2[] = { 244static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
242 { 245 {
243 .base = S5P6440_GPR_BASE + 0x4, 246 .base = S5P6440_GPR_BASE + 0x4,
244 .config = &s5p6440_gpio_cfgs[2], 247 .config = &s5p64x0_gpio_cfgs[2],
245 .chip = { 248 .chip = {
246 .base = S5P6440_GPR(0), 249 .base = S5P6440_GPR(0),
247 .ngpio = S5P6440_GPIO_R_NR, 250 .ngpio = S5P6440_GPIO_R_NR,
@@ -253,7 +256,7 @@ static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
253static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { 256static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
254 { 257 {
255 .base = S5P6440_GPF_BASE, 258 .base = S5P6440_GPF_BASE,
256 .config = &s5p6440_gpio_cfgs[5], 259 .config = &s5p64x0_gpio_cfgs[5],
257 .chip = { 260 .chip = {
258 .base = S5P6440_GPF(0), 261 .base = S5P6440_GPF(0),
259 .ngpio = S5P6440_GPIO_F_NR, 262 .ngpio = S5P6440_GPIO_F_NR,
@@ -261,7 +264,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
261 }, 264 },
262 }, { 265 }, {
263 .base = S5P6440_GPI_BASE, 266 .base = S5P6440_GPI_BASE,
264 .config = &s5p6440_gpio_cfgs[3], 267 .config = &s5p64x0_gpio_cfgs[3],
265 .chip = { 268 .chip = {
266 .base = S5P6440_GPI(0), 269 .base = S5P6440_GPI(0),
267 .ngpio = S5P6440_GPIO_I_NR, 270 .ngpio = S5P6440_GPIO_I_NR,
@@ -269,7 +272,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
269 }, 272 },
270 }, { 273 }, {
271 .base = S5P6440_GPJ_BASE, 274 .base = S5P6440_GPJ_BASE,
272 .config = &s5p6440_gpio_cfgs[3], 275 .config = &s5p64x0_gpio_cfgs[3],
273 .chip = { 276 .chip = {
274 .base = S5P6440_GPJ(0), 277 .base = S5P6440_GPJ(0),
275 .ngpio = S5P6440_GPIO_J_NR, 278 .ngpio = S5P6440_GPIO_J_NR,
@@ -277,7 +280,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
277 }, 280 },
278 }, { 281 }, {
279 .base = S5P6440_GPN_BASE, 282 .base = S5P6440_GPN_BASE,
280 .config = &s5p6440_gpio_cfgs[4], 283 .config = &s5p64x0_gpio_cfgs[4],
281 .chip = { 284 .chip = {
282 .base = S5P6440_GPN(0), 285 .base = S5P6440_GPN(0),
283 .ngpio = S5P6440_GPIO_N_NR, 286 .ngpio = S5P6440_GPIO_N_NR,
@@ -285,7 +288,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
285 }, 288 },
286 }, { 289 }, {
287 .base = S5P6440_GPP_BASE, 290 .base = S5P6440_GPP_BASE,
288 .config = &s5p6440_gpio_cfgs[5], 291 .config = &s5p64x0_gpio_cfgs[5],
289 .chip = { 292 .chip = {
290 .base = S5P6440_GPP(0), 293 .base = S5P6440_GPP(0),
291 .ngpio = S5P6440_GPIO_P_NR, 294 .ngpio = S5P6440_GPIO_P_NR,
@@ -294,7 +297,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
294 }, 297 },
295}; 298};
296 299
297void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) 300void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
298{ 301{
299 for (; nr_chips > 0; nr_chips--, chipcfg++) { 302 for (; nr_chips > 0; nr_chips--, chipcfg++) {
300 if (!chipcfg->set_config) 303 if (!chipcfg->set_config)
@@ -308,13 +311,13 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
308 } 311 }
309} 312}
310 313
311static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, 314static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
312 int nr_chips) 315 int nr_chips)
313{ 316{
314 for (; nr_chips > 0; nr_chips--, chip++) { 317 for (; nr_chips > 0; nr_chips--, chip++) {
315 chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input; 318 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
316 chip->chip.direction_output = 319 chip->chip.direction_output =
317 s5p6440_gpiolib_rbank_4bit2_output; 320 s5p64x0_gpiolib_rbank_4bit2_output;
318 s3c_gpiolib_add(chip); 321 s3c_gpiolib_add(chip);
319 } 322 }
320} 323}
@@ -324,8 +327,8 @@ static int __init s5p6440_gpiolib_init(void)
324 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; 327 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
325 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); 328 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
326 329
327 s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs, 330 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
328 ARRAY_SIZE(s5p6440_gpio_cfgs)); 331 ARRAY_SIZE(s5p64x0_gpio_cfgs));
329 332
330 for (; nr_chips > 0; nr_chips--, chips++) 333 for (; nr_chips > 0; nr_chips--, chips++)
331 s3c_gpiolib_add(chips); 334 s3c_gpiolib_add(chips);
@@ -336,8 +339,8 @@ static int __init s5p6440_gpiolib_init(void)
336 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, 339 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
337 ARRAY_SIZE(s5p6440_gpio_4bit2)); 340 ARRAY_SIZE(s5p6440_gpio_4bit2));
338 341
339 s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2, 342 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
340 ARRAY_SIZE(gpio_rbank_4bit2)); 343 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
341 344
342 return 0; 345 return 0;
343} 346}
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
new file mode 100644
index 000000000000..5486c8f01f1d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -0,0 +1,139 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22
23#define S5P6440_GPIO_A_NR (6)
24#define S5P6440_GPIO_B_NR (7)
25#define S5P6440_GPIO_C_NR (8)
26#define S5P6440_GPIO_F_NR (2)
27#define S5P6440_GPIO_G_NR (7)
28#define S5P6440_GPIO_H_NR (10)
29#define S5P6440_GPIO_I_NR (16)
30#define S5P6440_GPIO_J_NR (12)
31#define S5P6440_GPIO_N_NR (16)
32#define S5P6440_GPIO_P_NR (8)
33#define S5P6440_GPIO_R_NR (15)
34
35#define S5P6450_GPIO_A_NR (6)
36#define S5P6450_GPIO_B_NR (7)
37#define S5P6450_GPIO_C_NR (8)
38#define S5P6450_GPIO_D_NR (8)
39#define S5P6450_GPIO_F_NR (2)
40#define S5P6450_GPIO_G_NR (14)
41#define S5P6450_GPIO_H_NR (10)
42#define S5P6450_GPIO_I_NR (16)
43#define S5P6450_GPIO_J_NR (12)
44#define S5P6450_GPIO_K_NR (5)
45#define S5P6450_GPIO_N_NR (16)
46#define S5P6450_GPIO_P_NR (11)
47#define S5P6450_GPIO_Q_NR (14)
48#define S5P6450_GPIO_R_NR (15)
49#define S5P6450_GPIO_S_NR (8)
50
51/* GPIO bank numbers */
52
53/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
54 * space for debugging purposes so that any accidental
55 * change from one gpio bank to another can be caught.
56*/
57
58#define S5P64X0_GPIO_NEXT(__gpio) \
59 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
60
61enum s5p6440_gpio_number {
62 S5P6440_GPIO_A_START = 0,
63 S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
64 S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
65 S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
66 S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
67 S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
68 S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
69 S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
70 S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
71 S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
72 S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
73};
74
75enum s5p6450_gpio_number {
76 S5P6450_GPIO_A_START = 0,
77 S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
78 S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
79 S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
80 S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
81 S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
82 S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
83 S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
84 S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
85 S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
86 S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
87 S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
88 S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
89 S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
90 S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
91};
92
93/* GPIO number definitions */
94
95#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
96#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
97#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
98#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
99#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
100#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
101#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
102#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
103#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
104#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
105#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
106
107#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
108#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
109#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
110#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
111#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
112#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
113#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
114#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
115#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
116#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
117#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
118#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
119#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
120#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
121#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
122
123/* the end of the S5P64X0 specific gpios */
124
125#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
126#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
127
128#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
129 S5P6440_GPIO_END : S5P6450_GPIO_END)
130
131#define S3C_GPIO_END S5P64X0_GPIO_END
132
133/* define the number of gpios we need to the one after the last GPIO range */
134
135#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
136
137#include <asm-generic/gpio.h>
138
139#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 82ff753913da..85f448e20a8b 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -1,21 +1,24 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - GPIO register definitions 6 * S5P64X0 - GPIO register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11*/
12 12
13#ifndef __ASM_ARCH_REGS_GPIO_H 13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__ 14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15 15
16#include <mach/map.h> 16#include <mach/map.h>
17 17
18/* Will be implemented S5P6442 GPIOlib */
19
18/* Base addresses for each of the banks */ 20/* Base addresses for each of the banks */
21
19#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) 22#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000)
20#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) 23#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020)
21#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) 24#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040)
@@ -27,6 +30,7 @@
27#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) 30#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830)
28#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) 31#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160)
29#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) 32#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290)
33
30#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) 34#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900)
31#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) 35#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910)
32#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) 36#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914)
@@ -34,19 +38,23 @@
34#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924) 38#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924)
35 39
36/* for LCD */ 40/* for LCD */
41
37#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0) 42#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0)
38#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0) 43#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0)
39 44
40/* These set of macros are not really useful for the 45/*
41 * GPF/GPI/GPJ/GPN/GPP, 46 * These set of macros are not really useful for the
42 * useful for others set of GPIO's (4 bit) 47 * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
43 */ 48 */
49
44#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4)) 50#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4))
45#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4)) 51#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4))
46#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) 52#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
47 53
48/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit) 54/*
49 * */ 55 * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
56 */
57
50#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) 58#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
51#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2)) 59#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2))
52#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) 60#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 15:43:06 -0500