diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-07 15:00:25 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-07 15:00:25 -0500 |
| commit | 5bb47b9ff3d16d40f8d45380b373497a545fa280 (patch) | |
| tree | e13dd34395473342dc75eff5cbaf5b1ea753631c | |
| parent | 2f2408a88cf8fa43febfd7fb5783e61b2937b0f9 (diff) | |
| parent | 06af15e086e39a5a2a2413973a64af8e10122f28 (diff) | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (171 commits)
Blackfin arch: fix bug - BF527 0.2 silicon has different CPUID (DSPID) value
Blackfin arch: Enlarge flash partition for kenel for bf533/bf537 boards
Blackfin arch: fix bug: kernel crash when enable SDIO host driver
Blackfin arch: Print FP at level KERN_NOTICE
Blackfin arch: drop ad73311 test code
Blackfin arch: update board default configs
Blackfin arch: Set PB4 as the default irq for bf548 board v1.4+.
Blackfin arch: fix typo in early printk bit size processing
Blackfin arch: enable reprogram cclk and sclk for bf518f-ezbrd
Blackfin arch: add SDIO host driver platform data
Blackfin arch: fix bug - kernel stops at initial console
Blackfin arch: fix bug - kernel crash after config IP for ethernet port
Blackfin arch: add sdh support for bf518f-ezbrd
Blackfin arch: fix bug - kernel detects BF532 incorrectly
Blackfin arch: add () to avoid warnings from gcc
Blackfin arch: change HWTRACE Kconfig and set it on default
Blackfin arch: Clean oprofile build path for blackfin
Blackfin arch: remove hardware PM code, oprofile not use it
Blackfin arch: rewrite get_sclk()/get_vco()
Blackfin arch: cleanup and unify the ins functions
...
270 files changed, 30818 insertions, 9970 deletions
diff --git a/Documentation/blackfin/00-INDEX b/Documentation/blackfin/00-INDEX index 7cb3b356b249..d6840a91e1e1 100644 --- a/Documentation/blackfin/00-INDEX +++ b/Documentation/blackfin/00-INDEX | |||
| @@ -9,3 +9,6 @@ cachefeatures.txt | |||
| 9 | 9 | ||
| 10 | Filesystems | 10 | Filesystems |
| 11 | - Requirements for mounting the root file system. | 11 | - Requirements for mounting the root file system. |
| 12 | |||
| 13 | bfin-gpio-note.txt | ||
| 14 | - Notes in developing/using bfin-gpio driver. | ||
diff --git a/Documentation/blackfin/bfin-gpio-notes.txt b/Documentation/blackfin/bfin-gpio-notes.txt new file mode 100644 index 000000000000..9898c7ded7d3 --- /dev/null +++ b/Documentation/blackfin/bfin-gpio-notes.txt | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | /* | ||
| 2 | * File: Documentation/blackfin/bfin-gpio-note.txt | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: $Id: bfin-gpio-note.txt 2008-11-24 16:42 grafyang $ | ||
| 7 | * Description: This file contains the notes in developing/using bfin-gpio. | ||
| 8 | * | ||
| 9 | * | ||
| 10 | * Rev: | ||
| 11 | * | ||
| 12 | * Modified: | ||
| 13 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 14 | * | ||
| 15 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | |||
| 20 | 1. Blackfin GPIO introduction | ||
| 21 | |||
| 22 | There are many GPIO pins on Blackfin. Most of these pins are muxed to | ||
| 23 | multi-functions. They can be configured as peripheral, or just as GPIO, | ||
| 24 | configured to input with interrupt enabled, or output. | ||
| 25 | |||
| 26 | For detailed information, please see "arch/blackfin/kernel/bfin_gpio.c", | ||
| 27 | or the relevant HRM. | ||
| 28 | |||
| 29 | |||
| 30 | 2. Avoiding resource conflict | ||
| 31 | |||
| 32 | Followed function groups are used to avoiding resource conflict, | ||
| 33 | - Use the pin as peripheral, | ||
| 34 | int peripheral_request(unsigned short per, const char *label); | ||
| 35 | int peripheral_request_list(const unsigned short per[], const char *label); | ||
| 36 | void peripheral_free(unsigned short per); | ||
| 37 | void peripheral_free_list(const unsigned short per[]); | ||
| 38 | - Use the pin as GPIO, | ||
| 39 | int bfin_gpio_request(unsigned gpio, const char *label); | ||
| 40 | void bfin_gpio_free(unsigned gpio); | ||
| 41 | - Use the pin as GPIO interrupt, | ||
| 42 | int bfin_gpio_irq_request(unsigned gpio, const char *label); | ||
| 43 | void bfin_gpio_irq_free(unsigned gpio); | ||
| 44 | |||
| 45 | The request functions will record the function state for a certain pin, | ||
| 46 | the free functions will clear it's function state. | ||
| 47 | Once a pin is requested, it can't be requested again before it is freed by | ||
| 48 | previous caller, otherwise kernel will dump stacks, and the request | ||
| 49 | function fail. | ||
| 50 | These functions are wrapped by other functions, most of the users need not | ||
| 51 | care. | ||
| 52 | |||
| 53 | |||
| 54 | 3. But there are some exceptions | ||
| 55 | - Kernel permit the identical GPIO be requested both as GPIO and GPIO | ||
| 56 | interrut. | ||
| 57 | Some drivers, like gpio-keys, need this behavior. Kernel only print out | ||
| 58 | warning messages like, | ||
| 59 | bfin-gpio: GPIO 24 is already reserved by gpio-keys: BTN0, and you are | ||
| 60 | configuring it as IRQ! | ||
| 61 | |||
| 62 | Note: Consider the case that, if there are two drivers need the | ||
| 63 | identical GPIO, one of them use it as GPIO, the other use it as | ||
| 64 | GPIO interrupt. This will really cause resource conflict. So if | ||
| 65 | there is any abnormal driver behavior, please check the bfin-gpio | ||
| 66 | warning messages. | ||
| 67 | |||
| 68 | - Kernel permit the identical GPIO be requested from the same driver twice. | ||
| 69 | |||
| 70 | |||
| 71 | |||
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 29e71ed6b8a7..a949c4fbbddd 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
| @@ -26,6 +26,7 @@ config BLACKFIN | |||
| 26 | default y | 26 | default y |
| 27 | select HAVE_IDE | 27 | select HAVE_IDE |
| 28 | select HAVE_OPROFILE | 28 | select HAVE_OPROFILE |
| 29 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
| 29 | 30 | ||
| 30 | config ZONE_DMA | 31 | config ZONE_DMA |
| 31 | bool | 32 | bool |
| @@ -59,10 +60,6 @@ config GENERIC_CALIBRATE_DELAY | |||
| 59 | bool | 60 | bool |
| 60 | default y | 61 | default y |
| 61 | 62 | ||
| 62 | config HARDWARE_PM | ||
| 63 | def_bool y | ||
| 64 | depends on OPROFILE | ||
| 65 | |||
| 66 | source "init/Kconfig" | 63 | source "init/Kconfig" |
| 67 | 64 | ||
| 68 | source "kernel/Kconfig.preempt" | 65 | source "kernel/Kconfig.preempt" |
| @@ -77,6 +74,26 @@ choice | |||
| 77 | prompt "CPU" | 74 | prompt "CPU" |
| 78 | default BF533 | 75 | default BF533 |
| 79 | 76 | ||
| 77 | config BF512 | ||
| 78 | bool "BF512" | ||
| 79 | help | ||
| 80 | BF512 Processor Support. | ||
| 81 | |||
| 82 | config BF514 | ||
| 83 | bool "BF514" | ||
| 84 | help | ||
| 85 | BF514 Processor Support. | ||
| 86 | |||
| 87 | config BF516 | ||
| 88 | bool "BF516" | ||
| 89 | help | ||
| 90 | BF516 Processor Support. | ||
| 91 | |||
| 92 | config BF518 | ||
| 93 | bool "BF518" | ||
| 94 | help | ||
| 95 | BF518 Processor Support. | ||
| 96 | |||
| 80 | config BF522 | 97 | config BF522 |
| 81 | bool "BF522" | 98 | bool "BF522" |
| 82 | help | 99 | help |
| @@ -137,6 +154,16 @@ config BF537 | |||
| 137 | help | 154 | help |
| 138 | BF537 Processor Support. | 155 | BF537 Processor Support. |
| 139 | 156 | ||
| 157 | config BF538 | ||
| 158 | bool "BF538" | ||
| 159 | help | ||
| 160 | BF538 Processor Support. | ||
| 161 | |||
| 162 | config BF539 | ||
| 163 | bool "BF539" | ||
| 164 | help | ||
| 165 | BF539 Processor Support. | ||
| 166 | |||
| 140 | config BF542 | 167 | config BF542 |
| 141 | bool "BF542" | 168 | bool "BF542" |
| 142 | help | 169 | help |
| @@ -169,28 +196,55 @@ config BF561 | |||
| 169 | 196 | ||
| 170 | endchoice | 197 | endchoice |
| 171 | 198 | ||
| 199 | config SMP | ||
| 200 | depends on BF561 | ||
| 201 | bool "Symmetric multi-processing support" | ||
| 202 | ---help--- | ||
| 203 | This enables support for systems with more than one CPU, | ||
| 204 | like the dual core BF561. If you have a system with only one | ||
| 205 | CPU, say N. If you have a system with more than one CPU, say Y. | ||
| 206 | |||
| 207 | If you don't know what to do here, say N. | ||
| 208 | |||
| 209 | config NR_CPUS | ||
| 210 | int | ||
| 211 | depends on SMP | ||
| 212 | default 2 if BF561 | ||
| 213 | |||
| 214 | config IRQ_PER_CPU | ||
| 215 | bool | ||
| 216 | depends on SMP | ||
| 217 | default y | ||
| 218 | |||
| 219 | config TICK_SOURCE_SYSTMR0 | ||
| 220 | bool | ||
| 221 | select BFIN_GPTIMERS | ||
| 222 | depends on SMP | ||
| 223 | default y | ||
| 224 | |||
| 172 | config BF_REV_MIN | 225 | config BF_REV_MIN |
| 173 | int | 226 | int |
| 174 | default 0 if (BF52x || BF54x) | 227 | default 0 if (BF51x || BF52x || BF54x) |
| 175 | default 2 if (BF537 || BF536 || BF534) | 228 | default 2 if (BF537 || BF536 || BF534) |
| 176 | default 3 if (BF561 ||BF533 || BF532 || BF531) | 229 | default 3 if (BF561 ||BF533 || BF532 || BF531) |
| 230 | default 4 if (BF538 || BF539) | ||
| 177 | 231 | ||
| 178 | config BF_REV_MAX | 232 | config BF_REV_MAX |
| 179 | int | 233 | int |
| 180 | default 2 if (BF52x || BF54x) | 234 | default 2 if (BF51x || BF52x || BF54x) |
| 181 | default 3 if (BF537 || BF536 || BF534) | 235 | default 3 if (BF537 || BF536 || BF534) |
| 182 | default 5 if (BF561) | 236 | default 5 if (BF561 || BF538 || BF539) |
| 183 | default 6 if (BF533 || BF532 || BF531) | 237 | default 6 if (BF533 || BF532 || BF531) |
| 184 | 238 | ||
| 185 | choice | 239 | choice |
| 186 | prompt "Silicon Rev" | 240 | prompt "Silicon Rev" |
| 187 | default BF_REV_0_1 if (BF52x || BF54x) | 241 | default BF_REV_0_1 if (BF51x || BF52x || BF54x) |
| 188 | default BF_REV_0_2 if (BF534 || BF536 || BF537) | 242 | default BF_REV_0_2 if (BF534 || BF536 || BF537) |
| 189 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) | 243 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) |
| 190 | 244 | ||
| 191 | config BF_REV_0_0 | 245 | config BF_REV_0_0 |
| 192 | bool "0.0" | 246 | bool "0.0" |
| 193 | depends on (BF52x || BF54x) | 247 | depends on (BF51x || BF52x || BF54x) |
| 194 | 248 | ||
| 195 | config BF_REV_0_1 | 249 | config BF_REV_0_1 |
| 196 | bool "0.1" | 250 | bool "0.1" |
| @@ -206,11 +260,11 @@ config BF_REV_0_3 | |||
| 206 | 260 | ||
| 207 | config BF_REV_0_4 | 261 | config BF_REV_0_4 |
| 208 | bool "0.4" | 262 | bool "0.4" |
| 209 | depends on (BF561 || BF533 || BF532 || BF531) | 263 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
| 210 | 264 | ||
| 211 | config BF_REV_0_5 | 265 | config BF_REV_0_5 |
| 212 | bool "0.5" | 266 | bool "0.5" |
| 213 | depends on (BF561 || BF533 || BF532 || BF531) | 267 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
| 214 | 268 | ||
| 215 | config BF_REV_0_6 | 269 | config BF_REV_0_6 |
| 216 | bool "0.6" | 270 | bool "0.6" |
| @@ -224,6 +278,11 @@ config BF_REV_NONE | |||
| 224 | 278 | ||
| 225 | endchoice | 279 | endchoice |
| 226 | 280 | ||
| 281 | config BF51x | ||
| 282 | bool | ||
| 283 | depends on (BF512 || BF514 || BF516 || BF518) | ||
| 284 | default y | ||
| 285 | |||
| 227 | config BF52x | 286 | config BF52x |
| 228 | bool | 287 | bool |
| 229 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) | 288 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
| @@ -258,7 +317,7 @@ config MEM_MT48LC16M16A2TG_75 | |||
| 258 | 317 | ||
| 259 | config MEM_MT48LC32M8A2_75 | 318 | config MEM_MT48LC32M8A2_75 |
| 260 | bool | 319 | bool |
| 261 | depends on (BFIN537_STAMP || PNAV10) | 320 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
| 262 | default y | 321 | default y |
| 263 | 322 | ||
| 264 | config MEM_MT48LC8M32B2B5_7 | 323 | config MEM_MT48LC8M32B2B5_7 |
| @@ -271,10 +330,17 @@ config MEM_MT48LC32M16A2TG_75 | |||
| 271 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) | 330 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
| 272 | default y | 331 | default y |
| 273 | 332 | ||
| 333 | config MEM_MT48LC32M8A2_75 | ||
| 334 | bool | ||
| 335 | depends on (BFIN518F_EZBRD) | ||
| 336 | default y | ||
| 337 | |||
| 338 | source "arch/blackfin/mach-bf518/Kconfig" | ||
| 274 | source "arch/blackfin/mach-bf527/Kconfig" | 339 | source "arch/blackfin/mach-bf527/Kconfig" |
| 275 | source "arch/blackfin/mach-bf533/Kconfig" | 340 | source "arch/blackfin/mach-bf533/Kconfig" |
| 276 | source "arch/blackfin/mach-bf561/Kconfig" | 341 | source "arch/blackfin/mach-bf561/Kconfig" |
| 277 | source "arch/blackfin/mach-bf537/Kconfig" | 342 | source "arch/blackfin/mach-bf537/Kconfig" |
| 343 | source "arch/blackfin/mach-bf538/Kconfig" | ||
| 278 | source "arch/blackfin/mach-bf548/Kconfig" | 344 | source "arch/blackfin/mach-bf548/Kconfig" |
| 279 | 345 | ||
| 280 | menu "Board customizations" | 346 | menu "Board customizations" |
| @@ -307,6 +373,7 @@ config BOOT_LOAD | |||
| 307 | 373 | ||
| 308 | config ROM_BASE | 374 | config ROM_BASE |
| 309 | hex "Kernel ROM Base" | 375 | hex "Kernel ROM Base" |
| 376 | depends on ROMKERNEL | ||
| 310 | default "0x20040000" | 377 | default "0x20040000" |
| 311 | range 0x20000000 0x20400000 if !(BF54x || BF561) | 378 | range 0x20000000 0x20400000 if !(BF54x || BF561) |
| 312 | range 0x20000000 0x30000000 if (BF54x || BF561) | 379 | range 0x20000000 0x30000000 if (BF54x || BF561) |
| @@ -318,7 +385,7 @@ config CLKIN_HZ | |||
| 318 | int "Frequency of the crystal on the board in Hz" | 385 | int "Frequency of the crystal on the board in Hz" |
| 319 | default "11059200" if BFIN533_STAMP | 386 | default "11059200" if BFIN533_STAMP |
| 320 | default "27000000" if BFIN533_EZKIT | 387 | default "27000000" if BFIN533_EZKIT |
| 321 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) | 388 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD) |
| 322 | default "30000000" if BFIN561_EZKIT | 389 | default "30000000" if BFIN561_EZKIT |
| 323 | default "24576000" if PNAV10 | 390 | default "24576000" if PNAV10 |
| 324 | default "10000000" if BFIN532_IP0X | 391 | default "10000000" if BFIN532_IP0X |
| @@ -354,11 +421,11 @@ config VCO_MULT | |||
| 354 | range 1 64 | 421 | range 1 64 |
| 355 | default "22" if BFIN533_EZKIT | 422 | default "22" if BFIN533_EZKIT |
| 356 | default "45" if BFIN533_STAMP | 423 | default "45" if BFIN533_STAMP |
| 357 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) | 424 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
| 358 | default "22" if BFIN533_BLUETECHNIX_CM | 425 | default "22" if BFIN533_BLUETECHNIX_CM |
| 359 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) | 426 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
| 360 | default "20" if BFIN561_EZKIT | 427 | default "20" if BFIN561_EZKIT |
| 361 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) | 428 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
| 362 | help | 429 | help |
| 363 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | 430 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. |
| 364 | PLL Frequency = (Crystal Frequency) * (this setting) | 431 | PLL Frequency = (Crystal Frequency) * (this setting) |
| @@ -407,19 +474,70 @@ config MEM_MT46V32M16_5B | |||
| 407 | bool "MT46V32M16_5B" | 474 | bool "MT46V32M16_5B" |
| 408 | endchoice | 475 | endchoice |
| 409 | 476 | ||
| 410 | config MAX_MEM_SIZE | 477 | choice |
| 411 | int "Max SDRAM Memory Size in MBytes" | 478 | prompt "DDR/SDRAM Timing" |
| 412 | depends on !MPU | 479 | depends on BFIN_KERNEL_CLOCK |
| 413 | default 512 | 480 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC |
| 414 | help | 481 | help |
| 415 | This is the max memory size that the kernel will create CPLB | 482 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters |
| 416 | tables for. Your system will not be able to handle any more. | 483 | The calculated SDRAM timing parameters may not be 100% |
| 484 | accurate - This option is therefore marked experimental. | ||
| 485 | |||
| 486 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | ||
| 487 | bool "Calculate Timings (EXPERIMENTAL)" | ||
| 488 | depends on EXPERIMENTAL | ||
| 489 | |||
| 490 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | ||
| 491 | bool "Provide accurate Timings based on target SCLK" | ||
| 492 | help | ||
| 493 | Please consult the Blackfin Hardware Reference Manuals as well | ||
| 494 | as the memory device datasheet. | ||
| 495 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | ||
| 496 | endchoice | ||
| 497 | |||
| 498 | menu "Memory Init Control" | ||
| 499 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | ||
| 500 | |||
| 501 | config MEM_DDRCTL0 | ||
| 502 | depends on BF54x | ||
| 503 | hex "DDRCTL0" | ||
| 504 | default 0x0 | ||
| 505 | |||
| 506 | config MEM_DDRCTL1 | ||
| 507 | depends on BF54x | ||
| 508 | hex "DDRCTL1" | ||
| 509 | default 0x0 | ||
| 510 | |||
| 511 | config MEM_DDRCTL2 | ||
| 512 | depends on BF54x | ||
| 513 | hex "DDRCTL2" | ||
| 514 | default 0x0 | ||
| 515 | |||
| 516 | config MEM_EBIU_DDRQUE | ||
| 517 | depends on BF54x | ||
| 518 | hex "DDRQUE" | ||
| 519 | default 0x0 | ||
| 520 | |||
| 521 | config MEM_SDRRC | ||
| 522 | depends on !BF54x | ||
| 523 | hex "SDRRC" | ||
| 524 | default 0x0 | ||
| 525 | |||
| 526 | config MEM_SDGCTL | ||
| 527 | depends on !BF54x | ||
| 528 | hex "SDGCTL" | ||
| 529 | default 0x0 | ||
| 530 | endmenu | ||
| 417 | 531 | ||
| 418 | # | 532 | # |
| 419 | # Max & Min Speeds for various Chips | 533 | # Max & Min Speeds for various Chips |
| 420 | # | 534 | # |
| 421 | config MAX_VCO_HZ | 535 | config MAX_VCO_HZ |
| 422 | int | 536 | int |
| 537 | default 400000000 if BF512 | ||
| 538 | default 400000000 if BF514 | ||
| 539 | default 400000000 if BF516 | ||
| 540 | default 400000000 if BF518 | ||
| 423 | default 600000000 if BF522 | 541 | default 600000000 if BF522 |
| 424 | default 400000000 if BF523 | 542 | default 400000000 if BF523 |
| 425 | default 400000000 if BF524 | 543 | default 400000000 if BF524 |
| @@ -459,6 +577,7 @@ source kernel/Kconfig.hz | |||
| 459 | 577 | ||
| 460 | config GENERIC_TIME | 578 | config GENERIC_TIME |
| 461 | bool "Generic time" | 579 | bool "Generic time" |
| 580 | depends on !SMP | ||
| 462 | default y | 581 | default y |
| 463 | 582 | ||
| 464 | config GENERIC_CLOCKEVENTS | 583 | config GENERIC_CLOCKEVENTS |
| @@ -533,6 +652,7 @@ endmenu | |||
| 533 | 652 | ||
| 534 | 653 | ||
| 535 | menu "Blackfin Kernel Optimizations" | 654 | menu "Blackfin Kernel Optimizations" |
| 655 | depends on !SMP | ||
| 536 | 656 | ||
| 537 | comment "Memory Optimizations" | 657 | comment "Memory Optimizations" |
| 538 | 658 | ||
| @@ -655,6 +775,17 @@ config APP_STACK_L1 | |||
| 655 | 775 | ||
| 656 | Currently only works with FLAT binaries. | 776 | Currently only works with FLAT binaries. |
| 657 | 777 | ||
| 778 | config EXCEPTION_L1_SCRATCH | ||
| 779 | bool "Locate exception stack in L1 Scratch Memory" | ||
| 780 | default n | ||
| 781 | depends on !APP_STACK_L1 && !SYSCALL_TAB_L1 | ||
| 782 | help | ||
| 783 | Whenever an exception occurs, use the L1 Scratch memory for | ||
| 784 | stack storage. You cannot place the stacks of FLAT binaries | ||
| 785 | in L1 when using this option. | ||
| 786 | |||
| 787 | If you don't use L1 Scratch, then you should say Y here. | ||
| 788 | |||
| 658 | comment "Speed Optimizations" | 789 | comment "Speed Optimizations" |
| 659 | config BFIN_INS_LOWOVERHEAD | 790 | config BFIN_INS_LOWOVERHEAD |
| 660 | bool "ins[bwl] low overhead, higher interrupt latency" | 791 | bool "ins[bwl] low overhead, higher interrupt latency" |
| @@ -684,7 +815,6 @@ config BFIN_INS_LOWOVERHEAD | |||
| 684 | 815 | ||
| 685 | endmenu | 816 | endmenu |
| 686 | 817 | ||
| 687 | |||
| 688 | choice | 818 | choice |
| 689 | prompt "Kernel executes from" | 819 | prompt "Kernel executes from" |
| 690 | help | 820 | help |
| @@ -714,17 +844,9 @@ config BFIN_GPTIMERS | |||
| 714 | To compile this driver as a module, choose M here: the module | 844 | To compile this driver as a module, choose M here: the module |
| 715 | will be called gptimers.ko. | 845 | will be called gptimers.ko. |
| 716 | 846 | ||
| 717 | config BFIN_DMA_5XX | ||
| 718 | bool "Enable DMA Support" | ||
| 719 | depends on (BF52x || BF53x || BF561 || BF54x) | ||
| 720 | default y | ||
| 721 | help | ||
| 722 | DMA driver for BF5xx. | ||
| 723 | |||
| 724 | choice | 847 | choice |
| 725 | prompt "Uncached SDRAM region" | 848 | prompt "Uncached DMA region" |
| 726 | default DMA_UNCACHED_1M | 849 | default DMA_UNCACHED_1M |
| 727 | depends on BFIN_DMA_5XX | ||
| 728 | config DMA_UNCACHED_4M | 850 | config DMA_UNCACHED_4M |
| 729 | bool "Enable 4M DMA region" | 851 | bool "Enable 4M DMA region" |
| 730 | config DMA_UNCACHED_2M | 852 | config DMA_UNCACHED_2M |
| @@ -751,9 +873,11 @@ config BFIN_ICACHE_LOCK | |||
| 751 | choice | 873 | choice |
| 752 | prompt "Policy" | 874 | prompt "Policy" |
| 753 | depends on BFIN_DCACHE | 875 | depends on BFIN_DCACHE |
| 754 | default BFIN_WB | 876 | default BFIN_WB if !SMP |
| 877 | default BFIN_WT if SMP | ||
| 755 | config BFIN_WB | 878 | config BFIN_WB |
| 756 | bool "Write back" | 879 | bool "Write back" |
| 880 | depends on !SMP | ||
| 757 | help | 881 | help |
| 758 | Write Back Policy: | 882 | Write Back Policy: |
| 759 | Cached data will be written back to SDRAM only when needed. | 883 | Cached data will be written back to SDRAM only when needed. |
| @@ -790,7 +914,7 @@ endchoice | |||
| 790 | 914 | ||
| 791 | config BFIN_L2_CACHEABLE | 915 | config BFIN_L2_CACHEABLE |
| 792 | bool "Cache L2 SRAM" | 916 | bool "Cache L2 SRAM" |
| 793 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561) | 917 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP)) |
| 794 | default n | 918 | default n |
| 795 | help | 919 | help |
| 796 | Select to make L2 SRAM cacheable in L1 data and instruction cache. | 920 | Select to make L2 SRAM cacheable in L1 data and instruction cache. |
| @@ -980,7 +1104,7 @@ config PM_WAKEUP_GPIO_NUMBER | |||
| 980 | int "GPIO number" | 1104 | int "GPIO number" |
| 981 | range 0 47 | 1105 | range 0 47 |
| 982 | depends on PM_WAKEUP_BY_GPIO | 1106 | depends on PM_WAKEUP_BY_GPIO |
| 983 | default 2 if BFIN537_STAMP | 1107 | default 2 |
| 984 | 1108 | ||
| 985 | choice | 1109 | choice |
| 986 | prompt "GPIO Polarity" | 1110 | prompt "GPIO Polarity" |
| @@ -1003,7 +1127,7 @@ comment "Possible Suspend Mem / Hibernate Wake-Up Sources" | |||
| 1003 | 1127 | ||
| 1004 | config PM_BFIN_WAKE_PH6 | 1128 | config PM_BFIN_WAKE_PH6 |
| 1005 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | 1129 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" |
| 1006 | depends on PM && (BF52x || BF534 || BF536 || BF537) | 1130 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
| 1007 | default n | 1131 | default n |
| 1008 | help | 1132 | help |
| 1009 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | 1133 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) |
| @@ -1020,15 +1144,21 @@ menu "CPU Frequency scaling" | |||
| 1020 | 1144 | ||
| 1021 | source "drivers/cpufreq/Kconfig" | 1145 | source "drivers/cpufreq/Kconfig" |
| 1022 | 1146 | ||
| 1147 | config BFIN_CPU_FREQ | ||
| 1148 | bool | ||
| 1149 | depends on CPU_FREQ | ||
| 1150 | select CPU_FREQ_TABLE | ||
| 1151 | default y | ||
| 1152 | |||
| 1023 | config CPU_VOLTAGE | 1153 | config CPU_VOLTAGE |
| 1024 | bool "CPU Voltage scaling" | 1154 | bool "CPU Voltage scaling" |
| 1025 | depends on EXPERIMENTAL | 1155 | depends on EXPERIMENTAL |
| 1026 | depends on CPU_FREQ | 1156 | depends on CPU_FREQ |
| 1027 | default n | 1157 | default n |
| 1028 | help | 1158 | help |
| 1029 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | 1159 | Say Y here if you want CPU voltage scaling according to the CPU frequency. |
| 1030 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | 1160 | This option violates the PLL BYPASS recommendation in the Blackfin Processor |
| 1031 | manuals. There is a theoretical risk that during VDDINT transitions | 1161 | manuals. There is a theoretical risk that during VDDINT transitions |
| 1032 | the PLL may unlock. | 1162 | the PLL may unlock. |
| 1033 | 1163 | ||
| 1034 | endmenu | 1164 | endmenu |
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index 3ad25983ec97..5f981d9ca625 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug | |||
| @@ -2,8 +2,30 @@ menu "Kernel hacking" | |||
| 2 | 2 | ||
| 3 | source "lib/Kconfig.debug" | 3 | source "lib/Kconfig.debug" |
| 4 | 4 | ||
| 5 | config DEBUG_STACKOVERFLOW | ||
| 6 | bool "Check for stack overflows" | ||
| 7 | depends on DEBUG_KERNEL | ||
| 8 | help | ||
| 9 | This option will cause messages to be printed if free stack space | ||
| 10 | drops below a certain limit. | ||
| 11 | |||
| 12 | config DEBUG_STACK_USAGE | ||
| 13 | bool "Enable stack utilization instrumentation" | ||
| 14 | depends on DEBUG_KERNEL | ||
| 15 | help | ||
| 16 | Enables the display of the minimum amount of free stack which each | ||
| 17 | task has ever had available in the sysrq-T output. | ||
| 18 | |||
| 19 | This option will slow down process creation somewhat. | ||
| 20 | |||
| 5 | config HAVE_ARCH_KGDB | 21 | config HAVE_ARCH_KGDB |
| 6 | def_bool y | 22 | def_bool y |
| 23 | |||
| 24 | config KGDB_TESTCASE | ||
| 25 | tristate "KGDB: for test case in expect" | ||
| 26 | default n | ||
| 27 | help | ||
| 28 | This is a kgdb test case for automated testing. | ||
| 7 | 29 | ||
| 8 | config DEBUG_VERBOSE | 30 | config DEBUG_VERBOSE |
| 9 | bool "Verbose fault messages" | 31 | bool "Verbose fault messages" |
| @@ -182,11 +204,11 @@ config DEBUG_BFIN_HWTRACE_EXPAND_LEN | |||
| 182 | 4 for (2^4) 16k, or 4096 entries | 204 | 4 for (2^4) 16k, or 4096 entries |
| 183 | 205 | ||
| 184 | config DEBUG_BFIN_NO_KERN_HWTRACE | 206 | config DEBUG_BFIN_NO_KERN_HWTRACE |
| 185 | bool "Trace user apps (turn off hwtrace in kernel)" | 207 | bool "Turn off hwtrace in CPLB handlers" |
| 186 | depends on DEBUG_BFIN_HWTRACE_ON | 208 | depends on DEBUG_BFIN_HWTRACE_ON |
| 187 | default n | 209 | default y |
| 188 | help | 210 | help |
| 189 | Some pieces of the kernel contain a lot of flow changes which can | 211 | The CPLB error handler contains a lot of flow changes which can |
| 190 | quickly fill up the hardware trace buffer. When debugging crashes, | 212 | quickly fill up the hardware trace buffer. When debugging crashes, |
| 191 | the hardware trace may indicate that the problem lies in kernel | 213 | the hardware trace may indicate that the problem lies in kernel |
| 192 | space when in reality an application is buggy. | 214 | space when in reality an application is buggy. |
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index 6bf50977850c..e550c8d46066 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile | |||
| @@ -21,6 +21,10 @@ KALLSYMS += --symbol-prefix=_ | |||
| 21 | KBUILD_DEFCONFIG := BF537-STAMP_defconfig | 21 | KBUILD_DEFCONFIG := BF537-STAMP_defconfig |
| 22 | 22 | ||
| 23 | # setup the machine name and the machine dependent settings | 23 | # setup the machine name and the machine dependent settings |
| 24 | machine-$(CONFIG_BF512) := bf518 | ||
| 25 | machine-$(CONFIG_BF514) := bf518 | ||
| 26 | machine-$(CONFIG_BF516) := bf518 | ||
| 27 | machine-$(CONFIG_BF518) := bf518 | ||
| 24 | machine-$(CONFIG_BF522) := bf527 | 28 | machine-$(CONFIG_BF522) := bf527 |
| 25 | machine-$(CONFIG_BF523) := bf527 | 29 | machine-$(CONFIG_BF523) := bf527 |
| 26 | machine-$(CONFIG_BF524) := bf527 | 30 | machine-$(CONFIG_BF524) := bf527 |
| @@ -33,6 +37,8 @@ machine-$(CONFIG_BF533) := bf533 | |||
| 33 | machine-$(CONFIG_BF534) := bf537 | 37 | machine-$(CONFIG_BF534) := bf537 |
| 34 | machine-$(CONFIG_BF536) := bf537 | 38 | machine-$(CONFIG_BF536) := bf537 |
| 35 | machine-$(CONFIG_BF537) := bf537 | 39 | machine-$(CONFIG_BF537) := bf537 |
| 40 | machine-$(CONFIG_BF538) := bf538 | ||
| 41 | machine-$(CONFIG_BF539) := bf538 | ||
| 36 | machine-$(CONFIG_BF542) := bf548 | 42 | machine-$(CONFIG_BF542) := bf548 |
| 37 | machine-$(CONFIG_BF544) := bf548 | 43 | machine-$(CONFIG_BF544) := bf548 |
| 38 | machine-$(CONFIG_BF547) := bf548 | 44 | machine-$(CONFIG_BF547) := bf548 |
| @@ -42,6 +48,10 @@ machine-$(CONFIG_BF561) := bf561 | |||
| 42 | MACHINE := $(machine-y) | 48 | MACHINE := $(machine-y) |
| 43 | export MACHINE | 49 | export MACHINE |
| 44 | 50 | ||
| 51 | cpu-$(CONFIG_BF512) := bf512 | ||
| 52 | cpu-$(CONFIG_BF514) := bf514 | ||
| 53 | cpu-$(CONFIG_BF516) := bf516 | ||
| 54 | cpu-$(CONFIG_BF518) := bf518 | ||
| 45 | cpu-$(CONFIG_BF522) := bf522 | 55 | cpu-$(CONFIG_BF522) := bf522 |
| 46 | cpu-$(CONFIG_BF523) := bf523 | 56 | cpu-$(CONFIG_BF523) := bf523 |
| 47 | cpu-$(CONFIG_BF524) := bf524 | 57 | cpu-$(CONFIG_BF524) := bf524 |
| @@ -54,6 +64,8 @@ cpu-$(CONFIG_BF533) := bf533 | |||
| 54 | cpu-$(CONFIG_BF534) := bf534 | 64 | cpu-$(CONFIG_BF534) := bf534 |
| 55 | cpu-$(CONFIG_BF536) := bf536 | 65 | cpu-$(CONFIG_BF536) := bf536 |
| 56 | cpu-$(CONFIG_BF537) := bf537 | 66 | cpu-$(CONFIG_BF537) := bf537 |
| 67 | cpu-$(CONFIG_BF538) := bf538 | ||
| 68 | cpu-$(CONFIG_BF539) := bf539 | ||
| 57 | cpu-$(CONFIG_BF542) := bf542 | 69 | cpu-$(CONFIG_BF542) := bf542 |
| 58 | cpu-$(CONFIG_BF544) := bf544 | 70 | cpu-$(CONFIG_BF544) := bf544 |
| 59 | cpu-$(CONFIG_BF547) := bf547 | 71 | cpu-$(CONFIG_BF547) := bf547 |
| @@ -79,7 +91,7 @@ KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y) | |||
| 79 | CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }') | 91 | CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }') |
| 80 | CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__ | 92 | CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__ |
| 81 | 93 | ||
| 82 | head-y := arch/$(ARCH)/mach-$(MACHINE)/head.o arch/$(ARCH)/kernel/init_task.o | 94 | head-y := arch/$(ARCH)/kernel/init_task.o |
| 83 | 95 | ||
| 84 | core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/ | 96 | core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/ |
| 85 | 97 | ||
| @@ -95,10 +107,10 @@ else | |||
| 95 | core-y += arch/$(ARCH)/kernel/cplb-nompu/ | 107 | core-y += arch/$(ARCH)/kernel/cplb-nompu/ |
| 96 | endif | 108 | endif |
| 97 | 109 | ||
| 98 | libs-y += arch/$(ARCH)/lib/ | ||
| 99 | |||
| 100 | drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/ | 110 | drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/ |
| 101 | 111 | ||
| 112 | libs-y += arch/$(ARCH)/lib/ | ||
| 113 | |||
| 102 | machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y)) | 114 | machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y)) |
| 103 | 115 | ||
| 104 | KBUILD_CFLAGS += -Iarch/$(ARCH)/include/ | 116 | KBUILD_CFLAGS += -Iarch/$(ARCH)/include/ |
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig new file mode 100644 index 000000000000..e0b3f242b555 --- /dev/null +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig | |||
| @@ -0,0 +1,1191 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.28-rc2 | ||
| 4 | # | ||
| 5 | # CONFIG_MMU is not set | ||
| 6 | # CONFIG_FPU is not set | ||
| 7 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | ||
| 9 | CONFIG_BLACKFIN=y | ||
| 10 | CONFIG_ZONE_DMA=y | ||
| 11 | CONFIG_GENERIC_FIND_NEXT_BIT=y | ||
| 12 | CONFIG_GENERIC_HWEIGHT=y | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 15 | CONFIG_GENERIC_GPIO=y | ||
| 16 | CONFIG_FORCE_MAX_ZONEORDER=14 | ||
| 17 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 18 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 19 | |||
| 20 | # | ||
| 21 | # General setup | ||
| 22 | # | ||
| 23 | CONFIG_EXPERIMENTAL=y | ||
| 24 | CONFIG_BROKEN_ON_SMP=y | ||
| 25 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 26 | CONFIG_LOCALVERSION="" | ||
| 27 | CONFIG_LOCALVERSION_AUTO=y | ||
| 28 | CONFIG_SYSVIPC=y | ||
| 29 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 30 | # CONFIG_POSIX_MQUEUE is not set | ||
| 31 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 32 | # CONFIG_TASKSTATS is not set | ||
| 33 | # CONFIG_AUDIT is not set | ||
| 34 | CONFIG_IKCONFIG=y | ||
| 35 | CONFIG_IKCONFIG_PROC=y | ||
| 36 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 37 | # CONFIG_CGROUPS is not set | ||
| 38 | # CONFIG_GROUP_SCHED is not set | ||
| 39 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 40 | # CONFIG_RELAY is not set | ||
| 41 | # CONFIG_NAMESPACES is not set | ||
| 42 | CONFIG_BLK_DEV_INITRD=y | ||
| 43 | CONFIG_INITRAMFS_SOURCE="" | ||
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 45 | CONFIG_SYSCTL=y | ||
| 46 | CONFIG_EMBEDDED=y | ||
| 47 | CONFIG_UID16=y | ||
| 48 | CONFIG_SYSCTL_SYSCALL=y | ||
| 49 | CONFIG_KALLSYMS=y | ||
| 50 | # CONFIG_KALLSYMS_ALL is not set | ||
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 52 | CONFIG_HOTPLUG=y | ||
| 53 | CONFIG_PRINTK=y | ||
| 54 | CONFIG_BUG=y | ||
| 55 | # CONFIG_ELF_CORE is not set | ||
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | ||
| 58 | CONFIG_FUTEX=y | ||
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | ||
| 61 | CONFIG_SIGNALFD=y | ||
| 62 | CONFIG_TIMERFD=y | ||
| 63 | CONFIG_EVENTFD=y | ||
| 64 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 66 | CONFIG_SLAB=y | ||
| 67 | # CONFIG_SLUB is not set | ||
| 68 | # CONFIG_SLOB is not set | ||
| 69 | # CONFIG_PROFILING is not set | ||
| 70 | # CONFIG_MARKERS is not set | ||
| 71 | CONFIG_HAVE_OPROFILE=y | ||
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 73 | CONFIG_SLABINFO=y | ||
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | ||
| 76 | CONFIG_BASE_SMALL=0 | ||
| 77 | CONFIG_MODULES=y | ||
| 78 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 79 | CONFIG_MODULE_UNLOAD=y | ||
| 80 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 81 | # CONFIG_MODVERSIONS is not set | ||
| 82 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 83 | CONFIG_KMOD=y | ||
| 84 | CONFIG_BLOCK=y | ||
| 85 | # CONFIG_LBD is not set | ||
| 86 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 87 | # CONFIG_LSF is not set | ||
| 88 | # CONFIG_BLK_DEV_BSG is not set | ||
| 89 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 90 | |||
| 91 | # | ||
| 92 | # IO Schedulers | ||
| 93 | # | ||
| 94 | CONFIG_IOSCHED_NOOP=y | ||
| 95 | # CONFIG_IOSCHED_AS is not set | ||
| 96 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 97 | # CONFIG_IOSCHED_CFQ is not set | ||
| 98 | # CONFIG_DEFAULT_AS is not set | ||
| 99 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 100 | # CONFIG_DEFAULT_CFQ is not set | ||
| 101 | CONFIG_DEFAULT_NOOP=y | ||
| 102 | CONFIG_DEFAULT_IOSCHED="noop" | ||
| 103 | CONFIG_CLASSIC_RCU=y | ||
| 104 | # CONFIG_PREEMPT_NONE is not set | ||
| 105 | CONFIG_PREEMPT_VOLUNTARY=y | ||
| 106 | # CONFIG_PREEMPT is not set | ||
| 107 | # CONFIG_FREEZER is not set | ||
| 108 | |||
| 109 | # | ||
| 110 | # Blackfin Processor Options | ||
| 111 | # | ||
| 112 | |||
| 113 | # | ||
| 114 | # Processor and Board Settings | ||
| 115 | # | ||
| 116 | # CONFIG_BF512 is not set | ||
| 117 | # CONFIG_BF514 is not set | ||
| 118 | # CONFIG_BF516 is not set | ||
| 119 | CONFIG_BF518=y | ||
| 120 | # CONFIG_BF522 is not set | ||
| 121 | # CONFIG_BF523 is not set | ||
| 122 | # CONFIG_BF524 is not set | ||
| 123 | # CONFIG_BF525 is not set | ||
| 124 | # CONFIG_BF526 is not set | ||
| 125 | # CONFIG_BF527 is not set | ||
| 126 | # CONFIG_BF531 is not set | ||
| 127 | # CONFIG_BF532 is not set | ||
| 128 | # CONFIG_BF533 is not set | ||
| 129 | # CONFIG_BF534 is not set | ||
| 130 | # CONFIG_BF536 is not set | ||
| 131 | # CONFIG_BF537 is not set | ||
| 132 | # CONFIG_BF538 is not set | ||
| 133 | # CONFIG_BF539 is not set | ||
| 134 | # CONFIG_BF542 is not set | ||
| 135 | # CONFIG_BF544 is not set | ||
| 136 | # CONFIG_BF547 is not set | ||
| 137 | # CONFIG_BF548 is not set | ||
| 138 | # CONFIG_BF549 is not set | ||
| 139 | # CONFIG_BF561 is not set | ||
| 140 | CONFIG_BF_REV_MIN=0 | ||
| 141 | CONFIG_BF_REV_MAX=2 | ||
| 142 | CONFIG_BF_REV_0_0=y | ||
| 143 | # CONFIG_BF_REV_0_1 is not set | ||
| 144 | # CONFIG_BF_REV_0_2 is not set | ||
| 145 | # CONFIG_BF_REV_0_3 is not set | ||
| 146 | # CONFIG_BF_REV_0_4 is not set | ||
| 147 | # CONFIG_BF_REV_0_5 is not set | ||
| 148 | # CONFIG_BF_REV_0_6 is not set | ||
| 149 | # CONFIG_BF_REV_ANY is not set | ||
| 150 | # CONFIG_BF_REV_NONE is not set | ||
| 151 | CONFIG_BF51x=y | ||
| 152 | CONFIG_BFIN518F_EZBRD=y | ||
| 153 | |||
| 154 | # | ||
| 155 | # BF518 Specific Configuration | ||
| 156 | # | ||
| 157 | |||
| 158 | # | ||
| 159 | # Alternative Multiplexing Scheme | ||
| 160 | # | ||
| 161 | # CONFIG_BF518_SPORT0_PORTF is not set | ||
| 162 | CONFIG_BF518_SPORT0_PORTG=y | ||
| 163 | CONFIG_BF518_SPORT0_TSCLK_PG10=y | ||
| 164 | # CONFIG_BF518_SPORT0_TSCLK_PG14 is not set | ||
| 165 | CONFIG_BF518_UART1_PORTF=y | ||
| 166 | # CONFIG_BF518_UART1_PORTG is not set | ||
| 167 | |||
| 168 | # | ||
| 169 | # Interrupt Priority Assignment | ||
| 170 | # | ||
| 171 | |||
| 172 | # | ||
| 173 | # Priority | ||
| 174 | # | ||
| 175 | CONFIG_IRQ_PLL_WAKEUP=7 | ||
| 176 | CONFIG_IRQ_DMA0_ERROR=7 | ||
| 177 | CONFIG_IRQ_DMAR0_BLK=7 | ||
| 178 | CONFIG_IRQ_DMAR1_BLK=7 | ||
| 179 | CONFIG_IRQ_DMAR0_OVR=7 | ||
| 180 | CONFIG_IRQ_DMAR1_OVR=7 | ||
| 181 | CONFIG_IRQ_PPI_ERROR=7 | ||
| 182 | CONFIG_IRQ_MAC_ERROR=7 | ||
| 183 | CONFIG_IRQ_SPORT0_ERROR=7 | ||
| 184 | CONFIG_IRQ_SPORT1_ERROR=7 | ||
| 185 | CONFIG_IRQ_PTP_ERROR=7 | ||
| 186 | CONFIG_IRQ_UART0_ERROR=7 | ||
| 187 | CONFIG_IRQ_UART1_ERROR=7 | ||
| 188 | CONFIG_IRQ_RTC=8 | ||
| 189 | CONFIG_IRQ_PPI=8 | ||
| 190 | CONFIG_IRQ_SPORT0_RX=9 | ||
| 191 | CONFIG_IRQ_SPORT0_TX=9 | ||
| 192 | CONFIG_IRQ_SPORT1_RX=9 | ||
| 193 | CONFIG_IRQ_SPORT1_TX=9 | ||
| 194 | CONFIG_IRQ_TWI=10 | ||
| 195 | CONFIG_IRQ_SPI0=10 | ||
| 196 | CONFIG_IRQ_UART0_RX=10 | ||
| 197 | CONFIG_IRQ_UART0_TX=10 | ||
| 198 | CONFIG_IRQ_UART1_RX=10 | ||
| 199 | CONFIG_IRQ_UART1_TX=10 | ||
| 200 | CONFIG_IRQ_OPTSEC=11 | ||
| 201 | CONFIG_IRQ_CNT=11 | ||
| 202 | CONFIG_IRQ_MAC_RX=11 | ||
| 203 | CONFIG_IRQ_PORTH_INTA=11 | ||
| 204 | CONFIG_IRQ_MAC_TX=11 | ||
| 205 | CONFIG_IRQ_PORTH_INTB=11 | ||
| 206 | CONFIG_IRQ_TIMER0=12 | ||
| 207 | CONFIG_IRQ_TIMER1=12 | ||
| 208 | CONFIG_IRQ_TIMER2=12 | ||
| 209 | CONFIG_IRQ_TIMER3=12 | ||
| 210 | CONFIG_IRQ_TIMER4=12 | ||
| 211 | CONFIG_IRQ_TIMER5=12 | ||
| 212 | CONFIG_IRQ_TIMER6=12 | ||
| 213 | CONFIG_IRQ_TIMER7=12 | ||
| 214 | CONFIG_IRQ_PORTG_INTA=12 | ||
| 215 | CONFIG_IRQ_PORTG_INTB=12 | ||
| 216 | CONFIG_IRQ_MEM_DMA0=13 | ||
| 217 | CONFIG_IRQ_MEM_DMA1=13 | ||
| 218 | CONFIG_IRQ_WATCH=13 | ||
| 219 | CONFIG_IRQ_PORTF_INTA=13 | ||
| 220 | CONFIG_IRQ_PORTF_INTB=13 | ||
| 221 | CONFIG_IRQ_SPI0_ERROR=7 | ||
| 222 | CONFIG_IRQ_SPI1_ERROR=7 | ||
| 223 | CONFIG_IRQ_RSI_INT0=7 | ||
| 224 | CONFIG_IRQ_RSI_INT1=7 | ||
| 225 | CONFIG_IRQ_PWM_TRIP=10 | ||
| 226 | CONFIG_IRQ_PWM_SYNC=10 | ||
| 227 | CONFIG_IRQ_PTP_STAT=10 | ||
| 228 | |||
| 229 | # | ||
| 230 | # Board customizations | ||
| 231 | # | ||
| 232 | # CONFIG_CMDLINE_BOOL is not set | ||
| 233 | CONFIG_BOOT_LOAD=0x1000 | ||
| 234 | |||
| 235 | # | ||
| 236 | # Clock/PLL Setup | ||
| 237 | # | ||
| 238 | CONFIG_CLKIN_HZ=25000000 | ||
| 239 | # CONFIG_BFIN_KERNEL_CLOCK is not set | ||
| 240 | CONFIG_MAX_VCO_HZ=400000000 | ||
| 241 | CONFIG_MIN_VCO_HZ=50000000 | ||
| 242 | CONFIG_MAX_SCLK_HZ=133333333 | ||
| 243 | CONFIG_MIN_SCLK_HZ=27000000 | ||
| 244 | |||
| 245 | # | ||
| 246 | # Kernel Timer/Scheduler | ||
| 247 | # | ||
| 248 | # CONFIG_HZ_100 is not set | ||
| 249 | CONFIG_HZ_250=y | ||
| 250 | # CONFIG_HZ_300 is not set | ||
| 251 | # CONFIG_HZ_1000 is not set | ||
| 252 | CONFIG_HZ=250 | ||
| 253 | # CONFIG_SCHED_HRTICK is not set | ||
| 254 | CONFIG_GENERIC_TIME=y | ||
| 255 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 256 | # CONFIG_CYCLES_CLOCKSOURCE is not set | ||
| 257 | # CONFIG_NO_HZ is not set | ||
| 258 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 259 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 260 | |||
| 261 | # | ||
| 262 | # Misc | ||
| 263 | # | ||
| 264 | CONFIG_BFIN_SCRATCH_REG_RETN=y | ||
| 265 | # CONFIG_BFIN_SCRATCH_REG_RETE is not set | ||
| 266 | # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set | ||
| 267 | |||
| 268 | # | ||
| 269 | # Blackfin Kernel Optimizations | ||
| 270 | # | ||
| 271 | |||
| 272 | # | ||
| 273 | # Memory Optimizations | ||
| 274 | # | ||
| 275 | CONFIG_I_ENTRY_L1=y | ||
| 276 | CONFIG_EXCPT_IRQ_SYSC_L1=y | ||
| 277 | CONFIG_DO_IRQ_L1=y | ||
| 278 | CONFIG_CORE_TIMER_IRQ_L1=y | ||
| 279 | CONFIG_IDLE_L1=y | ||
| 280 | # CONFIG_SCHEDULE_L1 is not set | ||
| 281 | CONFIG_ARITHMETIC_OPS_L1=y | ||
| 282 | CONFIG_ACCESS_OK_L1=y | ||
| 283 | # CONFIG_MEMSET_L1 is not set | ||
| 284 | # CONFIG_MEMCPY_L1 is not set | ||
| 285 | # CONFIG_SYS_BFIN_SPINLOCK_L1 is not set | ||
| 286 | # CONFIG_IP_CHECKSUM_L1 is not set | ||
| 287 | CONFIG_CACHELINE_ALIGNED_L1=y | ||
| 288 | # CONFIG_SYSCALL_TAB_L1 is not set | ||
| 289 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | ||
| 290 | CONFIG_APP_STACK_L1=y | ||
| 291 | |||
| 292 | # | ||
| 293 | # Speed Optimizations | ||
| 294 | # | ||
| 295 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 296 | CONFIG_RAMKERNEL=y | ||
| 297 | # CONFIG_ROMKERNEL is not set | ||
| 298 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 299 | CONFIG_FLATMEM_MANUAL=y | ||
| 300 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 301 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 302 | CONFIG_FLATMEM=y | ||
| 303 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 304 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 305 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 306 | # CONFIG_RESOURCES_64BIT is not set | ||
| 307 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 308 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 309 | CONFIG_VIRT_TO_BUS=y | ||
| 310 | CONFIG_BFIN_GPTIMERS=y | ||
| 311 | # CONFIG_DMA_UNCACHED_4M is not set | ||
| 312 | # CONFIG_DMA_UNCACHED_2M is not set | ||
| 313 | CONFIG_DMA_UNCACHED_1M=y | ||
| 314 | # CONFIG_DMA_UNCACHED_NONE is not set | ||
| 315 | |||
| 316 | # | ||
| 317 | # Cache Support | ||
| 318 | # | ||
| 319 | CONFIG_BFIN_ICACHE=y | ||
| 320 | CONFIG_BFIN_DCACHE=y | ||
| 321 | # CONFIG_BFIN_DCACHE_BANKA is not set | ||
| 322 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 323 | CONFIG_BFIN_WB=y | ||
| 324 | # CONFIG_BFIN_WT is not set | ||
| 325 | # CONFIG_MPU is not set | ||
| 326 | |||
| 327 | # | ||
| 328 | # Asynchonous Memory Configuration | ||
| 329 | # | ||
| 330 | |||
| 331 | # | ||
| 332 | # EBIU_AMGCTL Global Control | ||
| 333 | # | ||
| 334 | CONFIG_C_AMCKEN=y | ||
| 335 | CONFIG_C_CDPRIO=y | ||
| 336 | # CONFIG_C_AMBEN is not set | ||
| 337 | # CONFIG_C_AMBEN_B0 is not set | ||
| 338 | # CONFIG_C_AMBEN_B0_B1 is not set | ||
| 339 | # CONFIG_C_AMBEN_B0_B1_B2 is not set | ||
| 340 | CONFIG_C_AMBEN_ALL=y | ||
| 341 | |||
| 342 | # | ||
| 343 | # EBIU_AMBCTL Control | ||
| 344 | # | ||
| 345 | CONFIG_BANK_0=0x7BB0 | ||
| 346 | CONFIG_BANK_1=0x5554 | ||
| 347 | CONFIG_BANK_2=0x7BB0 | ||
| 348 | CONFIG_BANK_3=0xFFC0 | ||
| 349 | |||
| 350 | # | ||
| 351 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | ||
| 352 | # | ||
| 353 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 354 | # CONFIG_PCCARD is not set | ||
| 355 | |||
| 356 | # | ||
| 357 | # Executable file formats | ||
| 358 | # | ||
| 359 | CONFIG_BINFMT_ELF_FDPIC=y | ||
| 360 | CONFIG_BINFMT_FLAT=y | ||
| 361 | CONFIG_BINFMT_ZFLAT=y | ||
| 362 | # CONFIG_BINFMT_SHARED_FLAT is not set | ||
| 363 | # CONFIG_HAVE_AOUT is not set | ||
| 364 | # CONFIG_BINFMT_MISC is not set | ||
| 365 | |||
| 366 | # | ||
| 367 | # Power management options | ||
| 368 | # | ||
| 369 | # CONFIG_PM is not set | ||
| 370 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 371 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | ||
| 372 | |||
| 373 | # | ||
| 374 | # CPU Frequency scaling | ||
| 375 | # | ||
| 376 | # CONFIG_CPU_FREQ is not set | ||
| 377 | CONFIG_NET=y | ||
| 378 | |||
| 379 | # | ||
| 380 | # Networking options | ||
| 381 | # | ||
| 382 | CONFIG_PACKET=y | ||
| 383 | # CONFIG_PACKET_MMAP is not set | ||
| 384 | CONFIG_UNIX=y | ||
| 385 | CONFIG_XFRM=y | ||
| 386 | # CONFIG_XFRM_USER is not set | ||
| 387 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 388 | # CONFIG_XFRM_MIGRATE is not set | ||
| 389 | # CONFIG_XFRM_STATISTICS is not set | ||
| 390 | # CONFIG_NET_KEY is not set | ||
| 391 | CONFIG_INET=y | ||
| 392 | # CONFIG_IP_MULTICAST is not set | ||
| 393 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 394 | CONFIG_IP_FIB_HASH=y | ||
| 395 | CONFIG_IP_PNP=y | ||
| 396 | # CONFIG_IP_PNP_DHCP is not set | ||
| 397 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 398 | # CONFIG_IP_PNP_RARP is not set | ||
| 399 | # CONFIG_NET_IPIP is not set | ||
| 400 | # CONFIG_NET_IPGRE is not set | ||
| 401 | # CONFIG_ARPD is not set | ||
| 402 | CONFIG_SYN_COOKIES=y | ||
| 403 | # CONFIG_INET_AH is not set | ||
| 404 | # CONFIG_INET_ESP is not set | ||
| 405 | # CONFIG_INET_IPCOMP is not set | ||
| 406 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 407 | # CONFIG_INET_TUNNEL is not set | ||
| 408 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 409 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 410 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 411 | # CONFIG_INET_LRO is not set | ||
| 412 | CONFIG_INET_DIAG=y | ||
| 413 | CONFIG_INET_TCP_DIAG=y | ||
| 414 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 415 | CONFIG_TCP_CONG_CUBIC=y | ||
| 416 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 417 | # CONFIG_TCP_MD5SIG is not set | ||
| 418 | # CONFIG_IPV6 is not set | ||
| 419 | # CONFIG_NETLABEL is not set | ||
| 420 | # CONFIG_NETWORK_SECMARK is not set | ||
| 421 | # CONFIG_NETFILTER is not set | ||
| 422 | # CONFIG_IP_DCCP is not set | ||
| 423 | # CONFIG_IP_SCTP is not set | ||
| 424 | # CONFIG_TIPC is not set | ||
| 425 | # CONFIG_ATM is not set | ||
| 426 | # CONFIG_BRIDGE is not set | ||
| 427 | # CONFIG_NET_DSA is not set | ||
| 428 | # CONFIG_VLAN_8021Q is not set | ||
| 429 | # CONFIG_DECNET is not set | ||
| 430 | # CONFIG_LLC2 is not set | ||
| 431 | # CONFIG_IPX is not set | ||
| 432 | # CONFIG_ATALK is not set | ||
| 433 | # CONFIG_X25 is not set | ||
| 434 | # CONFIG_LAPB is not set | ||
| 435 | # CONFIG_ECONET is not set | ||
| 436 | # CONFIG_WAN_ROUTER is not set | ||
| 437 | # CONFIG_NET_SCHED is not set | ||
| 438 | |||
| 439 | # | ||
| 440 | # Network testing | ||
| 441 | # | ||
| 442 | # CONFIG_NET_PKTGEN is not set | ||
| 443 | # CONFIG_HAMRADIO is not set | ||
| 444 | # CONFIG_CAN is not set | ||
| 445 | # CONFIG_IRDA is not set | ||
| 446 | # CONFIG_BT is not set | ||
| 447 | # CONFIG_AF_RXRPC is not set | ||
| 448 | # CONFIG_PHONET is not set | ||
| 449 | CONFIG_WIRELESS=y | ||
| 450 | # CONFIG_CFG80211 is not set | ||
| 451 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 452 | # CONFIG_WIRELESS_EXT is not set | ||
| 453 | # CONFIG_MAC80211 is not set | ||
| 454 | # CONFIG_IEEE80211 is not set | ||
| 455 | # CONFIG_RFKILL is not set | ||
| 456 | # CONFIG_NET_9P is not set | ||
| 457 | |||
| 458 | # | ||
| 459 | # Device Drivers | ||
| 460 | # | ||
| 461 | |||
| 462 | # | ||
| 463 | # Generic Driver Options | ||
| 464 | # | ||
| 465 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 466 | CONFIG_STANDALONE=y | ||
| 467 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 468 | # CONFIG_FW_LOADER is not set | ||
| 469 | # CONFIG_DEBUG_DRIVER is not set | ||
| 470 | # CONFIG_DEBUG_DEVRES is not set | ||
| 471 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 472 | # CONFIG_CONNECTOR is not set | ||
| 473 | CONFIG_MTD=y | ||
| 474 | # CONFIG_MTD_DEBUG is not set | ||
| 475 | # CONFIG_MTD_CONCAT is not set | ||
| 476 | CONFIG_MTD_PARTITIONS=y | ||
| 477 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 478 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 479 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 480 | |||
| 481 | # | ||
| 482 | # User Modules And Translation Layers | ||
| 483 | # | ||
| 484 | CONFIG_MTD_CHAR=y | ||
| 485 | CONFIG_MTD_BLKDEVS=y | ||
| 486 | CONFIG_MTD_BLOCK=y | ||
| 487 | # CONFIG_FTL is not set | ||
| 488 | # CONFIG_NFTL is not set | ||
| 489 | # CONFIG_INFTL is not set | ||
| 490 | # CONFIG_RFD_FTL is not set | ||
| 491 | # CONFIG_SSFDC is not set | ||
| 492 | # CONFIG_MTD_OOPS is not set | ||
| 493 | |||
| 494 | # | ||
| 495 | # RAM/ROM/Flash chip drivers | ||
| 496 | # | ||
| 497 | # CONFIG_MTD_CFI is not set | ||
| 498 | CONFIG_MTD_JEDECPROBE=m | ||
| 499 | CONFIG_MTD_GEN_PROBE=m | ||
| 500 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 501 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 502 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 503 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 504 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 505 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 506 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 507 | CONFIG_MTD_CFI_I1=y | ||
| 508 | CONFIG_MTD_CFI_I2=y | ||
| 509 | # CONFIG_MTD_CFI_I4 is not set | ||
| 510 | # CONFIG_MTD_CFI_I8 is not set | ||
| 511 | # CONFIG_MTD_CFI_INTELEXT is not set | ||
| 512 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 513 | # CONFIG_MTD_CFI_STAA is not set | ||
| 514 | CONFIG_MTD_RAM=y | ||
| 515 | CONFIG_MTD_ROM=m | ||
| 516 | # CONFIG_MTD_ABSENT is not set | ||
| 517 | |||
| 518 | # | ||
| 519 | # Mapping drivers for chip access | ||
| 520 | # | ||
| 521 | CONFIG_MTD_COMPLEX_MAPPINGS=y | ||
| 522 | # CONFIG_MTD_PHYSMAP is not set | ||
| 523 | # CONFIG_MTD_GPIO_ADDR is not set | ||
| 524 | # CONFIG_MTD_UCLINUX is not set | ||
| 525 | # CONFIG_MTD_PLATRAM is not set | ||
| 526 | |||
| 527 | # | ||
| 528 | # Self-contained MTD device drivers | ||
| 529 | # | ||
| 530 | # CONFIG_MTD_SLRAM is not set | ||
| 531 | # CONFIG_MTD_PHRAM is not set | ||
| 532 | # CONFIG_MTD_MTDRAM is not set | ||
| 533 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 534 | |||
| 535 | # | ||
| 536 | # Disk-On-Chip Device Drivers | ||
| 537 | # | ||
| 538 | # CONFIG_MTD_DOC2000 is not set | ||
| 539 | # CONFIG_MTD_DOC2001 is not set | ||
| 540 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 541 | # CONFIG_MTD_NAND is not set | ||
| 542 | # CONFIG_MTD_ONENAND is not set | ||
| 543 | |||
| 544 | # | ||
| 545 | # UBI - Unsorted block images | ||
| 546 | # | ||
| 547 | # CONFIG_MTD_UBI is not set | ||
| 548 | # CONFIG_PARPORT is not set | ||
| 549 | CONFIG_BLK_DEV=y | ||
| 550 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 551 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 552 | # CONFIG_BLK_DEV_NBD is not set | ||
| 553 | CONFIG_BLK_DEV_RAM=y | ||
| 554 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 555 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 556 | # CONFIG_BLK_DEV_XIP is not set | ||
| 557 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 558 | # CONFIG_ATA_OVER_ETH is not set | ||
| 559 | # CONFIG_BLK_DEV_HD is not set | ||
| 560 | CONFIG_MISC_DEVICES=y | ||
| 561 | # CONFIG_EEPROM_93CX6 is not set | ||
| 562 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 563 | CONFIG_HAVE_IDE=y | ||
| 564 | # CONFIG_IDE is not set | ||
| 565 | |||
| 566 | # | ||
| 567 | # SCSI device support | ||
| 568 | # | ||
| 569 | # CONFIG_RAID_ATTRS is not set | ||
| 570 | # CONFIG_SCSI is not set | ||
| 571 | # CONFIG_SCSI_DMA is not set | ||
| 572 | # CONFIG_SCSI_NETLINK is not set | ||
| 573 | # CONFIG_ATA is not set | ||
| 574 | # CONFIG_MD is not set | ||
| 575 | CONFIG_NETDEVICES=y | ||
| 576 | # CONFIG_DUMMY is not set | ||
| 577 | # CONFIG_BONDING is not set | ||
| 578 | # CONFIG_MACVLAN is not set | ||
| 579 | # CONFIG_EQUALIZER is not set | ||
| 580 | # CONFIG_TUN is not set | ||
| 581 | # CONFIG_VETH is not set | ||
| 582 | CONFIG_PHYLIB=y | ||
| 583 | |||
| 584 | # | ||
| 585 | # MII PHY device drivers | ||
| 586 | # | ||
| 587 | # CONFIG_MARVELL_PHY is not set | ||
| 588 | # CONFIG_DAVICOM_PHY is not set | ||
| 589 | # CONFIG_QSEMI_PHY is not set | ||
| 590 | # CONFIG_LXT_PHY is not set | ||
| 591 | # CONFIG_CICADA_PHY is not set | ||
| 592 | # CONFIG_VITESSE_PHY is not set | ||
| 593 | # CONFIG_SMSC_PHY is not set | ||
| 594 | # CONFIG_BROADCOM_PHY is not set | ||
| 595 | # CONFIG_ICPLUS_PHY is not set | ||
| 596 | # CONFIG_REALTEK_PHY is not set | ||
| 597 | # CONFIG_FIXED_PHY is not set | ||
| 598 | # CONFIG_MDIO_BITBANG is not set | ||
| 599 | CONFIG_NET_ETHERNET=y | ||
| 600 | CONFIG_MII=y | ||
| 601 | # CONFIG_BFIN_MAC is not set | ||
| 602 | # CONFIG_SMC91X is not set | ||
| 603 | # CONFIG_SMSC911X is not set | ||
| 604 | # CONFIG_DM9000 is not set | ||
| 605 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 606 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 607 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 608 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 609 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 610 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 611 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 612 | # CONFIG_NETDEV_1000 is not set | ||
| 613 | # CONFIG_NETDEV_10000 is not set | ||
| 614 | |||
| 615 | # | ||
| 616 | # Wireless LAN | ||
| 617 | # | ||
| 618 | # CONFIG_WLAN_PRE80211 is not set | ||
| 619 | # CONFIG_WLAN_80211 is not set | ||
| 620 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 621 | # CONFIG_WAN is not set | ||
| 622 | # CONFIG_PPP is not set | ||
| 623 | # CONFIG_SLIP is not set | ||
| 624 | # CONFIG_NETCONSOLE is not set | ||
| 625 | # CONFIG_NETPOLL is not set | ||
| 626 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 627 | # CONFIG_ISDN is not set | ||
| 628 | # CONFIG_PHONE is not set | ||
| 629 | |||
| 630 | # | ||
| 631 | # Input device support | ||
| 632 | # | ||
| 633 | CONFIG_INPUT=y | ||
| 634 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 635 | # CONFIG_INPUT_POLLDEV is not set | ||
| 636 | |||
| 637 | # | ||
| 638 | # Userland interfaces | ||
| 639 | # | ||
| 640 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 641 | # CONFIG_INPUT_JOYDEV is not set | ||
| 642 | # CONFIG_INPUT_EVDEV is not set | ||
| 643 | # CONFIG_INPUT_EVBUG is not set | ||
| 644 | |||
| 645 | # | ||
| 646 | # Input Device Drivers | ||
| 647 | # | ||
| 648 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 649 | # CONFIG_INPUT_MOUSE is not set | ||
| 650 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 651 | # CONFIG_INPUT_TABLET is not set | ||
| 652 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 653 | CONFIG_INPUT_MISC=y | ||
| 654 | # CONFIG_INPUT_UINPUT is not set | ||
| 655 | # CONFIG_CONFIG_INPUT_PCF8574 is not set | ||
| 656 | |||
| 657 | # | ||
| 658 | # Hardware I/O ports | ||
| 659 | # | ||
| 660 | # CONFIG_SERIO is not set | ||
| 661 | # CONFIG_GAMEPORT is not set | ||
| 662 | |||
| 663 | # | ||
| 664 | # Character devices | ||
| 665 | # | ||
| 666 | # CONFIG_AD9960 is not set | ||
| 667 | # CONFIG_SPI_ADC_BF533 is not set | ||
| 668 | # CONFIG_BF5xx_PPIFCD is not set | ||
| 669 | # CONFIG_BFIN_SIMPLE_TIMER is not set | ||
| 670 | # CONFIG_BF5xx_PPI is not set | ||
| 671 | # CONFIG_BFIN_SPORT is not set | ||
| 672 | # CONFIG_BFIN_TIMER_LATENCY is not set | ||
| 673 | # CONFIG_TWI_LCD is not set | ||
| 674 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 675 | CONFIG_SIMPLE_GPIO=m | ||
| 676 | CONFIG_VT=y | ||
| 677 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 678 | CONFIG_VT_CONSOLE=y | ||
| 679 | CONFIG_HW_CONSOLE=y | ||
| 680 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 681 | # CONFIG_DEVKMEM is not set | ||
| 682 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 683 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 684 | |||
| 685 | # | ||
| 686 | # Serial drivers | ||
| 687 | # | ||
| 688 | # CONFIG_SERIAL_8250 is not set | ||
| 689 | |||
| 690 | # | ||
| 691 | # Non-8250 serial port support | ||
| 692 | # | ||
| 693 | CONFIG_SERIAL_BFIN=y | ||
| 694 | CONFIG_SERIAL_BFIN_CONSOLE=y | ||
| 695 | CONFIG_SERIAL_BFIN_DMA=y | ||
| 696 | # CONFIG_SERIAL_BFIN_PIO is not set | ||
| 697 | CONFIG_SERIAL_BFIN_UART0=y | ||
| 698 | # CONFIG_BFIN_UART0_CTSRTS is not set | ||
| 699 | # CONFIG_SERIAL_BFIN_UART1 is not set | ||
| 700 | CONFIG_SERIAL_CORE=y | ||
| 701 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 702 | # CONFIG_SERIAL_BFIN_SPORT is not set | ||
| 703 | CONFIG_UNIX98_PTYS=y | ||
| 704 | # CONFIG_LEGACY_PTYS is not set | ||
| 705 | |||
| 706 | # | ||
| 707 | # CAN, the car bus and industrial fieldbus | ||
| 708 | # | ||
| 709 | # CONFIG_CAN4LINUX is not set | ||
| 710 | # CONFIG_IPMI_HANDLER is not set | ||
| 711 | # CONFIG_HW_RANDOM is not set | ||
| 712 | # CONFIG_R3964 is not set | ||
| 713 | # CONFIG_RAW_DRIVER is not set | ||
| 714 | # CONFIG_TCG_TPM is not set | ||
| 715 | CONFIG_I2C=y | ||
| 716 | CONFIG_I2C_BOARDINFO=y | ||
| 717 | CONFIG_I2C_CHARDEV=y | ||
| 718 | CONFIG_I2C_HELPER_AUTO=y | ||
| 719 | |||
| 720 | # | ||
| 721 | # I2C Hardware Bus support | ||
| 722 | # | ||
| 723 | |||
| 724 | # | ||
| 725 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 726 | # | ||
| 727 | CONFIG_I2C_BLACKFIN_TWI=y | ||
| 728 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 | ||
| 729 | # CONFIG_I2C_GPIO is not set | ||
| 730 | # CONFIG_I2C_OCORES is not set | ||
| 731 | # CONFIG_I2C_SIMTEC is not set | ||
| 732 | |||
| 733 | # | ||
| 734 | # External I2C/SMBus adapter drivers | ||
| 735 | # | ||
| 736 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 737 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 738 | |||
| 739 | # | ||
| 740 | # Other I2C/SMBus bus drivers | ||
| 741 | # | ||
| 742 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 743 | # CONFIG_I2C_STUB is not set | ||
| 744 | |||
| 745 | # | ||
| 746 | # Miscellaneous I2C Chip support | ||
| 747 | # | ||
| 748 | # CONFIG_DS1682 is not set | ||
| 749 | # CONFIG_AT24 is not set | ||
| 750 | # CONFIG_SENSORS_AD5252 is not set | ||
| 751 | # CONFIG_SENSORS_EEPROM is not set | ||
| 752 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 753 | # CONFIG_PCF8575 is not set | ||
| 754 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 755 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 756 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 757 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 758 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 759 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 760 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 761 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 762 | # CONFIG_SPI is not set | ||
| 763 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 764 | # CONFIG_GPIOLIB is not set | ||
| 765 | # CONFIG_W1 is not set | ||
| 766 | # CONFIG_POWER_SUPPLY is not set | ||
| 767 | # CONFIG_HWMON is not set | ||
| 768 | # CONFIG_THERMAL is not set | ||
| 769 | # CONFIG_THERMAL_HWMON is not set | ||
| 770 | CONFIG_WATCHDOG=y | ||
| 771 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 772 | |||
| 773 | # | ||
| 774 | # Watchdog Device Drivers | ||
| 775 | # | ||
| 776 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 777 | CONFIG_BFIN_WDT=y | ||
| 778 | |||
| 779 | # | ||
| 780 | # Multifunction device drivers | ||
| 781 | # | ||
| 782 | # CONFIG_MFD_CORE is not set | ||
| 783 | # CONFIG_MFD_SM501 is not set | ||
| 784 | # CONFIG_HTC_PASIC3 is not set | ||
| 785 | # CONFIG_MFD_TMIO is not set | ||
| 786 | # CONFIG_MFD_WM8400 is not set | ||
| 787 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 788 | |||
| 789 | # | ||
| 790 | # Multimedia devices | ||
| 791 | # | ||
| 792 | |||
| 793 | # | ||
| 794 | # Multimedia core support | ||
| 795 | # | ||
| 796 | # CONFIG_VIDEO_DEV is not set | ||
| 797 | # CONFIG_DVB_CORE is not set | ||
| 798 | # CONFIG_VIDEO_MEDIA is not set | ||
| 799 | |||
| 800 | # | ||
| 801 | # Multimedia drivers | ||
| 802 | # | ||
| 803 | # CONFIG_DAB is not set | ||
| 804 | |||
| 805 | # | ||
| 806 | # Graphics support | ||
| 807 | # | ||
| 808 | # CONFIG_VGASTATE is not set | ||
| 809 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 810 | # CONFIG_FB is not set | ||
| 811 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 812 | |||
| 813 | # | ||
| 814 | # Display device support | ||
| 815 | # | ||
| 816 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 817 | |||
| 818 | # | ||
| 819 | # Console display driver support | ||
| 820 | # | ||
| 821 | CONFIG_DUMMY_CONSOLE=y | ||
| 822 | # CONFIG_SOUND is not set | ||
| 823 | # CONFIG_HID_SUPPORT is not set | ||
| 824 | # CONFIG_USB_SUPPORT is not set | ||
| 825 | # CONFIG_MMC is not set | ||
| 826 | # CONFIG_MEMSTICK is not set | ||
| 827 | # CONFIG_NEW_LEDS is not set | ||
| 828 | # CONFIG_ACCESSIBILITY is not set | ||
| 829 | CONFIG_RTC_LIB=y | ||
| 830 | CONFIG_RTC_CLASS=y | ||
| 831 | CONFIG_RTC_HCTOSYS=y | ||
| 832 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 833 | # CONFIG_RTC_DEBUG is not set | ||
| 834 | |||
| 835 | # | ||
| 836 | # RTC interfaces | ||
| 837 | # | ||
| 838 | CONFIG_RTC_INTF_SYSFS=y | ||
| 839 | CONFIG_RTC_INTF_PROC=y | ||
| 840 | CONFIG_RTC_INTF_DEV=y | ||
| 841 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 842 | # CONFIG_RTC_DRV_TEST is not set | ||
| 843 | |||
| 844 | # | ||
| 845 | # I2C RTC drivers | ||
| 846 | # | ||
| 847 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 848 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 849 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 850 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 851 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 852 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 853 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 854 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 855 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 856 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 857 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 858 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 859 | |||
| 860 | # | ||
| 861 | # SPI RTC drivers | ||
| 862 | # | ||
| 863 | |||
| 864 | # | ||
| 865 | # Platform RTC drivers | ||
| 866 | # | ||
| 867 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 868 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 869 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 870 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 871 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 872 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 873 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 874 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 875 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 876 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 877 | |||
| 878 | # | ||
| 879 | # on-CPU RTC drivers | ||
| 880 | # | ||
| 881 | CONFIG_RTC_DRV_BFIN=y | ||
| 882 | # CONFIG_DMADEVICES is not set | ||
| 883 | # CONFIG_UIO is not set | ||
| 884 | # CONFIG_STAGING is not set | ||
| 885 | |||
| 886 | # | ||
| 887 | # File systems | ||
| 888 | # | ||
| 889 | # CONFIG_EXT2_FS is not set | ||
| 890 | # CONFIG_EXT3_FS is not set | ||
| 891 | # CONFIG_EXT4_FS is not set | ||
| 892 | # CONFIG_REISERFS_FS is not set | ||
| 893 | # CONFIG_JFS_FS is not set | ||
| 894 | # CONFIG_FS_POSIX_ACL is not set | ||
| 895 | CONFIG_FILE_LOCKING=y | ||
| 896 | # CONFIG_XFS_FS is not set | ||
| 897 | # CONFIG_OCFS2_FS is not set | ||
| 898 | # CONFIG_DNOTIFY is not set | ||
| 899 | CONFIG_INOTIFY=y | ||
| 900 | CONFIG_INOTIFY_USER=y | ||
| 901 | # CONFIG_QUOTA is not set | ||
| 902 | # CONFIG_AUTOFS_FS is not set | ||
| 903 | # CONFIG_AUTOFS4_FS is not set | ||
| 904 | # CONFIG_FUSE_FS is not set | ||
| 905 | |||
| 906 | # | ||
| 907 | # CD-ROM/DVD Filesystems | ||
| 908 | # | ||
| 909 | # CONFIG_ISO9660_FS is not set | ||
| 910 | # CONFIG_UDF_FS is not set | ||
| 911 | |||
| 912 | # | ||
| 913 | # DOS/FAT/NT Filesystems | ||
| 914 | # | ||
| 915 | # CONFIG_MSDOS_FS is not set | ||
| 916 | # CONFIG_VFAT_FS is not set | ||
| 917 | # CONFIG_NTFS_FS is not set | ||
| 918 | |||
| 919 | # | ||
| 920 | # Pseudo filesystems | ||
| 921 | # | ||
| 922 | CONFIG_PROC_FS=y | ||
| 923 | CONFIG_PROC_SYSCTL=y | ||
| 924 | CONFIG_SYSFS=y | ||
| 925 | # CONFIG_TMPFS is not set | ||
| 926 | # CONFIG_HUGETLB_PAGE is not set | ||
| 927 | # CONFIG_CONFIGFS_FS is not set | ||
| 928 | |||
| 929 | # | ||
| 930 | # Miscellaneous filesystems | ||
| 931 | # | ||
| 932 | # CONFIG_ADFS_FS is not set | ||
| 933 | # CONFIG_AFFS_FS is not set | ||
| 934 | # CONFIG_HFS_FS is not set | ||
| 935 | # CONFIG_HFSPLUS_FS is not set | ||
| 936 | # CONFIG_BEFS_FS is not set | ||
| 937 | # CONFIG_BFS_FS is not set | ||
| 938 | # CONFIG_EFS_FS is not set | ||
| 939 | # CONFIG_YAFFS_FS is not set | ||
| 940 | # CONFIG_JFFS2_FS is not set | ||
| 941 | # CONFIG_CRAMFS is not set | ||
| 942 | # CONFIG_VXFS_FS is not set | ||
| 943 | # CONFIG_MINIX_FS is not set | ||
| 944 | # CONFIG_OMFS_FS is not set | ||
| 945 | # CONFIG_HPFS_FS is not set | ||
| 946 | # CONFIG_QNX4FS_FS is not set | ||
| 947 | # CONFIG_ROMFS_FS is not set | ||
| 948 | # CONFIG_SYSV_FS is not set | ||
| 949 | # CONFIG_UFS_FS is not set | ||
| 950 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 951 | CONFIG_NFS_FS=m | ||
| 952 | CONFIG_NFS_V3=y | ||
| 953 | # CONFIG_NFS_V3_ACL is not set | ||
| 954 | # CONFIG_NFS_V4 is not set | ||
| 955 | # CONFIG_NFSD is not set | ||
| 956 | CONFIG_LOCKD=m | ||
| 957 | CONFIG_LOCKD_V4=y | ||
| 958 | CONFIG_NFS_COMMON=y | ||
| 959 | CONFIG_SUNRPC=m | ||
| 960 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 961 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 962 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 963 | CONFIG_SMB_FS=m | ||
| 964 | # CONFIG_SMB_NLS_DEFAULT is not set | ||
| 965 | # CONFIG_CIFS is not set | ||
| 966 | # CONFIG_NCP_FS is not set | ||
| 967 | # CONFIG_CODA_FS is not set | ||
| 968 | # CONFIG_AFS_FS is not set | ||
| 969 | |||
| 970 | # | ||
| 971 | # Partition Types | ||
| 972 | # | ||
| 973 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 974 | CONFIG_MSDOS_PARTITION=y | ||
| 975 | CONFIG_NLS=y | ||
| 976 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 977 | CONFIG_NLS_CODEPAGE_437=y | ||
| 978 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 979 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 980 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 981 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 982 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 983 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 984 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 985 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 986 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 987 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 988 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 989 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 990 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 991 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 992 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 993 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 994 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 995 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 996 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 997 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 998 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 999 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1000 | # CONFIG_NLS_ASCII is not set | ||
| 1001 | CONFIG_NLS_ISO8859_1=y | ||
| 1002 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1003 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1004 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1005 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1006 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1007 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1008 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1009 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1010 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1011 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1012 | # CONFIG_NLS_KOI8_R is not set | ||
| 1013 | # CONFIG_NLS_KOI8_U is not set | ||
| 1014 | # CONFIG_NLS_UTF8 is not set | ||
| 1015 | # CONFIG_DLM is not set | ||
| 1016 | |||
| 1017 | # | ||
| 1018 | # Kernel hacking | ||
| 1019 | # | ||
| 1020 | # CONFIG_PRINTK_TIME is not set | ||
| 1021 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1022 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1023 | CONFIG_FRAME_WARN=1024 | ||
| 1024 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1025 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1026 | CONFIG_DEBUG_FS=y | ||
| 1027 | # CONFIG_HEADERS_CHECK is not set | ||
| 1028 | CONFIG_DEBUG_KERNEL=y | ||
| 1029 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1030 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1031 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1032 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1033 | CONFIG_SCHED_DEBUG=y | ||
| 1034 | # CONFIG_SCHEDSTATS is not set | ||
| 1035 | # CONFIG_TIMER_STATS is not set | ||
| 1036 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1037 | # CONFIG_DEBUG_SLAB is not set | ||
| 1038 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1039 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1040 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1041 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1042 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1043 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1044 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1045 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1046 | CONFIG_DEBUG_INFO=y | ||
| 1047 | # CONFIG_DEBUG_VM is not set | ||
| 1048 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1049 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1050 | # CONFIG_DEBUG_LIST is not set | ||
| 1051 | # CONFIG_DEBUG_SG is not set | ||
| 1052 | # CONFIG_FRAME_POINTER is not set | ||
| 1053 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1054 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1055 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1056 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1057 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1058 | # CONFIG_FAULT_INJECTION is not set | ||
| 1059 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1060 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1061 | # CONFIG_SAMPLES is not set | ||
| 1062 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1063 | # CONFIG_KGDB is not set | ||
| 1064 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1065 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1066 | CONFIG_DEBUG_VERBOSE=y | ||
| 1067 | CONFIG_DEBUG_MMRS=y | ||
| 1068 | # CONFIG_DEBUG_HWERR is not set | ||
| 1069 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 1070 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | ||
| 1071 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | ||
| 1072 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | ||
| 1073 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | ||
| 1074 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | ||
| 1075 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | ||
| 1076 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | ||
| 1077 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | ||
| 1078 | CONFIG_EARLY_PRINTK=y | ||
| 1079 | CONFIG_CPLB_INFO=y | ||
| 1080 | CONFIG_ACCESS_CHECK=y | ||
| 1081 | |||
| 1082 | # | ||
| 1083 | # Security options | ||
| 1084 | # | ||
| 1085 | # CONFIG_KEYS is not set | ||
| 1086 | CONFIG_SECURITY=y | ||
| 1087 | # CONFIG_SECURITYFS is not set | ||
| 1088 | # CONFIG_SECURITY_NETWORK is not set | ||
| 1089 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1090 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 1091 | CONFIG_CRYPTO=y | ||
| 1092 | |||
| 1093 | # | ||
| 1094 | # Crypto core or helper | ||
| 1095 | # | ||
| 1096 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1097 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1098 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1099 | # CONFIG_CRYPTO_NULL is not set | ||
| 1100 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1101 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1102 | # CONFIG_CRYPTO_TEST is not set | ||
| 1103 | |||
| 1104 | # | ||
| 1105 | # Authenticated Encryption with Associated Data | ||
| 1106 | # | ||
| 1107 | # CONFIG_CRYPTO_CCM is not set | ||
| 1108 | # CONFIG_CRYPTO_GCM is not set | ||
| 1109 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1110 | |||
| 1111 | # | ||
| 1112 | # Block modes | ||
| 1113 | # | ||
| 1114 | # CONFIG_CRYPTO_CBC is not set | ||
| 1115 | # CONFIG_CRYPTO_CTR is not set | ||
| 1116 | # CONFIG_CRYPTO_CTS is not set | ||
| 1117 | # CONFIG_CRYPTO_ECB is not set | ||
| 1118 | # CONFIG_CRYPTO_LRW is not set | ||
| 1119 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1120 | # CONFIG_CRYPTO_XTS is not set | ||
| 1121 | |||
| 1122 | # | ||
| 1123 | # Hash modes | ||
| 1124 | # | ||
| 1125 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1126 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1127 | |||
| 1128 | # | ||
| 1129 | # Digest | ||
| 1130 | # | ||
| 1131 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1132 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1133 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1134 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1135 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1136 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1137 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1138 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1139 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1140 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1141 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1142 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1143 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1144 | |||
| 1145 | # | ||
| 1146 | # Ciphers | ||
| 1147 | # | ||
| 1148 | # CONFIG_CRYPTO_AES is not set | ||
| 1149 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1150 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1151 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1152 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1153 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1154 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1155 | # CONFIG_CRYPTO_DES is not set | ||
| 1156 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1157 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1158 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1159 | # CONFIG_CRYPTO_SEED is not set | ||
| 1160 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1161 | # CONFIG_CRYPTO_TEA is not set | ||
| 1162 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1163 | |||
| 1164 | # | ||
| 1165 | # Compression | ||
| 1166 | # | ||
| 1167 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1168 | # CONFIG_CRYPTO_LZO is not set | ||
| 1169 | |||
| 1170 | # | ||
| 1171 | # Random Number Generation | ||
| 1172 | # | ||
| 1173 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1174 | CONFIG_CRYPTO_HW=y | ||
| 1175 | |||
| 1176 | # | ||
| 1177 | # Library routines | ||
| 1178 | # | ||
| 1179 | CONFIG_BITREVERSE=y | ||
| 1180 | CONFIG_CRC_CCITT=m | ||
| 1181 | # CONFIG_CRC16 is not set | ||
| 1182 | # CONFIG_CRC_T10DIF is not set | ||
| 1183 | # CONFIG_CRC_ITU_T is not set | ||
| 1184 | CONFIG_CRC32=y | ||
| 1185 | # CONFIG_CRC7 is not set | ||
| 1186 | # CONFIG_LIBCRC32C is not set | ||
| 1187 | CONFIG_ZLIB_INFLATE=y | ||
| 1188 | CONFIG_PLIST=y | ||
| 1189 | CONFIG_HAS_IOMEM=y | ||
| 1190 | CONFIG_HAS_IOPORT=y | ||
| 1191 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig index 4443a47e516f..69f66c35b2a5 100644 --- a/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/arch/blackfin/configs/BF526-EZBRD_defconfig | |||
| @@ -1,7 +1,6 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.26.3 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # Thu Aug 28 16:49:53 2008 | ||
| 5 | # | 4 | # |
| 6 | # CONFIG_MMU is not set | 5 | # CONFIG_MMU is not set |
| 7 | # CONFIG_FPU is not set | 6 | # CONFIG_FPU is not set |
| @@ -37,8 +36,7 @@ CONFIG_IKCONFIG_PROC=y | |||
| 37 | CONFIG_LOG_BUF_SHIFT=14 | 36 | CONFIG_LOG_BUF_SHIFT=14 |
| 38 | # CONFIG_CGROUPS is not set | 37 | # CONFIG_CGROUPS is not set |
| 39 | # CONFIG_GROUP_SCHED is not set | 38 | # CONFIG_GROUP_SCHED is not set |
| 40 | CONFIG_SYSFS_DEPRECATED=y | 39 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 41 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 42 | # CONFIG_RELAY is not set | 40 | # CONFIG_RELAY is not set |
| 43 | # CONFIG_NAMESPACES is not set | 41 | # CONFIG_NAMESPACES is not set |
| 44 | CONFIG_BLK_DEV_INITRD=y | 42 | CONFIG_BLK_DEV_INITRD=y |
| @@ -48,13 +46,13 @@ CONFIG_SYSCTL=y | |||
| 48 | CONFIG_EMBEDDED=y | 46 | CONFIG_EMBEDDED=y |
| 49 | CONFIG_UID16=y | 47 | CONFIG_UID16=y |
| 50 | CONFIG_SYSCTL_SYSCALL=y | 48 | CONFIG_SYSCTL_SYSCALL=y |
| 51 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 52 | CONFIG_KALLSYMS=y | 49 | CONFIG_KALLSYMS=y |
| 50 | # CONFIG_KALLSYMS_ALL is not set | ||
| 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 54 | CONFIG_HOTPLUG=y | 52 | CONFIG_HOTPLUG=y |
| 55 | CONFIG_PRINTK=y | 53 | CONFIG_PRINTK=y |
| 56 | CONFIG_BUG=y | 54 | CONFIG_BUG=y |
| 57 | CONFIG_ELF_CORE=y | 55 | # CONFIG_ELF_CORE is not set |
| 58 | CONFIG_COMPAT_BRK=y | 56 | CONFIG_COMPAT_BRK=y |
| 59 | CONFIG_BASE_FULL=y | 57 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 58 | CONFIG_FUTEX=y |
| @@ -63,6 +61,7 @@ CONFIG_EPOLL=y | |||
| 63 | CONFIG_SIGNALFD=y | 61 | CONFIG_SIGNALFD=y |
| 64 | CONFIG_TIMERFD=y | 62 | CONFIG_TIMERFD=y |
| 65 | CONFIG_EVENTFD=y | 63 | CONFIG_EVENTFD=y |
| 64 | CONFIG_AIO=y | ||
| 66 | CONFIG_VM_EVENT_COUNTERS=y | 65 | CONFIG_VM_EVENT_COUNTERS=y |
| 67 | CONFIG_SLAB=y | 66 | CONFIG_SLAB=y |
| 68 | # CONFIG_SLUB is not set | 67 | # CONFIG_SLUB is not set |
| @@ -70,9 +69,7 @@ CONFIG_SLAB=y | |||
| 70 | # CONFIG_PROFILING is not set | 69 | # CONFIG_PROFILING is not set |
| 71 | # CONFIG_MARKERS is not set | 70 | # CONFIG_MARKERS is not set |
| 72 | CONFIG_HAVE_OPROFILE=y | 71 | CONFIG_HAVE_OPROFILE=y |
| 73 | # CONFIG_HAVE_KPROBES is not set | 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 74 | # CONFIG_HAVE_KRETPROBES is not set | ||
| 75 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 76 | CONFIG_SLABINFO=y | 73 | CONFIG_SLABINFO=y |
| 77 | CONFIG_RT_MUTEXES=y | 74 | CONFIG_RT_MUTEXES=y |
| 78 | CONFIG_TINY_SHMEM=y | 75 | CONFIG_TINY_SHMEM=y |
| @@ -89,6 +86,7 @@ CONFIG_BLOCK=y | |||
| 89 | # CONFIG_BLK_DEV_IO_TRACE is not set | 86 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 90 | # CONFIG_LSF is not set | 87 | # CONFIG_LSF is not set |
| 91 | # CONFIG_BLK_DEV_BSG is not set | 88 | # CONFIG_BLK_DEV_BSG is not set |
| 89 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 92 | 90 | ||
| 93 | # | 91 | # |
| 94 | # IO Schedulers | 92 | # IO Schedulers |
| @@ -106,6 +104,7 @@ CONFIG_CLASSIC_RCU=y | |||
| 106 | # CONFIG_PREEMPT_NONE is not set | 104 | # CONFIG_PREEMPT_NONE is not set |
| 107 | CONFIG_PREEMPT_VOLUNTARY=y | 105 | CONFIG_PREEMPT_VOLUNTARY=y |
| 108 | # CONFIG_PREEMPT is not set | 106 | # CONFIG_PREEMPT is not set |
| 107 | # CONFIG_FREEZER is not set | ||
| 109 | 108 | ||
| 110 | # | 109 | # |
| 111 | # Blackfin Processor Options | 110 | # Blackfin Processor Options |
| @@ -114,6 +113,10 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 114 | # | 113 | # |
| 115 | # Processor and Board Settings | 114 | # Processor and Board Settings |
| 116 | # | 115 | # |
| 116 | # CONFIG_BF512 is not set | ||
| 117 | # CONFIG_BF514 is not set | ||
| 118 | # CONFIG_BF516 is not set | ||
| 119 | # CONFIG_BF518 is not set | ||
| 117 | # CONFIG_BF522 is not set | 120 | # CONFIG_BF522 is not set |
| 118 | # CONFIG_BF523 is not set | 121 | # CONFIG_BF523 is not set |
| 119 | # CONFIG_BF524 is not set | 122 | # CONFIG_BF524 is not set |
| @@ -126,49 +129,27 @@ CONFIG_BF526=y | |||
| 126 | # CONFIG_BF534 is not set | 129 | # CONFIG_BF534 is not set |
| 127 | # CONFIG_BF536 is not set | 130 | # CONFIG_BF536 is not set |
| 128 | # CONFIG_BF537 is not set | 131 | # CONFIG_BF537 is not set |
| 132 | # CONFIG_BF538 is not set | ||
| 133 | # CONFIG_BF539 is not set | ||
| 129 | # CONFIG_BF542 is not set | 134 | # CONFIG_BF542 is not set |
| 130 | # CONFIG_BF544 is not set | 135 | # CONFIG_BF544 is not set |
| 131 | # CONFIG_BF547 is not set | 136 | # CONFIG_BF547 is not set |
| 132 | # CONFIG_BF548 is not set | 137 | # CONFIG_BF548 is not set |
| 133 | # CONFIG_BF549 is not set | 138 | # CONFIG_BF549 is not set |
| 134 | # CONFIG_BF561 is not set | 139 | # CONFIG_BF561 is not set |
| 140 | CONFIG_BF_REV_MIN=0 | ||
| 141 | CONFIG_BF_REV_MAX=2 | ||
| 135 | CONFIG_BF_REV_0_0=y | 142 | CONFIG_BF_REV_0_0=y |
| 136 | # CONFIG_BF_REV_0_1 is not set | 143 | # CONFIG_BF_REV_0_1 is not set |
| 137 | # CONFIG_BF_REV_0_2 is not set | 144 | # CONFIG_BF_REV_0_2 is not set |
| 138 | # CONFIG_BF_REV_0_3 is not set | 145 | # CONFIG_BF_REV_0_3 is not set |
| 139 | # CONFIG_BF_REV_0_4 is not set | 146 | # CONFIG_BF_REV_0_4 is not set |
| 140 | # CONFIG_BF_REV_0_5 is not set | 147 | # CONFIG_BF_REV_0_5 is not set |
| 148 | # CONFIG_BF_REV_0_6 is not set | ||
| 141 | # CONFIG_BF_REV_ANY is not set | 149 | # CONFIG_BF_REV_ANY is not set |
| 142 | # CONFIG_BF_REV_NONE is not set | 150 | # CONFIG_BF_REV_NONE is not set |
| 143 | CONFIG_BF52x=y | 151 | CONFIG_BF52x=y |
| 144 | CONFIG_MEM_MT48LC32M16A2TG_75=y | 152 | CONFIG_MEM_MT48LC32M16A2TG_75=y |
| 145 | # CONFIG_BFIN527_EZKIT is not set | ||
| 146 | # CONFIG_BFIN527_BLUETECHNIX_CM is not set | ||
| 147 | CONFIG_BFIN526_EZBRD=y | ||
| 148 | |||
| 149 | # | ||
| 150 | # BF527 Specific Configuration | ||
| 151 | # | ||
| 152 | |||
| 153 | # | ||
| 154 | # Alternative Multiplexing Scheme | ||
| 155 | # | ||
| 156 | # CONFIG_BF527_SPORT0_PORTF is not set | ||
| 157 | CONFIG_BF527_SPORT0_PORTG=y | ||
| 158 | CONFIG_BF527_SPORT0_TSCLK_PG10=y | ||
| 159 | # CONFIG_BF527_SPORT0_TSCLK_PG14 is not set | ||
| 160 | CONFIG_BF527_UART1_PORTF=y | ||
| 161 | # CONFIG_BF527_UART1_PORTG is not set | ||
| 162 | # CONFIG_BF527_NAND_D_PORTF is not set | ||
| 163 | CONFIG_BF527_NAND_D_PORTH=y | ||
| 164 | |||
| 165 | # | ||
| 166 | # Interrupt Priority Assignment | ||
| 167 | # | ||
| 168 | |||
| 169 | # | ||
| 170 | # Priority | ||
| 171 | # | ||
| 172 | CONFIG_IRQ_PLL_WAKEUP=7 | 153 | CONFIG_IRQ_PLL_WAKEUP=7 |
| 173 | CONFIG_IRQ_DMA0_ERROR=7 | 154 | CONFIG_IRQ_DMA0_ERROR=7 |
| 174 | CONFIG_IRQ_DMAR0_BLK=7 | 155 | CONFIG_IRQ_DMAR0_BLK=7 |
| @@ -188,7 +169,6 @@ CONFIG_IRQ_SPORT0_TX=9 | |||
| 188 | CONFIG_IRQ_SPORT1_RX=9 | 169 | CONFIG_IRQ_SPORT1_RX=9 |
| 189 | CONFIG_IRQ_SPORT1_TX=9 | 170 | CONFIG_IRQ_SPORT1_TX=9 |
| 190 | CONFIG_IRQ_TWI=10 | 171 | CONFIG_IRQ_TWI=10 |
| 191 | CONFIG_IRQ_SPI=10 | ||
| 192 | CONFIG_IRQ_UART0_RX=10 | 172 | CONFIG_IRQ_UART0_RX=10 |
| 193 | CONFIG_IRQ_UART0_TX=10 | 173 | CONFIG_IRQ_UART0_TX=10 |
| 194 | CONFIG_IRQ_UART1_RX=10 | 174 | CONFIG_IRQ_UART1_RX=10 |
| @@ -199,14 +179,14 @@ CONFIG_IRQ_MAC_RX=11 | |||
| 199 | CONFIG_IRQ_PORTH_INTA=11 | 179 | CONFIG_IRQ_PORTH_INTA=11 |
| 200 | CONFIG_IRQ_MAC_TX=11 | 180 | CONFIG_IRQ_MAC_TX=11 |
| 201 | CONFIG_IRQ_PORTH_INTB=11 | 181 | CONFIG_IRQ_PORTH_INTB=11 |
| 202 | CONFIG_IRQ_TMR0=12 | 182 | CONFIG_IRQ_TIMER0=12 |
| 203 | CONFIG_IRQ_TMR1=12 | 183 | CONFIG_IRQ_TIMER1=12 |
| 204 | CONFIG_IRQ_TMR2=12 | 184 | CONFIG_IRQ_TIMER2=12 |
| 205 | CONFIG_IRQ_TMR3=12 | 185 | CONFIG_IRQ_TIMER3=12 |
| 206 | CONFIG_IRQ_TMR4=12 | 186 | CONFIG_IRQ_TIMER4=12 |
| 207 | CONFIG_IRQ_TMR5=12 | 187 | CONFIG_IRQ_TIMER5=12 |
| 208 | CONFIG_IRQ_TMR6=12 | 188 | CONFIG_IRQ_TIMER6=12 |
| 209 | CONFIG_IRQ_TMR7=12 | 189 | CONFIG_IRQ_TIMER7=12 |
| 210 | CONFIG_IRQ_PORTG_INTA=12 | 190 | CONFIG_IRQ_PORTG_INTA=12 |
| 211 | CONFIG_IRQ_PORTG_INTB=12 | 191 | CONFIG_IRQ_PORTG_INTB=12 |
| 212 | CONFIG_IRQ_MEM_DMA0=13 | 192 | CONFIG_IRQ_MEM_DMA0=13 |
| @@ -214,6 +194,34 @@ CONFIG_IRQ_MEM_DMA1=13 | |||
| 214 | CONFIG_IRQ_WATCH=13 | 194 | CONFIG_IRQ_WATCH=13 |
| 215 | CONFIG_IRQ_PORTF_INTA=13 | 195 | CONFIG_IRQ_PORTF_INTA=13 |
| 216 | CONFIG_IRQ_PORTF_INTB=13 | 196 | CONFIG_IRQ_PORTF_INTB=13 |
| 197 | # CONFIG_BFIN527_EZKIT is not set | ||
| 198 | # CONFIG_BFIN527_BLUETECHNIX_CM is not set | ||
| 199 | CONFIG_BFIN526_EZBRD=y | ||
| 200 | |||
| 201 | # | ||
| 202 | # BF527 Specific Configuration | ||
| 203 | # | ||
| 204 | |||
| 205 | # | ||
| 206 | # Alternative Multiplexing Scheme | ||
| 207 | # | ||
| 208 | # CONFIG_BF527_SPORT0_PORTF is not set | ||
| 209 | CONFIG_BF527_SPORT0_PORTG=y | ||
| 210 | CONFIG_BF527_SPORT0_TSCLK_PG10=y | ||
| 211 | # CONFIG_BF527_SPORT0_TSCLK_PG14 is not set | ||
| 212 | CONFIG_BF527_UART1_PORTF=y | ||
| 213 | # CONFIG_BF527_UART1_PORTG is not set | ||
| 214 | # CONFIG_BF527_NAND_D_PORTF is not set | ||
| 215 | CONFIG_BF527_NAND_D_PORTH=y | ||
| 216 | |||
| 217 | # | ||
| 218 | # Interrupt Priority Assignment | ||
| 219 | # | ||
| 220 | |||
| 221 | # | ||
| 222 | # Priority | ||
| 223 | # | ||
| 224 | CONFIG_IRQ_SPI=10 | ||
| 217 | CONFIG_IRQ_SPI_ERROR=7 | 225 | CONFIG_IRQ_SPI_ERROR=7 |
| 218 | CONFIG_IRQ_NFC_ERROR=7 | 226 | CONFIG_IRQ_NFC_ERROR=7 |
| 219 | CONFIG_IRQ_HDMA_ERROR=7 | 227 | CONFIG_IRQ_HDMA_ERROR=7 |
| @@ -235,7 +243,6 @@ CONFIG_BOOT_LOAD=0x1000 | |||
| 235 | # | 243 | # |
| 236 | CONFIG_CLKIN_HZ=25000000 | 244 | CONFIG_CLKIN_HZ=25000000 |
| 237 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 245 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 238 | CONFIG_MAX_MEM_SIZE=512 | ||
| 239 | CONFIG_MAX_VCO_HZ=400000000 | 246 | CONFIG_MAX_VCO_HZ=400000000 |
| 240 | CONFIG_MIN_VCO_HZ=50000000 | 247 | CONFIG_MIN_VCO_HZ=50000000 |
| 241 | CONFIG_MAX_SCLK_HZ=133333333 | 248 | CONFIG_MAX_SCLK_HZ=133333333 |
| @@ -253,16 +260,11 @@ CONFIG_HZ=250 | |||
| 253 | CONFIG_GENERIC_TIME=y | 260 | CONFIG_GENERIC_TIME=y |
| 254 | CONFIG_GENERIC_CLOCKEVENTS=y | 261 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 255 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 262 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 256 | # CONFIG_TICK_ONESHOT is not set | ||
| 257 | # CONFIG_NO_HZ is not set | 263 | # CONFIG_NO_HZ is not set |
| 258 | # CONFIG_HIGH_RES_TIMERS is not set | 264 | # CONFIG_HIGH_RES_TIMERS is not set |
| 259 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 265 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 260 | 266 | ||
| 261 | # | 267 | # |
| 262 | # Memory Setup | ||
| 263 | # | ||
| 264 | |||
| 265 | # | ||
| 266 | # Misc | 268 | # Misc |
| 267 | # | 269 | # |
| 268 | CONFIG_BFIN_SCRATCH_REG_RETN=y | 270 | CONFIG_BFIN_SCRATCH_REG_RETN=y |
| @@ -291,6 +293,7 @@ CONFIG_ACCESS_OK_L1=y | |||
| 291 | CONFIG_CACHELINE_ALIGNED_L1=y | 293 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 292 | # CONFIG_SYSCALL_TAB_L1 is not set | 294 | # CONFIG_SYSCALL_TAB_L1 is not set |
| 293 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | 295 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set |
| 296 | CONFIG_APP_STACK_L1=y | ||
| 294 | 297 | ||
| 295 | # | 298 | # |
| 296 | # Speed Optimizations | 299 | # Speed Optimizations |
| @@ -304,15 +307,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 304 | # CONFIG_SPARSEMEM_MANUAL is not set | 307 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 305 | CONFIG_FLATMEM=y | 308 | CONFIG_FLATMEM=y |
| 306 | CONFIG_FLAT_NODE_MEM_MAP=y | 309 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 307 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 308 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 309 | CONFIG_PAGEFLAGS_EXTENDED=y | 310 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 310 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 311 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 311 | # CONFIG_RESOURCES_64BIT is not set | 312 | # CONFIG_RESOURCES_64BIT is not set |
| 313 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 312 | CONFIG_ZONE_DMA_FLAG=1 | 314 | CONFIG_ZONE_DMA_FLAG=1 |
| 313 | CONFIG_VIRT_TO_BUS=y | 315 | CONFIG_VIRT_TO_BUS=y |
| 314 | CONFIG_BFIN_GPTIMERS=y | 316 | CONFIG_BFIN_GPTIMERS=y |
| 315 | CONFIG_BFIN_DMA_5XX=y | ||
| 316 | # CONFIG_DMA_UNCACHED_4M is not set | 317 | # CONFIG_DMA_UNCACHED_4M is not set |
| 317 | # CONFIG_DMA_UNCACHED_2M is not set | 318 | # CONFIG_DMA_UNCACHED_2M is not set |
| 318 | CONFIG_DMA_UNCACHED_1M=y | 319 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -365,6 +366,7 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 365 | CONFIG_BINFMT_FLAT=y | 366 | CONFIG_BINFMT_FLAT=y |
| 366 | CONFIG_BINFMT_ZFLAT=y | 367 | CONFIG_BINFMT_ZFLAT=y |
| 367 | # CONFIG_BINFMT_SHARED_FLAT is not set | 368 | # CONFIG_BINFMT_SHARED_FLAT is not set |
| 369 | # CONFIG_HAVE_AOUT is not set | ||
| 368 | # CONFIG_BINFMT_MISC is not set | 370 | # CONFIG_BINFMT_MISC is not set |
| 369 | 371 | ||
| 370 | # | 372 | # |
| @@ -378,10 +380,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y | |||
| 378 | # CPU Frequency scaling | 380 | # CPU Frequency scaling |
| 379 | # | 381 | # |
| 380 | # CONFIG_CPU_FREQ is not set | 382 | # CONFIG_CPU_FREQ is not set |
| 381 | |||
| 382 | # | ||
| 383 | # Networking | ||
| 384 | # | ||
| 385 | CONFIG_NET=y | 383 | CONFIG_NET=y |
| 386 | 384 | ||
| 387 | # | 385 | # |
| @@ -432,6 +430,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 432 | # CONFIG_TIPC is not set | 430 | # CONFIG_TIPC is not set |
| 433 | # CONFIG_ATM is not set | 431 | # CONFIG_ATM is not set |
| 434 | # CONFIG_BRIDGE is not set | 432 | # CONFIG_BRIDGE is not set |
| 433 | # CONFIG_NET_DSA is not set | ||
| 435 | # CONFIG_VLAN_8021Q is not set | 434 | # CONFIG_VLAN_8021Q is not set |
| 436 | # CONFIG_DECNET is not set | 435 | # CONFIG_DECNET is not set |
| 437 | # CONFIG_LLC2 is not set | 436 | # CONFIG_LLC2 is not set |
| @@ -452,11 +451,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 452 | # CONFIG_IRDA is not set | 451 | # CONFIG_IRDA is not set |
| 453 | # CONFIG_BT is not set | 452 | # CONFIG_BT is not set |
| 454 | # CONFIG_AF_RXRPC is not set | 453 | # CONFIG_AF_RXRPC is not set |
| 455 | 454 | # CONFIG_PHONET is not set | |
| 456 | # | 455 | CONFIG_WIRELESS=y |
| 457 | # Wireless | ||
| 458 | # | ||
| 459 | # CONFIG_CFG80211 is not set | 456 | # CONFIG_CFG80211 is not set |
| 457 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 460 | # CONFIG_WIRELESS_EXT is not set | 458 | # CONFIG_WIRELESS_EXT is not set |
| 461 | # CONFIG_MAC80211 is not set | 459 | # CONFIG_MAC80211 is not set |
| 462 | # CONFIG_IEEE80211 is not set | 460 | # CONFIG_IEEE80211 is not set |
| @@ -474,6 +472,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 474 | CONFIG_STANDALONE=y | 472 | CONFIG_STANDALONE=y |
| 475 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 473 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 476 | # CONFIG_FW_LOADER is not set | 474 | # CONFIG_FW_LOADER is not set |
| 475 | # CONFIG_DEBUG_DRIVER is not set | ||
| 476 | # CONFIG_DEBUG_DEVRES is not set | ||
| 477 | # CONFIG_SYS_HYPERVISOR is not set | 477 | # CONFIG_SYS_HYPERVISOR is not set |
| 478 | # CONFIG_CONNECTOR is not set | 478 | # CONFIG_CONNECTOR is not set |
| 479 | CONFIG_MTD=y | 479 | CONFIG_MTD=y |
| @@ -534,7 +534,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y | |||
| 534 | # Self-contained MTD device drivers | 534 | # Self-contained MTD device drivers |
| 535 | # | 535 | # |
| 536 | # CONFIG_MTD_DATAFLASH is not set | 536 | # CONFIG_MTD_DATAFLASH is not set |
| 537 | # CONFIG_MTD_M25P80 is not set | 537 | CONFIG_MTD_M25P80=y |
| 538 | CONFIG_M25PXX_USE_FAST_READ=y | ||
| 538 | # CONFIG_MTD_SLRAM is not set | 539 | # CONFIG_MTD_SLRAM is not set |
| 539 | # CONFIG_MTD_PHRAM is not set | 540 | # CONFIG_MTD_PHRAM is not set |
| 540 | # CONFIG_MTD_MTDRAM is not set | 541 | # CONFIG_MTD_MTDRAM is not set |
| @@ -579,6 +580,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 | |||
| 579 | # CONFIG_BLK_DEV_XIP is not set | 580 | # CONFIG_BLK_DEV_XIP is not set |
| 580 | # CONFIG_CDROM_PKTCDVD is not set | 581 | # CONFIG_CDROM_PKTCDVD is not set |
| 581 | # CONFIG_ATA_OVER_ETH is not set | 582 | # CONFIG_ATA_OVER_ETH is not set |
| 583 | # CONFIG_BLK_DEV_HD is not set | ||
| 582 | CONFIG_MISC_DEVICES=y | 584 | CONFIG_MISC_DEVICES=y |
| 583 | # CONFIG_EEPROM_93CX6 is not set | 585 | # CONFIG_EEPROM_93CX6 is not set |
| 584 | # CONFIG_ENCLOSURE_SERVICES is not set | 586 | # CONFIG_ENCLOSURE_SERVICES is not set |
| @@ -595,7 +597,6 @@ CONFIG_HAVE_IDE=y | |||
| 595 | # CONFIG_ATA is not set | 597 | # CONFIG_ATA is not set |
| 596 | # CONFIG_MD is not set | 598 | # CONFIG_MD is not set |
| 597 | CONFIG_NETDEVICES=y | 599 | CONFIG_NETDEVICES=y |
| 598 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 599 | # CONFIG_DUMMY is not set | 600 | # CONFIG_DUMMY is not set |
| 600 | # CONFIG_BONDING is not set | 601 | # CONFIG_BONDING is not set |
| 601 | # CONFIG_MACVLAN is not set | 602 | # CONFIG_MACVLAN is not set |
| @@ -633,9 +634,10 @@ CONFIG_BFIN_MAC_RMII=y | |||
| 633 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 634 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 634 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 635 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 635 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 636 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 636 | # CONFIG_B44 is not set | 637 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set |
| 638 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 639 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 637 | CONFIG_NETDEV_1000=y | 640 | CONFIG_NETDEV_1000=y |
| 638 | # CONFIG_E1000E_ENABLED is not set | ||
| 639 | # CONFIG_AX88180 is not set | 641 | # CONFIG_AX88180 is not set |
| 640 | CONFIG_NETDEV_10000=y | 642 | CONFIG_NETDEV_10000=y |
| 641 | 643 | ||
| @@ -667,7 +669,7 @@ CONFIG_NETDEV_10000=y | |||
| 667 | # Input device support | 669 | # Input device support |
| 668 | # | 670 | # |
| 669 | CONFIG_INPUT=y | 671 | CONFIG_INPUT=y |
| 670 | # CONFIG_INPUT_FF_MEMLESS is not set | 672 | CONFIG_INPUT_FF_MEMLESS=m |
| 671 | # CONFIG_INPUT_POLLDEV is not set | 673 | # CONFIG_INPUT_POLLDEV is not set |
| 672 | 674 | ||
| 673 | # | 675 | # |
| @@ -692,8 +694,9 @@ CONFIG_INPUT_MISC=y | |||
| 692 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | 694 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set |
| 693 | # CONFIG_INPUT_POWERMATE is not set | 695 | # CONFIG_INPUT_POWERMATE is not set |
| 694 | # CONFIG_INPUT_YEALINK is not set | 696 | # CONFIG_INPUT_YEALINK is not set |
| 697 | # CONFIG_INPUT_CM109 is not set | ||
| 695 | # CONFIG_INPUT_UINPUT is not set | 698 | # CONFIG_INPUT_UINPUT is not set |
| 696 | # CONFIG_TWI_KEYPAD is not set | 699 | # CONFIG_CONFIG_INPUT_PCF8574 is not set |
| 697 | 700 | ||
| 698 | # | 701 | # |
| 699 | # Hardware I/O ports | 702 | # Hardware I/O ports |
| @@ -712,12 +715,15 @@ CONFIG_INPUT_MISC=y | |||
| 712 | # CONFIG_BFIN_SPORT is not set | 715 | # CONFIG_BFIN_SPORT is not set |
| 713 | # CONFIG_BFIN_TIMER_LATENCY is not set | 716 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 714 | # CONFIG_TWI_LCD is not set | 717 | # CONFIG_TWI_LCD is not set |
| 718 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 715 | CONFIG_SIMPLE_GPIO=m | 719 | CONFIG_SIMPLE_GPIO=m |
| 716 | CONFIG_VT=y | 720 | CONFIG_VT=y |
| 721 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 717 | CONFIG_VT_CONSOLE=y | 722 | CONFIG_VT_CONSOLE=y |
| 718 | CONFIG_HW_CONSOLE=y | 723 | CONFIG_HW_CONSOLE=y |
| 719 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 724 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 720 | CONFIG_DEVKMEM=y | 725 | # CONFIG_DEVKMEM is not set |
| 726 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 721 | # CONFIG_SERIAL_NONSTANDARD is not set | 727 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 722 | 728 | ||
| 723 | # | 729 | # |
| @@ -760,25 +766,39 @@ CONFIG_I2C_HELPER_AUTO=y | |||
| 760 | # | 766 | # |
| 761 | # I2C Hardware Bus support | 767 | # I2C Hardware Bus support |
| 762 | # | 768 | # |
| 769 | |||
| 770 | # | ||
| 771 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 772 | # | ||
| 763 | CONFIG_I2C_BLACKFIN_TWI=y | 773 | CONFIG_I2C_BLACKFIN_TWI=y |
| 764 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | 774 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 |
| 765 | # CONFIG_I2C_GPIO is not set | 775 | # CONFIG_I2C_GPIO is not set |
| 766 | # CONFIG_I2C_OCORES is not set | 776 | # CONFIG_I2C_OCORES is not set |
| 767 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 768 | # CONFIG_I2C_SIMTEC is not set | 777 | # CONFIG_I2C_SIMTEC is not set |
| 778 | |||
| 779 | # | ||
| 780 | # External I2C/SMBus adapter drivers | ||
| 781 | # | ||
| 782 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 769 | # CONFIG_I2C_TAOS_EVM is not set | 783 | # CONFIG_I2C_TAOS_EVM is not set |
| 770 | # CONFIG_I2C_STUB is not set | ||
| 771 | # CONFIG_I2C_TINY_USB is not set | 784 | # CONFIG_I2C_TINY_USB is not set |
| 785 | |||
| 786 | # | ||
| 787 | # Other I2C/SMBus bus drivers | ||
| 788 | # | ||
| 772 | # CONFIG_I2C_PCA_PLATFORM is not set | 789 | # CONFIG_I2C_PCA_PLATFORM is not set |
| 790 | # CONFIG_I2C_STUB is not set | ||
| 773 | 791 | ||
| 774 | # | 792 | # |
| 775 | # Miscellaneous I2C Chip support | 793 | # Miscellaneous I2C Chip support |
| 776 | # | 794 | # |
| 777 | # CONFIG_DS1682 is not set | 795 | # CONFIG_DS1682 is not set |
| 796 | # CONFIG_AT24 is not set | ||
| 778 | # CONFIG_SENSORS_AD5252 is not set | 797 | # CONFIG_SENSORS_AD5252 is not set |
| 779 | # CONFIG_SENSORS_EEPROM is not set | 798 | # CONFIG_SENSORS_EEPROM is not set |
| 780 | # CONFIG_SENSORS_PCF8574 is not set | 799 | # CONFIG_SENSORS_PCF8574 is not set |
| 781 | # CONFIG_PCF8575 is not set | 800 | # CONFIG_PCF8575 is not set |
| 801 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 782 | # CONFIG_SENSORS_PCF8591 is not set | 802 | # CONFIG_SENSORS_PCF8591 is not set |
| 783 | # CONFIG_SENSORS_MAX6875 is not set | 803 | # CONFIG_SENSORS_MAX6875 is not set |
| 784 | # CONFIG_SENSORS_TSL2550 is not set | 804 | # CONFIG_SENSORS_TSL2550 is not set |
| @@ -787,12 +807,14 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | |||
| 787 | # CONFIG_I2C_DEBUG_BUS is not set | 807 | # CONFIG_I2C_DEBUG_BUS is not set |
| 788 | # CONFIG_I2C_DEBUG_CHIP is not set | 808 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 789 | CONFIG_SPI=y | 809 | CONFIG_SPI=y |
| 810 | # CONFIG_SPI_DEBUG is not set | ||
| 790 | CONFIG_SPI_MASTER=y | 811 | CONFIG_SPI_MASTER=y |
| 791 | 812 | ||
| 792 | # | 813 | # |
| 793 | # SPI Master Controller Drivers | 814 | # SPI Master Controller Drivers |
| 794 | # | 815 | # |
| 795 | CONFIG_SPI_BFIN=y | 816 | CONFIG_SPI_BFIN=y |
| 817 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 796 | # CONFIG_SPI_BITBANG is not set | 818 | # CONFIG_SPI_BITBANG is not set |
| 797 | 819 | ||
| 798 | # | 820 | # |
| @@ -801,11 +823,15 @@ CONFIG_SPI_BFIN=y | |||
| 801 | # CONFIG_SPI_AT25 is not set | 823 | # CONFIG_SPI_AT25 is not set |
| 802 | # CONFIG_SPI_SPIDEV is not set | 824 | # CONFIG_SPI_SPIDEV is not set |
| 803 | # CONFIG_SPI_TLE62X0 is not set | 825 | # CONFIG_SPI_TLE62X0 is not set |
| 826 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 827 | # CONFIG_GPIOLIB is not set | ||
| 804 | # CONFIG_W1 is not set | 828 | # CONFIG_W1 is not set |
| 805 | # CONFIG_POWER_SUPPLY is not set | 829 | # CONFIG_POWER_SUPPLY is not set |
| 806 | CONFIG_HWMON=y | 830 | CONFIG_HWMON=y |
| 807 | # CONFIG_HWMON_VID is not set | 831 | # CONFIG_HWMON_VID is not set |
| 832 | # CONFIG_SENSORS_AD7414 is not set | ||
| 808 | # CONFIG_SENSORS_AD7418 is not set | 833 | # CONFIG_SENSORS_AD7418 is not set |
| 834 | # CONFIG_SENSORS_ADCXX is not set | ||
| 809 | # CONFIG_SENSORS_ADM1021 is not set | 835 | # CONFIG_SENSORS_ADM1021 is not set |
| 810 | # CONFIG_SENSORS_ADM1025 is not set | 836 | # CONFIG_SENSORS_ADM1025 is not set |
| 811 | # CONFIG_SENSORS_ADM1026 is not set | 837 | # CONFIG_SENSORS_ADM1026 is not set |
| @@ -834,6 +860,7 @@ CONFIG_HWMON=y | |||
| 834 | # CONFIG_SENSORS_LM90 is not set | 860 | # CONFIG_SENSORS_LM90 is not set |
| 835 | # CONFIG_SENSORS_LM92 is not set | 861 | # CONFIG_SENSORS_LM92 is not set |
| 836 | # CONFIG_SENSORS_LM93 is not set | 862 | # CONFIG_SENSORS_LM93 is not set |
| 863 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 837 | # CONFIG_SENSORS_MAX1619 is not set | 864 | # CONFIG_SENSORS_MAX1619 is not set |
| 838 | # CONFIG_SENSORS_MAX6650 is not set | 865 | # CONFIG_SENSORS_MAX6650 is not set |
| 839 | # CONFIG_SENSORS_PC87360 is not set | 866 | # CONFIG_SENSORS_PC87360 is not set |
| @@ -871,16 +898,14 @@ CONFIG_BFIN_WDT=y | |||
| 871 | # CONFIG_USBPCWATCHDOG is not set | 898 | # CONFIG_USBPCWATCHDOG is not set |
| 872 | 899 | ||
| 873 | # | 900 | # |
| 874 | # Sonics Silicon Backplane | ||
| 875 | # | ||
| 876 | CONFIG_SSB_POSSIBLE=y | ||
| 877 | # CONFIG_SSB is not set | ||
| 878 | |||
| 879 | # | ||
| 880 | # Multifunction device drivers | 901 | # Multifunction device drivers |
| 881 | # | 902 | # |
| 903 | # CONFIG_MFD_CORE is not set | ||
| 882 | # CONFIG_MFD_SM501 is not set | 904 | # CONFIG_MFD_SM501 is not set |
| 883 | # CONFIG_HTC_PASIC3 is not set | 905 | # CONFIG_HTC_PASIC3 is not set |
| 906 | # CONFIG_MFD_TMIO is not set | ||
| 907 | # CONFIG_MFD_WM8400 is not set | ||
| 908 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 884 | 909 | ||
| 885 | # | 910 | # |
| 886 | # Multimedia devices | 911 | # Multimedia devices |
| @@ -915,15 +940,8 @@ CONFIG_SSB_POSSIBLE=y | |||
| 915 | # Console display driver support | 940 | # Console display driver support |
| 916 | # | 941 | # |
| 917 | CONFIG_DUMMY_CONSOLE=y | 942 | CONFIG_DUMMY_CONSOLE=y |
| 918 | |||
| 919 | # | ||
| 920 | # Sound | ||
| 921 | # | ||
| 922 | CONFIG_SOUND=m | 943 | CONFIG_SOUND=m |
| 923 | 944 | CONFIG_SOUND_OSS_CORE=y | |
| 924 | # | ||
| 925 | # Advanced Linux Sound Architecture | ||
| 926 | # | ||
| 927 | CONFIG_SND=m | 945 | CONFIG_SND=m |
| 928 | CONFIG_SND_TIMER=m | 946 | CONFIG_SND_TIMER=m |
| 929 | CONFIG_SND_PCM=m | 947 | CONFIG_SND_PCM=m |
| @@ -937,56 +955,40 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 937 | CONFIG_SND_VERBOSE_PROCFS=y | 955 | CONFIG_SND_VERBOSE_PROCFS=y |
| 938 | # CONFIG_SND_VERBOSE_PRINTK is not set | 956 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 939 | # CONFIG_SND_DEBUG is not set | 957 | # CONFIG_SND_DEBUG is not set |
| 940 | 958 | CONFIG_SND_DRIVERS=y | |
| 941 | # | ||
| 942 | # Generic devices | ||
| 943 | # | ||
| 944 | # CONFIG_SND_DUMMY is not set | 959 | # CONFIG_SND_DUMMY is not set |
| 945 | # CONFIG_SND_MTPAV is not set | 960 | # CONFIG_SND_MTPAV is not set |
| 946 | # CONFIG_SND_SERIAL_U16550 is not set | 961 | # CONFIG_SND_SERIAL_U16550 is not set |
| 947 | # CONFIG_SND_MPU401 is not set | 962 | # CONFIG_SND_MPU401 is not set |
| 948 | 963 | CONFIG_SND_SPI=y | |
| 949 | # | ||
| 950 | # SPI devices | ||
| 951 | # | ||
| 952 | 964 | ||
| 953 | # | 965 | # |
| 954 | # ALSA Blackfin devices | 966 | # ALSA Blackfin devices |
| 955 | # | 967 | # |
| 956 | # CONFIG_SND_BLACKFIN_AD1836 is not set | 968 | # CONFIG_SND_BLACKFIN_AD1836 is not set |
| 957 | # CONFIG_SND_BFIN_AD73311 is not set | ||
| 958 | # CONFIG_SND_BFIN_AD73322 is not set | 969 | # CONFIG_SND_BFIN_AD73322 is not set |
| 959 | 970 | CONFIG_SND_USB=y | |
| 960 | # | ||
| 961 | # USB devices | ||
| 962 | # | ||
| 963 | # CONFIG_SND_USB_AUDIO is not set | 971 | # CONFIG_SND_USB_AUDIO is not set |
| 964 | # CONFIG_SND_USB_CAIAQ is not set | 972 | # CONFIG_SND_USB_CAIAQ is not set |
| 965 | |||
| 966 | # | ||
| 967 | # System on Chip audio support | ||
| 968 | # | ||
| 969 | CONFIG_SND_SOC=m | 973 | CONFIG_SND_SOC=m |
| 974 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 970 | CONFIG_SND_BF5XX_I2S=m | 975 | CONFIG_SND_BF5XX_I2S=m |
| 971 | CONFIG_SND_BF5XX_SOC_SSM2602=m | 976 | CONFIG_SND_BF5XX_SOC_SSM2602=m |
| 972 | # CONFIG_SND_BF5XX_AC97 is not set | 977 | # CONFIG_SND_BF5XX_SOC_AD73311 is not set |
| 978 | CONFIG_SND_BF5XX_AC97=m | ||
| 979 | CONFIG_SND_BF5XX_MMAP_SUPPORT=y | ||
| 980 | # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set | ||
| 973 | CONFIG_SND_BF5XX_SOC_SPORT=m | 981 | CONFIG_SND_BF5XX_SOC_SPORT=m |
| 974 | CONFIG_SND_BF5XX_SOC_I2S=m | 982 | CONFIG_SND_BF5XX_SOC_I2S=m |
| 983 | CONFIG_SND_BF5XX_SOC_AC97=m | ||
| 984 | CONFIG_SND_BF5XX_SOC_AD1980=m | ||
| 975 | CONFIG_SND_BF5XX_SPORT_NUM=0 | 985 | CONFIG_SND_BF5XX_SPORT_NUM=0 |
| 976 | 986 | # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set | |
| 977 | # | 987 | # CONFIG_SND_SOC_ALL_CODECS is not set |
| 978 | # ALSA SoC audio for Freescale SOCs | 988 | CONFIG_SND_SOC_AD1980=m |
| 979 | # | ||
| 980 | |||
| 981 | # | ||
| 982 | # SoC Audio for the Texas Instruments OMAP | ||
| 983 | # | ||
| 984 | CONFIG_SND_SOC_SSM2602=m | 989 | CONFIG_SND_SOC_SSM2602=m |
| 985 | |||
| 986 | # | ||
| 987 | # Open Sound System | ||
| 988 | # | ||
| 989 | # CONFIG_SOUND_PRIME is not set | 990 | # CONFIG_SOUND_PRIME is not set |
| 991 | CONFIG_AC97_BUS=m | ||
| 990 | CONFIG_HID_SUPPORT=y | 992 | CONFIG_HID_SUPPORT=y |
| 991 | CONFIG_HID=y | 993 | CONFIG_HID=y |
| 992 | # CONFIG_HID_DEBUG is not set | 994 | # CONFIG_HID_DEBUG is not set |
| @@ -996,9 +998,36 @@ CONFIG_HID=y | |||
| 996 | # USB Input Devices | 998 | # USB Input Devices |
| 997 | # | 999 | # |
| 998 | CONFIG_USB_HID=y | 1000 | CONFIG_USB_HID=y |
| 999 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | 1001 | # CONFIG_HID_PID is not set |
| 1000 | # CONFIG_HID_FF is not set | ||
| 1001 | # CONFIG_USB_HIDDEV is not set | 1002 | # CONFIG_USB_HIDDEV is not set |
| 1003 | |||
| 1004 | # | ||
| 1005 | # Special HID drivers | ||
| 1006 | # | ||
| 1007 | CONFIG_HID_COMPAT=y | ||
| 1008 | CONFIG_HID_A4TECH=y | ||
| 1009 | CONFIG_HID_APPLE=y | ||
| 1010 | CONFIG_HID_BELKIN=y | ||
| 1011 | CONFIG_HID_BRIGHT=y | ||
| 1012 | CONFIG_HID_CHERRY=y | ||
| 1013 | CONFIG_HID_CHICONY=y | ||
| 1014 | CONFIG_HID_CYPRESS=y | ||
| 1015 | CONFIG_HID_DELL=y | ||
| 1016 | CONFIG_HID_EZKEY=y | ||
| 1017 | CONFIG_HID_GYRATION=y | ||
| 1018 | CONFIG_HID_LOGITECH=y | ||
| 1019 | # CONFIG_LOGITECH_FF is not set | ||
| 1020 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1021 | CONFIG_HID_MICROSOFT=y | ||
| 1022 | CONFIG_HID_MONTEREY=y | ||
| 1023 | CONFIG_HID_PANTHERLORD=y | ||
| 1024 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1025 | CONFIG_HID_PETALYNX=y | ||
| 1026 | CONFIG_HID_SAMSUNG=y | ||
| 1027 | CONFIG_HID_SONY=y | ||
| 1028 | CONFIG_HID_SUNPLUS=y | ||
| 1029 | CONFIG_THRUSTMASTER_FF=m | ||
| 1030 | CONFIG_ZEROPLUS_FF=m | ||
| 1002 | CONFIG_USB_SUPPORT=y | 1031 | CONFIG_USB_SUPPORT=y |
| 1003 | CONFIG_USB_ARCH_HAS_HCD=y | 1032 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1004 | # CONFIG_USB_ARCH_HAS_OHCI is not set | 1033 | # CONFIG_USB_ARCH_HAS_OHCI is not set |
| @@ -1016,6 +1045,9 @@ CONFIG_USB_DEVICE_CLASS=y | |||
| 1016 | # CONFIG_USB_OTG is not set | 1045 | # CONFIG_USB_OTG is not set |
| 1017 | # CONFIG_USB_OTG_WHITELIST is not set | 1046 | # CONFIG_USB_OTG_WHITELIST is not set |
| 1018 | CONFIG_USB_OTG_BLACKLIST_HUB=y | 1047 | CONFIG_USB_OTG_BLACKLIST_HUB=y |
| 1048 | CONFIG_USB_MON=y | ||
| 1049 | # CONFIG_USB_WUSB is not set | ||
| 1050 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1019 | 1051 | ||
| 1020 | # | 1052 | # |
| 1021 | # USB Host Controller Drivers | 1053 | # USB Host Controller Drivers |
| @@ -1026,6 +1058,7 @@ CONFIG_USB_OTG_BLACKLIST_HUB=y | |||
| 1026 | # CONFIG_USB_ISP1362_HCD is not set | 1058 | # CONFIG_USB_ISP1362_HCD is not set |
| 1027 | # CONFIG_USB_SL811_HCD is not set | 1059 | # CONFIG_USB_SL811_HCD is not set |
| 1028 | # CONFIG_USB_R8A66597_HCD is not set | 1060 | # CONFIG_USB_R8A66597_HCD is not set |
| 1061 | # CONFIG_USB_HWA_HCD is not set | ||
| 1029 | CONFIG_USB_MUSB_HDRC=y | 1062 | CONFIG_USB_MUSB_HDRC=y |
| 1030 | CONFIG_USB_MUSB_SOC=y | 1063 | CONFIG_USB_MUSB_SOC=y |
| 1031 | 1064 | ||
| @@ -1037,7 +1070,7 @@ CONFIG_USB_MUSB_HOST=y | |||
| 1037 | # CONFIG_USB_MUSB_OTG is not set | 1070 | # CONFIG_USB_MUSB_OTG is not set |
| 1038 | CONFIG_USB_MUSB_HDRC_HCD=y | 1071 | CONFIG_USB_MUSB_HDRC_HCD=y |
| 1039 | CONFIG_MUSB_PIO_ONLY=y | 1072 | CONFIG_MUSB_PIO_ONLY=y |
| 1040 | CONFIG_USB_MUSB_LOGLEVEL=0 | 1073 | # CONFIG_USB_MUSB_DEBUG is not set |
| 1041 | 1074 | ||
| 1042 | # | 1075 | # |
| 1043 | # USB Device Class drivers | 1076 | # USB Device Class drivers |
| @@ -1045,6 +1078,7 @@ CONFIG_USB_MUSB_LOGLEVEL=0 | |||
| 1045 | # CONFIG_USB_ACM is not set | 1078 | # CONFIG_USB_ACM is not set |
| 1046 | # CONFIG_USB_PRINTER is not set | 1079 | # CONFIG_USB_PRINTER is not set |
| 1047 | # CONFIG_USB_WDM is not set | 1080 | # CONFIG_USB_WDM is not set |
| 1081 | # CONFIG_USB_TMC is not set | ||
| 1048 | 1082 | ||
| 1049 | # | 1083 | # |
| 1050 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1084 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' |
| @@ -1059,7 +1093,6 @@ CONFIG_USB_MUSB_LOGLEVEL=0 | |||
| 1059 | # USB Imaging devices | 1093 | # USB Imaging devices |
| 1060 | # | 1094 | # |
| 1061 | # CONFIG_USB_MDC800 is not set | 1095 | # CONFIG_USB_MDC800 is not set |
| 1062 | CONFIG_USB_MON=y | ||
| 1063 | 1096 | ||
| 1064 | # | 1097 | # |
| 1065 | # USB port drivers | 1098 | # USB port drivers |
| @@ -1072,7 +1105,7 @@ CONFIG_USB_MON=y | |||
| 1072 | # CONFIG_USB_EMI62 is not set | 1105 | # CONFIG_USB_EMI62 is not set |
| 1073 | # CONFIG_USB_EMI26 is not set | 1106 | # CONFIG_USB_EMI26 is not set |
| 1074 | # CONFIG_USB_ADUTUX is not set | 1107 | # CONFIG_USB_ADUTUX is not set |
| 1075 | # CONFIG_USB_AUERSWALD is not set | 1108 | # CONFIG_USB_SEVSEG is not set |
| 1076 | # CONFIG_USB_RIO500 is not set | 1109 | # CONFIG_USB_RIO500 is not set |
| 1077 | # CONFIG_USB_LEGOTOWER is not set | 1110 | # CONFIG_USB_LEGOTOWER is not set |
| 1078 | # CONFIG_USB_LCD is not set | 1111 | # CONFIG_USB_LCD is not set |
| @@ -1089,6 +1122,7 @@ CONFIG_USB_MON=y | |||
| 1089 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1122 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1090 | # CONFIG_USB_IOWARRIOR is not set | 1123 | # CONFIG_USB_IOWARRIOR is not set |
| 1091 | # CONFIG_USB_ISIGHTFW is not set | 1124 | # CONFIG_USB_ISIGHTFW is not set |
| 1125 | # CONFIG_USB_VST is not set | ||
| 1092 | # CONFIG_USB_GADGET is not set | 1126 | # CONFIG_USB_GADGET is not set |
| 1093 | # CONFIG_MMC is not set | 1127 | # CONFIG_MMC is not set |
| 1094 | # CONFIG_MEMSTICK is not set | 1128 | # CONFIG_MEMSTICK is not set |
| @@ -1128,36 +1162,45 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1128 | # | 1162 | # |
| 1129 | # SPI RTC drivers | 1163 | # SPI RTC drivers |
| 1130 | # | 1164 | # |
| 1165 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1166 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1131 | # CONFIG_RTC_DRV_MAX6902 is not set | 1167 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 1132 | # CONFIG_RTC_DRV_R9701 is not set | 1168 | # CONFIG_RTC_DRV_R9701 is not set |
| 1133 | # CONFIG_RTC_DRV_RS5C348 is not set | 1169 | # CONFIG_RTC_DRV_RS5C348 is not set |
| 1170 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1134 | 1171 | ||
| 1135 | # | 1172 | # |
| 1136 | # Platform RTC drivers | 1173 | # Platform RTC drivers |
| 1137 | # | 1174 | # |
| 1175 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1138 | # CONFIG_RTC_DRV_DS1511 is not set | 1176 | # CONFIG_RTC_DRV_DS1511 is not set |
| 1139 | # CONFIG_RTC_DRV_DS1553 is not set | 1177 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1140 | # CONFIG_RTC_DRV_DS1742 is not set | 1178 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1141 | # CONFIG_RTC_DRV_STK17TA8 is not set | 1179 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 1142 | # CONFIG_RTC_DRV_M48T86 is not set | 1180 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1181 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1143 | # CONFIG_RTC_DRV_M48T59 is not set | 1182 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1183 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1144 | # CONFIG_RTC_DRV_V3020 is not set | 1184 | # CONFIG_RTC_DRV_V3020 is not set |
| 1145 | 1185 | ||
| 1146 | # | 1186 | # |
| 1147 | # on-CPU RTC drivers | 1187 | # on-CPU RTC drivers |
| 1148 | # | 1188 | # |
| 1149 | CONFIG_RTC_DRV_BFIN=y | 1189 | CONFIG_RTC_DRV_BFIN=y |
| 1190 | # CONFIG_DMADEVICES is not set | ||
| 1150 | # CONFIG_UIO is not set | 1191 | # CONFIG_UIO is not set |
| 1192 | # CONFIG_STAGING is not set | ||
| 1151 | 1193 | ||
| 1152 | # | 1194 | # |
| 1153 | # File systems | 1195 | # File systems |
| 1154 | # | 1196 | # |
| 1155 | # CONFIG_EXT2_FS is not set | 1197 | # CONFIG_EXT2_FS is not set |
| 1156 | # CONFIG_EXT3_FS is not set | 1198 | # CONFIG_EXT3_FS is not set |
| 1157 | # CONFIG_EXT4DEV_FS is not set | 1199 | # CONFIG_EXT4_FS is not set |
| 1158 | # CONFIG_REISERFS_FS is not set | 1200 | # CONFIG_REISERFS_FS is not set |
| 1159 | # CONFIG_JFS_FS is not set | 1201 | # CONFIG_JFS_FS is not set |
| 1160 | # CONFIG_FS_POSIX_ACL is not set | 1202 | # CONFIG_FS_POSIX_ACL is not set |
| 1203 | CONFIG_FILE_LOCKING=y | ||
| 1161 | # CONFIG_XFS_FS is not set | 1204 | # CONFIG_XFS_FS is not set |
| 1162 | # CONFIG_OCFS2_FS is not set | 1205 | # CONFIG_OCFS2_FS is not set |
| 1163 | # CONFIG_DNOTIFY is not set | 1206 | # CONFIG_DNOTIFY is not set |
| @@ -1225,6 +1268,7 @@ CONFIG_JFFS2_RTIME=y | |||
| 1225 | # CONFIG_CRAMFS is not set | 1268 | # CONFIG_CRAMFS is not set |
| 1226 | # CONFIG_VXFS_FS is not set | 1269 | # CONFIG_VXFS_FS is not set |
| 1227 | # CONFIG_MINIX_FS is not set | 1270 | # CONFIG_MINIX_FS is not set |
| 1271 | # CONFIG_OMFS_FS is not set | ||
| 1228 | # CONFIG_HPFS_FS is not set | 1272 | # CONFIG_HPFS_FS is not set |
| 1229 | # CONFIG_QNX4FS_FS is not set | 1273 | # CONFIG_QNX4FS_FS is not set |
| 1230 | # CONFIG_ROMFS_FS is not set | 1274 | # CONFIG_ROMFS_FS is not set |
| @@ -1240,7 +1284,7 @@ CONFIG_LOCKD=m | |||
| 1240 | CONFIG_LOCKD_V4=y | 1284 | CONFIG_LOCKD_V4=y |
| 1241 | CONFIG_NFS_COMMON=y | 1285 | CONFIG_NFS_COMMON=y |
| 1242 | CONFIG_SUNRPC=m | 1286 | CONFIG_SUNRPC=m |
| 1243 | # CONFIG_SUNRPC_BIND34 is not set | 1287 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1244 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1288 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1245 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1289 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1246 | CONFIG_SMB_FS=m | 1290 | CONFIG_SMB_FS=m |
| @@ -1308,10 +1352,48 @@ CONFIG_FRAME_WARN=1024 | |||
| 1308 | # CONFIG_UNUSED_SYMBOLS is not set | 1352 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1309 | CONFIG_DEBUG_FS=y | 1353 | CONFIG_DEBUG_FS=y |
| 1310 | # CONFIG_HEADERS_CHECK is not set | 1354 | # CONFIG_HEADERS_CHECK is not set |
| 1311 | # CONFIG_DEBUG_KERNEL is not set | 1355 | CONFIG_DEBUG_KERNEL=y |
| 1356 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1357 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1358 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1359 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1360 | CONFIG_SCHED_DEBUG=y | ||
| 1361 | # CONFIG_SCHEDSTATS is not set | ||
| 1362 | # CONFIG_TIMER_STATS is not set | ||
| 1363 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1364 | # CONFIG_DEBUG_SLAB is not set | ||
| 1365 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1366 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1367 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1368 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1369 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1370 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1371 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1312 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1372 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1373 | CONFIG_DEBUG_INFO=y | ||
| 1374 | # CONFIG_DEBUG_VM is not set | ||
| 1375 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1376 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1377 | # CONFIG_DEBUG_LIST is not set | ||
| 1378 | # CONFIG_DEBUG_SG is not set | ||
| 1379 | # CONFIG_FRAME_POINTER is not set | ||
| 1380 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1381 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1382 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1383 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1384 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1385 | # CONFIG_FAULT_INJECTION is not set | ||
| 1386 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1387 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1313 | # CONFIG_SAMPLES is not set | 1388 | # CONFIG_SAMPLES is not set |
| 1389 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1390 | # CONFIG_KGDB is not set | ||
| 1391 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1392 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1393 | CONFIG_DEBUG_VERBOSE=y | ||
| 1314 | CONFIG_DEBUG_MMRS=y | 1394 | CONFIG_DEBUG_MMRS=y |
| 1395 | # CONFIG_DEBUG_HWERR is not set | ||
| 1396 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 1315 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1397 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1316 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1398 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1317 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1399 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -1329,8 +1411,9 @@ CONFIG_ACCESS_CHECK=y | |||
| 1329 | # | 1411 | # |
| 1330 | # CONFIG_KEYS is not set | 1412 | # CONFIG_KEYS is not set |
| 1331 | CONFIG_SECURITY=y | 1413 | CONFIG_SECURITY=y |
| 1414 | # CONFIG_SECURITYFS is not set | ||
| 1332 | # CONFIG_SECURITY_NETWORK is not set | 1415 | # CONFIG_SECURITY_NETWORK is not set |
| 1333 | # CONFIG_SECURITY_CAPABILITIES is not set | 1416 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1334 | # CONFIG_SECURITY_ROOTPLUG is not set | 1417 | # CONFIG_SECURITY_ROOTPLUG is not set |
| 1335 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | 1418 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 |
| 1336 | CONFIG_CRYPTO=y | 1419 | CONFIG_CRYPTO=y |
| @@ -1338,6 +1421,7 @@ CONFIG_CRYPTO=y | |||
| 1338 | # | 1421 | # |
| 1339 | # Crypto core or helper | 1422 | # Crypto core or helper |
| 1340 | # | 1423 | # |
| 1424 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1341 | # CONFIG_CRYPTO_MANAGER is not set | 1425 | # CONFIG_CRYPTO_MANAGER is not set |
| 1342 | # CONFIG_CRYPTO_GF128MUL is not set | 1426 | # CONFIG_CRYPTO_GF128MUL is not set |
| 1343 | # CONFIG_CRYPTO_NULL is not set | 1427 | # CONFIG_CRYPTO_NULL is not set |
| @@ -1376,6 +1460,10 @@ CONFIG_CRYPTO=y | |||
| 1376 | # CONFIG_CRYPTO_MD4 is not set | 1460 | # CONFIG_CRYPTO_MD4 is not set |
| 1377 | # CONFIG_CRYPTO_MD5 is not set | 1461 | # CONFIG_CRYPTO_MD5 is not set |
| 1378 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1462 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
| 1463 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1464 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1465 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1466 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1379 | # CONFIG_CRYPTO_SHA1 is not set | 1467 | # CONFIG_CRYPTO_SHA1 is not set |
| 1380 | # CONFIG_CRYPTO_SHA256 is not set | 1468 | # CONFIG_CRYPTO_SHA256 is not set |
| 1381 | # CONFIG_CRYPTO_SHA512 is not set | 1469 | # CONFIG_CRYPTO_SHA512 is not set |
| @@ -1406,15 +1494,20 @@ CONFIG_CRYPTO=y | |||
| 1406 | # | 1494 | # |
| 1407 | # CONFIG_CRYPTO_DEFLATE is not set | 1495 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1408 | # CONFIG_CRYPTO_LZO is not set | 1496 | # CONFIG_CRYPTO_LZO is not set |
| 1497 | |||
| 1498 | # | ||
| 1499 | # Random Number Generation | ||
| 1500 | # | ||
| 1501 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1409 | CONFIG_CRYPTO_HW=y | 1502 | CONFIG_CRYPTO_HW=y |
| 1410 | 1503 | ||
| 1411 | # | 1504 | # |
| 1412 | # Library routines | 1505 | # Library routines |
| 1413 | # | 1506 | # |
| 1414 | CONFIG_BITREVERSE=y | 1507 | CONFIG_BITREVERSE=y |
| 1415 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | ||
| 1416 | CONFIG_CRC_CCITT=m | 1508 | CONFIG_CRC_CCITT=m |
| 1417 | # CONFIG_CRC16 is not set | 1509 | # CONFIG_CRC16 is not set |
| 1510 | # CONFIG_CRC_T10DIF is not set | ||
| 1418 | # CONFIG_CRC_ITU_T is not set | 1511 | # CONFIG_CRC_ITU_T is not set |
| 1419 | CONFIG_CRC32=y | 1512 | CONFIG_CRC32=y |
| 1420 | # CONFIG_CRC7 is not set | 1513 | # CONFIG_CRC7 is not set |
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index 4a2a660a6b35..f92668af00b0 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24.7 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # | 4 | # |
| 5 | # CONFIG_MMU is not set | 5 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 6 | # CONFIG_FPU is not set |
| @@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 9 | CONFIG_BLACKFIN=y | 9 | CONFIG_BLACKFIN=y |
| 10 | CONFIG_ZONE_DMA=y | 10 | CONFIG_ZONE_DMA=y |
| 11 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 11 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 13 | CONFIG_GENERIC_HWEIGHT=y | 12 | CONFIG_GENERIC_HWEIGHT=y |
| 14 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| @@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 31 | # CONFIG_POSIX_MQUEUE is not set | 30 | # CONFIG_POSIX_MQUEUE is not set |
| 32 | # CONFIG_BSD_PROCESS_ACCT is not set | 31 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 33 | # CONFIG_TASKSTATS is not set | 32 | # CONFIG_TASKSTATS is not set |
| 34 | # CONFIG_USER_NS is not set | ||
| 35 | # CONFIG_PID_NS is not set | ||
| 36 | # CONFIG_AUDIT is not set | 33 | # CONFIG_AUDIT is not set |
| 37 | CONFIG_IKCONFIG=y | 34 | CONFIG_IKCONFIG=y |
| 38 | CONFIG_IKCONFIG_PROC=y | 35 | CONFIG_IKCONFIG_PROC=y |
| 39 | CONFIG_LOG_BUF_SHIFT=14 | 36 | CONFIG_LOG_BUF_SHIFT=14 |
| 40 | # CONFIG_CGROUPS is not set | 37 | # CONFIG_CGROUPS is not set |
| 41 | CONFIG_FAIR_GROUP_SCHED=y | 38 | # CONFIG_GROUP_SCHED is not set |
| 42 | CONFIG_FAIR_USER_SCHED=y | 39 | # CONFIG_SYSFS_DEPRECATED is not set |
| 43 | # CONFIG_FAIR_CGROUP_SCHED is not set | 40 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 44 | CONFIG_SYSFS_DEPRECATED=y | ||
| 45 | # CONFIG_RELAY is not set | 41 | # CONFIG_RELAY is not set |
| 42 | # CONFIG_NAMESPACES is not set | ||
| 46 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 47 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y | |||
| 51 | CONFIG_UID16=y | 48 | CONFIG_UID16=y |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 49 | CONFIG_SYSCTL_SYSCALL=y |
| 53 | CONFIG_KALLSYMS=y | 50 | CONFIG_KALLSYMS=y |
| 51 | # CONFIG_KALLSYMS_ALL is not set | ||
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | CONFIG_HOTPLUG=y | 53 | CONFIG_HOTPLUG=y |
| 56 | CONFIG_PRINTK=y | 54 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 55 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 56 | # CONFIG_ELF_CORE is not set |
| 57 | CONFIG_COMPAT_BRK=y | ||
| 59 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 59 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 60 | CONFIG_ANON_INODES=y |
| 62 | CONFIG_EPOLL=y | 61 | CONFIG_EPOLL=y |
| 63 | CONFIG_SIGNALFD=y | 62 | CONFIG_SIGNALFD=y |
| 63 | CONFIG_TIMERFD=y | ||
| 64 | CONFIG_EVENTFD=y | 64 | CONFIG_EVENTFD=y |
| 65 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 66 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| 70 | # CONFIG_PROFILING is not set | ||
| 71 | # CONFIG_MARKERS is not set | ||
| 72 | CONFIG_HAVE_OPROFILE=y | ||
| 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 69 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 70 | CONFIG_RT_MUTEXES=y | 75 | CONFIG_RT_MUTEXES=y |
| 71 | CONFIG_TINY_SHMEM=y | 76 | CONFIG_TINY_SHMEM=y |
| 72 | CONFIG_BASE_SMALL=0 | 77 | CONFIG_BASE_SMALL=0 |
| 73 | CONFIG_MODULES=y | 78 | CONFIG_MODULES=y |
| 79 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 74 | CONFIG_MODULE_UNLOAD=y | 80 | CONFIG_MODULE_UNLOAD=y |
| 75 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 81 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 76 | # CONFIG_MODVERSIONS is not set | 82 | # CONFIG_MODVERSIONS is not set |
| @@ -81,6 +87,7 @@ CONFIG_BLOCK=y | |||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | 87 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 82 | # CONFIG_LSF is not set | 88 | # CONFIG_LSF is not set |
| 83 | # CONFIG_BLK_DEV_BSG is not set | 89 | # CONFIG_BLK_DEV_BSG is not set |
| 90 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 84 | 91 | ||
| 85 | # | 92 | # |
| 86 | # IO Schedulers | 93 | # IO Schedulers |
| @@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y | |||
| 94 | # CONFIG_DEFAULT_CFQ is not set | 101 | # CONFIG_DEFAULT_CFQ is not set |
| 95 | # CONFIG_DEFAULT_NOOP is not set | 102 | # CONFIG_DEFAULT_NOOP is not set |
| 96 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 103 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 104 | CONFIG_CLASSIC_RCU=y | ||
| 97 | # CONFIG_PREEMPT_NONE is not set | 105 | # CONFIG_PREEMPT_NONE is not set |
| 98 | CONFIG_PREEMPT_VOLUNTARY=y | 106 | CONFIG_PREEMPT_VOLUNTARY=y |
| 99 | # CONFIG_PREEMPT is not set | 107 | # CONFIG_PREEMPT is not set |
| 108 | # CONFIG_FREEZER is not set | ||
| 100 | 109 | ||
| 101 | # | 110 | # |
| 102 | # Blackfin Processor Options | 111 | # Blackfin Processor Options |
| @@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 105 | # | 114 | # |
| 106 | # Processor and Board Settings | 115 | # Processor and Board Settings |
| 107 | # | 116 | # |
| 117 | # CONFIG_BF512 is not set | ||
| 118 | # CONFIG_BF514 is not set | ||
| 119 | # CONFIG_BF516 is not set | ||
| 120 | # CONFIG_BF518 is not set | ||
| 108 | # CONFIG_BF522 is not set | 121 | # CONFIG_BF522 is not set |
| 109 | # CONFIG_BF523 is not set | 122 | # CONFIG_BF523 is not set |
| 110 | # CONFIG_BF524 is not set | 123 | # CONFIG_BF524 is not set |
| @@ -117,47 +130,27 @@ CONFIG_BF527=y | |||
| 117 | # CONFIG_BF534 is not set | 130 | # CONFIG_BF534 is not set |
| 118 | # CONFIG_BF536 is not set | 131 | # CONFIG_BF536 is not set |
| 119 | # CONFIG_BF537 is not set | 132 | # CONFIG_BF537 is not set |
| 133 | # CONFIG_BF538 is not set | ||
| 134 | # CONFIG_BF539 is not set | ||
| 120 | # CONFIG_BF542 is not set | 135 | # CONFIG_BF542 is not set |
| 121 | # CONFIG_BF544 is not set | 136 | # CONFIG_BF544 is not set |
| 122 | # CONFIG_BF547 is not set | 137 | # CONFIG_BF547 is not set |
| 123 | # CONFIG_BF548 is not set | 138 | # CONFIG_BF548 is not set |
| 124 | # CONFIG_BF549 is not set | 139 | # CONFIG_BF549 is not set |
| 125 | # CONFIG_BF561 is not set | 140 | # CONFIG_BF561 is not set |
| 141 | CONFIG_BF_REV_MIN=0 | ||
| 142 | CONFIG_BF_REV_MAX=2 | ||
| 126 | CONFIG_BF_REV_0_0=y | 143 | CONFIG_BF_REV_0_0=y |
| 127 | # CONFIG_BF_REV_0_1 is not set | 144 | # CONFIG_BF_REV_0_1 is not set |
| 128 | # CONFIG_BF_REV_0_2 is not set | 145 | # CONFIG_BF_REV_0_2 is not set |
| 129 | # CONFIG_BF_REV_0_3 is not set | 146 | # CONFIG_BF_REV_0_3 is not set |
| 130 | # CONFIG_BF_REV_0_4 is not set | 147 | # CONFIG_BF_REV_0_4 is not set |
| 131 | # CONFIG_BF_REV_0_5 is not set | 148 | # CONFIG_BF_REV_0_5 is not set |
| 149 | # CONFIG_BF_REV_0_6 is not set | ||
| 132 | # CONFIG_BF_REV_ANY is not set | 150 | # CONFIG_BF_REV_ANY is not set |
| 133 | # CONFIG_BF_REV_NONE is not set | 151 | # CONFIG_BF_REV_NONE is not set |
| 134 | CONFIG_BF52x=y | 152 | CONFIG_BF52x=y |
| 135 | CONFIG_MEM_MT48LC32M16A2TG_75=y | 153 | CONFIG_MEM_MT48LC32M16A2TG_75=y |
| 136 | CONFIG_BFIN527_EZKIT=y | ||
| 137 | |||
| 138 | # | ||
| 139 | # BF527 Specific Configuration | ||
| 140 | # | ||
| 141 | |||
| 142 | # | ||
| 143 | # Alternative Multiplexing Scheme | ||
| 144 | # | ||
| 145 | # CONFIG_BF527_SPORT0_PORTF is not set | ||
| 146 | CONFIG_BF527_SPORT0_PORTG=y | ||
| 147 | CONFIG_BF527_SPORT0_TSCLK_PG10=y | ||
| 148 | # CONFIG_BF527_SPORT0_TSCLK_PG14 is not set | ||
| 149 | CONFIG_BF527_UART1_PORTF=y | ||
| 150 | # CONFIG_BF527_UART1_PORTG is not set | ||
| 151 | # CONFIG_BF527_NAND_D_PORTF is not set | ||
| 152 | CONFIG_BF527_NAND_D_PORTH=y | ||
| 153 | |||
| 154 | # | ||
| 155 | # Interrupt Priority Assignment | ||
| 156 | # | ||
| 157 | |||
| 158 | # | ||
| 159 | # Priority | ||
| 160 | # | ||
| 161 | CONFIG_IRQ_PLL_WAKEUP=7 | 154 | CONFIG_IRQ_PLL_WAKEUP=7 |
| 162 | CONFIG_IRQ_DMA0_ERROR=7 | 155 | CONFIG_IRQ_DMA0_ERROR=7 |
| 163 | CONFIG_IRQ_DMAR0_BLK=7 | 156 | CONFIG_IRQ_DMAR0_BLK=7 |
| @@ -177,7 +170,6 @@ CONFIG_IRQ_SPORT0_TX=9 | |||
| 177 | CONFIG_IRQ_SPORT1_RX=9 | 170 | CONFIG_IRQ_SPORT1_RX=9 |
| 178 | CONFIG_IRQ_SPORT1_TX=9 | 171 | CONFIG_IRQ_SPORT1_TX=9 |
| 179 | CONFIG_IRQ_TWI=10 | 172 | CONFIG_IRQ_TWI=10 |
| 180 | CONFIG_IRQ_SPI=10 | ||
| 181 | CONFIG_IRQ_UART0_RX=10 | 173 | CONFIG_IRQ_UART0_RX=10 |
| 182 | CONFIG_IRQ_UART0_TX=10 | 174 | CONFIG_IRQ_UART0_TX=10 |
| 183 | CONFIG_IRQ_UART1_RX=10 | 175 | CONFIG_IRQ_UART1_RX=10 |
| @@ -188,14 +180,14 @@ CONFIG_IRQ_MAC_RX=11 | |||
| 188 | CONFIG_IRQ_PORTH_INTA=11 | 180 | CONFIG_IRQ_PORTH_INTA=11 |
| 189 | CONFIG_IRQ_MAC_TX=11 | 181 | CONFIG_IRQ_MAC_TX=11 |
| 190 | CONFIG_IRQ_PORTH_INTB=11 | 182 | CONFIG_IRQ_PORTH_INTB=11 |
| 191 | CONFIG_IRQ_TMR0=12 | 183 | CONFIG_IRQ_TIMER0=8 |
| 192 | CONFIG_IRQ_TMR1=12 | 184 | CONFIG_IRQ_TIMER1=12 |
| 193 | CONFIG_IRQ_TMR2=12 | 185 | CONFIG_IRQ_TIMER2=12 |
| 194 | CONFIG_IRQ_TMR3=12 | 186 | CONFIG_IRQ_TIMER3=12 |
| 195 | CONFIG_IRQ_TMR4=12 | 187 | CONFIG_IRQ_TIMER4=12 |
| 196 | CONFIG_IRQ_TMR5=12 | 188 | CONFIG_IRQ_TIMER5=12 |
| 197 | CONFIG_IRQ_TMR6=12 | 189 | CONFIG_IRQ_TIMER6=12 |
| 198 | CONFIG_IRQ_TMR7=12 | 190 | CONFIG_IRQ_TIMER7=12 |
| 199 | CONFIG_IRQ_PORTG_INTA=12 | 191 | CONFIG_IRQ_PORTG_INTA=12 |
| 200 | CONFIG_IRQ_PORTG_INTB=12 | 192 | CONFIG_IRQ_PORTG_INTB=12 |
| 201 | CONFIG_IRQ_MEM_DMA0=13 | 193 | CONFIG_IRQ_MEM_DMA0=13 |
| @@ -203,6 +195,34 @@ CONFIG_IRQ_MEM_DMA1=13 | |||
| 203 | CONFIG_IRQ_WATCH=13 | 195 | CONFIG_IRQ_WATCH=13 |
| 204 | CONFIG_IRQ_PORTF_INTA=13 | 196 | CONFIG_IRQ_PORTF_INTA=13 |
| 205 | CONFIG_IRQ_PORTF_INTB=13 | 197 | CONFIG_IRQ_PORTF_INTB=13 |
| 198 | CONFIG_BFIN527_EZKIT=y | ||
| 199 | # CONFIG_BFIN527_BLUETECHNIX_CM is not set | ||
| 200 | # CONFIG_BFIN526_EZBRD is not set | ||
| 201 | |||
| 202 | # | ||
| 203 | # BF527 Specific Configuration | ||
| 204 | # | ||
| 205 | |||
| 206 | # | ||
| 207 | # Alternative Multiplexing Scheme | ||
| 208 | # | ||
| 209 | # CONFIG_BF527_SPORT0_PORTF is not set | ||
| 210 | CONFIG_BF527_SPORT0_PORTG=y | ||
| 211 | CONFIG_BF527_SPORT0_TSCLK_PG10=y | ||
| 212 | # CONFIG_BF527_SPORT0_TSCLK_PG14 is not set | ||
| 213 | CONFIG_BF527_UART1_PORTF=y | ||
| 214 | # CONFIG_BF527_UART1_PORTG is not set | ||
| 215 | # CONFIG_BF527_NAND_D_PORTF is not set | ||
| 216 | CONFIG_BF527_NAND_D_PORTH=y | ||
| 217 | |||
| 218 | # | ||
| 219 | # Interrupt Priority Assignment | ||
| 220 | # | ||
| 221 | |||
| 222 | # | ||
| 223 | # Priority | ||
| 224 | # | ||
| 225 | CONFIG_IRQ_SPI=10 | ||
| 206 | CONFIG_IRQ_SPI_ERROR=7 | 226 | CONFIG_IRQ_SPI_ERROR=7 |
| 207 | CONFIG_IRQ_NFC_ERROR=7 | 227 | CONFIG_IRQ_NFC_ERROR=7 |
| 208 | CONFIG_IRQ_HDMA_ERROR=7 | 228 | CONFIG_IRQ_HDMA_ERROR=7 |
| @@ -224,7 +244,6 @@ CONFIG_BOOT_LOAD=0x1000 | |||
| 224 | # | 244 | # |
| 225 | CONFIG_CLKIN_HZ=25000000 | 245 | CONFIG_CLKIN_HZ=25000000 |
| 226 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 246 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 227 | CONFIG_MAX_MEM_SIZE=512 | ||
| 228 | CONFIG_MAX_VCO_HZ=600000000 | 247 | CONFIG_MAX_VCO_HZ=600000000 |
| 229 | CONFIG_MIN_VCO_HZ=50000000 | 248 | CONFIG_MIN_VCO_HZ=50000000 |
| 230 | CONFIG_MAX_SCLK_HZ=133333333 | 249 | CONFIG_MAX_SCLK_HZ=133333333 |
| @@ -238,10 +257,10 @@ CONFIG_HZ_250=y | |||
| 238 | # CONFIG_HZ_300 is not set | 257 | # CONFIG_HZ_300 is not set |
| 239 | # CONFIG_HZ_1000 is not set | 258 | # CONFIG_HZ_1000 is not set |
| 240 | CONFIG_HZ=250 | 259 | CONFIG_HZ=250 |
| 260 | # CONFIG_SCHED_HRTICK is not set | ||
| 241 | CONFIG_GENERIC_TIME=y | 261 | CONFIG_GENERIC_TIME=y |
| 242 | CONFIG_GENERIC_CLOCKEVENTS=y | 262 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 243 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 263 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 244 | # CONFIG_TICK_ONESHOT is not set | ||
| 245 | # CONFIG_NO_HZ is not set | 264 | # CONFIG_NO_HZ is not set |
| 246 | # CONFIG_HIGH_RES_TIMERS is not set | 265 | # CONFIG_HIGH_RES_TIMERS is not set |
| 247 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 266 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -275,6 +294,12 @@ CONFIG_ACCESS_OK_L1=y | |||
| 275 | CONFIG_CACHELINE_ALIGNED_L1=y | 294 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 276 | # CONFIG_SYSCALL_TAB_L1 is not set | 295 | # CONFIG_SYSCALL_TAB_L1 is not set |
| 277 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | 296 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set |
| 297 | CONFIG_APP_STACK_L1=y | ||
| 298 | |||
| 299 | # | ||
| 300 | # Speed Optimizations | ||
| 301 | # | ||
| 302 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 278 | CONFIG_RAMKERNEL=y | 303 | CONFIG_RAMKERNEL=y |
| 279 | # CONFIG_ROMKERNEL is not set | 304 | # CONFIG_ROMKERNEL is not set |
| 280 | CONFIG_SELECT_MEMORY_MODEL=y | 305 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -283,14 +308,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 283 | # CONFIG_SPARSEMEM_MANUAL is not set | 308 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 284 | CONFIG_FLATMEM=y | 309 | CONFIG_FLATMEM=y |
| 285 | CONFIG_FLAT_NODE_MEM_MAP=y | 310 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 286 | # CONFIG_SPARSEMEM_STATIC is not set | 311 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 287 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 288 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 312 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 289 | # CONFIG_RESOURCES_64BIT is not set | 313 | # CONFIG_RESOURCES_64BIT is not set |
| 314 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 290 | CONFIG_ZONE_DMA_FLAG=1 | 315 | CONFIG_ZONE_DMA_FLAG=1 |
| 291 | CONFIG_VIRT_TO_BUS=y | 316 | CONFIG_VIRT_TO_BUS=y |
| 292 | CONFIG_BFIN_GPTIMERS=y | 317 | CONFIG_BFIN_GPTIMERS=y |
| 293 | CONFIG_BFIN_DMA_5XX=y | ||
| 294 | # CONFIG_DMA_UNCACHED_4M is not set | 318 | # CONFIG_DMA_UNCACHED_4M is not set |
| 295 | # CONFIG_DMA_UNCACHED_2M is not set | 319 | # CONFIG_DMA_UNCACHED_2M is not set |
| 296 | CONFIG_DMA_UNCACHED_1M=y | 320 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -305,7 +329,6 @@ CONFIG_BFIN_DCACHE=y | |||
| 305 | # CONFIG_BFIN_ICACHE_LOCK is not set | 329 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 306 | # CONFIG_BFIN_WB is not set | 330 | # CONFIG_BFIN_WB is not set |
| 307 | CONFIG_BFIN_WT=y | 331 | CONFIG_BFIN_WT=y |
| 308 | CONFIG_L1_MAX_PIECE=16 | ||
| 309 | # CONFIG_MPU is not set | 332 | # CONFIG_MPU is not set |
| 310 | 333 | ||
| 311 | # | 334 | # |
| @@ -334,7 +357,6 @@ CONFIG_BANK_3=0xFFC0 | |||
| 334 | # | 357 | # |
| 335 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 358 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 336 | # | 359 | # |
| 337 | # CONFIG_PCI is not set | ||
| 338 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 360 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 339 | # CONFIG_PCCARD is not set | 361 | # CONFIG_PCCARD is not set |
| 340 | 362 | ||
| @@ -345,23 +367,20 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 345 | CONFIG_BINFMT_FLAT=y | 367 | CONFIG_BINFMT_FLAT=y |
| 346 | CONFIG_BINFMT_ZFLAT=y | 368 | CONFIG_BINFMT_ZFLAT=y |
| 347 | # CONFIG_BINFMT_SHARED_FLAT is not set | 369 | # CONFIG_BINFMT_SHARED_FLAT is not set |
| 370 | # CONFIG_HAVE_AOUT is not set | ||
| 348 | # CONFIG_BINFMT_MISC is not set | 371 | # CONFIG_BINFMT_MISC is not set |
| 349 | 372 | ||
| 350 | # | 373 | # |
| 351 | # Power management options | 374 | # Power management options |
| 352 | # | 375 | # |
| 353 | # CONFIG_PM is not set | 376 | # CONFIG_PM is not set |
| 354 | CONFIG_SUSPEND_UP_POSSIBLE=y | 377 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 355 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | 378 | # CONFIG_PM_WAKEUP_BY_GPIO is not set |
| 356 | 379 | ||
| 357 | # | 380 | # |
| 358 | # CPU Frequency scaling | 381 | # CPU Frequency scaling |
| 359 | # | 382 | # |
| 360 | # CONFIG_CPU_FREQ is not set | 383 | # CONFIG_CPU_FREQ is not set |
| 361 | |||
| 362 | # | ||
| 363 | # Networking | ||
| 364 | # | ||
| 365 | CONFIG_NET=y | 384 | CONFIG_NET=y |
| 366 | 385 | ||
| 367 | # | 386 | # |
| @@ -374,6 +393,7 @@ CONFIG_XFRM=y | |||
| 374 | # CONFIG_XFRM_USER is not set | 393 | # CONFIG_XFRM_USER is not set |
| 375 | # CONFIG_XFRM_SUB_POLICY is not set | 394 | # CONFIG_XFRM_SUB_POLICY is not set |
| 376 | # CONFIG_XFRM_MIGRATE is not set | 395 | # CONFIG_XFRM_MIGRATE is not set |
| 396 | # CONFIG_XFRM_STATISTICS is not set | ||
| 377 | # CONFIG_NET_KEY is not set | 397 | # CONFIG_NET_KEY is not set |
| 378 | CONFIG_INET=y | 398 | CONFIG_INET=y |
| 379 | # CONFIG_IP_MULTICAST is not set | 399 | # CONFIG_IP_MULTICAST is not set |
| @@ -403,8 +423,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 403 | CONFIG_DEFAULT_TCP_CONG="cubic" | 423 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 404 | # CONFIG_TCP_MD5SIG is not set | 424 | # CONFIG_TCP_MD5SIG is not set |
| 405 | # CONFIG_IPV6 is not set | 425 | # CONFIG_IPV6 is not set |
| 406 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 407 | # CONFIG_INET6_TUNNEL is not set | ||
| 408 | # CONFIG_NETLABEL is not set | 426 | # CONFIG_NETLABEL is not set |
| 409 | # CONFIG_NETWORK_SECMARK is not set | 427 | # CONFIG_NETWORK_SECMARK is not set |
| 410 | # CONFIG_NETFILTER is not set | 428 | # CONFIG_NETFILTER is not set |
| @@ -413,6 +431,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 413 | # CONFIG_TIPC is not set | 431 | # CONFIG_TIPC is not set |
| 414 | # CONFIG_ATM is not set | 432 | # CONFIG_ATM is not set |
| 415 | # CONFIG_BRIDGE is not set | 433 | # CONFIG_BRIDGE is not set |
| 434 | # CONFIG_NET_DSA is not set | ||
| 416 | # CONFIG_VLAN_8021Q is not set | 435 | # CONFIG_VLAN_8021Q is not set |
| 417 | # CONFIG_DECNET is not set | 436 | # CONFIG_DECNET is not set |
| 418 | # CONFIG_LLC2 is not set | 437 | # CONFIG_LLC2 is not set |
| @@ -429,6 +448,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 429 | # | 448 | # |
| 430 | # CONFIG_NET_PKTGEN is not set | 449 | # CONFIG_NET_PKTGEN is not set |
| 431 | # CONFIG_HAMRADIO is not set | 450 | # CONFIG_HAMRADIO is not set |
| 451 | # CONFIG_CAN is not set | ||
| 432 | CONFIG_IRDA=m | 452 | CONFIG_IRDA=m |
| 433 | 453 | ||
| 434 | # | 454 | # |
| @@ -467,15 +487,6 @@ CONFIG_SIR_BFIN_DMA=y | |||
| 467 | # CONFIG_KS959_DONGLE is not set | 487 | # CONFIG_KS959_DONGLE is not set |
| 468 | 488 | ||
| 469 | # | 489 | # |
| 470 | # Old SIR device drivers | ||
| 471 | # | ||
| 472 | # CONFIG_IRPORT_SIR is not set | ||
| 473 | |||
| 474 | # | ||
| 475 | # Old Serial dongle support | ||
| 476 | # | ||
| 477 | |||
| 478 | # | ||
| 479 | # FIR device drivers | 490 | # FIR device drivers |
| 480 | # | 491 | # |
| 481 | # CONFIG_USB_IRDA is not set | 492 | # CONFIG_USB_IRDA is not set |
| @@ -483,11 +494,10 @@ CONFIG_SIR_BFIN_DMA=y | |||
| 483 | # CONFIG_MCS_FIR is not set | 494 | # CONFIG_MCS_FIR is not set |
| 484 | # CONFIG_BT is not set | 495 | # CONFIG_BT is not set |
| 485 | # CONFIG_AF_RXRPC is not set | 496 | # CONFIG_AF_RXRPC is not set |
| 486 | 497 | # CONFIG_PHONET is not set | |
| 487 | # | 498 | CONFIG_WIRELESS=y |
| 488 | # Wireless | ||
| 489 | # | ||
| 490 | # CONFIG_CFG80211 is not set | 499 | # CONFIG_CFG80211 is not set |
| 500 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 491 | # CONFIG_WIRELESS_EXT is not set | 501 | # CONFIG_WIRELESS_EXT is not set |
| 492 | # CONFIG_MAC80211 is not set | 502 | # CONFIG_MAC80211 is not set |
| 493 | # CONFIG_IEEE80211 is not set | 503 | # CONFIG_IEEE80211 is not set |
| @@ -505,6 +515,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 505 | CONFIG_STANDALONE=y | 515 | CONFIG_STANDALONE=y |
| 506 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 516 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 507 | # CONFIG_FW_LOADER is not set | 517 | # CONFIG_FW_LOADER is not set |
| 518 | # CONFIG_DEBUG_DRIVER is not set | ||
| 519 | # CONFIG_DEBUG_DEVRES is not set | ||
| 508 | # CONFIG_SYS_HYPERVISOR is not set | 520 | # CONFIG_SYS_HYPERVISOR is not set |
| 509 | # CONFIG_CONNECTOR is not set | 521 | # CONFIG_CONNECTOR is not set |
| 510 | CONFIG_MTD=y | 522 | CONFIG_MTD=y |
| @@ -513,6 +525,7 @@ CONFIG_MTD=y | |||
| 513 | CONFIG_MTD_PARTITIONS=y | 525 | CONFIG_MTD_PARTITIONS=y |
| 514 | # CONFIG_MTD_REDBOOT_PARTS is not set | 526 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 515 | # CONFIG_MTD_CMDLINE_PARTS is not set | 527 | # CONFIG_MTD_CMDLINE_PARTS is not set |
| 528 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 516 | 529 | ||
| 517 | # | 530 | # |
| 518 | # User Modules And Translation Layers | 531 | # User Modules And Translation Layers |
| @@ -556,6 +569,7 @@ CONFIG_MTD_ROM=m | |||
| 556 | # | 569 | # |
| 557 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 570 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 558 | # CONFIG_MTD_PHYSMAP is not set | 571 | # CONFIG_MTD_PHYSMAP is not set |
| 572 | # CONFIG_MTD_GPIO_ADDR is not set | ||
| 559 | # CONFIG_MTD_UCLINUX is not set | 573 | # CONFIG_MTD_UCLINUX is not set |
| 560 | # CONFIG_MTD_PLATRAM is not set | 574 | # CONFIG_MTD_PLATRAM is not set |
| 561 | 575 | ||
| @@ -563,7 +577,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y | |||
| 563 | # Self-contained MTD device drivers | 577 | # Self-contained MTD device drivers |
| 564 | # | 578 | # |
| 565 | # CONFIG_MTD_DATAFLASH is not set | 579 | # CONFIG_MTD_DATAFLASH is not set |
| 566 | # CONFIG_MTD_M25P80 is not set | 580 | CONFIG_MTD_M25P80=y |
| 581 | CONFIG_M25PXX_USE_FAST_READ=y | ||
| 567 | # CONFIG_MTD_SLRAM is not set | 582 | # CONFIG_MTD_SLRAM is not set |
| 568 | # CONFIG_MTD_PHRAM is not set | 583 | # CONFIG_MTD_PHRAM is not set |
| 569 | # CONFIG_MTD_MTDRAM is not set | 584 | # CONFIG_MTD_MTDRAM is not set |
| @@ -605,11 +620,14 @@ CONFIG_BLK_DEV=y | |||
| 605 | CONFIG_BLK_DEV_RAM=y | 620 | CONFIG_BLK_DEV_RAM=y |
| 606 | CONFIG_BLK_DEV_RAM_COUNT=16 | 621 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 607 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 622 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 608 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 623 | # CONFIG_BLK_DEV_XIP is not set |
| 609 | # CONFIG_CDROM_PKTCDVD is not set | 624 | # CONFIG_CDROM_PKTCDVD is not set |
| 610 | # CONFIG_ATA_OVER_ETH is not set | 625 | # CONFIG_ATA_OVER_ETH is not set |
| 626 | # CONFIG_BLK_DEV_HD is not set | ||
| 611 | CONFIG_MISC_DEVICES=y | 627 | CONFIG_MISC_DEVICES=y |
| 612 | # CONFIG_EEPROM_93CX6 is not set | 628 | # CONFIG_EEPROM_93CX6 is not set |
| 629 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 630 | CONFIG_HAVE_IDE=y | ||
| 613 | # CONFIG_IDE is not set | 631 | # CONFIG_IDE is not set |
| 614 | 632 | ||
| 615 | # | 633 | # |
| @@ -622,7 +640,6 @@ CONFIG_MISC_DEVICES=y | |||
| 622 | # CONFIG_ATA is not set | 640 | # CONFIG_ATA is not set |
| 623 | # CONFIG_MD is not set | 641 | # CONFIG_MD is not set |
| 624 | CONFIG_NETDEVICES=y | 642 | CONFIG_NETDEVICES=y |
| 625 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 626 | # CONFIG_DUMMY is not set | 643 | # CONFIG_DUMMY is not set |
| 627 | # CONFIG_BONDING is not set | 644 | # CONFIG_BONDING is not set |
| 628 | # CONFIG_MACVLAN is not set | 645 | # CONFIG_MACVLAN is not set |
| @@ -643,6 +660,7 @@ CONFIG_PHYLIB=y | |||
| 643 | # CONFIG_SMSC_PHY is not set | 660 | # CONFIG_SMSC_PHY is not set |
| 644 | # CONFIG_BROADCOM_PHY is not set | 661 | # CONFIG_BROADCOM_PHY is not set |
| 645 | # CONFIG_ICPLUS_PHY is not set | 662 | # CONFIG_ICPLUS_PHY is not set |
| 663 | # CONFIG_REALTEK_PHY is not set | ||
| 646 | # CONFIG_FIXED_PHY is not set | 664 | # CONFIG_FIXED_PHY is not set |
| 647 | # CONFIG_MDIO_BITBANG is not set | 665 | # CONFIG_MDIO_BITBANG is not set |
| 648 | CONFIG_NET_ETHERNET=y | 666 | CONFIG_NET_ETHERNET=y |
| @@ -655,11 +673,14 @@ CONFIG_BFIN_MAC_RMII=y | |||
| 655 | # CONFIG_SMC91X is not set | 673 | # CONFIG_SMC91X is not set |
| 656 | # CONFIG_SMSC911X is not set | 674 | # CONFIG_SMSC911X is not set |
| 657 | # CONFIG_DM9000 is not set | 675 | # CONFIG_DM9000 is not set |
| 676 | # CONFIG_ENC28J60 is not set | ||
| 658 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 677 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 659 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 678 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 660 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 679 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 661 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 680 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 662 | # CONFIG_B44 is not set | 681 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set |
| 682 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 683 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 663 | CONFIG_NETDEV_1000=y | 684 | CONFIG_NETDEV_1000=y |
| 664 | # CONFIG_AX88180 is not set | 685 | # CONFIG_AX88180 is not set |
| 665 | CONFIG_NETDEV_10000=y | 686 | CONFIG_NETDEV_10000=y |
| @@ -669,6 +690,7 @@ CONFIG_NETDEV_10000=y | |||
| 669 | # | 690 | # |
| 670 | # CONFIG_WLAN_PRE80211 is not set | 691 | # CONFIG_WLAN_PRE80211 is not set |
| 671 | # CONFIG_WLAN_80211 is not set | 692 | # CONFIG_WLAN_80211 is not set |
| 693 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 672 | 694 | ||
| 673 | # | 695 | # |
| 674 | # USB Network Adapters | 696 | # USB Network Adapters |
| @@ -681,7 +703,6 @@ CONFIG_NETDEV_10000=y | |||
| 681 | # CONFIG_WAN is not set | 703 | # CONFIG_WAN is not set |
| 682 | # CONFIG_PPP is not set | 704 | # CONFIG_PPP is not set |
| 683 | # CONFIG_SLIP is not set | 705 | # CONFIG_SLIP is not set |
| 684 | # CONFIG_SHAPER is not set | ||
| 685 | # CONFIG_NETCONSOLE is not set | 706 | # CONFIG_NETCONSOLE is not set |
| 686 | # CONFIG_NETPOLL is not set | 707 | # CONFIG_NETPOLL is not set |
| 687 | # CONFIG_NET_POLL_CONTROLLER is not set | 708 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -692,7 +713,7 @@ CONFIG_NETDEV_10000=y | |||
| 692 | # Input device support | 713 | # Input device support |
| 693 | # | 714 | # |
| 694 | CONFIG_INPUT=y | 715 | CONFIG_INPUT=y |
| 695 | # CONFIG_INPUT_FF_MEMLESS is not set | 716 | CONFIG_INPUT_FF_MEMLESS=m |
| 696 | # CONFIG_INPUT_POLLDEV is not set | 717 | # CONFIG_INPUT_POLLDEV is not set |
| 697 | 718 | ||
| 698 | # | 719 | # |
| @@ -717,8 +738,9 @@ CONFIG_INPUT_MISC=y | |||
| 717 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | 738 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set |
| 718 | # CONFIG_INPUT_POWERMATE is not set | 739 | # CONFIG_INPUT_POWERMATE is not set |
| 719 | # CONFIG_INPUT_YEALINK is not set | 740 | # CONFIG_INPUT_YEALINK is not set |
| 741 | # CONFIG_INPUT_CM109 is not set | ||
| 720 | # CONFIG_INPUT_UINPUT is not set | 742 | # CONFIG_INPUT_UINPUT is not set |
| 721 | # CONFIG_TWI_KEYPAD is not set | 743 | # CONFIG_CONFIG_INPUT_PCF8574 is not set |
| 722 | 744 | ||
| 723 | # | 745 | # |
| 724 | # Hardware I/O ports | 746 | # Hardware I/O ports |
| @@ -734,16 +756,18 @@ CONFIG_INPUT_MISC=y | |||
| 734 | # CONFIG_BF5xx_PPIFCD is not set | 756 | # CONFIG_BF5xx_PPIFCD is not set |
| 735 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 757 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 736 | # CONFIG_BF5xx_PPI is not set | 758 | # CONFIG_BF5xx_PPI is not set |
| 737 | CONFIG_BFIN_OTP=y | ||
| 738 | # CONFIG_BFIN_OTP_WRITE_ENABLE is not set | ||
| 739 | # CONFIG_BFIN_SPORT is not set | 759 | # CONFIG_BFIN_SPORT is not set |
| 740 | # CONFIG_BFIN_TIMER_LATENCY is not set | 760 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 741 | # CONFIG_TWI_LCD is not set | 761 | # CONFIG_TWI_LCD is not set |
| 762 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 742 | CONFIG_SIMPLE_GPIO=m | 763 | CONFIG_SIMPLE_GPIO=m |
| 743 | CONFIG_VT=y | 764 | CONFIG_VT=y |
| 765 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 744 | CONFIG_VT_CONSOLE=y | 766 | CONFIG_VT_CONSOLE=y |
| 745 | CONFIG_HW_CONSOLE=y | 767 | CONFIG_HW_CONSOLE=y |
| 746 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 768 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 769 | # CONFIG_DEVKMEM is not set | ||
| 770 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 747 | # CONFIG_SERIAL_NONSTANDARD is not set | 771 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 748 | 772 | ||
| 749 | # | 773 | # |
| @@ -766,6 +790,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y | |||
| 766 | # CONFIG_SERIAL_BFIN_SPORT is not set | 790 | # CONFIG_SERIAL_BFIN_SPORT is not set |
| 767 | CONFIG_UNIX98_PTYS=y | 791 | CONFIG_UNIX98_PTYS=y |
| 768 | # CONFIG_LEGACY_PTYS is not set | 792 | # CONFIG_LEGACY_PTYS is not set |
| 793 | CONFIG_BFIN_OTP=y | ||
| 794 | # CONFIG_BFIN_OTP_WRITE_ENABLE is not set | ||
| 769 | 795 | ||
| 770 | # | 796 | # |
| 771 | # CAN, the car bus and industrial fieldbus | 797 | # CAN, the car bus and industrial fieldbus |
| @@ -773,44 +799,49 @@ CONFIG_UNIX98_PTYS=y | |||
| 773 | # CONFIG_CAN4LINUX is not set | 799 | # CONFIG_CAN4LINUX is not set |
| 774 | # CONFIG_IPMI_HANDLER is not set | 800 | # CONFIG_IPMI_HANDLER is not set |
| 775 | # CONFIG_HW_RANDOM is not set | 801 | # CONFIG_HW_RANDOM is not set |
| 776 | # CONFIG_GEN_RTC is not set | ||
| 777 | # CONFIG_R3964 is not set | 802 | # CONFIG_R3964 is not set |
| 778 | # CONFIG_RAW_DRIVER is not set | 803 | # CONFIG_RAW_DRIVER is not set |
| 779 | # CONFIG_TCG_TPM is not set | 804 | # CONFIG_TCG_TPM is not set |
| 780 | CONFIG_I2C=y | 805 | CONFIG_I2C=y |
| 781 | CONFIG_I2C_BOARDINFO=y | 806 | CONFIG_I2C_BOARDINFO=y |
| 782 | CONFIG_I2C_CHARDEV=m | 807 | CONFIG_I2C_CHARDEV=m |
| 808 | CONFIG_I2C_HELPER_AUTO=y | ||
| 783 | 809 | ||
| 784 | # | 810 | # |
| 785 | # I2C Algorithms | 811 | # I2C Hardware Bus support |
| 786 | # | 812 | # |
| 787 | # CONFIG_I2C_ALGOBIT is not set | ||
| 788 | # CONFIG_I2C_ALGOPCF is not set | ||
| 789 | # CONFIG_I2C_ALGOPCA is not set | ||
| 790 | 813 | ||
| 791 | # | 814 | # |
| 792 | # I2C Hardware Bus support | 815 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 793 | # | 816 | # |
| 794 | CONFIG_I2C_BLACKFIN_TWI=m | 817 | CONFIG_I2C_BLACKFIN_TWI=m |
| 795 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | 818 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 |
| 796 | # CONFIG_I2C_GPIO is not set | 819 | # CONFIG_I2C_GPIO is not set |
| 797 | # CONFIG_I2C_OCORES is not set | 820 | # CONFIG_I2C_OCORES is not set |
| 798 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 799 | # CONFIG_I2C_SIMTEC is not set | 821 | # CONFIG_I2C_SIMTEC is not set |
| 822 | |||
| 823 | # | ||
| 824 | # External I2C/SMBus adapter drivers | ||
| 825 | # | ||
| 826 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 800 | # CONFIG_I2C_TAOS_EVM is not set | 827 | # CONFIG_I2C_TAOS_EVM is not set |
| 801 | # CONFIG_I2C_STUB is not set | ||
| 802 | # CONFIG_I2C_TINY_USB is not set | 828 | # CONFIG_I2C_TINY_USB is not set |
| 803 | 829 | ||
| 804 | # | 830 | # |
| 831 | # Other I2C/SMBus bus drivers | ||
| 832 | # | ||
| 833 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 834 | # CONFIG_I2C_STUB is not set | ||
| 835 | |||
| 836 | # | ||
| 805 | # Miscellaneous I2C Chip support | 837 | # Miscellaneous I2C Chip support |
| 806 | # | 838 | # |
| 807 | # CONFIG_SENSORS_DS1337 is not set | ||
| 808 | # CONFIG_SENSORS_DS1374 is not set | ||
| 809 | # CONFIG_DS1682 is not set | 839 | # CONFIG_DS1682 is not set |
| 840 | # CONFIG_AT24 is not set | ||
| 810 | # CONFIG_SENSORS_AD5252 is not set | 841 | # CONFIG_SENSORS_AD5252 is not set |
| 811 | # CONFIG_SENSORS_EEPROM is not set | 842 | # CONFIG_SENSORS_EEPROM is not set |
| 812 | # CONFIG_SENSORS_PCF8574 is not set | 843 | # CONFIG_SENSORS_PCF8574 is not set |
| 813 | # CONFIG_SENSORS_PCF8575 is not set | 844 | # CONFIG_PCF8575 is not set |
| 814 | # CONFIG_SENSORS_PCA9539 is not set | 845 | # CONFIG_SENSORS_PCA9539 is not set |
| 815 | # CONFIG_SENSORS_PCF8591 is not set | 846 | # CONFIG_SENSORS_PCF8591 is not set |
| 816 | # CONFIG_SENSORS_MAX6875 is not set | 847 | # CONFIG_SENSORS_MAX6875 is not set |
| @@ -819,17 +850,15 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | |||
| 819 | # CONFIG_I2C_DEBUG_ALGO is not set | 850 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 820 | # CONFIG_I2C_DEBUG_BUS is not set | 851 | # CONFIG_I2C_DEBUG_BUS is not set |
| 821 | # CONFIG_I2C_DEBUG_CHIP is not set | 852 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 822 | |||
| 823 | # | ||
| 824 | # SPI support | ||
| 825 | # | ||
| 826 | CONFIG_SPI=y | 853 | CONFIG_SPI=y |
| 854 | # CONFIG_SPI_DEBUG is not set | ||
| 827 | CONFIG_SPI_MASTER=y | 855 | CONFIG_SPI_MASTER=y |
| 828 | 856 | ||
| 829 | # | 857 | # |
| 830 | # SPI Master Controller Drivers | 858 | # SPI Master Controller Drivers |
| 831 | # | 859 | # |
| 832 | CONFIG_SPI_BFIN=y | 860 | CONFIG_SPI_BFIN=y |
| 861 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 833 | # CONFIG_SPI_BITBANG is not set | 862 | # CONFIG_SPI_BITBANG is not set |
| 834 | 863 | ||
| 835 | # | 864 | # |
| @@ -838,11 +867,15 @@ CONFIG_SPI_BFIN=y | |||
| 838 | # CONFIG_SPI_AT25 is not set | 867 | # CONFIG_SPI_AT25 is not set |
| 839 | # CONFIG_SPI_SPIDEV is not set | 868 | # CONFIG_SPI_SPIDEV is not set |
| 840 | # CONFIG_SPI_TLE62X0 is not set | 869 | # CONFIG_SPI_TLE62X0 is not set |
| 870 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 871 | # CONFIG_GPIOLIB is not set | ||
| 841 | # CONFIG_W1 is not set | 872 | # CONFIG_W1 is not set |
| 842 | # CONFIG_POWER_SUPPLY is not set | 873 | # CONFIG_POWER_SUPPLY is not set |
| 843 | CONFIG_HWMON=y | 874 | CONFIG_HWMON=y |
| 844 | # CONFIG_HWMON_VID is not set | 875 | # CONFIG_HWMON_VID is not set |
| 876 | # CONFIG_SENSORS_AD7414 is not set | ||
| 845 | # CONFIG_SENSORS_AD7418 is not set | 877 | # CONFIG_SENSORS_AD7418 is not set |
| 878 | # CONFIG_SENSORS_ADCXX is not set | ||
| 846 | # CONFIG_SENSORS_ADM1021 is not set | 879 | # CONFIG_SENSORS_ADM1021 is not set |
| 847 | # CONFIG_SENSORS_ADM1025 is not set | 880 | # CONFIG_SENSORS_ADM1025 is not set |
| 848 | # CONFIG_SENSORS_ADM1026 is not set | 881 | # CONFIG_SENSORS_ADM1026 is not set |
| @@ -850,6 +883,7 @@ CONFIG_HWMON=y | |||
| 850 | # CONFIG_SENSORS_ADM1031 is not set | 883 | # CONFIG_SENSORS_ADM1031 is not set |
| 851 | # CONFIG_SENSORS_ADM9240 is not set | 884 | # CONFIG_SENSORS_ADM9240 is not set |
| 852 | # CONFIG_SENSORS_ADT7470 is not set | 885 | # CONFIG_SENSORS_ADT7470 is not set |
| 886 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 853 | # CONFIG_SENSORS_ATXP1 is not set | 887 | # CONFIG_SENSORS_ATXP1 is not set |
| 854 | # CONFIG_SENSORS_DS1621 is not set | 888 | # CONFIG_SENSORS_DS1621 is not set |
| 855 | # CONFIG_SENSORS_F71805F is not set | 889 | # CONFIG_SENSORS_F71805F is not set |
| @@ -870,6 +904,7 @@ CONFIG_HWMON=y | |||
| 870 | # CONFIG_SENSORS_LM90 is not set | 904 | # CONFIG_SENSORS_LM90 is not set |
| 871 | # CONFIG_SENSORS_LM92 is not set | 905 | # CONFIG_SENSORS_LM92 is not set |
| 872 | # CONFIG_SENSORS_LM93 is not set | 906 | # CONFIG_SENSORS_LM93 is not set |
| 907 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 873 | # CONFIG_SENSORS_MAX1619 is not set | 908 | # CONFIG_SENSORS_MAX1619 is not set |
| 874 | # CONFIG_SENSORS_MAX6650 is not set | 909 | # CONFIG_SENSORS_MAX6650 is not set |
| 875 | # CONFIG_SENSORS_PC87360 is not set | 910 | # CONFIG_SENSORS_PC87360 is not set |
| @@ -878,6 +913,7 @@ CONFIG_HWMON=y | |||
| 878 | # CONFIG_SENSORS_SMSC47M1 is not set | 913 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 879 | # CONFIG_SENSORS_SMSC47M192 is not set | 914 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 880 | # CONFIG_SENSORS_SMSC47B397 is not set | 915 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 916 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 881 | # CONFIG_SENSORS_THMC50 is not set | 917 | # CONFIG_SENSORS_THMC50 is not set |
| 882 | # CONFIG_SENSORS_VT1211 is not set | 918 | # CONFIG_SENSORS_VT1211 is not set |
| 883 | # CONFIG_SENSORS_W83781D is not set | 919 | # CONFIG_SENSORS_W83781D is not set |
| @@ -885,9 +921,12 @@ CONFIG_HWMON=y | |||
| 885 | # CONFIG_SENSORS_W83792D is not set | 921 | # CONFIG_SENSORS_W83792D is not set |
| 886 | # CONFIG_SENSORS_W83793 is not set | 922 | # CONFIG_SENSORS_W83793 is not set |
| 887 | # CONFIG_SENSORS_W83L785TS is not set | 923 | # CONFIG_SENSORS_W83L785TS is not set |
| 924 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 888 | # CONFIG_SENSORS_W83627HF is not set | 925 | # CONFIG_SENSORS_W83627HF is not set |
| 889 | # CONFIG_SENSORS_W83627EHF is not set | 926 | # CONFIG_SENSORS_W83627EHF is not set |
| 890 | # CONFIG_HWMON_DEBUG_CHIP is not set | 927 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 928 | # CONFIG_THERMAL is not set | ||
| 929 | # CONFIG_THERMAL_HWMON is not set | ||
| 891 | CONFIG_WATCHDOG=y | 930 | CONFIG_WATCHDOG=y |
| 892 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 931 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 893 | 932 | ||
| @@ -903,21 +942,29 @@ CONFIG_BFIN_WDT=y | |||
| 903 | # CONFIG_USBPCWATCHDOG is not set | 942 | # CONFIG_USBPCWATCHDOG is not set |
| 904 | 943 | ||
| 905 | # | 944 | # |
| 906 | # Sonics Silicon Backplane | ||
| 907 | # | ||
| 908 | CONFIG_SSB_POSSIBLE=y | ||
| 909 | # CONFIG_SSB is not set | ||
| 910 | |||
| 911 | # | ||
| 912 | # Multifunction device drivers | 945 | # Multifunction device drivers |
| 913 | # | 946 | # |
| 947 | # CONFIG_MFD_CORE is not set | ||
| 914 | # CONFIG_MFD_SM501 is not set | 948 | # CONFIG_MFD_SM501 is not set |
| 949 | # CONFIG_HTC_PASIC3 is not set | ||
| 950 | # CONFIG_MFD_TMIO is not set | ||
| 951 | # CONFIG_MFD_WM8400 is not set | ||
| 952 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 915 | 953 | ||
| 916 | # | 954 | # |
| 917 | # Multimedia devices | 955 | # Multimedia devices |
| 918 | # | 956 | # |
| 957 | |||
| 958 | # | ||
| 959 | # Multimedia core support | ||
| 960 | # | ||
| 919 | # CONFIG_VIDEO_DEV is not set | 961 | # CONFIG_VIDEO_DEV is not set |
| 920 | # CONFIG_DVB_CORE is not set | 962 | # CONFIG_DVB_CORE is not set |
| 963 | # CONFIG_VIDEO_MEDIA is not set | ||
| 964 | |||
| 965 | # | ||
| 966 | # Multimedia drivers | ||
| 967 | # | ||
| 921 | # CONFIG_DAB is not set | 968 | # CONFIG_DAB is not set |
| 922 | 969 | ||
| 923 | # | 970 | # |
| @@ -928,6 +975,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 928 | CONFIG_FB=y | 975 | CONFIG_FB=y |
| 929 | # CONFIG_FIRMWARE_EDID is not set | 976 | # CONFIG_FIRMWARE_EDID is not set |
| 930 | # CONFIG_FB_DDC is not set | 977 | # CONFIG_FB_DDC is not set |
| 978 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 931 | CONFIG_FB_CFB_FILLRECT=y | 979 | CONFIG_FB_CFB_FILLRECT=y |
| 932 | CONFIG_FB_CFB_COPYAREA=y | 980 | CONFIG_FB_CFB_COPYAREA=y |
| 933 | CONFIG_FB_CFB_IMAGEBLIT=y | 981 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -935,8 +983,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 935 | # CONFIG_FB_SYS_FILLRECT is not set | 983 | # CONFIG_FB_SYS_FILLRECT is not set |
| 936 | # CONFIG_FB_SYS_COPYAREA is not set | 984 | # CONFIG_FB_SYS_COPYAREA is not set |
| 937 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 985 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 986 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 938 | # CONFIG_FB_SYS_FOPS is not set | 987 | # CONFIG_FB_SYS_FOPS is not set |
| 939 | CONFIG_FB_DEFERRED_IO=y | ||
| 940 | # CONFIG_FB_SVGALIB is not set | 988 | # CONFIG_FB_SVGALIB is not set |
| 941 | # CONFIG_FB_MACMODES is not set | 989 | # CONFIG_FB_MACMODES is not set |
| 942 | # CONFIG_FB_BACKLIGHT is not set | 990 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -947,12 +995,18 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 947 | # Frame buffer hardware drivers | 995 | # Frame buffer hardware drivers |
| 948 | # | 996 | # |
| 949 | CONFIG_FB_BFIN_T350MCQB=y | 997 | CONFIG_FB_BFIN_T350MCQB=y |
| 998 | # CONFIG_FB_BFIN_LQ035Q1 is not set | ||
| 950 | # CONFIG_FB_BFIN_7393 is not set | 999 | # CONFIG_FB_BFIN_7393 is not set |
| 951 | # CONFIG_FB_S1D13XXX is not set | 1000 | # CONFIG_FB_S1D13XXX is not set |
| 952 | # CONFIG_FB_VIRTUAL is not set | 1001 | # CONFIG_FB_VIRTUAL is not set |
| 1002 | # CONFIG_FB_METRONOME is not set | ||
| 953 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 1003 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 954 | CONFIG_LCD_CLASS_DEVICE=m | 1004 | CONFIG_LCD_CLASS_DEVICE=m |
| 955 | CONFIG_LCD_LTV350QV=m | 1005 | CONFIG_LCD_LTV350QV=m |
| 1006 | # CONFIG_LCD_ILI9320 is not set | ||
| 1007 | # CONFIG_LCD_TDO24M is not set | ||
| 1008 | # CONFIG_LCD_VGG2432A4 is not set | ||
| 1009 | # CONFIG_LCD_PLATFORM is not set | ||
| 956 | CONFIG_BACKLIGHT_CLASS_DEVICE=m | 1010 | CONFIG_BACKLIGHT_CLASS_DEVICE=m |
| 957 | # CONFIG_BACKLIGHT_CORGI is not set | 1011 | # CONFIG_BACKLIGHT_CORGI is not set |
| 958 | 1012 | ||
| @@ -977,15 +1031,8 @@ CONFIG_LOGO=y | |||
| 977 | # CONFIG_LOGO_LINUX_CLUT224 is not set | 1031 | # CONFIG_LOGO_LINUX_CLUT224 is not set |
| 978 | # CONFIG_LOGO_BLACKFIN_VGA16 is not set | 1032 | # CONFIG_LOGO_BLACKFIN_VGA16 is not set |
| 979 | CONFIG_LOGO_BLACKFIN_CLUT224=y | 1033 | CONFIG_LOGO_BLACKFIN_CLUT224=y |
| 980 | |||
| 981 | # | ||
| 982 | # Sound | ||
| 983 | # | ||
| 984 | CONFIG_SOUND=m | 1034 | CONFIG_SOUND=m |
| 985 | 1035 | # CONFIG_SOUND_OSS_CORE is not set | |
| 986 | # | ||
| 987 | # Advanced Linux Sound Architecture | ||
| 988 | # | ||
| 989 | CONFIG_SND=m | 1036 | CONFIG_SND=m |
| 990 | CONFIG_SND_TIMER=m | 1037 | CONFIG_SND_TIMER=m |
| 991 | CONFIG_SND_PCM=m | 1038 | CONFIG_SND_PCM=m |
| @@ -997,62 +1044,38 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 997 | CONFIG_SND_VERBOSE_PROCFS=y | 1044 | CONFIG_SND_VERBOSE_PROCFS=y |
| 998 | # CONFIG_SND_VERBOSE_PRINTK is not set | 1045 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 999 | # CONFIG_SND_DEBUG is not set | 1046 | # CONFIG_SND_DEBUG is not set |
| 1000 | 1047 | CONFIG_SND_DRIVERS=y | |
| 1001 | # | ||
| 1002 | # Generic devices | ||
| 1003 | # | ||
| 1004 | # CONFIG_SND_DUMMY is not set | 1048 | # CONFIG_SND_DUMMY is not set |
| 1005 | # CONFIG_SND_MTPAV is not set | 1049 | # CONFIG_SND_MTPAV is not set |
| 1006 | # CONFIG_SND_SERIAL_U16550 is not set | 1050 | # CONFIG_SND_SERIAL_U16550 is not set |
| 1007 | # CONFIG_SND_MPU401 is not set | 1051 | # CONFIG_SND_MPU401 is not set |
| 1008 | 1052 | CONFIG_SND_SPI=y | |
| 1009 | # | ||
| 1010 | # SPI devices | ||
| 1011 | # | ||
| 1012 | 1053 | ||
| 1013 | # | 1054 | # |
| 1014 | # ALSA Blackfin devices | 1055 | # ALSA Blackfin devices |
| 1015 | # | 1056 | # |
| 1016 | # CONFIG_SND_BLACKFIN_AD1836 is not set | 1057 | # CONFIG_SND_BLACKFIN_AD1836 is not set |
| 1017 | # CONFIG_SND_BLACKFIN_AD1836_TDM is not set | ||
| 1018 | # CONFIG_SND_BLACKFIN_AD1836_I2S is not set | ||
| 1019 | # CONFIG_SND_BLACKFIN_AD1836_MULSUB is not set | ||
| 1020 | # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set | ||
| 1021 | # CONFIG_SND_BFIN_AD73311 is not set | ||
| 1022 | # CONFIG_SND_BFIN_AD73322 is not set | 1058 | # CONFIG_SND_BFIN_AD73322 is not set |
| 1023 | 1059 | CONFIG_SND_USB=y | |
| 1024 | # | ||
| 1025 | # USB devices | ||
| 1026 | # | ||
| 1027 | # CONFIG_SND_USB_AUDIO is not set | 1060 | # CONFIG_SND_USB_AUDIO is not set |
| 1028 | # CONFIG_SND_USB_CAIAQ is not set | 1061 | # CONFIG_SND_USB_CAIAQ is not set |
| 1029 | |||
| 1030 | # | ||
| 1031 | # System on Chip audio support | ||
| 1032 | # | ||
| 1033 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 1034 | CONFIG_SND_SOC=m | 1062 | CONFIG_SND_SOC=m |
| 1035 | CONFIG_SND_BF5XX_SOC=m | 1063 | CONFIG_SND_SOC_AC97_BUS=y |
| 1036 | CONFIG_SND_MMAP_SUPPORT=y | 1064 | CONFIG_SND_BF5XX_I2S=m |
| 1065 | CONFIG_SND_BF5XX_SOC_SSM2602=m | ||
| 1066 | # CONFIG_SND_BF5XX_SOC_AD73311 is not set | ||
| 1067 | CONFIG_SND_BF5XX_AC97=m | ||
| 1068 | CONFIG_SND_BF5XX_MMAP_SUPPORT=y | ||
| 1069 | # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set | ||
| 1070 | CONFIG_SND_BF5XX_SOC_SPORT=m | ||
| 1037 | CONFIG_SND_BF5XX_SOC_I2S=m | 1071 | CONFIG_SND_BF5XX_SOC_I2S=m |
| 1038 | CONFIG_SND_BF5XX_SOC_AC97=m | 1072 | CONFIG_SND_BF5XX_SOC_AC97=m |
| 1039 | # CONFIG_SND_BF5XX_SOC_WM8750 is not set | 1073 | CONFIG_SND_BF5XX_SOC_AD1980=m |
| 1040 | # CONFIG_SND_BF5XX_SOC_WM8731 is not set | ||
| 1041 | CONFIG_SND_BF5XX_SOC_SSM2602=m | ||
| 1042 | CONFIG_SND_BF5XX_SOC_BF5xx=m | ||
| 1043 | CONFIG_SND_BF5XX_SPORT_NUM=0 | 1074 | CONFIG_SND_BF5XX_SPORT_NUM=0 |
| 1044 | # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set | 1075 | # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set |
| 1045 | 1076 | # CONFIG_SND_SOC_ALL_CODECS is not set | |
| 1046 | # | ||
| 1047 | # SoC Audio support for SuperH | ||
| 1048 | # | ||
| 1049 | CONFIG_SND_SOC_SSM2602=m | ||
| 1050 | # CONFIG_SND_SOC_SSM2602_SPI is not set | ||
| 1051 | CONFIG_SND_SOC_AD1980=m | 1077 | CONFIG_SND_SOC_AD1980=m |
| 1052 | 1078 | CONFIG_SND_SOC_SSM2602=m | |
| 1053 | # | ||
| 1054 | # Open Sound System | ||
| 1055 | # | ||
| 1056 | # CONFIG_SOUND_PRIME is not set | 1079 | # CONFIG_SOUND_PRIME is not set |
| 1057 | CONFIG_AC97_BUS=m | 1080 | CONFIG_AC97_BUS=m |
| 1058 | CONFIG_HID_SUPPORT=y | 1081 | CONFIG_HID_SUPPORT=y |
| @@ -1064,15 +1087,43 @@ CONFIG_HID=y | |||
| 1064 | # USB Input Devices | 1087 | # USB Input Devices |
| 1065 | # | 1088 | # |
| 1066 | CONFIG_USB_HID=y | 1089 | CONFIG_USB_HID=y |
| 1067 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | 1090 | # CONFIG_HID_PID is not set |
| 1068 | # CONFIG_HID_FF is not set | ||
| 1069 | # CONFIG_USB_HIDDEV is not set | 1091 | # CONFIG_USB_HIDDEV is not set |
| 1092 | |||
| 1093 | # | ||
| 1094 | # Special HID drivers | ||
| 1095 | # | ||
| 1096 | CONFIG_HID_COMPAT=y | ||
| 1097 | CONFIG_HID_A4TECH=y | ||
| 1098 | CONFIG_HID_APPLE=y | ||
| 1099 | CONFIG_HID_BELKIN=y | ||
| 1100 | CONFIG_HID_BRIGHT=y | ||
| 1101 | CONFIG_HID_CHERRY=y | ||
| 1102 | CONFIG_HID_CHICONY=y | ||
| 1103 | CONFIG_HID_CYPRESS=y | ||
| 1104 | CONFIG_HID_DELL=y | ||
| 1105 | CONFIG_HID_EZKEY=y | ||
| 1106 | CONFIG_HID_GYRATION=y | ||
| 1107 | CONFIG_HID_LOGITECH=y | ||
| 1108 | # CONFIG_LOGITECH_FF is not set | ||
| 1109 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1110 | CONFIG_HID_MICROSOFT=y | ||
| 1111 | CONFIG_HID_MONTEREY=y | ||
| 1112 | CONFIG_HID_PANTHERLORD=y | ||
| 1113 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1114 | CONFIG_HID_PETALYNX=y | ||
| 1115 | CONFIG_HID_SAMSUNG=y | ||
| 1116 | CONFIG_HID_SONY=y | ||
| 1117 | CONFIG_HID_SUNPLUS=y | ||
| 1118 | CONFIG_THRUSTMASTER_FF=m | ||
| 1119 | CONFIG_ZEROPLUS_FF=m | ||
| 1070 | CONFIG_USB_SUPPORT=y | 1120 | CONFIG_USB_SUPPORT=y |
| 1071 | CONFIG_USB_ARCH_HAS_HCD=y | 1121 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1072 | # CONFIG_USB_ARCH_HAS_OHCI is not set | 1122 | # CONFIG_USB_ARCH_HAS_OHCI is not set |
| 1073 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 1123 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| 1074 | CONFIG_USB=y | 1124 | CONFIG_USB=y |
| 1075 | # CONFIG_USB_DEBUG is not set | 1125 | # CONFIG_USB_DEBUG is not set |
| 1126 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 1076 | 1127 | ||
| 1077 | # | 1128 | # |
| 1078 | # Miscellaneous USB options | 1129 | # Miscellaneous USB options |
| @@ -1083,15 +1134,20 @@ CONFIG_USB_DEVICE_CLASS=y | |||
| 1083 | # CONFIG_USB_OTG is not set | 1134 | # CONFIG_USB_OTG is not set |
| 1084 | # CONFIG_USB_OTG_WHITELIST is not set | 1135 | # CONFIG_USB_OTG_WHITELIST is not set |
| 1085 | CONFIG_USB_OTG_BLACKLIST_HUB=y | 1136 | CONFIG_USB_OTG_BLACKLIST_HUB=y |
| 1137 | CONFIG_USB_MON=y | ||
| 1138 | # CONFIG_USB_WUSB is not set | ||
| 1139 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1086 | 1140 | ||
| 1087 | # | 1141 | # |
| 1088 | # USB Host Controller Drivers | 1142 | # USB Host Controller Drivers |
| 1089 | # | 1143 | # |
| 1144 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1090 | # CONFIG_USB_ISP116X_HCD is not set | 1145 | # CONFIG_USB_ISP116X_HCD is not set |
| 1091 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1092 | # CONFIG_USB_ISP1760_HCD is not set | 1146 | # CONFIG_USB_ISP1760_HCD is not set |
| 1147 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1093 | # CONFIG_USB_SL811_HCD is not set | 1148 | # CONFIG_USB_SL811_HCD is not set |
| 1094 | # CONFIG_USB_R8A66597_HCD is not set | 1149 | # CONFIG_USB_R8A66597_HCD is not set |
| 1150 | # CONFIG_USB_HWA_HCD is not set | ||
| 1095 | CONFIG_USB_MUSB_HDRC=y | 1151 | CONFIG_USB_MUSB_HDRC=y |
| 1096 | CONFIG_USB_MUSB_SOC=y | 1152 | CONFIG_USB_MUSB_SOC=y |
| 1097 | 1153 | ||
| @@ -1103,13 +1159,15 @@ CONFIG_USB_MUSB_HOST=y | |||
| 1103 | # CONFIG_USB_MUSB_OTG is not set | 1159 | # CONFIG_USB_MUSB_OTG is not set |
| 1104 | CONFIG_USB_MUSB_HDRC_HCD=y | 1160 | CONFIG_USB_MUSB_HDRC_HCD=y |
| 1105 | CONFIG_MUSB_PIO_ONLY=y | 1161 | CONFIG_MUSB_PIO_ONLY=y |
| 1106 | CONFIG_USB_MUSB_LOGLEVEL=0 | 1162 | # CONFIG_USB_MUSB_DEBUG is not set |
| 1107 | 1163 | ||
| 1108 | # | 1164 | # |
| 1109 | # USB Device Class drivers | 1165 | # USB Device Class drivers |
| 1110 | # | 1166 | # |
| 1111 | # CONFIG_USB_ACM is not set | 1167 | # CONFIG_USB_ACM is not set |
| 1112 | # CONFIG_USB_PRINTER is not set | 1168 | # CONFIG_USB_PRINTER is not set |
| 1169 | # CONFIG_USB_WDM is not set | ||
| 1170 | # CONFIG_USB_TMC is not set | ||
| 1113 | 1171 | ||
| 1114 | # | 1172 | # |
| 1115 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1173 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' |
| @@ -1124,15 +1182,10 @@ CONFIG_USB_MUSB_LOGLEVEL=0 | |||
| 1124 | # USB Imaging devices | 1182 | # USB Imaging devices |
| 1125 | # | 1183 | # |
| 1126 | # CONFIG_USB_MDC800 is not set | 1184 | # CONFIG_USB_MDC800 is not set |
| 1127 | CONFIG_USB_MON=y | ||
| 1128 | 1185 | ||
| 1129 | # | 1186 | # |
| 1130 | # USB port drivers | 1187 | # USB port drivers |
| 1131 | # | 1188 | # |
| 1132 | |||
| 1133 | # | ||
| 1134 | # USB Serial Converter support | ||
| 1135 | # | ||
| 1136 | # CONFIG_USB_SERIAL is not set | 1189 | # CONFIG_USB_SERIAL is not set |
| 1137 | 1190 | ||
| 1138 | # | 1191 | # |
| @@ -1141,7 +1194,7 @@ CONFIG_USB_MON=y | |||
| 1141 | # CONFIG_USB_EMI62 is not set | 1194 | # CONFIG_USB_EMI62 is not set |
| 1142 | # CONFIG_USB_EMI26 is not set | 1195 | # CONFIG_USB_EMI26 is not set |
| 1143 | # CONFIG_USB_ADUTUX is not set | 1196 | # CONFIG_USB_ADUTUX is not set |
| 1144 | # CONFIG_USB_AUERSWALD is not set | 1197 | # CONFIG_USB_SEVSEG is not set |
| 1145 | # CONFIG_USB_RIO500 is not set | 1198 | # CONFIG_USB_RIO500 is not set |
| 1146 | # CONFIG_USB_LEGOTOWER is not set | 1199 | # CONFIG_USB_LEGOTOWER is not set |
| 1147 | # CONFIG_USB_LCD is not set | 1200 | # CONFIG_USB_LCD is not set |
| @@ -1157,17 +1210,13 @@ CONFIG_USB_MON=y | |||
| 1157 | # CONFIG_USB_LD is not set | 1210 | # CONFIG_USB_LD is not set |
| 1158 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1211 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1159 | # CONFIG_USB_IOWARRIOR is not set | 1212 | # CONFIG_USB_IOWARRIOR is not set |
| 1160 | 1213 | # CONFIG_USB_ISIGHTFW is not set | |
| 1161 | # | 1214 | # CONFIG_USB_VST is not set |
| 1162 | # USB DSL modem support | ||
| 1163 | # | ||
| 1164 | |||
| 1165 | # | ||
| 1166 | # USB Gadget Support | ||
| 1167 | # | ||
| 1168 | # CONFIG_USB_GADGET is not set | 1215 | # CONFIG_USB_GADGET is not set |
| 1169 | # CONFIG_MMC is not set | 1216 | # CONFIG_MMC is not set |
| 1217 | # CONFIG_MEMSTICK is not set | ||
| 1170 | # CONFIG_NEW_LEDS is not set | 1218 | # CONFIG_NEW_LEDS is not set |
| 1219 | # CONFIG_ACCESSIBILITY is not set | ||
| 1171 | CONFIG_RTC_LIB=y | 1220 | CONFIG_RTC_LIB=y |
| 1172 | CONFIG_RTC_CLASS=y | 1221 | CONFIG_RTC_CLASS=y |
| 1173 | CONFIG_RTC_HCTOSYS=y | 1222 | CONFIG_RTC_HCTOSYS=y |
| @@ -1196,51 +1245,57 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1196 | # CONFIG_RTC_DRV_PCF8563 is not set | 1245 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1197 | # CONFIG_RTC_DRV_PCF8583 is not set | 1246 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1198 | # CONFIG_RTC_DRV_M41T80 is not set | 1247 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1248 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1249 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1199 | 1250 | ||
| 1200 | # | 1251 | # |
| 1201 | # SPI RTC drivers | 1252 | # SPI RTC drivers |
| 1202 | # | 1253 | # |
| 1203 | # CONFIG_RTC_DRV_RS5C348 is not set | 1254 | # CONFIG_RTC_DRV_M41T94 is not set |
| 1255 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1204 | # CONFIG_RTC_DRV_MAX6902 is not set | 1256 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 1257 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1258 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1259 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1205 | 1260 | ||
| 1206 | # | 1261 | # |
| 1207 | # Platform RTC drivers | 1262 | # Platform RTC drivers |
| 1208 | # | 1263 | # |
| 1264 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1265 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1209 | # CONFIG_RTC_DRV_DS1553 is not set | 1266 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1210 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1211 | # CONFIG_RTC_DRV_DS1742 is not set | 1267 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1268 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1212 | # CONFIG_RTC_DRV_M48T86 is not set | 1269 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1270 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1213 | # CONFIG_RTC_DRV_M48T59 is not set | 1271 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1272 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1214 | # CONFIG_RTC_DRV_V3020 is not set | 1273 | # CONFIG_RTC_DRV_V3020 is not set |
| 1215 | 1274 | ||
| 1216 | # | 1275 | # |
| 1217 | # on-CPU RTC drivers | 1276 | # on-CPU RTC drivers |
| 1218 | # | 1277 | # |
| 1219 | CONFIG_RTC_DRV_BFIN=y | 1278 | CONFIG_RTC_DRV_BFIN=y |
| 1220 | 1279 | # CONFIG_DMADEVICES is not set | |
| 1221 | # | ||
| 1222 | # Userspace I/O | ||
| 1223 | # | ||
| 1224 | # CONFIG_UIO is not set | 1280 | # CONFIG_UIO is not set |
| 1281 | # CONFIG_STAGING is not set | ||
| 1225 | 1282 | ||
| 1226 | # | 1283 | # |
| 1227 | # File systems | 1284 | # File systems |
| 1228 | # | 1285 | # |
| 1229 | # CONFIG_EXT2_FS is not set | 1286 | # CONFIG_EXT2_FS is not set |
| 1230 | # CONFIG_EXT3_FS is not set | 1287 | # CONFIG_EXT3_FS is not set |
| 1231 | # CONFIG_EXT4DEV_FS is not set | 1288 | # CONFIG_EXT4_FS is not set |
| 1232 | # CONFIG_REISERFS_FS is not set | 1289 | # CONFIG_REISERFS_FS is not set |
| 1233 | # CONFIG_JFS_FS is not set | 1290 | # CONFIG_JFS_FS is not set |
| 1234 | # CONFIG_FS_POSIX_ACL is not set | 1291 | # CONFIG_FS_POSIX_ACL is not set |
| 1292 | CONFIG_FILE_LOCKING=y | ||
| 1235 | # CONFIG_XFS_FS is not set | 1293 | # CONFIG_XFS_FS is not set |
| 1236 | # CONFIG_GFS2_FS is not set | ||
| 1237 | # CONFIG_OCFS2_FS is not set | 1294 | # CONFIG_OCFS2_FS is not set |
| 1238 | # CONFIG_MINIX_FS is not set | 1295 | # CONFIG_DNOTIFY is not set |
| 1239 | # CONFIG_ROMFS_FS is not set | ||
| 1240 | CONFIG_INOTIFY=y | 1296 | CONFIG_INOTIFY=y |
| 1241 | CONFIG_INOTIFY_USER=y | 1297 | CONFIG_INOTIFY_USER=y |
| 1242 | # CONFIG_QUOTA is not set | 1298 | # CONFIG_QUOTA is not set |
| 1243 | # CONFIG_DNOTIFY is not set | ||
| 1244 | # CONFIG_AUTOFS_FS is not set | 1299 | # CONFIG_AUTOFS_FS is not set |
| 1245 | # CONFIG_AUTOFS4_FS is not set | 1300 | # CONFIG_AUTOFS4_FS is not set |
| 1246 | # CONFIG_FUSE_FS is not set | 1301 | # CONFIG_FUSE_FS is not set |
| @@ -1280,11 +1335,11 @@ CONFIG_SYSFS=y | |||
| 1280 | # CONFIG_EFS_FS is not set | 1335 | # CONFIG_EFS_FS is not set |
| 1281 | CONFIG_YAFFS_FS=m | 1336 | CONFIG_YAFFS_FS=m |
| 1282 | CONFIG_YAFFS_YAFFS1=y | 1337 | CONFIG_YAFFS_YAFFS1=y |
| 1338 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1283 | # CONFIG_YAFFS_DOES_ECC is not set | 1339 | # CONFIG_YAFFS_DOES_ECC is not set |
| 1284 | CONFIG_YAFFS_YAFFS2=y | 1340 | CONFIG_YAFFS_YAFFS2=y |
| 1285 | CONFIG_YAFFS_AUTO_YAFFS2=y | 1341 | CONFIG_YAFFS_AUTO_YAFFS2=y |
| 1286 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | 1342 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set |
| 1287 | CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 | ||
| 1288 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | 1343 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 1289 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | 1344 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 1290 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | 1345 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| @@ -1301,8 +1356,11 @@ CONFIG_JFFS2_RTIME=y | |||
| 1301 | # CONFIG_JFFS2_RUBIN is not set | 1356 | # CONFIG_JFFS2_RUBIN is not set |
| 1302 | # CONFIG_CRAMFS is not set | 1357 | # CONFIG_CRAMFS is not set |
| 1303 | # CONFIG_VXFS_FS is not set | 1358 | # CONFIG_VXFS_FS is not set |
| 1359 | # CONFIG_MINIX_FS is not set | ||
| 1360 | # CONFIG_OMFS_FS is not set | ||
| 1304 | # CONFIG_HPFS_FS is not set | 1361 | # CONFIG_HPFS_FS is not set |
| 1305 | # CONFIG_QNX4FS_FS is not set | 1362 | # CONFIG_QNX4FS_FS is not set |
| 1363 | # CONFIG_ROMFS_FS is not set | ||
| 1306 | # CONFIG_SYSV_FS is not set | 1364 | # CONFIG_SYSV_FS is not set |
| 1307 | # CONFIG_UFS_FS is not set | 1365 | # CONFIG_UFS_FS is not set |
| 1308 | CONFIG_NETWORK_FILESYSTEMS=y | 1366 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1310,13 +1368,12 @@ CONFIG_NFS_FS=m | |||
| 1310 | CONFIG_NFS_V3=y | 1368 | CONFIG_NFS_V3=y |
| 1311 | # CONFIG_NFS_V3_ACL is not set | 1369 | # CONFIG_NFS_V3_ACL is not set |
| 1312 | # CONFIG_NFS_V4 is not set | 1370 | # CONFIG_NFS_V4 is not set |
| 1313 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1314 | # CONFIG_NFSD is not set | 1371 | # CONFIG_NFSD is not set |
| 1315 | CONFIG_LOCKD=m | 1372 | CONFIG_LOCKD=m |
| 1316 | CONFIG_LOCKD_V4=y | 1373 | CONFIG_LOCKD_V4=y |
| 1317 | CONFIG_NFS_COMMON=y | 1374 | CONFIG_NFS_COMMON=y |
| 1318 | CONFIG_SUNRPC=m | 1375 | CONFIG_SUNRPC=m |
| 1319 | # CONFIG_SUNRPC_BIND34 is not set | 1376 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1320 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1377 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1321 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1378 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1322 | CONFIG_SMB_FS=m | 1379 | CONFIG_SMB_FS=m |
| @@ -1372,9 +1429,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1372 | # CONFIG_NLS_KOI8_U is not set | 1429 | # CONFIG_NLS_KOI8_U is not set |
| 1373 | # CONFIG_NLS_UTF8 is not set | 1430 | # CONFIG_NLS_UTF8 is not set |
| 1374 | # CONFIG_DLM is not set | 1431 | # CONFIG_DLM is not set |
| 1375 | CONFIG_INSTRUMENTATION=y | ||
| 1376 | # CONFIG_PROFILING is not set | ||
| 1377 | # CONFIG_MARKERS is not set | ||
| 1378 | 1432 | ||
| 1379 | # | 1433 | # |
| 1380 | # Kernel hacking | 1434 | # Kernel hacking |
| @@ -1382,14 +1436,53 @@ CONFIG_INSTRUMENTATION=y | |||
| 1382 | # CONFIG_PRINTK_TIME is not set | 1436 | # CONFIG_PRINTK_TIME is not set |
| 1383 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1437 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1384 | CONFIG_ENABLE_MUST_CHECK=y | 1438 | CONFIG_ENABLE_MUST_CHECK=y |
| 1439 | CONFIG_FRAME_WARN=1024 | ||
| 1385 | # CONFIG_MAGIC_SYSRQ is not set | 1440 | # CONFIG_MAGIC_SYSRQ is not set |
| 1386 | # CONFIG_UNUSED_SYMBOLS is not set | 1441 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1387 | CONFIG_DEBUG_FS=y | 1442 | CONFIG_DEBUG_FS=y |
| 1388 | # CONFIG_HEADERS_CHECK is not set | 1443 | # CONFIG_HEADERS_CHECK is not set |
| 1389 | # CONFIG_DEBUG_KERNEL is not set | 1444 | CONFIG_DEBUG_KERNEL=y |
| 1445 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1446 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1447 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1448 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1449 | CONFIG_SCHED_DEBUG=y | ||
| 1450 | # CONFIG_SCHEDSTATS is not set | ||
| 1451 | # CONFIG_TIMER_STATS is not set | ||
| 1452 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1453 | # CONFIG_DEBUG_SLAB is not set | ||
| 1454 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1455 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1456 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1457 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1458 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1459 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1460 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1390 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1461 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1462 | CONFIG_DEBUG_INFO=y | ||
| 1463 | # CONFIG_DEBUG_VM is not set | ||
| 1464 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1465 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1466 | # CONFIG_DEBUG_LIST is not set | ||
| 1467 | # CONFIG_DEBUG_SG is not set | ||
| 1468 | # CONFIG_FRAME_POINTER is not set | ||
| 1469 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1470 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1471 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1472 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1473 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1474 | # CONFIG_FAULT_INJECTION is not set | ||
| 1475 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1476 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1391 | # CONFIG_SAMPLES is not set | 1477 | # CONFIG_SAMPLES is not set |
| 1478 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1479 | # CONFIG_KGDB is not set | ||
| 1480 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1481 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1482 | CONFIG_DEBUG_VERBOSE=y | ||
| 1392 | CONFIG_DEBUG_MMRS=y | 1483 | CONFIG_DEBUG_MMRS=y |
| 1484 | # CONFIG_DEBUG_HWERR is not set | ||
| 1485 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 1393 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1486 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1394 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1487 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1395 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1488 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -1407,10 +1500,95 @@ CONFIG_ACCESS_CHECK=y | |||
| 1407 | # | 1500 | # |
| 1408 | # CONFIG_KEYS is not set | 1501 | # CONFIG_KEYS is not set |
| 1409 | CONFIG_SECURITY=y | 1502 | CONFIG_SECURITY=y |
| 1503 | # CONFIG_SECURITYFS is not set | ||
| 1410 | # CONFIG_SECURITY_NETWORK is not set | 1504 | # CONFIG_SECURITY_NETWORK is not set |
| 1411 | # CONFIG_SECURITY_CAPABILITIES is not set | 1505 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1412 | # CONFIG_SECURITY_ROOTPLUG is not set | 1506 | # CONFIG_SECURITY_ROOTPLUG is not set |
| 1413 | # CONFIG_CRYPTO is not set | 1507 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 |
| 1508 | CONFIG_CRYPTO=y | ||
| 1509 | |||
| 1510 | # | ||
| 1511 | # Crypto core or helper | ||
| 1512 | # | ||
| 1513 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1514 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1515 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1516 | # CONFIG_CRYPTO_NULL is not set | ||
| 1517 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1518 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1519 | # CONFIG_CRYPTO_TEST is not set | ||
| 1520 | |||
| 1521 | # | ||
| 1522 | # Authenticated Encryption with Associated Data | ||
| 1523 | # | ||
| 1524 | # CONFIG_CRYPTO_CCM is not set | ||
| 1525 | # CONFIG_CRYPTO_GCM is not set | ||
| 1526 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1527 | |||
| 1528 | # | ||
| 1529 | # Block modes | ||
| 1530 | # | ||
| 1531 | # CONFIG_CRYPTO_CBC is not set | ||
| 1532 | # CONFIG_CRYPTO_CTR is not set | ||
| 1533 | # CONFIG_CRYPTO_CTS is not set | ||
| 1534 | # CONFIG_CRYPTO_ECB is not set | ||
| 1535 | # CONFIG_CRYPTO_LRW is not set | ||
| 1536 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1537 | # CONFIG_CRYPTO_XTS is not set | ||
| 1538 | |||
| 1539 | # | ||
| 1540 | # Hash modes | ||
| 1541 | # | ||
| 1542 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1543 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1544 | |||
| 1545 | # | ||
| 1546 | # Digest | ||
| 1547 | # | ||
| 1548 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1549 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1550 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1551 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1552 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1553 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1554 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1555 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1556 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1557 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1558 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1559 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1560 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1561 | |||
| 1562 | # | ||
| 1563 | # Ciphers | ||
| 1564 | # | ||
| 1565 | # CONFIG_CRYPTO_AES is not set | ||
| 1566 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1567 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1568 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1569 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1570 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1571 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1572 | # CONFIG_CRYPTO_DES is not set | ||
| 1573 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1574 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1575 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1576 | # CONFIG_CRYPTO_SEED is not set | ||
| 1577 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1578 | # CONFIG_CRYPTO_TEA is not set | ||
| 1579 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1580 | |||
| 1581 | # | ||
| 1582 | # Compression | ||
| 1583 | # | ||
| 1584 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1585 | # CONFIG_CRYPTO_LZO is not set | ||
| 1586 | |||
| 1587 | # | ||
| 1588 | # Random Number Generation | ||
| 1589 | # | ||
| 1590 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1591 | CONFIG_CRYPTO_HW=y | ||
| 1414 | 1592 | ||
| 1415 | # | 1593 | # |
| 1416 | # Library routines | 1594 | # Library routines |
| @@ -1418,6 +1596,7 @@ CONFIG_SECURITY=y | |||
| 1418 | CONFIG_BITREVERSE=y | 1596 | CONFIG_BITREVERSE=y |
| 1419 | CONFIG_CRC_CCITT=m | 1597 | CONFIG_CRC_CCITT=m |
| 1420 | # CONFIG_CRC16 is not set | 1598 | # CONFIG_CRC16 is not set |
| 1599 | # CONFIG_CRC_T10DIF is not set | ||
| 1421 | # CONFIG_CRC_ITU_T is not set | 1600 | # CONFIG_CRC_ITU_T is not set |
| 1422 | CONFIG_CRC32=y | 1601 | CONFIG_CRC32=y |
| 1423 | # CONFIG_CRC7 is not set | 1602 | # CONFIG_CRC7 is not set |
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index deeb5e45effb..92afd988449b 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24.7 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # | 4 | # |
| 5 | # CONFIG_MMU is not set | 5 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 6 | # CONFIG_FPU is not set |
| @@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 9 | CONFIG_BLACKFIN=y | 9 | CONFIG_BLACKFIN=y |
| 10 | CONFIG_ZONE_DMA=y | 10 | CONFIG_ZONE_DMA=y |
| 11 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 11 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 13 | CONFIG_GENERIC_HWEIGHT=y | 12 | CONFIG_GENERIC_HWEIGHT=y |
| 14 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| @@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 31 | # CONFIG_POSIX_MQUEUE is not set | 30 | # CONFIG_POSIX_MQUEUE is not set |
| 32 | # CONFIG_BSD_PROCESS_ACCT is not set | 31 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 33 | # CONFIG_TASKSTATS is not set | 32 | # CONFIG_TASKSTATS is not set |
| 34 | # CONFIG_USER_NS is not set | ||
| 35 | # CONFIG_PID_NS is not set | ||
| 36 | # CONFIG_AUDIT is not set | 33 | # CONFIG_AUDIT is not set |
| 37 | CONFIG_IKCONFIG=y | 34 | CONFIG_IKCONFIG=y |
| 38 | CONFIG_IKCONFIG_PROC=y | 35 | CONFIG_IKCONFIG_PROC=y |
| 39 | CONFIG_LOG_BUF_SHIFT=14 | 36 | CONFIG_LOG_BUF_SHIFT=14 |
| 40 | # CONFIG_CGROUPS is not set | 37 | # CONFIG_CGROUPS is not set |
| 41 | CONFIG_FAIR_GROUP_SCHED=y | 38 | # CONFIG_GROUP_SCHED is not set |
| 42 | CONFIG_FAIR_USER_SCHED=y | 39 | # CONFIG_SYSFS_DEPRECATED is not set |
| 43 | # CONFIG_FAIR_CGROUP_SCHED is not set | 40 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 44 | CONFIG_SYSFS_DEPRECATED=y | ||
| 45 | # CONFIG_RELAY is not set | 41 | # CONFIG_RELAY is not set |
| 42 | # CONFIG_NAMESPACES is not set | ||
| 46 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 47 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y | |||
| 51 | CONFIG_UID16=y | 48 | CONFIG_UID16=y |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 49 | CONFIG_SYSCTL_SYSCALL=y |
| 53 | CONFIG_KALLSYMS=y | 50 | CONFIG_KALLSYMS=y |
| 51 | # CONFIG_KALLSYMS_ALL is not set | ||
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | CONFIG_HOTPLUG=y | 53 | CONFIG_HOTPLUG=y |
| 56 | CONFIG_PRINTK=y | 54 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 55 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 56 | # CONFIG_ELF_CORE is not set |
| 57 | CONFIG_COMPAT_BRK=y | ||
| 59 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 59 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 60 | CONFIG_ANON_INODES=y |
| 62 | CONFIG_EPOLL=y | 61 | CONFIG_EPOLL=y |
| 63 | CONFIG_SIGNALFD=y | 62 | CONFIG_SIGNALFD=y |
| 63 | CONFIG_TIMERFD=y | ||
| 64 | CONFIG_EVENTFD=y | 64 | CONFIG_EVENTFD=y |
| 65 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 66 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| 70 | # CONFIG_PROFILING is not set | ||
| 71 | # CONFIG_MARKERS is not set | ||
| 72 | CONFIG_HAVE_OPROFILE=y | ||
| 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 69 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 70 | CONFIG_RT_MUTEXES=y | 75 | CONFIG_RT_MUTEXES=y |
| 71 | CONFIG_TINY_SHMEM=y | 76 | CONFIG_TINY_SHMEM=y |
| 72 | CONFIG_BASE_SMALL=0 | 77 | CONFIG_BASE_SMALL=0 |
| 73 | CONFIG_MODULES=y | 78 | CONFIG_MODULES=y |
| 79 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 74 | CONFIG_MODULE_UNLOAD=y | 80 | CONFIG_MODULE_UNLOAD=y |
| 75 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 81 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 76 | # CONFIG_MODVERSIONS is not set | 82 | # CONFIG_MODVERSIONS is not set |
| @@ -81,6 +87,7 @@ CONFIG_BLOCK=y | |||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | 87 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 82 | # CONFIG_LSF is not set | 88 | # CONFIG_LSF is not set |
| 83 | # CONFIG_BLK_DEV_BSG is not set | 89 | # CONFIG_BLK_DEV_BSG is not set |
| 90 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 84 | 91 | ||
| 85 | # | 92 | # |
| 86 | # IO Schedulers | 93 | # IO Schedulers |
| @@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y | |||
| 94 | # CONFIG_DEFAULT_CFQ is not set | 101 | # CONFIG_DEFAULT_CFQ is not set |
| 95 | # CONFIG_DEFAULT_NOOP is not set | 102 | # CONFIG_DEFAULT_NOOP is not set |
| 96 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 103 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 104 | CONFIG_CLASSIC_RCU=y | ||
| 97 | # CONFIG_PREEMPT_NONE is not set | 105 | # CONFIG_PREEMPT_NONE is not set |
| 98 | CONFIG_PREEMPT_VOLUNTARY=y | 106 | CONFIG_PREEMPT_VOLUNTARY=y |
| 99 | # CONFIG_PREEMPT is not set | 107 | # CONFIG_PREEMPT is not set |
| 108 | CONFIG_FREEZER=y | ||
| 100 | 109 | ||
| 101 | # | 110 | # |
| 102 | # Blackfin Processor Options | 111 | # Blackfin Processor Options |
| @@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 105 | # | 114 | # |
| 106 | # Processor and Board Settings | 115 | # Processor and Board Settings |
| 107 | # | 116 | # |
| 117 | # CONFIG_BF512 is not set | ||
| 118 | # CONFIG_BF514 is not set | ||
| 119 | # CONFIG_BF516 is not set | ||
| 120 | # CONFIG_BF518 is not set | ||
| 108 | # CONFIG_BF522 is not set | 121 | # CONFIG_BF522 is not set |
| 109 | # CONFIG_BF523 is not set | 122 | # CONFIG_BF523 is not set |
| 110 | # CONFIG_BF524 is not set | 123 | # CONFIG_BF524 is not set |
| @@ -117,24 +130,30 @@ CONFIG_BF533=y | |||
| 117 | # CONFIG_BF534 is not set | 130 | # CONFIG_BF534 is not set |
| 118 | # CONFIG_BF536 is not set | 131 | # CONFIG_BF536 is not set |
| 119 | # CONFIG_BF537 is not set | 132 | # CONFIG_BF537 is not set |
| 133 | # CONFIG_BF538 is not set | ||
| 134 | # CONFIG_BF539 is not set | ||
| 120 | # CONFIG_BF542 is not set | 135 | # CONFIG_BF542 is not set |
| 121 | # CONFIG_BF544 is not set | 136 | # CONFIG_BF544 is not set |
| 122 | # CONFIG_BF547 is not set | 137 | # CONFIG_BF547 is not set |
| 123 | # CONFIG_BF548 is not set | 138 | # CONFIG_BF548 is not set |
| 124 | # CONFIG_BF549 is not set | 139 | # CONFIG_BF549 is not set |
| 125 | # CONFIG_BF561 is not set | 140 | # CONFIG_BF561 is not set |
| 141 | CONFIG_BF_REV_MIN=3 | ||
| 142 | CONFIG_BF_REV_MAX=6 | ||
| 126 | # CONFIG_BF_REV_0_0 is not set | 143 | # CONFIG_BF_REV_0_0 is not set |
| 127 | # CONFIG_BF_REV_0_1 is not set | 144 | # CONFIG_BF_REV_0_1 is not set |
| 128 | # CONFIG_BF_REV_0_2 is not set | 145 | # CONFIG_BF_REV_0_2 is not set |
| 129 | CONFIG_BF_REV_0_3=y | 146 | CONFIG_BF_REV_0_3=y |
| 130 | # CONFIG_BF_REV_0_4 is not set | 147 | # CONFIG_BF_REV_0_4 is not set |
| 131 | # CONFIG_BF_REV_0_5 is not set | 148 | # CONFIG_BF_REV_0_5 is not set |
| 149 | # CONFIG_BF_REV_0_6 is not set | ||
| 132 | # CONFIG_BF_REV_ANY is not set | 150 | # CONFIG_BF_REV_ANY is not set |
| 133 | # CONFIG_BF_REV_NONE is not set | 151 | # CONFIG_BF_REV_NONE is not set |
| 134 | CONFIG_BF53x=y | 152 | CONFIG_BF53x=y |
| 135 | CONFIG_MEM_MT48LC16M16A2TG_75=y | 153 | CONFIG_MEM_MT48LC16M16A2TG_75=y |
| 136 | CONFIG_BFIN533_EZKIT=y | 154 | CONFIG_BFIN533_EZKIT=y |
| 137 | # CONFIG_BFIN533_STAMP is not set | 155 | # CONFIG_BFIN533_STAMP is not set |
| 156 | # CONFIG_BLACKSTAMP is not set | ||
| 138 | # CONFIG_BFIN533_BLUETECHNIX_CM is not set | 157 | # CONFIG_BFIN533_BLUETECHNIX_CM is not set |
| 139 | # CONFIG_H8606_HVSISTEMAS is not set | 158 | # CONFIG_H8606_HVSISTEMAS is not set |
| 140 | # CONFIG_BFIN532_IP0X is not set | 159 | # CONFIG_BFIN532_IP0X is not set |
| @@ -187,7 +206,6 @@ CONFIG_BOOT_LOAD=0x1000 | |||
| 187 | # | 206 | # |
| 188 | CONFIG_CLKIN_HZ=27000000 | 207 | CONFIG_CLKIN_HZ=27000000 |
| 189 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 208 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 190 | CONFIG_MAX_MEM_SIZE=512 | ||
| 191 | CONFIG_MAX_VCO_HZ=750000000 | 209 | CONFIG_MAX_VCO_HZ=750000000 |
| 192 | CONFIG_MIN_VCO_HZ=50000000 | 210 | CONFIG_MIN_VCO_HZ=50000000 |
| 193 | CONFIG_MAX_SCLK_HZ=133333333 | 211 | CONFIG_MAX_SCLK_HZ=133333333 |
| @@ -201,6 +219,7 @@ CONFIG_HZ_250=y | |||
| 201 | # CONFIG_HZ_300 is not set | 219 | # CONFIG_HZ_300 is not set |
| 202 | # CONFIG_HZ_1000 is not set | 220 | # CONFIG_HZ_1000 is not set |
| 203 | CONFIG_HZ=250 | 221 | CONFIG_HZ=250 |
| 222 | CONFIG_SCHED_HRTICK=y | ||
| 204 | CONFIG_GENERIC_TIME=y | 223 | CONFIG_GENERIC_TIME=y |
| 205 | CONFIG_GENERIC_CLOCKEVENTS=y | 224 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 206 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 225 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| @@ -238,6 +257,12 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y | |||
| 238 | CONFIG_CACHELINE_ALIGNED_L1=y | 257 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 239 | # CONFIG_SYSCALL_TAB_L1 is not set | 258 | # CONFIG_SYSCALL_TAB_L1 is not set |
| 240 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | 259 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set |
| 260 | CONFIG_APP_STACK_L1=y | ||
| 261 | |||
| 262 | # | ||
| 263 | # Speed Optimizations | ||
| 264 | # | ||
| 265 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 241 | CONFIG_RAMKERNEL=y | 266 | CONFIG_RAMKERNEL=y |
| 242 | # CONFIG_ROMKERNEL is not set | 267 | # CONFIG_ROMKERNEL is not set |
| 243 | CONFIG_SELECT_MEMORY_MODEL=y | 268 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -246,14 +271,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 246 | # CONFIG_SPARSEMEM_MANUAL is not set | 271 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 247 | CONFIG_FLATMEM=y | 272 | CONFIG_FLATMEM=y |
| 248 | CONFIG_FLAT_NODE_MEM_MAP=y | 273 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 249 | # CONFIG_SPARSEMEM_STATIC is not set | 274 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 250 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 251 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 275 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 252 | # CONFIG_RESOURCES_64BIT is not set | 276 | # CONFIG_RESOURCES_64BIT is not set |
| 277 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 253 | CONFIG_ZONE_DMA_FLAG=1 | 278 | CONFIG_ZONE_DMA_FLAG=1 |
| 254 | CONFIG_VIRT_TO_BUS=y | 279 | CONFIG_VIRT_TO_BUS=y |
| 255 | # CONFIG_BFIN_GPTIMERS is not set | 280 | # CONFIG_BFIN_GPTIMERS is not set |
| 256 | CONFIG_BFIN_DMA_5XX=y | ||
| 257 | # CONFIG_DMA_UNCACHED_4M is not set | 281 | # CONFIG_DMA_UNCACHED_4M is not set |
| 258 | # CONFIG_DMA_UNCACHED_2M is not set | 282 | # CONFIG_DMA_UNCACHED_2M is not set |
| 259 | CONFIG_DMA_UNCACHED_1M=y | 283 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -268,7 +292,6 @@ CONFIG_BFIN_DCACHE=y | |||
| 268 | # CONFIG_BFIN_ICACHE_LOCK is not set | 292 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 269 | # CONFIG_BFIN_WB is not set | 293 | # CONFIG_BFIN_WB is not set |
| 270 | CONFIG_BFIN_WT=y | 294 | CONFIG_BFIN_WT=y |
| 271 | CONFIG_L1_MAX_PIECE=16 | ||
| 272 | # CONFIG_MPU is not set | 295 | # CONFIG_MPU is not set |
| 273 | 296 | ||
| 274 | # | 297 | # |
| @@ -297,7 +320,6 @@ CONFIG_BANK_3=0xAAC2 | |||
| 297 | # | 320 | # |
| 298 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 321 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 299 | # | 322 | # |
| 300 | # CONFIG_PCI is not set | ||
| 301 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 323 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 302 | # CONFIG_PCCARD is not set | 324 | # CONFIG_PCCARD is not set |
| 303 | 325 | ||
| @@ -308,29 +330,30 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 308 | CONFIG_BINFMT_FLAT=y | 330 | CONFIG_BINFMT_FLAT=y |
| 309 | CONFIG_BINFMT_ZFLAT=y | 331 | CONFIG_BINFMT_ZFLAT=y |
| 310 | # CONFIG_BINFMT_SHARED_FLAT is not set | 332 | # CONFIG_BINFMT_SHARED_FLAT is not set |
| 333 | # CONFIG_HAVE_AOUT is not set | ||
| 311 | # CONFIG_BINFMT_MISC is not set | 334 | # CONFIG_BINFMT_MISC is not set |
| 312 | 335 | ||
| 313 | # | 336 | # |
| 314 | # Power management options | 337 | # Power management options |
| 315 | # | 338 | # |
| 316 | CONFIG_PM=y | 339 | CONFIG_PM=y |
| 317 | # CONFIG_PM_LEGACY is not set | ||
| 318 | # CONFIG_PM_DEBUG is not set | 340 | # CONFIG_PM_DEBUG is not set |
| 319 | CONFIG_PM_SLEEP=y | 341 | CONFIG_PM_SLEEP=y |
| 320 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 321 | CONFIG_SUSPEND=y | 342 | CONFIG_SUSPEND=y |
| 343 | CONFIG_SUSPEND_FREEZER=y | ||
| 344 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 322 | CONFIG_PM_BFIN_SLEEP_DEEPER=y | 345 | CONFIG_PM_BFIN_SLEEP_DEEPER=y |
| 323 | # CONFIG_PM_BFIN_SLEEP is not set | 346 | # CONFIG_PM_BFIN_SLEEP is not set |
| 324 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | 347 | # CONFIG_PM_WAKEUP_BY_GPIO is not set |
| 325 | 348 | ||
| 326 | # | 349 | # |
| 327 | # CPU Frequency scaling | 350 | # Possible Suspend Mem / Hibernate Wake-Up Sources |
| 328 | # | 351 | # |
| 329 | # CONFIG_CPU_FREQ is not set | ||
| 330 | 352 | ||
| 331 | # | 353 | # |
| 332 | # Networking | 354 | # CPU Frequency scaling |
| 333 | # | 355 | # |
| 356 | # CONFIG_CPU_FREQ is not set | ||
| 334 | CONFIG_NET=y | 357 | CONFIG_NET=y |
| 335 | 358 | ||
| 336 | # | 359 | # |
| @@ -343,6 +366,7 @@ CONFIG_XFRM=y | |||
| 343 | # CONFIG_XFRM_USER is not set | 366 | # CONFIG_XFRM_USER is not set |
| 344 | # CONFIG_XFRM_SUB_POLICY is not set | 367 | # CONFIG_XFRM_SUB_POLICY is not set |
| 345 | # CONFIG_XFRM_MIGRATE is not set | 368 | # CONFIG_XFRM_MIGRATE is not set |
| 369 | # CONFIG_XFRM_STATISTICS is not set | ||
| 346 | # CONFIG_NET_KEY is not set | 370 | # CONFIG_NET_KEY is not set |
| 347 | CONFIG_INET=y | 371 | CONFIG_INET=y |
| 348 | # CONFIG_IP_MULTICAST is not set | 372 | # CONFIG_IP_MULTICAST is not set |
| @@ -372,8 +396,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 372 | CONFIG_DEFAULT_TCP_CONG="cubic" | 396 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 373 | # CONFIG_TCP_MD5SIG is not set | 397 | # CONFIG_TCP_MD5SIG is not set |
| 374 | # CONFIG_IPV6 is not set | 398 | # CONFIG_IPV6 is not set |
| 375 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 376 | # CONFIG_INET6_TUNNEL is not set | ||
| 377 | # CONFIG_NETLABEL is not set | 399 | # CONFIG_NETLABEL is not set |
| 378 | # CONFIG_NETWORK_SECMARK is not set | 400 | # CONFIG_NETWORK_SECMARK is not set |
| 379 | # CONFIG_NETFILTER is not set | 401 | # CONFIG_NETFILTER is not set |
| @@ -382,6 +404,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 382 | # CONFIG_TIPC is not set | 404 | # CONFIG_TIPC is not set |
| 383 | # CONFIG_ATM is not set | 405 | # CONFIG_ATM is not set |
| 384 | # CONFIG_BRIDGE is not set | 406 | # CONFIG_BRIDGE is not set |
| 407 | # CONFIG_NET_DSA is not set | ||
| 385 | # CONFIG_VLAN_8021Q is not set | 408 | # CONFIG_VLAN_8021Q is not set |
| 386 | # CONFIG_DECNET is not set | 409 | # CONFIG_DECNET is not set |
| 387 | # CONFIG_LLC2 is not set | 410 | # CONFIG_LLC2 is not set |
| @@ -398,6 +421,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 398 | # | 421 | # |
| 399 | # CONFIG_NET_PKTGEN is not set | 422 | # CONFIG_NET_PKTGEN is not set |
| 400 | # CONFIG_HAMRADIO is not set | 423 | # CONFIG_HAMRADIO is not set |
| 424 | # CONFIG_CAN is not set | ||
| 401 | CONFIG_IRDA=m | 425 | CONFIG_IRDA=m |
| 402 | 426 | ||
| 403 | # | 427 | # |
| @@ -430,24 +454,14 @@ CONFIG_IRTTY_SIR=m | |||
| 430 | # CONFIG_DONGLE is not set | 454 | # CONFIG_DONGLE is not set |
| 431 | 455 | ||
| 432 | # | 456 | # |
| 433 | # Old SIR device drivers | ||
| 434 | # | ||
| 435 | # CONFIG_IRPORT_SIR is not set | ||
| 436 | |||
| 437 | # | ||
| 438 | # Old Serial dongle support | ||
| 439 | # | ||
| 440 | |||
| 441 | # | ||
| 442 | # FIR device drivers | 457 | # FIR device drivers |
| 443 | # | 458 | # |
| 444 | # CONFIG_BT is not set | 459 | # CONFIG_BT is not set |
| 445 | # CONFIG_AF_RXRPC is not set | 460 | # CONFIG_AF_RXRPC is not set |
| 446 | 461 | # CONFIG_PHONET is not set | |
| 447 | # | 462 | CONFIG_WIRELESS=y |
| 448 | # Wireless | ||
| 449 | # | ||
| 450 | # CONFIG_CFG80211 is not set | 463 | # CONFIG_CFG80211 is not set |
| 464 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 451 | # CONFIG_WIRELESS_EXT is not set | 465 | # CONFIG_WIRELESS_EXT is not set |
| 452 | # CONFIG_MAC80211 is not set | 466 | # CONFIG_MAC80211 is not set |
| 453 | # CONFIG_IEEE80211 is not set | 467 | # CONFIG_IEEE80211 is not set |
| @@ -465,6 +479,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 465 | CONFIG_STANDALONE=y | 479 | CONFIG_STANDALONE=y |
| 466 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 480 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 467 | # CONFIG_FW_LOADER is not set | 481 | # CONFIG_FW_LOADER is not set |
| 482 | # CONFIG_DEBUG_DRIVER is not set | ||
| 483 | # CONFIG_DEBUG_DEVRES is not set | ||
| 468 | # CONFIG_SYS_HYPERVISOR is not set | 484 | # CONFIG_SYS_HYPERVISOR is not set |
| 469 | # CONFIG_CONNECTOR is not set | 485 | # CONFIG_CONNECTOR is not set |
| 470 | CONFIG_MTD=y | 486 | CONFIG_MTD=y |
| @@ -473,6 +489,7 @@ CONFIG_MTD=y | |||
| 473 | CONFIG_MTD_PARTITIONS=y | 489 | CONFIG_MTD_PARTITIONS=y |
| 474 | # CONFIG_MTD_REDBOOT_PARTS is not set | 490 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 475 | # CONFIG_MTD_CMDLINE_PARTS is not set | 491 | # CONFIG_MTD_CMDLINE_PARTS is not set |
| 492 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 476 | 493 | ||
| 477 | # | 494 | # |
| 478 | # User Modules And Translation Layers | 495 | # User Modules And Translation Layers |
| @@ -516,6 +533,7 @@ CONFIG_MTD_ROM=m | |||
| 516 | # | 533 | # |
| 517 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 534 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 518 | # CONFIG_MTD_PHYSMAP is not set | 535 | # CONFIG_MTD_PHYSMAP is not set |
| 536 | # CONFIG_MTD_GPIO_ADDR is not set | ||
| 519 | # CONFIG_MTD_UCLINUX is not set | 537 | # CONFIG_MTD_UCLINUX is not set |
| 520 | # CONFIG_MTD_PLATRAM is not set | 538 | # CONFIG_MTD_PLATRAM is not set |
| 521 | 539 | ||
| @@ -550,11 +568,14 @@ CONFIG_BLK_DEV=y | |||
| 550 | CONFIG_BLK_DEV_RAM=y | 568 | CONFIG_BLK_DEV_RAM=y |
| 551 | CONFIG_BLK_DEV_RAM_COUNT=16 | 569 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 552 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 570 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 553 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 571 | # CONFIG_BLK_DEV_XIP is not set |
| 554 | # CONFIG_CDROM_PKTCDVD is not set | 572 | # CONFIG_CDROM_PKTCDVD is not set |
| 555 | # CONFIG_ATA_OVER_ETH is not set | 573 | # CONFIG_ATA_OVER_ETH is not set |
| 574 | # CONFIG_BLK_DEV_HD is not set | ||
| 556 | CONFIG_MISC_DEVICES=y | 575 | CONFIG_MISC_DEVICES=y |
| 557 | # CONFIG_EEPROM_93CX6 is not set | 576 | # CONFIG_EEPROM_93CX6 is not set |
| 577 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 578 | CONFIG_HAVE_IDE=y | ||
| 558 | # CONFIG_IDE is not set | 579 | # CONFIG_IDE is not set |
| 559 | 580 | ||
| 560 | # | 581 | # |
| @@ -567,7 +588,6 @@ CONFIG_MISC_DEVICES=y | |||
| 567 | # CONFIG_ATA is not set | 588 | # CONFIG_ATA is not set |
| 568 | # CONFIG_MD is not set | 589 | # CONFIG_MD is not set |
| 569 | CONFIG_NETDEVICES=y | 590 | CONFIG_NETDEVICES=y |
| 570 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 571 | # CONFIG_DUMMY is not set | 591 | # CONFIG_DUMMY is not set |
| 572 | # CONFIG_BONDING is not set | 592 | # CONFIG_BONDING is not set |
| 573 | # CONFIG_MACVLAN is not set | 593 | # CONFIG_MACVLAN is not set |
| @@ -580,11 +600,14 @@ CONFIG_MII=y | |||
| 580 | CONFIG_SMC91X=y | 600 | CONFIG_SMC91X=y |
| 581 | # CONFIG_SMSC911X is not set | 601 | # CONFIG_SMSC911X is not set |
| 582 | # CONFIG_DM9000 is not set | 602 | # CONFIG_DM9000 is not set |
| 603 | # CONFIG_ENC28J60 is not set | ||
| 583 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 604 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 584 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 605 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 585 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 606 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 586 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 607 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 587 | # CONFIG_B44 is not set | 608 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set |
| 609 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 610 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 588 | CONFIG_NETDEV_1000=y | 611 | CONFIG_NETDEV_1000=y |
| 589 | # CONFIG_AX88180 is not set | 612 | # CONFIG_AX88180 is not set |
| 590 | CONFIG_NETDEV_10000=y | 613 | CONFIG_NETDEV_10000=y |
| @@ -594,10 +617,10 @@ CONFIG_NETDEV_10000=y | |||
| 594 | # | 617 | # |
| 595 | # CONFIG_WLAN_PRE80211 is not set | 618 | # CONFIG_WLAN_PRE80211 is not set |
| 596 | # CONFIG_WLAN_80211 is not set | 619 | # CONFIG_WLAN_80211 is not set |
| 620 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 597 | # CONFIG_WAN is not set | 621 | # CONFIG_WAN is not set |
| 598 | # CONFIG_PPP is not set | 622 | # CONFIG_PPP is not set |
| 599 | # CONFIG_SLIP is not set | 623 | # CONFIG_SLIP is not set |
| 600 | # CONFIG_SHAPER is not set | ||
| 601 | # CONFIG_NETCONSOLE is not set | 624 | # CONFIG_NETCONSOLE is not set |
| 602 | # CONFIG_NETPOLL is not set | 625 | # CONFIG_NETPOLL is not set |
| 603 | # CONFIG_NET_POLL_CONTROLLER is not set | 626 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -645,8 +668,11 @@ CONFIG_INPUT_EVDEV=m | |||
| 645 | # CONFIG_BF5xx_PPI is not set | 668 | # CONFIG_BF5xx_PPI is not set |
| 646 | CONFIG_BFIN_SPORT=y | 669 | CONFIG_BFIN_SPORT=y |
| 647 | # CONFIG_BFIN_TIMER_LATENCY is not set | 670 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 671 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 648 | CONFIG_SIMPLE_GPIO=m | 672 | CONFIG_SIMPLE_GPIO=m |
| 649 | # CONFIG_VT is not set | 673 | # CONFIG_VT is not set |
| 674 | # CONFIG_DEVKMEM is not set | ||
| 675 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 650 | # CONFIG_SERIAL_NONSTANDARD is not set | 676 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 651 | 677 | ||
| 652 | # | 678 | # |
| @@ -675,22 +701,19 @@ CONFIG_UNIX98_PTYS=y | |||
| 675 | # CONFIG_CAN4LINUX is not set | 701 | # CONFIG_CAN4LINUX is not set |
| 676 | # CONFIG_IPMI_HANDLER is not set | 702 | # CONFIG_IPMI_HANDLER is not set |
| 677 | # CONFIG_HW_RANDOM is not set | 703 | # CONFIG_HW_RANDOM is not set |
| 678 | # CONFIG_GEN_RTC is not set | ||
| 679 | # CONFIG_R3964 is not set | 704 | # CONFIG_R3964 is not set |
| 680 | # CONFIG_RAW_DRIVER is not set | 705 | # CONFIG_RAW_DRIVER is not set |
| 681 | # CONFIG_TCG_TPM is not set | 706 | # CONFIG_TCG_TPM is not set |
| 682 | # CONFIG_I2C is not set | 707 | # CONFIG_I2C is not set |
| 683 | |||
| 684 | # | ||
| 685 | # SPI support | ||
| 686 | # | ||
| 687 | CONFIG_SPI=y | 708 | CONFIG_SPI=y |
| 709 | # CONFIG_SPI_DEBUG is not set | ||
| 688 | CONFIG_SPI_MASTER=y | 710 | CONFIG_SPI_MASTER=y |
| 689 | 711 | ||
| 690 | # | 712 | # |
| 691 | # SPI Master Controller Drivers | 713 | # SPI Master Controller Drivers |
| 692 | # | 714 | # |
| 693 | CONFIG_SPI_BFIN=y | 715 | CONFIG_SPI_BFIN=y |
| 716 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 694 | # CONFIG_SPI_BITBANG is not set | 717 | # CONFIG_SPI_BITBANG is not set |
| 695 | 718 | ||
| 696 | # | 719 | # |
| @@ -699,14 +722,18 @@ CONFIG_SPI_BFIN=y | |||
| 699 | # CONFIG_SPI_AT25 is not set | 722 | # CONFIG_SPI_AT25 is not set |
| 700 | # CONFIG_SPI_SPIDEV is not set | 723 | # CONFIG_SPI_SPIDEV is not set |
| 701 | # CONFIG_SPI_TLE62X0 is not set | 724 | # CONFIG_SPI_TLE62X0 is not set |
| 725 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 726 | # CONFIG_GPIOLIB is not set | ||
| 702 | # CONFIG_W1 is not set | 727 | # CONFIG_W1 is not set |
| 703 | # CONFIG_POWER_SUPPLY is not set | 728 | # CONFIG_POWER_SUPPLY is not set |
| 704 | CONFIG_HWMON=y | 729 | CONFIG_HWMON=y |
| 705 | # CONFIG_HWMON_VID is not set | 730 | # CONFIG_HWMON_VID is not set |
| 731 | # CONFIG_SENSORS_ADCXX is not set | ||
| 706 | # CONFIG_SENSORS_F71805F is not set | 732 | # CONFIG_SENSORS_F71805F is not set |
| 707 | # CONFIG_SENSORS_F71882FG is not set | 733 | # CONFIG_SENSORS_F71882FG is not set |
| 708 | # CONFIG_SENSORS_IT87 is not set | 734 | # CONFIG_SENSORS_IT87 is not set |
| 709 | # CONFIG_SENSORS_LM70 is not set | 735 | # CONFIG_SENSORS_LM70 is not set |
| 736 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 710 | # CONFIG_SENSORS_PC87360 is not set | 737 | # CONFIG_SENSORS_PC87360 is not set |
| 711 | # CONFIG_SENSORS_PC87427 is not set | 738 | # CONFIG_SENSORS_PC87427 is not set |
| 712 | # CONFIG_SENSORS_SMSC47M1 is not set | 739 | # CONFIG_SENSORS_SMSC47M1 is not set |
| @@ -715,6 +742,8 @@ CONFIG_HWMON=y | |||
| 715 | # CONFIG_SENSORS_W83627HF is not set | 742 | # CONFIG_SENSORS_W83627HF is not set |
| 716 | # CONFIG_SENSORS_W83627EHF is not set | 743 | # CONFIG_SENSORS_W83627EHF is not set |
| 717 | # CONFIG_HWMON_DEBUG_CHIP is not set | 744 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 745 | # CONFIG_THERMAL is not set | ||
| 746 | # CONFIG_THERMAL_HWMON is not set | ||
| 718 | CONFIG_WATCHDOG=y | 747 | CONFIG_WATCHDOG=y |
| 719 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 748 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 720 | 749 | ||
| @@ -725,21 +754,28 @@ CONFIG_WATCHDOG=y | |||
| 725 | CONFIG_BFIN_WDT=y | 754 | CONFIG_BFIN_WDT=y |
| 726 | 755 | ||
| 727 | # | 756 | # |
| 728 | # Sonics Silicon Backplane | ||
| 729 | # | ||
| 730 | CONFIG_SSB_POSSIBLE=y | ||
| 731 | # CONFIG_SSB is not set | ||
| 732 | |||
| 733 | # | ||
| 734 | # Multifunction device drivers | 757 | # Multifunction device drivers |
| 735 | # | 758 | # |
| 759 | # CONFIG_MFD_CORE is not set | ||
| 736 | # CONFIG_MFD_SM501 is not set | 760 | # CONFIG_MFD_SM501 is not set |
| 761 | # CONFIG_HTC_PASIC3 is not set | ||
| 762 | # CONFIG_MFD_TMIO is not set | ||
| 763 | # CONFIG_MFD_WM8400 is not set | ||
| 737 | 764 | ||
| 738 | # | 765 | # |
| 739 | # Multimedia devices | 766 | # Multimedia devices |
| 740 | # | 767 | # |
| 768 | |||
| 769 | # | ||
| 770 | # Multimedia core support | ||
| 771 | # | ||
| 741 | # CONFIG_VIDEO_DEV is not set | 772 | # CONFIG_VIDEO_DEV is not set |
| 742 | # CONFIG_DVB_CORE is not set | 773 | # CONFIG_DVB_CORE is not set |
| 774 | # CONFIG_VIDEO_MEDIA is not set | ||
| 775 | |||
| 776 | # | ||
| 777 | # Multimedia drivers | ||
| 778 | # | ||
| 743 | # CONFIG_DAB is not set | 779 | # CONFIG_DAB is not set |
| 744 | 780 | ||
| 745 | # | 781 | # |
| @@ -754,18 +790,22 @@ CONFIG_SSB_POSSIBLE=y | |||
| 754 | # Display device support | 790 | # Display device support |
| 755 | # | 791 | # |
| 756 | # CONFIG_DISPLAY_SUPPORT is not set | 792 | # CONFIG_DISPLAY_SUPPORT is not set |
| 757 | |||
| 758 | # | ||
| 759 | # Sound | ||
| 760 | # | ||
| 761 | # CONFIG_SOUND is not set | 793 | # CONFIG_SOUND is not set |
| 762 | CONFIG_HID_SUPPORT=y | 794 | CONFIG_HID_SUPPORT=y |
| 763 | CONFIG_HID=m | 795 | CONFIG_HID=m |
| 764 | # CONFIG_HID_DEBUG is not set | 796 | # CONFIG_HID_DEBUG is not set |
| 765 | # CONFIG_HIDRAW is not set | 797 | # CONFIG_HIDRAW is not set |
| 798 | # CONFIG_HID_PID is not set | ||
| 799 | |||
| 800 | # | ||
| 801 | # Special HID drivers | ||
| 802 | # | ||
| 803 | CONFIG_HID_COMPAT=y | ||
| 766 | # CONFIG_USB_SUPPORT is not set | 804 | # CONFIG_USB_SUPPORT is not set |
| 767 | # CONFIG_MMC is not set | 805 | # CONFIG_MMC is not set |
| 806 | # CONFIG_MEMSTICK is not set | ||
| 768 | # CONFIG_NEW_LEDS is not set | 807 | # CONFIG_NEW_LEDS is not set |
| 808 | # CONFIG_ACCESSIBILITY is not set | ||
| 769 | CONFIG_RTC_LIB=y | 809 | CONFIG_RTC_LIB=y |
| 770 | CONFIG_RTC_CLASS=y | 810 | CONFIG_RTC_CLASS=y |
| 771 | CONFIG_RTC_HCTOSYS=y | 811 | CONFIG_RTC_HCTOSYS=y |
| @@ -784,47 +824,51 @@ CONFIG_RTC_INTF_DEV=y | |||
| 784 | # | 824 | # |
| 785 | # SPI RTC drivers | 825 | # SPI RTC drivers |
| 786 | # | 826 | # |
| 787 | # CONFIG_RTC_DRV_RS5C348 is not set | 827 | # CONFIG_RTC_DRV_M41T94 is not set |
| 828 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 788 | # CONFIG_RTC_DRV_MAX6902 is not set | 829 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 830 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 831 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 832 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 789 | 833 | ||
| 790 | # | 834 | # |
| 791 | # Platform RTC drivers | 835 | # Platform RTC drivers |
| 792 | # | 836 | # |
| 837 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 838 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 793 | # CONFIG_RTC_DRV_DS1553 is not set | 839 | # CONFIG_RTC_DRV_DS1553 is not set |
| 794 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 795 | # CONFIG_RTC_DRV_DS1742 is not set | 840 | # CONFIG_RTC_DRV_DS1742 is not set |
| 841 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 796 | # CONFIG_RTC_DRV_M48T86 is not set | 842 | # CONFIG_RTC_DRV_M48T86 is not set |
| 843 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 797 | # CONFIG_RTC_DRV_M48T59 is not set | 844 | # CONFIG_RTC_DRV_M48T59 is not set |
| 845 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 798 | # CONFIG_RTC_DRV_V3020 is not set | 846 | # CONFIG_RTC_DRV_V3020 is not set |
| 799 | 847 | ||
| 800 | # | 848 | # |
| 801 | # on-CPU RTC drivers | 849 | # on-CPU RTC drivers |
| 802 | # | 850 | # |
| 803 | CONFIG_RTC_DRV_BFIN=y | 851 | CONFIG_RTC_DRV_BFIN=y |
| 804 | 852 | # CONFIG_DMADEVICES is not set | |
| 805 | # | ||
| 806 | # Userspace I/O | ||
| 807 | # | ||
| 808 | # CONFIG_UIO is not set | 853 | # CONFIG_UIO is not set |
| 854 | # CONFIG_STAGING is not set | ||
| 809 | 855 | ||
| 810 | # | 856 | # |
| 811 | # File systems | 857 | # File systems |
| 812 | # | 858 | # |
| 813 | # CONFIG_EXT2_FS is not set | 859 | # CONFIG_EXT2_FS is not set |
| 814 | # CONFIG_EXT3_FS is not set | 860 | # CONFIG_EXT3_FS is not set |
| 815 | # CONFIG_EXT4DEV_FS is not set | 861 | # CONFIG_EXT4_FS is not set |
| 816 | # CONFIG_REISERFS_FS is not set | 862 | # CONFIG_REISERFS_FS is not set |
| 817 | # CONFIG_JFS_FS is not set | 863 | # CONFIG_JFS_FS is not set |
| 818 | # CONFIG_FS_POSIX_ACL is not set | 864 | # CONFIG_FS_POSIX_ACL is not set |
| 865 | CONFIG_FILE_LOCKING=y | ||
| 819 | # CONFIG_XFS_FS is not set | 866 | # CONFIG_XFS_FS is not set |
| 820 | # CONFIG_GFS2_FS is not set | ||
| 821 | # CONFIG_OCFS2_FS is not set | 867 | # CONFIG_OCFS2_FS is not set |
| 822 | # CONFIG_MINIX_FS is not set | 868 | # CONFIG_DNOTIFY is not set |
| 823 | # CONFIG_ROMFS_FS is not set | ||
| 824 | CONFIG_INOTIFY=y | 869 | CONFIG_INOTIFY=y |
| 825 | CONFIG_INOTIFY_USER=y | 870 | CONFIG_INOTIFY_USER=y |
| 826 | # CONFIG_QUOTA is not set | 871 | # CONFIG_QUOTA is not set |
| 827 | # CONFIG_DNOTIFY is not set | ||
| 828 | # CONFIG_AUTOFS_FS is not set | 872 | # CONFIG_AUTOFS_FS is not set |
| 829 | # CONFIG_AUTOFS4_FS is not set | 873 | # CONFIG_AUTOFS4_FS is not set |
| 830 | # CONFIG_FUSE_FS is not set | 874 | # CONFIG_FUSE_FS is not set |
| @@ -864,11 +908,11 @@ CONFIG_SYSFS=y | |||
| 864 | # CONFIG_EFS_FS is not set | 908 | # CONFIG_EFS_FS is not set |
| 865 | CONFIG_YAFFS_FS=m | 909 | CONFIG_YAFFS_FS=m |
| 866 | CONFIG_YAFFS_YAFFS1=y | 910 | CONFIG_YAFFS_YAFFS1=y |
| 911 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 867 | # CONFIG_YAFFS_DOES_ECC is not set | 912 | # CONFIG_YAFFS_DOES_ECC is not set |
| 868 | CONFIG_YAFFS_YAFFS2=y | 913 | CONFIG_YAFFS_YAFFS2=y |
| 869 | CONFIG_YAFFS_AUTO_YAFFS2=y | 914 | CONFIG_YAFFS_AUTO_YAFFS2=y |
| 870 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | 915 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set |
| 871 | CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 | ||
| 872 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | 916 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 873 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | 917 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 874 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | 918 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| @@ -885,8 +929,11 @@ CONFIG_JFFS2_RTIME=y | |||
| 885 | # CONFIG_JFFS2_RUBIN is not set | 929 | # CONFIG_JFFS2_RUBIN is not set |
| 886 | # CONFIG_CRAMFS is not set | 930 | # CONFIG_CRAMFS is not set |
| 887 | # CONFIG_VXFS_FS is not set | 931 | # CONFIG_VXFS_FS is not set |
| 932 | # CONFIG_MINIX_FS is not set | ||
| 933 | # CONFIG_OMFS_FS is not set | ||
| 888 | # CONFIG_HPFS_FS is not set | 934 | # CONFIG_HPFS_FS is not set |
| 889 | # CONFIG_QNX4FS_FS is not set | 935 | # CONFIG_QNX4FS_FS is not set |
| 936 | # CONFIG_ROMFS_FS is not set | ||
| 890 | # CONFIG_SYSV_FS is not set | 937 | # CONFIG_SYSV_FS is not set |
| 891 | # CONFIG_UFS_FS is not set | 938 | # CONFIG_UFS_FS is not set |
| 892 | CONFIG_NETWORK_FILESYSTEMS=y | 939 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -894,13 +941,12 @@ CONFIG_NFS_FS=m | |||
| 894 | CONFIG_NFS_V3=y | 941 | CONFIG_NFS_V3=y |
| 895 | # CONFIG_NFS_V3_ACL is not set | 942 | # CONFIG_NFS_V3_ACL is not set |
| 896 | # CONFIG_NFS_V4 is not set | 943 | # CONFIG_NFS_V4 is not set |
| 897 | # CONFIG_NFS_DIRECTIO is not set | ||
| 898 | # CONFIG_NFSD is not set | 944 | # CONFIG_NFSD is not set |
| 899 | CONFIG_LOCKD=m | 945 | CONFIG_LOCKD=m |
| 900 | CONFIG_LOCKD_V4=y | 946 | CONFIG_LOCKD_V4=y |
| 901 | CONFIG_NFS_COMMON=y | 947 | CONFIG_NFS_COMMON=y |
| 902 | CONFIG_SUNRPC=m | 948 | CONFIG_SUNRPC=m |
| 903 | # CONFIG_SUNRPC_BIND34 is not set | 949 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 904 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 950 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 905 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 951 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 906 | CONFIG_SMB_FS=m | 952 | CONFIG_SMB_FS=m |
| @@ -956,9 +1002,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 956 | # CONFIG_NLS_KOI8_U is not set | 1002 | # CONFIG_NLS_KOI8_U is not set |
| 957 | # CONFIG_NLS_UTF8 is not set | 1003 | # CONFIG_NLS_UTF8 is not set |
| 958 | # CONFIG_DLM is not set | 1004 | # CONFIG_DLM is not set |
| 959 | CONFIG_INSTRUMENTATION=y | ||
| 960 | # CONFIG_PROFILING is not set | ||
| 961 | # CONFIG_MARKERS is not set | ||
| 962 | 1005 | ||
| 963 | # | 1006 | # |
| 964 | # Kernel hacking | 1007 | # Kernel hacking |
| @@ -966,14 +1009,53 @@ CONFIG_INSTRUMENTATION=y | |||
| 966 | # CONFIG_PRINTK_TIME is not set | 1009 | # CONFIG_PRINTK_TIME is not set |
| 967 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1010 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 968 | CONFIG_ENABLE_MUST_CHECK=y | 1011 | CONFIG_ENABLE_MUST_CHECK=y |
| 1012 | CONFIG_FRAME_WARN=1024 | ||
| 969 | # CONFIG_MAGIC_SYSRQ is not set | 1013 | # CONFIG_MAGIC_SYSRQ is not set |
| 970 | # CONFIG_UNUSED_SYMBOLS is not set | 1014 | # CONFIG_UNUSED_SYMBOLS is not set |
| 971 | CONFIG_DEBUG_FS=y | 1015 | CONFIG_DEBUG_FS=y |
| 972 | # CONFIG_HEADERS_CHECK is not set | 1016 | # CONFIG_HEADERS_CHECK is not set |
| 973 | # CONFIG_DEBUG_KERNEL is not set | 1017 | CONFIG_DEBUG_KERNEL=y |
| 1018 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1019 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1020 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1021 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1022 | CONFIG_SCHED_DEBUG=y | ||
| 1023 | # CONFIG_SCHEDSTATS is not set | ||
| 1024 | # CONFIG_TIMER_STATS is not set | ||
| 1025 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1026 | # CONFIG_DEBUG_SLAB is not set | ||
| 1027 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1028 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1029 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1030 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1031 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1032 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1033 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 974 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1034 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1035 | CONFIG_DEBUG_INFO=y | ||
| 1036 | # CONFIG_DEBUG_VM is not set | ||
| 1037 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1038 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1039 | # CONFIG_DEBUG_LIST is not set | ||
| 1040 | # CONFIG_DEBUG_SG is not set | ||
| 1041 | # CONFIG_FRAME_POINTER is not set | ||
| 1042 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1043 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1044 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1045 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1046 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1047 | # CONFIG_FAULT_INJECTION is not set | ||
| 1048 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1049 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 975 | # CONFIG_SAMPLES is not set | 1050 | # CONFIG_SAMPLES is not set |
| 1051 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1052 | # CONFIG_KGDB is not set | ||
| 1053 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1054 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1055 | CONFIG_DEBUG_VERBOSE=y | ||
| 976 | CONFIG_DEBUG_MMRS=y | 1056 | CONFIG_DEBUG_MMRS=y |
| 1057 | # CONFIG_DEBUG_HWERR is not set | ||
| 1058 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 977 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1059 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 978 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1060 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 979 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1061 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -991,9 +1073,94 @@ CONFIG_ACCESS_CHECK=y | |||
| 991 | # | 1073 | # |
| 992 | # CONFIG_KEYS is not set | 1074 | # CONFIG_KEYS is not set |
| 993 | CONFIG_SECURITY=y | 1075 | CONFIG_SECURITY=y |
| 1076 | # CONFIG_SECURITYFS is not set | ||
| 994 | # CONFIG_SECURITY_NETWORK is not set | 1077 | # CONFIG_SECURITY_NETWORK is not set |
| 995 | # CONFIG_SECURITY_CAPABILITIES is not set | 1078 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 996 | # CONFIG_CRYPTO is not set | 1079 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 |
| 1080 | CONFIG_CRYPTO=y | ||
| 1081 | |||
| 1082 | # | ||
| 1083 | # Crypto core or helper | ||
| 1084 | # | ||
| 1085 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1086 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1087 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1088 | # CONFIG_CRYPTO_NULL is not set | ||
| 1089 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1090 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1091 | # CONFIG_CRYPTO_TEST is not set | ||
| 1092 | |||
| 1093 | # | ||
| 1094 | # Authenticated Encryption with Associated Data | ||
| 1095 | # | ||
| 1096 | # CONFIG_CRYPTO_CCM is not set | ||
| 1097 | # CONFIG_CRYPTO_GCM is not set | ||
| 1098 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1099 | |||
| 1100 | # | ||
| 1101 | # Block modes | ||
| 1102 | # | ||
| 1103 | # CONFIG_CRYPTO_CBC is not set | ||
| 1104 | # CONFIG_CRYPTO_CTR is not set | ||
| 1105 | # CONFIG_CRYPTO_CTS is not set | ||
| 1106 | # CONFIG_CRYPTO_ECB is not set | ||
| 1107 | # CONFIG_CRYPTO_LRW is not set | ||
| 1108 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1109 | # CONFIG_CRYPTO_XTS is not set | ||
| 1110 | |||
| 1111 | # | ||
| 1112 | # Hash modes | ||
| 1113 | # | ||
| 1114 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1115 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1116 | |||
| 1117 | # | ||
| 1118 | # Digest | ||
| 1119 | # | ||
| 1120 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1121 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1122 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1123 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1124 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1125 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1126 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1127 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1128 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1129 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1130 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1131 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1132 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1133 | |||
| 1134 | # | ||
| 1135 | # Ciphers | ||
| 1136 | # | ||
| 1137 | # CONFIG_CRYPTO_AES is not set | ||
| 1138 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1139 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1140 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1141 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1142 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1143 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1144 | # CONFIG_CRYPTO_DES is not set | ||
| 1145 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1146 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1147 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1148 | # CONFIG_CRYPTO_SEED is not set | ||
| 1149 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1150 | # CONFIG_CRYPTO_TEA is not set | ||
| 1151 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1152 | |||
| 1153 | # | ||
| 1154 | # Compression | ||
| 1155 | # | ||
| 1156 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1157 | # CONFIG_CRYPTO_LZO is not set | ||
| 1158 | |||
| 1159 | # | ||
| 1160 | # Random Number Generation | ||
| 1161 | # | ||
| 1162 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1163 | CONFIG_CRYPTO_HW=y | ||
| 997 | 1164 | ||
| 998 | # | 1165 | # |
| 999 | # Library routines | 1166 | # Library routines |
| @@ -1001,6 +1168,7 @@ CONFIG_SECURITY=y | |||
| 1001 | CONFIG_BITREVERSE=y | 1168 | CONFIG_BITREVERSE=y |
| 1002 | CONFIG_CRC_CCITT=m | 1169 | CONFIG_CRC_CCITT=m |
| 1003 | # CONFIG_CRC16 is not set | 1170 | # CONFIG_CRC16 is not set |
| 1171 | # CONFIG_CRC_T10DIF is not set | ||
| 1004 | # CONFIG_CRC_ITU_T is not set | 1172 | # CONFIG_CRC_ITU_T is not set |
| 1005 | CONFIG_CRC32=y | 1173 | CONFIG_CRC32=y |
| 1006 | # CONFIG_CRC7 is not set | 1174 | # CONFIG_CRC7 is not set |
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index c23267ed880b..49eabb41e9e5 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24.7 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # | 4 | # |
| 5 | # CONFIG_MMU is not set | 5 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 6 | # CONFIG_FPU is not set |
| @@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 9 | CONFIG_BLACKFIN=y | 9 | CONFIG_BLACKFIN=y |
| 10 | CONFIG_ZONE_DMA=y | 10 | CONFIG_ZONE_DMA=y |
| 11 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 11 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 13 | CONFIG_GENERIC_HWEIGHT=y | 12 | CONFIG_GENERIC_HWEIGHT=y |
| 14 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| @@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 31 | # CONFIG_POSIX_MQUEUE is not set | 30 | # CONFIG_POSIX_MQUEUE is not set |
| 32 | # CONFIG_BSD_PROCESS_ACCT is not set | 31 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 33 | # CONFIG_TASKSTATS is not set | 32 | # CONFIG_TASKSTATS is not set |
| 34 | # CONFIG_USER_NS is not set | ||
| 35 | # CONFIG_PID_NS is not set | ||
| 36 | # CONFIG_AUDIT is not set | 33 | # CONFIG_AUDIT is not set |
| 37 | CONFIG_IKCONFIG=y | 34 | CONFIG_IKCONFIG=y |
| 38 | CONFIG_IKCONFIG_PROC=y | 35 | CONFIG_IKCONFIG_PROC=y |
| 39 | CONFIG_LOG_BUF_SHIFT=14 | 36 | CONFIG_LOG_BUF_SHIFT=14 |
| 40 | # CONFIG_CGROUPS is not set | 37 | # CONFIG_CGROUPS is not set |
| 41 | CONFIG_FAIR_GROUP_SCHED=y | 38 | # CONFIG_GROUP_SCHED is not set |
| 42 | CONFIG_FAIR_USER_SCHED=y | 39 | # CONFIG_SYSFS_DEPRECATED is not set |
| 43 | # CONFIG_FAIR_CGROUP_SCHED is not set | 40 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 44 | CONFIG_SYSFS_DEPRECATED=y | ||
| 45 | # CONFIG_RELAY is not set | 41 | # CONFIG_RELAY is not set |
| 42 | # CONFIG_NAMESPACES is not set | ||
| 46 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 47 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y | |||
| 51 | CONFIG_UID16=y | 48 | CONFIG_UID16=y |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 49 | CONFIG_SYSCTL_SYSCALL=y |
| 53 | CONFIG_KALLSYMS=y | 50 | CONFIG_KALLSYMS=y |
| 51 | # CONFIG_KALLSYMS_ALL is not set | ||
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | CONFIG_HOTPLUG=y | 53 | CONFIG_HOTPLUG=y |
| 56 | CONFIG_PRINTK=y | 54 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 55 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 56 | # CONFIG_ELF_CORE is not set |
| 57 | CONFIG_COMPAT_BRK=y | ||
| 59 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 59 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 60 | CONFIG_ANON_INODES=y |
| 62 | CONFIG_EPOLL=y | 61 | CONFIG_EPOLL=y |
| 63 | CONFIG_SIGNALFD=y | 62 | CONFIG_SIGNALFD=y |
| 63 | CONFIG_TIMERFD=y | ||
| 64 | CONFIG_EVENTFD=y | 64 | CONFIG_EVENTFD=y |
| 65 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 66 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| 70 | # CONFIG_PROFILING is not set | ||
| 71 | # CONFIG_MARKERS is not set | ||
| 72 | CONFIG_HAVE_OPROFILE=y | ||
| 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 69 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 70 | CONFIG_RT_MUTEXES=y | 75 | CONFIG_RT_MUTEXES=y |
| 71 | CONFIG_TINY_SHMEM=y | 76 | CONFIG_TINY_SHMEM=y |
| 72 | CONFIG_BASE_SMALL=0 | 77 | CONFIG_BASE_SMALL=0 |
| 73 | CONFIG_MODULES=y | 78 | CONFIG_MODULES=y |
| 79 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 74 | CONFIG_MODULE_UNLOAD=y | 80 | CONFIG_MODULE_UNLOAD=y |
| 75 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 81 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 76 | # CONFIG_MODVERSIONS is not set | 82 | # CONFIG_MODVERSIONS is not set |
| @@ -81,6 +87,7 @@ CONFIG_BLOCK=y | |||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | 87 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 82 | # CONFIG_LSF is not set | 88 | # CONFIG_LSF is not set |
| 83 | # CONFIG_BLK_DEV_BSG is not set | 89 | # CONFIG_BLK_DEV_BSG is not set |
| 90 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 84 | 91 | ||
| 85 | # | 92 | # |
| 86 | # IO Schedulers | 93 | # IO Schedulers |
| @@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y | |||
| 94 | # CONFIG_DEFAULT_CFQ is not set | 101 | # CONFIG_DEFAULT_CFQ is not set |
| 95 | # CONFIG_DEFAULT_NOOP is not set | 102 | # CONFIG_DEFAULT_NOOP is not set |
| 96 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 103 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 104 | CONFIG_CLASSIC_RCU=y | ||
| 97 | # CONFIG_PREEMPT_NONE is not set | 105 | # CONFIG_PREEMPT_NONE is not set |
| 98 | CONFIG_PREEMPT_VOLUNTARY=y | 106 | CONFIG_PREEMPT_VOLUNTARY=y |
| 99 | # CONFIG_PREEMPT is not set | 107 | # CONFIG_PREEMPT is not set |
| 108 | CONFIG_FREEZER=y | ||
| 100 | 109 | ||
| 101 | # | 110 | # |
| 102 | # Blackfin Processor Options | 111 | # Blackfin Processor Options |
| @@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 105 | # | 114 | # |
| 106 | # Processor and Board Settings | 115 | # Processor and Board Settings |
| 107 | # | 116 | # |
| 117 | # CONFIG_BF512 is not set | ||
| 118 | # CONFIG_BF514 is not set | ||
| 119 | # CONFIG_BF516 is not set | ||
| 120 | # CONFIG_BF518 is not set | ||
| 108 | # CONFIG_BF522 is not set | 121 | # CONFIG_BF522 is not set |
| 109 | # CONFIG_BF523 is not set | 122 | # CONFIG_BF523 is not set |
| 110 | # CONFIG_BF524 is not set | 123 | # CONFIG_BF524 is not set |
| @@ -117,24 +130,30 @@ CONFIG_BF533=y | |||
| 117 | # CONFIG_BF534 is not set | 130 | # CONFIG_BF534 is not set |
| 118 | # CONFIG_BF536 is not set | 131 | # CONFIG_BF536 is not set |
| 119 | # CONFIG_BF537 is not set | 132 | # CONFIG_BF537 is not set |
| 133 | # CONFIG_BF538 is not set | ||
| 134 | # CONFIG_BF539 is not set | ||
| 120 | # CONFIG_BF542 is not set | 135 | # CONFIG_BF542 is not set |
| 121 | # CONFIG_BF544 is not set | 136 | # CONFIG_BF544 is not set |
| 122 | # CONFIG_BF547 is not set | 137 | # CONFIG_BF547 is not set |
| 123 | # CONFIG_BF548 is not set | 138 | # CONFIG_BF548 is not set |
| 124 | # CONFIG_BF549 is not set | 139 | # CONFIG_BF549 is not set |
| 125 | # CONFIG_BF561 is not set | 140 | # CONFIG_BF561 is not set |
| 141 | CONFIG_BF_REV_MIN=3 | ||
| 142 | CONFIG_BF_REV_MAX=6 | ||
| 126 | # CONFIG_BF_REV_0_0 is not set | 143 | # CONFIG_BF_REV_0_0 is not set |
| 127 | # CONFIG_BF_REV_0_1 is not set | 144 | # CONFIG_BF_REV_0_1 is not set |
| 128 | # CONFIG_BF_REV_0_2 is not set | 145 | # CONFIG_BF_REV_0_2 is not set |
| 129 | CONFIG_BF_REV_0_3=y | 146 | CONFIG_BF_REV_0_3=y |
| 130 | # CONFIG_BF_REV_0_4 is not set | 147 | # CONFIG_BF_REV_0_4 is not set |
| 131 | # CONFIG_BF_REV_0_5 is not set | 148 | # CONFIG_BF_REV_0_5 is not set |
| 149 | # CONFIG_BF_REV_0_6 is not set | ||
| 132 | # CONFIG_BF_REV_ANY is not set | 150 | # CONFIG_BF_REV_ANY is not set |
| 133 | # CONFIG_BF_REV_NONE is not set | 151 | # CONFIG_BF_REV_NONE is not set |
| 134 | CONFIG_BF53x=y | 152 | CONFIG_BF53x=y |
| 135 | CONFIG_MEM_MT48LC64M4A2FB_7E=y | 153 | CONFIG_MEM_MT48LC64M4A2FB_7E=y |
| 136 | # CONFIG_BFIN533_EZKIT is not set | 154 | # CONFIG_BFIN533_EZKIT is not set |
| 137 | CONFIG_BFIN533_STAMP=y | 155 | CONFIG_BFIN533_STAMP=y |
| 156 | # CONFIG_BLACKSTAMP is not set | ||
| 138 | # CONFIG_BFIN533_BLUETECHNIX_CM is not set | 157 | # CONFIG_BFIN533_BLUETECHNIX_CM is not set |
| 139 | # CONFIG_H8606_HVSISTEMAS is not set | 158 | # CONFIG_H8606_HVSISTEMAS is not set |
| 140 | # CONFIG_BFIN532_IP0X is not set | 159 | # CONFIG_BFIN532_IP0X is not set |
| @@ -187,7 +206,6 @@ CONFIG_BOOT_LOAD=0x1000 | |||
| 187 | # | 206 | # |
| 188 | CONFIG_CLKIN_HZ=11059200 | 207 | CONFIG_CLKIN_HZ=11059200 |
| 189 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 208 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 190 | CONFIG_MAX_MEM_SIZE=512 | ||
| 191 | CONFIG_MAX_VCO_HZ=750000000 | 209 | CONFIG_MAX_VCO_HZ=750000000 |
| 192 | CONFIG_MIN_VCO_HZ=50000000 | 210 | CONFIG_MIN_VCO_HZ=50000000 |
| 193 | CONFIG_MAX_SCLK_HZ=133333333 | 211 | CONFIG_MAX_SCLK_HZ=133333333 |
| @@ -201,6 +219,7 @@ CONFIG_HZ_250=y | |||
| 201 | # CONFIG_HZ_300 is not set | 219 | # CONFIG_HZ_300 is not set |
| 202 | # CONFIG_HZ_1000 is not set | 220 | # CONFIG_HZ_1000 is not set |
| 203 | CONFIG_HZ=250 | 221 | CONFIG_HZ=250 |
| 222 | CONFIG_SCHED_HRTICK=y | ||
| 204 | CONFIG_GENERIC_TIME=y | 223 | CONFIG_GENERIC_TIME=y |
| 205 | CONFIG_GENERIC_CLOCKEVENTS=y | 224 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 206 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 225 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| @@ -238,6 +257,12 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y | |||
| 238 | CONFIG_CACHELINE_ALIGNED_L1=y | 257 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 239 | # CONFIG_SYSCALL_TAB_L1 is not set | 258 | # CONFIG_SYSCALL_TAB_L1 is not set |
| 240 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | 259 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set |
| 260 | CONFIG_APP_STACK_L1=y | ||
| 261 | |||
| 262 | # | ||
| 263 | # Speed Optimizations | ||
| 264 | # | ||
| 265 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 241 | CONFIG_RAMKERNEL=y | 266 | CONFIG_RAMKERNEL=y |
| 242 | # CONFIG_ROMKERNEL is not set | 267 | # CONFIG_ROMKERNEL is not set |
| 243 | CONFIG_SELECT_MEMORY_MODEL=y | 268 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -246,14 +271,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 246 | # CONFIG_SPARSEMEM_MANUAL is not set | 271 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 247 | CONFIG_FLATMEM=y | 272 | CONFIG_FLATMEM=y |
| 248 | CONFIG_FLAT_NODE_MEM_MAP=y | 273 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 249 | # CONFIG_SPARSEMEM_STATIC is not set | 274 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 250 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 251 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 275 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 252 | # CONFIG_RESOURCES_64BIT is not set | 276 | # CONFIG_RESOURCES_64BIT is not set |
| 277 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 253 | CONFIG_ZONE_DMA_FLAG=1 | 278 | CONFIG_ZONE_DMA_FLAG=1 |
| 254 | CONFIG_VIRT_TO_BUS=y | 279 | CONFIG_VIRT_TO_BUS=y |
| 255 | # CONFIG_BFIN_GPTIMERS is not set | 280 | # CONFIG_BFIN_GPTIMERS is not set |
| 256 | CONFIG_BFIN_DMA_5XX=y | ||
| 257 | # CONFIG_DMA_UNCACHED_4M is not set | 281 | # CONFIG_DMA_UNCACHED_4M is not set |
| 258 | # CONFIG_DMA_UNCACHED_2M is not set | 282 | # CONFIG_DMA_UNCACHED_2M is not set |
| 259 | CONFIG_DMA_UNCACHED_1M=y | 283 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -268,7 +292,6 @@ CONFIG_BFIN_DCACHE=y | |||
| 268 | # CONFIG_BFIN_ICACHE_LOCK is not set | 292 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 269 | # CONFIG_BFIN_WB is not set | 293 | # CONFIG_BFIN_WB is not set |
| 270 | CONFIG_BFIN_WT=y | 294 | CONFIG_BFIN_WT=y |
| 271 | CONFIG_L1_MAX_PIECE=16 | ||
| 272 | # CONFIG_MPU is not set | 295 | # CONFIG_MPU is not set |
| 273 | 296 | ||
| 274 | # | 297 | # |
| @@ -297,7 +320,6 @@ CONFIG_BANK_3=0xAAC2 | |||
| 297 | # | 320 | # |
| 298 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 321 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 299 | # | 322 | # |
| 300 | # CONFIG_PCI is not set | ||
| 301 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 323 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 302 | # CONFIG_PCCARD is not set | 324 | # CONFIG_PCCARD is not set |
| 303 | 325 | ||
| @@ -308,29 +330,30 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 308 | CONFIG_BINFMT_FLAT=y | 330 | CONFIG_BINFMT_FLAT=y |
| 309 | CONFIG_BINFMT_ZFLAT=y | 331 | CONFIG_BINFMT_ZFLAT=y |
| 310 | # CONFIG_BINFMT_SHARED_FLAT is not set | 332 | # CONFIG_BINFMT_SHARED_FLAT is not set |
| 333 | # CONFIG_HAVE_AOUT is not set | ||
| 311 | # CONFIG_BINFMT_MISC is not set | 334 | # CONFIG_BINFMT_MISC is not set |
| 312 | 335 | ||
| 313 | # | 336 | # |
| 314 | # Power management options | 337 | # Power management options |
| 315 | # | 338 | # |
| 316 | CONFIG_PM=y | 339 | CONFIG_PM=y |
| 317 | # CONFIG_PM_LEGACY is not set | ||
| 318 | # CONFIG_PM_DEBUG is not set | 340 | # CONFIG_PM_DEBUG is not set |
| 319 | CONFIG_PM_SLEEP=y | 341 | CONFIG_PM_SLEEP=y |
| 320 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 321 | CONFIG_SUSPEND=y | 342 | CONFIG_SUSPEND=y |
| 343 | CONFIG_SUSPEND_FREEZER=y | ||
| 344 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 322 | CONFIG_PM_BFIN_SLEEP_DEEPER=y | 345 | CONFIG_PM_BFIN_SLEEP_DEEPER=y |
| 323 | # CONFIG_PM_BFIN_SLEEP is not set | 346 | # CONFIG_PM_BFIN_SLEEP is not set |
| 324 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | 347 | # CONFIG_PM_WAKEUP_BY_GPIO is not set |
| 325 | 348 | ||
| 326 | # | 349 | # |
| 327 | # CPU Frequency scaling | 350 | # Possible Suspend Mem / Hibernate Wake-Up Sources |
| 328 | # | 351 | # |
| 329 | # CONFIG_CPU_FREQ is not set | ||
| 330 | 352 | ||
| 331 | # | 353 | # |
| 332 | # Networking | 354 | # CPU Frequency scaling |
| 333 | # | 355 | # |
| 356 | # CONFIG_CPU_FREQ is not set | ||
| 334 | CONFIG_NET=y | 357 | CONFIG_NET=y |
| 335 | 358 | ||
| 336 | # | 359 | # |
| @@ -343,6 +366,7 @@ CONFIG_XFRM=y | |||
| 343 | # CONFIG_XFRM_USER is not set | 366 | # CONFIG_XFRM_USER is not set |
| 344 | # CONFIG_XFRM_SUB_POLICY is not set | 367 | # CONFIG_XFRM_SUB_POLICY is not set |
| 345 | # CONFIG_XFRM_MIGRATE is not set | 368 | # CONFIG_XFRM_MIGRATE is not set |
| 369 | # CONFIG_XFRM_STATISTICS is not set | ||
| 346 | # CONFIG_NET_KEY is not set | 370 | # CONFIG_NET_KEY is not set |
| 347 | CONFIG_INET=y | 371 | CONFIG_INET=y |
| 348 | # CONFIG_IP_MULTICAST is not set | 372 | # CONFIG_IP_MULTICAST is not set |
| @@ -372,8 +396,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 372 | CONFIG_DEFAULT_TCP_CONG="cubic" | 396 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 373 | # CONFIG_TCP_MD5SIG is not set | 397 | # CONFIG_TCP_MD5SIG is not set |
| 374 | # CONFIG_IPV6 is not set | 398 | # CONFIG_IPV6 is not set |
| 375 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 376 | # CONFIG_INET6_TUNNEL is not set | ||
| 377 | # CONFIG_NETLABEL is not set | 399 | # CONFIG_NETLABEL is not set |
| 378 | # CONFIG_NETWORK_SECMARK is not set | 400 | # CONFIG_NETWORK_SECMARK is not set |
| 379 | # CONFIG_NETFILTER is not set | 401 | # CONFIG_NETFILTER is not set |
| @@ -382,6 +404,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 382 | # CONFIG_TIPC is not set | 404 | # CONFIG_TIPC is not set |
| 383 | # CONFIG_ATM is not set | 405 | # CONFIG_ATM is not set |
| 384 | # CONFIG_BRIDGE is not set | 406 | # CONFIG_BRIDGE is not set |
| 407 | # CONFIG_NET_DSA is not set | ||
| 385 | # CONFIG_VLAN_8021Q is not set | 408 | # CONFIG_VLAN_8021Q is not set |
| 386 | # CONFIG_DECNET is not set | 409 | # CONFIG_DECNET is not set |
| 387 | # CONFIG_LLC2 is not set | 410 | # CONFIG_LLC2 is not set |
| @@ -398,6 +421,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 398 | # | 421 | # |
| 399 | # CONFIG_NET_PKTGEN is not set | 422 | # CONFIG_NET_PKTGEN is not set |
| 400 | # CONFIG_HAMRADIO is not set | 423 | # CONFIG_HAMRADIO is not set |
| 424 | # CONFIG_CAN is not set | ||
| 401 | CONFIG_IRDA=m | 425 | CONFIG_IRDA=m |
| 402 | 426 | ||
| 403 | # | 427 | # |
| @@ -432,24 +456,14 @@ CONFIG_SIR_BFIN_DMA=y | |||
| 432 | # CONFIG_DONGLE is not set | 456 | # CONFIG_DONGLE is not set |
| 433 | 457 | ||
| 434 | # | 458 | # |
| 435 | # Old SIR device drivers | ||
| 436 | # | ||
| 437 | # CONFIG_IRPORT_SIR is not set | ||
| 438 | |||
| 439 | # | ||
| 440 | # Old Serial dongle support | ||
| 441 | # | ||
| 442 | |||
| 443 | # | ||
| 444 | # FIR device drivers | 459 | # FIR device drivers |
| 445 | # | 460 | # |
| 446 | # CONFIG_BT is not set | 461 | # CONFIG_BT is not set |
| 447 | # CONFIG_AF_RXRPC is not set | 462 | # CONFIG_AF_RXRPC is not set |
| 448 | 463 | # CONFIG_PHONET is not set | |
| 449 | # | 464 | CONFIG_WIRELESS=y |
| 450 | # Wireless | ||
| 451 | # | ||
| 452 | # CONFIG_CFG80211 is not set | 465 | # CONFIG_CFG80211 is not set |
| 466 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 453 | # CONFIG_WIRELESS_EXT is not set | 467 | # CONFIG_WIRELESS_EXT is not set |
| 454 | # CONFIG_MAC80211 is not set | 468 | # CONFIG_MAC80211 is not set |
| 455 | # CONFIG_IEEE80211 is not set | 469 | # CONFIG_IEEE80211 is not set |
| @@ -467,6 +481,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 467 | CONFIG_STANDALONE=y | 481 | CONFIG_STANDALONE=y |
| 468 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 482 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 469 | # CONFIG_FW_LOADER is not set | 483 | # CONFIG_FW_LOADER is not set |
| 484 | # CONFIG_DEBUG_DRIVER is not set | ||
| 485 | # CONFIG_DEBUG_DEVRES is not set | ||
| 470 | # CONFIG_SYS_HYPERVISOR is not set | 486 | # CONFIG_SYS_HYPERVISOR is not set |
| 471 | # CONFIG_CONNECTOR is not set | 487 | # CONFIG_CONNECTOR is not set |
| 472 | CONFIG_MTD=y | 488 | CONFIG_MTD=y |
| @@ -475,6 +491,7 @@ CONFIG_MTD=y | |||
| 475 | CONFIG_MTD_PARTITIONS=y | 491 | CONFIG_MTD_PARTITIONS=y |
| 476 | # CONFIG_MTD_REDBOOT_PARTS is not set | 492 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 477 | CONFIG_MTD_CMDLINE_PARTS=y | 493 | CONFIG_MTD_CMDLINE_PARTS=y |
| 494 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 478 | 495 | ||
| 479 | # | 496 | # |
| 480 | # User Modules And Translation Layers | 497 | # User Modules And Translation Layers |
| @@ -520,6 +537,7 @@ CONFIG_MTD_ROM=m | |||
| 520 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 537 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 521 | # CONFIG_MTD_PHYSMAP is not set | 538 | # CONFIG_MTD_PHYSMAP is not set |
| 522 | CONFIG_MTD_BFIN_ASYNC=m | 539 | CONFIG_MTD_BFIN_ASYNC=m |
| 540 | # CONFIG_MTD_GPIO_ADDR is not set | ||
| 523 | # CONFIG_MTD_UCLINUX is not set | 541 | # CONFIG_MTD_UCLINUX is not set |
| 524 | # CONFIG_MTD_PLATRAM is not set | 542 | # CONFIG_MTD_PLATRAM is not set |
| 525 | 543 | ||
| @@ -554,11 +572,14 @@ CONFIG_BLK_DEV=y | |||
| 554 | CONFIG_BLK_DEV_RAM=y | 572 | CONFIG_BLK_DEV_RAM=y |
| 555 | CONFIG_BLK_DEV_RAM_COUNT=16 | 573 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 556 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 574 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 557 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 575 | # CONFIG_BLK_DEV_XIP is not set |
| 558 | # CONFIG_CDROM_PKTCDVD is not set | 576 | # CONFIG_CDROM_PKTCDVD is not set |
| 559 | # CONFIG_ATA_OVER_ETH is not set | 577 | # CONFIG_ATA_OVER_ETH is not set |
| 578 | # CONFIG_BLK_DEV_HD is not set | ||
| 560 | CONFIG_MISC_DEVICES=y | 579 | CONFIG_MISC_DEVICES=y |
| 561 | # CONFIG_EEPROM_93CX6 is not set | 580 | # CONFIG_EEPROM_93CX6 is not set |
| 581 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 582 | CONFIG_HAVE_IDE=y | ||
| 562 | # CONFIG_IDE is not set | 583 | # CONFIG_IDE is not set |
| 563 | 584 | ||
| 564 | # | 585 | # |
| @@ -571,7 +592,6 @@ CONFIG_MISC_DEVICES=y | |||
| 571 | # CONFIG_ATA is not set | 592 | # CONFIG_ATA is not set |
| 572 | # CONFIG_MD is not set | 593 | # CONFIG_MD is not set |
| 573 | CONFIG_NETDEVICES=y | 594 | CONFIG_NETDEVICES=y |
| 574 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 575 | # CONFIG_DUMMY is not set | 595 | # CONFIG_DUMMY is not set |
| 576 | # CONFIG_BONDING is not set | 596 | # CONFIG_BONDING is not set |
| 577 | # CONFIG_MACVLAN is not set | 597 | # CONFIG_MACVLAN is not set |
| @@ -584,11 +604,14 @@ CONFIG_MII=y | |||
| 584 | CONFIG_SMC91X=y | 604 | CONFIG_SMC91X=y |
| 585 | # CONFIG_SMSC911X is not set | 605 | # CONFIG_SMSC911X is not set |
| 586 | # CONFIG_DM9000 is not set | 606 | # CONFIG_DM9000 is not set |
| 607 | # CONFIG_ENC28J60 is not set | ||
| 587 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 608 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 588 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 609 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 589 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 610 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 590 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 611 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 591 | # CONFIG_B44 is not set | 612 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set |
| 613 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 614 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 592 | CONFIG_NETDEV_1000=y | 615 | CONFIG_NETDEV_1000=y |
| 593 | # CONFIG_AX88180 is not set | 616 | # CONFIG_AX88180 is not set |
| 594 | CONFIG_NETDEV_10000=y | 617 | CONFIG_NETDEV_10000=y |
| @@ -598,10 +621,10 @@ CONFIG_NETDEV_10000=y | |||
| 598 | # | 621 | # |
| 599 | # CONFIG_WLAN_PRE80211 is not set | 622 | # CONFIG_WLAN_PRE80211 is not set |
| 600 | # CONFIG_WLAN_80211 is not set | 623 | # CONFIG_WLAN_80211 is not set |
| 624 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 601 | # CONFIG_WAN is not set | 625 | # CONFIG_WAN is not set |
| 602 | # CONFIG_PPP is not set | 626 | # CONFIG_PPP is not set |
| 603 | # CONFIG_SLIP is not set | 627 | # CONFIG_SLIP is not set |
| 604 | # CONFIG_SHAPER is not set | ||
| 605 | # CONFIG_NETCONSOLE is not set | 628 | # CONFIG_NETCONSOLE is not set |
| 606 | # CONFIG_NETPOLL is not set | 629 | # CONFIG_NETPOLL is not set |
| 607 | # CONFIG_NET_POLL_CONTROLLER is not set | 630 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -633,7 +656,7 @@ CONFIG_INPUT_EVDEV=m | |||
| 633 | # CONFIG_INPUT_TOUCHSCREEN is not set | 656 | # CONFIG_INPUT_TOUCHSCREEN is not set |
| 634 | CONFIG_INPUT_MISC=y | 657 | CONFIG_INPUT_MISC=y |
| 635 | # CONFIG_INPUT_UINPUT is not set | 658 | # CONFIG_INPUT_UINPUT is not set |
| 636 | CONFIG_TWI_KEYPAD=m | 659 | CONFIG_CONFIG_INPUT_PCF8574=m |
| 637 | 660 | ||
| 638 | # | 661 | # |
| 639 | # Hardware I/O ports | 662 | # Hardware I/O ports |
| @@ -652,8 +675,11 @@ CONFIG_TWI_KEYPAD=m | |||
| 652 | CONFIG_BFIN_SPORT=y | 675 | CONFIG_BFIN_SPORT=y |
| 653 | # CONFIG_BFIN_TIMER_LATENCY is not set | 676 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 654 | CONFIG_TWI_LCD=m | 677 | CONFIG_TWI_LCD=m |
| 678 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 655 | CONFIG_SIMPLE_GPIO=m | 679 | CONFIG_SIMPLE_GPIO=m |
| 656 | # CONFIG_VT is not set | 680 | # CONFIG_VT is not set |
| 681 | # CONFIG_DEVKMEM is not set | ||
| 682 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 657 | # CONFIG_SERIAL_NONSTANDARD is not set | 683 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 658 | 684 | ||
| 659 | # | 685 | # |
| @@ -682,41 +708,46 @@ CONFIG_UNIX98_PTYS=y | |||
| 682 | # CONFIG_CAN4LINUX is not set | 708 | # CONFIG_CAN4LINUX is not set |
| 683 | # CONFIG_IPMI_HANDLER is not set | 709 | # CONFIG_IPMI_HANDLER is not set |
| 684 | # CONFIG_HW_RANDOM is not set | 710 | # CONFIG_HW_RANDOM is not set |
| 685 | # CONFIG_GEN_RTC is not set | ||
| 686 | # CONFIG_R3964 is not set | 711 | # CONFIG_R3964 is not set |
| 687 | # CONFIG_RAW_DRIVER is not set | 712 | # CONFIG_RAW_DRIVER is not set |
| 688 | # CONFIG_TCG_TPM is not set | 713 | # CONFIG_TCG_TPM is not set |
| 689 | CONFIG_I2C=m | 714 | CONFIG_I2C=m |
| 690 | CONFIG_I2C_BOARDINFO=y | 715 | CONFIG_I2C_BOARDINFO=y |
| 691 | CONFIG_I2C_CHARDEV=m | 716 | CONFIG_I2C_CHARDEV=m |
| 717 | CONFIG_I2C_HELPER_AUTO=y | ||
| 692 | 718 | ||
| 693 | # | 719 | # |
| 694 | # I2C Algorithms | 720 | # I2C Hardware Bus support |
| 695 | # | 721 | # |
| 696 | CONFIG_I2C_ALGOBIT=m | ||
| 697 | # CONFIG_I2C_ALGOPCF is not set | ||
| 698 | # CONFIG_I2C_ALGOPCA is not set | ||
| 699 | 722 | ||
| 700 | # | 723 | # |
| 701 | # I2C Hardware Bus support | 724 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 702 | # | 725 | # |
| 703 | # CONFIG_I2C_GPIO is not set | 726 | # CONFIG_I2C_GPIO is not set |
| 704 | # CONFIG_I2C_OCORES is not set | 727 | # CONFIG_I2C_OCORES is not set |
| 705 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 706 | # CONFIG_I2C_SIMTEC is not set | 728 | # CONFIG_I2C_SIMTEC is not set |
| 729 | |||
| 730 | # | ||
| 731 | # External I2C/SMBus adapter drivers | ||
| 732 | # | ||
| 733 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 707 | # CONFIG_I2C_TAOS_EVM is not set | 734 | # CONFIG_I2C_TAOS_EVM is not set |
| 735 | |||
| 736 | # | ||
| 737 | # Other I2C/SMBus bus drivers | ||
| 738 | # | ||
| 739 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 708 | # CONFIG_I2C_STUB is not set | 740 | # CONFIG_I2C_STUB is not set |
| 709 | 741 | ||
| 710 | # | 742 | # |
| 711 | # Miscellaneous I2C Chip support | 743 | # Miscellaneous I2C Chip support |
| 712 | # | 744 | # |
| 713 | # CONFIG_SENSORS_DS1337 is not set | ||
| 714 | # CONFIG_SENSORS_DS1374 is not set | ||
| 715 | # CONFIG_DS1682 is not set | 745 | # CONFIG_DS1682 is not set |
| 746 | # CONFIG_AT24 is not set | ||
| 716 | # CONFIG_SENSORS_AD5252 is not set | 747 | # CONFIG_SENSORS_AD5252 is not set |
| 717 | # CONFIG_SENSORS_EEPROM is not set | 748 | # CONFIG_SENSORS_EEPROM is not set |
| 718 | # CONFIG_SENSORS_PCF8574 is not set | 749 | # CONFIG_SENSORS_PCF8574 is not set |
| 719 | # CONFIG_SENSORS_PCF8575 is not set | 750 | # CONFIG_PCF8575 is not set |
| 720 | # CONFIG_SENSORS_PCA9539 is not set | 751 | # CONFIG_SENSORS_PCA9539 is not set |
| 721 | # CONFIG_SENSORS_PCF8591 is not set | 752 | # CONFIG_SENSORS_PCF8591 is not set |
| 722 | # CONFIG_SENSORS_MAX6875 is not set | 753 | # CONFIG_SENSORS_MAX6875 is not set |
| @@ -725,17 +756,15 @@ CONFIG_I2C_ALGOBIT=m | |||
| 725 | # CONFIG_I2C_DEBUG_ALGO is not set | 756 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 726 | # CONFIG_I2C_DEBUG_BUS is not set | 757 | # CONFIG_I2C_DEBUG_BUS is not set |
| 727 | # CONFIG_I2C_DEBUG_CHIP is not set | 758 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 728 | |||
| 729 | # | ||
| 730 | # SPI support | ||
| 731 | # | ||
| 732 | CONFIG_SPI=y | 759 | CONFIG_SPI=y |
| 760 | # CONFIG_SPI_DEBUG is not set | ||
| 733 | CONFIG_SPI_MASTER=y | 761 | CONFIG_SPI_MASTER=y |
| 734 | 762 | ||
| 735 | # | 763 | # |
| 736 | # SPI Master Controller Drivers | 764 | # SPI Master Controller Drivers |
| 737 | # | 765 | # |
| 738 | CONFIG_SPI_BFIN=y | 766 | CONFIG_SPI_BFIN=y |
| 767 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 739 | # CONFIG_SPI_BITBANG is not set | 768 | # CONFIG_SPI_BITBANG is not set |
| 740 | 769 | ||
| 741 | # | 770 | # |
| @@ -744,11 +773,15 @@ CONFIG_SPI_BFIN=y | |||
| 744 | # CONFIG_SPI_AT25 is not set | 773 | # CONFIG_SPI_AT25 is not set |
| 745 | # CONFIG_SPI_SPIDEV is not set | 774 | # CONFIG_SPI_SPIDEV is not set |
| 746 | # CONFIG_SPI_TLE62X0 is not set | 775 | # CONFIG_SPI_TLE62X0 is not set |
| 776 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 777 | # CONFIG_GPIOLIB is not set | ||
| 747 | # CONFIG_W1 is not set | 778 | # CONFIG_W1 is not set |
| 748 | # CONFIG_POWER_SUPPLY is not set | 779 | # CONFIG_POWER_SUPPLY is not set |
| 749 | CONFIG_HWMON=y | 780 | CONFIG_HWMON=y |
| 750 | # CONFIG_HWMON_VID is not set | 781 | # CONFIG_HWMON_VID is not set |
| 782 | # CONFIG_SENSORS_AD7414 is not set | ||
| 751 | # CONFIG_SENSORS_AD7418 is not set | 783 | # CONFIG_SENSORS_AD7418 is not set |
| 784 | # CONFIG_SENSORS_ADCXX is not set | ||
| 752 | # CONFIG_SENSORS_ADM1021 is not set | 785 | # CONFIG_SENSORS_ADM1021 is not set |
| 753 | # CONFIG_SENSORS_ADM1025 is not set | 786 | # CONFIG_SENSORS_ADM1025 is not set |
| 754 | # CONFIG_SENSORS_ADM1026 is not set | 787 | # CONFIG_SENSORS_ADM1026 is not set |
| @@ -756,6 +789,7 @@ CONFIG_HWMON=y | |||
| 756 | # CONFIG_SENSORS_ADM1031 is not set | 789 | # CONFIG_SENSORS_ADM1031 is not set |
| 757 | # CONFIG_SENSORS_ADM9240 is not set | 790 | # CONFIG_SENSORS_ADM9240 is not set |
| 758 | # CONFIG_SENSORS_ADT7470 is not set | 791 | # CONFIG_SENSORS_ADT7470 is not set |
| 792 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 759 | # CONFIG_SENSORS_ATXP1 is not set | 793 | # CONFIG_SENSORS_ATXP1 is not set |
| 760 | # CONFIG_SENSORS_DS1621 is not set | 794 | # CONFIG_SENSORS_DS1621 is not set |
| 761 | # CONFIG_SENSORS_F71805F is not set | 795 | # CONFIG_SENSORS_F71805F is not set |
| @@ -776,6 +810,7 @@ CONFIG_HWMON=y | |||
| 776 | # CONFIG_SENSORS_LM90 is not set | 810 | # CONFIG_SENSORS_LM90 is not set |
| 777 | # CONFIG_SENSORS_LM92 is not set | 811 | # CONFIG_SENSORS_LM92 is not set |
| 778 | # CONFIG_SENSORS_LM93 is not set | 812 | # CONFIG_SENSORS_LM93 is not set |
| 813 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 779 | # CONFIG_SENSORS_MAX1619 is not set | 814 | # CONFIG_SENSORS_MAX1619 is not set |
| 780 | # CONFIG_SENSORS_MAX6650 is not set | 815 | # CONFIG_SENSORS_MAX6650 is not set |
| 781 | # CONFIG_SENSORS_PC87360 is not set | 816 | # CONFIG_SENSORS_PC87360 is not set |
| @@ -784,6 +819,7 @@ CONFIG_HWMON=y | |||
| 784 | # CONFIG_SENSORS_SMSC47M1 is not set | 819 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 785 | # CONFIG_SENSORS_SMSC47M192 is not set | 820 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 786 | # CONFIG_SENSORS_SMSC47B397 is not set | 821 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 822 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 787 | # CONFIG_SENSORS_THMC50 is not set | 823 | # CONFIG_SENSORS_THMC50 is not set |
| 788 | # CONFIG_SENSORS_VT1211 is not set | 824 | # CONFIG_SENSORS_VT1211 is not set |
| 789 | # CONFIG_SENSORS_W83781D is not set | 825 | # CONFIG_SENSORS_W83781D is not set |
| @@ -791,9 +827,12 @@ CONFIG_HWMON=y | |||
| 791 | # CONFIG_SENSORS_W83792D is not set | 827 | # CONFIG_SENSORS_W83792D is not set |
| 792 | # CONFIG_SENSORS_W83793 is not set | 828 | # CONFIG_SENSORS_W83793 is not set |
| 793 | # CONFIG_SENSORS_W83L785TS is not set | 829 | # CONFIG_SENSORS_W83L785TS is not set |
| 830 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 794 | # CONFIG_SENSORS_W83627HF is not set | 831 | # CONFIG_SENSORS_W83627HF is not set |
| 795 | # CONFIG_SENSORS_W83627EHF is not set | 832 | # CONFIG_SENSORS_W83627EHF is not set |
| 796 | # CONFIG_HWMON_DEBUG_CHIP is not set | 833 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 834 | # CONFIG_THERMAL is not set | ||
| 835 | # CONFIG_THERMAL_HWMON is not set | ||
| 797 | CONFIG_WATCHDOG=y | 836 | CONFIG_WATCHDOG=y |
| 798 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 837 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 799 | 838 | ||
| @@ -804,21 +843,29 @@ CONFIG_WATCHDOG=y | |||
| 804 | CONFIG_BFIN_WDT=y | 843 | CONFIG_BFIN_WDT=y |
| 805 | 844 | ||
| 806 | # | 845 | # |
| 807 | # Sonics Silicon Backplane | ||
| 808 | # | ||
| 809 | CONFIG_SSB_POSSIBLE=y | ||
| 810 | # CONFIG_SSB is not set | ||
| 811 | |||
| 812 | # | ||
| 813 | # Multifunction device drivers | 846 | # Multifunction device drivers |
| 814 | # | 847 | # |
| 848 | # CONFIG_MFD_CORE is not set | ||
| 815 | # CONFIG_MFD_SM501 is not set | 849 | # CONFIG_MFD_SM501 is not set |
| 850 | # CONFIG_HTC_PASIC3 is not set | ||
| 851 | # CONFIG_MFD_TMIO is not set | ||
| 852 | # CONFIG_MFD_WM8400 is not set | ||
| 853 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 816 | 854 | ||
| 817 | # | 855 | # |
| 818 | # Multimedia devices | 856 | # Multimedia devices |
| 819 | # | 857 | # |
| 858 | |||
| 859 | # | ||
| 860 | # Multimedia core support | ||
| 861 | # | ||
| 820 | # CONFIG_VIDEO_DEV is not set | 862 | # CONFIG_VIDEO_DEV is not set |
| 821 | # CONFIG_DVB_CORE is not set | 863 | # CONFIG_DVB_CORE is not set |
| 864 | # CONFIG_VIDEO_MEDIA is not set | ||
| 865 | |||
| 866 | # | ||
| 867 | # Multimedia drivers | ||
| 868 | # | ||
| 822 | # CONFIG_DAB is not set | 869 | # CONFIG_DAB is not set |
| 823 | 870 | ||
| 824 | # | 871 | # |
| @@ -829,6 +876,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 829 | CONFIG_FB=m | 876 | CONFIG_FB=m |
| 830 | CONFIG_FIRMWARE_EDID=y | 877 | CONFIG_FIRMWARE_EDID=y |
| 831 | # CONFIG_FB_DDC is not set | 878 | # CONFIG_FB_DDC is not set |
| 879 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 832 | CONFIG_FB_CFB_FILLRECT=m | 880 | CONFIG_FB_CFB_FILLRECT=m |
| 833 | CONFIG_FB_CFB_COPYAREA=m | 881 | CONFIG_FB_CFB_COPYAREA=m |
| 834 | CONFIG_FB_CFB_IMAGEBLIT=m | 882 | CONFIG_FB_CFB_IMAGEBLIT=m |
| @@ -836,8 +884,8 @@ CONFIG_FB_CFB_IMAGEBLIT=m | |||
| 836 | # CONFIG_FB_SYS_FILLRECT is not set | 884 | # CONFIG_FB_SYS_FILLRECT is not set |
| 837 | # CONFIG_FB_SYS_COPYAREA is not set | 885 | # CONFIG_FB_SYS_COPYAREA is not set |
| 838 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 886 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 887 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 839 | # CONFIG_FB_SYS_FOPS is not set | 888 | # CONFIG_FB_SYS_FOPS is not set |
| 840 | CONFIG_FB_DEFERRED_IO=y | ||
| 841 | # CONFIG_FB_SVGALIB is not set | 889 | # CONFIG_FB_SVGALIB is not set |
| 842 | # CONFIG_FB_MACMODES is not set | 890 | # CONFIG_FB_MACMODES is not set |
| 843 | # CONFIG_FB_BACKLIGHT is not set | 891 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -848,6 +896,7 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 848 | # Frame buffer hardware drivers | 896 | # Frame buffer hardware drivers |
| 849 | # | 897 | # |
| 850 | # CONFIG_FB_BFIN_T350MCQB is not set | 898 | # CONFIG_FB_BFIN_T350MCQB is not set |
| 899 | # CONFIG_FB_BFIN_LQ035Q1 is not set | ||
| 851 | CONFIG_FB_BFIN_7393=m | 900 | CONFIG_FB_BFIN_7393=m |
| 852 | CONFIG_NTSC=y | 901 | CONFIG_NTSC=y |
| 853 | # CONFIG_PAL is not set | 902 | # CONFIG_PAL is not set |
| @@ -859,6 +908,7 @@ CONFIG_ADV7393_1XMEM=y | |||
| 859 | # CONFIG_ADV7393_2XMEM is not set | 908 | # CONFIG_ADV7393_2XMEM is not set |
| 860 | # CONFIG_FB_S1D13XXX is not set | 909 | # CONFIG_FB_S1D13XXX is not set |
| 861 | # CONFIG_FB_VIRTUAL is not set | 910 | # CONFIG_FB_VIRTUAL is not set |
| 911 | # CONFIG_FB_METRONOME is not set | ||
| 862 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 912 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set |
| 863 | 913 | ||
| 864 | # | 914 | # |
| @@ -866,15 +916,8 @@ CONFIG_ADV7393_1XMEM=y | |||
| 866 | # | 916 | # |
| 867 | # CONFIG_DISPLAY_SUPPORT is not set | 917 | # CONFIG_DISPLAY_SUPPORT is not set |
| 868 | # CONFIG_LOGO is not set | 918 | # CONFIG_LOGO is not set |
| 869 | |||
| 870 | # | ||
| 871 | # Sound | ||
| 872 | # | ||
| 873 | CONFIG_SOUND=m | 919 | CONFIG_SOUND=m |
| 874 | 920 | CONFIG_SOUND_OSS_CORE=y | |
| 875 | # | ||
| 876 | # Advanced Linux Sound Architecture | ||
| 877 | # | ||
| 878 | CONFIG_SND=m | 921 | CONFIG_SND=m |
| 879 | CONFIG_SND_TIMER=m | 922 | CONFIG_SND_TIMER=m |
| 880 | CONFIG_SND_PCM=m | 923 | CONFIG_SND_PCM=m |
| @@ -888,18 +931,12 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 888 | CONFIG_SND_VERBOSE_PROCFS=y | 931 | CONFIG_SND_VERBOSE_PROCFS=y |
| 889 | # CONFIG_SND_VERBOSE_PRINTK is not set | 932 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 890 | # CONFIG_SND_DEBUG is not set | 933 | # CONFIG_SND_DEBUG is not set |
| 891 | 934 | CONFIG_SND_DRIVERS=y | |
| 892 | # | ||
| 893 | # Generic devices | ||
| 894 | # | ||
| 895 | # CONFIG_SND_DUMMY is not set | 935 | # CONFIG_SND_DUMMY is not set |
| 896 | # CONFIG_SND_MTPAV is not set | 936 | # CONFIG_SND_MTPAV is not set |
| 897 | # CONFIG_SND_SERIAL_U16550 is not set | 937 | # CONFIG_SND_SERIAL_U16550 is not set |
| 898 | # CONFIG_SND_MPU401 is not set | 938 | # CONFIG_SND_MPU401 is not set |
| 899 | 939 | CONFIG_SND_SPI=y | |
| 900 | # | ||
| 901 | # SPI devices | ||
| 902 | # | ||
| 903 | 940 | ||
| 904 | # | 941 | # |
| 905 | # ALSA Blackfin devices | 942 | # ALSA Blackfin devices |
| @@ -911,46 +948,46 @@ CONFIG_SND_BLACKFIN_AD1836_MULSUB=y | |||
| 911 | # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set | 948 | # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set |
| 912 | CONFIG_SND_BLACKFIN_SPORT=0 | 949 | CONFIG_SND_BLACKFIN_SPORT=0 |
| 913 | CONFIG_SND_BLACKFIN_SPI_PFBIT=4 | 950 | CONFIG_SND_BLACKFIN_SPI_PFBIT=4 |
| 914 | CONFIG_SND_BFIN_AD73311=m | ||
| 915 | CONFIG_SND_BFIN_SPORT=0 | 951 | CONFIG_SND_BFIN_SPORT=0 |
| 916 | CONFIG_SND_BFIN_AD73311_SE=4 | ||
| 917 | CONFIG_SND_BFIN_AD73322=m | 952 | CONFIG_SND_BFIN_AD73322=m |
| 918 | CONFIG_SND_BFIN_AD73322_SPORT0_SE=10 | 953 | CONFIG_SND_BFIN_AD73322_SPORT0_SE=10 |
| 919 | CONFIG_SND_BFIN_AD73322_SPORT1_SE=14 | 954 | CONFIG_SND_BFIN_AD73322_SPORT1_SE=14 |
| 920 | CONFIG_SND_BFIN_AD73322_RESET=12 | 955 | CONFIG_SND_BFIN_AD73322_RESET=12 |
| 921 | |||
| 922 | # | ||
| 923 | # System on Chip audio support | ||
| 924 | # | ||
| 925 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 926 | CONFIG_SND_SOC=m | 956 | CONFIG_SND_SOC=m |
| 927 | CONFIG_SND_BF5XX_SOC=m | 957 | CONFIG_SND_SOC_AC97_BUS=y |
| 928 | CONFIG_SND_MMAP_SUPPORT=y | 958 | CONFIG_SND_BF5XX_I2S=m |
| 929 | CONFIG_SND_BF5XX_SOC_AC97=m | ||
| 930 | # CONFIG_SND_BF5XX_SOC_WM8750 is not set | ||
| 931 | # CONFIG_SND_BF5XX_SOC_WM8731 is not set | ||
| 932 | # CONFIG_SND_BF5XX_SOC_SSM2602 is not set | 959 | # CONFIG_SND_BF5XX_SOC_SSM2602 is not set |
| 933 | CONFIG_SND_BF5XX_SOC_BF5xx=m | 960 | CONFIG_SND_BF5XX_SOC_AD73311=m |
| 961 | CONFIG_SND_BFIN_AD73311_SE=4 | ||
| 962 | CONFIG_SND_BF5XX_AC97=m | ||
| 963 | CONFIG_SND_BF5XX_MMAP_SUPPORT=y | ||
| 964 | # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set | ||
| 965 | CONFIG_SND_BF5XX_SOC_SPORT=m | ||
| 966 | CONFIG_SND_BF5XX_SOC_I2S=m | ||
| 967 | CONFIG_SND_BF5XX_SOC_AC97=m | ||
| 968 | CONFIG_SND_BF5XX_SOC_AD1980=m | ||
| 934 | CONFIG_SND_BF5XX_SPORT_NUM=0 | 969 | CONFIG_SND_BF5XX_SPORT_NUM=0 |
| 935 | # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set | 970 | # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set |
| 936 | 971 | # CONFIG_SND_SOC_ALL_CODECS is not set | |
| 937 | # | ||
| 938 | # SoC Audio support for SuperH | ||
| 939 | # | ||
| 940 | CONFIG_SND_SOC_AD1980=m | 972 | CONFIG_SND_SOC_AD1980=m |
| 941 | 973 | CONFIG_SND_SOC_AD73311=m | |
| 942 | # | ||
| 943 | # Open Sound System | ||
| 944 | # | ||
| 945 | # CONFIG_SOUND_PRIME is not set | 974 | # CONFIG_SOUND_PRIME is not set |
| 946 | CONFIG_AC97_BUS=m | 975 | CONFIG_AC97_BUS=m |
| 947 | CONFIG_HID_SUPPORT=y | 976 | CONFIG_HID_SUPPORT=y |
| 948 | CONFIG_HID=y | 977 | CONFIG_HID=y |
| 949 | # CONFIG_HID_DEBUG is not set | 978 | # CONFIG_HID_DEBUG is not set |
| 950 | # CONFIG_HIDRAW is not set | 979 | # CONFIG_HIDRAW is not set |
| 980 | # CONFIG_HID_PID is not set | ||
| 981 | |||
| 982 | # | ||
| 983 | # Special HID drivers | ||
| 984 | # | ||
| 985 | CONFIG_HID_COMPAT=y | ||
| 951 | # CONFIG_USB_SUPPORT is not set | 986 | # CONFIG_USB_SUPPORT is not set |
| 952 | # CONFIG_MMC is not set | 987 | # CONFIG_MMC is not set |
| 988 | # CONFIG_MEMSTICK is not set | ||
| 953 | # CONFIG_NEW_LEDS is not set | 989 | # CONFIG_NEW_LEDS is not set |
| 990 | # CONFIG_ACCESSIBILITY is not set | ||
| 954 | CONFIG_RTC_LIB=y | 991 | CONFIG_RTC_LIB=y |
| 955 | CONFIG_RTC_CLASS=y | 992 | CONFIG_RTC_CLASS=y |
| 956 | CONFIG_RTC_HCTOSYS=y | 993 | CONFIG_RTC_HCTOSYS=y |
| @@ -979,51 +1016,57 @@ CONFIG_RTC_INTF_DEV=y | |||
| 979 | # CONFIG_RTC_DRV_PCF8563 is not set | 1016 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 980 | # CONFIG_RTC_DRV_PCF8583 is not set | 1017 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 981 | # CONFIG_RTC_DRV_M41T80 is not set | 1018 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1019 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1020 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 982 | 1021 | ||
| 983 | # | 1022 | # |
| 984 | # SPI RTC drivers | 1023 | # SPI RTC drivers |
| 985 | # | 1024 | # |
| 986 | # CONFIG_RTC_DRV_RS5C348 is not set | 1025 | # CONFIG_RTC_DRV_M41T94 is not set |
| 1026 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 987 | # CONFIG_RTC_DRV_MAX6902 is not set | 1027 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 1028 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1029 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1030 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 988 | 1031 | ||
| 989 | # | 1032 | # |
| 990 | # Platform RTC drivers | 1033 | # Platform RTC drivers |
| 991 | # | 1034 | # |
| 1035 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1036 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 992 | # CONFIG_RTC_DRV_DS1553 is not set | 1037 | # CONFIG_RTC_DRV_DS1553 is not set |
| 993 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 994 | # CONFIG_RTC_DRV_DS1742 is not set | 1038 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1039 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 995 | # CONFIG_RTC_DRV_M48T86 is not set | 1040 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1041 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 996 | # CONFIG_RTC_DRV_M48T59 is not set | 1042 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1043 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 997 | # CONFIG_RTC_DRV_V3020 is not set | 1044 | # CONFIG_RTC_DRV_V3020 is not set |
| 998 | 1045 | ||
| 999 | # | 1046 | # |
| 1000 | # on-CPU RTC drivers | 1047 | # on-CPU RTC drivers |
| 1001 | # | 1048 | # |
| 1002 | CONFIG_RTC_DRV_BFIN=y | 1049 | CONFIG_RTC_DRV_BFIN=y |
| 1003 | 1050 | # CONFIG_DMADEVICES is not set | |
| 1004 | # | ||
| 1005 | # Userspace I/O | ||
| 1006 | # | ||
| 1007 | # CONFIG_UIO is not set | 1051 | # CONFIG_UIO is not set |
| 1052 | # CONFIG_STAGING is not set | ||
| 1008 | 1053 | ||
| 1009 | # | 1054 | # |
| 1010 | # File systems | 1055 | # File systems |
| 1011 | # | 1056 | # |
| 1012 | # CONFIG_EXT2_FS is not set | 1057 | # CONFIG_EXT2_FS is not set |
| 1013 | # CONFIG_EXT3_FS is not set | 1058 | # CONFIG_EXT3_FS is not set |
| 1014 | # CONFIG_EXT4DEV_FS is not set | 1059 | # CONFIG_EXT4_FS is not set |
| 1015 | # CONFIG_REISERFS_FS is not set | 1060 | # CONFIG_REISERFS_FS is not set |
| 1016 | # CONFIG_JFS_FS is not set | 1061 | # CONFIG_JFS_FS is not set |
| 1017 | # CONFIG_FS_POSIX_ACL is not set | 1062 | # CONFIG_FS_POSIX_ACL is not set |
| 1063 | CONFIG_FILE_LOCKING=y | ||
| 1018 | # CONFIG_XFS_FS is not set | 1064 | # CONFIG_XFS_FS is not set |
| 1019 | # CONFIG_GFS2_FS is not set | ||
| 1020 | # CONFIG_OCFS2_FS is not set | 1065 | # CONFIG_OCFS2_FS is not set |
| 1021 | # CONFIG_MINIX_FS is not set | 1066 | # CONFIG_DNOTIFY is not set |
| 1022 | # CONFIG_ROMFS_FS is not set | ||
| 1023 | CONFIG_INOTIFY=y | 1067 | CONFIG_INOTIFY=y |
| 1024 | CONFIG_INOTIFY_USER=y | 1068 | CONFIG_INOTIFY_USER=y |
| 1025 | # CONFIG_QUOTA is not set | 1069 | # CONFIG_QUOTA is not set |
| 1026 | # CONFIG_DNOTIFY is not set | ||
| 1027 | # CONFIG_AUTOFS_FS is not set | 1070 | # CONFIG_AUTOFS_FS is not set |
| 1028 | # CONFIG_AUTOFS4_FS is not set | 1071 | # CONFIG_AUTOFS4_FS is not set |
| 1029 | # CONFIG_FUSE_FS is not set | 1072 | # CONFIG_FUSE_FS is not set |
| @@ -1063,11 +1106,11 @@ CONFIG_SYSFS=y | |||
| 1063 | # CONFIG_EFS_FS is not set | 1106 | # CONFIG_EFS_FS is not set |
| 1064 | CONFIG_YAFFS_FS=m | 1107 | CONFIG_YAFFS_FS=m |
| 1065 | CONFIG_YAFFS_YAFFS1=y | 1108 | CONFIG_YAFFS_YAFFS1=y |
| 1109 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1066 | # CONFIG_YAFFS_DOES_ECC is not set | 1110 | # CONFIG_YAFFS_DOES_ECC is not set |
| 1067 | CONFIG_YAFFS_YAFFS2=y | 1111 | CONFIG_YAFFS_YAFFS2=y |
| 1068 | CONFIG_YAFFS_AUTO_YAFFS2=y | 1112 | CONFIG_YAFFS_AUTO_YAFFS2=y |
| 1069 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | 1113 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set |
| 1070 | CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 | ||
| 1071 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | 1114 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 1072 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | 1115 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 1073 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | 1116 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| @@ -1084,8 +1127,11 @@ CONFIG_JFFS2_RTIME=y | |||
| 1084 | # CONFIG_JFFS2_RUBIN is not set | 1127 | # CONFIG_JFFS2_RUBIN is not set |
| 1085 | # CONFIG_CRAMFS is not set | 1128 | # CONFIG_CRAMFS is not set |
| 1086 | # CONFIG_VXFS_FS is not set | 1129 | # CONFIG_VXFS_FS is not set |
| 1130 | # CONFIG_MINIX_FS is not set | ||
| 1131 | # CONFIG_OMFS_FS is not set | ||
| 1087 | # CONFIG_HPFS_FS is not set | 1132 | # CONFIG_HPFS_FS is not set |
| 1088 | # CONFIG_QNX4FS_FS is not set | 1133 | # CONFIG_QNX4FS_FS is not set |
| 1134 | # CONFIG_ROMFS_FS is not set | ||
| 1089 | # CONFIG_SYSV_FS is not set | 1135 | # CONFIG_SYSV_FS is not set |
| 1090 | # CONFIG_UFS_FS is not set | 1136 | # CONFIG_UFS_FS is not set |
| 1091 | CONFIG_NETWORK_FILESYSTEMS=y | 1137 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1093,13 +1139,12 @@ CONFIG_NFS_FS=m | |||
| 1093 | CONFIG_NFS_V3=y | 1139 | CONFIG_NFS_V3=y |
| 1094 | # CONFIG_NFS_V3_ACL is not set | 1140 | # CONFIG_NFS_V3_ACL is not set |
| 1095 | # CONFIG_NFS_V4 is not set | 1141 | # CONFIG_NFS_V4 is not set |
| 1096 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1097 | # CONFIG_NFSD is not set | 1142 | # CONFIG_NFSD is not set |
| 1098 | CONFIG_LOCKD=m | 1143 | CONFIG_LOCKD=m |
| 1099 | CONFIG_LOCKD_V4=y | 1144 | CONFIG_LOCKD_V4=y |
| 1100 | CONFIG_NFS_COMMON=y | 1145 | CONFIG_NFS_COMMON=y |
| 1101 | CONFIG_SUNRPC=m | 1146 | CONFIG_SUNRPC=m |
| 1102 | # CONFIG_SUNRPC_BIND34 is not set | 1147 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1103 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1148 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1104 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1149 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1105 | CONFIG_SMB_FS=m | 1150 | CONFIG_SMB_FS=m |
| @@ -1155,9 +1200,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1155 | # CONFIG_NLS_KOI8_U is not set | 1200 | # CONFIG_NLS_KOI8_U is not set |
| 1156 | # CONFIG_NLS_UTF8 is not set | 1201 | # CONFIG_NLS_UTF8 is not set |
| 1157 | # CONFIG_DLM is not set | 1202 | # CONFIG_DLM is not set |
| 1158 | CONFIG_INSTRUMENTATION=y | ||
| 1159 | # CONFIG_PROFILING is not set | ||
| 1160 | # CONFIG_MARKERS is not set | ||
| 1161 | 1203 | ||
| 1162 | # | 1204 | # |
| 1163 | # Kernel hacking | 1205 | # Kernel hacking |
| @@ -1165,14 +1207,53 @@ CONFIG_INSTRUMENTATION=y | |||
| 1165 | # CONFIG_PRINTK_TIME is not set | 1207 | # CONFIG_PRINTK_TIME is not set |
| 1166 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1208 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1167 | CONFIG_ENABLE_MUST_CHECK=y | 1209 | CONFIG_ENABLE_MUST_CHECK=y |
| 1210 | CONFIG_FRAME_WARN=1024 | ||
| 1168 | # CONFIG_MAGIC_SYSRQ is not set | 1211 | # CONFIG_MAGIC_SYSRQ is not set |
| 1169 | # CONFIG_UNUSED_SYMBOLS is not set | 1212 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1170 | CONFIG_DEBUG_FS=y | 1213 | CONFIG_DEBUG_FS=y |
| 1171 | # CONFIG_HEADERS_CHECK is not set | 1214 | # CONFIG_HEADERS_CHECK is not set |
| 1172 | # CONFIG_DEBUG_KERNEL is not set | 1215 | CONFIG_DEBUG_KERNEL=y |
| 1216 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1217 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1218 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1219 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1220 | CONFIG_SCHED_DEBUG=y | ||
| 1221 | # CONFIG_SCHEDSTATS is not set | ||
| 1222 | # CONFIG_TIMER_STATS is not set | ||
| 1223 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1224 | # CONFIG_DEBUG_SLAB is not set | ||
| 1225 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1226 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1227 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1228 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1229 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1230 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1231 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1173 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1232 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1233 | CONFIG_DEBUG_INFO=y | ||
| 1234 | # CONFIG_DEBUG_VM is not set | ||
| 1235 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1236 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1237 | # CONFIG_DEBUG_LIST is not set | ||
| 1238 | # CONFIG_DEBUG_SG is not set | ||
| 1239 | # CONFIG_FRAME_POINTER is not set | ||
| 1240 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1241 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1242 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1243 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1244 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1245 | # CONFIG_FAULT_INJECTION is not set | ||
| 1246 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1247 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1174 | # CONFIG_SAMPLES is not set | 1248 | # CONFIG_SAMPLES is not set |
| 1249 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1250 | # CONFIG_KGDB is not set | ||
| 1251 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1252 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1253 | CONFIG_DEBUG_VERBOSE=y | ||
| 1175 | CONFIG_DEBUG_MMRS=y | 1254 | CONFIG_DEBUG_MMRS=y |
| 1255 | # CONFIG_DEBUG_HWERR is not set | ||
| 1256 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 1176 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1257 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1177 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1258 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1178 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1259 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -1190,9 +1271,94 @@ CONFIG_ACCESS_CHECK=y | |||
| 1190 | # | 1271 | # |
| 1191 | # CONFIG_KEYS is not set | 1272 | # CONFIG_KEYS is not set |
| 1192 | CONFIG_SECURITY=y | 1273 | CONFIG_SECURITY=y |
| 1274 | # CONFIG_SECURITYFS is not set | ||
| 1193 | # CONFIG_SECURITY_NETWORK is not set | 1275 | # CONFIG_SECURITY_NETWORK is not set |
| 1194 | # CONFIG_SECURITY_CAPABILITIES is not set | 1276 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1195 | # CONFIG_CRYPTO is not set | 1277 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 |
| 1278 | CONFIG_CRYPTO=y | ||
| 1279 | |||
| 1280 | # | ||
| 1281 | # Crypto core or helper | ||
| 1282 | # | ||
| 1283 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1284 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1285 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1286 | # CONFIG_CRYPTO_NULL is not set | ||
| 1287 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1288 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1289 | # CONFIG_CRYPTO_TEST is not set | ||
| 1290 | |||
| 1291 | # | ||
| 1292 | # Authenticated Encryption with Associated Data | ||
| 1293 | # | ||
| 1294 | # CONFIG_CRYPTO_CCM is not set | ||
| 1295 | # CONFIG_CRYPTO_GCM is not set | ||
| 1296 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1297 | |||
| 1298 | # | ||
| 1299 | # Block modes | ||
| 1300 | # | ||
| 1301 | # CONFIG_CRYPTO_CBC is not set | ||
| 1302 | # CONFIG_CRYPTO_CTR is not set | ||
| 1303 | # CONFIG_CRYPTO_CTS is not set | ||
| 1304 | # CONFIG_CRYPTO_ECB is not set | ||
| 1305 | # CONFIG_CRYPTO_LRW is not set | ||
| 1306 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1307 | # CONFIG_CRYPTO_XTS is not set | ||
| 1308 | |||
| 1309 | # | ||
| 1310 | # Hash modes | ||
| 1311 | # | ||
| 1312 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1313 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1314 | |||
| 1315 | # | ||
| 1316 | # Digest | ||
| 1317 | # | ||
| 1318 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1319 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1320 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1321 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1322 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1323 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1324 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1325 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1326 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1327 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1328 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1329 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1330 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1331 | |||
| 1332 | # | ||
| 1333 | # Ciphers | ||
| 1334 | # | ||
| 1335 | # CONFIG_CRYPTO_AES is not set | ||
| 1336 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1337 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1338 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1339 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1340 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1341 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1342 | # CONFIG_CRYPTO_DES is not set | ||
| 1343 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1344 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1345 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1346 | # CONFIG_CRYPTO_SEED is not set | ||
| 1347 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1348 | # CONFIG_CRYPTO_TEA is not set | ||
| 1349 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1350 | |||
| 1351 | # | ||
| 1352 | # Compression | ||
| 1353 | # | ||
| 1354 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1355 | # CONFIG_CRYPTO_LZO is not set | ||
| 1356 | |||
| 1357 | # | ||
| 1358 | # Random Number Generation | ||
| 1359 | # | ||
| 1360 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1361 | CONFIG_CRYPTO_HW=y | ||
| 1196 | 1362 | ||
| 1197 | # | 1363 | # |
| 1198 | # Library routines | 1364 | # Library routines |
| @@ -1200,6 +1366,7 @@ CONFIG_SECURITY=y | |||
| 1200 | CONFIG_BITREVERSE=y | 1366 | CONFIG_BITREVERSE=y |
| 1201 | CONFIG_CRC_CCITT=m | 1367 | CONFIG_CRC_CCITT=m |
| 1202 | # CONFIG_CRC16 is not set | 1368 | # CONFIG_CRC16 is not set |
| 1369 | # CONFIG_CRC_T10DIF is not set | ||
| 1203 | # CONFIG_CRC_ITU_T is not set | 1370 | # CONFIG_CRC_ITU_T is not set |
| 1204 | CONFIG_CRC32=y | 1371 | CONFIG_CRC32=y |
| 1205 | # CONFIG_CRC7 is not set | 1372 | # CONFIG_CRC7 is not set |
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index 63a0f854745c..332142f7f9b4 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24.7 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # Tue Dec 30 17:24:37 2008 | ||
| 4 | # | 5 | # |
| 5 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -8,7 +9,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 9 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 9 | CONFIG_BLACKFIN=y | 10 | CONFIG_BLACKFIN=y |
| 10 | CONFIG_ZONE_DMA=y | 11 | CONFIG_ZONE_DMA=y |
| 11 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 13 | CONFIG_GENERIC_HWEIGHT=y | 13 | CONFIG_GENERIC_HWEIGHT=y |
| 14 | CONFIG_GENERIC_HARDIRQS=y | 14 | CONFIG_GENERIC_HARDIRQS=y |
| @@ -31,18 +31,16 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 31 | # CONFIG_POSIX_MQUEUE is not set | 31 | # CONFIG_POSIX_MQUEUE is not set |
| 32 | # CONFIG_BSD_PROCESS_ACCT is not set | 32 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 33 | # CONFIG_TASKSTATS is not set | 33 | # CONFIG_TASKSTATS is not set |
| 34 | # CONFIG_USER_NS is not set | ||
| 35 | # CONFIG_PID_NS is not set | ||
| 36 | # CONFIG_AUDIT is not set | 34 | # CONFIG_AUDIT is not set |
| 37 | CONFIG_IKCONFIG=y | 35 | CONFIG_IKCONFIG=y |
| 38 | CONFIG_IKCONFIG_PROC=y | 36 | CONFIG_IKCONFIG_PROC=y |
| 39 | CONFIG_LOG_BUF_SHIFT=14 | 37 | CONFIG_LOG_BUF_SHIFT=14 |
| 40 | # CONFIG_CGROUPS is not set | 38 | # CONFIG_CGROUPS is not set |
| 41 | CONFIG_FAIR_GROUP_SCHED=y | 39 | # CONFIG_GROUP_SCHED is not set |
| 42 | CONFIG_FAIR_USER_SCHED=y | 40 | # CONFIG_SYSFS_DEPRECATED is not set |
| 43 | # CONFIG_FAIR_CGROUP_SCHED is not set | 41 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 44 | CONFIG_SYSFS_DEPRECATED=y | ||
| 45 | # CONFIG_RELAY is not set | 42 | # CONFIG_RELAY is not set |
| 43 | # CONFIG_NAMESPACES is not set | ||
| 46 | CONFIG_BLK_DEV_INITRD=y | 44 | CONFIG_BLK_DEV_INITRD=y |
| 47 | CONFIG_INITRAMFS_SOURCE="" | 45 | CONFIG_INITRAMFS_SOURCE="" |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 46 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -51,26 +49,35 @@ CONFIG_EMBEDDED=y | |||
| 51 | CONFIG_UID16=y | 49 | CONFIG_UID16=y |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 50 | CONFIG_SYSCTL_SYSCALL=y |
| 53 | CONFIG_KALLSYMS=y | 51 | CONFIG_KALLSYMS=y |
| 52 | # CONFIG_KALLSYMS_ALL is not set | ||
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 53 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | CONFIG_HOTPLUG=y | 54 | CONFIG_HOTPLUG=y |
| 56 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 57 | # CONFIG_ELF_CORE is not set |
| 58 | CONFIG_COMPAT_BRK=y | ||
| 59 | CONFIG_BASE_FULL=y | 59 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 60 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 61 | CONFIG_ANON_INODES=y |
| 62 | CONFIG_EPOLL=y | 62 | CONFIG_EPOLL=y |
| 63 | CONFIG_SIGNALFD=y | 63 | CONFIG_SIGNALFD=y |
| 64 | CONFIG_TIMERFD=y | ||
| 64 | CONFIG_EVENTFD=y | 65 | CONFIG_EVENTFD=y |
| 66 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 67 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_SLAB=y | 68 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 69 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 70 | # CONFIG_SLOB is not set |
| 71 | # CONFIG_PROFILING is not set | ||
| 72 | # CONFIG_MARKERS is not set | ||
| 73 | CONFIG_HAVE_OPROFILE=y | ||
| 74 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 69 | CONFIG_SLABINFO=y | 75 | CONFIG_SLABINFO=y |
| 70 | CONFIG_RT_MUTEXES=y | 76 | CONFIG_RT_MUTEXES=y |
| 71 | CONFIG_TINY_SHMEM=y | 77 | CONFIG_TINY_SHMEM=y |
| 72 | CONFIG_BASE_SMALL=0 | 78 | CONFIG_BASE_SMALL=0 |
| 73 | CONFIG_MODULES=y | 79 | CONFIG_MODULES=y |
| 80 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 74 | CONFIG_MODULE_UNLOAD=y | 81 | CONFIG_MODULE_UNLOAD=y |
| 75 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 82 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 76 | # CONFIG_MODVERSIONS is not set | 83 | # CONFIG_MODVERSIONS is not set |
| @@ -81,6 +88,7 @@ CONFIG_BLOCK=y | |||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | 88 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 82 | # CONFIG_LSF is not set | 89 | # CONFIG_LSF is not set |
| 83 | # CONFIG_BLK_DEV_BSG is not set | 90 | # CONFIG_BLK_DEV_BSG is not set |
| 91 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 84 | 92 | ||
| 85 | # | 93 | # |
| 86 | # IO Schedulers | 94 | # IO Schedulers |
| @@ -94,9 +102,11 @@ CONFIG_DEFAULT_AS=y | |||
| 94 | # CONFIG_DEFAULT_CFQ is not set | 102 | # CONFIG_DEFAULT_CFQ is not set |
| 95 | # CONFIG_DEFAULT_NOOP is not set | 103 | # CONFIG_DEFAULT_NOOP is not set |
| 96 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 104 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 105 | CONFIG_CLASSIC_RCU=y | ||
| 97 | # CONFIG_PREEMPT_NONE is not set | 106 | # CONFIG_PREEMPT_NONE is not set |
| 98 | CONFIG_PREEMPT_VOLUNTARY=y | 107 | CONFIG_PREEMPT_VOLUNTARY=y |
| 99 | # CONFIG_PREEMPT is not set | 108 | # CONFIG_PREEMPT is not set |
| 109 | CONFIG_FREEZER=y | ||
| 100 | 110 | ||
| 101 | # | 111 | # |
| 102 | # Blackfin Processor Options | 112 | # Blackfin Processor Options |
| @@ -105,6 +115,10 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 105 | # | 115 | # |
| 106 | # Processor and Board Settings | 116 | # Processor and Board Settings |
| 107 | # | 117 | # |
| 118 | # CONFIG_BF512 is not set | ||
| 119 | # CONFIG_BF514 is not set | ||
| 120 | # CONFIG_BF516 is not set | ||
| 121 | # CONFIG_BF518 is not set | ||
| 108 | # CONFIG_BF522 is not set | 122 | # CONFIG_BF522 is not set |
| 109 | # CONFIG_BF523 is not set | 123 | # CONFIG_BF523 is not set |
| 110 | # CONFIG_BF524 is not set | 124 | # CONFIG_BF524 is not set |
| @@ -117,18 +131,23 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 117 | # CONFIG_BF534 is not set | 131 | # CONFIG_BF534 is not set |
| 118 | # CONFIG_BF536 is not set | 132 | # CONFIG_BF536 is not set |
| 119 | CONFIG_BF537=y | 133 | CONFIG_BF537=y |
| 134 | # CONFIG_BF538 is not set | ||
| 135 | # CONFIG_BF539 is not set | ||
| 120 | # CONFIG_BF542 is not set | 136 | # CONFIG_BF542 is not set |
| 121 | # CONFIG_BF544 is not set | 137 | # CONFIG_BF544 is not set |
| 122 | # CONFIG_BF547 is not set | 138 | # CONFIG_BF547 is not set |
| 123 | # CONFIG_BF548 is not set | 139 | # CONFIG_BF548 is not set |
| 124 | # CONFIG_BF549 is not set | 140 | # CONFIG_BF549 is not set |
| 125 | # CONFIG_BF561 is not set | 141 | # CONFIG_BF561 is not set |
| 142 | CONFIG_BF_REV_MIN=2 | ||
| 143 | CONFIG_BF_REV_MAX=3 | ||
| 126 | # CONFIG_BF_REV_0_0 is not set | 144 | # CONFIG_BF_REV_0_0 is not set |
| 127 | # CONFIG_BF_REV_0_1 is not set | 145 | # CONFIG_BF_REV_0_1 is not set |
| 128 | CONFIG_BF_REV_0_2=y | 146 | CONFIG_BF_REV_0_2=y |
| 129 | # CONFIG_BF_REV_0_3 is not set | 147 | # CONFIG_BF_REV_0_3 is not set |
| 130 | # CONFIG_BF_REV_0_4 is not set | 148 | # CONFIG_BF_REV_0_4 is not set |
| 131 | # CONFIG_BF_REV_0_5 is not set | 149 | # CONFIG_BF_REV_0_5 is not set |
| 150 | # CONFIG_BF_REV_0_6 is not set | ||
| 132 | # CONFIG_BF_REV_ANY is not set | 151 | # CONFIG_BF_REV_ANY is not set |
| 133 | # CONFIG_BF_REV_NONE is not set | 152 | # CONFIG_BF_REV_NONE is not set |
| 134 | CONFIG_BF53x=y | 153 | CONFIG_BF53x=y |
| @@ -141,27 +160,28 @@ CONFIG_IRQ_SPORT0_TX=9 | |||
| 141 | CONFIG_IRQ_SPORT1_RX=9 | 160 | CONFIG_IRQ_SPORT1_RX=9 |
| 142 | CONFIG_IRQ_SPORT1_TX=9 | 161 | CONFIG_IRQ_SPORT1_TX=9 |
| 143 | CONFIG_IRQ_TWI=10 | 162 | CONFIG_IRQ_TWI=10 |
| 144 | CONFIG_IRQ_SPI=10 | ||
| 145 | CONFIG_IRQ_UART0_RX=10 | 163 | CONFIG_IRQ_UART0_RX=10 |
| 146 | CONFIG_IRQ_UART0_TX=10 | 164 | CONFIG_IRQ_UART0_TX=10 |
| 147 | CONFIG_IRQ_UART1_RX=10 | 165 | CONFIG_IRQ_UART1_RX=10 |
| 148 | CONFIG_IRQ_UART1_TX=10 | 166 | CONFIG_IRQ_UART1_TX=10 |
| 149 | CONFIG_IRQ_MAC_RX=11 | 167 | CONFIG_IRQ_MAC_RX=11 |
| 150 | CONFIG_IRQ_MAC_TX=11 | 168 | CONFIG_IRQ_MAC_TX=11 |
| 151 | CONFIG_IRQ_TMR0=12 | 169 | CONFIG_IRQ_TIMER0=8 |
| 152 | CONFIG_IRQ_TMR1=12 | 170 | CONFIG_IRQ_TIMER1=12 |
| 153 | CONFIG_IRQ_TMR2=12 | 171 | CONFIG_IRQ_TIMER2=12 |
| 154 | CONFIG_IRQ_TMR3=12 | 172 | CONFIG_IRQ_TIMER3=12 |
| 155 | CONFIG_IRQ_TMR4=12 | 173 | CONFIG_IRQ_TIMER4=12 |
| 156 | CONFIG_IRQ_TMR5=12 | 174 | CONFIG_IRQ_TIMER5=12 |
| 157 | CONFIG_IRQ_TMR6=12 | 175 | CONFIG_IRQ_TIMER6=12 |
| 158 | CONFIG_IRQ_TMR7=12 | 176 | CONFIG_IRQ_TIMER7=12 |
| 159 | CONFIG_IRQ_PORTG_INTB=12 | 177 | CONFIG_IRQ_PORTG_INTB=12 |
| 160 | CONFIG_IRQ_MEM_DMA0=13 | 178 | CONFIG_IRQ_MEM_DMA0=13 |
| 161 | CONFIG_IRQ_MEM_DMA1=13 | 179 | CONFIG_IRQ_MEM_DMA1=13 |
| 162 | CONFIG_IRQ_WATCH=13 | 180 | CONFIG_IRQ_WATCH=13 |
| 181 | CONFIG_IRQ_SPI=10 | ||
| 163 | CONFIG_BFIN537_STAMP=y | 182 | CONFIG_BFIN537_STAMP=y |
| 164 | # CONFIG_BFIN537_BLUETECHNIX_CM is not set | 183 | # CONFIG_BFIN537_BLUETECHNIX_CM is not set |
| 184 | # CONFIG_BFIN537_BLUETECHNIX_TCM is not set | ||
| 165 | # CONFIG_PNAV10 is not set | 185 | # CONFIG_PNAV10 is not set |
| 166 | # CONFIG_CAMSIG_MINOTAUR is not set | 186 | # CONFIG_CAMSIG_MINOTAUR is not set |
| 167 | # CONFIG_GENERIC_BF537_BOARD is not set | 187 | # CONFIG_GENERIC_BF537_BOARD is not set |
| @@ -194,7 +214,6 @@ CONFIG_BOOT_LOAD=0x1000 | |||
| 194 | # | 214 | # |
| 195 | CONFIG_CLKIN_HZ=25000000 | 215 | CONFIG_CLKIN_HZ=25000000 |
| 196 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 216 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 197 | CONFIG_MAX_MEM_SIZE=512 | ||
| 198 | CONFIG_MAX_VCO_HZ=600000000 | 217 | CONFIG_MAX_VCO_HZ=600000000 |
| 199 | CONFIG_MIN_VCO_HZ=50000000 | 218 | CONFIG_MIN_VCO_HZ=50000000 |
| 200 | CONFIG_MAX_SCLK_HZ=133333333 | 219 | CONFIG_MAX_SCLK_HZ=133333333 |
| @@ -208,6 +227,7 @@ CONFIG_HZ_250=y | |||
| 208 | # CONFIG_HZ_300 is not set | 227 | # CONFIG_HZ_300 is not set |
| 209 | # CONFIG_HZ_1000 is not set | 228 | # CONFIG_HZ_1000 is not set |
| 210 | CONFIG_HZ=250 | 229 | CONFIG_HZ=250 |
| 230 | CONFIG_SCHED_HRTICK=y | ||
| 211 | CONFIG_GENERIC_TIME=y | 231 | CONFIG_GENERIC_TIME=y |
| 212 | CONFIG_GENERIC_CLOCKEVENTS=y | 232 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 213 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 233 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| @@ -245,6 +265,12 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y | |||
| 245 | CONFIG_CACHELINE_ALIGNED_L1=y | 265 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 246 | # CONFIG_SYSCALL_TAB_L1 is not set | 266 | # CONFIG_SYSCALL_TAB_L1 is not set |
| 247 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | 267 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set |
| 268 | CONFIG_APP_STACK_L1=y | ||
| 269 | |||
| 270 | # | ||
| 271 | # Speed Optimizations | ||
| 272 | # | ||
| 273 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 248 | CONFIG_RAMKERNEL=y | 274 | CONFIG_RAMKERNEL=y |
| 249 | # CONFIG_ROMKERNEL is not set | 275 | # CONFIG_ROMKERNEL is not set |
| 250 | CONFIG_SELECT_MEMORY_MODEL=y | 276 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -253,14 +279,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 253 | # CONFIG_SPARSEMEM_MANUAL is not set | 279 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 254 | CONFIG_FLATMEM=y | 280 | CONFIG_FLATMEM=y |
| 255 | CONFIG_FLAT_NODE_MEM_MAP=y | 281 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 256 | # CONFIG_SPARSEMEM_STATIC is not set | 282 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 257 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 258 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 283 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 259 | # CONFIG_RESOURCES_64BIT is not set | 284 | # CONFIG_RESOURCES_64BIT is not set |
| 285 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 260 | CONFIG_ZONE_DMA_FLAG=1 | 286 | CONFIG_ZONE_DMA_FLAG=1 |
| 261 | CONFIG_VIRT_TO_BUS=y | 287 | CONFIG_VIRT_TO_BUS=y |
| 262 | # CONFIG_BFIN_GPTIMERS is not set | 288 | CONFIG_BFIN_GPTIMERS=m |
| 263 | CONFIG_BFIN_DMA_5XX=y | ||
| 264 | # CONFIG_DMA_UNCACHED_4M is not set | 289 | # CONFIG_DMA_UNCACHED_4M is not set |
| 265 | # CONFIG_DMA_UNCACHED_2M is not set | 290 | # CONFIG_DMA_UNCACHED_2M is not set |
| 266 | CONFIG_DMA_UNCACHED_1M=y | 291 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -275,7 +300,6 @@ CONFIG_BFIN_DCACHE=y | |||
| 275 | # CONFIG_BFIN_ICACHE_LOCK is not set | 300 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 276 | # CONFIG_BFIN_WB is not set | 301 | # CONFIG_BFIN_WB is not set |
| 277 | CONFIG_BFIN_WT=y | 302 | CONFIG_BFIN_WT=y |
| 278 | CONFIG_L1_MAX_PIECE=16 | ||
| 279 | # CONFIG_MPU is not set | 303 | # CONFIG_MPU is not set |
| 280 | 304 | ||
| 281 | # | 305 | # |
| @@ -304,7 +328,6 @@ CONFIG_BANK_3=0x99B2 | |||
| 304 | # | 328 | # |
| 305 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 329 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 306 | # | 330 | # |
| 307 | # CONFIG_PCI is not set | ||
| 308 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 331 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 309 | # CONFIG_PCCARD is not set | 332 | # CONFIG_PCCARD is not set |
| 310 | 333 | ||
| @@ -315,29 +338,31 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 315 | CONFIG_BINFMT_FLAT=y | 338 | CONFIG_BINFMT_FLAT=y |
| 316 | CONFIG_BINFMT_ZFLAT=y | 339 | CONFIG_BINFMT_ZFLAT=y |
| 317 | # CONFIG_BINFMT_SHARED_FLAT is not set | 340 | # CONFIG_BINFMT_SHARED_FLAT is not set |
| 341 | # CONFIG_HAVE_AOUT is not set | ||
| 318 | # CONFIG_BINFMT_MISC is not set | 342 | # CONFIG_BINFMT_MISC is not set |
| 319 | 343 | ||
| 320 | # | 344 | # |
| 321 | # Power management options | 345 | # Power management options |
| 322 | # | 346 | # |
| 323 | CONFIG_PM=y | 347 | CONFIG_PM=y |
| 324 | # CONFIG_PM_LEGACY is not set | ||
| 325 | # CONFIG_PM_DEBUG is not set | 348 | # CONFIG_PM_DEBUG is not set |
| 326 | CONFIG_PM_SLEEP=y | 349 | CONFIG_PM_SLEEP=y |
| 327 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 328 | CONFIG_SUSPEND=y | 350 | CONFIG_SUSPEND=y |
| 351 | CONFIG_SUSPEND_FREEZER=y | ||
| 352 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 329 | CONFIG_PM_BFIN_SLEEP_DEEPER=y | 353 | CONFIG_PM_BFIN_SLEEP_DEEPER=y |
| 330 | # CONFIG_PM_BFIN_SLEEP is not set | 354 | # CONFIG_PM_BFIN_SLEEP is not set |
| 331 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | 355 | # CONFIG_PM_WAKEUP_BY_GPIO is not set |
| 332 | 356 | ||
| 333 | # | 357 | # |
| 334 | # CPU Frequency scaling | 358 | # Possible Suspend Mem / Hibernate Wake-Up Sources |
| 335 | # | 359 | # |
| 336 | # CONFIG_CPU_FREQ is not set | 360 | # CONFIG_PM_BFIN_WAKE_PH6 is not set |
| 337 | 361 | ||
| 338 | # | 362 | # |
| 339 | # Networking | 363 | # CPU Frequency scaling |
| 340 | # | 364 | # |
| 365 | # CONFIG_CPU_FREQ is not set | ||
| 341 | CONFIG_NET=y | 366 | CONFIG_NET=y |
| 342 | 367 | ||
| 343 | # | 368 | # |
| @@ -350,6 +375,7 @@ CONFIG_XFRM=y | |||
| 350 | # CONFIG_XFRM_USER is not set | 375 | # CONFIG_XFRM_USER is not set |
| 351 | # CONFIG_XFRM_SUB_POLICY is not set | 376 | # CONFIG_XFRM_SUB_POLICY is not set |
| 352 | # CONFIG_XFRM_MIGRATE is not set | 377 | # CONFIG_XFRM_MIGRATE is not set |
| 378 | # CONFIG_XFRM_STATISTICS is not set | ||
| 353 | # CONFIG_NET_KEY is not set | 379 | # CONFIG_NET_KEY is not set |
| 354 | CONFIG_INET=y | 380 | CONFIG_INET=y |
| 355 | # CONFIG_IP_MULTICAST is not set | 381 | # CONFIG_IP_MULTICAST is not set |
| @@ -379,8 +405,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 379 | CONFIG_DEFAULT_TCP_CONG="cubic" | 405 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 380 | # CONFIG_TCP_MD5SIG is not set | 406 | # CONFIG_TCP_MD5SIG is not set |
| 381 | # CONFIG_IPV6 is not set | 407 | # CONFIG_IPV6 is not set |
| 382 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 383 | # CONFIG_INET6_TUNNEL is not set | ||
| 384 | # CONFIG_NETLABEL is not set | 408 | # CONFIG_NETLABEL is not set |
| 385 | # CONFIG_NETWORK_SECMARK is not set | 409 | # CONFIG_NETWORK_SECMARK is not set |
| 386 | # CONFIG_NETFILTER is not set | 410 | # CONFIG_NETFILTER is not set |
| @@ -389,6 +413,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 389 | # CONFIG_TIPC is not set | 413 | # CONFIG_TIPC is not set |
| 390 | # CONFIG_ATM is not set | 414 | # CONFIG_ATM is not set |
| 391 | # CONFIG_BRIDGE is not set | 415 | # CONFIG_BRIDGE is not set |
| 416 | # CONFIG_NET_DSA is not set | ||
| 392 | # CONFIG_VLAN_8021Q is not set | 417 | # CONFIG_VLAN_8021Q is not set |
| 393 | # CONFIG_DECNET is not set | 418 | # CONFIG_DECNET is not set |
| 394 | # CONFIG_LLC2 is not set | 419 | # CONFIG_LLC2 is not set |
| @@ -405,6 +430,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 405 | # | 430 | # |
| 406 | # CONFIG_NET_PKTGEN is not set | 431 | # CONFIG_NET_PKTGEN is not set |
| 407 | # CONFIG_HAMRADIO is not set | 432 | # CONFIG_HAMRADIO is not set |
| 433 | # CONFIG_CAN is not set | ||
| 408 | CONFIG_IRDA=m | 434 | CONFIG_IRDA=m |
| 409 | 435 | ||
| 410 | # | 436 | # |
| @@ -440,24 +466,14 @@ CONFIG_SIR_BFIN_DMA=y | |||
| 440 | # CONFIG_DONGLE is not set | 466 | # CONFIG_DONGLE is not set |
| 441 | 467 | ||
| 442 | # | 468 | # |
| 443 | # Old SIR device drivers | ||
| 444 | # | ||
| 445 | # CONFIG_IRPORT_SIR is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Old Serial dongle support | ||
| 449 | # | ||
| 450 | |||
| 451 | # | ||
| 452 | # FIR device drivers | 469 | # FIR device drivers |
| 453 | # | 470 | # |
| 454 | # CONFIG_BT is not set | 471 | # CONFIG_BT is not set |
| 455 | # CONFIG_AF_RXRPC is not set | 472 | # CONFIG_AF_RXRPC is not set |
| 456 | 473 | # CONFIG_PHONET is not set | |
| 457 | # | 474 | CONFIG_WIRELESS=y |
| 458 | # Wireless | ||
| 459 | # | ||
| 460 | # CONFIG_CFG80211 is not set | 475 | # CONFIG_CFG80211 is not set |
| 476 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 461 | # CONFIG_WIRELESS_EXT is not set | 477 | # CONFIG_WIRELESS_EXT is not set |
| 462 | # CONFIG_MAC80211 is not set | 478 | # CONFIG_MAC80211 is not set |
| 463 | # CONFIG_IEEE80211 is not set | 479 | # CONFIG_IEEE80211 is not set |
| @@ -475,6 +491,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 475 | CONFIG_STANDALONE=y | 491 | CONFIG_STANDALONE=y |
| 476 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 492 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 477 | # CONFIG_FW_LOADER is not set | 493 | # CONFIG_FW_LOADER is not set |
| 494 | # CONFIG_DEBUG_DRIVER is not set | ||
| 495 | # CONFIG_DEBUG_DEVRES is not set | ||
| 478 | # CONFIG_SYS_HYPERVISOR is not set | 496 | # CONFIG_SYS_HYPERVISOR is not set |
| 479 | # CONFIG_CONNECTOR is not set | 497 | # CONFIG_CONNECTOR is not set |
| 480 | CONFIG_MTD=y | 498 | CONFIG_MTD=y |
| @@ -483,6 +501,7 @@ CONFIG_MTD=y | |||
| 483 | CONFIG_MTD_PARTITIONS=y | 501 | CONFIG_MTD_PARTITIONS=y |
| 484 | # CONFIG_MTD_REDBOOT_PARTS is not set | 502 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 485 | CONFIG_MTD_CMDLINE_PARTS=y | 503 | CONFIG_MTD_CMDLINE_PARTS=y |
| 504 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 486 | 505 | ||
| 487 | # | 506 | # |
| 488 | # User Modules And Translation Layers | 507 | # User Modules And Translation Layers |
| @@ -553,15 +572,11 @@ CONFIG_MTD_NAND=m | |||
| 553 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | 572 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set |
| 554 | # CONFIG_MTD_NAND_ECC_SMC is not set | 573 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 555 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | 574 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set |
| 556 | CONFIG_MTD_NAND_BFIN=m | 575 | # CONFIG_MTD_NAND_BFIN is not set |
| 557 | CONFIG_BFIN_NAND_BASE=0x20212000 | ||
| 558 | CONFIG_BFIN_NAND_CLE=2 | ||
| 559 | CONFIG_BFIN_NAND_ALE=1 | ||
| 560 | CONFIG_BFIN_NAND_READY=3 | ||
| 561 | CONFIG_MTD_NAND_IDS=m | 576 | CONFIG_MTD_NAND_IDS=m |
| 562 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 577 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 563 | # CONFIG_MTD_NAND_NANDSIM is not set | 578 | # CONFIG_MTD_NAND_NANDSIM is not set |
| 564 | # CONFIG_MTD_NAND_PLATFORM is not set | 579 | CONFIG_MTD_NAND_PLATFORM=m |
| 565 | # CONFIG_MTD_ONENAND is not set | 580 | # CONFIG_MTD_ONENAND is not set |
| 566 | 581 | ||
| 567 | # | 582 | # |
| @@ -576,11 +591,14 @@ CONFIG_BLK_DEV=y | |||
| 576 | CONFIG_BLK_DEV_RAM=y | 591 | CONFIG_BLK_DEV_RAM=y |
| 577 | CONFIG_BLK_DEV_RAM_COUNT=16 | 592 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 578 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 593 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 579 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 594 | # CONFIG_BLK_DEV_XIP is not set |
| 580 | # CONFIG_CDROM_PKTCDVD is not set | 595 | # CONFIG_CDROM_PKTCDVD is not set |
| 581 | # CONFIG_ATA_OVER_ETH is not set | 596 | # CONFIG_ATA_OVER_ETH is not set |
| 597 | # CONFIG_BLK_DEV_HD is not set | ||
| 582 | CONFIG_MISC_DEVICES=y | 598 | CONFIG_MISC_DEVICES=y |
| 583 | # CONFIG_EEPROM_93CX6 is not set | 599 | # CONFIG_EEPROM_93CX6 is not set |
| 600 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 601 | CONFIG_HAVE_IDE=y | ||
| 584 | # CONFIG_IDE is not set | 602 | # CONFIG_IDE is not set |
| 585 | 603 | ||
| 586 | # | 604 | # |
| @@ -593,7 +611,6 @@ CONFIG_MISC_DEVICES=y | |||
| 593 | # CONFIG_ATA is not set | 611 | # CONFIG_ATA is not set |
| 594 | # CONFIG_MD is not set | 612 | # CONFIG_MD is not set |
| 595 | CONFIG_NETDEVICES=y | 613 | CONFIG_NETDEVICES=y |
| 596 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 597 | # CONFIG_DUMMY is not set | 614 | # CONFIG_DUMMY is not set |
| 598 | # CONFIG_BONDING is not set | 615 | # CONFIG_BONDING is not set |
| 599 | # CONFIG_MACVLAN is not set | 616 | # CONFIG_MACVLAN is not set |
| @@ -614,6 +631,7 @@ CONFIG_PHYLIB=y | |||
| 614 | CONFIG_SMSC_PHY=y | 631 | CONFIG_SMSC_PHY=y |
| 615 | # CONFIG_BROADCOM_PHY is not set | 632 | # CONFIG_BROADCOM_PHY is not set |
| 616 | # CONFIG_ICPLUS_PHY is not set | 633 | # CONFIG_ICPLUS_PHY is not set |
| 634 | # CONFIG_REALTEK_PHY is not set | ||
| 617 | # CONFIG_FIXED_PHY is not set | 635 | # CONFIG_FIXED_PHY is not set |
| 618 | # CONFIG_MDIO_BITBANG is not set | 636 | # CONFIG_MDIO_BITBANG is not set |
| 619 | CONFIG_NET_ETHERNET=y | 637 | CONFIG_NET_ETHERNET=y |
| @@ -626,11 +644,14 @@ CONFIG_BFIN_RX_DESC_NUM=20 | |||
| 626 | # CONFIG_SMC91X is not set | 644 | # CONFIG_SMC91X is not set |
| 627 | # CONFIG_SMSC911X is not set | 645 | # CONFIG_SMSC911X is not set |
| 628 | # CONFIG_DM9000 is not set | 646 | # CONFIG_DM9000 is not set |
| 647 | # CONFIG_ENC28J60 is not set | ||
| 629 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 648 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 630 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 649 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 631 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 650 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 632 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 651 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 633 | # CONFIG_B44 is not set | 652 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set |
| 653 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 654 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 634 | CONFIG_NETDEV_1000=y | 655 | CONFIG_NETDEV_1000=y |
| 635 | # CONFIG_AX88180 is not set | 656 | # CONFIG_AX88180 is not set |
| 636 | CONFIG_NETDEV_10000=y | 657 | CONFIG_NETDEV_10000=y |
| @@ -640,10 +661,10 @@ CONFIG_NETDEV_10000=y | |||
| 640 | # | 661 | # |
| 641 | # CONFIG_WLAN_PRE80211 is not set | 662 | # CONFIG_WLAN_PRE80211 is not set |
| 642 | # CONFIG_WLAN_80211 is not set | 663 | # CONFIG_WLAN_80211 is not set |
| 664 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 643 | # CONFIG_WAN is not set | 665 | # CONFIG_WAN is not set |
| 644 | # CONFIG_PPP is not set | 666 | # CONFIG_PPP is not set |
| 645 | # CONFIG_SLIP is not set | 667 | # CONFIG_SLIP is not set |
| 646 | # CONFIG_SHAPER is not set | ||
| 647 | # CONFIG_NETCONSOLE is not set | 668 | # CONFIG_NETCONSOLE is not set |
| 648 | # CONFIG_NETPOLL is not set | 669 | # CONFIG_NETPOLL is not set |
| 649 | # CONFIG_NET_POLL_CONTROLLER is not set | 670 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -675,12 +696,15 @@ CONFIG_INPUT_EVDEV=m | |||
| 675 | # CONFIG_INPUT_TOUCHSCREEN is not set | 696 | # CONFIG_INPUT_TOUCHSCREEN is not set |
| 676 | CONFIG_INPUT_MISC=y | 697 | CONFIG_INPUT_MISC=y |
| 677 | # CONFIG_INPUT_UINPUT is not set | 698 | # CONFIG_INPUT_UINPUT is not set |
| 678 | CONFIG_TWI_KEYPAD=m | 699 | CONFIG_CONFIG_INPUT_PCF8574=m |
| 679 | 700 | ||
| 680 | # | 701 | # |
| 681 | # Hardware I/O ports | 702 | # Hardware I/O ports |
| 682 | # | 703 | # |
| 683 | # CONFIG_SERIO is not set | 704 | CONFIG_SERIO=y |
| 705 | CONFIG_SERIO_SERPORT=y | ||
| 706 | CONFIG_SERIO_LIBPS2=y | ||
| 707 | # CONFIG_SERIO_RAW is not set | ||
| 684 | # CONFIG_GAMEPORT is not set | 708 | # CONFIG_GAMEPORT is not set |
| 685 | 709 | ||
| 686 | # | 710 | # |
| @@ -691,11 +715,14 @@ CONFIG_TWI_KEYPAD=m | |||
| 691 | # CONFIG_BF5xx_PPIFCD is not set | 715 | # CONFIG_BF5xx_PPIFCD is not set |
| 692 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 716 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 693 | # CONFIG_BF5xx_PPI is not set | 717 | # CONFIG_BF5xx_PPI is not set |
| 694 | CONFIG_BFIN_SPORT=y | 718 | CONFIG_BFIN_SPORT=m |
| 695 | # CONFIG_BFIN_TIMER_LATENCY is not set | 719 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 696 | CONFIG_TWI_LCD=m | 720 | CONFIG_TWI_LCD=m |
| 721 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 697 | CONFIG_SIMPLE_GPIO=m | 722 | CONFIG_SIMPLE_GPIO=m |
| 698 | # CONFIG_VT is not set | 723 | # CONFIG_VT is not set |
| 724 | # CONFIG_DEVKMEM is not set | ||
| 725 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 699 | # CONFIG_SERIAL_NONSTANDARD is not set | 726 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 700 | 727 | ||
| 701 | # | 728 | # |
| @@ -727,48 +754,51 @@ CONFIG_CAN4LINUX=y | |||
| 727 | # | 754 | # |
| 728 | # linux embedded drivers | 755 | # linux embedded drivers |
| 729 | # | 756 | # |
| 730 | # CONFIG_CAN_MCF5282 is not set | ||
| 731 | # CONFIG_CAN_UNCTWINCAN is not set | ||
| 732 | CONFIG_CAN_BLACKFIN=m | 757 | CONFIG_CAN_BLACKFIN=m |
| 733 | # CONFIG_IPMI_HANDLER is not set | 758 | # CONFIG_IPMI_HANDLER is not set |
| 734 | # CONFIG_HW_RANDOM is not set | 759 | # CONFIG_HW_RANDOM is not set |
| 735 | # CONFIG_GEN_RTC is not set | ||
| 736 | # CONFIG_R3964 is not set | 760 | # CONFIG_R3964 is not set |
| 737 | # CONFIG_RAW_DRIVER is not set | 761 | # CONFIG_RAW_DRIVER is not set |
| 738 | # CONFIG_TCG_TPM is not set | 762 | # CONFIG_TCG_TPM is not set |
| 739 | CONFIG_I2C=m | 763 | CONFIG_I2C=m |
| 740 | CONFIG_I2C_BOARDINFO=y | 764 | CONFIG_I2C_BOARDINFO=y |
| 741 | CONFIG_I2C_CHARDEV=m | 765 | CONFIG_I2C_CHARDEV=m |
| 766 | CONFIG_I2C_HELPER_AUTO=y | ||
| 742 | 767 | ||
| 743 | # | 768 | # |
| 744 | # I2C Algorithms | 769 | # I2C Hardware Bus support |
| 745 | # | 770 | # |
| 746 | # CONFIG_I2C_ALGOBIT is not set | ||
| 747 | # CONFIG_I2C_ALGOPCF is not set | ||
| 748 | # CONFIG_I2C_ALGOPCA is not set | ||
| 749 | 771 | ||
| 750 | # | 772 | # |
| 751 | # I2C Hardware Bus support | 773 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 752 | # | 774 | # |
| 753 | CONFIG_I2C_BLACKFIN_TWI=m | 775 | CONFIG_I2C_BLACKFIN_TWI=m |
| 754 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | 776 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 |
| 755 | # CONFIG_I2C_GPIO is not set | 777 | # CONFIG_I2C_GPIO is not set |
| 756 | # CONFIG_I2C_OCORES is not set | 778 | # CONFIG_I2C_OCORES is not set |
| 757 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 758 | # CONFIG_I2C_SIMTEC is not set | 779 | # CONFIG_I2C_SIMTEC is not set |
| 780 | |||
| 781 | # | ||
| 782 | # External I2C/SMBus adapter drivers | ||
| 783 | # | ||
| 784 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 759 | # CONFIG_I2C_TAOS_EVM is not set | 785 | # CONFIG_I2C_TAOS_EVM is not set |
| 786 | |||
| 787 | # | ||
| 788 | # Other I2C/SMBus bus drivers | ||
| 789 | # | ||
| 790 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 760 | # CONFIG_I2C_STUB is not set | 791 | # CONFIG_I2C_STUB is not set |
| 761 | 792 | ||
| 762 | # | 793 | # |
| 763 | # Miscellaneous I2C Chip support | 794 | # Miscellaneous I2C Chip support |
| 764 | # | 795 | # |
| 765 | # CONFIG_SENSORS_DS1337 is not set | ||
| 766 | # CONFIG_SENSORS_DS1374 is not set | ||
| 767 | # CONFIG_DS1682 is not set | 796 | # CONFIG_DS1682 is not set |
| 797 | # CONFIG_AT24 is not set | ||
| 768 | CONFIG_SENSORS_AD5252=m | 798 | CONFIG_SENSORS_AD5252=m |
| 769 | # CONFIG_SENSORS_EEPROM is not set | 799 | # CONFIG_SENSORS_EEPROM is not set |
| 770 | # CONFIG_SENSORS_PCF8574 is not set | 800 | # CONFIG_SENSORS_PCF8574 is not set |
| 771 | # CONFIG_SENSORS_PCF8575 is not set | 801 | # CONFIG_PCF8575 is not set |
| 772 | # CONFIG_SENSORS_PCA9539 is not set | 802 | # CONFIG_SENSORS_PCA9539 is not set |
| 773 | # CONFIG_SENSORS_PCF8591 is not set | 803 | # CONFIG_SENSORS_PCF8591 is not set |
| 774 | # CONFIG_SENSORS_MAX6875 is not set | 804 | # CONFIG_SENSORS_MAX6875 is not set |
| @@ -777,17 +807,15 @@ CONFIG_SENSORS_AD5252=m | |||
| 777 | # CONFIG_I2C_DEBUG_ALGO is not set | 807 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 778 | # CONFIG_I2C_DEBUG_BUS is not set | 808 | # CONFIG_I2C_DEBUG_BUS is not set |
| 779 | # CONFIG_I2C_DEBUG_CHIP is not set | 809 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 780 | |||
| 781 | # | ||
| 782 | # SPI support | ||
| 783 | # | ||
| 784 | CONFIG_SPI=y | 810 | CONFIG_SPI=y |
| 811 | # CONFIG_SPI_DEBUG is not set | ||
| 785 | CONFIG_SPI_MASTER=y | 812 | CONFIG_SPI_MASTER=y |
| 786 | 813 | ||
| 787 | # | 814 | # |
| 788 | # SPI Master Controller Drivers | 815 | # SPI Master Controller Drivers |
| 789 | # | 816 | # |
| 790 | CONFIG_SPI_BFIN=y | 817 | CONFIG_SPI_BFIN=y |
| 818 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 791 | # CONFIG_SPI_BITBANG is not set | 819 | # CONFIG_SPI_BITBANG is not set |
| 792 | 820 | ||
| 793 | # | 821 | # |
| @@ -796,11 +824,15 @@ CONFIG_SPI_BFIN=y | |||
| 796 | # CONFIG_SPI_AT25 is not set | 824 | # CONFIG_SPI_AT25 is not set |
| 797 | # CONFIG_SPI_SPIDEV is not set | 825 | # CONFIG_SPI_SPIDEV is not set |
| 798 | # CONFIG_SPI_TLE62X0 is not set | 826 | # CONFIG_SPI_TLE62X0 is not set |
| 827 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 828 | # CONFIG_GPIOLIB is not set | ||
| 799 | # CONFIG_W1 is not set | 829 | # CONFIG_W1 is not set |
| 800 | # CONFIG_POWER_SUPPLY is not set | 830 | # CONFIG_POWER_SUPPLY is not set |
| 801 | CONFIG_HWMON=y | 831 | CONFIG_HWMON=y |
| 802 | # CONFIG_HWMON_VID is not set | 832 | # CONFIG_HWMON_VID is not set |
| 833 | # CONFIG_SENSORS_AD7414 is not set | ||
| 803 | # CONFIG_SENSORS_AD7418 is not set | 834 | # CONFIG_SENSORS_AD7418 is not set |
| 835 | # CONFIG_SENSORS_ADCXX is not set | ||
| 804 | # CONFIG_SENSORS_ADM1021 is not set | 836 | # CONFIG_SENSORS_ADM1021 is not set |
| 805 | # CONFIG_SENSORS_ADM1025 is not set | 837 | # CONFIG_SENSORS_ADM1025 is not set |
| 806 | # CONFIG_SENSORS_ADM1026 is not set | 838 | # CONFIG_SENSORS_ADM1026 is not set |
| @@ -808,6 +840,7 @@ CONFIG_HWMON=y | |||
| 808 | # CONFIG_SENSORS_ADM1031 is not set | 840 | # CONFIG_SENSORS_ADM1031 is not set |
| 809 | # CONFIG_SENSORS_ADM9240 is not set | 841 | # CONFIG_SENSORS_ADM9240 is not set |
| 810 | # CONFIG_SENSORS_ADT7470 is not set | 842 | # CONFIG_SENSORS_ADT7470 is not set |
| 843 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 811 | # CONFIG_SENSORS_ATXP1 is not set | 844 | # CONFIG_SENSORS_ATXP1 is not set |
| 812 | # CONFIG_SENSORS_DS1621 is not set | 845 | # CONFIG_SENSORS_DS1621 is not set |
| 813 | # CONFIG_SENSORS_F71805F is not set | 846 | # CONFIG_SENSORS_F71805F is not set |
| @@ -828,6 +861,7 @@ CONFIG_HWMON=y | |||
| 828 | # CONFIG_SENSORS_LM90 is not set | 861 | # CONFIG_SENSORS_LM90 is not set |
| 829 | # CONFIG_SENSORS_LM92 is not set | 862 | # CONFIG_SENSORS_LM92 is not set |
| 830 | # CONFIG_SENSORS_LM93 is not set | 863 | # CONFIG_SENSORS_LM93 is not set |
| 864 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 831 | # CONFIG_SENSORS_MAX1619 is not set | 865 | # CONFIG_SENSORS_MAX1619 is not set |
| 832 | # CONFIG_SENSORS_MAX6650 is not set | 866 | # CONFIG_SENSORS_MAX6650 is not set |
| 833 | # CONFIG_SENSORS_PC87360 is not set | 867 | # CONFIG_SENSORS_PC87360 is not set |
| @@ -836,6 +870,7 @@ CONFIG_HWMON=y | |||
| 836 | # CONFIG_SENSORS_SMSC47M1 is not set | 870 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 837 | # CONFIG_SENSORS_SMSC47M192 is not set | 871 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 838 | # CONFIG_SENSORS_SMSC47B397 is not set | 872 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 873 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 839 | # CONFIG_SENSORS_THMC50 is not set | 874 | # CONFIG_SENSORS_THMC50 is not set |
| 840 | # CONFIG_SENSORS_VT1211 is not set | 875 | # CONFIG_SENSORS_VT1211 is not set |
| 841 | # CONFIG_SENSORS_W83781D is not set | 876 | # CONFIG_SENSORS_W83781D is not set |
| @@ -843,9 +878,12 @@ CONFIG_HWMON=y | |||
| 843 | # CONFIG_SENSORS_W83792D is not set | 878 | # CONFIG_SENSORS_W83792D is not set |
| 844 | # CONFIG_SENSORS_W83793 is not set | 879 | # CONFIG_SENSORS_W83793 is not set |
| 845 | # CONFIG_SENSORS_W83L785TS is not set | 880 | # CONFIG_SENSORS_W83L785TS is not set |
| 881 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 846 | # CONFIG_SENSORS_W83627HF is not set | 882 | # CONFIG_SENSORS_W83627HF is not set |
| 847 | # CONFIG_SENSORS_W83627EHF is not set | 883 | # CONFIG_SENSORS_W83627EHF is not set |
| 848 | # CONFIG_HWMON_DEBUG_CHIP is not set | 884 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 885 | # CONFIG_THERMAL is not set | ||
| 886 | # CONFIG_THERMAL_HWMON is not set | ||
| 849 | CONFIG_WATCHDOG=y | 887 | CONFIG_WATCHDOG=y |
| 850 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 888 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 851 | 889 | ||
| @@ -856,21 +894,29 @@ CONFIG_WATCHDOG=y | |||
| 856 | CONFIG_BFIN_WDT=y | 894 | CONFIG_BFIN_WDT=y |
| 857 | 895 | ||
| 858 | # | 896 | # |
| 859 | # Sonics Silicon Backplane | ||
| 860 | # | ||
| 861 | CONFIG_SSB_POSSIBLE=y | ||
| 862 | # CONFIG_SSB is not set | ||
| 863 | |||
| 864 | # | ||
| 865 | # Multifunction device drivers | 897 | # Multifunction device drivers |
| 866 | # | 898 | # |
| 899 | # CONFIG_MFD_CORE is not set | ||
| 867 | # CONFIG_MFD_SM501 is not set | 900 | # CONFIG_MFD_SM501 is not set |
| 901 | # CONFIG_HTC_PASIC3 is not set | ||
| 902 | # CONFIG_MFD_TMIO is not set | ||
| 903 | # CONFIG_MFD_WM8400 is not set | ||
| 904 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 868 | 905 | ||
| 869 | # | 906 | # |
| 870 | # Multimedia devices | 907 | # Multimedia devices |
| 871 | # | 908 | # |
| 909 | |||
| 910 | # | ||
| 911 | # Multimedia core support | ||
| 912 | # | ||
| 872 | # CONFIG_VIDEO_DEV is not set | 913 | # CONFIG_VIDEO_DEV is not set |
| 873 | # CONFIG_DVB_CORE is not set | 914 | # CONFIG_DVB_CORE is not set |
| 915 | # CONFIG_VIDEO_MEDIA is not set | ||
| 916 | |||
| 917 | # | ||
| 918 | # Multimedia drivers | ||
| 919 | # | ||
| 874 | # CONFIG_DAB is not set | 920 | # CONFIG_DAB is not set |
| 875 | 921 | ||
| 876 | # | 922 | # |
| @@ -881,6 +927,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 881 | CONFIG_FB=m | 927 | CONFIG_FB=m |
| 882 | CONFIG_FIRMWARE_EDID=y | 928 | CONFIG_FIRMWARE_EDID=y |
| 883 | # CONFIG_FB_DDC is not set | 929 | # CONFIG_FB_DDC is not set |
| 930 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 884 | CONFIG_FB_CFB_FILLRECT=m | 931 | CONFIG_FB_CFB_FILLRECT=m |
| 885 | CONFIG_FB_CFB_COPYAREA=m | 932 | CONFIG_FB_CFB_COPYAREA=m |
| 886 | CONFIG_FB_CFB_IMAGEBLIT=m | 933 | CONFIG_FB_CFB_IMAGEBLIT=m |
| @@ -888,8 +935,8 @@ CONFIG_FB_CFB_IMAGEBLIT=m | |||
| 888 | # CONFIG_FB_SYS_FILLRECT is not set | 935 | # CONFIG_FB_SYS_FILLRECT is not set |
| 889 | # CONFIG_FB_SYS_COPYAREA is not set | 936 | # CONFIG_FB_SYS_COPYAREA is not set |
| 890 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 937 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 938 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 891 | # CONFIG_FB_SYS_FOPS is not set | 939 | # CONFIG_FB_SYS_FOPS is not set |
| 892 | CONFIG_FB_DEFERRED_IO=y | ||
| 893 | # CONFIG_FB_SVGALIB is not set | 940 | # CONFIG_FB_SVGALIB is not set |
| 894 | # CONFIG_FB_MACMODES is not set | 941 | # CONFIG_FB_MACMODES is not set |
| 895 | # CONFIG_FB_BACKLIGHT is not set | 942 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -899,8 +946,12 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 899 | # | 946 | # |
| 900 | # Frame buffer hardware drivers | 947 | # Frame buffer hardware drivers |
| 901 | # | 948 | # |
| 902 | # CONFIG_FB_HITACHI_TX09 is not set | ||
| 903 | # CONFIG_FB_BFIN_T350MCQB is not set | 949 | # CONFIG_FB_BFIN_T350MCQB is not set |
| 950 | # CONFIG_FB_BFIN_LQ035Q1 is not set | ||
| 951 | CONFIG_FB_BF537_LQ035=m | ||
| 952 | CONFIG_LQ035_SLAVE_ADDR=0x58 | ||
| 953 | # CONFIG_FB_BFIN_LANDSCAPE is not set | ||
| 954 | # CONFIG_FB_BFIN_BGR is not set | ||
| 904 | CONFIG_FB_BFIN_7393=m | 955 | CONFIG_FB_BFIN_7393=m |
| 905 | CONFIG_NTSC=y | 956 | CONFIG_NTSC=y |
| 906 | # CONFIG_PAL is not set | 957 | # CONFIG_PAL is not set |
| @@ -910,15 +961,17 @@ CONFIG_NTSC=y | |||
| 910 | # CONFIG_PAL_YCBCR is not set | 961 | # CONFIG_PAL_YCBCR is not set |
| 911 | CONFIG_ADV7393_1XMEM=y | 962 | CONFIG_ADV7393_1XMEM=y |
| 912 | # CONFIG_ADV7393_2XMEM is not set | 963 | # CONFIG_ADV7393_2XMEM is not set |
| 913 | CONFIG_FB_BF537_LQ035=m | 964 | # CONFIG_FB_HITACHI_TX09 is not set |
| 914 | CONFIG_LQ035_SLAVE_ADDR=0x58 | ||
| 915 | # CONFIG_FB_BFIN_LANDSCAPE is not set | ||
| 916 | # CONFIG_FB_BFIN_BGR is not set | ||
| 917 | # CONFIG_FB_S1D13XXX is not set | 965 | # CONFIG_FB_S1D13XXX is not set |
| 918 | # CONFIG_FB_VIRTUAL is not set | 966 | # CONFIG_FB_VIRTUAL is not set |
| 967 | # CONFIG_FB_METRONOME is not set | ||
| 919 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 968 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 920 | CONFIG_LCD_CLASS_DEVICE=m | 969 | CONFIG_LCD_CLASS_DEVICE=m |
| 921 | # CONFIG_LCD_LTV350QV is not set | 970 | # CONFIG_LCD_LTV350QV is not set |
| 971 | # CONFIG_LCD_ILI9320 is not set | ||
| 972 | # CONFIG_LCD_TDO24M is not set | ||
| 973 | # CONFIG_LCD_VGG2432A4 is not set | ||
| 974 | # CONFIG_LCD_PLATFORM is not set | ||
| 922 | CONFIG_BACKLIGHT_CLASS_DEVICE=m | 975 | CONFIG_BACKLIGHT_CLASS_DEVICE=m |
| 923 | CONFIG_BACKLIGHT_CORGI=m | 976 | CONFIG_BACKLIGHT_CORGI=m |
| 924 | 977 | ||
| @@ -927,15 +980,8 @@ CONFIG_BACKLIGHT_CORGI=m | |||
| 927 | # | 980 | # |
| 928 | # CONFIG_DISPLAY_SUPPORT is not set | 981 | # CONFIG_DISPLAY_SUPPORT is not set |
| 929 | # CONFIG_LOGO is not set | 982 | # CONFIG_LOGO is not set |
| 930 | |||
| 931 | # | ||
| 932 | # Sound | ||
| 933 | # | ||
| 934 | CONFIG_SOUND=m | 983 | CONFIG_SOUND=m |
| 935 | 984 | CONFIG_SOUND_OSS_CORE=y | |
| 936 | # | ||
| 937 | # Advanced Linux Sound Architecture | ||
| 938 | # | ||
| 939 | CONFIG_SND=m | 985 | CONFIG_SND=m |
| 940 | CONFIG_SND_TIMER=m | 986 | CONFIG_SND_TIMER=m |
| 941 | CONFIG_SND_PCM=m | 987 | CONFIG_SND_PCM=m |
| @@ -949,18 +995,12 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 949 | CONFIG_SND_VERBOSE_PROCFS=y | 995 | CONFIG_SND_VERBOSE_PROCFS=y |
| 950 | # CONFIG_SND_VERBOSE_PRINTK is not set | 996 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 951 | # CONFIG_SND_DEBUG is not set | 997 | # CONFIG_SND_DEBUG is not set |
| 952 | 998 | CONFIG_SND_DRIVERS=y | |
| 953 | # | ||
| 954 | # Generic devices | ||
| 955 | # | ||
| 956 | # CONFIG_SND_DUMMY is not set | 999 | # CONFIG_SND_DUMMY is not set |
| 957 | # CONFIG_SND_MTPAV is not set | 1000 | # CONFIG_SND_MTPAV is not set |
| 958 | # CONFIG_SND_SERIAL_U16550 is not set | 1001 | # CONFIG_SND_SERIAL_U16550 is not set |
| 959 | # CONFIG_SND_MPU401 is not set | 1002 | # CONFIG_SND_MPU401 is not set |
| 960 | 1003 | CONFIG_SND_SPI=y | |
| 961 | # | ||
| 962 | # SPI devices | ||
| 963 | # | ||
| 964 | 1004 | ||
| 965 | # | 1005 | # |
| 966 | # ALSA Blackfin devices | 1006 | # ALSA Blackfin devices |
| @@ -972,51 +1012,46 @@ CONFIG_SND_BLACKFIN_AD1836_MULSUB=y | |||
| 972 | # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set | 1012 | # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set |
| 973 | CONFIG_SND_BLACKFIN_SPORT=0 | 1013 | CONFIG_SND_BLACKFIN_SPORT=0 |
| 974 | CONFIG_SND_BLACKFIN_SPI_PFBIT=4 | 1014 | CONFIG_SND_BLACKFIN_SPI_PFBIT=4 |
| 975 | CONFIG_SND_BFIN_AD73311=m | ||
| 976 | CONFIG_SND_BFIN_SPORT=0 | 1015 | CONFIG_SND_BFIN_SPORT=0 |
| 977 | CONFIG_SND_BFIN_AD73311_SE=4 | ||
| 978 | CONFIG_SND_BFIN_AD73322=m | 1016 | CONFIG_SND_BFIN_AD73322=m |
| 979 | CONFIG_SND_BFIN_AD73322_SPORT0_SE=10 | 1017 | CONFIG_SND_BFIN_AD73322_SPORT0_SE=10 |
| 980 | CONFIG_SND_BFIN_AD73322_SPORT1_SE=14 | 1018 | CONFIG_SND_BFIN_AD73322_SPORT1_SE=14 |
| 981 | CONFIG_SND_BFIN_AD73322_RESET=12 | 1019 | CONFIG_SND_BFIN_AD73322_RESET=12 |
| 982 | |||
| 983 | # | ||
| 984 | # System on Chip audio support | ||
| 985 | # | ||
| 986 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 987 | CONFIG_SND_SOC=m | 1020 | CONFIG_SND_SOC=m |
| 988 | CONFIG_SND_BF5XX_SOC=m | 1021 | CONFIG_SND_SOC_AC97_BUS=y |
| 989 | CONFIG_SND_MMAP_SUPPORT=y | 1022 | CONFIG_SND_BF5XX_I2S=m |
| 990 | CONFIG_SND_BF5XX_SOC_AC97=m | ||
| 991 | # CONFIG_SND_BF5XX_SOC_WM8750 is not set | ||
| 992 | # CONFIG_SND_BF5XX_SOC_WM8731 is not set | ||
| 993 | # CONFIG_SND_BF5XX_SOC_SSM2602 is not set | 1023 | # CONFIG_SND_BF5XX_SOC_SSM2602 is not set |
| 994 | CONFIG_SND_BF5XX_SOC_BF5xx=m | 1024 | CONFIG_SND_BF5XX_SOC_AD73311=m |
| 1025 | CONFIG_SND_BFIN_AD73311_SE=4 | ||
| 1026 | CONFIG_SND_BF5XX_AC97=m | ||
| 1027 | CONFIG_SND_BF5XX_MMAP_SUPPORT=y | ||
| 1028 | # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set | ||
| 1029 | CONFIG_SND_BF5XX_SOC_SPORT=m | ||
| 1030 | CONFIG_SND_BF5XX_SOC_I2S=m | ||
| 1031 | CONFIG_SND_BF5XX_SOC_AC97=m | ||
| 1032 | CONFIG_SND_BF5XX_SOC_AD1980=m | ||
| 995 | CONFIG_SND_BF5XX_SPORT_NUM=0 | 1033 | CONFIG_SND_BF5XX_SPORT_NUM=0 |
| 996 | # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set | 1034 | # CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set |
| 997 | 1035 | # CONFIG_SND_SOC_ALL_CODECS is not set | |
| 998 | # | ||
| 999 | # SoC Audio support for SuperH | ||
| 1000 | # | ||
| 1001 | CONFIG_SND_SOC_AD1980=m | 1036 | CONFIG_SND_SOC_AD1980=m |
| 1002 | 1037 | CONFIG_SND_SOC_AD73311=m | |
| 1003 | # | ||
| 1004 | # Open Sound System | ||
| 1005 | # | ||
| 1006 | # CONFIG_SOUND_PRIME is not set | 1038 | # CONFIG_SOUND_PRIME is not set |
| 1007 | CONFIG_AC97_BUS=m | 1039 | CONFIG_AC97_BUS=m |
| 1008 | CONFIG_HID_SUPPORT=y | 1040 | CONFIG_HID_SUPPORT=y |
| 1009 | CONFIG_HID=y | 1041 | CONFIG_HID=y |
| 1010 | # CONFIG_HID_DEBUG is not set | 1042 | # CONFIG_HID_DEBUG is not set |
| 1011 | # CONFIG_HIDRAW is not set | 1043 | # CONFIG_HIDRAW is not set |
| 1044 | # CONFIG_HID_PID is not set | ||
| 1045 | |||
| 1046 | # | ||
| 1047 | # Special HID drivers | ||
| 1048 | # | ||
| 1049 | CONFIG_HID_COMPAT=y | ||
| 1012 | # CONFIG_USB_SUPPORT is not set | 1050 | # CONFIG_USB_SUPPORT is not set |
| 1013 | # CONFIG_NO_DUMMY_DELAY is not set | ||
| 1014 | # CONFIG_DUMMY_DELAY_BANK0 is not set | ||
| 1015 | # CONFIG_DUMMY_DELAY_BANK1 is not set | ||
| 1016 | # CONFIG_DUMMY_DELAY_BANK2 is not set | ||
| 1017 | # CONFIG_DUMMY_DELAY_BANK3 is not set | ||
| 1018 | # CONFIG_MMC is not set | 1051 | # CONFIG_MMC is not set |
| 1052 | # CONFIG_MEMSTICK is not set | ||
| 1019 | # CONFIG_NEW_LEDS is not set | 1053 | # CONFIG_NEW_LEDS is not set |
| 1054 | # CONFIG_ACCESSIBILITY is not set | ||
| 1020 | CONFIG_RTC_LIB=y | 1055 | CONFIG_RTC_LIB=y |
| 1021 | CONFIG_RTC_CLASS=y | 1056 | CONFIG_RTC_CLASS=y |
| 1022 | CONFIG_RTC_HCTOSYS=y | 1057 | CONFIG_RTC_HCTOSYS=y |
| @@ -1045,51 +1080,57 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1045 | # CONFIG_RTC_DRV_PCF8563 is not set | 1080 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1046 | # CONFIG_RTC_DRV_PCF8583 is not set | 1081 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1047 | # CONFIG_RTC_DRV_M41T80 is not set | 1082 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1083 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1084 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1048 | 1085 | ||
| 1049 | # | 1086 | # |
| 1050 | # SPI RTC drivers | 1087 | # SPI RTC drivers |
| 1051 | # | 1088 | # |
| 1052 | # CONFIG_RTC_DRV_RS5C348 is not set | 1089 | # CONFIG_RTC_DRV_M41T94 is not set |
| 1090 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1053 | # CONFIG_RTC_DRV_MAX6902 is not set | 1091 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 1092 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1093 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1094 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1054 | 1095 | ||
| 1055 | # | 1096 | # |
| 1056 | # Platform RTC drivers | 1097 | # Platform RTC drivers |
| 1057 | # | 1098 | # |
| 1099 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1100 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1058 | # CONFIG_RTC_DRV_DS1553 is not set | 1101 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1059 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1060 | # CONFIG_RTC_DRV_DS1742 is not set | 1102 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1103 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1061 | # CONFIG_RTC_DRV_M48T86 is not set | 1104 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1105 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1062 | # CONFIG_RTC_DRV_M48T59 is not set | 1106 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1107 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1063 | # CONFIG_RTC_DRV_V3020 is not set | 1108 | # CONFIG_RTC_DRV_V3020 is not set |
| 1064 | 1109 | ||
| 1065 | # | 1110 | # |
| 1066 | # on-CPU RTC drivers | 1111 | # on-CPU RTC drivers |
| 1067 | # | 1112 | # |
| 1068 | CONFIG_RTC_DRV_BFIN=y | 1113 | CONFIG_RTC_DRV_BFIN=y |
| 1069 | 1114 | # CONFIG_DMADEVICES is not set | |
| 1070 | # | ||
| 1071 | # Userspace I/O | ||
| 1072 | # | ||
| 1073 | # CONFIG_UIO is not set | 1115 | # CONFIG_UIO is not set |
| 1116 | # CONFIG_STAGING is not set | ||
| 1074 | 1117 | ||
| 1075 | # | 1118 | # |
| 1076 | # File systems | 1119 | # File systems |
| 1077 | # | 1120 | # |
| 1078 | # CONFIG_EXT2_FS is not set | 1121 | # CONFIG_EXT2_FS is not set |
| 1079 | # CONFIG_EXT3_FS is not set | 1122 | # CONFIG_EXT3_FS is not set |
| 1080 | # CONFIG_EXT4DEV_FS is not set | 1123 | # CONFIG_EXT4_FS is not set |
| 1081 | # CONFIG_REISERFS_FS is not set | 1124 | # CONFIG_REISERFS_FS is not set |
| 1082 | # CONFIG_JFS_FS is not set | 1125 | # CONFIG_JFS_FS is not set |
| 1083 | # CONFIG_FS_POSIX_ACL is not set | 1126 | # CONFIG_FS_POSIX_ACL is not set |
| 1127 | CONFIG_FILE_LOCKING=y | ||
| 1084 | # CONFIG_XFS_FS is not set | 1128 | # CONFIG_XFS_FS is not set |
| 1085 | # CONFIG_GFS2_FS is not set | ||
| 1086 | # CONFIG_OCFS2_FS is not set | 1129 | # CONFIG_OCFS2_FS is not set |
| 1087 | # CONFIG_MINIX_FS is not set | 1130 | # CONFIG_DNOTIFY is not set |
| 1088 | # CONFIG_ROMFS_FS is not set | ||
| 1089 | CONFIG_INOTIFY=y | 1131 | CONFIG_INOTIFY=y |
| 1090 | CONFIG_INOTIFY_USER=y | 1132 | CONFIG_INOTIFY_USER=y |
| 1091 | # CONFIG_QUOTA is not set | 1133 | # CONFIG_QUOTA is not set |
| 1092 | # CONFIG_DNOTIFY is not set | ||
| 1093 | # CONFIG_AUTOFS_FS is not set | 1134 | # CONFIG_AUTOFS_FS is not set |
| 1094 | # CONFIG_AUTOFS4_FS is not set | 1135 | # CONFIG_AUTOFS4_FS is not set |
| 1095 | # CONFIG_FUSE_FS is not set | 1136 | # CONFIG_FUSE_FS is not set |
| @@ -1129,11 +1170,11 @@ CONFIG_SYSFS=y | |||
| 1129 | # CONFIG_EFS_FS is not set | 1170 | # CONFIG_EFS_FS is not set |
| 1130 | CONFIG_YAFFS_FS=m | 1171 | CONFIG_YAFFS_FS=m |
| 1131 | CONFIG_YAFFS_YAFFS1=y | 1172 | CONFIG_YAFFS_YAFFS1=y |
| 1173 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1132 | # CONFIG_YAFFS_DOES_ECC is not set | 1174 | # CONFIG_YAFFS_DOES_ECC is not set |
| 1133 | CONFIG_YAFFS_YAFFS2=y | 1175 | CONFIG_YAFFS_YAFFS2=y |
| 1134 | CONFIG_YAFFS_AUTO_YAFFS2=y | 1176 | CONFIG_YAFFS_AUTO_YAFFS2=y |
| 1135 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | 1177 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set |
| 1136 | CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 | ||
| 1137 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | 1178 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 1138 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | 1179 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 1139 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | 1180 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| @@ -1150,8 +1191,11 @@ CONFIG_JFFS2_RTIME=y | |||
| 1150 | # CONFIG_JFFS2_RUBIN is not set | 1191 | # CONFIG_JFFS2_RUBIN is not set |
| 1151 | # CONFIG_CRAMFS is not set | 1192 | # CONFIG_CRAMFS is not set |
| 1152 | # CONFIG_VXFS_FS is not set | 1193 | # CONFIG_VXFS_FS is not set |
| 1194 | # CONFIG_MINIX_FS is not set | ||
| 1195 | # CONFIG_OMFS_FS is not set | ||
| 1153 | # CONFIG_HPFS_FS is not set | 1196 | # CONFIG_HPFS_FS is not set |
| 1154 | # CONFIG_QNX4FS_FS is not set | 1197 | # CONFIG_QNX4FS_FS is not set |
| 1198 | # CONFIG_ROMFS_FS is not set | ||
| 1155 | # CONFIG_SYSV_FS is not set | 1199 | # CONFIG_SYSV_FS is not set |
| 1156 | # CONFIG_UFS_FS is not set | 1200 | # CONFIG_UFS_FS is not set |
| 1157 | CONFIG_NETWORK_FILESYSTEMS=y | 1201 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1159,13 +1203,12 @@ CONFIG_NFS_FS=m | |||
| 1159 | CONFIG_NFS_V3=y | 1203 | CONFIG_NFS_V3=y |
| 1160 | # CONFIG_NFS_V3_ACL is not set | 1204 | # CONFIG_NFS_V3_ACL is not set |
| 1161 | # CONFIG_NFS_V4 is not set | 1205 | # CONFIG_NFS_V4 is not set |
| 1162 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1163 | # CONFIG_NFSD is not set | 1206 | # CONFIG_NFSD is not set |
| 1164 | CONFIG_LOCKD=m | 1207 | CONFIG_LOCKD=m |
| 1165 | CONFIG_LOCKD_V4=y | 1208 | CONFIG_LOCKD_V4=y |
| 1166 | CONFIG_NFS_COMMON=y | 1209 | CONFIG_NFS_COMMON=y |
| 1167 | CONFIG_SUNRPC=m | 1210 | CONFIG_SUNRPC=m |
| 1168 | # CONFIG_SUNRPC_BIND34 is not set | 1211 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1169 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1212 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1170 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1213 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1171 | CONFIG_SMB_FS=m | 1214 | CONFIG_SMB_FS=m |
| @@ -1221,9 +1264,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1221 | # CONFIG_NLS_KOI8_U is not set | 1264 | # CONFIG_NLS_KOI8_U is not set |
| 1222 | # CONFIG_NLS_UTF8 is not set | 1265 | # CONFIG_NLS_UTF8 is not set |
| 1223 | # CONFIG_DLM is not set | 1266 | # CONFIG_DLM is not set |
| 1224 | CONFIG_INSTRUMENTATION=y | ||
| 1225 | # CONFIG_PROFILING is not set | ||
| 1226 | # CONFIG_MARKERS is not set | ||
| 1227 | 1267 | ||
| 1228 | # | 1268 | # |
| 1229 | # Kernel hacking | 1269 | # Kernel hacking |
| @@ -1231,14 +1271,53 @@ CONFIG_INSTRUMENTATION=y | |||
| 1231 | # CONFIG_PRINTK_TIME is not set | 1271 | # CONFIG_PRINTK_TIME is not set |
| 1232 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1272 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1233 | CONFIG_ENABLE_MUST_CHECK=y | 1273 | CONFIG_ENABLE_MUST_CHECK=y |
| 1274 | CONFIG_FRAME_WARN=1024 | ||
| 1234 | # CONFIG_MAGIC_SYSRQ is not set | 1275 | # CONFIG_MAGIC_SYSRQ is not set |
| 1235 | # CONFIG_UNUSED_SYMBOLS is not set | 1276 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1236 | CONFIG_DEBUG_FS=y | 1277 | CONFIG_DEBUG_FS=y |
| 1237 | # CONFIG_HEADERS_CHECK is not set | 1278 | # CONFIG_HEADERS_CHECK is not set |
| 1238 | # CONFIG_DEBUG_KERNEL is not set | 1279 | CONFIG_DEBUG_KERNEL=y |
| 1280 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1281 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1282 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1283 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1284 | CONFIG_SCHED_DEBUG=y | ||
| 1285 | # CONFIG_SCHEDSTATS is not set | ||
| 1286 | # CONFIG_TIMER_STATS is not set | ||
| 1287 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1288 | # CONFIG_DEBUG_SLAB is not set | ||
| 1289 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1290 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1291 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1292 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1293 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1294 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1295 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1239 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1296 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1297 | CONFIG_DEBUG_INFO=y | ||
| 1298 | # CONFIG_DEBUG_VM is not set | ||
| 1299 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1300 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1301 | # CONFIG_DEBUG_LIST is not set | ||
| 1302 | # CONFIG_DEBUG_SG is not set | ||
| 1303 | # CONFIG_FRAME_POINTER is not set | ||
| 1304 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1305 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1306 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1307 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1308 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1309 | # CONFIG_FAULT_INJECTION is not set | ||
| 1310 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1311 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1240 | # CONFIG_SAMPLES is not set | 1312 | # CONFIG_SAMPLES is not set |
| 1313 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1314 | # CONFIG_KGDB is not set | ||
| 1315 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1316 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1317 | CONFIG_DEBUG_VERBOSE=y | ||
| 1241 | CONFIG_DEBUG_MMRS=y | 1318 | CONFIG_DEBUG_MMRS=y |
| 1319 | # CONFIG_DEBUG_HWERR is not set | ||
| 1320 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 1242 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1321 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1243 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1322 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1244 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1323 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -1256,9 +1335,94 @@ CONFIG_ACCESS_CHECK=y | |||
| 1256 | # | 1335 | # |
| 1257 | # CONFIG_KEYS is not set | 1336 | # CONFIG_KEYS is not set |
| 1258 | CONFIG_SECURITY=y | 1337 | CONFIG_SECURITY=y |
| 1338 | # CONFIG_SECURITYFS is not set | ||
| 1259 | # CONFIG_SECURITY_NETWORK is not set | 1339 | # CONFIG_SECURITY_NETWORK is not set |
| 1260 | # CONFIG_SECURITY_CAPABILITIES is not set | 1340 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1261 | # CONFIG_CRYPTO is not set | 1341 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 |
| 1342 | CONFIG_CRYPTO=y | ||
| 1343 | |||
| 1344 | # | ||
| 1345 | # Crypto core or helper | ||
| 1346 | # | ||
| 1347 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1348 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1349 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1350 | # CONFIG_CRYPTO_NULL is not set | ||
| 1351 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1352 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1353 | # CONFIG_CRYPTO_TEST is not set | ||
| 1354 | |||
| 1355 | # | ||
| 1356 | # Authenticated Encryption with Associated Data | ||
| 1357 | # | ||
| 1358 | # CONFIG_CRYPTO_CCM is not set | ||
| 1359 | # CONFIG_CRYPTO_GCM is not set | ||
| 1360 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1361 | |||
| 1362 | # | ||
| 1363 | # Block modes | ||
| 1364 | # | ||
| 1365 | # CONFIG_CRYPTO_CBC is not set | ||
| 1366 | # CONFIG_CRYPTO_CTR is not set | ||
| 1367 | # CONFIG_CRYPTO_CTS is not set | ||
| 1368 | # CONFIG_CRYPTO_ECB is not set | ||
| 1369 | # CONFIG_CRYPTO_LRW is not set | ||
| 1370 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1371 | # CONFIG_CRYPTO_XTS is not set | ||
| 1372 | |||
| 1373 | # | ||
| 1374 | # Hash modes | ||
| 1375 | # | ||
| 1376 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1377 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1378 | |||
| 1379 | # | ||
| 1380 | # Digest | ||
| 1381 | # | ||
| 1382 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1383 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1384 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1385 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1386 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1387 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1388 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1389 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1390 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1391 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1392 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1393 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1394 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1395 | |||
| 1396 | # | ||
| 1397 | # Ciphers | ||
| 1398 | # | ||
| 1399 | # CONFIG_CRYPTO_AES is not set | ||
| 1400 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1401 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1402 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1403 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1404 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1405 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1406 | # CONFIG_CRYPTO_DES is not set | ||
| 1407 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1408 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1409 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1410 | # CONFIG_CRYPTO_SEED is not set | ||
| 1411 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1412 | # CONFIG_CRYPTO_TEA is not set | ||
| 1413 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1414 | |||
| 1415 | # | ||
| 1416 | # Compression | ||
| 1417 | # | ||
| 1418 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1419 | # CONFIG_CRYPTO_LZO is not set | ||
| 1420 | |||
| 1421 | # | ||
| 1422 | # Random Number Generation | ||
| 1423 | # | ||
| 1424 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1425 | CONFIG_CRYPTO_HW=y | ||
| 1262 | 1426 | ||
| 1263 | # | 1427 | # |
| 1264 | # Library routines | 1428 | # Library routines |
| @@ -1266,6 +1430,7 @@ CONFIG_SECURITY=y | |||
| 1266 | CONFIG_BITREVERSE=y | 1430 | CONFIG_BITREVERSE=y |
| 1267 | CONFIG_CRC_CCITT=m | 1431 | CONFIG_CRC_CCITT=m |
| 1268 | # CONFIG_CRC16 is not set | 1432 | # CONFIG_CRC16 is not set |
| 1433 | # CONFIG_CRC_T10DIF is not set | ||
| 1269 | # CONFIG_CRC_ITU_T is not set | 1434 | # CONFIG_CRC_ITU_T is not set |
| 1270 | CONFIG_CRC32=y | 1435 | CONFIG_CRC32=y |
| 1271 | # CONFIG_CRC7 is not set | 1436 | # CONFIG_CRC7 is not set |
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig new file mode 100644 index 000000000000..ed15934c67c2 --- /dev/null +++ b/arch/blackfin/configs/BF538-EZKIT_defconfig | |||
| @@ -0,0 +1,1368 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.28-rc2 | ||
| 4 | # | ||
| 5 | # CONFIG_MMU is not set | ||
| 6 | # CONFIG_FPU is not set | ||
| 7 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | ||
| 9 | CONFIG_BLACKFIN=y | ||
| 10 | CONFIG_ZONE_DMA=y | ||
| 11 | CONFIG_GENERIC_FIND_NEXT_BIT=y | ||
| 12 | CONFIG_GENERIC_HWEIGHT=y | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 15 | CONFIG_GENERIC_GPIO=y | ||
| 16 | CONFIG_FORCE_MAX_ZONEORDER=14 | ||
| 17 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 18 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 19 | |||
| 20 | # | ||
| 21 | # General setup | ||
| 22 | # | ||
| 23 | CONFIG_EXPERIMENTAL=y | ||
| 24 | CONFIG_BROKEN_ON_SMP=y | ||
| 25 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 26 | CONFIG_LOCALVERSION="" | ||
| 27 | CONFIG_LOCALVERSION_AUTO=y | ||
| 28 | CONFIG_SYSVIPC=y | ||
| 29 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 30 | # CONFIG_POSIX_MQUEUE is not set | ||
| 31 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 32 | # CONFIG_TASKSTATS is not set | ||
| 33 | # CONFIG_AUDIT is not set | ||
| 34 | CONFIG_IKCONFIG=y | ||
| 35 | CONFIG_IKCONFIG_PROC=y | ||
| 36 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 37 | # CONFIG_CGROUPS is not set | ||
| 38 | # CONFIG_GROUP_SCHED is not set | ||
| 39 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 40 | # CONFIG_RELAY is not set | ||
| 41 | # CONFIG_NAMESPACES is not set | ||
| 42 | CONFIG_BLK_DEV_INITRD=y | ||
| 43 | CONFIG_INITRAMFS_SOURCE="" | ||
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 45 | CONFIG_SYSCTL=y | ||
| 46 | CONFIG_EMBEDDED=y | ||
| 47 | CONFIG_UID16=y | ||
| 48 | CONFIG_SYSCTL_SYSCALL=y | ||
| 49 | CONFIG_KALLSYMS=y | ||
| 50 | # CONFIG_KALLSYMS_ALL is not set | ||
| 51 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 52 | CONFIG_HOTPLUG=y | ||
| 53 | CONFIG_PRINTK=y | ||
| 54 | CONFIG_BUG=y | ||
| 55 | # CONFIG_ELF_CORE is not set | ||
| 56 | CONFIG_COMPAT_BRK=y | ||
| 57 | CONFIG_BASE_FULL=y | ||
| 58 | CONFIG_FUTEX=y | ||
| 59 | CONFIG_ANON_INODES=y | ||
| 60 | CONFIG_EPOLL=y | ||
| 61 | CONFIG_SIGNALFD=y | ||
| 62 | CONFIG_TIMERFD=y | ||
| 63 | CONFIG_EVENTFD=y | ||
| 64 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 66 | CONFIG_SLAB=y | ||
| 67 | # CONFIG_SLUB is not set | ||
| 68 | # CONFIG_SLOB is not set | ||
| 69 | # CONFIG_PROFILING is not set | ||
| 70 | # CONFIG_MARKERS is not set | ||
| 71 | CONFIG_HAVE_OPROFILE=y | ||
| 72 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 73 | CONFIG_SLABINFO=y | ||
| 74 | CONFIG_RT_MUTEXES=y | ||
| 75 | CONFIG_TINY_SHMEM=y | ||
| 76 | CONFIG_BASE_SMALL=0 | ||
| 77 | CONFIG_MODULES=y | ||
| 78 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 79 | CONFIG_MODULE_UNLOAD=y | ||
| 80 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 81 | # CONFIG_MODVERSIONS is not set | ||
| 82 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 83 | CONFIG_KMOD=y | ||
| 84 | CONFIG_BLOCK=y | ||
| 85 | # CONFIG_LBD is not set | ||
| 86 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 87 | # CONFIG_LSF is not set | ||
| 88 | # CONFIG_BLK_DEV_BSG is not set | ||
| 89 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 90 | |||
| 91 | # | ||
| 92 | # IO Schedulers | ||
| 93 | # | ||
| 94 | CONFIG_IOSCHED_NOOP=y | ||
| 95 | CONFIG_IOSCHED_AS=y | ||
| 96 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 97 | CONFIG_IOSCHED_CFQ=y | ||
| 98 | CONFIG_DEFAULT_AS=y | ||
| 99 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 100 | # CONFIG_DEFAULT_CFQ is not set | ||
| 101 | # CONFIG_DEFAULT_NOOP is not set | ||
| 102 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 103 | CONFIG_CLASSIC_RCU=y | ||
| 104 | # CONFIG_PREEMPT_NONE is not set | ||
| 105 | CONFIG_PREEMPT_VOLUNTARY=y | ||
| 106 | # CONFIG_PREEMPT is not set | ||
| 107 | # CONFIG_FREEZER is not set | ||
| 108 | |||
| 109 | # | ||
| 110 | # Blackfin Processor Options | ||
| 111 | # | ||
| 112 | |||
| 113 | # | ||
| 114 | # Processor and Board Settings | ||
| 115 | # | ||
| 116 | # CONFIG_BF512 is not set | ||
| 117 | # CONFIG_BF514 is not set | ||
| 118 | # CONFIG_BF516 is not set | ||
| 119 | # CONFIG_BF518 is not set | ||
| 120 | # CONFIG_BF522 is not set | ||
| 121 | # CONFIG_BF523 is not set | ||
| 122 | # CONFIG_BF524 is not set | ||
| 123 | # CONFIG_BF525 is not set | ||
| 124 | # CONFIG_BF526 is not set | ||
| 125 | # CONFIG_BF527 is not set | ||
| 126 | # CONFIG_BF531 is not set | ||
| 127 | # CONFIG_BF532 is not set | ||
| 128 | # CONFIG_BF533 is not set | ||
| 129 | # CONFIG_BF534 is not set | ||
| 130 | # CONFIG_BF536 is not set | ||
| 131 | # CONFIG_BF537 is not set | ||
| 132 | CONFIG_BF538=y | ||
| 133 | # CONFIG_BF539 is not set | ||
| 134 | # CONFIG_BF542 is not set | ||
| 135 | # CONFIG_BF544 is not set | ||
| 136 | # CONFIG_BF547 is not set | ||
| 137 | # CONFIG_BF548 is not set | ||
| 138 | # CONFIG_BF549 is not set | ||
| 139 | # CONFIG_BF561 is not set | ||
| 140 | CONFIG_BF_REV_MIN=4 | ||
| 141 | CONFIG_BF_REV_MAX=5 | ||
| 142 | # CONFIG_BF_REV_0_0 is not set | ||
| 143 | # CONFIG_BF_REV_0_1 is not set | ||
| 144 | # CONFIG_BF_REV_0_2 is not set | ||
| 145 | # CONFIG_BF_REV_0_3 is not set | ||
| 146 | CONFIG_BF_REV_0_4=y | ||
| 147 | # CONFIG_BF_REV_0_5 is not set | ||
| 148 | # CONFIG_BF_REV_0_6 is not set | ||
| 149 | # CONFIG_BF_REV_ANY is not set | ||
| 150 | # CONFIG_BF_REV_NONE is not set | ||
| 151 | CONFIG_MEM_MT48LC32M8A2_75=y | ||
| 152 | CONFIG_IRQ_PLL_WAKEUP=7 | ||
| 153 | CONFIG_IRQ_DMA0_ERROR=7 | ||
| 154 | CONFIG_IRQ_PPI_ERROR=7 | ||
| 155 | CONFIG_IRQ_SPORT0_ERROR=7 | ||
| 156 | CONFIG_IRQ_SPORT1_ERROR=7 | ||
| 157 | CONFIG_IRQ_UART0_ERROR=7 | ||
| 158 | CONFIG_IRQ_UART1_ERROR=7 | ||
| 159 | CONFIG_IRQ_RTC=8 | ||
| 160 | CONFIG_IRQ_PPI=8 | ||
| 161 | CONFIG_IRQ_SPORT0_RX=9 | ||
| 162 | CONFIG_IRQ_SPORT0_TX=9 | ||
| 163 | CONFIG_IRQ_SPORT1_RX=9 | ||
| 164 | CONFIG_IRQ_SPORT1_TX=9 | ||
| 165 | CONFIG_IRQ_SPI0=10 | ||
| 166 | CONFIG_IRQ_UART0_RX=10 | ||
| 167 | CONFIG_IRQ_UART0_TX=10 | ||
| 168 | CONFIG_IRQ_UART1_RX=10 | ||
| 169 | CONFIG_IRQ_UART1_TX=10 | ||
| 170 | CONFIG_IRQ_TIMER0=12 | ||
| 171 | CONFIG_IRQ_TIMER1=12 | ||
| 172 | CONFIG_IRQ_TIMER2=12 | ||
| 173 | CONFIG_IRQ_WATCH=13 | ||
| 174 | CONFIG_IRQ_PORTF_INTA=12 | ||
| 175 | CONFIG_IRQ_PORTF_INTB=12 | ||
| 176 | CONFIG_IRQ_SPI0_ERROR=7 | ||
| 177 | CONFIG_IRQ_SPI1_ERROR=7 | ||
| 178 | CONFIG_IRQ_DMA1_ERROR=7 | ||
| 179 | CONFIG_IRQ_CAN_RX=11 | ||
| 180 | CONFIG_IRQ_CAN_TX=11 | ||
| 181 | CONFIG_BFIN538_EZKIT=y | ||
| 182 | |||
| 183 | # | ||
| 184 | # BF538 Specific Configuration | ||
| 185 | # | ||
| 186 | |||
| 187 | # | ||
| 188 | # Interrupt Priority Assignment | ||
| 189 | # | ||
| 190 | |||
| 191 | # | ||
| 192 | # Priority | ||
| 193 | # | ||
| 194 | CONFIG_IRQ_MEM0_DMA0=13 | ||
| 195 | CONFIG_IRQ_MEM0_DMA1=13 | ||
| 196 | CONFIG_IRQ_SPORT2_ERROR=7 | ||
| 197 | CONFIG_IRQ_SPORT3_ERROR=7 | ||
| 198 | CONFIG_IRQ_SPI2_ERROR=7 | ||
| 199 | CONFIG_IRQ_UART2_ERROR=7 | ||
| 200 | CONFIG_IRQ_CAN_ERROR=7 | ||
| 201 | CONFIG_IRQ_SPORT2_RX=9 | ||
| 202 | CONFIG_IRQ_SPORT2_TX=9 | ||
| 203 | CONFIG_IRQ_SPORT3_RX=9 | ||
| 204 | CONFIG_IRQ_SPORT3_TX=9 | ||
| 205 | CONFIG_IRQ_SPI1=10 | ||
| 206 | CONFIG_IRQ_SPI2=10 | ||
| 207 | CONFIG_IRQ_UART2_RX=10 | ||
| 208 | CONFIG_IRQ_UART2_TX=10 | ||
| 209 | CONFIG_IRQ_TWI0=11 | ||
| 210 | CONFIG_IRQ_TWI1=11 | ||
| 211 | CONFIG_IRQ_MEM1_DMA0=13 | ||
| 212 | CONFIG_IRQ_MEM1_DMA1=13 | ||
| 213 | |||
| 214 | # | ||
| 215 | # Board customizations | ||
| 216 | # | ||
| 217 | # CONFIG_CMDLINE_BOOL is not set | ||
| 218 | CONFIG_BOOT_LOAD=0x1000 | ||
| 219 | |||
| 220 | # | ||
| 221 | # Clock/PLL Setup | ||
| 222 | # | ||
| 223 | CONFIG_CLKIN_HZ=25000000 | ||
| 224 | # CONFIG_BFIN_KERNEL_CLOCK is not set | ||
| 225 | CONFIG_MAX_VCO_HZ=533333333 | ||
| 226 | CONFIG_MIN_VCO_HZ=50000000 | ||
| 227 | CONFIG_MAX_SCLK_HZ=133333333 | ||
| 228 | CONFIG_MIN_SCLK_HZ=27000000 | ||
| 229 | |||
| 230 | # | ||
| 231 | # Kernel Timer/Scheduler | ||
| 232 | # | ||
| 233 | # CONFIG_HZ_100 is not set | ||
| 234 | CONFIG_HZ_250=y | ||
| 235 | # CONFIG_HZ_300 is not set | ||
| 236 | # CONFIG_HZ_1000 is not set | ||
| 237 | CONFIG_HZ=250 | ||
| 238 | CONFIG_SCHED_HRTICK=y | ||
| 239 | CONFIG_GENERIC_TIME=y | ||
| 240 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 241 | # CONFIG_CYCLES_CLOCKSOURCE is not set | ||
| 242 | CONFIG_TICK_ONESHOT=y | ||
| 243 | # CONFIG_NO_HZ is not set | ||
| 244 | CONFIG_HIGH_RES_TIMERS=y | ||
| 245 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 246 | |||
| 247 | # | ||
| 248 | # Misc | ||
| 249 | # | ||
| 250 | CONFIG_BFIN_SCRATCH_REG_RETN=y | ||
| 251 | # CONFIG_BFIN_SCRATCH_REG_RETE is not set | ||
| 252 | # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set | ||
| 253 | |||
| 254 | # | ||
| 255 | # Blackfin Kernel Optimizations | ||
| 256 | # | ||
| 257 | |||
| 258 | # | ||
| 259 | # Memory Optimizations | ||
| 260 | # | ||
| 261 | CONFIG_I_ENTRY_L1=y | ||
| 262 | CONFIG_EXCPT_IRQ_SYSC_L1=y | ||
| 263 | CONFIG_DO_IRQ_L1=y | ||
| 264 | CONFIG_CORE_TIMER_IRQ_L1=y | ||
| 265 | CONFIG_IDLE_L1=y | ||
| 266 | CONFIG_SCHEDULE_L1=y | ||
| 267 | CONFIG_ARITHMETIC_OPS_L1=y | ||
| 268 | CONFIG_ACCESS_OK_L1=y | ||
| 269 | CONFIG_MEMSET_L1=y | ||
| 270 | CONFIG_MEMCPY_L1=y | ||
| 271 | CONFIG_SYS_BFIN_SPINLOCK_L1=y | ||
| 272 | # CONFIG_IP_CHECKSUM_L1 is not set | ||
| 273 | CONFIG_CACHELINE_ALIGNED_L1=y | ||
| 274 | # CONFIG_SYSCALL_TAB_L1 is not set | ||
| 275 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | ||
| 276 | CONFIG_APP_STACK_L1=y | ||
| 277 | |||
| 278 | # | ||
| 279 | # Speed Optimizations | ||
| 280 | # | ||
| 281 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 282 | CONFIG_RAMKERNEL=y | ||
| 283 | # CONFIG_ROMKERNEL is not set | ||
| 284 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 285 | CONFIG_FLATMEM_MANUAL=y | ||
| 286 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 287 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 288 | CONFIG_FLATMEM=y | ||
| 289 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 290 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 291 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 292 | # CONFIG_RESOURCES_64BIT is not set | ||
| 293 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 294 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 295 | CONFIG_VIRT_TO_BUS=y | ||
| 296 | CONFIG_BFIN_GPTIMERS=y | ||
| 297 | # CONFIG_DMA_UNCACHED_4M is not set | ||
| 298 | # CONFIG_DMA_UNCACHED_2M is not set | ||
| 299 | CONFIG_DMA_UNCACHED_1M=y | ||
| 300 | # CONFIG_DMA_UNCACHED_NONE is not set | ||
| 301 | |||
| 302 | # | ||
| 303 | # Cache Support | ||
| 304 | # | ||
| 305 | CONFIG_BFIN_ICACHE=y | ||
| 306 | CONFIG_BFIN_DCACHE=y | ||
| 307 | # CONFIG_BFIN_DCACHE_BANKA is not set | ||
| 308 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 309 | # CONFIG_BFIN_WB is not set | ||
| 310 | CONFIG_BFIN_WT=y | ||
| 311 | # CONFIG_MPU is not set | ||
| 312 | |||
| 313 | # | ||
| 314 | # Asynchonous Memory Configuration | ||
| 315 | # | ||
| 316 | |||
| 317 | # | ||
| 318 | # EBIU_AMGCTL Global Control | ||
| 319 | # | ||
| 320 | CONFIG_C_AMCKEN=y | ||
| 321 | CONFIG_C_CDPRIO=y | ||
| 322 | # CONFIG_C_AMBEN is not set | ||
| 323 | # CONFIG_C_AMBEN_B0 is not set | ||
| 324 | # CONFIG_C_AMBEN_B0_B1 is not set | ||
| 325 | # CONFIG_C_AMBEN_B0_B1_B2 is not set | ||
| 326 | CONFIG_C_AMBEN_ALL=y | ||
| 327 | |||
| 328 | # | ||
| 329 | # EBIU_AMBCTL Control | ||
| 330 | # | ||
| 331 | CONFIG_BANK_0=0x7BB0 | ||
| 332 | CONFIG_BANK_1=0x7BB0 | ||
| 333 | CONFIG_BANK_2=0x7BB0 | ||
| 334 | CONFIG_BANK_3=0x99B2 | ||
| 335 | |||
| 336 | # | ||
| 337 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | ||
| 338 | # | ||
| 339 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 340 | # CONFIG_PCCARD is not set | ||
| 341 | |||
| 342 | # | ||
| 343 | # Executable file formats | ||
| 344 | # | ||
| 345 | CONFIG_BINFMT_ELF_FDPIC=y | ||
| 346 | CONFIG_BINFMT_FLAT=y | ||
| 347 | CONFIG_BINFMT_ZFLAT=y | ||
| 348 | # CONFIG_BINFMT_SHARED_FLAT is not set | ||
| 349 | # CONFIG_HAVE_AOUT is not set | ||
| 350 | # CONFIG_BINFMT_MISC is not set | ||
| 351 | |||
| 352 | # | ||
| 353 | # Power management options | ||
| 354 | # | ||
| 355 | # CONFIG_PM is not set | ||
| 356 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 357 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | ||
| 358 | |||
| 359 | # | ||
| 360 | # CPU Frequency scaling | ||
| 361 | # | ||
| 362 | # CONFIG_CPU_FREQ is not set | ||
| 363 | CONFIG_NET=y | ||
| 364 | |||
| 365 | # | ||
| 366 | # Networking options | ||
| 367 | # | ||
| 368 | CONFIG_PACKET=y | ||
| 369 | # CONFIG_PACKET_MMAP is not set | ||
| 370 | CONFIG_UNIX=y | ||
| 371 | CONFIG_XFRM=y | ||
| 372 | # CONFIG_XFRM_USER is not set | ||
| 373 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 374 | # CONFIG_XFRM_MIGRATE is not set | ||
| 375 | # CONFIG_XFRM_STATISTICS is not set | ||
| 376 | # CONFIG_NET_KEY is not set | ||
| 377 | CONFIG_INET=y | ||
| 378 | # CONFIG_IP_MULTICAST is not set | ||
| 379 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 380 | CONFIG_IP_FIB_HASH=y | ||
| 381 | CONFIG_IP_PNP=y | ||
| 382 | # CONFIG_IP_PNP_DHCP is not set | ||
| 383 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 384 | # CONFIG_IP_PNP_RARP is not set | ||
| 385 | # CONFIG_NET_IPIP is not set | ||
| 386 | # CONFIG_NET_IPGRE is not set | ||
| 387 | # CONFIG_ARPD is not set | ||
| 388 | CONFIG_SYN_COOKIES=y | ||
| 389 | # CONFIG_INET_AH is not set | ||
| 390 | # CONFIG_INET_ESP is not set | ||
| 391 | # CONFIG_INET_IPCOMP is not set | ||
| 392 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 393 | # CONFIG_INET_TUNNEL is not set | ||
| 394 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 395 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 396 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 397 | # CONFIG_INET_LRO is not set | ||
| 398 | CONFIG_INET_DIAG=y | ||
| 399 | CONFIG_INET_TCP_DIAG=y | ||
| 400 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 401 | CONFIG_TCP_CONG_CUBIC=y | ||
| 402 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 403 | # CONFIG_TCP_MD5SIG is not set | ||
| 404 | # CONFIG_IPV6 is not set | ||
| 405 | # CONFIG_NETLABEL is not set | ||
| 406 | # CONFIG_NETWORK_SECMARK is not set | ||
| 407 | # CONFIG_NETFILTER is not set | ||
| 408 | # CONFIG_IP_DCCP is not set | ||
| 409 | # CONFIG_IP_SCTP is not set | ||
| 410 | # CONFIG_TIPC is not set | ||
| 411 | # CONFIG_ATM is not set | ||
| 412 | # CONFIG_BRIDGE is not set | ||
| 413 | # CONFIG_NET_DSA is not set | ||
| 414 | # CONFIG_VLAN_8021Q is not set | ||
| 415 | # CONFIG_DECNET is not set | ||
| 416 | # CONFIG_LLC2 is not set | ||
| 417 | # CONFIG_IPX is not set | ||
| 418 | # CONFIG_ATALK is not set | ||
| 419 | # CONFIG_X25 is not set | ||
| 420 | # CONFIG_LAPB is not set | ||
| 421 | # CONFIG_ECONET is not set | ||
| 422 | # CONFIG_WAN_ROUTER is not set | ||
| 423 | # CONFIG_NET_SCHED is not set | ||
| 424 | |||
| 425 | # | ||
| 426 | # Network testing | ||
| 427 | # | ||
| 428 | # CONFIG_NET_PKTGEN is not set | ||
| 429 | # CONFIG_HAMRADIO is not set | ||
| 430 | # CONFIG_CAN is not set | ||
| 431 | CONFIG_IRDA=m | ||
| 432 | |||
| 433 | # | ||
| 434 | # IrDA protocols | ||
| 435 | # | ||
| 436 | CONFIG_IRLAN=m | ||
| 437 | CONFIG_IRCOMM=m | ||
| 438 | # CONFIG_IRDA_ULTRA is not set | ||
| 439 | |||
| 440 | # | ||
| 441 | # IrDA options | ||
| 442 | # | ||
| 443 | CONFIG_IRDA_CACHE_LAST_LSAP=y | ||
| 444 | # CONFIG_IRDA_FAST_RR is not set | ||
| 445 | # CONFIG_IRDA_DEBUG is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Infrared-port device drivers | ||
| 449 | # | ||
| 450 | |||
| 451 | # | ||
| 452 | # SIR device drivers | ||
| 453 | # | ||
| 454 | CONFIG_IRTTY_SIR=m | ||
| 455 | CONFIG_BFIN_SIR=m | ||
| 456 | CONFIG_SIR_BFIN_DMA=y | ||
| 457 | # CONFIG_SIR_BFIN_PIO is not set | ||
| 458 | |||
| 459 | # | ||
| 460 | # Dongle support | ||
| 461 | # | ||
| 462 | # CONFIG_DONGLE is not set | ||
| 463 | |||
| 464 | # | ||
| 465 | # FIR device drivers | ||
| 466 | # | ||
| 467 | # CONFIG_BT is not set | ||
| 468 | # CONFIG_AF_RXRPC is not set | ||
| 469 | # CONFIG_PHONET is not set | ||
| 470 | CONFIG_WIRELESS=y | ||
| 471 | # CONFIG_CFG80211 is not set | ||
| 472 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 473 | # CONFIG_WIRELESS_EXT is not set | ||
| 474 | # CONFIG_MAC80211 is not set | ||
| 475 | # CONFIG_IEEE80211 is not set | ||
| 476 | # CONFIG_RFKILL is not set | ||
| 477 | # CONFIG_NET_9P is not set | ||
| 478 | |||
| 479 | # | ||
| 480 | # Device Drivers | ||
| 481 | # | ||
| 482 | |||
| 483 | # | ||
| 484 | # Generic Driver Options | ||
| 485 | # | ||
| 486 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 487 | CONFIG_STANDALONE=y | ||
| 488 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 489 | # CONFIG_FW_LOADER is not set | ||
| 490 | # CONFIG_DEBUG_DRIVER is not set | ||
| 491 | # CONFIG_DEBUG_DEVRES is not set | ||
| 492 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 493 | # CONFIG_CONNECTOR is not set | ||
| 494 | CONFIG_MTD=y | ||
| 495 | # CONFIG_MTD_DEBUG is not set | ||
| 496 | # CONFIG_MTD_CONCAT is not set | ||
| 497 | CONFIG_MTD_PARTITIONS=y | ||
| 498 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 499 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 500 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 501 | |||
| 502 | # | ||
| 503 | # User Modules And Translation Layers | ||
| 504 | # | ||
| 505 | CONFIG_MTD_CHAR=m | ||
| 506 | CONFIG_MTD_BLKDEVS=y | ||
| 507 | CONFIG_MTD_BLOCK=y | ||
| 508 | # CONFIG_FTL is not set | ||
| 509 | # CONFIG_NFTL is not set | ||
| 510 | # CONFIG_INFTL is not set | ||
| 511 | # CONFIG_RFD_FTL is not set | ||
| 512 | # CONFIG_SSFDC is not set | ||
| 513 | # CONFIG_MTD_OOPS is not set | ||
| 514 | |||
| 515 | # | ||
| 516 | # RAM/ROM/Flash chip drivers | ||
| 517 | # | ||
| 518 | CONFIG_MTD_CFI=m | ||
| 519 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 520 | CONFIG_MTD_GEN_PROBE=m | ||
| 521 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 522 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 523 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 524 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 525 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 526 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 527 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 528 | CONFIG_MTD_CFI_I1=y | ||
| 529 | CONFIG_MTD_CFI_I2=y | ||
| 530 | # CONFIG_MTD_CFI_I4 is not set | ||
| 531 | # CONFIG_MTD_CFI_I8 is not set | ||
| 532 | # CONFIG_MTD_CFI_INTELEXT is not set | ||
| 533 | CONFIG_MTD_CFI_AMDSTD=m | ||
| 534 | # CONFIG_MTD_CFI_STAA is not set | ||
| 535 | CONFIG_MTD_CFI_UTIL=m | ||
| 536 | CONFIG_MTD_RAM=y | ||
| 537 | CONFIG_MTD_ROM=m | ||
| 538 | # CONFIG_MTD_ABSENT is not set | ||
| 539 | |||
| 540 | # | ||
| 541 | # Mapping drivers for chip access | ||
| 542 | # | ||
| 543 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 544 | CONFIG_MTD_PHYSMAP=m | ||
| 545 | CONFIG_MTD_PHYSMAP_START=0x20000000 | ||
| 546 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 547 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 548 | # CONFIG_MTD_UCLINUX is not set | ||
| 549 | # CONFIG_MTD_PLATRAM is not set | ||
| 550 | |||
| 551 | # | ||
| 552 | # Self-contained MTD device drivers | ||
| 553 | # | ||
| 554 | # CONFIG_MTD_DATAFLASH is not set | ||
| 555 | # CONFIG_MTD_M25P80 is not set | ||
| 556 | # CONFIG_MTD_SLRAM is not set | ||
| 557 | # CONFIG_MTD_PHRAM is not set | ||
| 558 | # CONFIG_MTD_MTDRAM is not set | ||
| 559 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 560 | |||
| 561 | # | ||
| 562 | # Disk-On-Chip Device Drivers | ||
| 563 | # | ||
| 564 | # CONFIG_MTD_DOC2000 is not set | ||
| 565 | # CONFIG_MTD_DOC2001 is not set | ||
| 566 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 567 | CONFIG_MTD_NAND=m | ||
| 568 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 569 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 570 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 571 | CONFIG_MTD_NAND_BFIN=m | ||
| 572 | CONFIG_BFIN_NAND_BASE=0x20212000 | ||
| 573 | CONFIG_BFIN_NAND_CLE=2 | ||
| 574 | CONFIG_BFIN_NAND_ALE=1 | ||
| 575 | CONFIG_BFIN_NAND_READY=3 | ||
| 576 | CONFIG_MTD_NAND_IDS=m | ||
| 577 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 578 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 579 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 580 | # CONFIG_MTD_ONENAND is not set | ||
| 581 | |||
| 582 | # | ||
| 583 | # UBI - Unsorted block images | ||
| 584 | # | ||
| 585 | # CONFIG_MTD_UBI is not set | ||
| 586 | # CONFIG_PARPORT is not set | ||
| 587 | CONFIG_BLK_DEV=y | ||
| 588 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 589 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 590 | # CONFIG_BLK_DEV_NBD is not set | ||
| 591 | CONFIG_BLK_DEV_RAM=y | ||
| 592 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 593 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 594 | # CONFIG_BLK_DEV_XIP is not set | ||
| 595 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 596 | # CONFIG_ATA_OVER_ETH is not set | ||
| 597 | # CONFIG_BLK_DEV_HD is not set | ||
| 598 | # CONFIG_MISC_DEVICES is not set | ||
| 599 | CONFIG_HAVE_IDE=y | ||
| 600 | # CONFIG_IDE is not set | ||
| 601 | |||
| 602 | # | ||
| 603 | # SCSI device support | ||
| 604 | # | ||
| 605 | # CONFIG_RAID_ATTRS is not set | ||
| 606 | # CONFIG_SCSI is not set | ||
| 607 | # CONFIG_SCSI_DMA is not set | ||
| 608 | # CONFIG_SCSI_NETLINK is not set | ||
| 609 | # CONFIG_ATA is not set | ||
| 610 | # CONFIG_MD is not set | ||
| 611 | CONFIG_NETDEVICES=y | ||
| 612 | # CONFIG_DUMMY is not set | ||
| 613 | # CONFIG_BONDING is not set | ||
| 614 | # CONFIG_MACVLAN is not set | ||
| 615 | # CONFIG_EQUALIZER is not set | ||
| 616 | # CONFIG_TUN is not set | ||
| 617 | # CONFIG_VETH is not set | ||
| 618 | CONFIG_PHYLIB=y | ||
| 619 | |||
| 620 | # | ||
| 621 | # MII PHY device drivers | ||
| 622 | # | ||
| 623 | # CONFIG_MARVELL_PHY is not set | ||
| 624 | # CONFIG_DAVICOM_PHY is not set | ||
| 625 | # CONFIG_QSEMI_PHY is not set | ||
| 626 | # CONFIG_LXT_PHY is not set | ||
| 627 | # CONFIG_CICADA_PHY is not set | ||
| 628 | # CONFIG_VITESSE_PHY is not set | ||
| 629 | CONFIG_SMSC_PHY=y | ||
| 630 | # CONFIG_BROADCOM_PHY is not set | ||
| 631 | # CONFIG_ICPLUS_PHY is not set | ||
| 632 | # CONFIG_REALTEK_PHY is not set | ||
| 633 | # CONFIG_FIXED_PHY is not set | ||
| 634 | # CONFIG_MDIO_BITBANG is not set | ||
| 635 | CONFIG_NET_ETHERNET=y | ||
| 636 | CONFIG_MII=y | ||
| 637 | CONFIG_SMC91X=y | ||
| 638 | # CONFIG_SMSC911X is not set | ||
| 639 | # CONFIG_DM9000 is not set | ||
| 640 | # CONFIG_ENC28J60 is not set | ||
| 641 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 642 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 643 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 644 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 645 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 646 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 647 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 648 | # CONFIG_NETDEV_1000 is not set | ||
| 649 | # CONFIG_NETDEV_10000 is not set | ||
| 650 | |||
| 651 | # | ||
| 652 | # Wireless LAN | ||
| 653 | # | ||
| 654 | # CONFIG_WLAN_PRE80211 is not set | ||
| 655 | # CONFIG_WLAN_80211 is not set | ||
| 656 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 657 | # CONFIG_WAN is not set | ||
| 658 | # CONFIG_PPP is not set | ||
| 659 | # CONFIG_SLIP is not set | ||
| 660 | # CONFIG_NETCONSOLE is not set | ||
| 661 | # CONFIG_NETPOLL is not set | ||
| 662 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 663 | # CONFIG_ISDN is not set | ||
| 664 | # CONFIG_PHONE is not set | ||
| 665 | |||
| 666 | # | ||
| 667 | # Input device support | ||
| 668 | # | ||
| 669 | CONFIG_INPUT=y | ||
| 670 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 671 | # CONFIG_INPUT_POLLDEV is not set | ||
| 672 | |||
| 673 | # | ||
| 674 | # Userland interfaces | ||
| 675 | # | ||
| 676 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 677 | # CONFIG_INPUT_JOYDEV is not set | ||
| 678 | CONFIG_INPUT_EVDEV=m | ||
| 679 | # CONFIG_INPUT_EVBUG is not set | ||
| 680 | |||
| 681 | # | ||
| 682 | # Input Device Drivers | ||
| 683 | # | ||
| 684 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 685 | # CONFIG_INPUT_MOUSE is not set | ||
| 686 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 687 | # CONFIG_INPUT_TABLET is not set | ||
| 688 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 689 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 690 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
| 691 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 692 | CONFIG_TOUCHSCREEN_AD7879_SPI=y | ||
| 693 | CONFIG_TOUCHSCREEN_AD7879=m | ||
| 694 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 695 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 696 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 697 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 698 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 699 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 700 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 701 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 702 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 703 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 704 | CONFIG_INPUT_MISC=y | ||
| 705 | # CONFIG_INPUT_UINPUT is not set | ||
| 706 | # CONFIG_CONFIG_INPUT_PCF8574 is not set | ||
| 707 | |||
| 708 | # | ||
| 709 | # Hardware I/O ports | ||
| 710 | # | ||
| 711 | # CONFIG_SERIO is not set | ||
| 712 | # CONFIG_GAMEPORT is not set | ||
| 713 | |||
| 714 | # | ||
| 715 | # Character devices | ||
| 716 | # | ||
| 717 | # CONFIG_AD9960 is not set | ||
| 718 | # CONFIG_SPI_ADC_BF533 is not set | ||
| 719 | # CONFIG_BF5xx_PPIFCD is not set | ||
| 720 | # CONFIG_BFIN_SIMPLE_TIMER is not set | ||
| 721 | # CONFIG_BF5xx_PPI is not set | ||
| 722 | CONFIG_BFIN_SPORT=y | ||
| 723 | # CONFIG_BFIN_TIMER_LATENCY is not set | ||
| 724 | # CONFIG_TWI_LCD is not set | ||
| 725 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 726 | CONFIG_SIMPLE_GPIO=m | ||
| 727 | # CONFIG_VT is not set | ||
| 728 | # CONFIG_DEVKMEM is not set | ||
| 729 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 730 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 731 | |||
| 732 | # | ||
| 733 | # Serial drivers | ||
| 734 | # | ||
| 735 | # CONFIG_SERIAL_8250 is not set | ||
| 736 | |||
| 737 | # | ||
| 738 | # Non-8250 serial port support | ||
| 739 | # | ||
| 740 | CONFIG_SERIAL_BFIN=y | ||
| 741 | CONFIG_SERIAL_BFIN_CONSOLE=y | ||
| 742 | CONFIG_SERIAL_BFIN_DMA=y | ||
| 743 | # CONFIG_SERIAL_BFIN_PIO is not set | ||
| 744 | CONFIG_SERIAL_BFIN_UART0=y | ||
| 745 | # CONFIG_BFIN_UART0_CTSRTS is not set | ||
| 746 | CONFIG_SERIAL_BFIN_UART1=y | ||
| 747 | # CONFIG_BFIN_UART1_CTSRTS is not set | ||
| 748 | CONFIG_SERIAL_BFIN_UART2=y | ||
| 749 | # CONFIG_BFIN_UART2_CTSRTS is not set | ||
| 750 | CONFIG_SERIAL_CORE=y | ||
| 751 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 752 | # CONFIG_SERIAL_BFIN_SPORT is not set | ||
| 753 | CONFIG_UNIX98_PTYS=y | ||
| 754 | # CONFIG_LEGACY_PTYS is not set | ||
| 755 | |||
| 756 | # | ||
| 757 | # CAN, the car bus and industrial fieldbus | ||
| 758 | # | ||
| 759 | # CONFIG_CAN4LINUX is not set | ||
| 760 | # CONFIG_IPMI_HANDLER is not set | ||
| 761 | # CONFIG_HW_RANDOM is not set | ||
| 762 | # CONFIG_R3964 is not set | ||
| 763 | # CONFIG_RAW_DRIVER is not set | ||
| 764 | # CONFIG_TCG_TPM is not set | ||
| 765 | CONFIG_I2C=y | ||
| 766 | CONFIG_I2C_BOARDINFO=y | ||
| 767 | # CONFIG_I2C_CHARDEV is not set | ||
| 768 | CONFIG_I2C_HELPER_AUTO=y | ||
| 769 | |||
| 770 | # | ||
| 771 | # I2C Hardware Bus support | ||
| 772 | # | ||
| 773 | |||
| 774 | # | ||
| 775 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 776 | # | ||
| 777 | CONFIG_I2C_BLACKFIN_TWI=y | ||
| 778 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 | ||
| 779 | # CONFIG_I2C_GPIO is not set | ||
| 780 | # CONFIG_I2C_OCORES is not set | ||
| 781 | # CONFIG_I2C_SIMTEC is not set | ||
| 782 | |||
| 783 | # | ||
| 784 | # External I2C/SMBus adapter drivers | ||
| 785 | # | ||
| 786 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 787 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 788 | |||
| 789 | # | ||
| 790 | # Other I2C/SMBus bus drivers | ||
| 791 | # | ||
| 792 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 793 | # CONFIG_I2C_STUB is not set | ||
| 794 | |||
| 795 | # | ||
| 796 | # Miscellaneous I2C Chip support | ||
| 797 | # | ||
| 798 | # CONFIG_DS1682 is not set | ||
| 799 | # CONFIG_AT24 is not set | ||
| 800 | # CONFIG_SENSORS_AD5252 is not set | ||
| 801 | # CONFIG_SENSORS_EEPROM is not set | ||
| 802 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 803 | # CONFIG_PCF8575 is not set | ||
| 804 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 805 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 806 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 807 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 808 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 809 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 810 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 811 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 812 | CONFIG_SPI=y | ||
| 813 | # CONFIG_SPI_DEBUG is not set | ||
| 814 | CONFIG_SPI_MASTER=y | ||
| 815 | |||
| 816 | # | ||
| 817 | # SPI Master Controller Drivers | ||
| 818 | # | ||
| 819 | CONFIG_SPI_BFIN=y | ||
| 820 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 821 | # CONFIG_SPI_BITBANG is not set | ||
| 822 | |||
| 823 | # | ||
| 824 | # SPI Protocol Masters | ||
| 825 | # | ||
| 826 | # CONFIG_SPI_AT25 is not set | ||
| 827 | # CONFIG_SPI_SPIDEV is not set | ||
| 828 | # CONFIG_SPI_TLE62X0 is not set | ||
| 829 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 830 | # CONFIG_GPIOLIB is not set | ||
| 831 | # CONFIG_W1 is not set | ||
| 832 | # CONFIG_POWER_SUPPLY is not set | ||
| 833 | CONFIG_HWMON=y | ||
| 834 | # CONFIG_HWMON_VID is not set | ||
| 835 | # CONFIG_SENSORS_AD7414 is not set | ||
| 836 | # CONFIG_SENSORS_AD7418 is not set | ||
| 837 | # CONFIG_SENSORS_ADCXX is not set | ||
| 838 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 839 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 840 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 841 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 842 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 843 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 844 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 845 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 846 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 847 | # CONFIG_SENSORS_DS1621 is not set | ||
| 848 | # CONFIG_SENSORS_F71805F is not set | ||
| 849 | # CONFIG_SENSORS_F71882FG is not set | ||
| 850 | # CONFIG_SENSORS_F75375S is not set | ||
| 851 | # CONFIG_SENSORS_GL518SM is not set | ||
| 852 | # CONFIG_SENSORS_GL520SM is not set | ||
| 853 | # CONFIG_SENSORS_IT87 is not set | ||
| 854 | # CONFIG_SENSORS_LM63 is not set | ||
| 855 | # CONFIG_SENSORS_LM70 is not set | ||
| 856 | # CONFIG_SENSORS_LM75 is not set | ||
| 857 | # CONFIG_SENSORS_LM77 is not set | ||
| 858 | # CONFIG_SENSORS_LM78 is not set | ||
| 859 | # CONFIG_SENSORS_LM80 is not set | ||
| 860 | # CONFIG_SENSORS_LM83 is not set | ||
| 861 | # CONFIG_SENSORS_LM85 is not set | ||
| 862 | # CONFIG_SENSORS_LM87 is not set | ||
| 863 | # CONFIG_SENSORS_LM90 is not set | ||
| 864 | # CONFIG_SENSORS_LM92 is not set | ||
| 865 | # CONFIG_SENSORS_LM93 is not set | ||
| 866 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 867 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 868 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 869 | # CONFIG_SENSORS_PC87360 is not set | ||
| 870 | # CONFIG_SENSORS_PC87427 is not set | ||
| 871 | # CONFIG_SENSORS_DME1737 is not set | ||
| 872 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 873 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 874 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 875 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 876 | # CONFIG_SENSORS_THMC50 is not set | ||
| 877 | # CONFIG_SENSORS_VT1211 is not set | ||
| 878 | # CONFIG_SENSORS_W83781D is not set | ||
| 879 | # CONFIG_SENSORS_W83791D is not set | ||
| 880 | # CONFIG_SENSORS_W83792D is not set | ||
| 881 | # CONFIG_SENSORS_W83793 is not set | ||
| 882 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 883 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 884 | # CONFIG_SENSORS_W83627HF is not set | ||
| 885 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 886 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 887 | # CONFIG_THERMAL is not set | ||
| 888 | # CONFIG_THERMAL_HWMON is not set | ||
| 889 | CONFIG_WATCHDOG=y | ||
| 890 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 891 | |||
| 892 | # | ||
| 893 | # Watchdog Device Drivers | ||
| 894 | # | ||
| 895 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 896 | CONFIG_BFIN_WDT=y | ||
| 897 | |||
| 898 | # | ||
| 899 | # Multifunction device drivers | ||
| 900 | # | ||
| 901 | # CONFIG_MFD_CORE is not set | ||
| 902 | # CONFIG_MFD_SM501 is not set | ||
| 903 | # CONFIG_HTC_PASIC3 is not set | ||
| 904 | # CONFIG_MFD_TMIO is not set | ||
| 905 | # CONFIG_MFD_WM8400 is not set | ||
| 906 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 907 | |||
| 908 | # | ||
| 909 | # Multimedia devices | ||
| 910 | # | ||
| 911 | |||
| 912 | # | ||
| 913 | # Multimedia core support | ||
| 914 | # | ||
| 915 | # CONFIG_VIDEO_DEV is not set | ||
| 916 | # CONFIG_DVB_CORE is not set | ||
| 917 | # CONFIG_VIDEO_MEDIA is not set | ||
| 918 | |||
| 919 | # | ||
| 920 | # Multimedia drivers | ||
| 921 | # | ||
| 922 | # CONFIG_DAB is not set | ||
| 923 | |||
| 924 | # | ||
| 925 | # Graphics support | ||
| 926 | # | ||
| 927 | # CONFIG_VGASTATE is not set | ||
| 928 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 929 | CONFIG_FB=m | ||
| 930 | # CONFIG_FIRMWARE_EDID is not set | ||
| 931 | # CONFIG_FB_DDC is not set | ||
| 932 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 933 | CONFIG_FB_CFB_FILLRECT=m | ||
| 934 | CONFIG_FB_CFB_COPYAREA=m | ||
| 935 | CONFIG_FB_CFB_IMAGEBLIT=m | ||
| 936 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 937 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 938 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 939 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 940 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 941 | # CONFIG_FB_SYS_FOPS is not set | ||
| 942 | # CONFIG_FB_SVGALIB is not set | ||
| 943 | # CONFIG_FB_MACMODES is not set | ||
| 944 | # CONFIG_FB_BACKLIGHT is not set | ||
| 945 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 946 | # CONFIG_FB_TILEBLITTING is not set | ||
| 947 | |||
| 948 | # | ||
| 949 | # Frame buffer hardware drivers | ||
| 950 | # | ||
| 951 | # CONFIG_FB_BFIN_T350MCQB is not set | ||
| 952 | CONFIG_FB_BFIN_LQ035Q1=m | ||
| 953 | # CONFIG_FB_BFIN_7393 is not set | ||
| 954 | # CONFIG_FB_S1D13XXX is not set | ||
| 955 | # CONFIG_FB_VIRTUAL is not set | ||
| 956 | # CONFIG_FB_METRONOME is not set | ||
| 957 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 958 | |||
| 959 | # | ||
| 960 | # Display device support | ||
| 961 | # | ||
| 962 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 963 | # CONFIG_LOGO is not set | ||
| 964 | # CONFIG_SOUND is not set | ||
| 965 | CONFIG_HID_SUPPORT=y | ||
| 966 | CONFIG_HID=y | ||
| 967 | # CONFIG_HID_DEBUG is not set | ||
| 968 | # CONFIG_HIDRAW is not set | ||
| 969 | # CONFIG_HID_PID is not set | ||
| 970 | |||
| 971 | # | ||
| 972 | # Special HID drivers | ||
| 973 | # | ||
| 974 | CONFIG_HID_COMPAT=y | ||
| 975 | # CONFIG_USB_SUPPORT is not set | ||
| 976 | # CONFIG_MMC is not set | ||
| 977 | # CONFIG_MEMSTICK is not set | ||
| 978 | # CONFIG_NEW_LEDS is not set | ||
| 979 | # CONFIG_ACCESSIBILITY is not set | ||
| 980 | CONFIG_RTC_LIB=y | ||
| 981 | CONFIG_RTC_CLASS=y | ||
| 982 | CONFIG_RTC_HCTOSYS=y | ||
| 983 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 984 | # CONFIG_RTC_DEBUG is not set | ||
| 985 | |||
| 986 | # | ||
| 987 | # RTC interfaces | ||
| 988 | # | ||
| 989 | CONFIG_RTC_INTF_SYSFS=y | ||
| 990 | CONFIG_RTC_INTF_PROC=y | ||
| 991 | CONFIG_RTC_INTF_DEV=y | ||
| 992 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 993 | # CONFIG_RTC_DRV_TEST is not set | ||
| 994 | |||
| 995 | # | ||
| 996 | # I2C RTC drivers | ||
| 997 | # | ||
| 998 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 999 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1000 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1001 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1002 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1003 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1004 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1005 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1006 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1007 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1008 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1009 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1010 | |||
| 1011 | # | ||
| 1012 | # SPI RTC drivers | ||
| 1013 | # | ||
| 1014 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1015 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1016 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1017 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1018 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1019 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1020 | |||
| 1021 | # | ||
| 1022 | # Platform RTC drivers | ||
| 1023 | # | ||
| 1024 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1025 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1026 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1027 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1028 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1029 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1030 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1031 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1032 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1033 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1034 | |||
| 1035 | # | ||
| 1036 | # on-CPU RTC drivers | ||
| 1037 | # | ||
| 1038 | CONFIG_RTC_DRV_BFIN=y | ||
| 1039 | # CONFIG_DMADEVICES is not set | ||
| 1040 | # CONFIG_UIO is not set | ||
| 1041 | # CONFIG_STAGING is not set | ||
| 1042 | |||
| 1043 | # | ||
| 1044 | # File systems | ||
| 1045 | # | ||
| 1046 | # CONFIG_EXT2_FS is not set | ||
| 1047 | # CONFIG_EXT3_FS is not set | ||
| 1048 | # CONFIG_EXT4_FS is not set | ||
| 1049 | # CONFIG_REISERFS_FS is not set | ||
| 1050 | # CONFIG_JFS_FS is not set | ||
| 1051 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1052 | CONFIG_FILE_LOCKING=y | ||
| 1053 | # CONFIG_XFS_FS is not set | ||
| 1054 | # CONFIG_OCFS2_FS is not set | ||
| 1055 | # CONFIG_DNOTIFY is not set | ||
| 1056 | CONFIG_INOTIFY=y | ||
| 1057 | CONFIG_INOTIFY_USER=y | ||
| 1058 | # CONFIG_QUOTA is not set | ||
| 1059 | # CONFIG_AUTOFS_FS is not set | ||
| 1060 | # CONFIG_AUTOFS4_FS is not set | ||
| 1061 | # CONFIG_FUSE_FS is not set | ||
| 1062 | |||
| 1063 | # | ||
| 1064 | # CD-ROM/DVD Filesystems | ||
| 1065 | # | ||
| 1066 | # CONFIG_ISO9660_FS is not set | ||
| 1067 | # CONFIG_UDF_FS is not set | ||
| 1068 | |||
| 1069 | # | ||
| 1070 | # DOS/FAT/NT Filesystems | ||
| 1071 | # | ||
| 1072 | # CONFIG_MSDOS_FS is not set | ||
| 1073 | # CONFIG_VFAT_FS is not set | ||
| 1074 | # CONFIG_NTFS_FS is not set | ||
| 1075 | |||
| 1076 | # | ||
| 1077 | # Pseudo filesystems | ||
| 1078 | # | ||
| 1079 | CONFIG_PROC_FS=y | ||
| 1080 | CONFIG_PROC_SYSCTL=y | ||
| 1081 | CONFIG_SYSFS=y | ||
| 1082 | # CONFIG_TMPFS is not set | ||
| 1083 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1084 | # CONFIG_CONFIGFS_FS is not set | ||
| 1085 | |||
| 1086 | # | ||
| 1087 | # Miscellaneous filesystems | ||
| 1088 | # | ||
| 1089 | # CONFIG_ADFS_FS is not set | ||
| 1090 | # CONFIG_AFFS_FS is not set | ||
| 1091 | # CONFIG_HFS_FS is not set | ||
| 1092 | # CONFIG_HFSPLUS_FS is not set | ||
| 1093 | # CONFIG_BEFS_FS is not set | ||
| 1094 | # CONFIG_BFS_FS is not set | ||
| 1095 | # CONFIG_EFS_FS is not set | ||
| 1096 | CONFIG_YAFFS_FS=m | ||
| 1097 | CONFIG_YAFFS_YAFFS1=y | ||
| 1098 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1099 | # CONFIG_YAFFS_DOES_ECC is not set | ||
| 1100 | CONFIG_YAFFS_YAFFS2=y | ||
| 1101 | CONFIG_YAFFS_AUTO_YAFFS2=y | ||
| 1102 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | ||
| 1103 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | ||
| 1104 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | ||
| 1105 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | ||
| 1106 | CONFIG_JFFS2_FS=m | ||
| 1107 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1108 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1109 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1110 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 1111 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1112 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1113 | CONFIG_JFFS2_ZLIB=y | ||
| 1114 | # CONFIG_JFFS2_LZO is not set | ||
| 1115 | CONFIG_JFFS2_RTIME=y | ||
| 1116 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1117 | # CONFIG_CRAMFS is not set | ||
| 1118 | # CONFIG_VXFS_FS is not set | ||
| 1119 | # CONFIG_MINIX_FS is not set | ||
| 1120 | # CONFIG_OMFS_FS is not set | ||
| 1121 | # CONFIG_HPFS_FS is not set | ||
| 1122 | # CONFIG_QNX4FS_FS is not set | ||
| 1123 | # CONFIG_ROMFS_FS is not set | ||
| 1124 | # CONFIG_SYSV_FS is not set | ||
| 1125 | # CONFIG_UFS_FS is not set | ||
| 1126 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1127 | CONFIG_NFS_FS=m | ||
| 1128 | CONFIG_NFS_V3=y | ||
| 1129 | # CONFIG_NFS_V3_ACL is not set | ||
| 1130 | # CONFIG_NFS_V4 is not set | ||
| 1131 | # CONFIG_NFSD is not set | ||
| 1132 | CONFIG_LOCKD=m | ||
| 1133 | CONFIG_LOCKD_V4=y | ||
| 1134 | CONFIG_NFS_COMMON=y | ||
| 1135 | CONFIG_SUNRPC=m | ||
| 1136 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1137 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1138 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1139 | CONFIG_SMB_FS=m | ||
| 1140 | # CONFIG_SMB_NLS_DEFAULT is not set | ||
| 1141 | # CONFIG_CIFS is not set | ||
| 1142 | # CONFIG_NCP_FS is not set | ||
| 1143 | # CONFIG_CODA_FS is not set | ||
| 1144 | # CONFIG_AFS_FS is not set | ||
| 1145 | |||
| 1146 | # | ||
| 1147 | # Partition Types | ||
| 1148 | # | ||
| 1149 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 1150 | CONFIG_MSDOS_PARTITION=y | ||
| 1151 | CONFIG_NLS=m | ||
| 1152 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1153 | # CONFIG_NLS_CODEPAGE_437 is not set | ||
| 1154 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1155 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1156 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1157 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1158 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1159 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1160 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1161 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1162 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1163 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1164 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1165 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1166 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1167 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1168 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1169 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1170 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1171 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1172 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1173 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1174 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1175 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1176 | # CONFIG_NLS_ASCII is not set | ||
| 1177 | # CONFIG_NLS_ISO8859_1 is not set | ||
| 1178 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1179 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1180 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1181 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1182 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1183 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1184 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1185 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1186 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1187 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1188 | # CONFIG_NLS_KOI8_R is not set | ||
| 1189 | # CONFIG_NLS_KOI8_U is not set | ||
| 1190 | # CONFIG_NLS_UTF8 is not set | ||
| 1191 | # CONFIG_DLM is not set | ||
| 1192 | |||
| 1193 | # | ||
| 1194 | # Kernel hacking | ||
| 1195 | # | ||
| 1196 | # CONFIG_PRINTK_TIME is not set | ||
| 1197 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1198 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1199 | CONFIG_FRAME_WARN=1024 | ||
| 1200 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1201 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1202 | CONFIG_DEBUG_FS=y | ||
| 1203 | # CONFIG_HEADERS_CHECK is not set | ||
| 1204 | CONFIG_DEBUG_KERNEL=y | ||
| 1205 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1206 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1207 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1208 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1209 | CONFIG_SCHED_DEBUG=y | ||
| 1210 | # CONFIG_SCHEDSTATS is not set | ||
| 1211 | # CONFIG_TIMER_STATS is not set | ||
| 1212 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1213 | # CONFIG_DEBUG_SLAB is not set | ||
| 1214 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1215 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1216 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1217 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1218 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1219 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1220 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1221 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1222 | CONFIG_DEBUG_INFO=y | ||
| 1223 | # CONFIG_DEBUG_VM is not set | ||
| 1224 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1225 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1226 | # CONFIG_DEBUG_LIST is not set | ||
| 1227 | # CONFIG_DEBUG_SG is not set | ||
| 1228 | # CONFIG_FRAME_POINTER is not set | ||
| 1229 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1230 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1231 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1232 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1233 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1234 | # CONFIG_FAULT_INJECTION is not set | ||
| 1235 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1236 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1237 | # CONFIG_SAMPLES is not set | ||
| 1238 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1239 | # CONFIG_KGDB is not set | ||
| 1240 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1241 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1242 | CONFIG_DEBUG_VERBOSE=y | ||
| 1243 | CONFIG_DEBUG_MMRS=y | ||
| 1244 | # CONFIG_DEBUG_HWERR is not set | ||
| 1245 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 1246 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | ||
| 1247 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | ||
| 1248 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | ||
| 1249 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set | ||
| 1250 | # CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set | ||
| 1251 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | ||
| 1252 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | ||
| 1253 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | ||
| 1254 | CONFIG_EARLY_PRINTK=y | ||
| 1255 | CONFIG_CPLB_INFO=y | ||
| 1256 | CONFIG_ACCESS_CHECK=y | ||
| 1257 | |||
| 1258 | # | ||
| 1259 | # Security options | ||
| 1260 | # | ||
| 1261 | # CONFIG_KEYS is not set | ||
| 1262 | CONFIG_SECURITY=y | ||
| 1263 | # CONFIG_SECURITYFS is not set | ||
| 1264 | # CONFIG_SECURITY_NETWORK is not set | ||
| 1265 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1266 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 1267 | CONFIG_CRYPTO=y | ||
| 1268 | |||
| 1269 | # | ||
| 1270 | # Crypto core or helper | ||
| 1271 | # | ||
| 1272 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1273 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1274 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1275 | # CONFIG_CRYPTO_NULL is not set | ||
| 1276 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1277 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1278 | # CONFIG_CRYPTO_TEST is not set | ||
| 1279 | |||
| 1280 | # | ||
| 1281 | # Authenticated Encryption with Associated Data | ||
| 1282 | # | ||
| 1283 | # CONFIG_CRYPTO_CCM is not set | ||
| 1284 | # CONFIG_CRYPTO_GCM is not set | ||
| 1285 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1286 | |||
| 1287 | # | ||
| 1288 | # Block modes | ||
| 1289 | # | ||
| 1290 | # CONFIG_CRYPTO_CBC is not set | ||
| 1291 | # CONFIG_CRYPTO_CTR is not set | ||
| 1292 | # CONFIG_CRYPTO_CTS is not set | ||
| 1293 | # CONFIG_CRYPTO_ECB is not set | ||
| 1294 | # CONFIG_CRYPTO_LRW is not set | ||
| 1295 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1296 | # CONFIG_CRYPTO_XTS is not set | ||
| 1297 | |||
| 1298 | # | ||
| 1299 | # Hash modes | ||
| 1300 | # | ||
| 1301 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1302 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1303 | |||
| 1304 | # | ||
| 1305 | # Digest | ||
| 1306 | # | ||
| 1307 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1308 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1309 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1310 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1311 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1312 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1313 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1314 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1315 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1316 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1317 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1318 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1319 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1320 | |||
| 1321 | # | ||
| 1322 | # Ciphers | ||
| 1323 | # | ||
| 1324 | # CONFIG_CRYPTO_AES is not set | ||
| 1325 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1326 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1327 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1328 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1329 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1330 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1331 | # CONFIG_CRYPTO_DES is not set | ||
| 1332 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1333 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1334 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1335 | # CONFIG_CRYPTO_SEED is not set | ||
| 1336 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1337 | # CONFIG_CRYPTO_TEA is not set | ||
| 1338 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1339 | |||
| 1340 | # | ||
| 1341 | # Compression | ||
| 1342 | # | ||
| 1343 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1344 | # CONFIG_CRYPTO_LZO is not set | ||
| 1345 | |||
| 1346 | # | ||
| 1347 | # Random Number Generation | ||
| 1348 | # | ||
| 1349 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1350 | CONFIG_CRYPTO_HW=y | ||
| 1351 | |||
| 1352 | # | ||
| 1353 | # Library routines | ||
| 1354 | # | ||
| 1355 | CONFIG_BITREVERSE=y | ||
| 1356 | CONFIG_CRC_CCITT=m | ||
| 1357 | # CONFIG_CRC16 is not set | ||
| 1358 | # CONFIG_CRC_T10DIF is not set | ||
| 1359 | # CONFIG_CRC_ITU_T is not set | ||
| 1360 | CONFIG_CRC32=y | ||
| 1361 | # CONFIG_CRC7 is not set | ||
| 1362 | # CONFIG_LIBCRC32C is not set | ||
| 1363 | CONFIG_ZLIB_INFLATE=y | ||
| 1364 | CONFIG_ZLIB_DEFLATE=m | ||
| 1365 | CONFIG_PLIST=y | ||
| 1366 | CONFIG_HAS_IOMEM=y | ||
| 1367 | CONFIG_HAS_IOPORT=y | ||
| 1368 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index bf63660815b9..d4ed9ce1f62f 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24.7 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # | 4 | # |
| 5 | # CONFIG_MMU is not set | 5 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 6 | # CONFIG_FPU is not set |
| @@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 9 | CONFIG_BLACKFIN=y | 9 | CONFIG_BLACKFIN=y |
| 10 | CONFIG_ZONE_DMA=y | 10 | CONFIG_ZONE_DMA=y |
| 11 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 11 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 13 | CONFIG_GENERIC_HWEIGHT=y | 12 | CONFIG_GENERIC_HWEIGHT=y |
| 14 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| @@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 31 | # CONFIG_POSIX_MQUEUE is not set | 30 | # CONFIG_POSIX_MQUEUE is not set |
| 32 | # CONFIG_BSD_PROCESS_ACCT is not set | 31 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 33 | # CONFIG_TASKSTATS is not set | 32 | # CONFIG_TASKSTATS is not set |
| 34 | # CONFIG_USER_NS is not set | ||
| 35 | # CONFIG_PID_NS is not set | ||
| 36 | # CONFIG_AUDIT is not set | 33 | # CONFIG_AUDIT is not set |
| 37 | CONFIG_IKCONFIG=y | 34 | CONFIG_IKCONFIG=y |
| 38 | CONFIG_IKCONFIG_PROC=y | 35 | CONFIG_IKCONFIG_PROC=y |
| 39 | CONFIG_LOG_BUF_SHIFT=14 | 36 | CONFIG_LOG_BUF_SHIFT=14 |
| 40 | # CONFIG_CGROUPS is not set | 37 | # CONFIG_CGROUPS is not set |
| 41 | CONFIG_FAIR_GROUP_SCHED=y | 38 | # CONFIG_GROUP_SCHED is not set |
| 42 | CONFIG_FAIR_USER_SCHED=y | 39 | # CONFIG_SYSFS_DEPRECATED is not set |
| 43 | # CONFIG_FAIR_CGROUP_SCHED is not set | 40 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 44 | CONFIG_SYSFS_DEPRECATED=y | ||
| 45 | # CONFIG_RELAY is not set | 41 | # CONFIG_RELAY is not set |
| 42 | # CONFIG_NAMESPACES is not set | ||
| 46 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 47 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y | |||
| 51 | CONFIG_UID16=y | 48 | CONFIG_UID16=y |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 49 | CONFIG_SYSCTL_SYSCALL=y |
| 53 | CONFIG_KALLSYMS=y | 50 | CONFIG_KALLSYMS=y |
| 51 | # CONFIG_KALLSYMS_ALL is not set | ||
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | CONFIG_HOTPLUG=y | 53 | CONFIG_HOTPLUG=y |
| 56 | CONFIG_PRINTK=y | 54 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 55 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 56 | # CONFIG_ELF_CORE is not set |
| 57 | CONFIG_COMPAT_BRK=y | ||
| 59 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 59 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 60 | CONFIG_ANON_INODES=y |
| 62 | CONFIG_EPOLL=y | 61 | CONFIG_EPOLL=y |
| 63 | CONFIG_SIGNALFD=y | 62 | CONFIG_SIGNALFD=y |
| 63 | CONFIG_TIMERFD=y | ||
| 64 | CONFIG_EVENTFD=y | 64 | CONFIG_EVENTFD=y |
| 65 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 66 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| 70 | # CONFIG_PROFILING is not set | ||
| 71 | # CONFIG_MARKERS is not set | ||
| 72 | CONFIG_HAVE_OPROFILE=y | ||
| 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 69 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 70 | CONFIG_RT_MUTEXES=y | 75 | CONFIG_RT_MUTEXES=y |
| 71 | CONFIG_TINY_SHMEM=y | 76 | CONFIG_TINY_SHMEM=y |
| 72 | CONFIG_BASE_SMALL=0 | 77 | CONFIG_BASE_SMALL=0 |
| 73 | CONFIG_MODULES=y | 78 | CONFIG_MODULES=y |
| 79 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 74 | CONFIG_MODULE_UNLOAD=y | 80 | CONFIG_MODULE_UNLOAD=y |
| 75 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 81 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 76 | # CONFIG_MODVERSIONS is not set | 82 | # CONFIG_MODVERSIONS is not set |
| @@ -81,6 +87,7 @@ CONFIG_BLOCK=y | |||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | 87 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 82 | # CONFIG_LSF is not set | 88 | # CONFIG_LSF is not set |
| 83 | # CONFIG_BLK_DEV_BSG is not set | 89 | # CONFIG_BLK_DEV_BSG is not set |
| 90 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 84 | 91 | ||
| 85 | # | 92 | # |
| 86 | # IO Schedulers | 93 | # IO Schedulers |
| @@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y | |||
| 94 | # CONFIG_DEFAULT_CFQ is not set | 101 | # CONFIG_DEFAULT_CFQ is not set |
| 95 | # CONFIG_DEFAULT_NOOP is not set | 102 | # CONFIG_DEFAULT_NOOP is not set |
| 96 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 103 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 104 | CONFIG_CLASSIC_RCU=y | ||
| 97 | # CONFIG_PREEMPT_NONE is not set | 105 | # CONFIG_PREEMPT_NONE is not set |
| 98 | CONFIG_PREEMPT_VOLUNTARY=y | 106 | CONFIG_PREEMPT_VOLUNTARY=y |
| 99 | # CONFIG_PREEMPT is not set | 107 | # CONFIG_PREEMPT is not set |
| 108 | # CONFIG_FREEZER is not set | ||
| 100 | 109 | ||
| 101 | # | 110 | # |
| 102 | # Blackfin Processor Options | 111 | # Blackfin Processor Options |
| @@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 105 | # | 114 | # |
| 106 | # Processor and Board Settings | 115 | # Processor and Board Settings |
| 107 | # | 116 | # |
| 117 | # CONFIG_BF512 is not set | ||
| 118 | # CONFIG_BF514 is not set | ||
| 119 | # CONFIG_BF516 is not set | ||
| 120 | # CONFIG_BF518 is not set | ||
| 108 | # CONFIG_BF522 is not set | 121 | # CONFIG_BF522 is not set |
| 109 | # CONFIG_BF523 is not set | 122 | # CONFIG_BF523 is not set |
| 110 | # CONFIG_BF524 is not set | 123 | # CONFIG_BF524 is not set |
| @@ -117,18 +130,23 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 117 | # CONFIG_BF534 is not set | 130 | # CONFIG_BF534 is not set |
| 118 | # CONFIG_BF536 is not set | 131 | # CONFIG_BF536 is not set |
| 119 | # CONFIG_BF537 is not set | 132 | # CONFIG_BF537 is not set |
| 133 | # CONFIG_BF538 is not set | ||
| 134 | # CONFIG_BF539 is not set | ||
| 120 | # CONFIG_BF542 is not set | 135 | # CONFIG_BF542 is not set |
| 121 | # CONFIG_BF544 is not set | 136 | # CONFIG_BF544 is not set |
| 122 | # CONFIG_BF547 is not set | 137 | # CONFIG_BF547 is not set |
| 123 | CONFIG_BF548=y | 138 | CONFIG_BF548=y |
| 124 | # CONFIG_BF549 is not set | 139 | # CONFIG_BF549 is not set |
| 125 | # CONFIG_BF561 is not set | 140 | # CONFIG_BF561 is not set |
| 141 | CONFIG_BF_REV_MIN=0 | ||
| 142 | CONFIG_BF_REV_MAX=2 | ||
| 126 | CONFIG_BF_REV_0_0=y | 143 | CONFIG_BF_REV_0_0=y |
| 127 | # CONFIG_BF_REV_0_1 is not set | 144 | # CONFIG_BF_REV_0_1 is not set |
| 128 | # CONFIG_BF_REV_0_2 is not set | 145 | # CONFIG_BF_REV_0_2 is not set |
| 129 | # CONFIG_BF_REV_0_3 is not set | 146 | # CONFIG_BF_REV_0_3 is not set |
| 130 | # CONFIG_BF_REV_0_4 is not set | 147 | # CONFIG_BF_REV_0_4 is not set |
| 131 | # CONFIG_BF_REV_0_5 is not set | 148 | # CONFIG_BF_REV_0_5 is not set |
| 149 | # CONFIG_BF_REV_0_6 is not set | ||
| 132 | # CONFIG_BF_REV_ANY is not set | 150 | # CONFIG_BF_REV_ANY is not set |
| 133 | # CONFIG_BF_REV_NONE is not set | 151 | # CONFIG_BF_REV_NONE is not set |
| 134 | CONFIG_BF54x=y | 152 | CONFIG_BF54x=y |
| @@ -138,15 +156,12 @@ CONFIG_IRQ_SPORT0_RX=9 | |||
| 138 | CONFIG_IRQ_SPORT0_TX=9 | 156 | CONFIG_IRQ_SPORT0_TX=9 |
| 139 | CONFIG_IRQ_SPORT1_RX=9 | 157 | CONFIG_IRQ_SPORT1_RX=9 |
| 140 | CONFIG_IRQ_SPORT1_TX=9 | 158 | CONFIG_IRQ_SPORT1_TX=9 |
| 159 | CONFIG_IRQ_SPI0=10 | ||
| 141 | CONFIG_IRQ_UART0_RX=10 | 160 | CONFIG_IRQ_UART0_RX=10 |
| 142 | CONFIG_IRQ_UART0_TX=10 | 161 | CONFIG_IRQ_UART0_TX=10 |
| 143 | CONFIG_IRQ_UART1_RX=10 | 162 | CONFIG_IRQ_UART1_RX=10 |
| 144 | CONFIG_IRQ_UART1_TX=10 | 163 | CONFIG_IRQ_UART1_TX=10 |
| 145 | CONFIG_IRQ_CNT=8 | 164 | CONFIG_IRQ_CNT=8 |
| 146 | CONFIG_IRQ_USB_INT0=11 | ||
| 147 | CONFIG_IRQ_USB_INT1=11 | ||
| 148 | CONFIG_IRQ_USB_INT2=11 | ||
| 149 | CONFIG_IRQ_USB_DMA=11 | ||
| 150 | CONFIG_IRQ_TIMER0=11 | 165 | CONFIG_IRQ_TIMER0=11 |
| 151 | CONFIG_IRQ_TIMER1=11 | 166 | CONFIG_IRQ_TIMER1=11 |
| 152 | CONFIG_IRQ_TIMER2=11 | 167 | CONFIG_IRQ_TIMER2=11 |
| @@ -155,9 +170,21 @@ CONFIG_IRQ_TIMER4=11 | |||
| 155 | CONFIG_IRQ_TIMER5=11 | 170 | CONFIG_IRQ_TIMER5=11 |
| 156 | CONFIG_IRQ_TIMER6=11 | 171 | CONFIG_IRQ_TIMER6=11 |
| 157 | CONFIG_IRQ_TIMER7=11 | 172 | CONFIG_IRQ_TIMER7=11 |
| 173 | CONFIG_IRQ_USB_INT0=11 | ||
| 174 | CONFIG_IRQ_USB_INT1=11 | ||
| 175 | CONFIG_IRQ_USB_INT2=11 | ||
| 176 | CONFIG_IRQ_USB_DMA=11 | ||
| 158 | CONFIG_IRQ_TIMER8=11 | 177 | CONFIG_IRQ_TIMER8=11 |
| 159 | CONFIG_IRQ_TIMER9=11 | 178 | CONFIG_IRQ_TIMER9=11 |
| 160 | CONFIG_IRQ_TIMER10=11 | 179 | CONFIG_IRQ_TIMER10=11 |
| 180 | CONFIG_IRQ_SPORT2_RX=9 | ||
| 181 | CONFIG_IRQ_SPORT2_TX=9 | ||
| 182 | CONFIG_IRQ_SPORT3_RX=9 | ||
| 183 | CONFIG_IRQ_SPORT3_TX=9 | ||
| 184 | CONFIG_IRQ_SPI1=10 | ||
| 185 | CONFIG_IRQ_SPI2=10 | ||
| 186 | CONFIG_IRQ_TWI0=11 | ||
| 187 | CONFIG_IRQ_TWI1=11 | ||
| 161 | CONFIG_BFIN548_EZKIT=y | 188 | CONFIG_BFIN548_EZKIT=y |
| 162 | # CONFIG_BFIN548_BLUETECHNIX_CM is not set | 189 | # CONFIG_BFIN548_BLUETECHNIX_CM is not set |
| 163 | 190 | ||
| @@ -180,7 +207,6 @@ CONFIG_IRQ_SPORT1_ERR=7 | |||
| 180 | CONFIG_IRQ_SPI0_ERR=7 | 207 | CONFIG_IRQ_SPI0_ERR=7 |
| 181 | CONFIG_IRQ_UART0_ERR=7 | 208 | CONFIG_IRQ_UART0_ERR=7 |
| 182 | CONFIG_IRQ_EPPI0=8 | 209 | CONFIG_IRQ_EPPI0=8 |
| 183 | CONFIG_IRQ_SPI0=10 | ||
| 184 | CONFIG_IRQ_PINT0=12 | 210 | CONFIG_IRQ_PINT0=12 |
| 185 | CONFIG_IRQ_PINT1=12 | 211 | CONFIG_IRQ_PINT1=12 |
| 186 | CONFIG_IRQ_MDMAS0=13 | 212 | CONFIG_IRQ_MDMAS0=13 |
| @@ -195,18 +221,10 @@ CONFIG_IRQ_SPI2_ERR=7 | |||
| 195 | CONFIG_IRQ_UART1_ERR=7 | 221 | CONFIG_IRQ_UART1_ERR=7 |
| 196 | CONFIG_IRQ_UART2_ERR=7 | 222 | CONFIG_IRQ_UART2_ERR=7 |
| 197 | CONFIG_IRQ_CAN0_ERR=7 | 223 | CONFIG_IRQ_CAN0_ERR=7 |
| 198 | CONFIG_IRQ_SPORT2_RX=9 | ||
| 199 | CONFIG_IRQ_SPORT2_TX=9 | ||
| 200 | CONFIG_IRQ_SPORT3_RX=9 | ||
| 201 | CONFIG_IRQ_SPORT3_TX=9 | ||
| 202 | CONFIG_IRQ_EPPI1=9 | 224 | CONFIG_IRQ_EPPI1=9 |
| 203 | CONFIG_IRQ_EPPI2=9 | 225 | CONFIG_IRQ_EPPI2=9 |
| 204 | CONFIG_IRQ_SPI1=10 | ||
| 205 | CONFIG_IRQ_SPI2=10 | ||
| 206 | CONFIG_IRQ_ATAPI_RX=10 | 226 | CONFIG_IRQ_ATAPI_RX=10 |
| 207 | CONFIG_IRQ_ATAPI_TX=10 | 227 | CONFIG_IRQ_ATAPI_TX=10 |
| 208 | CONFIG_IRQ_TWI0=11 | ||
| 209 | CONFIG_IRQ_TWI1=11 | ||
| 210 | CONFIG_IRQ_CAN0_RX=11 | 228 | CONFIG_IRQ_CAN0_RX=11 |
| 211 | CONFIG_IRQ_CAN0_TX=11 | 229 | CONFIG_IRQ_CAN0_TX=11 |
| 212 | CONFIG_IRQ_MDMAS2=13 | 230 | CONFIG_IRQ_MDMAS2=13 |
| @@ -260,7 +278,6 @@ CONFIG_BOOT_LOAD=0x1000 | |||
| 260 | # | 278 | # |
| 261 | CONFIG_CLKIN_HZ=25000000 | 279 | CONFIG_CLKIN_HZ=25000000 |
| 262 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 280 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 263 | CONFIG_MAX_MEM_SIZE=512 | ||
| 264 | CONFIG_MAX_VCO_HZ=600000000 | 281 | CONFIG_MAX_VCO_HZ=600000000 |
| 265 | CONFIG_MIN_VCO_HZ=50000000 | 282 | CONFIG_MIN_VCO_HZ=50000000 |
| 266 | CONFIG_MAX_SCLK_HZ=133333333 | 283 | CONFIG_MAX_SCLK_HZ=133333333 |
| @@ -274,10 +291,10 @@ CONFIG_HZ_250=y | |||
| 274 | # CONFIG_HZ_300 is not set | 291 | # CONFIG_HZ_300 is not set |
| 275 | # CONFIG_HZ_1000 is not set | 292 | # CONFIG_HZ_1000 is not set |
| 276 | CONFIG_HZ=250 | 293 | CONFIG_HZ=250 |
| 294 | # CONFIG_SCHED_HRTICK is not set | ||
| 277 | CONFIG_GENERIC_TIME=y | 295 | CONFIG_GENERIC_TIME=y |
| 278 | CONFIG_GENERIC_CLOCKEVENTS=y | 296 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 279 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 297 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 280 | # CONFIG_TICK_ONESHOT is not set | ||
| 281 | # CONFIG_NO_HZ is not set | 298 | # CONFIG_NO_HZ is not set |
| 282 | # CONFIG_HIGH_RES_TIMERS is not set | 299 | # CONFIG_HIGH_RES_TIMERS is not set |
| 283 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 300 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -311,6 +328,12 @@ CONFIG_ACCESS_OK_L1=y | |||
| 311 | CONFIG_CACHELINE_ALIGNED_L1=y | 328 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 312 | # CONFIG_SYSCALL_TAB_L1 is not set | 329 | # CONFIG_SYSCALL_TAB_L1 is not set |
| 313 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | 330 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set |
| 331 | CONFIG_APP_STACK_L1=y | ||
| 332 | |||
| 333 | # | ||
| 334 | # Speed Optimizations | ||
| 335 | # | ||
| 336 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 314 | CONFIG_RAMKERNEL=y | 337 | CONFIG_RAMKERNEL=y |
| 315 | # CONFIG_ROMKERNEL is not set | 338 | # CONFIG_ROMKERNEL is not set |
| 316 | CONFIG_SELECT_MEMORY_MODEL=y | 339 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -319,14 +342,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 319 | # CONFIG_SPARSEMEM_MANUAL is not set | 342 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 320 | CONFIG_FLATMEM=y | 343 | CONFIG_FLATMEM=y |
| 321 | CONFIG_FLAT_NODE_MEM_MAP=y | 344 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 322 | # CONFIG_SPARSEMEM_STATIC is not set | 345 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 323 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 324 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 346 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 325 | # CONFIG_RESOURCES_64BIT is not set | 347 | # CONFIG_RESOURCES_64BIT is not set |
| 348 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 326 | CONFIG_ZONE_DMA_FLAG=1 | 349 | CONFIG_ZONE_DMA_FLAG=1 |
| 327 | CONFIG_VIRT_TO_BUS=y | 350 | CONFIG_VIRT_TO_BUS=y |
| 328 | # CONFIG_BFIN_GPTIMERS is not set | 351 | # CONFIG_BFIN_GPTIMERS is not set |
| 329 | CONFIG_BFIN_DMA_5XX=y | ||
| 330 | # CONFIG_DMA_UNCACHED_4M is not set | 352 | # CONFIG_DMA_UNCACHED_4M is not set |
| 331 | CONFIG_DMA_UNCACHED_2M=y | 353 | CONFIG_DMA_UNCACHED_2M=y |
| 332 | # CONFIG_DMA_UNCACHED_1M is not set | 354 | # CONFIG_DMA_UNCACHED_1M is not set |
| @@ -341,7 +363,7 @@ CONFIG_BFIN_DCACHE=y | |||
| 341 | # CONFIG_BFIN_ICACHE_LOCK is not set | 363 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 342 | # CONFIG_BFIN_WB is not set | 364 | # CONFIG_BFIN_WB is not set |
| 343 | CONFIG_BFIN_WT=y | 365 | CONFIG_BFIN_WT=y |
| 344 | CONFIG_L1_MAX_PIECE=16 | 366 | # CONFIG_BFIN_L2_CACHEABLE is not set |
| 345 | # CONFIG_MPU is not set | 367 | # CONFIG_MPU is not set |
| 346 | 368 | ||
| 347 | # | 369 | # |
| @@ -373,7 +395,6 @@ CONFIG_EBIU_FCTLVAL=0x6 | |||
| 373 | # | 395 | # |
| 374 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 396 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 375 | # | 397 | # |
| 376 | # CONFIG_PCI is not set | ||
| 377 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 398 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 378 | # CONFIG_PCCARD is not set | 399 | # CONFIG_PCCARD is not set |
| 379 | 400 | ||
| @@ -384,23 +405,20 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 384 | CONFIG_BINFMT_FLAT=y | 405 | CONFIG_BINFMT_FLAT=y |
| 385 | CONFIG_BINFMT_ZFLAT=y | 406 | CONFIG_BINFMT_ZFLAT=y |
| 386 | # CONFIG_BINFMT_SHARED_FLAT is not set | 407 | # CONFIG_BINFMT_SHARED_FLAT is not set |
| 408 | # CONFIG_HAVE_AOUT is not set | ||
| 387 | # CONFIG_BINFMT_MISC is not set | 409 | # CONFIG_BINFMT_MISC is not set |
| 388 | 410 | ||
| 389 | # | 411 | # |
| 390 | # Power management options | 412 | # Power management options |
| 391 | # | 413 | # |
| 392 | # CONFIG_PM is not set | 414 | # CONFIG_PM is not set |
| 393 | CONFIG_SUSPEND_UP_POSSIBLE=y | 415 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 394 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | 416 | # CONFIG_PM_WAKEUP_BY_GPIO is not set |
| 395 | 417 | ||
| 396 | # | 418 | # |
| 397 | # CPU Frequency scaling | 419 | # CPU Frequency scaling |
| 398 | # | 420 | # |
| 399 | # CONFIG_CPU_FREQ is not set | 421 | # CONFIG_CPU_FREQ is not set |
| 400 | |||
| 401 | # | ||
| 402 | # Networking | ||
| 403 | # | ||
| 404 | CONFIG_NET=y | 422 | CONFIG_NET=y |
| 405 | 423 | ||
| 406 | # | 424 | # |
| @@ -413,6 +431,7 @@ CONFIG_XFRM=y | |||
| 413 | # CONFIG_XFRM_USER is not set | 431 | # CONFIG_XFRM_USER is not set |
| 414 | # CONFIG_XFRM_SUB_POLICY is not set | 432 | # CONFIG_XFRM_SUB_POLICY is not set |
| 415 | # CONFIG_XFRM_MIGRATE is not set | 433 | # CONFIG_XFRM_MIGRATE is not set |
| 434 | # CONFIG_XFRM_STATISTICS is not set | ||
| 416 | # CONFIG_NET_KEY is not set | 435 | # CONFIG_NET_KEY is not set |
| 417 | CONFIG_INET=y | 436 | CONFIG_INET=y |
| 418 | # CONFIG_IP_MULTICAST is not set | 437 | # CONFIG_IP_MULTICAST is not set |
| @@ -442,8 +461,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 442 | CONFIG_DEFAULT_TCP_CONG="cubic" | 461 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 443 | # CONFIG_TCP_MD5SIG is not set | 462 | # CONFIG_TCP_MD5SIG is not set |
| 444 | # CONFIG_IPV6 is not set | 463 | # CONFIG_IPV6 is not set |
| 445 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 446 | # CONFIG_INET6_TUNNEL is not set | ||
| 447 | # CONFIG_NETLABEL is not set | 464 | # CONFIG_NETLABEL is not set |
| 448 | # CONFIG_NETWORK_SECMARK is not set | 465 | # CONFIG_NETWORK_SECMARK is not set |
| 449 | # CONFIG_NETFILTER is not set | 466 | # CONFIG_NETFILTER is not set |
| @@ -452,6 +469,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 452 | # CONFIG_TIPC is not set | 469 | # CONFIG_TIPC is not set |
| 453 | # CONFIG_ATM is not set | 470 | # CONFIG_ATM is not set |
| 454 | # CONFIG_BRIDGE is not set | 471 | # CONFIG_BRIDGE is not set |
| 472 | # CONFIG_NET_DSA is not set | ||
| 455 | # CONFIG_VLAN_8021Q is not set | 473 | # CONFIG_VLAN_8021Q is not set |
| 456 | # CONFIG_DECNET is not set | 474 | # CONFIG_DECNET is not set |
| 457 | # CONFIG_LLC2 is not set | 475 | # CONFIG_LLC2 is not set |
| @@ -468,6 +486,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 468 | # | 486 | # |
| 469 | # CONFIG_NET_PKTGEN is not set | 487 | # CONFIG_NET_PKTGEN is not set |
| 470 | # CONFIG_HAMRADIO is not set | 488 | # CONFIG_HAMRADIO is not set |
| 489 | # CONFIG_CAN is not set | ||
| 471 | CONFIG_IRDA=m | 490 | CONFIG_IRDA=m |
| 472 | 491 | ||
| 473 | # | 492 | # |
| @@ -493,9 +512,9 @@ CONFIG_IRCOMM=m | |||
| 493 | # | 512 | # |
| 494 | CONFIG_IRTTY_SIR=m | 513 | CONFIG_IRTTY_SIR=m |
| 495 | CONFIG_BFIN_SIR=m | 514 | CONFIG_BFIN_SIR=m |
| 515 | CONFIG_BFIN_SIR3=y | ||
| 496 | # CONFIG_BFIN_SIR0 is not set | 516 | # CONFIG_BFIN_SIR0 is not set |
| 497 | # CONFIG_BFIN_SIR2 is not set | 517 | # CONFIG_BFIN_SIR2 is not set |
| 498 | CONFIG_BFIN_SIR3=y | ||
| 499 | CONFIG_SIR_BFIN_DMA=y | 518 | CONFIG_SIR_BFIN_DMA=y |
| 500 | # CONFIG_SIR_BFIN_PIO is not set | 519 | # CONFIG_SIR_BFIN_PIO is not set |
| 501 | 520 | ||
| @@ -508,15 +527,6 @@ CONFIG_SIR_BFIN_DMA=y | |||
| 508 | # CONFIG_KS959_DONGLE is not set | 527 | # CONFIG_KS959_DONGLE is not set |
| 509 | 528 | ||
| 510 | # | 529 | # |
| 511 | # Old SIR device drivers | ||
| 512 | # | ||
| 513 | # CONFIG_IRPORT_SIR is not set | ||
| 514 | |||
| 515 | # | ||
| 516 | # Old Serial dongle support | ||
| 517 | # | ||
| 518 | |||
| 519 | # | ||
| 520 | # FIR device drivers | 530 | # FIR device drivers |
| 521 | # | 531 | # |
| 522 | # CONFIG_USB_IRDA is not set | 532 | # CONFIG_USB_IRDA is not set |
| @@ -524,11 +534,10 @@ CONFIG_SIR_BFIN_DMA=y | |||
| 524 | # CONFIG_MCS_FIR is not set | 534 | # CONFIG_MCS_FIR is not set |
| 525 | # CONFIG_BT is not set | 535 | # CONFIG_BT is not set |
| 526 | # CONFIG_AF_RXRPC is not set | 536 | # CONFIG_AF_RXRPC is not set |
| 527 | 537 | # CONFIG_PHONET is not set | |
| 528 | # | 538 | CONFIG_WIRELESS=y |
| 529 | # Wireless | ||
| 530 | # | ||
| 531 | # CONFIG_CFG80211 is not set | 539 | # CONFIG_CFG80211 is not set |
| 540 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 532 | # CONFIG_WIRELESS_EXT is not set | 541 | # CONFIG_WIRELESS_EXT is not set |
| 533 | # CONFIG_MAC80211 is not set | 542 | # CONFIG_MAC80211 is not set |
| 534 | # CONFIG_IEEE80211 is not set | 543 | # CONFIG_IEEE80211 is not set |
| @@ -546,6 +555,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 546 | CONFIG_STANDALONE=y | 555 | CONFIG_STANDALONE=y |
| 547 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 556 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 548 | # CONFIG_FW_LOADER is not set | 557 | # CONFIG_FW_LOADER is not set |
| 558 | # CONFIG_DEBUG_DRIVER is not set | ||
| 559 | # CONFIG_DEBUG_DEVRES is not set | ||
| 549 | # CONFIG_SYS_HYPERVISOR is not set | 560 | # CONFIG_SYS_HYPERVISOR is not set |
| 550 | # CONFIG_CONNECTOR is not set | 561 | # CONFIG_CONNECTOR is not set |
| 551 | CONFIG_MTD=y | 562 | CONFIG_MTD=y |
| @@ -554,6 +565,7 @@ CONFIG_MTD=y | |||
| 554 | CONFIG_MTD_PARTITIONS=y | 565 | CONFIG_MTD_PARTITIONS=y |
| 555 | # CONFIG_MTD_REDBOOT_PARTS is not set | 566 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 556 | CONFIG_MTD_CMDLINE_PARTS=y | 567 | CONFIG_MTD_CMDLINE_PARTS=y |
| 568 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 557 | 569 | ||
| 558 | # | 570 | # |
| 559 | # User Modules And Translation Layers | 571 | # User Modules And Translation Layers |
| @@ -601,6 +613,7 @@ CONFIG_MTD_PHYSMAP=y | |||
| 601 | CONFIG_MTD_PHYSMAP_START=0x20000000 | 613 | CONFIG_MTD_PHYSMAP_START=0x20000000 |
| 602 | CONFIG_MTD_PHYSMAP_LEN=0 | 614 | CONFIG_MTD_PHYSMAP_LEN=0 |
| 603 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | 615 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 |
| 616 | # CONFIG_MTD_GPIO_ADDR is not set | ||
| 604 | # CONFIG_MTD_UCLINUX is not set | 617 | # CONFIG_MTD_UCLINUX is not set |
| 605 | # CONFIG_MTD_PLATRAM is not set | 618 | # CONFIG_MTD_PLATRAM is not set |
| 606 | 619 | ||
| @@ -608,7 +621,8 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | |||
| 608 | # Self-contained MTD device drivers | 621 | # Self-contained MTD device drivers |
| 609 | # | 622 | # |
| 610 | # CONFIG_MTD_DATAFLASH is not set | 623 | # CONFIG_MTD_DATAFLASH is not set |
| 611 | # CONFIG_MTD_M25P80 is not set | 624 | CONFIG_MTD_M25P80=y |
| 625 | CONFIG_M25PXX_USE_FAST_READ=y | ||
| 612 | # CONFIG_MTD_SLRAM is not set | 626 | # CONFIG_MTD_SLRAM is not set |
| 613 | # CONFIG_MTD_PHRAM is not set | 627 | # CONFIG_MTD_PHRAM is not set |
| 614 | # CONFIG_MTD_MTDRAM is not set | 628 | # CONFIG_MTD_MTDRAM is not set |
| @@ -648,11 +662,14 @@ CONFIG_BLK_DEV=y | |||
| 648 | CONFIG_BLK_DEV_RAM=y | 662 | CONFIG_BLK_DEV_RAM=y |
| 649 | CONFIG_BLK_DEV_RAM_COUNT=16 | 663 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 650 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 664 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 651 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 665 | # CONFIG_BLK_DEV_XIP is not set |
| 652 | # CONFIG_CDROM_PKTCDVD is not set | 666 | # CONFIG_CDROM_PKTCDVD is not set |
| 653 | # CONFIG_ATA_OVER_ETH is not set | 667 | # CONFIG_ATA_OVER_ETH is not set |
| 668 | # CONFIG_BLK_DEV_HD is not set | ||
| 654 | CONFIG_MISC_DEVICES=y | 669 | CONFIG_MISC_DEVICES=y |
| 655 | # CONFIG_EEPROM_93CX6 is not set | 670 | # CONFIG_EEPROM_93CX6 is not set |
| 671 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 672 | CONFIG_HAVE_IDE=y | ||
| 656 | # CONFIG_IDE is not set | 673 | # CONFIG_IDE is not set |
| 657 | 674 | ||
| 658 | # | 675 | # |
| @@ -696,13 +713,16 @@ CONFIG_SCSI_WAIT_SCAN=m | |||
| 696 | CONFIG_SCSI_LOWLEVEL=y | 713 | CONFIG_SCSI_LOWLEVEL=y |
| 697 | # CONFIG_ISCSI_TCP is not set | 714 | # CONFIG_ISCSI_TCP is not set |
| 698 | # CONFIG_SCSI_DEBUG is not set | 715 | # CONFIG_SCSI_DEBUG is not set |
| 716 | # CONFIG_SCSI_DH is not set | ||
| 699 | CONFIG_ATA=y | 717 | CONFIG_ATA=y |
| 700 | # CONFIG_ATA_NONSTANDARD is not set | 718 | # CONFIG_ATA_NONSTANDARD is not set |
| 719 | CONFIG_SATA_PMP=y | ||
| 720 | CONFIG_ATA_SFF=y | ||
| 721 | # CONFIG_SATA_MV is not set | ||
| 701 | # CONFIG_PATA_PLATFORM is not set | 722 | # CONFIG_PATA_PLATFORM is not set |
| 702 | CONFIG_PATA_BF54X=y | 723 | CONFIG_PATA_BF54X=y |
| 703 | # CONFIG_MD is not set | 724 | # CONFIG_MD is not set |
| 704 | CONFIG_NETDEVICES=y | 725 | CONFIG_NETDEVICES=y |
| 705 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 706 | # CONFIG_DUMMY is not set | 726 | # CONFIG_DUMMY is not set |
| 707 | # CONFIG_BONDING is not set | 727 | # CONFIG_BONDING is not set |
| 708 | # CONFIG_MACVLAN is not set | 728 | # CONFIG_MACVLAN is not set |
| @@ -715,11 +735,14 @@ CONFIG_MII=y | |||
| 715 | # CONFIG_SMC91X is not set | 735 | # CONFIG_SMC91X is not set |
| 716 | CONFIG_SMSC911X=y | 736 | CONFIG_SMSC911X=y |
| 717 | # CONFIG_DM9000 is not set | 737 | # CONFIG_DM9000 is not set |
| 738 | # CONFIG_ENC28J60 is not set | ||
| 718 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 739 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 719 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 740 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 720 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 741 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 721 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 742 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 722 | # CONFIG_B44 is not set | 743 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set |
| 744 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 745 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 723 | CONFIG_NETDEV_1000=y | 746 | CONFIG_NETDEV_1000=y |
| 724 | # CONFIG_AX88180 is not set | 747 | # CONFIG_AX88180 is not set |
| 725 | CONFIG_NETDEV_10000=y | 748 | CONFIG_NETDEV_10000=y |
| @@ -729,6 +752,7 @@ CONFIG_NETDEV_10000=y | |||
| 729 | # | 752 | # |
| 730 | # CONFIG_WLAN_PRE80211 is not set | 753 | # CONFIG_WLAN_PRE80211 is not set |
| 731 | # CONFIG_WLAN_80211 is not set | 754 | # CONFIG_WLAN_80211 is not set |
| 755 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 732 | 756 | ||
| 733 | # | 757 | # |
| 734 | # USB Network Adapters | 758 | # USB Network Adapters |
| @@ -741,7 +765,6 @@ CONFIG_NETDEV_10000=y | |||
| 741 | # CONFIG_WAN is not set | 765 | # CONFIG_WAN is not set |
| 742 | # CONFIG_PPP is not set | 766 | # CONFIG_PPP is not set |
| 743 | # CONFIG_SLIP is not set | 767 | # CONFIG_SLIP is not set |
| 744 | # CONFIG_SHAPER is not set | ||
| 745 | # CONFIG_NETCONSOLE is not set | 768 | # CONFIG_NETCONSOLE is not set |
| 746 | # CONFIG_NETPOLL is not set | 769 | # CONFIG_NETPOLL is not set |
| 747 | # CONFIG_NET_POLL_CONTROLLER is not set | 770 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -752,7 +775,7 @@ CONFIG_NETDEV_10000=y | |||
| 752 | # Input device support | 775 | # Input device support |
| 753 | # | 776 | # |
| 754 | CONFIG_INPUT=y | 777 | CONFIG_INPUT=y |
| 755 | # CONFIG_INPUT_FF_MEMLESS is not set | 778 | CONFIG_INPUT_FF_MEMLESS=m |
| 756 | # CONFIG_INPUT_POLLDEV is not set | 779 | # CONFIG_INPUT_POLLDEV is not set |
| 757 | 780 | ||
| 758 | # | 781 | # |
| @@ -776,30 +799,37 @@ CONFIG_INPUT_KEYBOARD=y | |||
| 776 | # CONFIG_KEYBOARD_GPIO is not set | 799 | # CONFIG_KEYBOARD_GPIO is not set |
| 777 | CONFIG_KEYBOARD_BFIN=y | 800 | CONFIG_KEYBOARD_BFIN=y |
| 778 | # CONFIG_KEYBOARD_OPENCORES is not set | 801 | # CONFIG_KEYBOARD_OPENCORES is not set |
| 802 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
| 779 | # CONFIG_INPUT_MOUSE is not set | 803 | # CONFIG_INPUT_MOUSE is not set |
| 780 | # CONFIG_INPUT_JOYSTICK is not set | 804 | # CONFIG_INPUT_JOYSTICK is not set |
| 781 | # CONFIG_INPUT_TABLET is not set | 805 | # CONFIG_INPUT_TABLET is not set |
| 782 | CONFIG_INPUT_TOUCHSCREEN=y | 806 | CONFIG_INPUT_TOUCHSCREEN=y |
| 783 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | 807 | # CONFIG_TOUCHSCREEN_ADS7846 is not set |
| 784 | CONFIG_TOUCHSCREEN_AD7877=m | 808 | CONFIG_TOUCHSCREEN_AD7877=m |
| 809 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 810 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
| 811 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 785 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 812 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 786 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 813 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 787 | # CONFIG_TOUCHSCREEN_ELO is not set | 814 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 788 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 815 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 816 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 789 | # CONFIG_TOUCHSCREEN_MK712 is not set | 817 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| 790 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | 818 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set |
| 791 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 819 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 792 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 820 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 793 | # CONFIG_TOUCHSCREEN_UCB1400 is not set | 821 | # CONFIG_TOUCHSCREEN_WM97XX is not set |
| 794 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 822 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 823 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 795 | CONFIG_INPUT_MISC=y | 824 | CONFIG_INPUT_MISC=y |
| 796 | # CONFIG_INPUT_ATI_REMOTE is not set | 825 | # CONFIG_INPUT_ATI_REMOTE is not set |
| 797 | # CONFIG_INPUT_ATI_REMOTE2 is not set | 826 | # CONFIG_INPUT_ATI_REMOTE2 is not set |
| 798 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | 827 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set |
| 799 | # CONFIG_INPUT_POWERMATE is not set | 828 | # CONFIG_INPUT_POWERMATE is not set |
| 800 | # CONFIG_INPUT_YEALINK is not set | 829 | # CONFIG_INPUT_YEALINK is not set |
| 830 | # CONFIG_INPUT_CM109 is not set | ||
| 801 | # CONFIG_INPUT_UINPUT is not set | 831 | # CONFIG_INPUT_UINPUT is not set |
| 802 | # CONFIG_TWI_KEYPAD is not set | 832 | # CONFIG_CONFIG_INPUT_PCF8574 is not set |
| 803 | 833 | ||
| 804 | # | 834 | # |
| 805 | # Hardware I/O ports | 835 | # Hardware I/O ports |
| @@ -815,16 +845,18 @@ CONFIG_INPUT_MISC=y | |||
| 815 | # CONFIG_BF5xx_PPIFCD is not set | 845 | # CONFIG_BF5xx_PPIFCD is not set |
| 816 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 846 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 817 | # CONFIG_BF5xx_PPI is not set | 847 | # CONFIG_BF5xx_PPI is not set |
| 818 | CONFIG_BFIN_OTP=y | ||
| 819 | # CONFIG_BFIN_OTP_WRITE_ENABLE is not set | ||
| 820 | # CONFIG_BFIN_SPORT is not set | 848 | # CONFIG_BFIN_SPORT is not set |
| 821 | # CONFIG_BFIN_TIMER_LATENCY is not set | 849 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 822 | # CONFIG_TWI_LCD is not set | 850 | # CONFIG_TWI_LCD is not set |
| 851 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 823 | CONFIG_SIMPLE_GPIO=m | 852 | CONFIG_SIMPLE_GPIO=m |
| 824 | CONFIG_VT=y | 853 | CONFIG_VT=y |
| 854 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 825 | CONFIG_VT_CONSOLE=y | 855 | CONFIG_VT_CONSOLE=y |
| 826 | CONFIG_HW_CONSOLE=y | 856 | CONFIG_HW_CONSOLE=y |
| 827 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 857 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 858 | # CONFIG_DEVKMEM is not set | ||
| 859 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 828 | # CONFIG_SERIAL_NONSTANDARD is not set | 860 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 829 | 861 | ||
| 830 | # | 862 | # |
| @@ -849,6 +881,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y | |||
| 849 | # CONFIG_SERIAL_BFIN_SPORT is not set | 881 | # CONFIG_SERIAL_BFIN_SPORT is not set |
| 850 | CONFIG_UNIX98_PTYS=y | 882 | CONFIG_UNIX98_PTYS=y |
| 851 | # CONFIG_LEGACY_PTYS is not set | 883 | # CONFIG_LEGACY_PTYS is not set |
| 884 | CONFIG_BFIN_OTP=y | ||
| 885 | # CONFIG_BFIN_OTP_WRITE_ENABLE is not set | ||
| 852 | 886 | ||
| 853 | # | 887 | # |
| 854 | # CAN, the car bus and industrial fieldbus | 888 | # CAN, the car bus and industrial fieldbus |
| @@ -856,44 +890,49 @@ CONFIG_UNIX98_PTYS=y | |||
| 856 | # CONFIG_CAN4LINUX is not set | 890 | # CONFIG_CAN4LINUX is not set |
| 857 | # CONFIG_IPMI_HANDLER is not set | 891 | # CONFIG_IPMI_HANDLER is not set |
| 858 | # CONFIG_HW_RANDOM is not set | 892 | # CONFIG_HW_RANDOM is not set |
| 859 | # CONFIG_GEN_RTC is not set | ||
| 860 | # CONFIG_R3964 is not set | 893 | # CONFIG_R3964 is not set |
| 861 | # CONFIG_RAW_DRIVER is not set | 894 | # CONFIG_RAW_DRIVER is not set |
| 862 | # CONFIG_TCG_TPM is not set | 895 | # CONFIG_TCG_TPM is not set |
| 863 | CONFIG_I2C=y | 896 | CONFIG_I2C=y |
| 864 | CONFIG_I2C_BOARDINFO=y | 897 | CONFIG_I2C_BOARDINFO=y |
| 865 | CONFIG_I2C_CHARDEV=y | 898 | CONFIG_I2C_CHARDEV=y |
| 899 | CONFIG_I2C_HELPER_AUTO=y | ||
| 866 | 900 | ||
| 867 | # | 901 | # |
| 868 | # I2C Algorithms | 902 | # I2C Hardware Bus support |
| 869 | # | 903 | # |
| 870 | # CONFIG_I2C_ALGOBIT is not set | ||
| 871 | # CONFIG_I2C_ALGOPCF is not set | ||
| 872 | # CONFIG_I2C_ALGOPCA is not set | ||
| 873 | 904 | ||
| 874 | # | 905 | # |
| 875 | # I2C Hardware Bus support | 906 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 876 | # | 907 | # |
| 877 | CONFIG_I2C_BLACKFIN_TWI=y | 908 | CONFIG_I2C_BLACKFIN_TWI=y |
| 878 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | 909 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 |
| 879 | # CONFIG_I2C_GPIO is not set | 910 | # CONFIG_I2C_GPIO is not set |
| 880 | # CONFIG_I2C_OCORES is not set | 911 | # CONFIG_I2C_OCORES is not set |
| 881 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 882 | # CONFIG_I2C_SIMTEC is not set | 912 | # CONFIG_I2C_SIMTEC is not set |
| 913 | |||
| 914 | # | ||
| 915 | # External I2C/SMBus adapter drivers | ||
| 916 | # | ||
| 917 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 883 | # CONFIG_I2C_TAOS_EVM is not set | 918 | # CONFIG_I2C_TAOS_EVM is not set |
| 884 | # CONFIG_I2C_STUB is not set | ||
| 885 | # CONFIG_I2C_TINY_USB is not set | 919 | # CONFIG_I2C_TINY_USB is not set |
| 886 | 920 | ||
| 887 | # | 921 | # |
| 922 | # Other I2C/SMBus bus drivers | ||
| 923 | # | ||
| 924 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 925 | # CONFIG_I2C_STUB is not set | ||
| 926 | |||
| 927 | # | ||
| 888 | # Miscellaneous I2C Chip support | 928 | # Miscellaneous I2C Chip support |
| 889 | # | 929 | # |
| 890 | # CONFIG_SENSORS_DS1337 is not set | ||
| 891 | # CONFIG_SENSORS_DS1374 is not set | ||
| 892 | # CONFIG_DS1682 is not set | 930 | # CONFIG_DS1682 is not set |
| 931 | # CONFIG_AT24 is not set | ||
| 893 | # CONFIG_SENSORS_AD5252 is not set | 932 | # CONFIG_SENSORS_AD5252 is not set |
| 894 | # CONFIG_SENSORS_EEPROM is not set | 933 | # CONFIG_SENSORS_EEPROM is not set |
| 895 | # CONFIG_SENSORS_PCF8574 is not set | 934 | # CONFIG_SENSORS_PCF8574 is not set |
| 896 | # CONFIG_SENSORS_PCF8575 is not set | 935 | # CONFIG_PCF8575 is not set |
| 897 | # CONFIG_SENSORS_PCA9539 is not set | 936 | # CONFIG_SENSORS_PCA9539 is not set |
| 898 | # CONFIG_SENSORS_PCF8591 is not set | 937 | # CONFIG_SENSORS_PCF8591 is not set |
| 899 | # CONFIG_SENSORS_MAX6875 is not set | 938 | # CONFIG_SENSORS_MAX6875 is not set |
| @@ -902,17 +941,15 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | |||
| 902 | # CONFIG_I2C_DEBUG_ALGO is not set | 941 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 903 | # CONFIG_I2C_DEBUG_BUS is not set | 942 | # CONFIG_I2C_DEBUG_BUS is not set |
| 904 | # CONFIG_I2C_DEBUG_CHIP is not set | 943 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 905 | |||
| 906 | # | ||
| 907 | # SPI support | ||
| 908 | # | ||
| 909 | CONFIG_SPI=y | 944 | CONFIG_SPI=y |
| 945 | # CONFIG_SPI_DEBUG is not set | ||
| 910 | CONFIG_SPI_MASTER=y | 946 | CONFIG_SPI_MASTER=y |
| 911 | 947 | ||
| 912 | # | 948 | # |
| 913 | # SPI Master Controller Drivers | 949 | # SPI Master Controller Drivers |
| 914 | # | 950 | # |
| 915 | CONFIG_SPI_BFIN=y | 951 | CONFIG_SPI_BFIN=y |
| 952 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 916 | # CONFIG_SPI_BITBANG is not set | 953 | # CONFIG_SPI_BITBANG is not set |
| 917 | 954 | ||
| 918 | # | 955 | # |
| @@ -921,11 +958,15 @@ CONFIG_SPI_BFIN=y | |||
| 921 | # CONFIG_SPI_AT25 is not set | 958 | # CONFIG_SPI_AT25 is not set |
| 922 | # CONFIG_SPI_SPIDEV is not set | 959 | # CONFIG_SPI_SPIDEV is not set |
| 923 | # CONFIG_SPI_TLE62X0 is not set | 960 | # CONFIG_SPI_TLE62X0 is not set |
| 961 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 962 | # CONFIG_GPIOLIB is not set | ||
| 924 | # CONFIG_W1 is not set | 963 | # CONFIG_W1 is not set |
| 925 | # CONFIG_POWER_SUPPLY is not set | 964 | # CONFIG_POWER_SUPPLY is not set |
| 926 | CONFIG_HWMON=y | 965 | CONFIG_HWMON=y |
| 927 | # CONFIG_HWMON_VID is not set | 966 | # CONFIG_HWMON_VID is not set |
| 967 | # CONFIG_SENSORS_AD7414 is not set | ||
| 928 | # CONFIG_SENSORS_AD7418 is not set | 968 | # CONFIG_SENSORS_AD7418 is not set |
| 969 | # CONFIG_SENSORS_ADCXX is not set | ||
| 929 | # CONFIG_SENSORS_ADM1021 is not set | 970 | # CONFIG_SENSORS_ADM1021 is not set |
| 930 | # CONFIG_SENSORS_ADM1025 is not set | 971 | # CONFIG_SENSORS_ADM1025 is not set |
| 931 | # CONFIG_SENSORS_ADM1026 is not set | 972 | # CONFIG_SENSORS_ADM1026 is not set |
| @@ -933,6 +974,7 @@ CONFIG_HWMON=y | |||
| 933 | # CONFIG_SENSORS_ADM1031 is not set | 974 | # CONFIG_SENSORS_ADM1031 is not set |
| 934 | # CONFIG_SENSORS_ADM9240 is not set | 975 | # CONFIG_SENSORS_ADM9240 is not set |
| 935 | # CONFIG_SENSORS_ADT7470 is not set | 976 | # CONFIG_SENSORS_ADT7470 is not set |
| 977 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 936 | # CONFIG_SENSORS_ATXP1 is not set | 978 | # CONFIG_SENSORS_ATXP1 is not set |
| 937 | # CONFIG_SENSORS_DS1621 is not set | 979 | # CONFIG_SENSORS_DS1621 is not set |
| 938 | # CONFIG_SENSORS_F71805F is not set | 980 | # CONFIG_SENSORS_F71805F is not set |
| @@ -953,6 +995,7 @@ CONFIG_HWMON=y | |||
| 953 | # CONFIG_SENSORS_LM90 is not set | 995 | # CONFIG_SENSORS_LM90 is not set |
| 954 | # CONFIG_SENSORS_LM92 is not set | 996 | # CONFIG_SENSORS_LM92 is not set |
| 955 | # CONFIG_SENSORS_LM93 is not set | 997 | # CONFIG_SENSORS_LM93 is not set |
| 998 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 956 | # CONFIG_SENSORS_MAX1619 is not set | 999 | # CONFIG_SENSORS_MAX1619 is not set |
| 957 | # CONFIG_SENSORS_MAX6650 is not set | 1000 | # CONFIG_SENSORS_MAX6650 is not set |
| 958 | # CONFIG_SENSORS_PC87360 is not set | 1001 | # CONFIG_SENSORS_PC87360 is not set |
| @@ -961,6 +1004,7 @@ CONFIG_HWMON=y | |||
| 961 | # CONFIG_SENSORS_SMSC47M1 is not set | 1004 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 962 | # CONFIG_SENSORS_SMSC47M192 is not set | 1005 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 963 | # CONFIG_SENSORS_SMSC47B397 is not set | 1006 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 1007 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 964 | # CONFIG_SENSORS_THMC50 is not set | 1008 | # CONFIG_SENSORS_THMC50 is not set |
| 965 | # CONFIG_SENSORS_VT1211 is not set | 1009 | # CONFIG_SENSORS_VT1211 is not set |
| 966 | # CONFIG_SENSORS_W83781D is not set | 1010 | # CONFIG_SENSORS_W83781D is not set |
| @@ -968,9 +1012,12 @@ CONFIG_HWMON=y | |||
| 968 | # CONFIG_SENSORS_W83792D is not set | 1012 | # CONFIG_SENSORS_W83792D is not set |
| 969 | # CONFIG_SENSORS_W83793 is not set | 1013 | # CONFIG_SENSORS_W83793 is not set |
| 970 | # CONFIG_SENSORS_W83L785TS is not set | 1014 | # CONFIG_SENSORS_W83L785TS is not set |
| 1015 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 971 | # CONFIG_SENSORS_W83627HF is not set | 1016 | # CONFIG_SENSORS_W83627HF is not set |
| 972 | # CONFIG_SENSORS_W83627EHF is not set | 1017 | # CONFIG_SENSORS_W83627EHF is not set |
| 973 | # CONFIG_HWMON_DEBUG_CHIP is not set | 1018 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 1019 | # CONFIG_THERMAL is not set | ||
| 1020 | # CONFIG_THERMAL_HWMON is not set | ||
| 974 | CONFIG_WATCHDOG=y | 1021 | CONFIG_WATCHDOG=y |
| 975 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 1022 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 976 | 1023 | ||
| @@ -986,23 +1033,30 @@ CONFIG_BFIN_WDT=y | |||
| 986 | # CONFIG_USBPCWATCHDOG is not set | 1033 | # CONFIG_USBPCWATCHDOG is not set |
| 987 | 1034 | ||
| 988 | # | 1035 | # |
| 989 | # Sonics Silicon Backplane | ||
| 990 | # | ||
| 991 | CONFIG_SSB_POSSIBLE=y | ||
| 992 | # CONFIG_SSB is not set | ||
| 993 | |||
| 994 | # | ||
| 995 | # Multifunction device drivers | 1036 | # Multifunction device drivers |
| 996 | # | 1037 | # |
| 1038 | # CONFIG_MFD_CORE is not set | ||
| 997 | # CONFIG_MFD_SM501 is not set | 1039 | # CONFIG_MFD_SM501 is not set |
| 1040 | # CONFIG_HTC_PASIC3 is not set | ||
| 1041 | # CONFIG_MFD_TMIO is not set | ||
| 1042 | # CONFIG_MFD_WM8400 is not set | ||
| 1043 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 998 | 1044 | ||
| 999 | # | 1045 | # |
| 1000 | # Multimedia devices | 1046 | # Multimedia devices |
| 1001 | # | 1047 | # |
| 1048 | |||
| 1049 | # | ||
| 1050 | # Multimedia core support | ||
| 1051 | # | ||
| 1002 | # CONFIG_VIDEO_DEV is not set | 1052 | # CONFIG_VIDEO_DEV is not set |
| 1003 | # CONFIG_DVB_CORE is not set | 1053 | # CONFIG_DVB_CORE is not set |
| 1054 | # CONFIG_VIDEO_MEDIA is not set | ||
| 1055 | |||
| 1056 | # | ||
| 1057 | # Multimedia drivers | ||
| 1058 | # | ||
| 1004 | # CONFIG_DAB is not set | 1059 | # CONFIG_DAB is not set |
| 1005 | # CONFIG_USB_DABUSB is not set | ||
| 1006 | 1060 | ||
| 1007 | # | 1061 | # |
| 1008 | # Graphics support | 1062 | # Graphics support |
| @@ -1012,6 +1066,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1012 | CONFIG_FB=y | 1066 | CONFIG_FB=y |
| 1013 | CONFIG_FIRMWARE_EDID=y | 1067 | CONFIG_FIRMWARE_EDID=y |
| 1014 | # CONFIG_FB_DDC is not set | 1068 | # CONFIG_FB_DDC is not set |
| 1069 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1015 | CONFIG_FB_CFB_FILLRECT=y | 1070 | CONFIG_FB_CFB_FILLRECT=y |
| 1016 | CONFIG_FB_CFB_COPYAREA=y | 1071 | CONFIG_FB_CFB_COPYAREA=y |
| 1017 | CONFIG_FB_CFB_IMAGEBLIT=y | 1072 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -1019,8 +1074,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 1019 | # CONFIG_FB_SYS_FILLRECT is not set | 1074 | # CONFIG_FB_SYS_FILLRECT is not set |
| 1020 | # CONFIG_FB_SYS_COPYAREA is not set | 1075 | # CONFIG_FB_SYS_COPYAREA is not set |
| 1021 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 1076 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 1077 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 1022 | # CONFIG_FB_SYS_FOPS is not set | 1078 | # CONFIG_FB_SYS_FOPS is not set |
| 1023 | CONFIG_FB_DEFERRED_IO=y | ||
| 1024 | # CONFIG_FB_SVGALIB is not set | 1079 | # CONFIG_FB_SVGALIB is not set |
| 1025 | # CONFIG_FB_MACMODES is not set | 1080 | # CONFIG_FB_MACMODES is not set |
| 1026 | # CONFIG_FB_BACKLIGHT is not set | 1081 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -1032,9 +1087,11 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 1032 | # | 1087 | # |
| 1033 | CONFIG_FB_BF54X_LQ043=y | 1088 | CONFIG_FB_BF54X_LQ043=y |
| 1034 | # CONFIG_FB_BFIN_T350MCQB is not set | 1089 | # CONFIG_FB_BFIN_T350MCQB is not set |
| 1090 | # CONFIG_FB_BFIN_LQ035Q1 is not set | ||
| 1035 | # CONFIG_FB_BFIN_7393 is not set | 1091 | # CONFIG_FB_BFIN_7393 is not set |
| 1036 | # CONFIG_FB_S1D13XXX is not set | 1092 | # CONFIG_FB_S1D13XXX is not set |
| 1037 | # CONFIG_FB_VIRTUAL is not set | 1093 | # CONFIG_FB_VIRTUAL is not set |
| 1094 | # CONFIG_FB_METRONOME is not set | ||
| 1038 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 1095 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set |
| 1039 | 1096 | ||
| 1040 | # | 1097 | # |
| @@ -1066,15 +1123,8 @@ CONFIG_LOGO=y | |||
| 1066 | # CONFIG_LOGO_LINUX_CLUT224 is not set | 1123 | # CONFIG_LOGO_LINUX_CLUT224 is not set |
| 1067 | # CONFIG_LOGO_BLACKFIN_VGA16 is not set | 1124 | # CONFIG_LOGO_BLACKFIN_VGA16 is not set |
| 1068 | CONFIG_LOGO_BLACKFIN_CLUT224=y | 1125 | CONFIG_LOGO_BLACKFIN_CLUT224=y |
| 1069 | |||
| 1070 | # | ||
| 1071 | # Sound | ||
| 1072 | # | ||
| 1073 | CONFIG_SOUND=y | 1126 | CONFIG_SOUND=y |
| 1074 | 1127 | CONFIG_SOUND_OSS_CORE=y | |
| 1075 | # | ||
| 1076 | # Advanced Linux Sound Architecture | ||
| 1077 | # | ||
| 1078 | CONFIG_SND=y | 1128 | CONFIG_SND=y |
| 1079 | CONFIG_SND_TIMER=y | 1129 | CONFIG_SND_TIMER=y |
| 1080 | CONFIG_SND_PCM=y | 1130 | CONFIG_SND_PCM=y |
| @@ -1088,56 +1138,35 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 1088 | CONFIG_SND_VERBOSE_PROCFS=y | 1138 | CONFIG_SND_VERBOSE_PROCFS=y |
| 1089 | # CONFIG_SND_VERBOSE_PRINTK is not set | 1139 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 1090 | # CONFIG_SND_DEBUG is not set | 1140 | # CONFIG_SND_DEBUG is not set |
| 1091 | 1141 | CONFIG_SND_DRIVERS=y | |
| 1092 | # | ||
| 1093 | # Generic devices | ||
| 1094 | # | ||
| 1095 | # CONFIG_SND_DUMMY is not set | 1142 | # CONFIG_SND_DUMMY is not set |
| 1096 | # CONFIG_SND_MTPAV is not set | 1143 | # CONFIG_SND_MTPAV is not set |
| 1097 | # CONFIG_SND_SERIAL_U16550 is not set | 1144 | # CONFIG_SND_SERIAL_U16550 is not set |
| 1098 | # CONFIG_SND_MPU401 is not set | 1145 | # CONFIG_SND_MPU401 is not set |
| 1099 | 1146 | CONFIG_SND_SPI=y | |
| 1100 | # | ||
| 1101 | # SPI devices | ||
| 1102 | # | ||
| 1103 | 1147 | ||
| 1104 | # | 1148 | # |
| 1105 | # ALSA Blackfin devices | 1149 | # ALSA Blackfin devices |
| 1106 | # | 1150 | # |
| 1107 | # CONFIG_SND_BLACKFIN_AD1836 is not set | 1151 | # CONFIG_SND_BLACKFIN_AD1836 is not set |
| 1108 | # CONFIG_SND_BFIN_AD73311 is not set | ||
| 1109 | # CONFIG_SND_BFIN_AD73322 is not set | 1152 | # CONFIG_SND_BFIN_AD73322 is not set |
| 1110 | 1153 | CONFIG_SND_USB=y | |
| 1111 | # | ||
| 1112 | # USB devices | ||
| 1113 | # | ||
| 1114 | # CONFIG_SND_USB_AUDIO is not set | 1154 | # CONFIG_SND_USB_AUDIO is not set |
| 1115 | # CONFIG_SND_USB_CAIAQ is not set | 1155 | # CONFIG_SND_USB_CAIAQ is not set |
| 1116 | |||
| 1117 | # | ||
| 1118 | # System on Chip audio support | ||
| 1119 | # | ||
| 1120 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 1121 | CONFIG_SND_SOC=y | 1156 | CONFIG_SND_SOC=y |
| 1122 | CONFIG_SND_BF5XX_SOC=y | 1157 | CONFIG_SND_SOC_AC97_BUS=y |
| 1123 | CONFIG_SND_MMAP_SUPPORT=y | 1158 | # CONFIG_SND_BF5XX_I2S is not set |
| 1159 | CONFIG_SND_BF5XX_AC97=y | ||
| 1160 | CONFIG_SND_BF5XX_MMAP_SUPPORT=y | ||
| 1161 | # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set | ||
| 1162 | CONFIG_SND_BF5XX_SOC_SPORT=y | ||
| 1124 | CONFIG_SND_BF5XX_SOC_AC97=y | 1163 | CONFIG_SND_BF5XX_SOC_AC97=y |
| 1125 | CONFIG_SND_BF5XX_SOC_BF548_EZKIT=y | 1164 | CONFIG_SND_BF5XX_SOC_AD1980=y |
| 1126 | # CONFIG_SND_BF5XX_SOC_WM8750 is not set | ||
| 1127 | # CONFIG_SND_BF5XX_SOC_WM8731 is not set | ||
| 1128 | # CONFIG_SND_BF5XX_SOC_SSM2602 is not set | ||
| 1129 | CONFIG_SND_BF5XX_SPORT_NUM=0 | 1165 | CONFIG_SND_BF5XX_SPORT_NUM=0 |
| 1130 | CONFIG_SND_BF5XX_HAVE_COLD_RESET=y | 1166 | CONFIG_SND_BF5XX_HAVE_COLD_RESET=y |
| 1131 | CONFIG_SND_BF5XX_RESET_GPIO_NUM=19 | 1167 | CONFIG_SND_BF5XX_RESET_GPIO_NUM=19 |
| 1132 | 1168 | # CONFIG_SND_SOC_ALL_CODECS is not set | |
| 1133 | # | ||
| 1134 | # SoC Audio support for SuperH | ||
| 1135 | # | ||
| 1136 | CONFIG_SND_SOC_AD1980=y | 1169 | CONFIG_SND_SOC_AD1980=y |
| 1137 | |||
| 1138 | # | ||
| 1139 | # Open Sound System | ||
| 1140 | # | ||
| 1141 | # CONFIG_SOUND_PRIME is not set | 1170 | # CONFIG_SOUND_PRIME is not set |
| 1142 | CONFIG_AC97_BUS=y | 1171 | CONFIG_AC97_BUS=y |
| 1143 | CONFIG_HID_SUPPORT=y | 1172 | CONFIG_HID_SUPPORT=y |
| @@ -1149,15 +1178,43 @@ CONFIG_HID=y | |||
| 1149 | # USB Input Devices | 1178 | # USB Input Devices |
| 1150 | # | 1179 | # |
| 1151 | CONFIG_USB_HID=y | 1180 | CONFIG_USB_HID=y |
| 1152 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | 1181 | # CONFIG_HID_PID is not set |
| 1153 | # CONFIG_HID_FF is not set | ||
| 1154 | # CONFIG_USB_HIDDEV is not set | 1182 | # CONFIG_USB_HIDDEV is not set |
| 1183 | |||
| 1184 | # | ||
| 1185 | # Special HID drivers | ||
| 1186 | # | ||
| 1187 | CONFIG_HID_COMPAT=y | ||
| 1188 | CONFIG_HID_A4TECH=y | ||
| 1189 | CONFIG_HID_APPLE=y | ||
| 1190 | CONFIG_HID_BELKIN=y | ||
| 1191 | CONFIG_HID_BRIGHT=y | ||
| 1192 | CONFIG_HID_CHERRY=y | ||
| 1193 | CONFIG_HID_CHICONY=y | ||
| 1194 | CONFIG_HID_CYPRESS=y | ||
| 1195 | CONFIG_HID_DELL=y | ||
| 1196 | CONFIG_HID_EZKEY=y | ||
| 1197 | CONFIG_HID_GYRATION=y | ||
| 1198 | CONFIG_HID_LOGITECH=y | ||
| 1199 | # CONFIG_LOGITECH_FF is not set | ||
| 1200 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1201 | CONFIG_HID_MICROSOFT=y | ||
| 1202 | CONFIG_HID_MONTEREY=y | ||
| 1203 | CONFIG_HID_PANTHERLORD=y | ||
| 1204 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1205 | CONFIG_HID_PETALYNX=y | ||
| 1206 | CONFIG_HID_SAMSUNG=y | ||
| 1207 | CONFIG_HID_SONY=y | ||
| 1208 | CONFIG_HID_SUNPLUS=y | ||
| 1209 | CONFIG_THRUSTMASTER_FF=m | ||
| 1210 | CONFIG_ZEROPLUS_FF=m | ||
| 1155 | CONFIG_USB_SUPPORT=y | 1211 | CONFIG_USB_SUPPORT=y |
| 1156 | CONFIG_USB_ARCH_HAS_HCD=y | 1212 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1157 | # CONFIG_USB_ARCH_HAS_OHCI is not set | 1213 | # CONFIG_USB_ARCH_HAS_OHCI is not set |
| 1158 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 1214 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| 1159 | CONFIG_USB=y | 1215 | CONFIG_USB=y |
| 1160 | # CONFIG_USB_DEBUG is not set | 1216 | # CONFIG_USB_DEBUG is not set |
| 1217 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 1161 | 1218 | ||
| 1162 | # | 1219 | # |
| 1163 | # Miscellaneous USB options | 1220 | # Miscellaneous USB options |
| @@ -1168,15 +1225,20 @@ CONFIG_USB_DEVICE_CLASS=y | |||
| 1168 | # CONFIG_USB_OTG is not set | 1225 | # CONFIG_USB_OTG is not set |
| 1169 | # CONFIG_USB_OTG_WHITELIST is not set | 1226 | # CONFIG_USB_OTG_WHITELIST is not set |
| 1170 | CONFIG_USB_OTG_BLACKLIST_HUB=y | 1227 | CONFIG_USB_OTG_BLACKLIST_HUB=y |
| 1228 | CONFIG_USB_MON=y | ||
| 1229 | # CONFIG_USB_WUSB is not set | ||
| 1230 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1171 | 1231 | ||
| 1172 | # | 1232 | # |
| 1173 | # USB Host Controller Drivers | 1233 | # USB Host Controller Drivers |
| 1174 | # | 1234 | # |
| 1235 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1175 | # CONFIG_USB_ISP116X_HCD is not set | 1236 | # CONFIG_USB_ISP116X_HCD is not set |
| 1176 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1177 | # CONFIG_USB_ISP1760_HCD is not set | 1237 | # CONFIG_USB_ISP1760_HCD is not set |
| 1238 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1178 | # CONFIG_USB_SL811_HCD is not set | 1239 | # CONFIG_USB_SL811_HCD is not set |
| 1179 | # CONFIG_USB_R8A66597_HCD is not set | 1240 | # CONFIG_USB_R8A66597_HCD is not set |
| 1241 | # CONFIG_USB_HWA_HCD is not set | ||
| 1180 | CONFIG_USB_MUSB_HDRC=y | 1242 | CONFIG_USB_MUSB_HDRC=y |
| 1181 | CONFIG_USB_MUSB_SOC=y | 1243 | CONFIG_USB_MUSB_SOC=y |
| 1182 | 1244 | ||
| @@ -1190,13 +1252,15 @@ CONFIG_USB_MUSB_HDRC_HCD=y | |||
| 1190 | # CONFIG_MUSB_PIO_ONLY is not set | 1252 | # CONFIG_MUSB_PIO_ONLY is not set |
| 1191 | CONFIG_USB_INVENTRA_DMA=y | 1253 | CONFIG_USB_INVENTRA_DMA=y |
| 1192 | # CONFIG_USB_TI_CPPI_DMA is not set | 1254 | # CONFIG_USB_TI_CPPI_DMA is not set |
| 1193 | CONFIG_USB_MUSB_LOGLEVEL=0 | 1255 | # CONFIG_USB_MUSB_DEBUG is not set |
| 1194 | 1256 | ||
| 1195 | # | 1257 | # |
| 1196 | # USB Device Class drivers | 1258 | # USB Device Class drivers |
| 1197 | # | 1259 | # |
| 1198 | # CONFIG_USB_ACM is not set | 1260 | # CONFIG_USB_ACM is not set |
| 1199 | # CONFIG_USB_PRINTER is not set | 1261 | # CONFIG_USB_PRINTER is not set |
| 1262 | # CONFIG_USB_WDM is not set | ||
| 1263 | # CONFIG_USB_TMC is not set | ||
| 1200 | 1264 | ||
| 1201 | # | 1265 | # |
| 1202 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1266 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' |
| @@ -1218,6 +1282,7 @@ CONFIG_USB_STORAGE=m | |||
| 1218 | # CONFIG_USB_STORAGE_ALAUDA is not set | 1282 | # CONFIG_USB_STORAGE_ALAUDA is not set |
| 1219 | # CONFIG_USB_STORAGE_ONETOUCH is not set | 1283 | # CONFIG_USB_STORAGE_ONETOUCH is not set |
| 1220 | # CONFIG_USB_STORAGE_KARMA is not set | 1284 | # CONFIG_USB_STORAGE_KARMA is not set |
| 1285 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1221 | # CONFIG_USB_LIBUSUAL is not set | 1286 | # CONFIG_USB_LIBUSUAL is not set |
| 1222 | 1287 | ||
| 1223 | # | 1288 | # |
| @@ -1225,15 +1290,10 @@ CONFIG_USB_STORAGE=m | |||
| 1225 | # | 1290 | # |
| 1226 | # CONFIG_USB_MDC800 is not set | 1291 | # CONFIG_USB_MDC800 is not set |
| 1227 | # CONFIG_USB_MICROTEK is not set | 1292 | # CONFIG_USB_MICROTEK is not set |
| 1228 | CONFIG_USB_MON=y | ||
| 1229 | 1293 | ||
| 1230 | # | 1294 | # |
| 1231 | # USB port drivers | 1295 | # USB port drivers |
| 1232 | # | 1296 | # |
| 1233 | |||
| 1234 | # | ||
| 1235 | # USB Serial Converter support | ||
| 1236 | # | ||
| 1237 | # CONFIG_USB_SERIAL is not set | 1297 | # CONFIG_USB_SERIAL is not set |
| 1238 | 1298 | ||
| 1239 | # | 1299 | # |
| @@ -1242,7 +1302,7 @@ CONFIG_USB_MON=y | |||
| 1242 | # CONFIG_USB_EMI62 is not set | 1302 | # CONFIG_USB_EMI62 is not set |
| 1243 | # CONFIG_USB_EMI26 is not set | 1303 | # CONFIG_USB_EMI26 is not set |
| 1244 | # CONFIG_USB_ADUTUX is not set | 1304 | # CONFIG_USB_ADUTUX is not set |
| 1245 | # CONFIG_USB_AUERSWALD is not set | 1305 | # CONFIG_USB_SEVSEG is not set |
| 1246 | # CONFIG_USB_RIO500 is not set | 1306 | # CONFIG_USB_RIO500 is not set |
| 1247 | # CONFIG_USB_LEGOTOWER is not set | 1307 | # CONFIG_USB_LEGOTOWER is not set |
| 1248 | # CONFIG_USB_LCD is not set | 1308 | # CONFIG_USB_LCD is not set |
| @@ -1258,34 +1318,31 @@ CONFIG_USB_MON=y | |||
| 1258 | # CONFIG_USB_LD is not set | 1318 | # CONFIG_USB_LD is not set |
| 1259 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1319 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1260 | # CONFIG_USB_IOWARRIOR is not set | 1320 | # CONFIG_USB_IOWARRIOR is not set |
| 1261 | 1321 | # CONFIG_USB_ISIGHTFW is not set | |
| 1262 | # | 1322 | # CONFIG_USB_VST is not set |
| 1263 | # USB DSL modem support | ||
| 1264 | # | ||
| 1265 | |||
| 1266 | # | ||
| 1267 | # USB Gadget Support | ||
| 1268 | # | ||
| 1269 | # CONFIG_USB_GADGET is not set | 1323 | # CONFIG_USB_GADGET is not set |
| 1270 | CONFIG_MMC=m | 1324 | CONFIG_MMC=m |
| 1271 | # CONFIG_MMC_DEBUG is not set | 1325 | # CONFIG_MMC_DEBUG is not set |
| 1272 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1326 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 1273 | 1327 | ||
| 1274 | # | 1328 | # |
| 1275 | # MMC/SD Card Drivers | 1329 | # MMC/SD/SDIO Card Drivers |
| 1276 | # | 1330 | # |
| 1277 | CONFIG_MMC_BLOCK=m | 1331 | CONFIG_MMC_BLOCK=m |
| 1278 | CONFIG_MMC_BLOCK_BOUNCE=y | 1332 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 1279 | # CONFIG_SDIO_UART is not set | 1333 | # CONFIG_SDIO_UART is not set |
| 1334 | # CONFIG_MMC_TEST is not set | ||
| 1280 | 1335 | ||
| 1281 | # | 1336 | # |
| 1282 | # MMC/SD Host Controller Drivers | 1337 | # MMC/SD/SDIO Host Controller Drivers |
| 1283 | # | 1338 | # |
| 1339 | # CONFIG_MMC_SDHCI is not set | ||
| 1284 | CONFIG_SDH_BFIN=m | 1340 | CONFIG_SDH_BFIN=m |
| 1285 | # CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set | 1341 | # CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set |
| 1286 | # CONFIG_MMC_SPI is not set | 1342 | # CONFIG_MMC_SPI is not set |
| 1287 | # CONFIG_SPI_MMC is not set | 1343 | # CONFIG_MEMSTICK is not set |
| 1288 | # CONFIG_NEW_LEDS is not set | 1344 | # CONFIG_NEW_LEDS is not set |
| 1345 | # CONFIG_ACCESSIBILITY is not set | ||
| 1289 | CONFIG_RTC_LIB=y | 1346 | CONFIG_RTC_LIB=y |
| 1290 | CONFIG_RTC_CLASS=y | 1347 | CONFIG_RTC_CLASS=y |
| 1291 | CONFIG_RTC_HCTOSYS=y | 1348 | CONFIG_RTC_HCTOSYS=y |
| @@ -1314,32 +1371,40 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1314 | # CONFIG_RTC_DRV_PCF8563 is not set | 1371 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1315 | # CONFIG_RTC_DRV_PCF8583 is not set | 1372 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1316 | # CONFIG_RTC_DRV_M41T80 is not set | 1373 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1374 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1375 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1317 | 1376 | ||
| 1318 | # | 1377 | # |
| 1319 | # SPI RTC drivers | 1378 | # SPI RTC drivers |
| 1320 | # | 1379 | # |
| 1321 | # CONFIG_RTC_DRV_RS5C348 is not set | 1380 | # CONFIG_RTC_DRV_M41T94 is not set |
| 1381 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1322 | # CONFIG_RTC_DRV_MAX6902 is not set | 1382 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 1383 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1384 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1385 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1323 | 1386 | ||
| 1324 | # | 1387 | # |
| 1325 | # Platform RTC drivers | 1388 | # Platform RTC drivers |
| 1326 | # | 1389 | # |
| 1390 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1391 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1327 | # CONFIG_RTC_DRV_DS1553 is not set | 1392 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1328 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1329 | # CONFIG_RTC_DRV_DS1742 is not set | 1393 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1394 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1330 | # CONFIG_RTC_DRV_M48T86 is not set | 1395 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1396 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1331 | # CONFIG_RTC_DRV_M48T59 is not set | 1397 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1398 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1332 | # CONFIG_RTC_DRV_V3020 is not set | 1399 | # CONFIG_RTC_DRV_V3020 is not set |
| 1333 | 1400 | ||
| 1334 | # | 1401 | # |
| 1335 | # on-CPU RTC drivers | 1402 | # on-CPU RTC drivers |
| 1336 | # | 1403 | # |
| 1337 | CONFIG_RTC_DRV_BFIN=y | 1404 | CONFIG_RTC_DRV_BFIN=y |
| 1338 | 1405 | # CONFIG_DMADEVICES is not set | |
| 1339 | # | ||
| 1340 | # Userspace I/O | ||
| 1341 | # | ||
| 1342 | # CONFIG_UIO is not set | 1406 | # CONFIG_UIO is not set |
| 1407 | # CONFIG_STAGING is not set | ||
| 1343 | 1408 | ||
| 1344 | # | 1409 | # |
| 1345 | # File systems | 1410 | # File systems |
| @@ -1352,22 +1417,20 @@ CONFIG_EXT3_FS=y | |||
| 1352 | CONFIG_EXT3_FS_XATTR=y | 1417 | CONFIG_EXT3_FS_XATTR=y |
| 1353 | # CONFIG_EXT3_FS_POSIX_ACL is not set | 1418 | # CONFIG_EXT3_FS_POSIX_ACL is not set |
| 1354 | # CONFIG_EXT3_FS_SECURITY is not set | 1419 | # CONFIG_EXT3_FS_SECURITY is not set |
| 1355 | # CONFIG_EXT4DEV_FS is not set | 1420 | # CONFIG_EXT4_FS is not set |
| 1356 | CONFIG_JBD=y | 1421 | CONFIG_JBD=y |
| 1357 | # CONFIG_JBD_DEBUG is not set | 1422 | # CONFIG_JBD_DEBUG is not set |
| 1358 | CONFIG_FS_MBCACHE=y | 1423 | CONFIG_FS_MBCACHE=y |
| 1359 | # CONFIG_REISERFS_FS is not set | 1424 | # CONFIG_REISERFS_FS is not set |
| 1360 | # CONFIG_JFS_FS is not set | 1425 | # CONFIG_JFS_FS is not set |
| 1361 | # CONFIG_FS_POSIX_ACL is not set | 1426 | # CONFIG_FS_POSIX_ACL is not set |
| 1427 | CONFIG_FILE_LOCKING=y | ||
| 1362 | # CONFIG_XFS_FS is not set | 1428 | # CONFIG_XFS_FS is not set |
| 1363 | # CONFIG_GFS2_FS is not set | ||
| 1364 | # CONFIG_OCFS2_FS is not set | 1429 | # CONFIG_OCFS2_FS is not set |
| 1365 | # CONFIG_MINIX_FS is not set | 1430 | # CONFIG_DNOTIFY is not set |
| 1366 | # CONFIG_ROMFS_FS is not set | ||
| 1367 | CONFIG_INOTIFY=y | 1431 | CONFIG_INOTIFY=y |
| 1368 | CONFIG_INOTIFY_USER=y | 1432 | CONFIG_INOTIFY_USER=y |
| 1369 | # CONFIG_QUOTA is not set | 1433 | # CONFIG_QUOTA is not set |
| 1370 | # CONFIG_DNOTIFY is not set | ||
| 1371 | # CONFIG_AUTOFS_FS is not set | 1434 | # CONFIG_AUTOFS_FS is not set |
| 1372 | # CONFIG_AUTOFS4_FS is not set | 1435 | # CONFIG_AUTOFS4_FS is not set |
| 1373 | # CONFIG_FUSE_FS is not set | 1436 | # CONFIG_FUSE_FS is not set |
| @@ -1414,11 +1477,11 @@ CONFIG_SYSFS=y | |||
| 1414 | # CONFIG_EFS_FS is not set | 1477 | # CONFIG_EFS_FS is not set |
| 1415 | CONFIG_YAFFS_FS=m | 1478 | CONFIG_YAFFS_FS=m |
| 1416 | CONFIG_YAFFS_YAFFS1=y | 1479 | CONFIG_YAFFS_YAFFS1=y |
| 1480 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1417 | # CONFIG_YAFFS_DOES_ECC is not set | 1481 | # CONFIG_YAFFS_DOES_ECC is not set |
| 1418 | CONFIG_YAFFS_YAFFS2=y | 1482 | CONFIG_YAFFS_YAFFS2=y |
| 1419 | CONFIG_YAFFS_AUTO_YAFFS2=y | 1483 | CONFIG_YAFFS_AUTO_YAFFS2=y |
| 1420 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | 1484 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set |
| 1421 | CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 | ||
| 1422 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | 1485 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 1423 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | 1486 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 1424 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | 1487 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| @@ -1435,8 +1498,11 @@ CONFIG_JFFS2_RTIME=y | |||
| 1435 | # CONFIG_JFFS2_RUBIN is not set | 1498 | # CONFIG_JFFS2_RUBIN is not set |
| 1436 | # CONFIG_CRAMFS is not set | 1499 | # CONFIG_CRAMFS is not set |
| 1437 | # CONFIG_VXFS_FS is not set | 1500 | # CONFIG_VXFS_FS is not set |
| 1501 | # CONFIG_MINIX_FS is not set | ||
| 1502 | # CONFIG_OMFS_FS is not set | ||
| 1438 | # CONFIG_HPFS_FS is not set | 1503 | # CONFIG_HPFS_FS is not set |
| 1439 | # CONFIG_QNX4FS_FS is not set | 1504 | # CONFIG_QNX4FS_FS is not set |
| 1505 | # CONFIG_ROMFS_FS is not set | ||
| 1440 | # CONFIG_SYSV_FS is not set | 1506 | # CONFIG_SYSV_FS is not set |
| 1441 | # CONFIG_UFS_FS is not set | 1507 | # CONFIG_UFS_FS is not set |
| 1442 | CONFIG_NETWORK_FILESYSTEMS=y | 1508 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1444,18 +1510,16 @@ CONFIG_NFS_FS=m | |||
| 1444 | CONFIG_NFS_V3=y | 1510 | CONFIG_NFS_V3=y |
| 1445 | # CONFIG_NFS_V3_ACL is not set | 1511 | # CONFIG_NFS_V3_ACL is not set |
| 1446 | # CONFIG_NFS_V4 is not set | 1512 | # CONFIG_NFS_V4 is not set |
| 1447 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1448 | CONFIG_NFSD=m | 1513 | CONFIG_NFSD=m |
| 1449 | CONFIG_NFSD_V3=y | 1514 | CONFIG_NFSD_V3=y |
| 1450 | # CONFIG_NFSD_V3_ACL is not set | 1515 | # CONFIG_NFSD_V3_ACL is not set |
| 1451 | # CONFIG_NFSD_V4 is not set | 1516 | # CONFIG_NFSD_V4 is not set |
| 1452 | CONFIG_NFSD_TCP=y | ||
| 1453 | CONFIG_LOCKD=m | 1517 | CONFIG_LOCKD=m |
| 1454 | CONFIG_LOCKD_V4=y | 1518 | CONFIG_LOCKD_V4=y |
| 1455 | CONFIG_EXPORTFS=m | 1519 | CONFIG_EXPORTFS=m |
| 1456 | CONFIG_NFS_COMMON=y | 1520 | CONFIG_NFS_COMMON=y |
| 1457 | CONFIG_SUNRPC=m | 1521 | CONFIG_SUNRPC=m |
| 1458 | # CONFIG_SUNRPC_BIND34 is not set | 1522 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1459 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1523 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1460 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1524 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1461 | CONFIG_SMB_FS=m | 1525 | CONFIG_SMB_FS=m |
| @@ -1533,9 +1597,6 @@ CONFIG_NLS_KOI8_R=m | |||
| 1533 | CONFIG_NLS_KOI8_U=m | 1597 | CONFIG_NLS_KOI8_U=m |
| 1534 | CONFIG_NLS_UTF8=m | 1598 | CONFIG_NLS_UTF8=m |
| 1535 | # CONFIG_DLM is not set | 1599 | # CONFIG_DLM is not set |
| 1536 | CONFIG_INSTRUMENTATION=y | ||
| 1537 | # CONFIG_PROFILING is not set | ||
| 1538 | # CONFIG_MARKERS is not set | ||
| 1539 | 1600 | ||
| 1540 | # | 1601 | # |
| 1541 | # Kernel hacking | 1602 | # Kernel hacking |
| @@ -1543,14 +1604,53 @@ CONFIG_INSTRUMENTATION=y | |||
| 1543 | # CONFIG_PRINTK_TIME is not set | 1604 | # CONFIG_PRINTK_TIME is not set |
| 1544 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1605 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1545 | CONFIG_ENABLE_MUST_CHECK=y | 1606 | CONFIG_ENABLE_MUST_CHECK=y |
| 1607 | CONFIG_FRAME_WARN=1024 | ||
| 1546 | # CONFIG_MAGIC_SYSRQ is not set | 1608 | # CONFIG_MAGIC_SYSRQ is not set |
| 1547 | # CONFIG_UNUSED_SYMBOLS is not set | 1609 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1548 | CONFIG_DEBUG_FS=y | 1610 | CONFIG_DEBUG_FS=y |
| 1549 | # CONFIG_HEADERS_CHECK is not set | 1611 | # CONFIG_HEADERS_CHECK is not set |
| 1550 | # CONFIG_DEBUG_KERNEL is not set | 1612 | CONFIG_DEBUG_KERNEL=y |
| 1613 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1614 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1615 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1616 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1617 | CONFIG_SCHED_DEBUG=y | ||
| 1618 | # CONFIG_SCHEDSTATS is not set | ||
| 1619 | # CONFIG_TIMER_STATS is not set | ||
| 1620 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1621 | # CONFIG_DEBUG_SLAB is not set | ||
| 1622 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1623 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1624 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1625 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1626 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1627 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1628 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1551 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1629 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1630 | CONFIG_DEBUG_INFO=y | ||
| 1631 | # CONFIG_DEBUG_VM is not set | ||
| 1632 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1633 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1634 | # CONFIG_DEBUG_LIST is not set | ||
| 1635 | # CONFIG_DEBUG_SG is not set | ||
| 1636 | # CONFIG_FRAME_POINTER is not set | ||
| 1637 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1638 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1639 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1640 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1641 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1642 | # CONFIG_FAULT_INJECTION is not set | ||
| 1643 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1644 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1552 | # CONFIG_SAMPLES is not set | 1645 | # CONFIG_SAMPLES is not set |
| 1646 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1647 | # CONFIG_KGDB is not set | ||
| 1648 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1649 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1650 | CONFIG_DEBUG_VERBOSE=y | ||
| 1553 | CONFIG_DEBUG_MMRS=y | 1651 | CONFIG_DEBUG_MMRS=y |
| 1652 | # CONFIG_DEBUG_HWERR is not set | ||
| 1653 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 1554 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1654 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 1555 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1655 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1556 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1656 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -1568,10 +1668,95 @@ CONFIG_ACCESS_CHECK=y | |||
| 1568 | # | 1668 | # |
| 1569 | # CONFIG_KEYS is not set | 1669 | # CONFIG_KEYS is not set |
| 1570 | CONFIG_SECURITY=y | 1670 | CONFIG_SECURITY=y |
| 1671 | # CONFIG_SECURITYFS is not set | ||
| 1571 | # CONFIG_SECURITY_NETWORK is not set | 1672 | # CONFIG_SECURITY_NETWORK is not set |
| 1572 | # CONFIG_SECURITY_CAPABILITIES is not set | 1673 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1573 | # CONFIG_SECURITY_ROOTPLUG is not set | 1674 | # CONFIG_SECURITY_ROOTPLUG is not set |
| 1574 | # CONFIG_CRYPTO is not set | 1675 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 |
| 1676 | CONFIG_CRYPTO=y | ||
| 1677 | |||
| 1678 | # | ||
| 1679 | # Crypto core or helper | ||
| 1680 | # | ||
| 1681 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1682 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1683 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1684 | # CONFIG_CRYPTO_NULL is not set | ||
| 1685 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1686 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1687 | # CONFIG_CRYPTO_TEST is not set | ||
| 1688 | |||
| 1689 | # | ||
| 1690 | # Authenticated Encryption with Associated Data | ||
| 1691 | # | ||
| 1692 | # CONFIG_CRYPTO_CCM is not set | ||
| 1693 | # CONFIG_CRYPTO_GCM is not set | ||
| 1694 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1695 | |||
| 1696 | # | ||
| 1697 | # Block modes | ||
| 1698 | # | ||
| 1699 | # CONFIG_CRYPTO_CBC is not set | ||
| 1700 | # CONFIG_CRYPTO_CTR is not set | ||
| 1701 | # CONFIG_CRYPTO_CTS is not set | ||
| 1702 | # CONFIG_CRYPTO_ECB is not set | ||
| 1703 | # CONFIG_CRYPTO_LRW is not set | ||
| 1704 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1705 | # CONFIG_CRYPTO_XTS is not set | ||
| 1706 | |||
| 1707 | # | ||
| 1708 | # Hash modes | ||
| 1709 | # | ||
| 1710 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1711 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1712 | |||
| 1713 | # | ||
| 1714 | # Digest | ||
| 1715 | # | ||
| 1716 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1717 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1718 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1719 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1720 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1721 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1722 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1723 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1724 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1725 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1726 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1727 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1728 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1729 | |||
| 1730 | # | ||
| 1731 | # Ciphers | ||
| 1732 | # | ||
| 1733 | # CONFIG_CRYPTO_AES is not set | ||
| 1734 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1735 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1736 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1737 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1738 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1739 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1740 | # CONFIG_CRYPTO_DES is not set | ||
| 1741 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1742 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1743 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1744 | # CONFIG_CRYPTO_SEED is not set | ||
| 1745 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1746 | # CONFIG_CRYPTO_TEA is not set | ||
| 1747 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1748 | |||
| 1749 | # | ||
| 1750 | # Compression | ||
| 1751 | # | ||
| 1752 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1753 | # CONFIG_CRYPTO_LZO is not set | ||
| 1754 | |||
| 1755 | # | ||
| 1756 | # Random Number Generation | ||
| 1757 | # | ||
| 1758 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1759 | CONFIG_CRYPTO_HW=y | ||
| 1575 | 1760 | ||
| 1576 | # | 1761 | # |
| 1577 | # Library routines | 1762 | # Library routines |
| @@ -1579,6 +1764,7 @@ CONFIG_SECURITY=y | |||
| 1579 | CONFIG_BITREVERSE=y | 1764 | CONFIG_BITREVERSE=y |
| 1580 | CONFIG_CRC_CCITT=m | 1765 | CONFIG_CRC_CCITT=m |
| 1581 | # CONFIG_CRC16 is not set | 1766 | # CONFIG_CRC16 is not set |
| 1767 | # CONFIG_CRC_T10DIF is not set | ||
| 1582 | # CONFIG_CRC_ITU_T is not set | 1768 | # CONFIG_CRC_ITU_T is not set |
| 1583 | CONFIG_CRC32=y | 1769 | CONFIG_CRC32=y |
| 1584 | # CONFIG_CRC7 is not set | 1770 | # CONFIG_CRC7 is not set |
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 3c70d6230a12..1ecb7a38c905 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24.7 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # | 4 | # |
| 5 | # CONFIG_MMU is not set | 5 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 6 | # CONFIG_FPU is not set |
| @@ -8,7 +8,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 9 | CONFIG_BLACKFIN=y | 9 | CONFIG_BLACKFIN=y |
| 10 | CONFIG_ZONE_DMA=y | 10 | CONFIG_ZONE_DMA=y |
| 11 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 11 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 13 | CONFIG_GENERIC_HWEIGHT=y | 12 | CONFIG_GENERIC_HWEIGHT=y |
| 14 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| @@ -31,18 +30,16 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 31 | # CONFIG_POSIX_MQUEUE is not set | 30 | # CONFIG_POSIX_MQUEUE is not set |
| 32 | # CONFIG_BSD_PROCESS_ACCT is not set | 31 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 33 | # CONFIG_TASKSTATS is not set | 32 | # CONFIG_TASKSTATS is not set |
| 34 | # CONFIG_USER_NS is not set | ||
| 35 | # CONFIG_PID_NS is not set | ||
| 36 | # CONFIG_AUDIT is not set | 33 | # CONFIG_AUDIT is not set |
| 37 | CONFIG_IKCONFIG=y | 34 | CONFIG_IKCONFIG=y |
| 38 | CONFIG_IKCONFIG_PROC=y | 35 | CONFIG_IKCONFIG_PROC=y |
| 39 | CONFIG_LOG_BUF_SHIFT=14 | 36 | CONFIG_LOG_BUF_SHIFT=14 |
| 40 | # CONFIG_CGROUPS is not set | 37 | # CONFIG_CGROUPS is not set |
| 41 | CONFIG_FAIR_GROUP_SCHED=y | 38 | # CONFIG_GROUP_SCHED is not set |
| 42 | CONFIG_FAIR_USER_SCHED=y | 39 | # CONFIG_SYSFS_DEPRECATED is not set |
| 43 | # CONFIG_FAIR_CGROUP_SCHED is not set | 40 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 44 | CONFIG_SYSFS_DEPRECATED=y | ||
| 45 | # CONFIG_RELAY is not set | 41 | # CONFIG_RELAY is not set |
| 42 | # CONFIG_NAMESPACES is not set | ||
| 46 | CONFIG_BLK_DEV_INITRD=y | 43 | CONFIG_BLK_DEV_INITRD=y |
| 47 | CONFIG_INITRAMFS_SOURCE="" | 44 | CONFIG_INITRAMFS_SOURCE="" |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -51,26 +48,35 @@ CONFIG_EMBEDDED=y | |||
| 51 | CONFIG_UID16=y | 48 | CONFIG_UID16=y |
| 52 | CONFIG_SYSCTL_SYSCALL=y | 49 | CONFIG_SYSCTL_SYSCALL=y |
| 53 | CONFIG_KALLSYMS=y | 50 | CONFIG_KALLSYMS=y |
| 51 | # CONFIG_KALLSYMS_ALL is not set | ||
| 54 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 52 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 55 | CONFIG_HOTPLUG=y | 53 | CONFIG_HOTPLUG=y |
| 56 | CONFIG_PRINTK=y | 54 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 55 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 56 | # CONFIG_ELF_CORE is not set |
| 57 | CONFIG_COMPAT_BRK=y | ||
| 59 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 59 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 60 | CONFIG_ANON_INODES=y |
| 62 | CONFIG_EPOLL=y | 61 | CONFIG_EPOLL=y |
| 63 | CONFIG_SIGNALFD=y | 62 | CONFIG_SIGNALFD=y |
| 63 | CONFIG_TIMERFD=y | ||
| 64 | CONFIG_EVENTFD=y | 64 | CONFIG_EVENTFD=y |
| 65 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 66 | CONFIG_VM_EVENT_COUNTERS=y |
| 66 | CONFIG_SLAB=y | 67 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 68 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 69 | # CONFIG_SLOB is not set |
| 70 | # CONFIG_PROFILING is not set | ||
| 71 | # CONFIG_MARKERS is not set | ||
| 72 | CONFIG_HAVE_OPROFILE=y | ||
| 73 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 69 | CONFIG_SLABINFO=y | 74 | CONFIG_SLABINFO=y |
| 70 | CONFIG_RT_MUTEXES=y | 75 | CONFIG_RT_MUTEXES=y |
| 71 | CONFIG_TINY_SHMEM=y | 76 | CONFIG_TINY_SHMEM=y |
| 72 | CONFIG_BASE_SMALL=0 | 77 | CONFIG_BASE_SMALL=0 |
| 73 | CONFIG_MODULES=y | 78 | CONFIG_MODULES=y |
| 79 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 74 | CONFIG_MODULE_UNLOAD=y | 80 | CONFIG_MODULE_UNLOAD=y |
| 75 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 81 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 76 | # CONFIG_MODVERSIONS is not set | 82 | # CONFIG_MODVERSIONS is not set |
| @@ -81,6 +87,7 @@ CONFIG_BLOCK=y | |||
| 81 | # CONFIG_BLK_DEV_IO_TRACE is not set | 87 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 82 | # CONFIG_LSF is not set | 88 | # CONFIG_LSF is not set |
| 83 | # CONFIG_BLK_DEV_BSG is not set | 89 | # CONFIG_BLK_DEV_BSG is not set |
| 90 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 84 | 91 | ||
| 85 | # | 92 | # |
| 86 | # IO Schedulers | 93 | # IO Schedulers |
| @@ -94,9 +101,11 @@ CONFIG_DEFAULT_AS=y | |||
| 94 | # CONFIG_DEFAULT_CFQ is not set | 101 | # CONFIG_DEFAULT_CFQ is not set |
| 95 | # CONFIG_DEFAULT_NOOP is not set | 102 | # CONFIG_DEFAULT_NOOP is not set |
| 96 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 103 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 104 | CONFIG_CLASSIC_RCU=y | ||
| 97 | # CONFIG_PREEMPT_NONE is not set | 105 | # CONFIG_PREEMPT_NONE is not set |
| 98 | CONFIG_PREEMPT_VOLUNTARY=y | 106 | CONFIG_PREEMPT_VOLUNTARY=y |
| 99 | # CONFIG_PREEMPT is not set | 107 | # CONFIG_PREEMPT is not set |
| 108 | # CONFIG_FREEZER is not set | ||
| 100 | 109 | ||
| 101 | # | 110 | # |
| 102 | # Blackfin Processor Options | 111 | # Blackfin Processor Options |
| @@ -105,6 +114,10 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 105 | # | 114 | # |
| 106 | # Processor and Board Settings | 115 | # Processor and Board Settings |
| 107 | # | 116 | # |
| 117 | # CONFIG_BF512 is not set | ||
| 118 | # CONFIG_BF514 is not set | ||
| 119 | # CONFIG_BF516 is not set | ||
| 120 | # CONFIG_BF518 is not set | ||
| 108 | # CONFIG_BF522 is not set | 121 | # CONFIG_BF522 is not set |
| 109 | # CONFIG_BF523 is not set | 122 | # CONFIG_BF523 is not set |
| 110 | # CONFIG_BF524 is not set | 123 | # CONFIG_BF524 is not set |
| @@ -117,24 +130,38 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 117 | # CONFIG_BF534 is not set | 130 | # CONFIG_BF534 is not set |
| 118 | # CONFIG_BF536 is not set | 131 | # CONFIG_BF536 is not set |
| 119 | # CONFIG_BF537 is not set | 132 | # CONFIG_BF537 is not set |
| 133 | # CONFIG_BF538 is not set | ||
| 134 | # CONFIG_BF539 is not set | ||
| 120 | # CONFIG_BF542 is not set | 135 | # CONFIG_BF542 is not set |
| 121 | # CONFIG_BF544 is not set | 136 | # CONFIG_BF544 is not set |
| 122 | # CONFIG_BF547 is not set | 137 | # CONFIG_BF547 is not set |
| 123 | # CONFIG_BF548 is not set | 138 | # CONFIG_BF548 is not set |
| 124 | # CONFIG_BF549 is not set | 139 | # CONFIG_BF549 is not set |
| 125 | CONFIG_BF561=y | 140 | CONFIG_BF561=y |
| 141 | # CONFIG_SMP is not set | ||
| 142 | CONFIG_BF_REV_MIN=3 | ||
| 143 | CONFIG_BF_REV_MAX=5 | ||
| 126 | # CONFIG_BF_REV_0_0 is not set | 144 | # CONFIG_BF_REV_0_0 is not set |
| 127 | # CONFIG_BF_REV_0_1 is not set | 145 | # CONFIG_BF_REV_0_1 is not set |
| 128 | # CONFIG_BF_REV_0_2 is not set | 146 | # CONFIG_BF_REV_0_2 is not set |
| 129 | CONFIG_BF_REV_0_3=y | 147 | CONFIG_BF_REV_0_3=y |
| 130 | # CONFIG_BF_REV_0_4 is not set | 148 | # CONFIG_BF_REV_0_4 is not set |
| 131 | # CONFIG_BF_REV_0_5 is not set | 149 | # CONFIG_BF_REV_0_5 is not set |
| 150 | # CONFIG_BF_REV_0_6 is not set | ||
| 132 | # CONFIG_BF_REV_ANY is not set | 151 | # CONFIG_BF_REV_ANY is not set |
| 133 | # CONFIG_BF_REV_NONE is not set | 152 | # CONFIG_BF_REV_NONE is not set |
| 134 | CONFIG_MEM_MT48LC16M16A2TG_75=y | 153 | CONFIG_MEM_MT48LC16M16A2TG_75=y |
| 135 | CONFIG_IRQ_PLL_WAKEUP=7 | 154 | CONFIG_IRQ_PLL_WAKEUP=7 |
| 136 | CONFIG_IRQ_SPORT0_ERROR=7 | 155 | CONFIG_IRQ_SPORT0_ERROR=7 |
| 137 | CONFIG_IRQ_SPORT1_ERROR=7 | 156 | CONFIG_IRQ_SPORT1_ERROR=7 |
| 157 | CONFIG_IRQ_TIMER0=10 | ||
| 158 | CONFIG_IRQ_TIMER1=10 | ||
| 159 | CONFIG_IRQ_TIMER2=10 | ||
| 160 | CONFIG_IRQ_TIMER3=10 | ||
| 161 | CONFIG_IRQ_TIMER4=10 | ||
| 162 | CONFIG_IRQ_TIMER5=10 | ||
| 163 | CONFIG_IRQ_TIMER6=10 | ||
| 164 | CONFIG_IRQ_TIMER7=10 | ||
| 138 | CONFIG_IRQ_SPI_ERROR=7 | 165 | CONFIG_IRQ_SPI_ERROR=7 |
| 139 | CONFIG_BFIN561_EZKIT=y | 166 | CONFIG_BFIN561_EZKIT=y |
| 140 | # CONFIG_BFIN561_TEPLA is not set | 167 | # CONFIG_BFIN561_TEPLA is not set |
| @@ -148,10 +175,6 @@ CONFIG_BFIN561_EZKIT=y | |||
| 148 | # | 175 | # |
| 149 | # Core B Support | 176 | # Core B Support |
| 150 | # | 177 | # |
| 151 | |||
| 152 | # | ||
| 153 | # Core B Support | ||
| 154 | # | ||
| 155 | CONFIG_BF561_COREB=y | 178 | CONFIG_BF561_COREB=y |
| 156 | CONFIG_BF561_COREB_RESET=y | 179 | CONFIG_BF561_COREB_RESET=y |
| 157 | 180 | ||
| @@ -193,14 +216,6 @@ CONFIG_IRQ_DMA2_8=9 | |||
| 193 | CONFIG_IRQ_DMA2_9=9 | 216 | CONFIG_IRQ_DMA2_9=9 |
| 194 | CONFIG_IRQ_DMA2_10=9 | 217 | CONFIG_IRQ_DMA2_10=9 |
| 195 | CONFIG_IRQ_DMA2_11=9 | 218 | CONFIG_IRQ_DMA2_11=9 |
| 196 | CONFIG_IRQ_TIMER0=10 | ||
| 197 | CONFIG_IRQ_TIMER1=10 | ||
| 198 | CONFIG_IRQ_TIMER2=10 | ||
| 199 | CONFIG_IRQ_TIMER3=10 | ||
| 200 | CONFIG_IRQ_TIMER4=10 | ||
| 201 | CONFIG_IRQ_TIMER5=10 | ||
| 202 | CONFIG_IRQ_TIMER6=10 | ||
| 203 | CONFIG_IRQ_TIMER7=10 | ||
| 204 | CONFIG_IRQ_TIMER8=10 | 219 | CONFIG_IRQ_TIMER8=10 |
| 205 | CONFIG_IRQ_TIMER9=10 | 220 | CONFIG_IRQ_TIMER9=10 |
| 206 | CONFIG_IRQ_TIMER10=10 | 221 | CONFIG_IRQ_TIMER10=10 |
| @@ -230,7 +245,6 @@ CONFIG_BOOT_LOAD=0x1000 | |||
| 230 | # | 245 | # |
| 231 | CONFIG_CLKIN_HZ=30000000 | 246 | CONFIG_CLKIN_HZ=30000000 |
| 232 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 247 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 233 | CONFIG_MAX_MEM_SIZE=512 | ||
| 234 | CONFIG_MAX_VCO_HZ=600000000 | 248 | CONFIG_MAX_VCO_HZ=600000000 |
| 235 | CONFIG_MIN_VCO_HZ=50000000 | 249 | CONFIG_MIN_VCO_HZ=50000000 |
| 236 | CONFIG_MAX_SCLK_HZ=133333333 | 250 | CONFIG_MAX_SCLK_HZ=133333333 |
| @@ -244,6 +258,7 @@ CONFIG_HZ_250=y | |||
| 244 | # CONFIG_HZ_300 is not set | 258 | # CONFIG_HZ_300 is not set |
| 245 | # CONFIG_HZ_1000 is not set | 259 | # CONFIG_HZ_1000 is not set |
| 246 | CONFIG_HZ=250 | 260 | CONFIG_HZ=250 |
| 261 | CONFIG_SCHED_HRTICK=y | ||
| 247 | CONFIG_GENERIC_TIME=y | 262 | CONFIG_GENERIC_TIME=y |
| 248 | CONFIG_GENERIC_CLOCKEVENTS=y | 263 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 249 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 264 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| @@ -281,6 +296,12 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y | |||
| 281 | CONFIG_CACHELINE_ALIGNED_L1=y | 296 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 282 | # CONFIG_SYSCALL_TAB_L1 is not set | 297 | # CONFIG_SYSCALL_TAB_L1 is not set |
| 283 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set | 298 | # CONFIG_CPLB_SWITCH_TAB_L1 is not set |
| 299 | CONFIG_APP_STACK_L1=y | ||
| 300 | |||
| 301 | # | ||
| 302 | # Speed Optimizations | ||
| 303 | # | ||
| 304 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 284 | CONFIG_RAMKERNEL=y | 305 | CONFIG_RAMKERNEL=y |
| 285 | # CONFIG_ROMKERNEL is not set | 306 | # CONFIG_ROMKERNEL is not set |
| 286 | CONFIG_SELECT_MEMORY_MODEL=y | 307 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -289,14 +310,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 289 | # CONFIG_SPARSEMEM_MANUAL is not set | 310 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 290 | CONFIG_FLATMEM=y | 311 | CONFIG_FLATMEM=y |
| 291 | CONFIG_FLAT_NODE_MEM_MAP=y | 312 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 292 | # CONFIG_SPARSEMEM_STATIC is not set | 313 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 293 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 294 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 314 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 295 | # CONFIG_RESOURCES_64BIT is not set | 315 | # CONFIG_RESOURCES_64BIT is not set |
| 316 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 296 | CONFIG_ZONE_DMA_FLAG=1 | 317 | CONFIG_ZONE_DMA_FLAG=1 |
| 297 | CONFIG_VIRT_TO_BUS=y | 318 | CONFIG_VIRT_TO_BUS=y |
| 298 | # CONFIG_BFIN_GPTIMERS is not set | 319 | # CONFIG_BFIN_GPTIMERS is not set |
| 299 | CONFIG_BFIN_DMA_5XX=y | ||
| 300 | # CONFIG_DMA_UNCACHED_4M is not set | 320 | # CONFIG_DMA_UNCACHED_4M is not set |
| 301 | # CONFIG_DMA_UNCACHED_2M is not set | 321 | # CONFIG_DMA_UNCACHED_2M is not set |
| 302 | CONFIG_DMA_UNCACHED_1M=y | 322 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -311,7 +331,7 @@ CONFIG_BFIN_DCACHE=y | |||
| 311 | # CONFIG_BFIN_ICACHE_LOCK is not set | 331 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 312 | # CONFIG_BFIN_WB is not set | 332 | # CONFIG_BFIN_WB is not set |
| 313 | CONFIG_BFIN_WT=y | 333 | CONFIG_BFIN_WT=y |
| 314 | CONFIG_L1_MAX_PIECE=16 | 334 | # CONFIG_BFIN_L2_CACHEABLE is not set |
| 315 | # CONFIG_MPU is not set | 335 | # CONFIG_MPU is not set |
| 316 | 336 | ||
| 317 | # | 337 | # |
| @@ -344,7 +364,6 @@ CONFIG_BANK_3=0xAAC2 | |||
| 344 | # | 364 | # |
| 345 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 365 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 346 | # | 366 | # |
| 347 | # CONFIG_PCI is not set | ||
| 348 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 367 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 349 | # CONFIG_PCCARD is not set | 368 | # CONFIG_PCCARD is not set |
| 350 | 369 | ||
| @@ -355,23 +374,20 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 355 | CONFIG_BINFMT_FLAT=y | 374 | CONFIG_BINFMT_FLAT=y |
| 356 | CONFIG_BINFMT_ZFLAT=y | 375 | CONFIG_BINFMT_ZFLAT=y |
| 357 | # CONFIG_BINFMT_SHARED_FLAT is not set | 376 | # CONFIG_BINFMT_SHARED_FLAT is not set |
| 377 | # CONFIG_HAVE_AOUT is not set | ||
| 358 | # CONFIG_BINFMT_MISC is not set | 378 | # CONFIG_BINFMT_MISC is not set |
| 359 | 379 | ||
| 360 | # | 380 | # |
| 361 | # Power management options | 381 | # Power management options |
| 362 | # | 382 | # |
| 363 | # CONFIG_PM is not set | 383 | # CONFIG_PM is not set |
| 364 | CONFIG_SUSPEND_UP_POSSIBLE=y | 384 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 365 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | 385 | # CONFIG_PM_WAKEUP_BY_GPIO is not set |
| 366 | 386 | ||
| 367 | # | 387 | # |
| 368 | # CPU Frequency scaling | 388 | # CPU Frequency scaling |
| 369 | # | 389 | # |
| 370 | # CONFIG_CPU_FREQ is not set | 390 | # CONFIG_CPU_FREQ is not set |
| 371 | |||
| 372 | # | ||
| 373 | # Networking | ||
| 374 | # | ||
| 375 | CONFIG_NET=y | 391 | CONFIG_NET=y |
| 376 | 392 | ||
| 377 | # | 393 | # |
| @@ -384,6 +400,7 @@ CONFIG_XFRM=y | |||
| 384 | # CONFIG_XFRM_USER is not set | 400 | # CONFIG_XFRM_USER is not set |
| 385 | # CONFIG_XFRM_SUB_POLICY is not set | 401 | # CONFIG_XFRM_SUB_POLICY is not set |
| 386 | # CONFIG_XFRM_MIGRATE is not set | 402 | # CONFIG_XFRM_MIGRATE is not set |
| 403 | # CONFIG_XFRM_STATISTICS is not set | ||
| 387 | # CONFIG_NET_KEY is not set | 404 | # CONFIG_NET_KEY is not set |
| 388 | CONFIG_INET=y | 405 | CONFIG_INET=y |
| 389 | # CONFIG_IP_MULTICAST is not set | 406 | # CONFIG_IP_MULTICAST is not set |
| @@ -413,8 +430,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 413 | CONFIG_DEFAULT_TCP_CONG="cubic" | 430 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 414 | # CONFIG_TCP_MD5SIG is not set | 431 | # CONFIG_TCP_MD5SIG is not set |
| 415 | # CONFIG_IPV6 is not set | 432 | # CONFIG_IPV6 is not set |
| 416 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 417 | # CONFIG_INET6_TUNNEL is not set | ||
| 418 | # CONFIG_NETLABEL is not set | 433 | # CONFIG_NETLABEL is not set |
| 419 | # CONFIG_NETWORK_SECMARK is not set | 434 | # CONFIG_NETWORK_SECMARK is not set |
| 420 | # CONFIG_NETFILTER is not set | 435 | # CONFIG_NETFILTER is not set |
| @@ -423,6 +438,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 423 | # CONFIG_TIPC is not set | 438 | # CONFIG_TIPC is not set |
| 424 | # CONFIG_ATM is not set | 439 | # CONFIG_ATM is not set |
| 425 | # CONFIG_BRIDGE is not set | 440 | # CONFIG_BRIDGE is not set |
| 441 | # CONFIG_NET_DSA is not set | ||
| 426 | # CONFIG_VLAN_8021Q is not set | 442 | # CONFIG_VLAN_8021Q is not set |
| 427 | # CONFIG_DECNET is not set | 443 | # CONFIG_DECNET is not set |
| 428 | # CONFIG_LLC2 is not set | 444 | # CONFIG_LLC2 is not set |
| @@ -439,6 +455,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 439 | # | 455 | # |
| 440 | # CONFIG_NET_PKTGEN is not set | 456 | # CONFIG_NET_PKTGEN is not set |
| 441 | # CONFIG_HAMRADIO is not set | 457 | # CONFIG_HAMRADIO is not set |
| 458 | # CONFIG_CAN is not set | ||
| 442 | CONFIG_IRDA=m | 459 | CONFIG_IRDA=m |
| 443 | 460 | ||
| 444 | # | 461 | # |
| @@ -471,24 +488,14 @@ CONFIG_IRTTY_SIR=m | |||
| 471 | # CONFIG_DONGLE is not set | 488 | # CONFIG_DONGLE is not set |
| 472 | 489 | ||
| 473 | # | 490 | # |
| 474 | # Old SIR device drivers | ||
| 475 | # | ||
| 476 | # CONFIG_IRPORT_SIR is not set | ||
| 477 | |||
| 478 | # | ||
| 479 | # Old Serial dongle support | ||
| 480 | # | ||
| 481 | |||
| 482 | # | ||
| 483 | # FIR device drivers | 491 | # FIR device drivers |
| 484 | # | 492 | # |
| 485 | # CONFIG_BT is not set | 493 | # CONFIG_BT is not set |
| 486 | # CONFIG_AF_RXRPC is not set | 494 | # CONFIG_AF_RXRPC is not set |
| 487 | 495 | # CONFIG_PHONET is not set | |
| 488 | # | 496 | CONFIG_WIRELESS=y |
| 489 | # Wireless | ||
| 490 | # | ||
| 491 | # CONFIG_CFG80211 is not set | 497 | # CONFIG_CFG80211 is not set |
| 498 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 492 | # CONFIG_WIRELESS_EXT is not set | 499 | # CONFIG_WIRELESS_EXT is not set |
| 493 | # CONFIG_MAC80211 is not set | 500 | # CONFIG_MAC80211 is not set |
| 494 | # CONFIG_IEEE80211 is not set | 501 | # CONFIG_IEEE80211 is not set |
| @@ -506,6 +513,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 506 | CONFIG_STANDALONE=y | 513 | CONFIG_STANDALONE=y |
| 507 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 514 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 508 | # CONFIG_FW_LOADER is not set | 515 | # CONFIG_FW_LOADER is not set |
| 516 | # CONFIG_DEBUG_DRIVER is not set | ||
| 517 | # CONFIG_DEBUG_DEVRES is not set | ||
| 509 | # CONFIG_SYS_HYPERVISOR is not set | 518 | # CONFIG_SYS_HYPERVISOR is not set |
| 510 | # CONFIG_CONNECTOR is not set | 519 | # CONFIG_CONNECTOR is not set |
| 511 | CONFIG_MTD=y | 520 | CONFIG_MTD=y |
| @@ -514,6 +523,7 @@ CONFIG_MTD=y | |||
| 514 | CONFIG_MTD_PARTITIONS=y | 523 | CONFIG_MTD_PARTITIONS=y |
| 515 | # CONFIG_MTD_REDBOOT_PARTS is not set | 524 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 516 | CONFIG_MTD_CMDLINE_PARTS=y | 525 | CONFIG_MTD_CMDLINE_PARTS=y |
| 526 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 517 | 527 | ||
| 518 | # | 528 | # |
| 519 | # User Modules And Translation Layers | 529 | # User Modules And Translation Layers |
| @@ -595,11 +605,14 @@ CONFIG_BLK_DEV=y | |||
| 595 | CONFIG_BLK_DEV_RAM=y | 605 | CONFIG_BLK_DEV_RAM=y |
| 596 | CONFIG_BLK_DEV_RAM_COUNT=16 | 606 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 597 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 607 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 598 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 608 | # CONFIG_BLK_DEV_XIP is not set |
| 599 | # CONFIG_CDROM_PKTCDVD is not set | 609 | # CONFIG_CDROM_PKTCDVD is not set |
| 600 | # CONFIG_ATA_OVER_ETH is not set | 610 | # CONFIG_ATA_OVER_ETH is not set |
| 611 | # CONFIG_BLK_DEV_HD is not set | ||
| 601 | CONFIG_MISC_DEVICES=y | 612 | CONFIG_MISC_DEVICES=y |
| 602 | # CONFIG_EEPROM_93CX6 is not set | 613 | # CONFIG_EEPROM_93CX6 is not set |
| 614 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 615 | CONFIG_HAVE_IDE=y | ||
| 603 | # CONFIG_IDE is not set | 616 | # CONFIG_IDE is not set |
| 604 | 617 | ||
| 605 | # | 618 | # |
| @@ -612,7 +625,6 @@ CONFIG_MISC_DEVICES=y | |||
| 612 | # CONFIG_ATA is not set | 625 | # CONFIG_ATA is not set |
| 613 | # CONFIG_MD is not set | 626 | # CONFIG_MD is not set |
| 614 | CONFIG_NETDEVICES=y | 627 | CONFIG_NETDEVICES=y |
| 615 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 616 | # CONFIG_DUMMY is not set | 628 | # CONFIG_DUMMY is not set |
| 617 | # CONFIG_BONDING is not set | 629 | # CONFIG_BONDING is not set |
| 618 | # CONFIG_MACVLAN is not set | 630 | # CONFIG_MACVLAN is not set |
| @@ -625,11 +637,14 @@ CONFIG_MII=y | |||
| 625 | CONFIG_SMC91X=y | 637 | CONFIG_SMC91X=y |
| 626 | # CONFIG_SMSC911X is not set | 638 | # CONFIG_SMSC911X is not set |
| 627 | # CONFIG_DM9000 is not set | 639 | # CONFIG_DM9000 is not set |
| 640 | # CONFIG_ENC28J60 is not set | ||
| 628 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 641 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 629 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 642 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 630 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 643 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 631 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 644 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 632 | # CONFIG_B44 is not set | 645 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set |
| 646 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 647 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 633 | CONFIG_NETDEV_1000=y | 648 | CONFIG_NETDEV_1000=y |
| 634 | # CONFIG_AX88180 is not set | 649 | # CONFIG_AX88180 is not set |
| 635 | CONFIG_NETDEV_10000=y | 650 | CONFIG_NETDEV_10000=y |
| @@ -639,10 +654,10 @@ CONFIG_NETDEV_10000=y | |||
| 639 | # | 654 | # |
| 640 | # CONFIG_WLAN_PRE80211 is not set | 655 | # CONFIG_WLAN_PRE80211 is not set |
| 641 | # CONFIG_WLAN_80211 is not set | 656 | # CONFIG_WLAN_80211 is not set |
| 657 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 642 | # CONFIG_WAN is not set | 658 | # CONFIG_WAN is not set |
| 643 | # CONFIG_PPP is not set | 659 | # CONFIG_PPP is not set |
| 644 | # CONFIG_SLIP is not set | 660 | # CONFIG_SLIP is not set |
| 645 | # CONFIG_SHAPER is not set | ||
| 646 | # CONFIG_NETCONSOLE is not set | 661 | # CONFIG_NETCONSOLE is not set |
| 647 | # CONFIG_NETPOLL is not set | 662 | # CONFIG_NETPOLL is not set |
| 648 | # CONFIG_NET_POLL_CONTROLLER is not set | 663 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -690,8 +705,11 @@ CONFIG_INPUT_EVDEV=m | |||
| 690 | # CONFIG_BF5xx_PPI is not set | 705 | # CONFIG_BF5xx_PPI is not set |
| 691 | # CONFIG_BFIN_SPORT is not set | 706 | # CONFIG_BFIN_SPORT is not set |
| 692 | # CONFIG_BFIN_TIMER_LATENCY is not set | 707 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 708 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 693 | CONFIG_SIMPLE_GPIO=m | 709 | CONFIG_SIMPLE_GPIO=m |
| 694 | # CONFIG_VT is not set | 710 | # CONFIG_VT is not set |
| 711 | # CONFIG_DEVKMEM is not set | ||
| 712 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 695 | # CONFIG_SERIAL_NONSTANDARD is not set | 713 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 696 | 714 | ||
| 697 | # | 715 | # |
| @@ -720,22 +738,19 @@ CONFIG_UNIX98_PTYS=y | |||
| 720 | # CONFIG_CAN4LINUX is not set | 738 | # CONFIG_CAN4LINUX is not set |
| 721 | # CONFIG_IPMI_HANDLER is not set | 739 | # CONFIG_IPMI_HANDLER is not set |
| 722 | # CONFIG_HW_RANDOM is not set | 740 | # CONFIG_HW_RANDOM is not set |
| 723 | # CONFIG_GEN_RTC is not set | ||
| 724 | # CONFIG_R3964 is not set | 741 | # CONFIG_R3964 is not set |
| 725 | # CONFIG_RAW_DRIVER is not set | 742 | # CONFIG_RAW_DRIVER is not set |
| 726 | # CONFIG_TCG_TPM is not set | 743 | # CONFIG_TCG_TPM is not set |
| 727 | # CONFIG_I2C is not set | 744 | # CONFIG_I2C is not set |
| 728 | |||
| 729 | # | ||
| 730 | # SPI support | ||
| 731 | # | ||
| 732 | CONFIG_SPI=y | 745 | CONFIG_SPI=y |
| 746 | # CONFIG_SPI_DEBUG is not set | ||
| 733 | CONFIG_SPI_MASTER=y | 747 | CONFIG_SPI_MASTER=y |
| 734 | 748 | ||
| 735 | # | 749 | # |
| 736 | # SPI Master Controller Drivers | 750 | # SPI Master Controller Drivers |
| 737 | # | 751 | # |
| 738 | CONFIG_SPI_BFIN=y | 752 | CONFIG_SPI_BFIN=y |
| 753 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 739 | # CONFIG_SPI_BITBANG is not set | 754 | # CONFIG_SPI_BITBANG is not set |
| 740 | 755 | ||
| 741 | # | 756 | # |
| @@ -744,14 +759,18 @@ CONFIG_SPI_BFIN=y | |||
| 744 | # CONFIG_SPI_AT25 is not set | 759 | # CONFIG_SPI_AT25 is not set |
| 745 | # CONFIG_SPI_SPIDEV is not set | 760 | # CONFIG_SPI_SPIDEV is not set |
| 746 | # CONFIG_SPI_TLE62X0 is not set | 761 | # CONFIG_SPI_TLE62X0 is not set |
| 762 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 763 | # CONFIG_GPIOLIB is not set | ||
| 747 | # CONFIG_W1 is not set | 764 | # CONFIG_W1 is not set |
| 748 | # CONFIG_POWER_SUPPLY is not set | 765 | # CONFIG_POWER_SUPPLY is not set |
| 749 | CONFIG_HWMON=y | 766 | CONFIG_HWMON=y |
| 750 | # CONFIG_HWMON_VID is not set | 767 | # CONFIG_HWMON_VID is not set |
| 768 | # CONFIG_SENSORS_ADCXX is not set | ||
| 751 | # CONFIG_SENSORS_F71805F is not set | 769 | # CONFIG_SENSORS_F71805F is not set |
| 752 | # CONFIG_SENSORS_F71882FG is not set | 770 | # CONFIG_SENSORS_F71882FG is not set |
| 753 | # CONFIG_SENSORS_IT87 is not set | 771 | # CONFIG_SENSORS_IT87 is not set |
| 754 | # CONFIG_SENSORS_LM70 is not set | 772 | # CONFIG_SENSORS_LM70 is not set |
| 773 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 755 | # CONFIG_SENSORS_PC87360 is not set | 774 | # CONFIG_SENSORS_PC87360 is not set |
| 756 | # CONFIG_SENSORS_PC87427 is not set | 775 | # CONFIG_SENSORS_PC87427 is not set |
| 757 | # CONFIG_SENSORS_SMSC47M1 is not set | 776 | # CONFIG_SENSORS_SMSC47M1 is not set |
| @@ -760,6 +779,8 @@ CONFIG_HWMON=y | |||
| 760 | # CONFIG_SENSORS_W83627HF is not set | 779 | # CONFIG_SENSORS_W83627HF is not set |
| 761 | # CONFIG_SENSORS_W83627EHF is not set | 780 | # CONFIG_SENSORS_W83627EHF is not set |
| 762 | # CONFIG_HWMON_DEBUG_CHIP is not set | 781 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 782 | # CONFIG_THERMAL is not set | ||
| 783 | # CONFIG_THERMAL_HWMON is not set | ||
| 763 | CONFIG_WATCHDOG=y | 784 | CONFIG_WATCHDOG=y |
| 764 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 785 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 765 | 786 | ||
| @@ -770,21 +791,28 @@ CONFIG_WATCHDOG=y | |||
| 770 | CONFIG_BFIN_WDT=y | 791 | CONFIG_BFIN_WDT=y |
| 771 | 792 | ||
| 772 | # | 793 | # |
| 773 | # Sonics Silicon Backplane | ||
| 774 | # | ||
| 775 | CONFIG_SSB_POSSIBLE=y | ||
| 776 | # CONFIG_SSB is not set | ||
| 777 | |||
| 778 | # | ||
| 779 | # Multifunction device drivers | 794 | # Multifunction device drivers |
| 780 | # | 795 | # |
| 796 | # CONFIG_MFD_CORE is not set | ||
| 781 | # CONFIG_MFD_SM501 is not set | 797 | # CONFIG_MFD_SM501 is not set |
| 798 | # CONFIG_HTC_PASIC3 is not set | ||
| 799 | # CONFIG_MFD_TMIO is not set | ||
| 800 | # CONFIG_MFD_WM8400 is not set | ||
| 782 | 801 | ||
| 783 | # | 802 | # |
| 784 | # Multimedia devices | 803 | # Multimedia devices |
| 785 | # | 804 | # |
| 805 | |||
| 806 | # | ||
| 807 | # Multimedia core support | ||
| 808 | # | ||
| 786 | # CONFIG_VIDEO_DEV is not set | 809 | # CONFIG_VIDEO_DEV is not set |
| 787 | # CONFIG_DVB_CORE is not set | 810 | # CONFIG_DVB_CORE is not set |
| 811 | # CONFIG_VIDEO_MEDIA is not set | ||
| 812 | |||
| 813 | # | ||
| 814 | # Multimedia drivers | ||
| 815 | # | ||
| 788 | # CONFIG_DAB is not set | 816 | # CONFIG_DAB is not set |
| 789 | 817 | ||
| 790 | # | 818 | # |
| @@ -799,43 +827,43 @@ CONFIG_SSB_POSSIBLE=y | |||
| 799 | # Display device support | 827 | # Display device support |
| 800 | # | 828 | # |
| 801 | # CONFIG_DISPLAY_SUPPORT is not set | 829 | # CONFIG_DISPLAY_SUPPORT is not set |
| 802 | |||
| 803 | # | ||
| 804 | # Sound | ||
| 805 | # | ||
| 806 | # CONFIG_SOUND is not set | 830 | # CONFIG_SOUND is not set |
| 807 | CONFIG_HID_SUPPORT=y | 831 | CONFIG_HID_SUPPORT=y |
| 808 | CONFIG_HID=m | 832 | CONFIG_HID=m |
| 809 | # CONFIG_HID_DEBUG is not set | 833 | # CONFIG_HID_DEBUG is not set |
| 810 | # CONFIG_HIDRAW is not set | 834 | # CONFIG_HIDRAW is not set |
| 835 | # CONFIG_HID_PID is not set | ||
| 836 | |||
| 837 | # | ||
| 838 | # Special HID drivers | ||
| 839 | # | ||
| 840 | CONFIG_HID_COMPAT=y | ||
| 811 | # CONFIG_USB_SUPPORT is not set | 841 | # CONFIG_USB_SUPPORT is not set |
| 812 | # CONFIG_MMC is not set | 842 | # CONFIG_MMC is not set |
| 843 | # CONFIG_MEMSTICK is not set | ||
| 813 | # CONFIG_NEW_LEDS is not set | 844 | # CONFIG_NEW_LEDS is not set |
| 845 | # CONFIG_ACCESSIBILITY is not set | ||
| 814 | # CONFIG_RTC_CLASS is not set | 846 | # CONFIG_RTC_CLASS is not set |
| 815 | 847 | # CONFIG_DMADEVICES is not set | |
| 816 | # | ||
| 817 | # Userspace I/O | ||
| 818 | # | ||
| 819 | # CONFIG_UIO is not set | 848 | # CONFIG_UIO is not set |
| 849 | # CONFIG_STAGING is not set | ||
| 820 | 850 | ||
| 821 | # | 851 | # |
| 822 | # File systems | 852 | # File systems |
| 823 | # | 853 | # |
| 824 | # CONFIG_EXT2_FS is not set | 854 | # CONFIG_EXT2_FS is not set |
| 825 | # CONFIG_EXT3_FS is not set | 855 | # CONFIG_EXT3_FS is not set |
| 826 | # CONFIG_EXT4DEV_FS is not set | 856 | # CONFIG_EXT4_FS is not set |
| 827 | # CONFIG_REISERFS_FS is not set | 857 | # CONFIG_REISERFS_FS is not set |
| 828 | # CONFIG_JFS_FS is not set | 858 | # CONFIG_JFS_FS is not set |
| 829 | # CONFIG_FS_POSIX_ACL is not set | 859 | # CONFIG_FS_POSIX_ACL is not set |
| 860 | CONFIG_FILE_LOCKING=y | ||
| 830 | # CONFIG_XFS_FS is not set | 861 | # CONFIG_XFS_FS is not set |
| 831 | # CONFIG_GFS2_FS is not set | ||
| 832 | # CONFIG_OCFS2_FS is not set | 862 | # CONFIG_OCFS2_FS is not set |
| 833 | # CONFIG_MINIX_FS is not set | 863 | # CONFIG_DNOTIFY is not set |
| 834 | # CONFIG_ROMFS_FS is not set | ||
| 835 | CONFIG_INOTIFY=y | 864 | CONFIG_INOTIFY=y |
| 836 | CONFIG_INOTIFY_USER=y | 865 | CONFIG_INOTIFY_USER=y |
| 837 | # CONFIG_QUOTA is not set | 866 | # CONFIG_QUOTA is not set |
| 838 | # CONFIG_DNOTIFY is not set | ||
| 839 | # CONFIG_AUTOFS_FS is not set | 867 | # CONFIG_AUTOFS_FS is not set |
| 840 | # CONFIG_AUTOFS4_FS is not set | 868 | # CONFIG_AUTOFS4_FS is not set |
| 841 | # CONFIG_FUSE_FS is not set | 869 | # CONFIG_FUSE_FS is not set |
| @@ -875,11 +903,11 @@ CONFIG_SYSFS=y | |||
| 875 | # CONFIG_EFS_FS is not set | 903 | # CONFIG_EFS_FS is not set |
| 876 | CONFIG_YAFFS_FS=m | 904 | CONFIG_YAFFS_FS=m |
| 877 | CONFIG_YAFFS_YAFFS1=y | 905 | CONFIG_YAFFS_YAFFS1=y |
| 906 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 878 | # CONFIG_YAFFS_DOES_ECC is not set | 907 | # CONFIG_YAFFS_DOES_ECC is not set |
| 879 | CONFIG_YAFFS_YAFFS2=y | 908 | CONFIG_YAFFS_YAFFS2=y |
| 880 | CONFIG_YAFFS_AUTO_YAFFS2=y | 909 | CONFIG_YAFFS_AUTO_YAFFS2=y |
| 881 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | 910 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set |
| 882 | CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 | ||
| 883 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | 911 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 884 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | 912 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 885 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | 913 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| @@ -896,8 +924,11 @@ CONFIG_JFFS2_RTIME=y | |||
| 896 | # CONFIG_JFFS2_RUBIN is not set | 924 | # CONFIG_JFFS2_RUBIN is not set |
| 897 | # CONFIG_CRAMFS is not set | 925 | # CONFIG_CRAMFS is not set |
| 898 | # CONFIG_VXFS_FS is not set | 926 | # CONFIG_VXFS_FS is not set |
| 927 | # CONFIG_MINIX_FS is not set | ||
| 928 | # CONFIG_OMFS_FS is not set | ||
| 899 | # CONFIG_HPFS_FS is not set | 929 | # CONFIG_HPFS_FS is not set |
| 900 | # CONFIG_QNX4FS_FS is not set | 930 | # CONFIG_QNX4FS_FS is not set |
| 931 | # CONFIG_ROMFS_FS is not set | ||
| 901 | # CONFIG_SYSV_FS is not set | 932 | # CONFIG_SYSV_FS is not set |
| 902 | # CONFIG_UFS_FS is not set | 933 | # CONFIG_UFS_FS is not set |
| 903 | CONFIG_NETWORK_FILESYSTEMS=y | 934 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -905,13 +936,12 @@ CONFIG_NFS_FS=m | |||
| 905 | CONFIG_NFS_V3=y | 936 | CONFIG_NFS_V3=y |
| 906 | # CONFIG_NFS_V3_ACL is not set | 937 | # CONFIG_NFS_V3_ACL is not set |
| 907 | # CONFIG_NFS_V4 is not set | 938 | # CONFIG_NFS_V4 is not set |
| 908 | # CONFIG_NFS_DIRECTIO is not set | ||
| 909 | # CONFIG_NFSD is not set | 939 | # CONFIG_NFSD is not set |
| 910 | CONFIG_LOCKD=m | 940 | CONFIG_LOCKD=m |
| 911 | CONFIG_LOCKD_V4=y | 941 | CONFIG_LOCKD_V4=y |
| 912 | CONFIG_NFS_COMMON=y | 942 | CONFIG_NFS_COMMON=y |
| 913 | CONFIG_SUNRPC=m | 943 | CONFIG_SUNRPC=m |
| 914 | # CONFIG_SUNRPC_BIND34 is not set | 944 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 915 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 945 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 916 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 946 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 917 | CONFIG_SMB_FS=m | 947 | CONFIG_SMB_FS=m |
| @@ -967,9 +997,6 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 967 | # CONFIG_NLS_KOI8_U is not set | 997 | # CONFIG_NLS_KOI8_U is not set |
| 968 | # CONFIG_NLS_UTF8 is not set | 998 | # CONFIG_NLS_UTF8 is not set |
| 969 | # CONFIG_DLM is not set | 999 | # CONFIG_DLM is not set |
| 970 | CONFIG_INSTRUMENTATION=y | ||
| 971 | # CONFIG_PROFILING is not set | ||
| 972 | # CONFIG_MARKERS is not set | ||
| 973 | 1000 | ||
| 974 | # | 1001 | # |
| 975 | # Kernel hacking | 1002 | # Kernel hacking |
| @@ -977,14 +1004,53 @@ CONFIG_INSTRUMENTATION=y | |||
| 977 | # CONFIG_PRINTK_TIME is not set | 1004 | # CONFIG_PRINTK_TIME is not set |
| 978 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1005 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 979 | CONFIG_ENABLE_MUST_CHECK=y | 1006 | CONFIG_ENABLE_MUST_CHECK=y |
| 1007 | CONFIG_FRAME_WARN=1024 | ||
| 980 | # CONFIG_MAGIC_SYSRQ is not set | 1008 | # CONFIG_MAGIC_SYSRQ is not set |
| 981 | # CONFIG_UNUSED_SYMBOLS is not set | 1009 | # CONFIG_UNUSED_SYMBOLS is not set |
| 982 | CONFIG_DEBUG_FS=y | 1010 | CONFIG_DEBUG_FS=y |
| 983 | # CONFIG_HEADERS_CHECK is not set | 1011 | # CONFIG_HEADERS_CHECK is not set |
| 984 | # CONFIG_DEBUG_KERNEL is not set | 1012 | CONFIG_DEBUG_KERNEL=y |
| 1013 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1014 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1015 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1016 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1017 | CONFIG_SCHED_DEBUG=y | ||
| 1018 | # CONFIG_SCHEDSTATS is not set | ||
| 1019 | # CONFIG_TIMER_STATS is not set | ||
| 1020 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1021 | # CONFIG_DEBUG_SLAB is not set | ||
| 1022 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1023 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1024 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1025 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1026 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1027 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1028 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 985 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1029 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1030 | CONFIG_DEBUG_INFO=y | ||
| 1031 | # CONFIG_DEBUG_VM is not set | ||
| 1032 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1033 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1034 | # CONFIG_DEBUG_LIST is not set | ||
| 1035 | # CONFIG_DEBUG_SG is not set | ||
| 1036 | # CONFIG_FRAME_POINTER is not set | ||
| 1037 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1038 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1039 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1040 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1041 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1042 | # CONFIG_FAULT_INJECTION is not set | ||
| 1043 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1044 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 986 | # CONFIG_SAMPLES is not set | 1045 | # CONFIG_SAMPLES is not set |
| 1046 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1047 | # CONFIG_KGDB is not set | ||
| 1048 | # CONFIG_DEBUG_STACKOVERFLOW is not set | ||
| 1049 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1050 | CONFIG_DEBUG_VERBOSE=y | ||
| 987 | CONFIG_DEBUG_MMRS=y | 1051 | CONFIG_DEBUG_MMRS=y |
| 1052 | # CONFIG_DEBUG_HWERR is not set | ||
| 1053 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 988 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1054 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 989 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1055 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 990 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1056 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -994,7 +1060,6 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | |||
| 994 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set | 1060 | # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set |
| 995 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set | 1061 | # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set |
| 996 | CONFIG_EARLY_PRINTK=y | 1062 | CONFIG_EARLY_PRINTK=y |
| 997 | # CONFIG_DUAL_CORE_TEST_MODULE is not set | ||
| 998 | CONFIG_CPLB_INFO=y | 1063 | CONFIG_CPLB_INFO=y |
| 999 | CONFIG_ACCESS_CHECK=y | 1064 | CONFIG_ACCESS_CHECK=y |
| 1000 | 1065 | ||
| @@ -1003,9 +1068,94 @@ CONFIG_ACCESS_CHECK=y | |||
| 1003 | # | 1068 | # |
| 1004 | # CONFIG_KEYS is not set | 1069 | # CONFIG_KEYS is not set |
| 1005 | CONFIG_SECURITY=y | 1070 | CONFIG_SECURITY=y |
| 1071 | # CONFIG_SECURITYFS is not set | ||
| 1006 | # CONFIG_SECURITY_NETWORK is not set | 1072 | # CONFIG_SECURITY_NETWORK is not set |
| 1007 | # CONFIG_SECURITY_CAPABILITIES is not set | 1073 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1008 | # CONFIG_CRYPTO is not set | 1074 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 |
| 1075 | CONFIG_CRYPTO=y | ||
| 1076 | |||
| 1077 | # | ||
| 1078 | # Crypto core or helper | ||
| 1079 | # | ||
| 1080 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1081 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1082 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1083 | # CONFIG_CRYPTO_NULL is not set | ||
| 1084 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1085 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1086 | # CONFIG_CRYPTO_TEST is not set | ||
| 1087 | |||
| 1088 | # | ||
| 1089 | # Authenticated Encryption with Associated Data | ||
| 1090 | # | ||
| 1091 | # CONFIG_CRYPTO_CCM is not set | ||
| 1092 | # CONFIG_CRYPTO_GCM is not set | ||
| 1093 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1094 | |||
| 1095 | # | ||
| 1096 | # Block modes | ||
| 1097 | # | ||
| 1098 | # CONFIG_CRYPTO_CBC is not set | ||
| 1099 | # CONFIG_CRYPTO_CTR is not set | ||
| 1100 | # CONFIG_CRYPTO_CTS is not set | ||
| 1101 | # CONFIG_CRYPTO_ECB is not set | ||
| 1102 | # CONFIG_CRYPTO_LRW is not set | ||
| 1103 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1104 | # CONFIG_CRYPTO_XTS is not set | ||
| 1105 | |||
| 1106 | # | ||
| 1107 | # Hash modes | ||
| 1108 | # | ||
| 1109 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1110 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1111 | |||
| 1112 | # | ||
| 1113 | # Digest | ||
| 1114 | # | ||
| 1115 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1116 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1117 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1118 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1119 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1120 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1121 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1122 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1123 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1124 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1125 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1126 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1127 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1128 | |||
| 1129 | # | ||
| 1130 | # Ciphers | ||
| 1131 | # | ||
| 1132 | # CONFIG_CRYPTO_AES is not set | ||
| 1133 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1134 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1135 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1136 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1137 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1138 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1139 | # CONFIG_CRYPTO_DES is not set | ||
| 1140 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1141 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1142 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1143 | # CONFIG_CRYPTO_SEED is not set | ||
| 1144 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1145 | # CONFIG_CRYPTO_TEA is not set | ||
| 1146 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1147 | |||
| 1148 | # | ||
| 1149 | # Compression | ||
| 1150 | # | ||
| 1151 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1152 | # CONFIG_CRYPTO_LZO is not set | ||
| 1153 | |||
| 1154 | # | ||
| 1155 | # Random Number Generation | ||
| 1156 | # | ||
| 1157 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1158 | CONFIG_CRYPTO_HW=y | ||
| 1009 | 1159 | ||
| 1010 | # | 1160 | # |
| 1011 | # Library routines | 1161 | # Library routines |
| @@ -1013,6 +1163,7 @@ CONFIG_SECURITY=y | |||
| 1013 | CONFIG_BITREVERSE=y | 1163 | CONFIG_BITREVERSE=y |
| 1014 | CONFIG_CRC_CCITT=m | 1164 | CONFIG_CRC_CCITT=m |
| 1015 | # CONFIG_CRC16 is not set | 1165 | # CONFIG_CRC16 is not set |
| 1166 | # CONFIG_CRC_T10DIF is not set | ||
| 1016 | # CONFIG_CRC_ITU_T is not set | 1167 | # CONFIG_CRC_ITU_T is not set |
| 1017 | CONFIG_CRC32=y | 1168 | CONFIG_CRC32=y |
| 1018 | # CONFIG_CRC7 is not set | 1169 | # CONFIG_CRC7 is not set |
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig index 2921f9952d5f..9683b2e13097 100644 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ b/arch/blackfin/configs/BlackStamp_defconfig | |||
| @@ -53,7 +53,7 @@ CONFIG_KALLSYMS=y | |||
| 53 | CONFIG_HOTPLUG=y | 53 | CONFIG_HOTPLUG=y |
| 54 | CONFIG_PRINTK=y | 54 | CONFIG_PRINTK=y |
| 55 | CONFIG_BUG=y | 55 | CONFIG_BUG=y |
| 56 | CONFIG_ELF_CORE=y | 56 | # CONFIG_ELF_CORE is not set |
| 57 | CONFIG_COMPAT_BRK=y | 57 | CONFIG_COMPAT_BRK=y |
| 58 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 59 | CONFIG_FUTEX=y | 59 | CONFIG_FUTEX=y |
| @@ -276,7 +276,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 276 | CONFIG_ZONE_DMA_FLAG=1 | 276 | CONFIG_ZONE_DMA_FLAG=1 |
| 277 | CONFIG_VIRT_TO_BUS=y | 277 | CONFIG_VIRT_TO_BUS=y |
| 278 | CONFIG_BFIN_GPTIMERS=y | 278 | CONFIG_BFIN_GPTIMERS=y |
| 279 | CONFIG_BFIN_DMA_5XX=y | ||
| 280 | # CONFIG_DMA_UNCACHED_4M is not set | 279 | # CONFIG_DMA_UNCACHED_4M is not set |
| 281 | # CONFIG_DMA_UNCACHED_2M is not set | 280 | # CONFIG_DMA_UNCACHED_2M is not set |
| 282 | CONFIG_DMA_UNCACHED_1M=y | 281 | CONFIG_DMA_UNCACHED_1M=y |
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig index b6a14635fb91..a041e7eba770 100644 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ b/arch/blackfin/configs/CM-BF527_defconfig | |||
| @@ -42,7 +42,7 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_FAIR_GROUP_SCHED=y | 42 | CONFIG_FAIR_GROUP_SCHED=y |
| 43 | CONFIG_FAIR_USER_SCHED=y | 43 | CONFIG_FAIR_USER_SCHED=y |
| 44 | # CONFIG_FAIR_CGROUP_SCHED is not set | 44 | # CONFIG_FAIR_CGROUP_SCHED is not set |
| 45 | CONFIG_SYSFS_DEPRECATED=y | 45 | # CONFIG_SYSFS_DEPRECATED is not set |
| 46 | # CONFIG_RELAY is not set | 46 | # CONFIG_RELAY is not set |
| 47 | CONFIG_BLK_DEV_INITRD=y | 47 | CONFIG_BLK_DEV_INITRD=y |
| 48 | CONFIG_INITRAMFS_SOURCE="" | 48 | CONFIG_INITRAMFS_SOURCE="" |
| @@ -56,7 +56,7 @@ CONFIG_KALLSYMS=y | |||
| 56 | CONFIG_HOTPLUG=y | 56 | CONFIG_HOTPLUG=y |
| 57 | CONFIG_PRINTK=y | 57 | CONFIG_PRINTK=y |
| 58 | CONFIG_BUG=y | 58 | CONFIG_BUG=y |
| 59 | CONFIG_ELF_CORE=y | 59 | # CONFIG_ELF_CORE is not set |
| 60 | CONFIG_BASE_FULL=y | 60 | CONFIG_BASE_FULL=y |
| 61 | CONFIG_FUTEX=y | 61 | CONFIG_FUTEX=y |
| 62 | CONFIG_ANON_INODES=y | 62 | CONFIG_ANON_INODES=y |
| @@ -190,14 +190,14 @@ CONFIG_IRQ_MAC_RX=11 | |||
| 190 | CONFIG_IRQ_PORTH_INTA=11 | 190 | CONFIG_IRQ_PORTH_INTA=11 |
| 191 | CONFIG_IRQ_MAC_TX=11 | 191 | CONFIG_IRQ_MAC_TX=11 |
| 192 | CONFIG_IRQ_PORTH_INTB=11 | 192 | CONFIG_IRQ_PORTH_INTB=11 |
| 193 | CONFIG_IRQ_TMR0=12 | 193 | CONFIG_IRQ_TIMER0=12 |
| 194 | CONFIG_IRQ_TMR1=12 | 194 | CONFIG_IRQ_TIMER1=12 |
| 195 | CONFIG_IRQ_TMR2=12 | 195 | CONFIG_IRQ_TIMER2=12 |
| 196 | CONFIG_IRQ_TMR3=12 | 196 | CONFIG_IRQ_TIMER3=12 |
| 197 | CONFIG_IRQ_TMR4=12 | 197 | CONFIG_IRQ_TIMER4=12 |
| 198 | CONFIG_IRQ_TMR5=12 | 198 | CONFIG_IRQ_TIMER5=12 |
| 199 | CONFIG_IRQ_TMR6=12 | 199 | CONFIG_IRQ_TIMER6=12 |
| 200 | CONFIG_IRQ_TMR7=12 | 200 | CONFIG_IRQ_TIMER7=12 |
| 201 | CONFIG_IRQ_PORTG_INTA=12 | 201 | CONFIG_IRQ_PORTG_INTA=12 |
| 202 | CONFIG_IRQ_PORTG_INTB=12 | 202 | CONFIG_IRQ_PORTG_INTB=12 |
| 203 | CONFIG_IRQ_MEM_DMA0=13 | 203 | CONFIG_IRQ_MEM_DMA0=13 |
| @@ -292,7 +292,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 292 | CONFIG_ZONE_DMA_FLAG=1 | 292 | CONFIG_ZONE_DMA_FLAG=1 |
| 293 | CONFIG_VIRT_TO_BUS=y | 293 | CONFIG_VIRT_TO_BUS=y |
| 294 | CONFIG_BFIN_GPTIMERS=y | 294 | CONFIG_BFIN_GPTIMERS=y |
| 295 | CONFIG_BFIN_DMA_5XX=y | ||
| 296 | # CONFIG_DMA_UNCACHED_4M is not set | 295 | # CONFIG_DMA_UNCACHED_4M is not set |
| 297 | # CONFIG_DMA_UNCACHED_2M is not set | 296 | # CONFIG_DMA_UNCACHED_2M is not set |
| 298 | CONFIG_DMA_UNCACHED_1M=y | 297 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -650,6 +649,7 @@ CONFIG_BFIN_OTP=y | |||
| 650 | # CONFIG_TWI_LCD is not set | 649 | # CONFIG_TWI_LCD is not set |
| 651 | CONFIG_SIMPLE_GPIO=m | 650 | CONFIG_SIMPLE_GPIO=m |
| 652 | # CONFIG_VT is not set | 651 | # CONFIG_VT is not set |
| 652 | # CONFIG_DEVKMEM is not set | ||
| 653 | # CONFIG_SERIAL_NONSTANDARD is not set | 653 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 654 | 654 | ||
| 655 | # | 655 | # |
| @@ -699,7 +699,7 @@ CONFIG_I2C_CHARDEV=m | |||
| 699 | # I2C Hardware Bus support | 699 | # I2C Hardware Bus support |
| 700 | # | 700 | # |
| 701 | CONFIG_I2C_BLACKFIN_TWI=m | 701 | CONFIG_I2C_BLACKFIN_TWI=m |
| 702 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | 702 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 |
| 703 | # CONFIG_I2C_GPIO is not set | 703 | # CONFIG_I2C_GPIO is not set |
| 704 | # CONFIG_I2C_OCORES is not set | 704 | # CONFIG_I2C_OCORES is not set |
| 705 | # CONFIG_I2C_PARPORT_LIGHT is not set | 705 | # CONFIG_I2C_PARPORT_LIGHT is not set |
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index c3ba9066b935..085211b9e4e4 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig | |||
| @@ -42,7 +42,7 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 42 | CONFIG_IKCONFIG=y | 42 | CONFIG_IKCONFIG=y |
| 43 | CONFIG_IKCONFIG_PROC=y | 43 | CONFIG_IKCONFIG_PROC=y |
| 44 | CONFIG_LOG_BUF_SHIFT=14 | 44 | CONFIG_LOG_BUF_SHIFT=14 |
| 45 | CONFIG_SYSFS_DEPRECATED=y | 45 | # CONFIG_SYSFS_DEPRECATED is not set |
| 46 | # CONFIG_RELAY is not set | 46 | # CONFIG_RELAY is not set |
| 47 | # CONFIG_BLK_DEV_INITRD is not set | 47 | # CONFIG_BLK_DEV_INITRD is not set |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y | |||
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| 56 | CONFIG_PRINTK=y | 56 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 57 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 58 | # CONFIG_ELF_CORE is not set |
| 59 | CONFIG_BASE_FULL=y | 59 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 60 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 61 | CONFIG_ANON_INODES=y |
| @@ -254,7 +254,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 254 | CONFIG_ZONE_DMA_FLAG=1 | 254 | CONFIG_ZONE_DMA_FLAG=1 |
| 255 | CONFIG_LARGE_ALLOCS=y | 255 | CONFIG_LARGE_ALLOCS=y |
| 256 | # CONFIG_BFIN_GPTIMERS is not set | 256 | # CONFIG_BFIN_GPTIMERS is not set |
| 257 | CONFIG_BFIN_DMA_5XX=y | ||
| 258 | # CONFIG_DMA_UNCACHED_2M is not set | 257 | # CONFIG_DMA_UNCACHED_2M is not set |
| 259 | CONFIG_DMA_UNCACHED_1M=y | 258 | CONFIG_DMA_UNCACHED_1M=y |
| 260 | # CONFIG_DMA_UNCACHED_NONE is not set | 259 | # CONFIG_DMA_UNCACHED_NONE is not set |
| @@ -598,6 +597,7 @@ CONFIG_NETDEV_10000=y | |||
| 598 | CONFIG_BFIN_SPORT=y | 597 | CONFIG_BFIN_SPORT=y |
| 599 | # CONFIG_BFIN_TIMER_LATENCY is not set | 598 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 600 | # CONFIG_VT is not set | 599 | # CONFIG_VT is not set |
| 600 | # CONFIG_DEVKMEM is not set | ||
| 601 | # CONFIG_SERIAL_NONSTANDARD is not set | 601 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 602 | 602 | ||
| 603 | # | 603 | # |
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig index cdc6b7feb59e..750203e27a46 100644 --- a/arch/blackfin/configs/CM-BF537E_defconfig +++ b/arch/blackfin/configs/CM-BF537E_defconfig | |||
| @@ -42,7 +42,7 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 42 | CONFIG_IKCONFIG=y | 42 | CONFIG_IKCONFIG=y |
| 43 | CONFIG_IKCONFIG_PROC=y | 43 | CONFIG_IKCONFIG_PROC=y |
| 44 | CONFIG_LOG_BUF_SHIFT=14 | 44 | CONFIG_LOG_BUF_SHIFT=14 |
| 45 | CONFIG_SYSFS_DEPRECATED=y | 45 | # CONFIG_SYSFS_DEPRECATED is not set |
| 46 | # CONFIG_RELAY is not set | 46 | # CONFIG_RELAY is not set |
| 47 | # CONFIG_BLK_DEV_INITRD is not set | 47 | # CONFIG_BLK_DEV_INITRD is not set |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y | |||
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| 56 | CONFIG_PRINTK=y | 56 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 57 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 58 | # CONFIG_ELF_CORE is not set |
| 59 | CONFIG_BASE_FULL=y | 59 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 60 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 61 | CONFIG_ANON_INODES=y |
| @@ -157,14 +157,14 @@ CONFIG_IRQ_UART1_RX=10 | |||
| 157 | CONFIG_IRQ_UART1_TX=10 | 157 | CONFIG_IRQ_UART1_TX=10 |
| 158 | CONFIG_IRQ_MAC_RX=11 | 158 | CONFIG_IRQ_MAC_RX=11 |
| 159 | CONFIG_IRQ_MAC_TX=11 | 159 | CONFIG_IRQ_MAC_TX=11 |
| 160 | CONFIG_IRQ_TMR0=12 | 160 | CONFIG_IRQ_TIMER0=12 |
| 161 | CONFIG_IRQ_TMR1=12 | 161 | CONFIG_IRQ_TIMER1=12 |
| 162 | CONFIG_IRQ_TMR2=12 | 162 | CONFIG_IRQ_TIMER2=12 |
| 163 | CONFIG_IRQ_TMR3=12 | 163 | CONFIG_IRQ_TIMER3=12 |
| 164 | CONFIG_IRQ_TMR4=12 | 164 | CONFIG_IRQ_TIMER4=12 |
| 165 | CONFIG_IRQ_TMR5=12 | 165 | CONFIG_IRQ_TIMER5=12 |
| 166 | CONFIG_IRQ_TMR6=12 | 166 | CONFIG_IRQ_TIMER6=12 |
| 167 | CONFIG_IRQ_TMR7=12 | 167 | CONFIG_IRQ_TIMER7=12 |
| 168 | CONFIG_IRQ_PORTG_INTB=12 | 168 | CONFIG_IRQ_PORTG_INTB=12 |
| 169 | CONFIG_IRQ_MEM_DMA0=13 | 169 | CONFIG_IRQ_MEM_DMA0=13 |
| 170 | CONFIG_IRQ_MEM_DMA1=13 | 170 | CONFIG_IRQ_MEM_DMA1=13 |
| @@ -262,7 +262,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 262 | CONFIG_ZONE_DMA_FLAG=1 | 262 | CONFIG_ZONE_DMA_FLAG=1 |
| 263 | CONFIG_LARGE_ALLOCS=y | 263 | CONFIG_LARGE_ALLOCS=y |
| 264 | # CONFIG_BFIN_GPTIMERS is not set | 264 | # CONFIG_BFIN_GPTIMERS is not set |
| 265 | CONFIG_BFIN_DMA_5XX=y | ||
| 266 | # CONFIG_DMA_UNCACHED_2M is not set | 265 | # CONFIG_DMA_UNCACHED_2M is not set |
| 267 | CONFIG_DMA_UNCACHED_1M=y | 266 | CONFIG_DMA_UNCACHED_1M=y |
| 268 | # CONFIG_DMA_UNCACHED_NONE is not set | 267 | # CONFIG_DMA_UNCACHED_NONE is not set |
| @@ -627,6 +626,7 @@ CONFIG_NETDEV_10000=y | |||
| 627 | CONFIG_BFIN_SPORT=y | 626 | CONFIG_BFIN_SPORT=y |
| 628 | # CONFIG_BFIN_TIMER_LATENCY is not set | 627 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 629 | # CONFIG_VT is not set | 628 | # CONFIG_VT is not set |
| 629 | # CONFIG_DEVKMEM is not set | ||
| 630 | # CONFIG_SERIAL_NONSTANDARD is not set | 630 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 631 | 631 | ||
| 632 | # | 632 | # |
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig index f074bdcd1ce5..dec8a7d5cc0e 100644 --- a/arch/blackfin/configs/CM-BF537U_defconfig +++ b/arch/blackfin/configs/CM-BF537U_defconfig | |||
| @@ -42,7 +42,7 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 42 | CONFIG_IKCONFIG=y | 42 | CONFIG_IKCONFIG=y |
| 43 | CONFIG_IKCONFIG_PROC=y | 43 | CONFIG_IKCONFIG_PROC=y |
| 44 | CONFIG_LOG_BUF_SHIFT=14 | 44 | CONFIG_LOG_BUF_SHIFT=14 |
| 45 | CONFIG_SYSFS_DEPRECATED=y | 45 | # CONFIG_SYSFS_DEPRECATED is not set |
| 46 | # CONFIG_RELAY is not set | 46 | # CONFIG_RELAY is not set |
| 47 | # CONFIG_BLK_DEV_INITRD is not set | 47 | # CONFIG_BLK_DEV_INITRD is not set |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y | |||
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| 56 | CONFIG_PRINTK=y | 56 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 57 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 58 | # CONFIG_ELF_CORE is not set |
| 59 | CONFIG_BASE_FULL=y | 59 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 60 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 61 | CONFIG_ANON_INODES=y |
| @@ -157,14 +157,14 @@ CONFIG_IRQ_UART1_RX=10 | |||
| 157 | CONFIG_IRQ_UART1_TX=10 | 157 | CONFIG_IRQ_UART1_TX=10 |
| 158 | CONFIG_IRQ_MAC_RX=11 | 158 | CONFIG_IRQ_MAC_RX=11 |
| 159 | CONFIG_IRQ_MAC_TX=11 | 159 | CONFIG_IRQ_MAC_TX=11 |
| 160 | CONFIG_IRQ_TMR0=12 | 160 | CONFIG_IRQ_TIMER0=12 |
| 161 | CONFIG_IRQ_TMR1=12 | 161 | CONFIG_IRQ_TIMER1=12 |
| 162 | CONFIG_IRQ_TMR2=12 | 162 | CONFIG_IRQ_TIMER2=12 |
| 163 | CONFIG_IRQ_TMR3=12 | 163 | CONFIG_IRQ_TIMER3=12 |
| 164 | CONFIG_IRQ_TMR4=12 | 164 | CONFIG_IRQ_TIMER4=12 |
| 165 | CONFIG_IRQ_TMR5=12 | 165 | CONFIG_IRQ_TIMER5=12 |
| 166 | CONFIG_IRQ_TMR6=12 | 166 | CONFIG_IRQ_TIMER6=12 |
| 167 | CONFIG_IRQ_TMR7=12 | 167 | CONFIG_IRQ_TIMER7=12 |
| 168 | CONFIG_IRQ_PORTG_INTB=12 | 168 | CONFIG_IRQ_PORTG_INTB=12 |
| 169 | CONFIG_IRQ_MEM_DMA0=13 | 169 | CONFIG_IRQ_MEM_DMA0=13 |
| 170 | CONFIG_IRQ_MEM_DMA1=13 | 170 | CONFIG_IRQ_MEM_DMA1=13 |
| @@ -262,7 +262,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 262 | CONFIG_ZONE_DMA_FLAG=1 | 262 | CONFIG_ZONE_DMA_FLAG=1 |
| 263 | CONFIG_LARGE_ALLOCS=y | 263 | CONFIG_LARGE_ALLOCS=y |
| 264 | # CONFIG_BFIN_GPTIMERS is not set | 264 | # CONFIG_BFIN_GPTIMERS is not set |
| 265 | CONFIG_BFIN_DMA_5XX=y | ||
| 266 | # CONFIG_DMA_UNCACHED_2M is not set | 265 | # CONFIG_DMA_UNCACHED_2M is not set |
| 267 | CONFIG_DMA_UNCACHED_1M=y | 266 | CONFIG_DMA_UNCACHED_1M=y |
| 268 | # CONFIG_DMA_UNCACHED_NONE is not set | 267 | # CONFIG_DMA_UNCACHED_NONE is not set |
| @@ -607,6 +606,7 @@ CONFIG_NETDEV_10000=y | |||
| 607 | CONFIG_BFIN_SPORT=y | 606 | CONFIG_BFIN_SPORT=y |
| 608 | # CONFIG_BFIN_TIMER_LATENCY is not set | 607 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 609 | # CONFIG_VT is not set | 608 | # CONFIG_VT is not set |
| 609 | # CONFIG_DEVKMEM is not set | ||
| 610 | # CONFIG_SERIAL_NONSTANDARD is not set | 610 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 611 | 611 | ||
| 612 | # | 612 | # |
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index 5c44fdb8e6e3..efd68bc78f35 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig | |||
| @@ -41,7 +41,7 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 41 | CONFIG_FAIR_GROUP_SCHED=y | 41 | CONFIG_FAIR_GROUP_SCHED=y |
| 42 | CONFIG_FAIR_USER_SCHED=y | 42 | CONFIG_FAIR_USER_SCHED=y |
| 43 | # CONFIG_FAIR_CGROUP_SCHED is not set | 43 | # CONFIG_FAIR_CGROUP_SCHED is not set |
| 44 | CONFIG_SYSFS_DEPRECATED=y | 44 | # CONFIG_SYSFS_DEPRECATED is not set |
| 45 | # CONFIG_RELAY is not set | 45 | # CONFIG_RELAY is not set |
| 46 | CONFIG_BLK_DEV_INITRD=y | 46 | CONFIG_BLK_DEV_INITRD=y |
| 47 | CONFIG_INITRAMFS_SOURCE="" | 47 | CONFIG_INITRAMFS_SOURCE="" |
| @@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y | |||
| 55 | CONFIG_HOTPLUG=y | 55 | CONFIG_HOTPLUG=y |
| 56 | CONFIG_PRINTK=y | 56 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 57 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 58 | # CONFIG_ELF_CORE is not set |
| 59 | CONFIG_BASE_FULL=y | 59 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 60 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 61 | CONFIG_ANON_INODES=y |
| @@ -325,7 +325,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 325 | CONFIG_ZONE_DMA_FLAG=1 | 325 | CONFIG_ZONE_DMA_FLAG=1 |
| 326 | CONFIG_VIRT_TO_BUS=y | 326 | CONFIG_VIRT_TO_BUS=y |
| 327 | # CONFIG_BFIN_GPTIMERS is not set | 327 | # CONFIG_BFIN_GPTIMERS is not set |
| 328 | CONFIG_BFIN_DMA_5XX=y | ||
| 329 | # CONFIG_DMA_UNCACHED_2M is not set | 328 | # CONFIG_DMA_UNCACHED_2M is not set |
| 330 | CONFIG_DMA_UNCACHED_1M=y | 329 | CONFIG_DMA_UNCACHED_1M=y |
| 331 | # CONFIG_DMA_UNCACHED_NONE is not set | 330 | # CONFIG_DMA_UNCACHED_NONE is not set |
| @@ -544,7 +543,7 @@ CONFIG_MTD_RAM=y | |||
| 544 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 543 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 545 | CONFIG_MTD_PHYSMAP=y | 544 | CONFIG_MTD_PHYSMAP=y |
| 546 | CONFIG_MTD_PHYSMAP_START=0x20000000 | 545 | CONFIG_MTD_PHYSMAP_START=0x20000000 |
| 547 | CONFIG_MTD_PHYSMAP_LEN=0x800000 | 546 | CONFIG_MTD_PHYSMAP_LEN=0 |
| 548 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | 547 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 |
| 549 | # CONFIG_MTD_UCLINUX is not set | 548 | # CONFIG_MTD_UCLINUX is not set |
| 550 | # CONFIG_MTD_PLATRAM is not set | 549 | # CONFIG_MTD_PLATRAM is not set |
| @@ -732,6 +731,7 @@ CONFIG_BFIN_OTP=y | |||
| 732 | # CONFIG_TWI_LCD is not set | 731 | # CONFIG_TWI_LCD is not set |
| 733 | # CONFIG_SIMPLE_GPIO is not set | 732 | # CONFIG_SIMPLE_GPIO is not set |
| 734 | # CONFIG_VT is not set | 733 | # CONFIG_VT is not set |
| 734 | # CONFIG_DEVKMEM is not set | ||
| 735 | # CONFIG_SERIAL_NONSTANDARD is not set | 735 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 736 | 736 | ||
| 737 | # | 737 | # |
| @@ -782,7 +782,7 @@ CONFIG_I2C_CHARDEV=y | |||
| 782 | # I2C Hardware Bus support | 782 | # I2C Hardware Bus support |
| 783 | # | 783 | # |
| 784 | CONFIG_I2C_BLACKFIN_TWI=y | 784 | CONFIG_I2C_BLACKFIN_TWI=y |
| 785 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | 785 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 |
| 786 | # CONFIG_I2C_GPIO is not set | 786 | # CONFIG_I2C_GPIO is not set |
| 787 | # CONFIG_I2C_OCORES is not set | 787 | # CONFIG_I2C_OCORES is not set |
| 788 | # CONFIG_I2C_PARPORT_LIGHT is not set | 788 | # CONFIG_I2C_PARPORT_LIGHT is not set |
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig index 086fe5dda495..346bc7af8f42 100644 --- a/arch/blackfin/configs/CM-BF561_defconfig +++ b/arch/blackfin/configs/CM-BF561_defconfig | |||
| @@ -42,7 +42,7 @@ CONFIG_LOG_BUF_SHIFT=14 | |||
| 42 | CONFIG_FAIR_GROUP_SCHED=y | 42 | CONFIG_FAIR_GROUP_SCHED=y |
| 43 | CONFIG_FAIR_USER_SCHED=y | 43 | CONFIG_FAIR_USER_SCHED=y |
| 44 | # CONFIG_FAIR_CGROUP_SCHED is not set | 44 | # CONFIG_FAIR_CGROUP_SCHED is not set |
| 45 | CONFIG_SYSFS_DEPRECATED=y | 45 | # CONFIG_SYSFS_DEPRECATED is not set |
| 46 | # CONFIG_RELAY is not set | 46 | # CONFIG_RELAY is not set |
| 47 | # CONFIG_BLK_DEV_INITRD is not set | 47 | # CONFIG_BLK_DEV_INITRD is not set |
| 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 48 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| @@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y | |||
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| 56 | CONFIG_PRINTK=y | 56 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 57 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 58 | # CONFIG_ELF_CORE is not set |
| 59 | CONFIG_BASE_FULL=y | 59 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 60 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 61 | CONFIG_ANON_INODES=y |
| @@ -300,7 +300,6 @@ CONFIG_ZONE_DMA_FLAG=1 | |||
| 300 | CONFIG_VIRT_TO_BUS=y | 300 | CONFIG_VIRT_TO_BUS=y |
| 301 | CONFIG_LARGE_ALLOCS=y | 301 | CONFIG_LARGE_ALLOCS=y |
| 302 | # CONFIG_BFIN_GPTIMERS is not set | 302 | # CONFIG_BFIN_GPTIMERS is not set |
| 303 | CONFIG_BFIN_DMA_5XX=y | ||
| 304 | # CONFIG_DMA_UNCACHED_2M is not set | 303 | # CONFIG_DMA_UNCACHED_2M is not set |
| 305 | CONFIG_DMA_UNCACHED_1M=y | 304 | CONFIG_DMA_UNCACHED_1M=y |
| 306 | # CONFIG_DMA_UNCACHED_NONE is not set | 305 | # CONFIG_DMA_UNCACHED_NONE is not set |
| @@ -612,6 +611,7 @@ CONFIG_NETDEV_10000=y | |||
| 612 | # CONFIG_BFIN_TIMER_LATENCY is not set | 611 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 613 | # CONFIG_SIMPLE_GPIO is not set | 612 | # CONFIG_SIMPLE_GPIO is not set |
| 614 | # CONFIG_VT is not set | 613 | # CONFIG_VT is not set |
| 614 | # CONFIG_DEVKMEM is not set | ||
| 615 | # CONFIG_SERIAL_NONSTANDARD is not set | 615 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 616 | 616 | ||
| 617 | # | 617 | # |
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index 1fc31f1b762b..5d3901d23fd1 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig | |||
| @@ -54,7 +54,7 @@ CONFIG_KALLSYMS=y | |||
| 54 | CONFIG_HOTPLUG=y | 54 | CONFIG_HOTPLUG=y |
| 55 | CONFIG_PRINTK=y | 55 | CONFIG_PRINTK=y |
| 56 | CONFIG_BUG=y | 56 | CONFIG_BUG=y |
| 57 | CONFIG_ELF_CORE=y | 57 | # CONFIG_ELF_CORE is not set |
| 58 | CONFIG_BASE_FULL=y | 58 | CONFIG_BASE_FULL=y |
| 59 | CONFIG_FUTEX=y | 59 | CONFIG_FUTEX=y |
| 60 | CONFIG_ANON_INODES=y | 60 | CONFIG_ANON_INODES=y |
| @@ -250,7 +250,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 250 | CONFIG_ZONE_DMA_FLAG=1 | 250 | CONFIG_ZONE_DMA_FLAG=1 |
| 251 | CONFIG_LARGE_ALLOCS=y | 251 | CONFIG_LARGE_ALLOCS=y |
| 252 | CONFIG_BFIN_GPTIMERS=y | 252 | CONFIG_BFIN_GPTIMERS=y |
| 253 | CONFIG_BFIN_DMA_5XX=y | ||
| 254 | # CONFIG_DMA_UNCACHED_2M is not set | 253 | # CONFIG_DMA_UNCACHED_2M is not set |
| 255 | CONFIG_DMA_UNCACHED_1M=y | 254 | CONFIG_DMA_UNCACHED_1M=y |
| 256 | # CONFIG_DMA_UNCACHED_NONE is not set | 255 | # CONFIG_DMA_UNCACHED_NONE is not set |
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig index 285d2241df26..e66f5daaa828 100644 --- a/arch/blackfin/configs/IP0X_defconfig +++ b/arch/blackfin/configs/IP0X_defconfig | |||
| @@ -55,7 +55,7 @@ CONFIG_KALLSYMS=y | |||
| 55 | # CONFIG_HOTPLUG is not set | 55 | # CONFIG_HOTPLUG is not set |
| 56 | CONFIG_PRINTK=y | 56 | CONFIG_PRINTK=y |
| 57 | CONFIG_BUG=y | 57 | CONFIG_BUG=y |
| 58 | CONFIG_ELF_CORE=y | 58 | # CONFIG_ELF_CORE is not set |
| 59 | CONFIG_BASE_FULL=y | 59 | CONFIG_BASE_FULL=y |
| 60 | CONFIG_FUTEX=y | 60 | CONFIG_FUTEX=y |
| 61 | CONFIG_ANON_INODES=y | 61 | CONFIG_ANON_INODES=y |
| @@ -262,7 +262,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 262 | CONFIG_ZONE_DMA_FLAG=1 | 262 | CONFIG_ZONE_DMA_FLAG=1 |
| 263 | CONFIG_LARGE_ALLOCS=y | 263 | CONFIG_LARGE_ALLOCS=y |
| 264 | # CONFIG_BFIN_GPTIMERS is not set | 264 | # CONFIG_BFIN_GPTIMERS is not set |
| 265 | CONFIG_BFIN_DMA_5XX=y | ||
| 266 | # CONFIG_DMA_UNCACHED_2M is not set | 265 | # CONFIG_DMA_UNCACHED_2M is not set |
| 267 | CONFIG_DMA_UNCACHED_1M=y | 266 | CONFIG_DMA_UNCACHED_1M=y |
| 268 | # CONFIG_DMA_UNCACHED_NONE is not set | 267 | # CONFIG_DMA_UNCACHED_NONE is not set |
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig index bffca7de65d4..ce5dde9de9db 100644 --- a/arch/blackfin/configs/PNAV-10_defconfig +++ b/arch/blackfin/configs/PNAV-10_defconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.22.12 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # | 4 | # |
| 5 | # CONFIG_MMU is not set | 5 | # CONFIG_MMU is not set |
| 6 | # CONFIG_FPU is not set | 6 | # CONFIG_FPU is not set |
| @@ -8,41 +8,37 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 8 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 9 | CONFIG_BLACKFIN=y | 9 | CONFIG_BLACKFIN=y |
| 10 | CONFIG_ZONE_DMA=y | 10 | CONFIG_ZONE_DMA=y |
| 11 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 11 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 13 | CONFIG_GENERIC_HWEIGHT=y | 12 | CONFIG_GENERIC_HWEIGHT=y |
| 14 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| 15 | CONFIG_GENERIC_IRQ_PROBE=y | 14 | CONFIG_GENERIC_IRQ_PROBE=y |
| 16 | CONFIG_GENERIC_TIME=y | ||
| 17 | CONFIG_GENERIC_GPIO=y | 15 | CONFIG_GENERIC_GPIO=y |
| 18 | CONFIG_FORCE_MAX_ZONEORDER=14 | 16 | CONFIG_FORCE_MAX_ZONEORDER=14 |
| 19 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 17 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 20 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 18 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 21 | 19 | ||
| 22 | # | 20 | # |
| 23 | # Code maturity level options | 21 | # General setup |
| 24 | # | 22 | # |
| 25 | CONFIG_EXPERIMENTAL=y | 23 | CONFIG_EXPERIMENTAL=y |
| 26 | CONFIG_BROKEN_ON_SMP=y | 24 | CONFIG_BROKEN_ON_SMP=y |
| 27 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 25 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_LOCALVERSION="" | 26 | CONFIG_LOCALVERSION="" |
| 33 | CONFIG_LOCALVERSION_AUTO=y | 27 | CONFIG_LOCALVERSION_AUTO=y |
| 34 | CONFIG_SYSVIPC=y | 28 | CONFIG_SYSVIPC=y |
| 35 | # CONFIG_IPC_NS is not set | ||
| 36 | CONFIG_SYSVIPC_SYSCTL=y | 29 | CONFIG_SYSVIPC_SYSCTL=y |
| 37 | # CONFIG_POSIX_MQUEUE is not set | 30 | # CONFIG_POSIX_MQUEUE is not set |
| 38 | # CONFIG_BSD_PROCESS_ACCT is not set | 31 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 39 | # CONFIG_TASKSTATS is not set | 32 | # CONFIG_TASKSTATS is not set |
| 40 | # CONFIG_UTS_NS is not set | ||
| 41 | # CONFIG_AUDIT is not set | 33 | # CONFIG_AUDIT is not set |
| 42 | # CONFIG_IKCONFIG is not set | 34 | # CONFIG_IKCONFIG is not set |
| 43 | CONFIG_LOG_BUF_SHIFT=14 | 35 | CONFIG_LOG_BUF_SHIFT=14 |
| 44 | CONFIG_SYSFS_DEPRECATED=y | 36 | # CONFIG_CGROUPS is not set |
| 37 | # CONFIG_GROUP_SCHED is not set | ||
| 38 | # CONFIG_SYSFS_DEPRECATED is not set | ||
| 39 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 45 | # CONFIG_RELAY is not set | 40 | # CONFIG_RELAY is not set |
| 41 | # CONFIG_NAMESPACES is not set | ||
| 46 | # CONFIG_BLK_DEV_INITRD is not set | 42 | # CONFIG_BLK_DEV_INITRD is not set |
| 47 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 43 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 48 | CONFIG_SYSCTL=y | 44 | CONFIG_SYSCTL=y |
| @@ -54,40 +50,41 @@ CONFIG_KALLSYMS=y | |||
| 54 | CONFIG_HOTPLUG=y | 50 | CONFIG_HOTPLUG=y |
| 55 | CONFIG_PRINTK=y | 51 | CONFIG_PRINTK=y |
| 56 | CONFIG_BUG=y | 52 | CONFIG_BUG=y |
| 57 | CONFIG_ELF_CORE=y | 53 | # CONFIG_ELF_CORE is not set |
| 54 | CONFIG_COMPAT_BRK=y | ||
| 58 | CONFIG_BASE_FULL=y | 55 | CONFIG_BASE_FULL=y |
| 59 | CONFIG_FUTEX=y | 56 | CONFIG_FUTEX=y |
| 60 | CONFIG_ANON_INODES=y | 57 | CONFIG_ANON_INODES=y |
| 61 | CONFIG_EPOLL=y | 58 | CONFIG_EPOLL=y |
| 62 | CONFIG_SIGNALFD=y | 59 | CONFIG_SIGNALFD=y |
| 60 | CONFIG_TIMERFD=y | ||
| 63 | CONFIG_EVENTFD=y | 61 | CONFIG_EVENTFD=y |
| 62 | CONFIG_AIO=y | ||
| 64 | CONFIG_VM_EVENT_COUNTERS=y | 63 | CONFIG_VM_EVENT_COUNTERS=y |
| 65 | CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=9 | ||
| 66 | # CONFIG_NP2 is not set | ||
| 67 | CONFIG_SLAB=y | 64 | CONFIG_SLAB=y |
| 68 | # CONFIG_SLUB is not set | 65 | # CONFIG_SLUB is not set |
| 69 | # CONFIG_SLOB is not set | 66 | # CONFIG_SLOB is not set |
| 67 | # CONFIG_PROFILING is not set | ||
| 68 | # CONFIG_MARKERS is not set | ||
| 69 | CONFIG_HAVE_OPROFILE=y | ||
| 70 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 71 | CONFIG_SLABINFO=y | ||
| 70 | CONFIG_RT_MUTEXES=y | 72 | CONFIG_RT_MUTEXES=y |
| 71 | CONFIG_TINY_SHMEM=y | 73 | CONFIG_TINY_SHMEM=y |
| 72 | CONFIG_BASE_SMALL=0 | 74 | CONFIG_BASE_SMALL=0 |
| 73 | |||
| 74 | # | ||
| 75 | # Loadable module support | ||
| 76 | # | ||
| 77 | CONFIG_MODULES=y | 75 | CONFIG_MODULES=y |
| 76 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 78 | CONFIG_MODULE_UNLOAD=y | 77 | CONFIG_MODULE_UNLOAD=y |
| 79 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 78 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 80 | # CONFIG_MODVERSIONS is not set | 79 | # CONFIG_MODVERSIONS is not set |
| 81 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 80 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 82 | CONFIG_KMOD=y | 81 | CONFIG_KMOD=y |
| 83 | |||
| 84 | # | ||
| 85 | # Block layer | ||
| 86 | # | ||
| 87 | CONFIG_BLOCK=y | 82 | CONFIG_BLOCK=y |
| 88 | # CONFIG_LBD is not set | 83 | # CONFIG_LBD is not set |
| 89 | # CONFIG_BLK_DEV_IO_TRACE is not set | 84 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 90 | # CONFIG_LSF is not set | 85 | # CONFIG_LSF is not set |
| 86 | # CONFIG_BLK_DEV_BSG is not set | ||
| 87 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 91 | 88 | ||
| 92 | # | 89 | # |
| 93 | # IO Schedulers | 90 | # IO Schedulers |
| @@ -101,9 +98,11 @@ CONFIG_DEFAULT_AS=y | |||
| 101 | # CONFIG_DEFAULT_CFQ is not set | 98 | # CONFIG_DEFAULT_CFQ is not set |
| 102 | # CONFIG_DEFAULT_NOOP is not set | 99 | # CONFIG_DEFAULT_NOOP is not set |
| 103 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 100 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 101 | CONFIG_CLASSIC_RCU=y | ||
| 104 | # CONFIG_PREEMPT_NONE is not set | 102 | # CONFIG_PREEMPT_NONE is not set |
| 105 | CONFIG_PREEMPT_VOLUNTARY=y | 103 | CONFIG_PREEMPT_VOLUNTARY=y |
| 106 | # CONFIG_PREEMPT is not set | 104 | # CONFIG_PREEMPT is not set |
| 105 | # CONFIG_FREEZER is not set | ||
| 107 | 106 | ||
| 108 | # | 107 | # |
| 109 | # Blackfin Processor Options | 108 | # Blackfin Processor Options |
| @@ -112,8 +111,15 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 112 | # | 111 | # |
| 113 | # Processor and Board Settings | 112 | # Processor and Board Settings |
| 114 | # | 113 | # |
| 114 | # CONFIG_BF512 is not set | ||
| 115 | # CONFIG_BF514 is not set | ||
| 116 | # CONFIG_BF516 is not set | ||
| 117 | # CONFIG_BF518 is not set | ||
| 115 | # CONFIG_BF522 is not set | 118 | # CONFIG_BF522 is not set |
| 119 | # CONFIG_BF523 is not set | ||
| 120 | # CONFIG_BF524 is not set | ||
| 116 | # CONFIG_BF525 is not set | 121 | # CONFIG_BF525 is not set |
| 122 | # CONFIG_BF526 is not set | ||
| 117 | # CONFIG_BF527 is not set | 123 | # CONFIG_BF527 is not set |
| 118 | # CONFIG_BF531 is not set | 124 | # CONFIG_BF531 is not set |
| 119 | # CONFIG_BF532 is not set | 125 | # CONFIG_BF532 is not set |
| @@ -121,22 +127,26 @@ CONFIG_PREEMPT_VOLUNTARY=y | |||
| 121 | # CONFIG_BF534 is not set | 127 | # CONFIG_BF534 is not set |
| 122 | # CONFIG_BF536 is not set | 128 | # CONFIG_BF536 is not set |
| 123 | CONFIG_BF537=y | 129 | CONFIG_BF537=y |
| 130 | # CONFIG_BF538 is not set | ||
| 131 | # CONFIG_BF539 is not set | ||
| 124 | # CONFIG_BF542 is not set | 132 | # CONFIG_BF542 is not set |
| 125 | # CONFIG_BF544 is not set | 133 | # CONFIG_BF544 is not set |
| 126 | # CONFIG_BF547 is not set | 134 | # CONFIG_BF547 is not set |
| 127 | # CONFIG_BF548 is not set | 135 | # CONFIG_BF548 is not set |
| 128 | # CONFIG_BF549 is not set | 136 | # CONFIG_BF549 is not set |
| 129 | # CONFIG_BF561 is not set | 137 | # CONFIG_BF561 is not set |
| 138 | CONFIG_BF_REV_MIN=2 | ||
| 139 | CONFIG_BF_REV_MAX=3 | ||
| 130 | # CONFIG_BF_REV_0_0 is not set | 140 | # CONFIG_BF_REV_0_0 is not set |
| 131 | # CONFIG_BF_REV_0_1 is not set | 141 | # CONFIG_BF_REV_0_1 is not set |
| 132 | CONFIG_BF_REV_0_2=y | 142 | CONFIG_BF_REV_0_2=y |
| 133 | # CONFIG_BF_REV_0_3 is not set | 143 | # CONFIG_BF_REV_0_3 is not set |
| 134 | # CONFIG_BF_REV_0_4 is not set | 144 | # CONFIG_BF_REV_0_4 is not set |
| 135 | # CONFIG_BF_REV_0_5 is not set | 145 | # CONFIG_BF_REV_0_5 is not set |
| 146 | # CONFIG_BF_REV_0_6 is not set | ||
| 136 | # CONFIG_BF_REV_ANY is not set | 147 | # CONFIG_BF_REV_ANY is not set |
| 137 | # CONFIG_BF_REV_NONE is not set | 148 | # CONFIG_BF_REV_NONE is not set |
| 138 | CONFIG_BF53x=y | 149 | CONFIG_BF53x=y |
| 139 | CONFIG_BFIN_SINGLE_CORE=y | ||
| 140 | CONFIG_MEM_MT48LC32M8A2_75=y | 150 | CONFIG_MEM_MT48LC32M8A2_75=y |
| 141 | CONFIG_IRQ_PLL_WAKEUP=7 | 151 | CONFIG_IRQ_PLL_WAKEUP=7 |
| 142 | CONFIG_IRQ_RTC=8 | 152 | CONFIG_IRQ_RTC=8 |
| @@ -146,28 +156,30 @@ CONFIG_IRQ_SPORT0_TX=9 | |||
| 146 | CONFIG_IRQ_SPORT1_RX=9 | 156 | CONFIG_IRQ_SPORT1_RX=9 |
| 147 | CONFIG_IRQ_SPORT1_TX=9 | 157 | CONFIG_IRQ_SPORT1_TX=9 |
| 148 | CONFIG_IRQ_TWI=10 | 158 | CONFIG_IRQ_TWI=10 |
| 149 | CONFIG_IRQ_SPI=10 | ||
| 150 | CONFIG_IRQ_UART0_RX=10 | 159 | CONFIG_IRQ_UART0_RX=10 |
| 151 | CONFIG_IRQ_UART0_TX=10 | 160 | CONFIG_IRQ_UART0_TX=10 |
| 152 | CONFIG_IRQ_UART1_RX=10 | 161 | CONFIG_IRQ_UART1_RX=10 |
| 153 | CONFIG_IRQ_UART1_TX=10 | 162 | CONFIG_IRQ_UART1_TX=10 |
| 154 | CONFIG_IRQ_MAC_RX=11 | 163 | CONFIG_IRQ_MAC_RX=11 |
| 155 | CONFIG_IRQ_MAC_TX=11 | 164 | CONFIG_IRQ_MAC_TX=11 |
| 156 | CONFIG_IRQ_TMR0=12 | 165 | CONFIG_IRQ_TIMER0=12 |
| 157 | CONFIG_IRQ_TMR1=12 | 166 | CONFIG_IRQ_TIMER1=12 |
| 158 | CONFIG_IRQ_TMR2=12 | 167 | CONFIG_IRQ_TIMER2=12 |
| 159 | CONFIG_IRQ_TMR3=12 | 168 | CONFIG_IRQ_TIMER3=12 |
| 160 | CONFIG_IRQ_TMR4=12 | 169 | CONFIG_IRQ_TIMER4=12 |
| 161 | CONFIG_IRQ_TMR5=12 | 170 | CONFIG_IRQ_TIMER5=12 |
| 162 | CONFIG_IRQ_TMR6=12 | 171 | CONFIG_IRQ_TIMER6=12 |
| 163 | CONFIG_IRQ_TMR7=12 | 172 | CONFIG_IRQ_TIMER7=12 |
| 164 | CONFIG_IRQ_PORTG_INTB=12 | 173 | CONFIG_IRQ_PORTG_INTB=12 |
| 165 | CONFIG_IRQ_MEM_DMA0=13 | 174 | CONFIG_IRQ_MEM_DMA0=13 |
| 166 | CONFIG_IRQ_MEM_DMA1=13 | 175 | CONFIG_IRQ_MEM_DMA1=13 |
| 167 | CONFIG_IRQ_WATCH=13 | 176 | CONFIG_IRQ_WATCH=13 |
| 177 | CONFIG_IRQ_SPI=10 | ||
| 168 | # CONFIG_BFIN537_STAMP is not set | 178 | # CONFIG_BFIN537_STAMP is not set |
| 169 | # CONFIG_BFIN537_BLUETECHNIX_CM is not set | 179 | # CONFIG_BFIN537_BLUETECHNIX_CM is not set |
| 180 | # CONFIG_BFIN537_BLUETECHNIX_TCM is not set | ||
| 170 | CONFIG_PNAV10=y | 181 | CONFIG_PNAV10=y |
| 182 | # CONFIG_CAMSIG_MINOTAUR is not set | ||
| 171 | # CONFIG_GENERIC_BF537_BOARD is not set | 183 | # CONFIG_GENERIC_BF537_BOARD is not set |
| 172 | 184 | ||
| 173 | # | 185 | # |
| @@ -191,6 +203,7 @@ CONFIG_IRQ_PROG_INTA=12 | |||
| 191 | # Board customizations | 203 | # Board customizations |
| 192 | # | 204 | # |
| 193 | # CONFIG_CMDLINE_BOOL is not set | 205 | # CONFIG_CMDLINE_BOOL is not set |
| 206 | CONFIG_BOOT_LOAD=0x1000 | ||
| 194 | 207 | ||
| 195 | # | 208 | # |
| 196 | # Clock/PLL Setup | 209 | # Clock/PLL Setup |
| @@ -199,7 +212,7 @@ CONFIG_CLKIN_HZ=24576000 | |||
| 199 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 212 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 200 | CONFIG_MAX_VCO_HZ=600000000 | 213 | CONFIG_MAX_VCO_HZ=600000000 |
| 201 | CONFIG_MIN_VCO_HZ=50000000 | 214 | CONFIG_MIN_VCO_HZ=50000000 |
| 202 | CONFIG_MAX_SCLK_HZ=133000000 | 215 | CONFIG_MAX_SCLK_HZ=133333333 |
| 203 | CONFIG_MIN_SCLK_HZ=27000000 | 216 | CONFIG_MIN_SCLK_HZ=27000000 |
| 204 | 217 | ||
| 205 | # | 218 | # |
| @@ -210,13 +223,17 @@ CONFIG_HZ_250=y | |||
| 210 | # CONFIG_HZ_300 is not set | 223 | # CONFIG_HZ_300 is not set |
| 211 | # CONFIG_HZ_1000 is not set | 224 | # CONFIG_HZ_1000 is not set |
| 212 | CONFIG_HZ=250 | 225 | CONFIG_HZ=250 |
| 226 | # CONFIG_SCHED_HRTICK is not set | ||
| 227 | CONFIG_GENERIC_TIME=y | ||
| 228 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 229 | # CONFIG_CYCLES_CLOCKSOURCE is not set | ||
| 230 | # CONFIG_NO_HZ is not set | ||
| 231 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 232 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 213 | 233 | ||
| 214 | # | 234 | # |
| 215 | # Memory Setup | 235 | # Misc |
| 216 | # | 236 | # |
| 217 | CONFIG_MAX_MEM_SIZE=64 | ||
| 218 | CONFIG_MEM_ADD_WIDTH=10 | ||
| 219 | CONFIG_BOOT_LOAD=0x1000 | ||
| 220 | CONFIG_BFIN_SCRATCH_REG_RETN=y | 237 | CONFIG_BFIN_SCRATCH_REG_RETN=y |
| 221 | # CONFIG_BFIN_SCRATCH_REG_RETE is not set | 238 | # CONFIG_BFIN_SCRATCH_REG_RETE is not set |
| 222 | # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set | 239 | # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set |
| @@ -243,6 +260,12 @@ CONFIG_IP_CHECKSUM_L1=y | |||
| 243 | CONFIG_CACHELINE_ALIGNED_L1=y | 260 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 244 | CONFIG_SYSCALL_TAB_L1=y | 261 | CONFIG_SYSCALL_TAB_L1=y |
| 245 | CONFIG_CPLB_SWITCH_TAB_L1=y | 262 | CONFIG_CPLB_SWITCH_TAB_L1=y |
| 263 | CONFIG_APP_STACK_L1=y | ||
| 264 | |||
| 265 | # | ||
| 266 | # Speed Optimizations | ||
| 267 | # | ||
| 268 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 246 | CONFIG_RAMKERNEL=y | 269 | CONFIG_RAMKERNEL=y |
| 247 | # CONFIG_ROMKERNEL is not set | 270 | # CONFIG_ROMKERNEL is not set |
| 248 | CONFIG_SELECT_MEMORY_MODEL=y | 271 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -251,13 +274,14 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 251 | # CONFIG_SPARSEMEM_MANUAL is not set | 274 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 252 | CONFIG_FLATMEM=y | 275 | CONFIG_FLATMEM=y |
| 253 | CONFIG_FLAT_NODE_MEM_MAP=y | 276 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 254 | # CONFIG_SPARSEMEM_STATIC is not set | 277 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 255 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 278 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 256 | # CONFIG_RESOURCES_64BIT is not set | 279 | # CONFIG_RESOURCES_64BIT is not set |
| 280 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 257 | CONFIG_ZONE_DMA_FLAG=1 | 281 | CONFIG_ZONE_DMA_FLAG=1 |
| 258 | CONFIG_LARGE_ALLOCS=y | 282 | CONFIG_VIRT_TO_BUS=y |
| 259 | # CONFIG_BFIN_GPTIMERS is not set | 283 | CONFIG_BFIN_GPTIMERS=y |
| 260 | CONFIG_BFIN_DMA_5XX=y | 284 | # CONFIG_DMA_UNCACHED_4M is not set |
| 261 | # CONFIG_DMA_UNCACHED_2M is not set | 285 | # CONFIG_DMA_UNCACHED_2M is not set |
| 262 | CONFIG_DMA_UNCACHED_1M=y | 286 | CONFIG_DMA_UNCACHED_1M=y |
| 263 | # CONFIG_DMA_UNCACHED_NONE is not set | 287 | # CONFIG_DMA_UNCACHED_NONE is not set |
| @@ -271,7 +295,7 @@ CONFIG_BFIN_DCACHE=y | |||
| 271 | # CONFIG_BFIN_ICACHE_LOCK is not set | 295 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 272 | CONFIG_BFIN_WB=y | 296 | CONFIG_BFIN_WB=y |
| 273 | # CONFIG_BFIN_WT is not set | 297 | # CONFIG_BFIN_WT is not set |
| 274 | CONFIG_L1_MAX_PIECE=16 | 298 | # CONFIG_MPU is not set |
| 275 | 299 | ||
| 276 | # | 300 | # |
| 277 | # Asynchonous Memory Configuration | 301 | # Asynchonous Memory Configuration |
| @@ -299,12 +323,7 @@ CONFIG_BANK_3=0x99B2 | |||
| 299 | # | 323 | # |
| 300 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 324 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 301 | # | 325 | # |
| 302 | # CONFIG_PCI is not set | ||
| 303 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 326 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 304 | |||
| 305 | # | ||
| 306 | # PCCARD (PCMCIA/CardBus) support | ||
| 307 | # | ||
| 308 | # CONFIG_PCCARD is not set | 327 | # CONFIG_PCCARD is not set |
| 309 | 328 | ||
| 310 | # | 329 | # |
| @@ -314,21 +333,20 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 314 | CONFIG_BINFMT_FLAT=y | 333 | CONFIG_BINFMT_FLAT=y |
| 315 | CONFIG_BINFMT_ZFLAT=y | 334 | CONFIG_BINFMT_ZFLAT=y |
| 316 | # CONFIG_BINFMT_SHARED_FLAT is not set | 335 | # CONFIG_BINFMT_SHARED_FLAT is not set |
| 336 | # CONFIG_HAVE_AOUT is not set | ||
| 317 | # CONFIG_BINFMT_MISC is not set | 337 | # CONFIG_BINFMT_MISC is not set |
| 318 | 338 | ||
| 319 | # | 339 | # |
| 320 | # Power management options | 340 | # Power management options |
| 321 | # | 341 | # |
| 322 | # CONFIG_PM is not set | 342 | # CONFIG_PM is not set |
| 343 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 344 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | ||
| 323 | 345 | ||
| 324 | # | 346 | # |
| 325 | # CPU Frequency scaling | 347 | # CPU Frequency scaling |
| 326 | # | 348 | # |
| 327 | # CONFIG_CPU_FREQ is not set | 349 | # CONFIG_CPU_FREQ is not set |
| 328 | |||
| 329 | # | ||
| 330 | # Networking | ||
| 331 | # | ||
| 332 | CONFIG_NET=y | 350 | CONFIG_NET=y |
| 333 | 351 | ||
| 334 | # | 352 | # |
| @@ -341,6 +359,7 @@ CONFIG_XFRM=y | |||
| 341 | # CONFIG_XFRM_USER is not set | 359 | # CONFIG_XFRM_USER is not set |
| 342 | # CONFIG_XFRM_SUB_POLICY is not set | 360 | # CONFIG_XFRM_SUB_POLICY is not set |
| 343 | # CONFIG_XFRM_MIGRATE is not set | 361 | # CONFIG_XFRM_MIGRATE is not set |
| 362 | # CONFIG_XFRM_STATISTICS is not set | ||
| 344 | # CONFIG_NET_KEY is not set | 363 | # CONFIG_NET_KEY is not set |
| 345 | CONFIG_INET=y | 364 | CONFIG_INET=y |
| 346 | # CONFIG_IP_MULTICAST is not set | 365 | # CONFIG_IP_MULTICAST is not set |
| @@ -362,6 +381,7 @@ CONFIG_SYN_COOKIES=y | |||
| 362 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 381 | CONFIG_INET_XFRM_MODE_TRANSPORT=y |
| 363 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 382 | CONFIG_INET_XFRM_MODE_TUNNEL=y |
| 364 | CONFIG_INET_XFRM_MODE_BEET=y | 383 | CONFIG_INET_XFRM_MODE_BEET=y |
| 384 | # CONFIG_INET_LRO is not set | ||
| 365 | CONFIG_INET_DIAG=y | 385 | CONFIG_INET_DIAG=y |
| 366 | CONFIG_INET_TCP_DIAG=y | 386 | CONFIG_INET_TCP_DIAG=y |
| 367 | # CONFIG_TCP_CONG_ADVANCED is not set | 387 | # CONFIG_TCP_CONG_ADVANCED is not set |
| @@ -369,8 +389,6 @@ CONFIG_TCP_CONG_CUBIC=y | |||
| 369 | CONFIG_DEFAULT_TCP_CONG="cubic" | 389 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 370 | # CONFIG_TCP_MD5SIG is not set | 390 | # CONFIG_TCP_MD5SIG is not set |
| 371 | # CONFIG_IPV6 is not set | 391 | # CONFIG_IPV6 is not set |
| 372 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 373 | # CONFIG_INET6_TUNNEL is not set | ||
| 374 | # CONFIG_NETLABEL is not set | 392 | # CONFIG_NETLABEL is not set |
| 375 | # CONFIG_NETWORK_SECMARK is not set | 393 | # CONFIG_NETWORK_SECMARK is not set |
| 376 | # CONFIG_NETFILTER is not set | 394 | # CONFIG_NETFILTER is not set |
| @@ -379,6 +397,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 379 | # CONFIG_TIPC is not set | 397 | # CONFIG_TIPC is not set |
| 380 | # CONFIG_ATM is not set | 398 | # CONFIG_ATM is not set |
| 381 | # CONFIG_BRIDGE is not set | 399 | # CONFIG_BRIDGE is not set |
| 400 | # CONFIG_NET_DSA is not set | ||
| 382 | # CONFIG_VLAN_8021Q is not set | 401 | # CONFIG_VLAN_8021Q is not set |
| 383 | # CONFIG_DECNET is not set | 402 | # CONFIG_DECNET is not set |
| 384 | # CONFIG_LLC2 is not set | 403 | # CONFIG_LLC2 is not set |
| @@ -388,10 +407,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 388 | # CONFIG_LAPB is not set | 407 | # CONFIG_LAPB is not set |
| 389 | # CONFIG_ECONET is not set | 408 | # CONFIG_ECONET is not set |
| 390 | # CONFIG_WAN_ROUTER is not set | 409 | # CONFIG_WAN_ROUTER is not set |
| 391 | |||
| 392 | # | ||
| 393 | # QoS and/or fair queueing | ||
| 394 | # | ||
| 395 | # CONFIG_NET_SCHED is not set | 410 | # CONFIG_NET_SCHED is not set |
| 396 | 411 | ||
| 397 | # | 412 | # |
| @@ -399,18 +414,19 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 399 | # | 414 | # |
| 400 | # CONFIG_NET_PKTGEN is not set | 415 | # CONFIG_NET_PKTGEN is not set |
| 401 | # CONFIG_HAMRADIO is not set | 416 | # CONFIG_HAMRADIO is not set |
| 417 | # CONFIG_CAN is not set | ||
| 402 | # CONFIG_IRDA is not set | 418 | # CONFIG_IRDA is not set |
| 403 | # CONFIG_BT is not set | 419 | # CONFIG_BT is not set |
| 404 | # CONFIG_AF_RXRPC is not set | 420 | # CONFIG_AF_RXRPC is not set |
| 405 | 421 | # CONFIG_PHONET is not set | |
| 406 | # | 422 | CONFIG_WIRELESS=y |
| 407 | # Wireless | ||
| 408 | # | ||
| 409 | # CONFIG_CFG80211 is not set | 423 | # CONFIG_CFG80211 is not set |
| 424 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 410 | # CONFIG_WIRELESS_EXT is not set | 425 | # CONFIG_WIRELESS_EXT is not set |
| 411 | # CONFIG_MAC80211 is not set | 426 | # CONFIG_MAC80211 is not set |
| 412 | # CONFIG_IEEE80211 is not set | 427 | # CONFIG_IEEE80211 is not set |
| 413 | # CONFIG_RFKILL is not set | 428 | # CONFIG_RFKILL is not set |
| 429 | # CONFIG_NET_9P is not set | ||
| 414 | 430 | ||
| 415 | # | 431 | # |
| 416 | # Device Drivers | 432 | # Device Drivers |
| @@ -419,14 +435,11 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 419 | # | 435 | # |
| 420 | # Generic Driver Options | 436 | # Generic Driver Options |
| 421 | # | 437 | # |
| 438 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 422 | CONFIG_STANDALONE=y | 439 | CONFIG_STANDALONE=y |
| 423 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 440 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 424 | # CONFIG_FW_LOADER is not set | 441 | # CONFIG_FW_LOADER is not set |
| 425 | # CONFIG_SYS_HYPERVISOR is not set | 442 | # CONFIG_SYS_HYPERVISOR is not set |
| 426 | |||
| 427 | # | ||
| 428 | # Connector - unified userspace <-> kernelspace linker | ||
| 429 | # | ||
| 430 | # CONFIG_CONNECTOR is not set | 443 | # CONFIG_CONNECTOR is not set |
| 431 | CONFIG_MTD=y | 444 | CONFIG_MTD=y |
| 432 | # CONFIG_MTD_DEBUG is not set | 445 | # CONFIG_MTD_DEBUG is not set |
| @@ -434,6 +447,7 @@ CONFIG_MTD=y | |||
| 434 | CONFIG_MTD_PARTITIONS=y | 447 | CONFIG_MTD_PARTITIONS=y |
| 435 | # CONFIG_MTD_REDBOOT_PARTS is not set | 448 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 436 | # CONFIG_MTD_CMDLINE_PARTS is not set | 449 | # CONFIG_MTD_CMDLINE_PARTS is not set |
| 450 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 437 | 451 | ||
| 438 | # | 452 | # |
| 439 | # User Modules And Translation Layers | 453 | # User Modules And Translation Layers |
| @@ -446,6 +460,7 @@ CONFIG_MTD_BLOCK=y | |||
| 446 | # CONFIG_INFTL is not set | 460 | # CONFIG_INFTL is not set |
| 447 | # CONFIG_RFD_FTL is not set | 461 | # CONFIG_RFD_FTL is not set |
| 448 | # CONFIG_SSFDC is not set | 462 | # CONFIG_SSFDC is not set |
| 463 | # CONFIG_MTD_OOPS is not set | ||
| 449 | 464 | ||
| 450 | # | 465 | # |
| 451 | # RAM/ROM/Flash chip drivers | 466 | # RAM/ROM/Flash chip drivers |
| @@ -470,7 +485,7 @@ CONFIG_MTD_RAM=y | |||
| 470 | # Mapping drivers for chip access | 485 | # Mapping drivers for chip access |
| 471 | # | 486 | # |
| 472 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 487 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 473 | # CONFIG_MTD_BF5xx is not set | 488 | # CONFIG_MTD_GPIO_ADDR is not set |
| 474 | CONFIG_MTD_UCLINUX=y | 489 | CONFIG_MTD_UCLINUX=y |
| 475 | # CONFIG_MTD_PLATRAM is not set | 490 | # CONFIG_MTD_PLATRAM is not set |
| 476 | 491 | ||
| @@ -509,33 +524,22 @@ CONFIG_MTD_NAND_IDS=y | |||
| 509 | # UBI - Unsorted block images | 524 | # UBI - Unsorted block images |
| 510 | # | 525 | # |
| 511 | # CONFIG_MTD_UBI is not set | 526 | # CONFIG_MTD_UBI is not set |
| 512 | |||
| 513 | # | ||
| 514 | # Parallel port support | ||
| 515 | # | ||
| 516 | # CONFIG_PARPORT is not set | 527 | # CONFIG_PARPORT is not set |
| 517 | 528 | CONFIG_BLK_DEV=y | |
| 518 | # | ||
| 519 | # Plug and Play support | ||
| 520 | # | ||
| 521 | # CONFIG_PNPACPI is not set | ||
| 522 | |||
| 523 | # | ||
| 524 | # Block devices | ||
| 525 | # | ||
| 526 | # CONFIG_BLK_DEV_COW_COMMON is not set | 529 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 527 | # CONFIG_BLK_DEV_LOOP is not set | 530 | # CONFIG_BLK_DEV_LOOP is not set |
| 528 | # CONFIG_BLK_DEV_NBD is not set | 531 | # CONFIG_BLK_DEV_NBD is not set |
| 529 | CONFIG_BLK_DEV_RAM=y | 532 | CONFIG_BLK_DEV_RAM=y |
| 530 | CONFIG_BLK_DEV_RAM_COUNT=16 | 533 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 531 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 534 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 532 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 535 | # CONFIG_BLK_DEV_XIP is not set |
| 533 | # CONFIG_CDROM_PKTCDVD is not set | 536 | # CONFIG_CDROM_PKTCDVD is not set |
| 534 | # CONFIG_ATA_OVER_ETH is not set | 537 | # CONFIG_ATA_OVER_ETH is not set |
| 535 | 538 | # CONFIG_BLK_DEV_HD is not set | |
| 536 | # | 539 | CONFIG_MISC_DEVICES=y |
| 537 | # Misc devices | 540 | # CONFIG_EEPROM_93CX6 is not set |
| 538 | # | 541 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 542 | CONFIG_HAVE_IDE=y | ||
| 539 | # CONFIG_IDE is not set | 543 | # CONFIG_IDE is not set |
| 540 | 544 | ||
| 541 | # | 545 | # |
| @@ -543,22 +547,17 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | |||
| 543 | # | 547 | # |
| 544 | # CONFIG_RAID_ATTRS is not set | 548 | # CONFIG_RAID_ATTRS is not set |
| 545 | # CONFIG_SCSI is not set | 549 | # CONFIG_SCSI is not set |
| 550 | # CONFIG_SCSI_DMA is not set | ||
| 546 | # CONFIG_SCSI_NETLINK is not set | 551 | # CONFIG_SCSI_NETLINK is not set |
| 547 | # CONFIG_ATA is not set | 552 | # CONFIG_ATA is not set |
| 548 | |||
| 549 | # | ||
| 550 | # Multi-device support (RAID and LVM) | ||
| 551 | # | ||
| 552 | # CONFIG_MD is not set | 553 | # CONFIG_MD is not set |
| 553 | |||
| 554 | # | ||
| 555 | # Network device support | ||
| 556 | # | ||
| 557 | CONFIG_NETDEVICES=y | 554 | CONFIG_NETDEVICES=y |
| 558 | # CONFIG_DUMMY is not set | 555 | # CONFIG_DUMMY is not set |
| 559 | # CONFIG_BONDING is not set | 556 | # CONFIG_BONDING is not set |
| 557 | # CONFIG_MACVLAN is not set | ||
| 560 | # CONFIG_EQUALIZER is not set | 558 | # CONFIG_EQUALIZER is not set |
| 561 | # CONFIG_TUN is not set | 559 | # CONFIG_TUN is not set |
| 560 | # CONFIG_VETH is not set | ||
| 562 | CONFIG_PHYLIB=y | 561 | CONFIG_PHYLIB=y |
| 563 | 562 | ||
| 564 | # | 563 | # |
| @@ -572,46 +571,45 @@ CONFIG_PHYLIB=y | |||
| 572 | # CONFIG_VITESSE_PHY is not set | 571 | # CONFIG_VITESSE_PHY is not set |
| 573 | # CONFIG_SMSC_PHY is not set | 572 | # CONFIG_SMSC_PHY is not set |
| 574 | # CONFIG_BROADCOM_PHY is not set | 573 | # CONFIG_BROADCOM_PHY is not set |
| 574 | # CONFIG_ICPLUS_PHY is not set | ||
| 575 | # CONFIG_REALTEK_PHY is not set | ||
| 575 | # CONFIG_FIXED_PHY is not set | 576 | # CONFIG_FIXED_PHY is not set |
| 576 | 577 | # CONFIG_MDIO_BITBANG is not set | |
| 577 | # | ||
| 578 | # Ethernet (10 or 100Mbit) | ||
| 579 | # | ||
| 580 | CONFIG_NET_ETHERNET=y | 578 | CONFIG_NET_ETHERNET=y |
| 581 | CONFIG_MII=y | 579 | CONFIG_MII=y |
| 582 | # CONFIG_SMC91X is not set | ||
| 583 | CONFIG_BFIN_MAC=y | 580 | CONFIG_BFIN_MAC=y |
| 584 | # CONFIG_BFIN_MAC_USE_L1 is not set | 581 | # CONFIG_BFIN_MAC_USE_L1 is not set |
| 585 | CONFIG_BFIN_TX_DESC_NUM=100 | 582 | CONFIG_BFIN_TX_DESC_NUM=100 |
| 586 | CONFIG_BFIN_RX_DESC_NUM=100 | 583 | CONFIG_BFIN_RX_DESC_NUM=100 |
| 587 | CONFIG_BFIN_MAC_RMII=y | 584 | CONFIG_BFIN_MAC_RMII=y |
| 585 | # CONFIG_SMC91X is not set | ||
| 588 | # CONFIG_SMSC911X is not set | 586 | # CONFIG_SMSC911X is not set |
| 589 | # CONFIG_DM9000 is not set | 587 | # CONFIG_DM9000 is not set |
| 588 | # CONFIG_ENC28J60 is not set | ||
| 589 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 590 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 591 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 592 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 593 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 594 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 595 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 590 | CONFIG_NETDEV_1000=y | 596 | CONFIG_NETDEV_1000=y |
| 591 | CONFIG_NETDEV_10000=y | ||
| 592 | # CONFIG_AX88180 is not set | 597 | # CONFIG_AX88180 is not set |
| 598 | CONFIG_NETDEV_10000=y | ||
| 593 | 599 | ||
| 594 | # | 600 | # |
| 595 | # Wireless LAN | 601 | # Wireless LAN |
| 596 | # | 602 | # |
| 597 | # CONFIG_WLAN_PRE80211 is not set | 603 | # CONFIG_WLAN_PRE80211 is not set |
| 598 | # CONFIG_WLAN_80211 is not set | 604 | # CONFIG_WLAN_80211 is not set |
| 605 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 599 | # CONFIG_WAN is not set | 606 | # CONFIG_WAN is not set |
| 600 | # CONFIG_PPP is not set | 607 | # CONFIG_PPP is not set |
| 601 | # CONFIG_SLIP is not set | 608 | # CONFIG_SLIP is not set |
| 602 | # CONFIG_SHAPER is not set | ||
| 603 | # CONFIG_NETCONSOLE is not set | 609 | # CONFIG_NETCONSOLE is not set |
| 604 | # CONFIG_NETPOLL is not set | 610 | # CONFIG_NETPOLL is not set |
| 605 | # CONFIG_NET_POLL_CONTROLLER is not set | 611 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 606 | |||
| 607 | # | ||
| 608 | # ISDN subsystem | ||
| 609 | # | ||
| 610 | # CONFIG_ISDN is not set | 612 | # CONFIG_ISDN is not set |
| 611 | |||
| 612 | # | ||
| 613 | # Telephony Support | ||
| 614 | # | ||
| 615 | # CONFIG_PHONE is not set | 613 | # CONFIG_PHONE is not set |
| 616 | 614 | ||
| 617 | # | 615 | # |
| @@ -626,9 +624,6 @@ CONFIG_INPUT=y | |||
| 626 | # | 624 | # |
| 627 | # CONFIG_INPUT_MOUSEDEV is not set | 625 | # CONFIG_INPUT_MOUSEDEV is not set |
| 628 | # CONFIG_INPUT_JOYDEV is not set | 626 | # CONFIG_INPUT_JOYDEV is not set |
| 629 | CONFIG_INPUT_TSDEV=y | ||
| 630 | CONFIG_INPUT_TSDEV_SCREEN_X=240 | ||
| 631 | CONFIG_INPUT_TSDEV_SCREEN_Y=320 | ||
| 632 | CONFIG_INPUT_EVDEV=y | 627 | CONFIG_INPUT_EVDEV=y |
| 633 | # CONFIG_INPUT_EVBUG is not set | 628 | # CONFIG_INPUT_EVBUG is not set |
| 634 | 629 | ||
| @@ -642,24 +637,29 @@ CONFIG_INPUT_EVDEV=y | |||
| 642 | CONFIG_INPUT_TOUCHSCREEN=y | 637 | CONFIG_INPUT_TOUCHSCREEN=y |
| 643 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | 638 | # CONFIG_TOUCHSCREEN_ADS7846 is not set |
| 644 | CONFIG_TOUCHSCREEN_AD7877=y | 639 | CONFIG_TOUCHSCREEN_AD7877=y |
| 640 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 641 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
| 642 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 643 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 645 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 644 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 646 | # CONFIG_TOUCHSCREEN_ELO is not set | 645 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 647 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 646 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 647 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 648 | # CONFIG_TOUCHSCREEN_MK712 is not set | 648 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| 649 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | 649 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set |
| 650 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 650 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 651 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 651 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 652 | # CONFIG_TOUCHSCREEN_UCB1400 is not set | ||
| 653 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 652 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 653 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 654 | CONFIG_INPUT_MISC=y | 654 | CONFIG_INPUT_MISC=y |
| 655 | # CONFIG_INPUT_ATI_REMOTE is not set | 655 | # CONFIG_INPUT_ATI_REMOTE is not set |
| 656 | # CONFIG_INPUT_ATI_REMOTE2 is not set | 656 | # CONFIG_INPUT_ATI_REMOTE2 is not set |
| 657 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | 657 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set |
| 658 | # CONFIG_INPUT_POWERMATE is not set | 658 | # CONFIG_INPUT_POWERMATE is not set |
| 659 | # CONFIG_INPUT_YEALINK is not set | 659 | # CONFIG_INPUT_YEALINK is not set |
| 660 | # CONFIG_INPUT_CM109 is not set | ||
| 660 | CONFIG_INPUT_UINPUT=y | 661 | CONFIG_INPUT_UINPUT=y |
| 661 | # CONFIG_BF53X_PFBUTTONS is not set | 662 | # CONFIG_CONFIG_INPUT_PCF8574 is not set |
| 662 | # CONFIG_TWI_KEYPAD is not set | ||
| 663 | 663 | ||
| 664 | # | 664 | # |
| 665 | # Hardware I/O ports | 665 | # Hardware I/O ports |
| @@ -672,18 +672,17 @@ CONFIG_INPUT_UINPUT=y | |||
| 672 | # | 672 | # |
| 673 | # CONFIG_AD9960 is not set | 673 | # CONFIG_AD9960 is not set |
| 674 | # CONFIG_SPI_ADC_BF533 is not set | 674 | # CONFIG_SPI_ADC_BF533 is not set |
| 675 | # CONFIG_BF5xx_PFLAGS is not set | ||
| 676 | # CONFIG_BF5xx_PPIFCD is not set | 675 | # CONFIG_BF5xx_PPIFCD is not set |
| 677 | # CONFIG_BFIN_SIMPLE_TIMER is not set | 676 | # CONFIG_BFIN_SIMPLE_TIMER is not set |
| 678 | # CONFIG_BF5xx_PPI is not set | 677 | # CONFIG_BF5xx_PPI is not set |
| 679 | CONFIG_BFIN_SPORT=y | 678 | CONFIG_BFIN_SPORT=y |
| 680 | # CONFIG_BFIN_TIMER_LATENCY is not set | 679 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 681 | CONFIG_TWI_LCD=m | 680 | CONFIG_TWI_LCD=m |
| 682 | CONFIG_TWI_LCD_SLAVE_ADDR=34 | 681 | CONFIG_BFIN_DMA_INTERFACE=m |
| 683 | # CONFIG_AD5304 is not set | 682 | # CONFIG_SIMPLE_GPIO is not set |
| 684 | # CONFIG_BF5xx_TEA5764 is not set | ||
| 685 | # CONFIG_BF5xx_FBDMA is not set | ||
| 686 | # CONFIG_VT is not set | 683 | # CONFIG_VT is not set |
| 684 | CONFIG_DEVKMEM=y | ||
| 685 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 687 | # CONFIG_SERIAL_NONSTANDARD is not set | 686 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 688 | 687 | ||
| 689 | # | 688 | # |
| @@ -716,68 +715,59 @@ CONFIG_CAN4LINUX=y | |||
| 716 | # | 715 | # |
| 717 | # linux embedded drivers | 716 | # linux embedded drivers |
| 718 | # | 717 | # |
| 719 | # CONFIG_CAN_MCF5282 is not set | ||
| 720 | # CONFIG_CAN_UNCTWINCAN is not set | ||
| 721 | CONFIG_CAN_BLACKFIN=m | 718 | CONFIG_CAN_BLACKFIN=m |
| 722 | |||
| 723 | # | ||
| 724 | # IPMI | ||
| 725 | # | ||
| 726 | # CONFIG_IPMI_HANDLER is not set | 719 | # CONFIG_IPMI_HANDLER is not set |
| 727 | # CONFIG_WATCHDOG is not set | ||
| 728 | CONFIG_HW_RANDOM=y | 720 | CONFIG_HW_RANDOM=y |
| 729 | # CONFIG_GEN_RTC is not set | ||
| 730 | # CONFIG_R3964 is not set | 721 | # CONFIG_R3964 is not set |
| 731 | # CONFIG_RAW_DRIVER is not set | 722 | # CONFIG_RAW_DRIVER is not set |
| 732 | |||
| 733 | # | ||
| 734 | # TPM devices | ||
| 735 | # | ||
| 736 | # CONFIG_TCG_TPM is not set | 723 | # CONFIG_TCG_TPM is not set |
| 737 | CONFIG_I2C=y | 724 | CONFIG_I2C=y |
| 738 | CONFIG_I2C_BOARDINFO=y | 725 | CONFIG_I2C_BOARDINFO=y |
| 739 | CONFIG_I2C_CHARDEV=y | 726 | CONFIG_I2C_CHARDEV=y |
| 727 | CONFIG_I2C_HELPER_AUTO=y | ||
| 740 | 728 | ||
| 741 | # | 729 | # |
| 742 | # I2C Algorithms | 730 | # I2C Hardware Bus support |
| 743 | # | 731 | # |
| 744 | # CONFIG_I2C_ALGOBIT is not set | ||
| 745 | # CONFIG_I2C_ALGOPCF is not set | ||
| 746 | # CONFIG_I2C_ALGOPCA is not set | ||
| 747 | 732 | ||
| 748 | # | 733 | # |
| 749 | # I2C Hardware Bus support | 734 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 750 | # | 735 | # |
| 751 | # CONFIG_I2C_BLACKFIN_GPIO is not set | ||
| 752 | CONFIG_I2C_BLACKFIN_TWI=y | 736 | CONFIG_I2C_BLACKFIN_TWI=y |
| 753 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | 737 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 |
| 754 | # CONFIG_I2C_GPIO is not set | 738 | # CONFIG_I2C_GPIO is not set |
| 755 | # CONFIG_I2C_OCORES is not set | 739 | # CONFIG_I2C_OCORES is not set |
| 756 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 757 | # CONFIG_I2C_SIMTEC is not set | 740 | # CONFIG_I2C_SIMTEC is not set |
| 741 | |||
| 742 | # | ||
| 743 | # External I2C/SMBus adapter drivers | ||
| 744 | # | ||
| 745 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 746 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 747 | |||
| 748 | # | ||
| 749 | # Other I2C/SMBus bus drivers | ||
| 750 | # | ||
| 751 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 758 | # CONFIG_I2C_STUB is not set | 752 | # CONFIG_I2C_STUB is not set |
| 759 | 753 | ||
| 760 | # | 754 | # |
| 761 | # Miscellaneous I2C Chip support | 755 | # Miscellaneous I2C Chip support |
| 762 | # | 756 | # |
| 763 | # CONFIG_SENSORS_DS1337 is not set | 757 | # CONFIG_DS1682 is not set |
| 764 | # CONFIG_SENSORS_DS1374 is not set | 758 | # CONFIG_AT24 is not set |
| 765 | # CONFIG_SENSORS_AD5252 is not set | 759 | # CONFIG_SENSORS_AD5252 is not set |
| 766 | # CONFIG_SENSORS_EEPROM is not set | 760 | # CONFIG_SENSORS_EEPROM is not set |
| 767 | CONFIG_SENSORS_PCF8574=m | 761 | CONFIG_SENSORS_PCF8574=m |
| 768 | CONFIG_SENSORS_PCF8575=y | 762 | # CONFIG_PCF8575 is not set |
| 769 | # CONFIG_SENSORS_PCA9543 is not set | ||
| 770 | # CONFIG_SENSORS_PCA9539 is not set | 763 | # CONFIG_SENSORS_PCA9539 is not set |
| 771 | # CONFIG_SENSORS_PCF8591 is not set | 764 | # CONFIG_SENSORS_PCF8591 is not set |
| 772 | # CONFIG_SENSORS_MAX6875 is not set | 765 | # CONFIG_SENSORS_MAX6875 is not set |
| 766 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 773 | # CONFIG_I2C_DEBUG_CORE is not set | 767 | # CONFIG_I2C_DEBUG_CORE is not set |
| 774 | # CONFIG_I2C_DEBUG_ALGO is not set | 768 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 775 | # CONFIG_I2C_DEBUG_BUS is not set | 769 | # CONFIG_I2C_DEBUG_BUS is not set |
| 776 | # CONFIG_I2C_DEBUG_CHIP is not set | 770 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 777 | |||
| 778 | # | ||
| 779 | # SPI support | ||
| 780 | # | ||
| 781 | CONFIG_SPI=y | 771 | CONFIG_SPI=y |
| 782 | CONFIG_SPI_MASTER=y | 772 | CONFIG_SPI_MASTER=y |
| 783 | 773 | ||
| @@ -785,6 +775,7 @@ CONFIG_SPI_MASTER=y | |||
| 785 | # SPI Master Controller Drivers | 775 | # SPI Master Controller Drivers |
| 786 | # | 776 | # |
| 787 | CONFIG_SPI_BFIN=y | 777 | CONFIG_SPI_BFIN=y |
| 778 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 788 | # CONFIG_SPI_BITBANG is not set | 779 | # CONFIG_SPI_BITBANG is not set |
| 789 | 780 | ||
| 790 | # | 781 | # |
| @@ -792,27 +783,29 @@ CONFIG_SPI_BFIN=y | |||
| 792 | # | 783 | # |
| 793 | # CONFIG_SPI_AT25 is not set | 784 | # CONFIG_SPI_AT25 is not set |
| 794 | # CONFIG_SPI_SPIDEV is not set | 785 | # CONFIG_SPI_SPIDEV is not set |
| 795 | 786 | # CONFIG_SPI_TLE62X0 is not set | |
| 796 | # | 787 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 797 | # Dallas's 1-wire bus | 788 | # CONFIG_GPIOLIB is not set |
| 798 | # | ||
| 799 | # CONFIG_W1 is not set | 789 | # CONFIG_W1 is not set |
| 790 | # CONFIG_POWER_SUPPLY is not set | ||
| 800 | CONFIG_HWMON=y | 791 | CONFIG_HWMON=y |
| 801 | # CONFIG_HWMON_VID is not set | 792 | # CONFIG_HWMON_VID is not set |
| 802 | # CONFIG_SENSORS_ABITUGURU is not set | 793 | # CONFIG_SENSORS_AD7414 is not set |
| 803 | # CONFIG_SENSORS_AD7418 is not set | 794 | # CONFIG_SENSORS_AD7418 is not set |
| 795 | # CONFIG_SENSORS_ADCXX is not set | ||
| 804 | # CONFIG_SENSORS_ADM1021 is not set | 796 | # CONFIG_SENSORS_ADM1021 is not set |
| 805 | # CONFIG_SENSORS_ADM1025 is not set | 797 | # CONFIG_SENSORS_ADM1025 is not set |
| 806 | # CONFIG_SENSORS_ADM1026 is not set | 798 | # CONFIG_SENSORS_ADM1026 is not set |
| 807 | # CONFIG_SENSORS_ADM1029 is not set | 799 | # CONFIG_SENSORS_ADM1029 is not set |
| 808 | # CONFIG_SENSORS_ADM1031 is not set | 800 | # CONFIG_SENSORS_ADM1031 is not set |
| 809 | # CONFIG_SENSORS_ADM9240 is not set | 801 | # CONFIG_SENSORS_ADM9240 is not set |
| 810 | # CONFIG_SENSORS_ASB100 is not set | 802 | # CONFIG_SENSORS_ADT7470 is not set |
| 803 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 811 | # CONFIG_SENSORS_ATXP1 is not set | 804 | # CONFIG_SENSORS_ATXP1 is not set |
| 812 | # CONFIG_SENSORS_DS1621 is not set | 805 | # CONFIG_SENSORS_DS1621 is not set |
| 813 | # CONFIG_SENSORS_F71805F is not set | 806 | # CONFIG_SENSORS_F71805F is not set |
| 814 | # CONFIG_SENSORS_FSCHER is not set | 807 | # CONFIG_SENSORS_F71882FG is not set |
| 815 | # CONFIG_SENSORS_FSCPOS is not set | 808 | # CONFIG_SENSORS_F75375S is not set |
| 816 | # CONFIG_SENSORS_GL518SM is not set | 809 | # CONFIG_SENSORS_GL518SM is not set |
| 817 | # CONFIG_SENSORS_GL520SM is not set | 810 | # CONFIG_SENSORS_GL520SM is not set |
| 818 | # CONFIG_SENSORS_IT87 is not set | 811 | # CONFIG_SENSORS_IT87 is not set |
| @@ -827,58 +820,76 @@ CONFIG_HWMON=y | |||
| 827 | # CONFIG_SENSORS_LM87 is not set | 820 | # CONFIG_SENSORS_LM87 is not set |
| 828 | # CONFIG_SENSORS_LM90 is not set | 821 | # CONFIG_SENSORS_LM90 is not set |
| 829 | # CONFIG_SENSORS_LM92 is not set | 822 | # CONFIG_SENSORS_LM92 is not set |
| 823 | # CONFIG_SENSORS_LM93 is not set | ||
| 824 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 830 | # CONFIG_SENSORS_MAX1619 is not set | 825 | # CONFIG_SENSORS_MAX1619 is not set |
| 831 | # CONFIG_SENSORS_MAX6650 is not set | 826 | # CONFIG_SENSORS_MAX6650 is not set |
| 832 | # CONFIG_SENSORS_PC87360 is not set | 827 | # CONFIG_SENSORS_PC87360 is not set |
| 833 | # CONFIG_SENSORS_PC87427 is not set | 828 | # CONFIG_SENSORS_PC87427 is not set |
| 829 | # CONFIG_SENSORS_DME1737 is not set | ||
| 834 | # CONFIG_SENSORS_SMSC47M1 is not set | 830 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 835 | # CONFIG_SENSORS_SMSC47M192 is not set | 831 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 836 | # CONFIG_SENSORS_SMSC47B397 is not set | 832 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 833 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 834 | # CONFIG_SENSORS_THMC50 is not set | ||
| 837 | # CONFIG_SENSORS_VT1211 is not set | 835 | # CONFIG_SENSORS_VT1211 is not set |
| 838 | # CONFIG_SENSORS_W83781D is not set | 836 | # CONFIG_SENSORS_W83781D is not set |
| 839 | # CONFIG_SENSORS_W83791D is not set | 837 | # CONFIG_SENSORS_W83791D is not set |
| 840 | # CONFIG_SENSORS_W83792D is not set | 838 | # CONFIG_SENSORS_W83792D is not set |
| 841 | # CONFIG_SENSORS_W83793 is not set | 839 | # CONFIG_SENSORS_W83793 is not set |
| 842 | # CONFIG_SENSORS_W83L785TS is not set | 840 | # CONFIG_SENSORS_W83L785TS is not set |
| 841 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 843 | # CONFIG_SENSORS_W83627HF is not set | 842 | # CONFIG_SENSORS_W83627HF is not set |
| 844 | # CONFIG_SENSORS_W83627EHF is not set | 843 | # CONFIG_SENSORS_W83627EHF is not set |
| 845 | # CONFIG_HWMON_DEBUG_CHIP is not set | 844 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 845 | # CONFIG_THERMAL is not set | ||
| 846 | # CONFIG_THERMAL_HWMON is not set | ||
| 847 | # CONFIG_WATCHDOG is not set | ||
| 846 | 848 | ||
| 847 | # | 849 | # |
| 848 | # Multifunction device drivers | 850 | # Multifunction device drivers |
| 849 | # | 851 | # |
| 852 | # CONFIG_MFD_CORE is not set | ||
| 850 | # CONFIG_MFD_SM501 is not set | 853 | # CONFIG_MFD_SM501 is not set |
| 854 | # CONFIG_HTC_PASIC3 is not set | ||
| 855 | # CONFIG_MFD_TMIO is not set | ||
| 856 | # CONFIG_MFD_WM8400 is not set | ||
| 857 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 851 | 858 | ||
| 852 | # | 859 | # |
| 853 | # Multimedia devices | 860 | # Multimedia devices |
| 854 | # | 861 | # |
| 862 | |||
| 863 | # | ||
| 864 | # Multimedia core support | ||
| 865 | # | ||
| 855 | # CONFIG_VIDEO_DEV is not set | 866 | # CONFIG_VIDEO_DEV is not set |
| 856 | # CONFIG_DVB_CORE is not set | 867 | # CONFIG_DVB_CORE is not set |
| 857 | CONFIG_DAB=y | 868 | # CONFIG_VIDEO_MEDIA is not set |
| 858 | 869 | ||
| 859 | # | 870 | # |
| 860 | # Graphics support | 871 | # Multimedia drivers |
| 861 | # | 872 | # |
| 862 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 873 | CONFIG_DAB=y |
| 863 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 864 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 865 | 874 | ||
| 866 | # | 875 | # |
| 867 | # Display device support | 876 | # Graphics support |
| 868 | # | 877 | # |
| 869 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 870 | # CONFIG_VGASTATE is not set | 878 | # CONFIG_VGASTATE is not set |
| 879 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 871 | CONFIG_FB=y | 880 | CONFIG_FB=y |
| 872 | CONFIG_FIRMWARE_EDID=y | 881 | CONFIG_FIRMWARE_EDID=y |
| 873 | # CONFIG_FB_DDC is not set | 882 | # CONFIG_FB_DDC is not set |
| 883 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 874 | CONFIG_FB_CFB_FILLRECT=y | 884 | CONFIG_FB_CFB_FILLRECT=y |
| 875 | CONFIG_FB_CFB_COPYAREA=y | 885 | CONFIG_FB_CFB_COPYAREA=y |
| 876 | CONFIG_FB_CFB_IMAGEBLIT=y | 886 | CONFIG_FB_CFB_IMAGEBLIT=y |
| 887 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 877 | # CONFIG_FB_SYS_FILLRECT is not set | 888 | # CONFIG_FB_SYS_FILLRECT is not set |
| 878 | # CONFIG_FB_SYS_COPYAREA is not set | 889 | # CONFIG_FB_SYS_COPYAREA is not set |
| 879 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 890 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 891 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 880 | # CONFIG_FB_SYS_FOPS is not set | 892 | # CONFIG_FB_SYS_FOPS is not set |
| 881 | CONFIG_FB_DEFERRED_IO=y | ||
| 882 | # CONFIG_FB_SVGALIB is not set | 893 | # CONFIG_FB_SVGALIB is not set |
| 883 | # CONFIG_FB_MACMODES is not set | 894 | # CONFIG_FB_MACMODES is not set |
| 884 | # CONFIG_FB_BACKLIGHT is not set | 895 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -888,25 +899,34 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 888 | # | 899 | # |
| 889 | # Frame buffer hardware drivers | 900 | # Frame buffer hardware drivers |
| 890 | # | 901 | # |
| 891 | # CONFIG_FB_BFIN_7171 is not set | 902 | # CONFIG_FB_BFIN_T350MCQB is not set |
| 892 | # CONFIG_FB_BFIN_7393 is not set | 903 | # CONFIG_FB_BFIN_LQ035Q1 is not set |
| 893 | CONFIG_FB_BF537_LQ035=y | 904 | CONFIG_FB_BF537_LQ035=y |
| 894 | CONFIG_LQ035_SLAVE_ADDR=0x58 | 905 | CONFIG_LQ035_SLAVE_ADDR=0x58 |
| 895 | CONFIG_FB_BFIN_LANDSCAPE=y | 906 | CONFIG_FB_BFIN_LANDSCAPE=y |
| 896 | # CONFIG_FB_BFIN_BGR is not set | 907 | # CONFIG_FB_BFIN_BGR is not set |
| 897 | # CONFIG_FB_BFIN_T350MCQB is not set | 908 | # CONFIG_FB_BFIN_7393 is not set |
| 909 | # CONFIG_FB_HITACHI_TX09 is not set | ||
| 898 | # CONFIG_FB_S1D13XXX is not set | 910 | # CONFIG_FB_S1D13XXX is not set |
| 899 | # CONFIG_FB_VIRTUAL is not set | 911 | # CONFIG_FB_VIRTUAL is not set |
| 900 | # CONFIG_LOGO is not set | 912 | # CONFIG_FB_METRONOME is not set |
| 913 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 914 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 915 | # CONFIG_LCD_LTV350QV is not set | ||
| 916 | # CONFIG_LCD_ILI9320 is not set | ||
| 917 | # CONFIG_LCD_TDO24M is not set | ||
| 918 | # CONFIG_LCD_VGG2432A4 is not set | ||
| 919 | # CONFIG_LCD_PLATFORM is not set | ||
| 920 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 921 | # CONFIG_BACKLIGHT_CORGI is not set | ||
| 901 | 922 | ||
| 902 | # | 923 | # |
| 903 | # Sound | 924 | # Display device support |
| 904 | # | 925 | # |
| 926 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 927 | # CONFIG_LOGO is not set | ||
| 905 | CONFIG_SOUND=y | 928 | CONFIG_SOUND=y |
| 906 | 929 | CONFIG_SOUND_OSS_CORE=y | |
| 907 | # | ||
| 908 | # Advanced Linux Sound Architecture | ||
| 909 | # | ||
| 910 | CONFIG_SND=m | 930 | CONFIG_SND=m |
| 911 | # CONFIG_SND_SEQUENCER is not set | 931 | # CONFIG_SND_SEQUENCER is not set |
| 912 | # CONFIG_SND_MIXER_OSS is not set | 932 | # CONFIG_SND_MIXER_OSS is not set |
| @@ -916,46 +936,30 @@ CONFIG_SND=m | |||
| 916 | # CONFIG_SND_VERBOSE_PROCFS is not set | 936 | # CONFIG_SND_VERBOSE_PROCFS is not set |
| 917 | # CONFIG_SND_VERBOSE_PRINTK is not set | 937 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 918 | # CONFIG_SND_DEBUG is not set | 938 | # CONFIG_SND_DEBUG is not set |
| 919 | 939 | CONFIG_SND_DRIVERS=y | |
| 920 | # | ||
| 921 | # Generic devices | ||
| 922 | # | ||
| 923 | # CONFIG_SND_DUMMY is not set | 940 | # CONFIG_SND_DUMMY is not set |
| 924 | # CONFIG_SND_MTPAV is not set | 941 | # CONFIG_SND_MTPAV is not set |
| 925 | # CONFIG_SND_SERIAL_U16550 is not set | 942 | # CONFIG_SND_SERIAL_U16550 is not set |
| 926 | # CONFIG_SND_MPU401 is not set | 943 | # CONFIG_SND_MPU401 is not set |
| 944 | CONFIG_SND_SPI=y | ||
| 927 | 945 | ||
| 928 | # | 946 | # |
| 929 | # ALSA Blackfin devices | 947 | # ALSA Blackfin devices |
| 930 | # | 948 | # |
| 931 | # CONFIG_SND_BLACKFIN_AD1836 is not set | 949 | # CONFIG_SND_BLACKFIN_AD1836 is not set |
| 932 | # CONFIG_SND_BFIN_AD73311 is not set | 950 | # CONFIG_SND_BFIN_AD73322 is not set |
| 933 | |||
| 934 | # | ||
| 935 | # System on Chip audio support | ||
| 936 | # | ||
| 937 | # CONFIG_SND_SOC is not set | 951 | # CONFIG_SND_SOC is not set |
| 938 | |||
| 939 | # | ||
| 940 | # Open Sound System | ||
| 941 | # | ||
| 942 | CONFIG_SOUND_PRIME=y | 952 | CONFIG_SOUND_PRIME=y |
| 943 | # CONFIG_OSS_OBSOLETE is not set | 953 | CONFIG_HID_SUPPORT=y |
| 944 | # CONFIG_SOUND_MSNDCLAS is not set | ||
| 945 | # CONFIG_SOUND_MSNDPIN is not set | ||
| 946 | |||
| 947 | # | ||
| 948 | # HID Devices | ||
| 949 | # | ||
| 950 | # CONFIG_HID is not set | 954 | # CONFIG_HID is not set |
| 951 | 955 | # CONFIG_HID_PID is not set | |
| 952 | # | 956 | CONFIG_USB_SUPPORT=y |
| 953 | # USB support | ||
| 954 | # | ||
| 955 | CONFIG_USB_ARCH_HAS_HCD=y | 957 | CONFIG_USB_ARCH_HAS_HCD=y |
| 956 | # CONFIG_USB_ARCH_HAS_OHCI is not set | 958 | # CONFIG_USB_ARCH_HAS_OHCI is not set |
| 957 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 959 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| 958 | # CONFIG_USB is not set | 960 | # CONFIG_USB is not set |
| 961 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 962 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 959 | 963 | ||
| 960 | # | 964 | # |
| 961 | # Enable Host or Gadget support to see Inventra options | 965 | # Enable Host or Gadget support to see Inventra options |
| @@ -964,37 +968,11 @@ CONFIG_USB_ARCH_HAS_HCD=y | |||
| 964 | # | 968 | # |
| 965 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 969 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' |
| 966 | # | 970 | # |
| 967 | |||
| 968 | # | ||
| 969 | # USB Gadget Support | ||
| 970 | # | ||
| 971 | # CONFIG_USB_GADGET is not set | 971 | # CONFIG_USB_GADGET is not set |
| 972 | # CONFIG_MMC is not set | 972 | # CONFIG_MMC is not set |
| 973 | 973 | # CONFIG_MEMSTICK is not set | |
| 974 | # | ||
| 975 | # LED devices | ||
| 976 | # | ||
| 977 | # CONFIG_NEW_LEDS is not set | 974 | # CONFIG_NEW_LEDS is not set |
| 978 | 975 | # CONFIG_ACCESSIBILITY is not set | |
| 979 | # | ||
| 980 | # LED drivers | ||
| 981 | # | ||
| 982 | |||
| 983 | # | ||
| 984 | # LED Triggers | ||
| 985 | # | ||
| 986 | |||
| 987 | # | ||
| 988 | # InfiniBand support | ||
| 989 | # | ||
| 990 | |||
| 991 | # | ||
| 992 | # EDAC - error detection and reporting (RAS) (EXPERIMENTAL) | ||
| 993 | # | ||
| 994 | |||
| 995 | # | ||
| 996 | # Real Time Clock | ||
| 997 | # | ||
| 998 | CONFIG_RTC_LIB=y | 976 | CONFIG_RTC_LIB=y |
| 999 | CONFIG_RTC_CLASS=y | 977 | CONFIG_RTC_CLASS=y |
| 1000 | CONFIG_RTC_HCTOSYS=y | 978 | CONFIG_RTC_HCTOSYS=y |
| @@ -1014,6 +992,7 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1014 | # I2C RTC drivers | 992 | # I2C RTC drivers |
| 1015 | # | 993 | # |
| 1016 | # CONFIG_RTC_DRV_DS1307 is not set | 994 | # CONFIG_RTC_DRV_DS1307 is not set |
| 995 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1017 | # CONFIG_RTC_DRV_DS1672 is not set | 996 | # CONFIG_RTC_DRV_DS1672 is not set |
| 1018 | # CONFIG_RTC_DRV_MAX6900 is not set | 997 | # CONFIG_RTC_DRV_MAX6900 is not set |
| 1019 | # CONFIG_RTC_DRV_RS5C372 is not set | 998 | # CONFIG_RTC_DRV_RS5C372 is not set |
| @@ -1021,43 +1000,41 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1021 | # CONFIG_RTC_DRV_X1205 is not set | 1000 | # CONFIG_RTC_DRV_X1205 is not set |
| 1022 | # CONFIG_RTC_DRV_PCF8563 is not set | 1001 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1023 | # CONFIG_RTC_DRV_PCF8583 is not set | 1002 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1003 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1004 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1005 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1024 | 1006 | ||
| 1025 | # | 1007 | # |
| 1026 | # SPI RTC drivers | 1008 | # SPI RTC drivers |
| 1027 | # | 1009 | # |
| 1028 | # CONFIG_RTC_DRV_RS5C348 is not set | 1010 | # CONFIG_RTC_DRV_M41T94 is not set |
| 1011 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1029 | # CONFIG_RTC_DRV_MAX6902 is not set | 1012 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 1013 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1014 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1015 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1030 | 1016 | ||
| 1031 | # | 1017 | # |
| 1032 | # Platform RTC drivers | 1018 | # Platform RTC drivers |
| 1033 | # | 1019 | # |
| 1020 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1021 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1034 | # CONFIG_RTC_DRV_DS1553 is not set | 1022 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1035 | # CONFIG_RTC_DRV_DS1742 is not set | 1023 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1024 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1036 | # CONFIG_RTC_DRV_M48T86 is not set | 1025 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1026 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1027 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1028 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1037 | # CONFIG_RTC_DRV_V3020 is not set | 1029 | # CONFIG_RTC_DRV_V3020 is not set |
| 1038 | 1030 | ||
| 1039 | # | 1031 | # |
| 1040 | # on-CPU RTC drivers | 1032 | # on-CPU RTC drivers |
| 1041 | # | 1033 | # |
| 1042 | CONFIG_RTC_DRV_BFIN=y | 1034 | CONFIG_RTC_DRV_BFIN=y |
| 1043 | 1035 | # CONFIG_DMADEVICES is not set | |
| 1044 | # | 1036 | # CONFIG_UIO is not set |
| 1045 | # DMA Engine support | 1037 | # CONFIG_STAGING is not set |
| 1046 | # | ||
| 1047 | # CONFIG_DMA_ENGINE is not set | ||
| 1048 | |||
| 1049 | # | ||
| 1050 | # DMA Clients | ||
| 1051 | # | ||
| 1052 | |||
| 1053 | # | ||
| 1054 | # DMA Devices | ||
| 1055 | # | ||
| 1056 | |||
| 1057 | # | ||
| 1058 | # PBX support | ||
| 1059 | # | ||
| 1060 | # CONFIG_PBX is not set | ||
| 1061 | 1038 | ||
| 1062 | # | 1039 | # |
| 1063 | # File systems | 1040 | # File systems |
| @@ -1067,20 +1044,18 @@ CONFIG_EXT2_FS_XATTR=y | |||
| 1067 | # CONFIG_EXT2_FS_POSIX_ACL is not set | 1044 | # CONFIG_EXT2_FS_POSIX_ACL is not set |
| 1068 | # CONFIG_EXT2_FS_SECURITY is not set | 1045 | # CONFIG_EXT2_FS_SECURITY is not set |
| 1069 | # CONFIG_EXT3_FS is not set | 1046 | # CONFIG_EXT3_FS is not set |
| 1070 | # CONFIG_EXT4DEV_FS is not set | 1047 | # CONFIG_EXT4_FS is not set |
| 1071 | CONFIG_FS_MBCACHE=y | 1048 | CONFIG_FS_MBCACHE=y |
| 1072 | # CONFIG_REISERFS_FS is not set | 1049 | # CONFIG_REISERFS_FS is not set |
| 1073 | # CONFIG_JFS_FS is not set | 1050 | # CONFIG_JFS_FS is not set |
| 1074 | # CONFIG_FS_POSIX_ACL is not set | 1051 | # CONFIG_FS_POSIX_ACL is not set |
| 1052 | CONFIG_FILE_LOCKING=y | ||
| 1075 | # CONFIG_XFS_FS is not set | 1053 | # CONFIG_XFS_FS is not set |
| 1076 | # CONFIG_GFS2_FS is not set | ||
| 1077 | # CONFIG_OCFS2_FS is not set | 1054 | # CONFIG_OCFS2_FS is not set |
| 1078 | # CONFIG_MINIX_FS is not set | 1055 | # CONFIG_DNOTIFY is not set |
| 1079 | # CONFIG_ROMFS_FS is not set | ||
| 1080 | CONFIG_INOTIFY=y | 1056 | CONFIG_INOTIFY=y |
| 1081 | CONFIG_INOTIFY_USER=y | 1057 | CONFIG_INOTIFY_USER=y |
| 1082 | # CONFIG_QUOTA is not set | 1058 | # CONFIG_QUOTA is not set |
| 1083 | # CONFIG_DNOTIFY is not set | ||
| 1084 | # CONFIG_AUTOFS_FS is not set | 1059 | # CONFIG_AUTOFS_FS is not set |
| 1085 | # CONFIG_AUTOFS4_FS is not set | 1060 | # CONFIG_AUTOFS4_FS is not set |
| 1086 | # CONFIG_FUSE_FS is not set | 1061 | # CONFIG_FUSE_FS is not set |
| @@ -1106,7 +1081,6 @@ CONFIG_PROC_SYSCTL=y | |||
| 1106 | CONFIG_SYSFS=y | 1081 | CONFIG_SYSFS=y |
| 1107 | # CONFIG_TMPFS is not set | 1082 | # CONFIG_TMPFS is not set |
| 1108 | # CONFIG_HUGETLB_PAGE is not set | 1083 | # CONFIG_HUGETLB_PAGE is not set |
| 1109 | CONFIG_RAMFS=y | ||
| 1110 | # CONFIG_CONFIGFS_FS is not set | 1084 | # CONFIG_CONFIGFS_FS is not set |
| 1111 | 1085 | ||
| 1112 | # | 1086 | # |
| @@ -1121,36 +1095,35 @@ CONFIG_RAMFS=y | |||
| 1121 | # CONFIG_EFS_FS is not set | 1095 | # CONFIG_EFS_FS is not set |
| 1122 | CONFIG_YAFFS_FS=y | 1096 | CONFIG_YAFFS_FS=y |
| 1123 | CONFIG_YAFFS_YAFFS1=y | 1097 | CONFIG_YAFFS_YAFFS1=y |
| 1098 | # CONFIG_YAFFS_9BYTE_TAGS is not set | ||
| 1124 | # CONFIG_YAFFS_DOES_ECC is not set | 1099 | # CONFIG_YAFFS_DOES_ECC is not set |
| 1125 | CONFIG_YAFFS_YAFFS2=y | 1100 | CONFIG_YAFFS_YAFFS2=y |
| 1126 | CONFIG_YAFFS_AUTO_YAFFS2=y | 1101 | CONFIG_YAFFS_AUTO_YAFFS2=y |
| 1127 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set | 1102 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set |
| 1128 | CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 | ||
| 1129 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set | 1103 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 1130 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set | 1104 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 1131 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y | 1105 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| 1132 | # CONFIG_JFFS2_FS is not set | 1106 | # CONFIG_JFFS2_FS is not set |
| 1133 | # CONFIG_CRAMFS is not set | 1107 | # CONFIG_CRAMFS is not set |
| 1134 | # CONFIG_VXFS_FS is not set | 1108 | # CONFIG_VXFS_FS is not set |
| 1109 | # CONFIG_MINIX_FS is not set | ||
| 1110 | # CONFIG_OMFS_FS is not set | ||
| 1135 | # CONFIG_HPFS_FS is not set | 1111 | # CONFIG_HPFS_FS is not set |
| 1136 | # CONFIG_QNX4FS_FS is not set | 1112 | # CONFIG_QNX4FS_FS is not set |
| 1113 | # CONFIG_ROMFS_FS is not set | ||
| 1137 | # CONFIG_SYSV_FS is not set | 1114 | # CONFIG_SYSV_FS is not set |
| 1138 | # CONFIG_UFS_FS is not set | 1115 | # CONFIG_UFS_FS is not set |
| 1139 | 1116 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 1140 | # | ||
| 1141 | # Network File Systems | ||
| 1142 | # | ||
| 1143 | CONFIG_NFS_FS=m | 1117 | CONFIG_NFS_FS=m |
| 1144 | CONFIG_NFS_V3=y | 1118 | CONFIG_NFS_V3=y |
| 1145 | # CONFIG_NFS_V3_ACL is not set | 1119 | # CONFIG_NFS_V3_ACL is not set |
| 1146 | # CONFIG_NFS_V4 is not set | 1120 | # CONFIG_NFS_V4 is not set |
| 1147 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1148 | # CONFIG_NFSD is not set | 1121 | # CONFIG_NFSD is not set |
| 1149 | CONFIG_LOCKD=m | 1122 | CONFIG_LOCKD=m |
| 1150 | CONFIG_LOCKD_V4=y | 1123 | CONFIG_LOCKD_V4=y |
| 1151 | CONFIG_NFS_COMMON=y | 1124 | CONFIG_NFS_COMMON=y |
| 1152 | CONFIG_SUNRPC=m | 1125 | CONFIG_SUNRPC=m |
| 1153 | # CONFIG_SUNRPC_BIND34 is not set | 1126 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1154 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1127 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1155 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1128 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1156 | CONFIG_SMB_FS=m | 1129 | CONFIG_SMB_FS=m |
| @@ -1159,17 +1132,12 @@ CONFIG_SMB_FS=m | |||
| 1159 | # CONFIG_NCP_FS is not set | 1132 | # CONFIG_NCP_FS is not set |
| 1160 | # CONFIG_CODA_FS is not set | 1133 | # CONFIG_CODA_FS is not set |
| 1161 | # CONFIG_AFS_FS is not set | 1134 | # CONFIG_AFS_FS is not set |
| 1162 | # CONFIG_9P_FS is not set | ||
| 1163 | 1135 | ||
| 1164 | # | 1136 | # |
| 1165 | # Partition Types | 1137 | # Partition Types |
| 1166 | # | 1138 | # |
| 1167 | # CONFIG_PARTITION_ADVANCED is not set | 1139 | # CONFIG_PARTITION_ADVANCED is not set |
| 1168 | CONFIG_MSDOS_PARTITION=y | 1140 | CONFIG_MSDOS_PARTITION=y |
| 1169 | |||
| 1170 | # | ||
| 1171 | # Native Language Support | ||
| 1172 | # | ||
| 1173 | CONFIG_NLS=m | 1141 | CONFIG_NLS=m |
| 1174 | CONFIG_NLS_DEFAULT="iso8859-1" | 1142 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1175 | # CONFIG_NLS_CODEPAGE_437 is not set | 1143 | # CONFIG_NLS_CODEPAGE_437 is not set |
| @@ -1210,29 +1178,30 @@ CONFIG_NLS_DEFAULT="iso8859-1" | |||
| 1210 | # CONFIG_NLS_KOI8_R is not set | 1178 | # CONFIG_NLS_KOI8_R is not set |
| 1211 | # CONFIG_NLS_KOI8_U is not set | 1179 | # CONFIG_NLS_KOI8_U is not set |
| 1212 | # CONFIG_NLS_UTF8 is not set | 1180 | # CONFIG_NLS_UTF8 is not set |
| 1213 | |||
| 1214 | # | ||
| 1215 | # Distributed Lock Manager | ||
| 1216 | # | ||
| 1217 | # CONFIG_DLM is not set | 1181 | # CONFIG_DLM is not set |
| 1218 | 1182 | ||
| 1219 | # | 1183 | # |
| 1220 | # Profiling support | ||
| 1221 | # | ||
| 1222 | # CONFIG_PROFILING is not set | ||
| 1223 | |||
| 1224 | # | ||
| 1225 | # Kernel hacking | 1184 | # Kernel hacking |
| 1226 | # | 1185 | # |
| 1227 | # CONFIG_PRINTK_TIME is not set | 1186 | # CONFIG_PRINTK_TIME is not set |
| 1187 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1228 | CONFIG_ENABLE_MUST_CHECK=y | 1188 | CONFIG_ENABLE_MUST_CHECK=y |
| 1189 | CONFIG_FRAME_WARN=1024 | ||
| 1229 | # CONFIG_MAGIC_SYSRQ is not set | 1190 | # CONFIG_MAGIC_SYSRQ is not set |
| 1230 | # CONFIG_UNUSED_SYMBOLS is not set | 1191 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1231 | # CONFIG_DEBUG_FS is not set | 1192 | # CONFIG_DEBUG_FS is not set |
| 1232 | # CONFIG_HEADERS_CHECK is not set | 1193 | # CONFIG_HEADERS_CHECK is not set |
| 1233 | # CONFIG_DEBUG_KERNEL is not set | 1194 | # CONFIG_DEBUG_KERNEL is not set |
| 1234 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1195 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1196 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1197 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1198 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1199 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1200 | # CONFIG_SAMPLES is not set | ||
| 1201 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1202 | CONFIG_DEBUG_VERBOSE=y | ||
| 1235 | # CONFIG_DEBUG_MMRS is not set | 1203 | # CONFIG_DEBUG_MMRS is not set |
| 1204 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 1236 | # CONFIG_DEBUG_HUNT_FOR_ZERO is not set | 1205 | # CONFIG_DEBUG_HUNT_FOR_ZERO is not set |
| 1237 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 1206 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 1238 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 1207 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -1250,13 +1219,94 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 | |||
| 1250 | # | 1219 | # |
| 1251 | # CONFIG_KEYS is not set | 1220 | # CONFIG_KEYS is not set |
| 1252 | CONFIG_SECURITY=y | 1221 | CONFIG_SECURITY=y |
| 1222 | # CONFIG_SECURITYFS is not set | ||
| 1253 | # CONFIG_SECURITY_NETWORK is not set | 1223 | # CONFIG_SECURITY_NETWORK is not set |
| 1254 | CONFIG_SECURITY_CAPABILITIES=y | 1224 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1225 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 1226 | CONFIG_CRYPTO=y | ||
| 1227 | |||
| 1228 | # | ||
| 1229 | # Crypto core or helper | ||
| 1230 | # | ||
| 1231 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1232 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1233 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1234 | # CONFIG_CRYPTO_NULL is not set | ||
| 1235 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1236 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1237 | # CONFIG_CRYPTO_TEST is not set | ||
| 1238 | |||
| 1239 | # | ||
| 1240 | # Authenticated Encryption with Associated Data | ||
| 1241 | # | ||
| 1242 | # CONFIG_CRYPTO_CCM is not set | ||
| 1243 | # CONFIG_CRYPTO_GCM is not set | ||
| 1244 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1245 | |||
| 1246 | # | ||
| 1247 | # Block modes | ||
| 1248 | # | ||
| 1249 | # CONFIG_CRYPTO_CBC is not set | ||
| 1250 | # CONFIG_CRYPTO_CTR is not set | ||
| 1251 | # CONFIG_CRYPTO_CTS is not set | ||
| 1252 | # CONFIG_CRYPTO_ECB is not set | ||
| 1253 | # CONFIG_CRYPTO_LRW is not set | ||
| 1254 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1255 | # CONFIG_CRYPTO_XTS is not set | ||
| 1256 | |||
| 1257 | # | ||
| 1258 | # Hash modes | ||
| 1259 | # | ||
| 1260 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1261 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1262 | |||
| 1263 | # | ||
| 1264 | # Digest | ||
| 1265 | # | ||
| 1266 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1267 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1268 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1269 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1270 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1271 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1272 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1273 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1274 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1275 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1276 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1277 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1278 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1279 | |||
| 1280 | # | ||
| 1281 | # Ciphers | ||
| 1282 | # | ||
| 1283 | # CONFIG_CRYPTO_AES is not set | ||
| 1284 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1285 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1286 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1287 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1288 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1289 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1290 | # CONFIG_CRYPTO_DES is not set | ||
| 1291 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1292 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1293 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1294 | # CONFIG_CRYPTO_SEED is not set | ||
| 1295 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1296 | # CONFIG_CRYPTO_TEA is not set | ||
| 1297 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1298 | |||
| 1299 | # | ||
| 1300 | # Compression | ||
| 1301 | # | ||
| 1302 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1303 | # CONFIG_CRYPTO_LZO is not set | ||
| 1255 | 1304 | ||
| 1256 | # | 1305 | # |
| 1257 | # Cryptographic options | 1306 | # Random Number Generation |
| 1258 | # | 1307 | # |
| 1259 | # CONFIG_CRYPTO is not set | 1308 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 1309 | CONFIG_CRYPTO_HW=y | ||
| 1260 | 1310 | ||
| 1261 | # | 1311 | # |
| 1262 | # Library routines | 1312 | # Library routines |
| @@ -1264,8 +1314,10 @@ CONFIG_SECURITY_CAPABILITIES=y | |||
| 1264 | CONFIG_BITREVERSE=y | 1314 | CONFIG_BITREVERSE=y |
| 1265 | CONFIG_CRC_CCITT=m | 1315 | CONFIG_CRC_CCITT=m |
| 1266 | # CONFIG_CRC16 is not set | 1316 | # CONFIG_CRC16 is not set |
| 1317 | # CONFIG_CRC_T10DIF is not set | ||
| 1267 | # CONFIG_CRC_ITU_T is not set | 1318 | # CONFIG_CRC_ITU_T is not set |
| 1268 | CONFIG_CRC32=y | 1319 | CONFIG_CRC32=y |
| 1320 | # CONFIG_CRC7 is not set | ||
| 1269 | # CONFIG_LIBCRC32C is not set | 1321 | # CONFIG_LIBCRC32C is not set |
| 1270 | CONFIG_ZLIB_INFLATE=y | 1322 | CONFIG_ZLIB_INFLATE=y |
| 1271 | CONFIG_PLIST=y | 1323 | CONFIG_PLIST=y |
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig index b1309f878fcd..7c8250d6fa66 100644 --- a/arch/blackfin/configs/SRV1_defconfig +++ b/arch/blackfin/configs/SRV1_defconfig | |||
| @@ -59,7 +59,7 @@ CONFIG_KALLSYMS_ALL=y | |||
| 59 | CONFIG_HOTPLUG=y | 59 | CONFIG_HOTPLUG=y |
| 60 | CONFIG_PRINTK=y | 60 | CONFIG_PRINTK=y |
| 61 | CONFIG_BUG=y | 61 | CONFIG_BUG=y |
| 62 | CONFIG_ELF_CORE=y | 62 | # CONFIG_ELF_CORE is not set |
| 63 | CONFIG_BASE_FULL=y | 63 | CONFIG_BASE_FULL=y |
| 64 | CONFIG_FUTEX=y | 64 | CONFIG_FUTEX=y |
| 65 | CONFIG_ANON_INODES=y | 65 | CONFIG_ANON_INODES=y |
| @@ -172,14 +172,14 @@ CONFIG_IRQ_UART1_RX=10 | |||
| 172 | CONFIG_IRQ_UART1_TX=10 | 172 | CONFIG_IRQ_UART1_TX=10 |
| 173 | CONFIG_IRQ_MAC_RX=11 | 173 | CONFIG_IRQ_MAC_RX=11 |
| 174 | CONFIG_IRQ_MAC_TX=11 | 174 | CONFIG_IRQ_MAC_TX=11 |
| 175 | CONFIG_IRQ_TMR0=12 | 175 | CONFIG_IRQ_TIMER0=12 |
| 176 | CONFIG_IRQ_TMR1=12 | 176 | CONFIG_IRQ_TIMER1=12 |
| 177 | CONFIG_IRQ_TMR2=12 | 177 | CONFIG_IRQ_TIMER2=12 |
| 178 | CONFIG_IRQ_TMR3=12 | 178 | CONFIG_IRQ_TIMER3=12 |
| 179 | CONFIG_IRQ_TMR4=12 | 179 | CONFIG_IRQ_TIMER4=12 |
| 180 | CONFIG_IRQ_TMR5=12 | 180 | CONFIG_IRQ_TIMER5=12 |
| 181 | CONFIG_IRQ_TMR6=12 | 181 | CONFIG_IRQ_TIMER6=12 |
| 182 | CONFIG_IRQ_TMR7=12 | 182 | CONFIG_IRQ_TIMER7=12 |
| 183 | CONFIG_IRQ_PORTG_INTB=12 | 183 | CONFIG_IRQ_PORTG_INTB=12 |
| 184 | CONFIG_IRQ_MEM_DMA0=13 | 184 | CONFIG_IRQ_MEM_DMA0=13 |
| 185 | CONFIG_IRQ_MEM_DMA1=13 | 185 | CONFIG_IRQ_MEM_DMA1=13 |
| @@ -271,7 +271,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 | |||
| 271 | # CONFIG_RESOURCES_64BIT is not set | 271 | # CONFIG_RESOURCES_64BIT is not set |
| 272 | CONFIG_ZONE_DMA_FLAG=1 | 272 | CONFIG_ZONE_DMA_FLAG=1 |
| 273 | CONFIG_LARGE_ALLOCS=y | 273 | CONFIG_LARGE_ALLOCS=y |
| 274 | CONFIG_BFIN_DMA_5XX=y | ||
| 275 | CONFIG_DMA_UNCACHED_2M=y | 274 | CONFIG_DMA_UNCACHED_2M=y |
| 276 | # CONFIG_DMA_UNCACHED_1M is not set | 275 | # CONFIG_DMA_UNCACHED_1M is not set |
| 277 | # CONFIG_DMA_UNCACHED_NONE is not set | 276 | # CONFIG_DMA_UNCACHED_NONE is not set |
| @@ -786,7 +785,7 @@ CONFIG_I2C_CHARDEV=y | |||
| 786 | # | 785 | # |
| 787 | # CONFIG_I2C_BLACKFIN_GPIO is not set | 786 | # CONFIG_I2C_BLACKFIN_GPIO is not set |
| 788 | CONFIG_I2C_BLACKFIN_TWI=y | 787 | CONFIG_I2C_BLACKFIN_TWI=y |
| 789 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 | 788 | CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 |
| 790 | # CONFIG_I2C_GPIO is not set | 789 | # CONFIG_I2C_GPIO is not set |
| 791 | # CONFIG_I2C_OCORES is not set | 790 | # CONFIG_I2C_OCORES is not set |
| 792 | # CONFIG_I2C_PARPORT_LIGHT is not set | 791 | # CONFIG_I2C_PARPORT_LIGHT is not set |
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig index c482ee171f9e..9af522c7dadf 100644 --- a/arch/blackfin/configs/TCM-BF537_defconfig +++ b/arch/blackfin/configs/TCM-BF537_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24.7 | 3 | # Linux kernel version: 2.6.28-rc2 |
| 4 | # Thu Jul 31 00:53:15 2008 | 4 | # Tue Jan 6 09:22:17 2009 |
| 5 | # | 5 | # |
| 6 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 7 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -9,7 +9,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 9 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set | 9 | # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set |
| 10 | CONFIG_BLACKFIN=y | 10 | CONFIG_BLACKFIN=y |
| 11 | CONFIG_ZONE_DMA=y | 11 | CONFIG_ZONE_DMA=y |
| 12 | CONFIG_SEMAPHORE_SLEEPERS=y | ||
| 13 | CONFIG_GENERIC_FIND_NEXT_BIT=y | 12 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 14 | CONFIG_GENERIC_HWEIGHT=y | 13 | CONFIG_GENERIC_HWEIGHT=y |
| 15 | CONFIG_GENERIC_HARDIRQS=y | 14 | CONFIG_GENERIC_HARDIRQS=y |
| @@ -30,17 +29,14 @@ CONFIG_LOCALVERSION_AUTO=y | |||
| 30 | CONFIG_SYSVIPC=y | 29 | CONFIG_SYSVIPC=y |
| 31 | CONFIG_SYSVIPC_SYSCTL=y | 30 | CONFIG_SYSVIPC_SYSCTL=y |
| 32 | # CONFIG_BSD_PROCESS_ACCT is not set | 31 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 33 | # CONFIG_USER_NS is not set | ||
| 34 | # CONFIG_PID_NS is not set | ||
| 35 | CONFIG_IKCONFIG=y | 32 | CONFIG_IKCONFIG=y |
| 36 | CONFIG_IKCONFIG_PROC=y | 33 | CONFIG_IKCONFIG_PROC=y |
| 37 | CONFIG_LOG_BUF_SHIFT=14 | 34 | CONFIG_LOG_BUF_SHIFT=14 |
| 38 | # CONFIG_CGROUPS is not set | 35 | # CONFIG_CGROUPS is not set |
| 39 | CONFIG_FAIR_GROUP_SCHED=y | 36 | # CONFIG_GROUP_SCHED is not set |
| 40 | CONFIG_FAIR_USER_SCHED=y | 37 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 41 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 42 | CONFIG_SYSFS_DEPRECATED=y | ||
| 43 | # CONFIG_RELAY is not set | 38 | # CONFIG_RELAY is not set |
| 39 | # CONFIG_NAMESPACES is not set | ||
| 44 | # CONFIG_BLK_DEV_INITRD is not set | 40 | # CONFIG_BLK_DEV_INITRD is not set |
| 45 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 41 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 46 | CONFIG_SYSCTL=y | 42 | CONFIG_SYSCTL=y |
| @@ -52,22 +48,30 @@ CONFIG_KALLSYMS=y | |||
| 52 | # CONFIG_HOTPLUG is not set | 48 | # CONFIG_HOTPLUG is not set |
| 53 | CONFIG_PRINTK=y | 49 | CONFIG_PRINTK=y |
| 54 | CONFIG_BUG=y | 50 | CONFIG_BUG=y |
| 55 | CONFIG_ELF_CORE=y | 51 | # CONFIG_ELF_CORE is not set |
| 52 | CONFIG_COMPAT_BRK=y | ||
| 56 | CONFIG_BASE_FULL=y | 53 | CONFIG_BASE_FULL=y |
| 57 | CONFIG_FUTEX=y | 54 | CONFIG_FUTEX=y |
| 58 | CONFIG_ANON_INODES=y | 55 | CONFIG_ANON_INODES=y |
| 59 | CONFIG_EPOLL=y | 56 | CONFIG_EPOLL=y |
| 60 | CONFIG_SIGNALFD=y | 57 | CONFIG_SIGNALFD=y |
| 58 | CONFIG_TIMERFD=y | ||
| 61 | CONFIG_EVENTFD=y | 59 | CONFIG_EVENTFD=y |
| 60 | CONFIG_AIO=y | ||
| 62 | CONFIG_VM_EVENT_COUNTERS=y | 61 | CONFIG_VM_EVENT_COUNTERS=y |
| 63 | CONFIG_SLAB=y | 62 | CONFIG_SLAB=y |
| 64 | # CONFIG_SLUB is not set | 63 | # CONFIG_SLUB is not set |
| 65 | # CONFIG_SLOB is not set | 64 | # CONFIG_SLOB is not set |
| 65 | # CONFIG_PROFILING is not set | ||
| 66 | # CONFIG_MARKERS is not set | ||
| 67 | CONFIG_HAVE_OPROFILE=y | ||
| 68 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 66 | CONFIG_SLABINFO=y | 69 | CONFIG_SLABINFO=y |
| 67 | CONFIG_RT_MUTEXES=y | 70 | CONFIG_RT_MUTEXES=y |
| 68 | CONFIG_TINY_SHMEM=y | 71 | CONFIG_TINY_SHMEM=y |
| 69 | CONFIG_BASE_SMALL=0 | 72 | CONFIG_BASE_SMALL=0 |
| 70 | CONFIG_MODULES=y | 73 | CONFIG_MODULES=y |
| 74 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 71 | CONFIG_MODULE_UNLOAD=y | 75 | CONFIG_MODULE_UNLOAD=y |
| 72 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 76 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 73 | # CONFIG_MODVERSIONS is not set | 77 | # CONFIG_MODVERSIONS is not set |
| @@ -78,6 +82,7 @@ CONFIG_BLOCK=y | |||
| 78 | # CONFIG_BLK_DEV_IO_TRACE is not set | 82 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 79 | # CONFIG_LSF is not set | 83 | # CONFIG_LSF is not set |
| 80 | # CONFIG_BLK_DEV_BSG is not set | 84 | # CONFIG_BLK_DEV_BSG is not set |
| 85 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 81 | 86 | ||
| 82 | # | 87 | # |
| 83 | # IO Schedulers | 88 | # IO Schedulers |
| @@ -91,9 +96,11 @@ CONFIG_IOSCHED_CFQ=y | |||
| 91 | # CONFIG_DEFAULT_CFQ is not set | 96 | # CONFIG_DEFAULT_CFQ is not set |
| 92 | CONFIG_DEFAULT_NOOP=y | 97 | CONFIG_DEFAULT_NOOP=y |
| 93 | CONFIG_DEFAULT_IOSCHED="noop" | 98 | CONFIG_DEFAULT_IOSCHED="noop" |
| 99 | CONFIG_CLASSIC_RCU=y | ||
| 94 | CONFIG_PREEMPT_NONE=y | 100 | CONFIG_PREEMPT_NONE=y |
| 95 | # CONFIG_PREEMPT_VOLUNTARY is not set | 101 | # CONFIG_PREEMPT_VOLUNTARY is not set |
| 96 | # CONFIG_PREEMPT is not set | 102 | # CONFIG_PREEMPT is not set |
| 103 | # CONFIG_FREEZER is not set | ||
| 97 | 104 | ||
| 98 | # | 105 | # |
| 99 | # Blackfin Processor Options | 106 | # Blackfin Processor Options |
| @@ -102,6 +109,10 @@ CONFIG_PREEMPT_NONE=y | |||
| 102 | # | 109 | # |
| 103 | # Processor and Board Settings | 110 | # Processor and Board Settings |
| 104 | # | 111 | # |
| 112 | # CONFIG_BF512 is not set | ||
| 113 | # CONFIG_BF514 is not set | ||
| 114 | # CONFIG_BF516 is not set | ||
| 115 | # CONFIG_BF518 is not set | ||
| 105 | # CONFIG_BF522 is not set | 116 | # CONFIG_BF522 is not set |
| 106 | # CONFIG_BF523 is not set | 117 | # CONFIG_BF523 is not set |
| 107 | # CONFIG_BF524 is not set | 118 | # CONFIG_BF524 is not set |
| @@ -114,18 +125,23 @@ CONFIG_PREEMPT_NONE=y | |||
| 114 | # CONFIG_BF534 is not set | 125 | # CONFIG_BF534 is not set |
| 115 | # CONFIG_BF536 is not set | 126 | # CONFIG_BF536 is not set |
| 116 | CONFIG_BF537=y | 127 | CONFIG_BF537=y |
| 128 | # CONFIG_BF538 is not set | ||
| 129 | # CONFIG_BF539 is not set | ||
| 117 | # CONFIG_BF542 is not set | 130 | # CONFIG_BF542 is not set |
| 118 | # CONFIG_BF544 is not set | 131 | # CONFIG_BF544 is not set |
| 119 | # CONFIG_BF547 is not set | 132 | # CONFIG_BF547 is not set |
| 120 | # CONFIG_BF548 is not set | 133 | # CONFIG_BF548 is not set |
| 121 | # CONFIG_BF549 is not set | 134 | # CONFIG_BF549 is not set |
| 122 | # CONFIG_BF561 is not set | 135 | # CONFIG_BF561 is not set |
| 136 | CONFIG_BF_REV_MIN=2 | ||
| 137 | CONFIG_BF_REV_MAX=3 | ||
| 123 | # CONFIG_BF_REV_0_0 is not set | 138 | # CONFIG_BF_REV_0_0 is not set |
| 124 | # CONFIG_BF_REV_0_1 is not set | 139 | # CONFIG_BF_REV_0_1 is not set |
| 125 | CONFIG_BF_REV_0_2=y | 140 | CONFIG_BF_REV_0_2=y |
| 126 | # CONFIG_BF_REV_0_3 is not set | 141 | # CONFIG_BF_REV_0_3 is not set |
| 127 | # CONFIG_BF_REV_0_4 is not set | 142 | # CONFIG_BF_REV_0_4 is not set |
| 128 | # CONFIG_BF_REV_0_5 is not set | 143 | # CONFIG_BF_REV_0_5 is not set |
| 144 | # CONFIG_BF_REV_0_6 is not set | ||
| 129 | # CONFIG_BF_REV_ANY is not set | 145 | # CONFIG_BF_REV_ANY is not set |
| 130 | # CONFIG_BF_REV_NONE is not set | 146 | # CONFIG_BF_REV_NONE is not set |
| 131 | CONFIG_BF53x=y | 147 | CONFIG_BF53x=y |
| @@ -137,25 +153,25 @@ CONFIG_IRQ_SPORT0_TX=9 | |||
| 137 | CONFIG_IRQ_SPORT1_RX=9 | 153 | CONFIG_IRQ_SPORT1_RX=9 |
| 138 | CONFIG_IRQ_SPORT1_TX=9 | 154 | CONFIG_IRQ_SPORT1_TX=9 |
| 139 | CONFIG_IRQ_TWI=10 | 155 | CONFIG_IRQ_TWI=10 |
| 140 | CONFIG_IRQ_SPI=10 | ||
| 141 | CONFIG_IRQ_UART0_RX=10 | 156 | CONFIG_IRQ_UART0_RX=10 |
| 142 | CONFIG_IRQ_UART0_TX=10 | 157 | CONFIG_IRQ_UART0_TX=10 |
| 143 | CONFIG_IRQ_UART1_RX=10 | 158 | CONFIG_IRQ_UART1_RX=10 |
| 144 | CONFIG_IRQ_UART1_TX=10 | 159 | CONFIG_IRQ_UART1_TX=10 |
| 145 | CONFIG_IRQ_MAC_RX=11 | 160 | CONFIG_IRQ_MAC_RX=11 |
| 146 | CONFIG_IRQ_MAC_TX=11 | 161 | CONFIG_IRQ_MAC_TX=11 |
| 147 | CONFIG_IRQ_TMR0=12 | 162 | CONFIG_IRQ_TIMER0=12 |
| 148 | CONFIG_IRQ_TMR1=12 | 163 | CONFIG_IRQ_TIMER1=12 |
| 149 | CONFIG_IRQ_TMR2=12 | 164 | CONFIG_IRQ_TIMER2=12 |
| 150 | CONFIG_IRQ_TMR3=12 | 165 | CONFIG_IRQ_TIMER3=12 |
| 151 | CONFIG_IRQ_TMR4=12 | 166 | CONFIG_IRQ_TIMER4=12 |
| 152 | CONFIG_IRQ_TMR5=12 | 167 | CONFIG_IRQ_TIMER5=12 |
| 153 | CONFIG_IRQ_TMR6=12 | 168 | CONFIG_IRQ_TIMER6=12 |
| 154 | CONFIG_IRQ_TMR7=12 | 169 | CONFIG_IRQ_TIMER7=12 |
| 155 | CONFIG_IRQ_PORTG_INTB=12 | 170 | CONFIG_IRQ_PORTG_INTB=12 |
| 156 | CONFIG_IRQ_MEM_DMA0=13 | 171 | CONFIG_IRQ_MEM_DMA0=13 |
| 157 | CONFIG_IRQ_MEM_DMA1=13 | 172 | CONFIG_IRQ_MEM_DMA1=13 |
| 158 | CONFIG_IRQ_WATCH=13 | 173 | CONFIG_IRQ_WATCH=13 |
| 174 | CONFIG_IRQ_SPI=10 | ||
| 159 | # CONFIG_BFIN537_STAMP is not set | 175 | # CONFIG_BFIN537_STAMP is not set |
| 160 | # CONFIG_BFIN537_BLUETECHNIX_CM is not set | 176 | # CONFIG_BFIN537_BLUETECHNIX_CM is not set |
| 161 | CONFIG_BFIN537_BLUETECHNIX_TCM=y | 177 | CONFIG_BFIN537_BLUETECHNIX_TCM=y |
| @@ -191,7 +207,6 @@ CONFIG_BOOT_LOAD=0x1000 | |||
| 191 | # | 207 | # |
| 192 | CONFIG_CLKIN_HZ=25000000 | 208 | CONFIG_CLKIN_HZ=25000000 |
| 193 | # CONFIG_BFIN_KERNEL_CLOCK is not set | 209 | # CONFIG_BFIN_KERNEL_CLOCK is not set |
| 194 | CONFIG_MAX_MEM_SIZE=32 | ||
| 195 | CONFIG_MAX_VCO_HZ=600000000 | 210 | CONFIG_MAX_VCO_HZ=600000000 |
| 196 | CONFIG_MIN_VCO_HZ=50000000 | 211 | CONFIG_MIN_VCO_HZ=50000000 |
| 197 | CONFIG_MAX_SCLK_HZ=133333333 | 212 | CONFIG_MAX_SCLK_HZ=133333333 |
| @@ -205,10 +220,10 @@ CONFIG_HZ_250=y | |||
| 205 | # CONFIG_HZ_300 is not set | 220 | # CONFIG_HZ_300 is not set |
| 206 | # CONFIG_HZ_1000 is not set | 221 | # CONFIG_HZ_1000 is not set |
| 207 | CONFIG_HZ=250 | 222 | CONFIG_HZ=250 |
| 223 | # CONFIG_SCHED_HRTICK is not set | ||
| 208 | CONFIG_GENERIC_TIME=y | 224 | CONFIG_GENERIC_TIME=y |
| 209 | CONFIG_GENERIC_CLOCKEVENTS=y | 225 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 210 | # CONFIG_CYCLES_CLOCKSOURCE is not set | 226 | # CONFIG_CYCLES_CLOCKSOURCE is not set |
| 211 | # CONFIG_TICK_ONESHOT is not set | ||
| 212 | # CONFIG_NO_HZ is not set | 227 | # CONFIG_NO_HZ is not set |
| 213 | # CONFIG_HIGH_RES_TIMERS is not set | 228 | # CONFIG_HIGH_RES_TIMERS is not set |
| 214 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 229 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -242,6 +257,12 @@ CONFIG_IP_CHECKSUM_L1=y | |||
| 242 | CONFIG_CACHELINE_ALIGNED_L1=y | 257 | CONFIG_CACHELINE_ALIGNED_L1=y |
| 243 | CONFIG_SYSCALL_TAB_L1=y | 258 | CONFIG_SYSCALL_TAB_L1=y |
| 244 | CONFIG_CPLB_SWITCH_TAB_L1=y | 259 | CONFIG_CPLB_SWITCH_TAB_L1=y |
| 260 | CONFIG_APP_STACK_L1=y | ||
| 261 | |||
| 262 | # | ||
| 263 | # Speed Optimizations | ||
| 264 | # | ||
| 265 | CONFIG_BFIN_INS_LOWOVERHEAD=y | ||
| 245 | CONFIG_RAMKERNEL=y | 266 | CONFIG_RAMKERNEL=y |
| 246 | # CONFIG_ROMKERNEL is not set | 267 | # CONFIG_ROMKERNEL is not set |
| 247 | CONFIG_SELECT_MEMORY_MODEL=y | 268 | CONFIG_SELECT_MEMORY_MODEL=y |
| @@ -250,14 +271,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 250 | # CONFIG_SPARSEMEM_MANUAL is not set | 271 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 251 | CONFIG_FLATMEM=y | 272 | CONFIG_FLATMEM=y |
| 252 | CONFIG_FLAT_NODE_MEM_MAP=y | 273 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 253 | # CONFIG_SPARSEMEM_STATIC is not set | 274 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 254 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 255 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 275 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 256 | # CONFIG_RESOURCES_64BIT is not set | 276 | # CONFIG_RESOURCES_64BIT is not set |
| 277 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 257 | CONFIG_ZONE_DMA_FLAG=1 | 278 | CONFIG_ZONE_DMA_FLAG=1 |
| 258 | CONFIG_VIRT_TO_BUS=y | 279 | CONFIG_VIRT_TO_BUS=y |
| 259 | # CONFIG_BFIN_GPTIMERS is not set | 280 | # CONFIG_BFIN_GPTIMERS is not set |
| 260 | CONFIG_BFIN_DMA_5XX=y | ||
| 261 | # CONFIG_DMA_UNCACHED_4M is not set | 281 | # CONFIG_DMA_UNCACHED_4M is not set |
| 262 | # CONFIG_DMA_UNCACHED_2M is not set | 282 | # CONFIG_DMA_UNCACHED_2M is not set |
| 263 | CONFIG_DMA_UNCACHED_1M=y | 283 | CONFIG_DMA_UNCACHED_1M=y |
| @@ -300,7 +320,6 @@ CONFIG_BANK_3=0xFFC2 | |||
| 300 | # | 320 | # |
| 301 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) | 321 | # Bus options (PCI, PCMCIA, EISA, MCA, ISA) |
| 302 | # | 322 | # |
| 303 | # CONFIG_PCI is not set | ||
| 304 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 323 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 305 | 324 | ||
| 306 | # | 325 | # |
| @@ -310,23 +329,20 @@ CONFIG_BINFMT_ELF_FDPIC=y | |||
| 310 | CONFIG_BINFMT_FLAT=y | 329 | CONFIG_BINFMT_FLAT=y |
| 311 | CONFIG_BINFMT_ZFLAT=y | 330 | CONFIG_BINFMT_ZFLAT=y |
| 312 | CONFIG_BINFMT_SHARED_FLAT=y | 331 | CONFIG_BINFMT_SHARED_FLAT=y |
| 332 | # CONFIG_HAVE_AOUT is not set | ||
| 313 | # CONFIG_BINFMT_MISC is not set | 333 | # CONFIG_BINFMT_MISC is not set |
| 314 | 334 | ||
| 315 | # | 335 | # |
| 316 | # Power management options | 336 | # Power management options |
| 317 | # | 337 | # |
| 318 | # CONFIG_PM is not set | 338 | # CONFIG_PM is not set |
| 319 | CONFIG_SUSPEND_UP_POSSIBLE=y | 339 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 320 | # CONFIG_PM_WAKEUP_BY_GPIO is not set | 340 | # CONFIG_PM_WAKEUP_BY_GPIO is not set |
| 321 | 341 | ||
| 322 | # | 342 | # |
| 323 | # CPU Frequency scaling | 343 | # CPU Frequency scaling |
| 324 | # | 344 | # |
| 325 | # CONFIG_CPU_FREQ is not set | 345 | # CONFIG_CPU_FREQ is not set |
| 326 | |||
| 327 | # | ||
| 328 | # Networking | ||
| 329 | # | ||
| 330 | # CONFIG_NET is not set | 346 | # CONFIG_NET is not set |
| 331 | 347 | ||
| 332 | # | 348 | # |
| @@ -345,6 +361,7 @@ CONFIG_MTD=y | |||
| 345 | CONFIG_MTD_PARTITIONS=y | 361 | CONFIG_MTD_PARTITIONS=y |
| 346 | # CONFIG_MTD_REDBOOT_PARTS is not set | 362 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 347 | # CONFIG_MTD_CMDLINE_PARTS is not set | 363 | # CONFIG_MTD_CMDLINE_PARTS is not set |
| 364 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 348 | 365 | ||
| 349 | # | 366 | # |
| 350 | # User Modules And Translation Layers | 367 | # User Modules And Translation Layers |
| @@ -362,8 +379,10 @@ CONFIG_MTD_BLOCK=y | |||
| 362 | # | 379 | # |
| 363 | # RAM/ROM/Flash chip drivers | 380 | # RAM/ROM/Flash chip drivers |
| 364 | # | 381 | # |
| 365 | # CONFIG_MTD_CFI is not set | 382 | CONFIG_MTD_CFI=y |
| 366 | # CONFIG_MTD_JEDECPROBE is not set | 383 | # CONFIG_MTD_JEDECPROBE is not set |
| 384 | CONFIG_MTD_GEN_PROBE=y | ||
| 385 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 367 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | 386 | CONFIG_MTD_MAP_BANK_WIDTH_1=y |
| 368 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | 387 | CONFIG_MTD_MAP_BANK_WIDTH_2=y |
| 369 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | 388 | CONFIG_MTD_MAP_BANK_WIDTH_4=y |
| @@ -374,6 +393,10 @@ CONFIG_MTD_CFI_I1=y | |||
| 374 | CONFIG_MTD_CFI_I2=y | 393 | CONFIG_MTD_CFI_I2=y |
| 375 | # CONFIG_MTD_CFI_I4 is not set | 394 | # CONFIG_MTD_CFI_I4 is not set |
| 376 | # CONFIG_MTD_CFI_I8 is not set | 395 | # CONFIG_MTD_CFI_I8 is not set |
| 396 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 397 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 398 | # CONFIG_MTD_CFI_STAA is not set | ||
| 399 | CONFIG_MTD_CFI_UTIL=y | ||
| 377 | CONFIG_MTD_RAM=y | 400 | CONFIG_MTD_RAM=y |
| 378 | # CONFIG_MTD_ROM is not set | 401 | # CONFIG_MTD_ROM is not set |
| 379 | # CONFIG_MTD_ABSENT is not set | 402 | # CONFIG_MTD_ABSENT is not set |
| @@ -381,8 +404,9 @@ CONFIG_MTD_RAM=y | |||
| 381 | # | 404 | # |
| 382 | # Mapping drivers for chip access | 405 | # Mapping drivers for chip access |
| 383 | # | 406 | # |
| 384 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 407 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 385 | # CONFIG_MTD_GPIO_ADDR is not set | 408 | # CONFIG_MTD_PHYSMAP is not set |
| 409 | CONFIG_MTD_GPIO_ADDR=y | ||
| 386 | CONFIG_MTD_UCLINUX=y | 410 | CONFIG_MTD_UCLINUX=y |
| 387 | # CONFIG_MTD_PLATRAM is not set | 411 | # CONFIG_MTD_PLATRAM is not set |
| 388 | 412 | ||
| @@ -416,10 +440,13 @@ CONFIG_BLK_DEV=y | |||
| 416 | CONFIG_BLK_DEV_RAM=y | 440 | CONFIG_BLK_DEV_RAM=y |
| 417 | CONFIG_BLK_DEV_RAM_COUNT=16 | 441 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 418 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 442 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 419 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 443 | # CONFIG_BLK_DEV_XIP is not set |
| 420 | # CONFIG_CDROM_PKTCDVD is not set | 444 | # CONFIG_CDROM_PKTCDVD is not set |
| 445 | # CONFIG_BLK_DEV_HD is not set | ||
| 421 | CONFIG_MISC_DEVICES=y | 446 | CONFIG_MISC_DEVICES=y |
| 422 | # CONFIG_EEPROM_93CX6 is not set | 447 | # CONFIG_EEPROM_93CX6 is not set |
| 448 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 449 | CONFIG_HAVE_IDE=y | ||
| 423 | # CONFIG_IDE is not set | 450 | # CONFIG_IDE is not set |
| 424 | 451 | ||
| 425 | # | 452 | # |
| @@ -454,8 +481,11 @@ CONFIG_MISC_DEVICES=y | |||
| 454 | # CONFIG_BF5xx_PPI is not set | 481 | # CONFIG_BF5xx_PPI is not set |
| 455 | CONFIG_BFIN_SPORT=y | 482 | CONFIG_BFIN_SPORT=y |
| 456 | # CONFIG_BFIN_TIMER_LATENCY is not set | 483 | # CONFIG_BFIN_TIMER_LATENCY is not set |
| 484 | CONFIG_BFIN_DMA_INTERFACE=m | ||
| 457 | # CONFIG_SIMPLE_GPIO is not set | 485 | # CONFIG_SIMPLE_GPIO is not set |
| 458 | # CONFIG_VT is not set | 486 | # CONFIG_VT is not set |
| 487 | # CONFIG_DEVKMEM is not set | ||
| 488 | # CONFIG_BFIN_JTAG_COMM is not set | ||
| 459 | # CONFIG_SERIAL_NONSTANDARD is not set | 489 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 460 | 490 | ||
| 461 | # | 491 | # |
| @@ -486,15 +516,10 @@ CONFIG_UNIX98_PTYS=y | |||
| 486 | # CONFIG_CAN4LINUX is not set | 516 | # CONFIG_CAN4LINUX is not set |
| 487 | # CONFIG_IPMI_HANDLER is not set | 517 | # CONFIG_IPMI_HANDLER is not set |
| 488 | # CONFIG_HW_RANDOM is not set | 518 | # CONFIG_HW_RANDOM is not set |
| 489 | # CONFIG_GEN_RTC is not set | ||
| 490 | # CONFIG_R3964 is not set | 519 | # CONFIG_R3964 is not set |
| 491 | # CONFIG_RAW_DRIVER is not set | 520 | # CONFIG_RAW_DRIVER is not set |
| 492 | # CONFIG_TCG_TPM is not set | 521 | # CONFIG_TCG_TPM is not set |
| 493 | # CONFIG_I2C is not set | 522 | # CONFIG_I2C is not set |
| 494 | |||
| 495 | # | ||
| 496 | # SPI support | ||
| 497 | # | ||
| 498 | CONFIG_SPI=y | 523 | CONFIG_SPI=y |
| 499 | CONFIG_SPI_MASTER=y | 524 | CONFIG_SPI_MASTER=y |
| 500 | 525 | ||
| @@ -502,6 +527,7 @@ CONFIG_SPI_MASTER=y | |||
| 502 | # SPI Master Controller Drivers | 527 | # SPI Master Controller Drivers |
| 503 | # | 528 | # |
| 504 | CONFIG_SPI_BFIN=y | 529 | CONFIG_SPI_BFIN=y |
| 530 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 505 | # CONFIG_SPI_BITBANG is not set | 531 | # CONFIG_SPI_BITBANG is not set |
| 506 | 532 | ||
| 507 | # | 533 | # |
| @@ -510,9 +536,13 @@ CONFIG_SPI_BFIN=y | |||
| 510 | # CONFIG_SPI_AT25 is not set | 536 | # CONFIG_SPI_AT25 is not set |
| 511 | # CONFIG_SPI_SPIDEV is not set | 537 | # CONFIG_SPI_SPIDEV is not set |
| 512 | # CONFIG_SPI_TLE62X0 is not set | 538 | # CONFIG_SPI_TLE62X0 is not set |
| 539 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 540 | # CONFIG_GPIOLIB is not set | ||
| 513 | # CONFIG_W1 is not set | 541 | # CONFIG_W1 is not set |
| 514 | # CONFIG_POWER_SUPPLY is not set | 542 | # CONFIG_POWER_SUPPLY is not set |
| 515 | # CONFIG_HWMON is not set | 543 | # CONFIG_HWMON is not set |
| 544 | # CONFIG_THERMAL is not set | ||
| 545 | # CONFIG_THERMAL_HWMON is not set | ||
| 516 | CONFIG_WATCHDOG=y | 546 | CONFIG_WATCHDOG=y |
| 517 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 547 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 518 | 548 | ||
| @@ -523,20 +553,27 @@ CONFIG_WATCHDOG=y | |||
| 523 | CONFIG_BFIN_WDT=y | 553 | CONFIG_BFIN_WDT=y |
| 524 | 554 | ||
| 525 | # | 555 | # |
| 526 | # Sonics Silicon Backplane | ||
| 527 | # | ||
| 528 | CONFIG_SSB_POSSIBLE=y | ||
| 529 | # CONFIG_SSB is not set | ||
| 530 | |||
| 531 | # | ||
| 532 | # Multifunction device drivers | 556 | # Multifunction device drivers |
| 533 | # | 557 | # |
| 558 | # CONFIG_MFD_CORE is not set | ||
| 534 | # CONFIG_MFD_SM501 is not set | 559 | # CONFIG_MFD_SM501 is not set |
| 560 | # CONFIG_HTC_PASIC3 is not set | ||
| 561 | # CONFIG_MFD_TMIO is not set | ||
| 562 | # CONFIG_MFD_WM8400 is not set | ||
| 535 | 563 | ||
| 536 | # | 564 | # |
| 537 | # Multimedia devices | 565 | # Multimedia devices |
| 538 | # | 566 | # |
| 567 | |||
| 568 | # | ||
| 569 | # Multimedia core support | ||
| 570 | # | ||
| 539 | # CONFIG_VIDEO_DEV is not set | 571 | # CONFIG_VIDEO_DEV is not set |
| 572 | # CONFIG_VIDEO_MEDIA is not set | ||
| 573 | |||
| 574 | # | ||
| 575 | # Multimedia drivers | ||
| 576 | # | ||
| 540 | # CONFIG_DAB is not set | 577 | # CONFIG_DAB is not set |
| 541 | 578 | ||
| 542 | # | 579 | # |
| @@ -551,20 +588,16 @@ CONFIG_SSB_POSSIBLE=y | |||
| 551 | # Display device support | 588 | # Display device support |
| 552 | # | 589 | # |
| 553 | # CONFIG_DISPLAY_SUPPORT is not set | 590 | # CONFIG_DISPLAY_SUPPORT is not set |
| 554 | |||
| 555 | # | ||
| 556 | # Sound | ||
| 557 | # | ||
| 558 | # CONFIG_SOUND is not set | 591 | # CONFIG_SOUND is not set |
| 559 | # CONFIG_USB_SUPPORT is not set | 592 | # CONFIG_USB_SUPPORT is not set |
| 560 | # CONFIG_MMC is not set | 593 | # CONFIG_MMC is not set |
| 594 | # CONFIG_MEMSTICK is not set | ||
| 561 | # CONFIG_NEW_LEDS is not set | 595 | # CONFIG_NEW_LEDS is not set |
| 596 | # CONFIG_ACCESSIBILITY is not set | ||
| 562 | # CONFIG_RTC_CLASS is not set | 597 | # CONFIG_RTC_CLASS is not set |
| 563 | 598 | # CONFIG_DMADEVICES is not set | |
| 564 | # | ||
| 565 | # Userspace I/O | ||
| 566 | # | ||
| 567 | # CONFIG_UIO is not set | 599 | # CONFIG_UIO is not set |
| 600 | # CONFIG_STAGING is not set | ||
| 568 | 601 | ||
| 569 | # | 602 | # |
| 570 | # File systems | 603 | # File systems |
| @@ -574,19 +607,17 @@ CONFIG_EXT2_FS_XATTR=y | |||
| 574 | # CONFIG_EXT2_FS_POSIX_ACL is not set | 607 | # CONFIG_EXT2_FS_POSIX_ACL is not set |
| 575 | # CONFIG_EXT2_FS_SECURITY is not set | 608 | # CONFIG_EXT2_FS_SECURITY is not set |
| 576 | # CONFIG_EXT3_FS is not set | 609 | # CONFIG_EXT3_FS is not set |
| 577 | # CONFIG_EXT4DEV_FS is not set | 610 | # CONFIG_EXT4_FS is not set |
| 578 | CONFIG_FS_MBCACHE=y | 611 | CONFIG_FS_MBCACHE=y |
| 579 | # CONFIG_REISERFS_FS is not set | 612 | # CONFIG_REISERFS_FS is not set |
| 580 | # CONFIG_JFS_FS is not set | 613 | # CONFIG_JFS_FS is not set |
| 581 | # CONFIG_FS_POSIX_ACL is not set | 614 | # CONFIG_FS_POSIX_ACL is not set |
| 615 | CONFIG_FILE_LOCKING=y | ||
| 582 | # CONFIG_XFS_FS is not set | 616 | # CONFIG_XFS_FS is not set |
| 583 | # CONFIG_GFS2_FS is not set | 617 | # CONFIG_DNOTIFY is not set |
| 584 | # CONFIG_MINIX_FS is not set | ||
| 585 | # CONFIG_ROMFS_FS is not set | ||
| 586 | CONFIG_INOTIFY=y | 618 | CONFIG_INOTIFY=y |
| 587 | CONFIG_INOTIFY_USER=y | 619 | CONFIG_INOTIFY_USER=y |
| 588 | # CONFIG_QUOTA is not set | 620 | # CONFIG_QUOTA is not set |
| 589 | # CONFIG_DNOTIFY is not set | ||
| 590 | # CONFIG_AUTOFS_FS is not set | 621 | # CONFIG_AUTOFS_FS is not set |
| 591 | # CONFIG_AUTOFS4_FS is not set | 622 | # CONFIG_AUTOFS4_FS is not set |
| 592 | # CONFIG_FUSE_FS is not set | 623 | # CONFIG_FUSE_FS is not set |
| @@ -628,8 +659,11 @@ CONFIG_SYSFS=y | |||
| 628 | # CONFIG_JFFS2_FS is not set | 659 | # CONFIG_JFFS2_FS is not set |
| 629 | # CONFIG_CRAMFS is not set | 660 | # CONFIG_CRAMFS is not set |
| 630 | # CONFIG_VXFS_FS is not set | 661 | # CONFIG_VXFS_FS is not set |
| 662 | # CONFIG_MINIX_FS is not set | ||
| 663 | # CONFIG_OMFS_FS is not set | ||
| 631 | # CONFIG_HPFS_FS is not set | 664 | # CONFIG_HPFS_FS is not set |
| 632 | # CONFIG_QNX4FS_FS is not set | 665 | # CONFIG_QNX4FS_FS is not set |
| 666 | # CONFIG_ROMFS_FS is not set | ||
| 633 | # CONFIG_SYSV_FS is not set | 667 | # CONFIG_SYSV_FS is not set |
| 634 | # CONFIG_UFS_FS is not set | 668 | # CONFIG_UFS_FS is not set |
| 635 | 669 | ||
| @@ -639,7 +673,6 @@ CONFIG_SYSFS=y | |||
| 639 | # CONFIG_PARTITION_ADVANCED is not set | 673 | # CONFIG_PARTITION_ADVANCED is not set |
| 640 | CONFIG_MSDOS_PARTITION=y | 674 | CONFIG_MSDOS_PARTITION=y |
| 641 | # CONFIG_NLS is not set | 675 | # CONFIG_NLS is not set |
| 642 | # CONFIG_INSTRUMENTATION is not set | ||
| 643 | 676 | ||
| 644 | # | 677 | # |
| 645 | # Kernel hacking | 678 | # Kernel hacking |
| @@ -647,14 +680,22 @@ CONFIG_MSDOS_PARTITION=y | |||
| 647 | # CONFIG_PRINTK_TIME is not set | 680 | # CONFIG_PRINTK_TIME is not set |
| 648 | CONFIG_ENABLE_WARN_DEPRECATED=y | 681 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 649 | CONFIG_ENABLE_MUST_CHECK=y | 682 | CONFIG_ENABLE_MUST_CHECK=y |
| 683 | CONFIG_FRAME_WARN=1024 | ||
| 650 | # CONFIG_MAGIC_SYSRQ is not set | 684 | # CONFIG_MAGIC_SYSRQ is not set |
| 651 | # CONFIG_UNUSED_SYMBOLS is not set | 685 | # CONFIG_UNUSED_SYMBOLS is not set |
| 652 | CONFIG_DEBUG_FS=y | 686 | CONFIG_DEBUG_FS=y |
| 653 | # CONFIG_HEADERS_CHECK is not set | 687 | # CONFIG_HEADERS_CHECK is not set |
| 654 | # CONFIG_DEBUG_KERNEL is not set | 688 | # CONFIG_DEBUG_KERNEL is not set |
| 655 | # CONFIG_DEBUG_BUGVERBOSE is not set | 689 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 690 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 691 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 692 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 693 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 656 | # CONFIG_SAMPLES is not set | 694 | # CONFIG_SAMPLES is not set |
| 695 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 696 | CONFIG_DEBUG_VERBOSE=y | ||
| 657 | CONFIG_DEBUG_MMRS=y | 697 | CONFIG_DEBUG_MMRS=y |
| 698 | # CONFIG_DEBUG_DOUBLEFAULT is not set | ||
| 658 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 699 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 659 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 700 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| 660 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y | 701 | CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y |
| @@ -671,9 +712,8 @@ CONFIG_ACCESS_CHECK=y | |||
| 671 | # Security options | 712 | # Security options |
| 672 | # | 713 | # |
| 673 | # CONFIG_KEYS is not set | 714 | # CONFIG_KEYS is not set |
| 674 | CONFIG_SECURITY=y | 715 | # CONFIG_SECURITY is not set |
| 675 | # CONFIG_SECURITY_NETWORK is not set | 716 | # CONFIG_SECURITYFS is not set |
| 676 | CONFIG_SECURITY_CAPABILITIES=y | ||
| 677 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 717 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 678 | # CONFIG_CRYPTO is not set | 718 | # CONFIG_CRYPTO is not set |
| 679 | 719 | ||
| @@ -682,6 +722,7 @@ CONFIG_SECURITY_CAPABILITIES=y | |||
| 682 | # | 722 | # |
| 683 | # CONFIG_CRC_CCITT is not set | 723 | # CONFIG_CRC_CCITT is not set |
| 684 | # CONFIG_CRC16 is not set | 724 | # CONFIG_CRC16 is not set |
| 725 | # CONFIG_CRC_T10DIF is not set | ||
| 685 | # CONFIG_CRC_ITU_T is not set | 726 | # CONFIG_CRC_ITU_T is not set |
| 686 | # CONFIG_CRC32 is not set | 727 | # CONFIG_CRC32 is not set |
| 687 | # CONFIG_CRC7 is not set | 728 | # CONFIG_CRC7 is not set |
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h index 25776c19064b..94b2a9b19451 100644 --- a/arch/blackfin/include/asm/atomic.h +++ b/arch/blackfin/include/asm/atomic.h | |||
| @@ -15,104 +15,159 @@ | |||
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #define ATOMIC_INIT(i) { (i) } | 17 | #define ATOMIC_INIT(i) { (i) } |
| 18 | |||
| 19 | #define atomic_read(v) ((v)->counter) | ||
| 20 | #define atomic_set(v, i) (((v)->counter) = i) | 18 | #define atomic_set(v, i) (((v)->counter) = i) |
| 21 | 19 | ||
| 22 | static __inline__ void atomic_add(int i, atomic_t * v) | 20 | #ifdef CONFIG_SMP |
| 21 | |||
| 22 | #define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter) | ||
| 23 | |||
| 24 | asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr); | ||
| 25 | |||
| 26 | asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value); | ||
| 27 | |||
| 28 | asmlinkage int __raw_atomic_clear_asm(volatile int *ptr, int value); | ||
| 29 | |||
| 30 | asmlinkage int __raw_atomic_set_asm(volatile int *ptr, int value); | ||
| 31 | |||
| 32 | asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value); | ||
| 33 | |||
| 34 | asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value); | ||
| 35 | |||
| 36 | static inline void atomic_add(int i, atomic_t *v) | ||
| 37 | { | ||
| 38 | __raw_atomic_update_asm(&v->counter, i); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void atomic_sub(int i, atomic_t *v) | ||
| 42 | { | ||
| 43 | __raw_atomic_update_asm(&v->counter, -i); | ||
| 44 | } | ||
| 45 | |||
| 46 | static inline int atomic_add_return(int i, atomic_t *v) | ||
| 47 | { | ||
| 48 | return __raw_atomic_update_asm(&v->counter, i); | ||
| 49 | } | ||
| 50 | |||
| 51 | static inline int atomic_sub_return(int i, atomic_t *v) | ||
| 52 | { | ||
| 53 | return __raw_atomic_update_asm(&v->counter, -i); | ||
| 54 | } | ||
| 55 | |||
| 56 | static inline void atomic_inc(volatile atomic_t *v) | ||
| 57 | { | ||
| 58 | __raw_atomic_update_asm(&v->counter, 1); | ||
| 59 | } | ||
| 60 | |||
| 61 | static inline void atomic_dec(volatile atomic_t *v) | ||
| 62 | { | ||
| 63 | __raw_atomic_update_asm(&v->counter, -1); | ||
| 64 | } | ||
| 65 | |||
| 66 | static inline void atomic_clear_mask(int mask, atomic_t *v) | ||
| 67 | { | ||
| 68 | __raw_atomic_clear_asm(&v->counter, mask); | ||
| 69 | } | ||
| 70 | |||
| 71 | static inline void atomic_set_mask(int mask, atomic_t *v) | ||
| 72 | { | ||
| 73 | __raw_atomic_set_asm(&v->counter, mask); | ||
| 74 | } | ||
| 75 | |||
| 76 | static inline int atomic_test_mask(int mask, atomic_t *v) | ||
| 77 | { | ||
| 78 | return __raw_atomic_test_asm(&v->counter, mask); | ||
| 79 | } | ||
| 80 | |||
| 81 | /* Atomic operations are already serializing */ | ||
| 82 | #define smp_mb__before_atomic_dec() barrier() | ||
| 83 | #define smp_mb__after_atomic_dec() barrier() | ||
| 84 | #define smp_mb__before_atomic_inc() barrier() | ||
| 85 | #define smp_mb__after_atomic_inc() barrier() | ||
| 86 | |||
| 87 | #else /* !CONFIG_SMP */ | ||
| 88 | |||
| 89 | #define atomic_read(v) ((v)->counter) | ||
| 90 | |||
| 91 | static inline void atomic_add(int i, atomic_t *v) | ||
| 23 | { | 92 | { |
| 24 | long flags; | 93 | long flags; |
| 25 | 94 | ||
| 26 | local_irq_save(flags); | 95 | local_irq_save_hw(flags); |
| 27 | v->counter += i; | 96 | v->counter += i; |
| 28 | local_irq_restore(flags); | 97 | local_irq_restore_hw(flags); |
| 29 | } | 98 | } |
| 30 | 99 | ||
| 31 | static __inline__ void atomic_sub(int i, atomic_t * v) | 100 | static inline void atomic_sub(int i, atomic_t *v) |
| 32 | { | 101 | { |
| 33 | long flags; | 102 | long flags; |
| 34 | 103 | ||
| 35 | local_irq_save(flags); | 104 | local_irq_save_hw(flags); |
| 36 | v->counter -= i; | 105 | v->counter -= i; |
| 37 | local_irq_restore(flags); | 106 | local_irq_restore_hw(flags); |
| 38 | 107 | ||
| 39 | } | 108 | } |
| 40 | 109 | ||
| 41 | static inline int atomic_add_return(int i, atomic_t * v) | 110 | static inline int atomic_add_return(int i, atomic_t *v) |
| 42 | { | 111 | { |
| 43 | int __temp = 0; | 112 | int __temp = 0; |
| 44 | long flags; | 113 | long flags; |
| 45 | 114 | ||
| 46 | local_irq_save(flags); | 115 | local_irq_save_hw(flags); |
| 47 | v->counter += i; | 116 | v->counter += i; |
| 48 | __temp = v->counter; | 117 | __temp = v->counter; |
| 49 | local_irq_restore(flags); | 118 | local_irq_restore_hw(flags); |
| 50 | 119 | ||
| 51 | 120 | ||
| 52 | return __temp; | 121 | return __temp; |
| 53 | } | 122 | } |
| 54 | 123 | ||
| 55 | #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) | 124 | static inline int atomic_sub_return(int i, atomic_t *v) |
| 56 | static inline int atomic_sub_return(int i, atomic_t * v) | ||
| 57 | { | 125 | { |
| 58 | int __temp = 0; | 126 | int __temp = 0; |
| 59 | long flags; | 127 | long flags; |
| 60 | 128 | ||
| 61 | local_irq_save(flags); | 129 | local_irq_save_hw(flags); |
| 62 | v->counter -= i; | 130 | v->counter -= i; |
| 63 | __temp = v->counter; | 131 | __temp = v->counter; |
| 64 | local_irq_restore(flags); | 132 | local_irq_restore_hw(flags); |
| 65 | 133 | ||
| 66 | return __temp; | 134 | return __temp; |
| 67 | } | 135 | } |
| 68 | 136 | ||
| 69 | static __inline__ void atomic_inc(volatile atomic_t * v) | 137 | static inline void atomic_inc(volatile atomic_t *v) |
| 70 | { | 138 | { |
| 71 | long flags; | 139 | long flags; |
| 72 | 140 | ||
| 73 | local_irq_save(flags); | 141 | local_irq_save_hw(flags); |
| 74 | v->counter++; | 142 | v->counter++; |
| 75 | local_irq_restore(flags); | 143 | local_irq_restore_hw(flags); |
| 76 | } | 144 | } |
| 77 | 145 | ||
| 78 | #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) | 146 | static inline void atomic_dec(volatile atomic_t *v) |
| 79 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | ||
| 80 | |||
| 81 | #define atomic_add_unless(v, a, u) \ | ||
| 82 | ({ \ | ||
| 83 | int c, old; \ | ||
| 84 | c = atomic_read(v); \ | ||
| 85 | while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \ | ||
| 86 | c = old; \ | ||
| 87 | c != (u); \ | ||
| 88 | }) | ||
| 89 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) | ||
| 90 | |||
| 91 | static __inline__ void atomic_dec(volatile atomic_t * v) | ||
| 92 | { | 147 | { |
| 93 | long flags; | 148 | long flags; |
| 94 | 149 | ||
| 95 | local_irq_save(flags); | 150 | local_irq_save_hw(flags); |
| 96 | v->counter--; | 151 | v->counter--; |
| 97 | local_irq_restore(flags); | 152 | local_irq_restore_hw(flags); |
| 98 | } | 153 | } |
| 99 | 154 | ||
| 100 | static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v) | 155 | static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) |
| 101 | { | 156 | { |
| 102 | long flags; | 157 | long flags; |
| 103 | 158 | ||
| 104 | local_irq_save(flags); | 159 | local_irq_save_hw(flags); |
| 105 | v->counter &= ~mask; | 160 | v->counter &= ~mask; |
| 106 | local_irq_restore(flags); | 161 | local_irq_restore_hw(flags); |
| 107 | } | 162 | } |
| 108 | 163 | ||
| 109 | static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v) | 164 | static inline void atomic_set_mask(unsigned int mask, atomic_t *v) |
| 110 | { | 165 | { |
| 111 | long flags; | 166 | long flags; |
| 112 | 167 | ||
| 113 | local_irq_save(flags); | 168 | local_irq_save_hw(flags); |
| 114 | v->counter |= mask; | 169 | v->counter |= mask; |
| 115 | local_irq_restore(flags); | 170 | local_irq_restore_hw(flags); |
| 116 | } | 171 | } |
| 117 | 172 | ||
| 118 | /* Atomic operations are already serializing */ | 173 | /* Atomic operations are already serializing */ |
| @@ -121,9 +176,25 @@ static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v) | |||
| 121 | #define smp_mb__before_atomic_inc() barrier() | 176 | #define smp_mb__before_atomic_inc() barrier() |
| 122 | #define smp_mb__after_atomic_inc() barrier() | 177 | #define smp_mb__after_atomic_inc() barrier() |
| 123 | 178 | ||
| 179 | #endif /* !CONFIG_SMP */ | ||
| 180 | |||
| 181 | #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) | ||
| 124 | #define atomic_dec_return(v) atomic_sub_return(1,(v)) | 182 | #define atomic_dec_return(v) atomic_sub_return(1,(v)) |
| 125 | #define atomic_inc_return(v) atomic_add_return(1,(v)) | 183 | #define atomic_inc_return(v) atomic_add_return(1,(v)) |
| 126 | 184 | ||
| 185 | #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) | ||
| 186 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | ||
| 187 | |||
| 188 | #define atomic_add_unless(v, a, u) \ | ||
| 189 | ({ \ | ||
| 190 | int c, old; \ | ||
| 191 | c = atomic_read(v); \ | ||
| 192 | while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \ | ||
| 193 | c = old; \ | ||
| 194 | c != (u); \ | ||
| 195 | }) | ||
| 196 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) | ||
| 197 | |||
| 127 | /* | 198 | /* |
| 128 | * atomic_inc_and_test - increment and test | 199 | * atomic_inc_and_test - increment and test |
| 129 | * @v: pointer of type atomic_t | 200 | * @v: pointer of type atomic_t |
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h index 77295666c34b..daffc0684e75 100644 --- a/arch/blackfin/include/asm/bfin-global.h +++ b/arch/blackfin/include/asm/bfin-global.h | |||
| @@ -47,6 +47,9 @@ | |||
| 47 | # define DMA_UNCACHED_REGION (0) | 47 | # define DMA_UNCACHED_REGION (0) |
| 48 | #endif | 48 | #endif |
| 49 | 49 | ||
| 50 | extern void bfin_setup_caches(unsigned int cpu); | ||
| 51 | extern void bfin_setup_cpudata(unsigned int cpu); | ||
| 52 | |||
| 50 | extern unsigned long get_cclk(void); | 53 | extern unsigned long get_cclk(void); |
| 51 | extern unsigned long get_sclk(void); | 54 | extern unsigned long get_sclk(void); |
| 52 | extern unsigned long sclk_to_usecs(unsigned long sclk); | 55 | extern unsigned long sclk_to_usecs(unsigned long sclk); |
| @@ -58,8 +61,6 @@ extern void dump_bfin_trace_buffer(void); | |||
| 58 | 61 | ||
| 59 | /* init functions only */ | 62 | /* init functions only */ |
| 60 | extern int init_arch_irq(void); | 63 | extern int init_arch_irq(void); |
| 61 | extern void bfin_icache_init(void); | ||
| 62 | extern void bfin_dcache_init(void); | ||
| 63 | extern void init_exception_vectors(void); | 64 | extern void init_exception_vectors(void); |
| 64 | extern void program_IAR(void); | 65 | extern void program_IAR(void); |
| 65 | 66 | ||
| @@ -110,7 +111,7 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; | |||
| 110 | 111 | ||
| 111 | #ifdef CONFIG_BFIN_ICACHE_LOCK | 112 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
| 112 | extern void cache_grab_lock(int way); | 113 | extern void cache_grab_lock(int way); |
| 113 | extern void cache_lock(int way); | 114 | extern void bfin_cache_lock(int way); |
| 114 | #endif | 115 | #endif |
| 115 | 116 | ||
| 116 | #endif | 117 | #endif |
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h index 9fa19158e38d..1306e6b22946 100644 --- a/arch/blackfin/include/asm/bfin5xx_spi.h +++ b/arch/blackfin/include/asm/bfin5xx_spi.h | |||
| @@ -1,22 +1,12 @@ | |||
| 1 | /************************************************************ | 1 | /* |
| 2 | 2 | * Blackfin On-Chip SPI Driver | |
| 3 | * Copyright (C) 2006-2008, Analog Devices. All Rights Reserved | 3 | * |
| 4 | * | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 5 | * FILE bfin5xx_spi.h | 5 | * |
| 6 | * PROGRAMMER(S): Luke Yang (Analog Devices Inc.) | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
| 7 | * | 7 | * |
| 8 | * | 8 | * Licensed under the GPL-2 or later. |
| 9 | * DATE OF CREATION: March. 10th 2006 | 9 | */ |
| 10 | * | ||
| 11 | * SYNOPSIS: | ||
| 12 | * | ||
| 13 | * DESCRIPTION: header file for SPI controller driver for Blackfin5xx. | ||
| 14 | ************************************************************** | ||
| 15 | |||
| 16 | * MODIFICATION HISTORY: | ||
| 17 | * March 10, 2006 bfin5xx_spi.h Created. (Luke Yang) | ||
| 18 | |||
| 19 | ************************************************************/ | ||
| 20 | 10 | ||
| 21 | #ifndef _SPI_CHANNEL_H_ | 11 | #ifndef _SPI_CHANNEL_H_ |
| 22 | #define _SPI_CHANNEL_H_ | 12 | #define _SPI_CHANNEL_H_ |
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h new file mode 100644 index 000000000000..d61d5497c590 --- /dev/null +++ b/arch/blackfin/include/asm/bfin_sdh.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * bfin_sdh.h - Blackfin SDH definitions | ||
| 3 | * | ||
| 4 | * Copyright 2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __BFIN_SDH_H__ | ||
| 10 | #define __BFIN_SDH_H__ | ||
| 11 | |||
| 12 | struct bfin_sd_host { | ||
| 13 | int dma_chan; | ||
| 14 | int irq_int0; | ||
| 15 | int irq_int1; | ||
| 16 | u16 pin_req[7]; | ||
| 17 | }; | ||
| 18 | |||
| 19 | #endif | ||
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h index c76ed8def302..fe88a2c19213 100644 --- a/arch/blackfin/include/asm/bfin_sport.h +++ b/arch/blackfin/include/asm/bfin_sport.h | |||
| @@ -120,9 +120,6 @@ struct sport_register { | |||
| 120 | #define SPORT_IOC_MAGIC 'P' | 120 | #define SPORT_IOC_MAGIC 'P' |
| 121 | #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) | 121 | #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) |
| 122 | 122 | ||
| 123 | /* Test purpose */ | ||
| 124 | #define ENABLE_AD73311 _IOWR('P', 0x02, int) | ||
| 125 | |||
| 126 | struct sport_dev { | 123 | struct sport_dev { |
| 127 | struct cdev cdev; /* Char device structure */ | 124 | struct cdev cdev; /* Char device structure */ |
| 128 | 125 | ||
diff --git a/arch/blackfin/include/asm/bfrom.h b/arch/blackfin/include/asm/bfrom.h index cfe8024c3b2f..9e4be5e5e767 100644 --- a/arch/blackfin/include/asm/bfrom.h +++ b/arch/blackfin/include/asm/bfrom.h | |||
| @@ -43,6 +43,11 @@ __attribute__((__noreturn__)) | |||
| 43 | static inline void bfrom_SoftReset(void *new_stack) | 43 | static inline void bfrom_SoftReset(void *new_stack) |
| 44 | { | 44 | { |
| 45 | while (1) | 45 | while (1) |
| 46 | /* | ||
| 47 | * We don't declare the SP as clobbered on purpose, since | ||
| 48 | * it confuses the heck out of the compiler, and this function | ||
| 49 | * never returns | ||
| 50 | */ | ||
| 46 | __asm__ __volatile__( | 51 | __asm__ __volatile__( |
| 47 | "sp = %[stack];" | 52 | "sp = %[stack];" |
| 48 | "jump (%[bfrom_syscontrol]);" | 53 | "jump (%[bfrom_syscontrol]);" |
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index c428e4106f89..21b036eadab1 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h | |||
| @@ -7,7 +7,6 @@ | |||
| 7 | 7 | ||
| 8 | #include <linux/compiler.h> | 8 | #include <linux/compiler.h> |
| 9 | #include <asm/byteorder.h> /* swab32 */ | 9 | #include <asm/byteorder.h> /* swab32 */ |
| 10 | #include <asm/system.h> /* save_flags */ | ||
| 11 | 10 | ||
| 12 | #ifdef __KERNEL__ | 11 | #ifdef __KERNEL__ |
| 13 | 12 | ||
| @@ -20,80 +19,107 @@ | |||
| 20 | #include <asm-generic/bitops/sched.h> | 19 | #include <asm-generic/bitops/sched.h> |
| 21 | #include <asm-generic/bitops/ffz.h> | 20 | #include <asm-generic/bitops/ffz.h> |
| 22 | 21 | ||
| 23 | static __inline__ void set_bit(int nr, volatile unsigned long *addr) | 22 | #ifdef CONFIG_SMP |
| 23 | |||
| 24 | #include <linux/linkage.h> | ||
| 25 | |||
| 26 | asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr); | ||
| 27 | |||
| 28 | asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr); | ||
| 29 | |||
| 30 | asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr); | ||
| 31 | |||
| 32 | asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr); | ||
| 33 | |||
| 34 | asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr); | ||
| 35 | |||
| 36 | asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr); | ||
| 37 | |||
| 38 | asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr); | ||
| 39 | |||
| 40 | static inline void set_bit(int nr, volatile unsigned long *addr) | ||
| 24 | { | 41 | { |
| 25 | int *a = (int *)addr; | 42 | volatile unsigned long *a = addr + (nr >> 5); |
| 26 | int mask; | 43 | __raw_bit_set_asm(a, nr & 0x1f); |
| 27 | unsigned long flags; | 44 | } |
| 28 | 45 | ||
| 29 | a += nr >> 5; | 46 | static inline void clear_bit(int nr, volatile unsigned long *addr) |
| 30 | mask = 1 << (nr & 0x1f); | 47 | { |
| 31 | local_irq_save(flags); | 48 | volatile unsigned long *a = addr + (nr >> 5); |
| 32 | *a |= mask; | 49 | __raw_bit_clear_asm(a, nr & 0x1f); |
| 33 | local_irq_restore(flags); | ||
| 34 | } | 50 | } |
| 35 | 51 | ||
| 36 | static __inline__ void __set_bit(int nr, volatile unsigned long *addr) | 52 | static inline void change_bit(int nr, volatile unsigned long *addr) |
| 37 | { | 53 | { |
| 38 | int *a = (int *)addr; | 54 | volatile unsigned long *a = addr + (nr >> 5); |
| 39 | int mask; | 55 | __raw_bit_toggle_asm(a, nr & 0x1f); |
| 56 | } | ||
| 40 | 57 | ||
| 41 | a += nr >> 5; | 58 | static inline int test_bit(int nr, const volatile unsigned long *addr) |
| 42 | mask = 1 << (nr & 0x1f); | 59 | { |
| 43 | *a |= mask; | 60 | volatile const unsigned long *a = addr + (nr >> 5); |
| 61 | return __raw_bit_test_asm(a, nr & 0x1f) != 0; | ||
| 44 | } | 62 | } |
| 45 | 63 | ||
| 46 | /* | 64 | static inline int test_and_set_bit(int nr, volatile unsigned long *addr) |
| 47 | * clear_bit() doesn't provide any barrier for the compiler. | 65 | { |
| 48 | */ | 66 | volatile unsigned long *a = addr + (nr >> 5); |
| 49 | #define smp_mb__before_clear_bit() barrier() | 67 | return __raw_bit_test_set_asm(a, nr & 0x1f); |
| 50 | #define smp_mb__after_clear_bit() barrier() | 68 | } |
| 69 | |||
| 70 | static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) | ||
| 71 | { | ||
| 72 | volatile unsigned long *a = addr + (nr >> 5); | ||
| 73 | return __raw_bit_test_clear_asm(a, nr & 0x1f); | ||
| 74 | } | ||
| 75 | |||
| 76 | static inline int test_and_change_bit(int nr, volatile unsigned long *addr) | ||
| 77 | { | ||
| 78 | volatile unsigned long *a = addr + (nr >> 5); | ||
| 79 | return __raw_bit_test_toggle_asm(a, nr & 0x1f); | ||
| 80 | } | ||
| 81 | |||
| 82 | #else /* !CONFIG_SMP */ | ||
| 83 | |||
| 84 | #include <asm/system.h> /* save_flags */ | ||
| 51 | 85 | ||
| 52 | static __inline__ void clear_bit(int nr, volatile unsigned long *addr) | 86 | static inline void set_bit(int nr, volatile unsigned long *addr) |
| 53 | { | 87 | { |
| 54 | int *a = (int *)addr; | 88 | int *a = (int *)addr; |
| 55 | int mask; | 89 | int mask; |
| 56 | unsigned long flags; | 90 | unsigned long flags; |
| 57 | a += nr >> 5; | 91 | a += nr >> 5; |
| 58 | mask = 1 << (nr & 0x1f); | 92 | mask = 1 << (nr & 0x1f); |
| 59 | local_irq_save(flags); | 93 | local_irq_save_hw(flags); |
| 60 | *a &= ~mask; | 94 | *a |= mask; |
| 61 | local_irq_restore(flags); | 95 | local_irq_restore_hw(flags); |
| 62 | } | 96 | } |
| 63 | 97 | ||
| 64 | static __inline__ void __clear_bit(int nr, volatile unsigned long *addr) | 98 | static inline void clear_bit(int nr, volatile unsigned long *addr) |
| 65 | { | 99 | { |
| 66 | int *a = (int *)addr; | 100 | int *a = (int *)addr; |
| 67 | int mask; | 101 | int mask; |
| 68 | 102 | unsigned long flags; | |
| 69 | a += nr >> 5; | 103 | a += nr >> 5; |
| 70 | mask = 1 << (nr & 0x1f); | 104 | mask = 1 << (nr & 0x1f); |
| 105 | local_irq_save_hw(flags); | ||
| 71 | *a &= ~mask; | 106 | *a &= ~mask; |
| 107 | local_irq_restore_hw(flags); | ||
| 72 | } | 108 | } |
| 73 | 109 | ||
| 74 | static __inline__ void change_bit(int nr, volatile unsigned long *addr) | 110 | static inline void change_bit(int nr, volatile unsigned long *addr) |
| 75 | { | 111 | { |
| 76 | int mask, flags; | 112 | int mask, flags; |
| 77 | unsigned long *ADDR = (unsigned long *)addr; | 113 | unsigned long *ADDR = (unsigned long *)addr; |
| 78 | 114 | ||
| 79 | ADDR += nr >> 5; | 115 | ADDR += nr >> 5; |
| 80 | mask = 1 << (nr & 31); | 116 | mask = 1 << (nr & 31); |
| 81 | local_irq_save(flags); | 117 | local_irq_save_hw(flags); |
| 82 | *ADDR ^= mask; | ||
| 83 | local_irq_restore(flags); | ||
| 84 | } | ||
| 85 | |||
| 86 | static __inline__ void __change_bit(int nr, volatile unsigned long *addr) | ||
| 87 | { | ||
| 88 | int mask; | ||
| 89 | unsigned long *ADDR = (unsigned long *)addr; | ||
| 90 | |||
| 91 | ADDR += nr >> 5; | ||
| 92 | mask = 1 << (nr & 31); | ||
| 93 | *ADDR ^= mask; | 118 | *ADDR ^= mask; |
| 119 | local_irq_restore_hw(flags); | ||
| 94 | } | 120 | } |
| 95 | 121 | ||
| 96 | static __inline__ int test_and_set_bit(int nr, void *addr) | 122 | static inline int test_and_set_bit(int nr, volatile unsigned long *addr) |
| 97 | { | 123 | { |
| 98 | int mask, retval; | 124 | int mask, retval; |
| 99 | volatile unsigned int *a = (volatile unsigned int *)addr; | 125 | volatile unsigned int *a = (volatile unsigned int *)addr; |
| @@ -101,27 +127,31 @@ static __inline__ int test_and_set_bit(int nr, void *addr) | |||
| 101 | 127 | ||
| 102 | a += nr >> 5; | 128 | a += nr >> 5; |
| 103 | mask = 1 << (nr & 0x1f); | 129 | mask = 1 << (nr & 0x1f); |
| 104 | local_irq_save(flags); | 130 | local_irq_save_hw(flags); |
| 105 | retval = (mask & *a) != 0; | 131 | retval = (mask & *a) != 0; |
| 106 | *a |= mask; | 132 | *a |= mask; |
| 107 | local_irq_restore(flags); | 133 | local_irq_restore_hw(flags); |
| 108 | 134 | ||
| 109 | return retval; | 135 | return retval; |
| 110 | } | 136 | } |
| 111 | 137 | ||
| 112 | static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr) | 138 | static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) |
| 113 | { | 139 | { |
| 114 | int mask, retval; | 140 | int mask, retval; |
| 115 | volatile unsigned int *a = (volatile unsigned int *)addr; | 141 | volatile unsigned int *a = (volatile unsigned int *)addr; |
| 142 | unsigned long flags; | ||
| 116 | 143 | ||
| 117 | a += nr >> 5; | 144 | a += nr >> 5; |
| 118 | mask = 1 << (nr & 0x1f); | 145 | mask = 1 << (nr & 0x1f); |
| 146 | local_irq_save_hw(flags); | ||
| 119 | retval = (mask & *a) != 0; | 147 | retval = (mask & *a) != 0; |
| 120 | *a |= mask; | 148 | *a &= ~mask; |
| 149 | local_irq_restore_hw(flags); | ||
| 150 | |||
| 121 | return retval; | 151 | return retval; |
| 122 | } | 152 | } |
| 123 | 153 | ||
| 124 | static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr) | 154 | static inline int test_and_change_bit(int nr, volatile unsigned long *addr) |
| 125 | { | 155 | { |
| 126 | int mask, retval; | 156 | int mask, retval; |
| 127 | volatile unsigned int *a = (volatile unsigned int *)addr; | 157 | volatile unsigned int *a = (volatile unsigned int *)addr; |
| @@ -129,15 +159,52 @@ static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr) | |||
| 129 | 159 | ||
| 130 | a += nr >> 5; | 160 | a += nr >> 5; |
| 131 | mask = 1 << (nr & 0x1f); | 161 | mask = 1 << (nr & 0x1f); |
| 132 | local_irq_save(flags); | 162 | local_irq_save_hw(flags); |
| 133 | retval = (mask & *a) != 0; | 163 | retval = (mask & *a) != 0; |
| 164 | *a ^= mask; | ||
| 165 | local_irq_restore_hw(flags); | ||
| 166 | return retval; | ||
| 167 | } | ||
| 168 | |||
| 169 | #endif /* CONFIG_SMP */ | ||
| 170 | |||
| 171 | /* | ||
| 172 | * clear_bit() doesn't provide any barrier for the compiler. | ||
| 173 | */ | ||
| 174 | #define smp_mb__before_clear_bit() barrier() | ||
| 175 | #define smp_mb__after_clear_bit() barrier() | ||
| 176 | |||
| 177 | static inline void __set_bit(int nr, volatile unsigned long *addr) | ||
| 178 | { | ||
| 179 | int *a = (int *)addr; | ||
| 180 | int mask; | ||
| 181 | |||
| 182 | a += nr >> 5; | ||
| 183 | mask = 1 << (nr & 0x1f); | ||
| 184 | *a |= mask; | ||
| 185 | } | ||
| 186 | |||
| 187 | static inline void __clear_bit(int nr, volatile unsigned long *addr) | ||
| 188 | { | ||
| 189 | int *a = (int *)addr; | ||
| 190 | int mask; | ||
| 191 | |||
| 192 | a += nr >> 5; | ||
| 193 | mask = 1 << (nr & 0x1f); | ||
| 134 | *a &= ~mask; | 194 | *a &= ~mask; |
| 135 | local_irq_restore(flags); | 195 | } |
| 136 | 196 | ||
| 137 | return retval; | 197 | static inline void __change_bit(int nr, volatile unsigned long *addr) |
| 198 | { | ||
| 199 | int mask; | ||
| 200 | unsigned long *ADDR = (unsigned long *)addr; | ||
| 201 | |||
| 202 | ADDR += nr >> 5; | ||
| 203 | mask = 1 << (nr & 31); | ||
| 204 | *ADDR ^= mask; | ||
| 138 | } | 205 | } |
| 139 | 206 | ||
| 140 | static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr) | 207 | static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) |
| 141 | { | 208 | { |
| 142 | int mask, retval; | 209 | int mask, retval; |
| 143 | volatile unsigned int *a = (volatile unsigned int *)addr; | 210 | volatile unsigned int *a = (volatile unsigned int *)addr; |
| @@ -145,26 +212,23 @@ static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr) | |||
| 145 | a += nr >> 5; | 212 | a += nr >> 5; |
| 146 | mask = 1 << (nr & 0x1f); | 213 | mask = 1 << (nr & 0x1f); |
| 147 | retval = (mask & *a) != 0; | 214 | retval = (mask & *a) != 0; |
| 148 | *a &= ~mask; | 215 | *a |= mask; |
| 149 | return retval; | 216 | return retval; |
| 150 | } | 217 | } |
| 151 | 218 | ||
| 152 | static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr) | 219 | static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) |
| 153 | { | 220 | { |
| 154 | int mask, retval; | 221 | int mask, retval; |
| 155 | volatile unsigned int *a = (volatile unsigned int *)addr; | 222 | volatile unsigned int *a = (volatile unsigned int *)addr; |
| 156 | unsigned long flags; | ||
| 157 | 223 | ||
| 158 | a += nr >> 5; | 224 | a += nr >> 5; |
| 159 | mask = 1 << (nr & 0x1f); | 225 | mask = 1 << (nr & 0x1f); |
| 160 | local_irq_save(flags); | ||
| 161 | retval = (mask & *a) != 0; | 226 | retval = (mask & *a) != 0; |
| 162 | *a ^= mask; | 227 | *a &= ~mask; |
| 163 | local_irq_restore(flags); | ||
| 164 | return retval; | 228 | return retval; |
| 165 | } | 229 | } |
| 166 | 230 | ||
| 167 | static __inline__ int __test_and_change_bit(int nr, | 231 | static inline int __test_and_change_bit(int nr, |
| 168 | volatile unsigned long *addr) | 232 | volatile unsigned long *addr) |
| 169 | { | 233 | { |
| 170 | int mask, retval; | 234 | int mask, retval; |
| @@ -177,16 +241,7 @@ static __inline__ int __test_and_change_bit(int nr, | |||
| 177 | return retval; | 241 | return retval; |
| 178 | } | 242 | } |
| 179 | 243 | ||
| 180 | /* | 244 | static inline int __test_bit(int nr, const void *addr) |
| 181 | * This routine doesn't need to be atomic. | ||
| 182 | */ | ||
| 183 | static __inline__ int __constant_test_bit(int nr, const void *addr) | ||
| 184 | { | ||
| 185 | return ((1UL << (nr & 31)) & | ||
| 186 | (((const volatile unsigned int *)addr)[nr >> 5])) != 0; | ||
| 187 | } | ||
| 188 | |||
| 189 | static __inline__ int __test_bit(int nr, const void *addr) | ||
| 190 | { | 245 | { |
| 191 | int *a = (int *)addr; | 246 | int *a = (int *)addr; |
| 192 | int mask; | 247 | int mask; |
| @@ -196,10 +251,16 @@ static __inline__ int __test_bit(int nr, const void *addr) | |||
| 196 | return ((mask & *a) != 0); | 251 | return ((mask & *a) != 0); |
| 197 | } | 252 | } |
| 198 | 253 | ||
| 199 | #define test_bit(nr,addr) \ | 254 | #ifndef CONFIG_SMP |
| 200 | (__builtin_constant_p(nr) ? \ | 255 | /* |
| 201 | __constant_test_bit((nr),(addr)) : \ | 256 | * This routine doesn't need irq save and restore ops in UP |
| 202 | __test_bit((nr),(addr))) | 257 | * context. |
| 258 | */ | ||
| 259 | static inline int test_bit(int nr, const void *addr) | ||
| 260 | { | ||
| 261 | return __test_bit(nr, addr); | ||
| 262 | } | ||
| 263 | #endif | ||
| 203 | 264 | ||
| 204 | #include <asm-generic/bitops/find.h> | 265 | #include <asm-generic/bitops/find.h> |
| 205 | #include <asm-generic/bitops/hweight.h> | 266 | #include <asm-generic/bitops/hweight.h> |
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h index 8749b0e321ab..8bb2cb139756 100644 --- a/arch/blackfin/include/asm/blackfin.h +++ b/arch/blackfin/include/asm/blackfin.h | |||
| @@ -6,11 +6,6 @@ | |||
| 6 | #ifndef _BLACKFIN_H_ | 6 | #ifndef _BLACKFIN_H_ |
| 7 | #define _BLACKFIN_H_ | 7 | #define _BLACKFIN_H_ |
| 8 | 8 | ||
| 9 | #define LO(con32) ((con32) & 0xFFFF) | ||
| 10 | #define lo(con32) ((con32) & 0xFFFF) | ||
| 11 | #define HI(con32) (((con32) >> 16) & 0xFFFF) | ||
| 12 | #define hi(con32) (((con32) >> 16) & 0xFFFF) | ||
| 13 | |||
| 14 | #include <mach/anomaly.h> | 9 | #include <mach/anomaly.h> |
| 15 | 10 | ||
| 16 | #ifndef __ASSEMBLY__ | 11 | #ifndef __ASSEMBLY__ |
| @@ -65,6 +60,11 @@ static inline void CSYNC(void) | |||
| 65 | 60 | ||
| 66 | #else /* __ASSEMBLY__ */ | 61 | #else /* __ASSEMBLY__ */ |
| 67 | 62 | ||
| 63 | #define LO(con32) ((con32) & 0xFFFF) | ||
| 64 | #define lo(con32) ((con32) & 0xFFFF) | ||
| 65 | #define HI(con32) (((con32) >> 16) & 0xFFFF) | ||
| 66 | #define hi(con32) (((con32) >> 16) & 0xFFFF) | ||
| 67 | |||
| 68 | /* SSYNC & CSYNC implementations for assembly files */ | 68 | /* SSYNC & CSYNC implementations for assembly files */ |
| 69 | 69 | ||
| 70 | #define ssync(x) SSYNC(x) | 70 | #define ssync(x) SSYNC(x) |
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 023d72133b5a..86637814cf25 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h | |||
| @@ -12,6 +12,11 @@ | |||
| 12 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | 12 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
| 13 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | 13 | #define SMP_CACHE_BYTES L1_CACHE_BYTES |
| 14 | 14 | ||
| 15 | #ifdef CONFIG_SMP | ||
| 16 | #define __cacheline_aligned | ||
| 17 | #else | ||
| 18 | #define ____cacheline_aligned | ||
| 19 | |||
| 15 | /* | 20 | /* |
| 16 | * Put cacheline_aliged data to L1 data memory | 21 | * Put cacheline_aliged data to L1 data memory |
| 17 | */ | 22 | */ |
| @@ -21,9 +26,33 @@ | |||
| 21 | __section__(".data_l1.cacheline_aligned"))) | 26 | __section__(".data_l1.cacheline_aligned"))) |
| 22 | #endif | 27 | #endif |
| 23 | 28 | ||
| 29 | #endif | ||
| 30 | |||
| 24 | /* | 31 | /* |
| 25 | * largest L1 which this arch supports | 32 | * largest L1 which this arch supports |
| 26 | */ | 33 | */ |
| 27 | #define L1_CACHE_SHIFT_MAX 5 | 34 | #define L1_CACHE_SHIFT_MAX 5 |
| 28 | 35 | ||
| 36 | #if defined(CONFIG_SMP) && \ | ||
| 37 | !defined(CONFIG_BFIN_CACHE_COHERENT) && \ | ||
| 38 | defined(CONFIG_BFIN_DCACHE) | ||
| 39 | #define __ARCH_SYNC_CORE_DCACHE | ||
| 40 | #ifndef __ASSEMBLY__ | ||
| 41 | asmlinkage void __raw_smp_mark_barrier_asm(void); | ||
| 42 | asmlinkage void __raw_smp_check_barrier_asm(void); | ||
| 43 | |||
| 44 | static inline void smp_mark_barrier(void) | ||
| 45 | { | ||
| 46 | __raw_smp_mark_barrier_asm(); | ||
| 47 | } | ||
| 48 | static inline void smp_check_barrier(void) | ||
| 49 | { | ||
| 50 | __raw_smp_check_barrier_asm(); | ||
| 51 | } | ||
| 52 | |||
| 53 | void resync_core_dcache(void); | ||
| 54 | #endif | ||
| 55 | #endif | ||
| 56 | |||
| 57 | |||
| 29 | #endif | 58 | #endif |
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index 4403415583fa..1b040f5b4feb 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h | |||
| @@ -35,6 +35,7 @@ extern void blackfin_icache_flush_range(unsigned long start_address, unsigned lo | |||
| 35 | extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); | 35 | extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); |
| 36 | extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); | 36 | extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); |
| 37 | extern void blackfin_dflush_page(void *page); | 37 | extern void blackfin_dflush_page(void *page); |
| 38 | extern void blackfin_invalidate_entire_dcache(void); | ||
| 38 | 39 | ||
| 39 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | 40 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
| 40 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | 41 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
| @@ -44,12 +45,20 @@ extern void blackfin_dflush_page(void *page); | |||
| 44 | #define flush_cache_vmap(start, end) do { } while (0) | 45 | #define flush_cache_vmap(start, end) do { } while (0) |
| 45 | #define flush_cache_vunmap(start, end) do { } while (0) | 46 | #define flush_cache_vunmap(start, end) do { } while (0) |
| 46 | 47 | ||
| 48 | #ifdef CONFIG_SMP | ||
| 49 | #define flush_icache_range_others(start, end) \ | ||
| 50 | smp_icache_flush_range_others((start), (end)) | ||
| 51 | #else | ||
| 52 | #define flush_icache_range_others(start, end) do { } while (0) | ||
| 53 | #endif | ||
| 54 | |||
| 47 | static inline void flush_icache_range(unsigned start, unsigned end) | 55 | static inline void flush_icache_range(unsigned start, unsigned end) |
| 48 | { | 56 | { |
| 49 | #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE) | 57 | #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE) |
| 50 | 58 | ||
| 51 | # if defined(CONFIG_BFIN_WT) | 59 | # if defined(CONFIG_BFIN_WT) |
| 52 | blackfin_icache_flush_range((start), (end)); | 60 | blackfin_icache_flush_range((start), (end)); |
| 61 | flush_icache_range_others(start, end); | ||
| 53 | # else | 62 | # else |
| 54 | blackfin_icache_dcache_flush_range((start), (end)); | 63 | blackfin_icache_dcache_flush_range((start), (end)); |
| 55 | # endif | 64 | # endif |
| @@ -58,6 +67,7 @@ static inline void flush_icache_range(unsigned start, unsigned end) | |||
| 58 | 67 | ||
| 59 | # if defined(CONFIG_BFIN_ICACHE) | 68 | # if defined(CONFIG_BFIN_ICACHE) |
| 60 | blackfin_icache_flush_range((start), (end)); | 69 | blackfin_icache_flush_range((start), (end)); |
| 70 | flush_icache_range_others(start, end); | ||
| 61 | # endif | 71 | # endif |
| 62 | # if defined(CONFIG_BFIN_DCACHE) | 72 | # if defined(CONFIG_BFIN_DCACHE) |
| 63 | blackfin_dcache_flush_range((start), (end)); | 73 | blackfin_dcache_flush_range((start), (end)); |
| @@ -66,10 +76,12 @@ static inline void flush_icache_range(unsigned start, unsigned end) | |||
| 66 | #endif | 76 | #endif |
| 67 | } | 77 | } |
| 68 | 78 | ||
| 69 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | 79 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 70 | do { memcpy(dst, src, len); \ | 80 | do { memcpy(dst, src, len); \ |
| 71 | flush_icache_range ((unsigned) (dst), (unsigned) (dst) + (len)); \ | 81 | flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ |
| 82 | flush_icache_range_others((unsigned long) (dst), (unsigned long) (dst) + (len));\ | ||
| 72 | } while (0) | 83 | } while (0) |
| 84 | |||
| 73 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) | 85 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) |
| 74 | 86 | ||
| 75 | #if defined(CONFIG_BFIN_DCACHE) | 87 | #if defined(CONFIG_BFIN_DCACHE) |
| @@ -82,7 +94,7 @@ do { memcpy(dst, src, len); \ | |||
| 82 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) | 94 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) |
| 83 | #else | 95 | #else |
| 84 | # define flush_dcache_range(start,end) do { } while (0) | 96 | # define flush_dcache_range(start,end) do { } while (0) |
| 85 | # define flush_dcache_page(page) do { } while (0) | 97 | # define flush_dcache_page(page) do { } while (0) |
| 86 | #endif | 98 | #endif |
| 87 | 99 | ||
| 88 | extern unsigned long reserved_mem_dcache_on; | 100 | extern unsigned long reserved_mem_dcache_on; |
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h index 6f6af2b8e9e0..f67289a0d8d2 100644 --- a/arch/blackfin/include/asm/checksum.h +++ b/arch/blackfin/include/asm/checksum.h | |||
| @@ -78,7 +78,8 @@ csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, | |||
| 78 | "%0 = %0 + %4;\n\t" | 78 | "%0 = %0 + %4;\n\t" |
| 79 | "NOP;\n\t" | 79 | "NOP;\n\t" |
| 80 | : "=d" (sum) | 80 | : "=d" (sum) |
| 81 | : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum)); | 81 | : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum) |
| 82 | : "CC"); | ||
| 82 | 83 | ||
| 83 | return (sum); | 84 | return (sum); |
| 84 | } | 85 | } |
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S index c0e630edfb9a..16561ab18b38 100644 --- a/arch/blackfin/include/asm/context.S +++ b/arch/blackfin/include/asm/context.S | |||
| @@ -303,9 +303,14 @@ | |||
| 303 | RETI = [sp++]; | 303 | RETI = [sp++]; |
| 304 | RETS = [sp++]; | 304 | RETS = [sp++]; |
| 305 | 305 | ||
| 306 | p0.h = _irq_flags; | 306 | #ifdef CONFIG_SMP |
| 307 | p0.l = _irq_flags; | 307 | GET_PDA(p0, r0); |
| 308 | r0 = [p0 + PDA_IRQFLAGS]; | ||
| 309 | #else | ||
| 310 | p0.h = _bfin_irq_flags; | ||
| 311 | p0.l = _bfin_irq_flags; | ||
| 308 | r0 = [p0]; | 312 | r0 = [p0]; |
| 313 | #endif | ||
| 309 | sti r0; | 314 | sti r0; |
| 310 | 315 | ||
| 311 | sp += 4; /* Skip Reserved */ | 316 | sp += 4; /* Skip Reserved */ |
| @@ -353,3 +358,41 @@ | |||
| 353 | csync; | 358 | csync; |
| 354 | .endm | 359 | .endm |
| 355 | 360 | ||
| 361 | .macro save_context_cplb | ||
| 362 | [--sp] = (R7:0, P5:0); | ||
| 363 | [--sp] = fp; | ||
| 364 | |||
| 365 | [--sp] = a0.x; | ||
| 366 | [--sp] = a0.w; | ||
| 367 | [--sp] = a1.x; | ||
| 368 | [--sp] = a1.w; | ||
| 369 | |||
| 370 | [--sp] = LC0; | ||
| 371 | [--sp] = LC1; | ||
| 372 | [--sp] = LT0; | ||
| 373 | [--sp] = LT1; | ||
| 374 | [--sp] = LB0; | ||
| 375 | [--sp] = LB1; | ||
| 376 | |||
| 377 | [--sp] = RETS; | ||
| 378 | .endm | ||
| 379 | |||
| 380 | .macro restore_context_cplb | ||
| 381 | RETS = [sp++]; | ||
| 382 | |||
| 383 | LB1 = [sp++]; | ||
| 384 | LB0 = [sp++]; | ||
| 385 | LT1 = [sp++]; | ||
| 386 | LT0 = [sp++]; | ||
| 387 | LC1 = [sp++]; | ||
| 388 | LC0 = [sp++]; | ||
| 389 | |||
| 390 | a1.w = [sp++]; | ||
| 391 | a1.x = [sp++]; | ||
| 392 | a0.w = [sp++]; | ||
| 393 | a0.x = [sp++]; | ||
| 394 | |||
| 395 | fp = [sp++]; | ||
| 396 | |||
| 397 | (R7:0, P5:0) = [SP++]; | ||
| 398 | .endm | ||
diff --git a/arch/blackfin/include/asm/cplb-mpu.h b/arch/blackfin/include/asm/cplb-mpu.h deleted file mode 100644 index 75c67b99d607..000000000000 --- a/arch/blackfin/include/asm/cplb-mpu.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/cplbinit.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | #ifndef __ASM_BFIN_CPLB_MPU_H | ||
| 30 | #define __ASM_BFIN_CPLB_MPU_H | ||
| 31 | |||
| 32 | struct cplb_entry { | ||
| 33 | unsigned long data, addr; | ||
| 34 | }; | ||
| 35 | |||
| 36 | struct mem_region { | ||
| 37 | unsigned long start, end; | ||
| 38 | unsigned long dcplb_data; | ||
| 39 | unsigned long icplb_data; | ||
| 40 | }; | ||
| 41 | |||
| 42 | extern struct cplb_entry dcplb_tbl[MAX_CPLBS]; | ||
| 43 | extern struct cplb_entry icplb_tbl[MAX_CPLBS]; | ||
| 44 | extern int first_switched_icplb; | ||
| 45 | extern int first_mask_dcplb; | ||
| 46 | extern int first_switched_dcplb; | ||
| 47 | |||
| 48 | extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot; | ||
| 49 | extern int nr_cplb_flush; | ||
| 50 | |||
| 51 | extern int page_mask_order; | ||
| 52 | extern int page_mask_nelts; | ||
| 53 | |||
| 54 | extern unsigned long *current_rwx_mask; | ||
| 55 | |||
| 56 | extern void flush_switched_cplbs(void); | ||
| 57 | extern void set_mask_dcplbs(unsigned long *); | ||
| 58 | |||
| 59 | extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *); | ||
| 60 | |||
| 61 | #endif /* __ASM_BFIN_CPLB_MPU_H */ | ||
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index 9e8b4035fcec..ad566ff9ad16 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | #ifndef _CPLB_H | 30 | #ifndef _CPLB_H |
| 31 | #define _CPLB_H | 31 | #define _CPLB_H |
| 32 | 32 | ||
| 33 | #include <asm/blackfin.h> | ||
| 34 | #include <mach/anomaly.h> | 33 | #include <mach/anomaly.h> |
| 35 | 34 | ||
| 36 | #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) | 35 | #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) |
| @@ -55,13 +54,24 @@ | |||
| 55 | #endif | 54 | #endif |
| 56 | 55 | ||
| 57 | #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) | 56 | #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) |
| 57 | |||
| 58 | #ifdef CONFIG_SMP | ||
| 59 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) | ||
| 60 | #define L2_IMEMORY (CPLB_COMMON | CPLB_LOCK) | ||
| 61 | #define L2_DMEMORY (CPLB_COMMON | CPLB_LOCK) | ||
| 62 | |||
| 63 | #else | ||
| 58 | #ifdef CONFIG_BFIN_L2_CACHEABLE | 64 | #ifdef CONFIG_BFIN_L2_CACHEABLE |
| 59 | #define L2_IMEMORY (SDRAM_IGENERIC) | 65 | #define L2_IMEMORY (SDRAM_IGENERIC) |
| 60 | #define L2_DMEMORY (SDRAM_DGENERIC) | 66 | #define L2_DMEMORY (SDRAM_DGENERIC) |
| 61 | #else | 67 | #else |
| 62 | #define L2_IMEMORY (CPLB_COMMON) | 68 | #define L2_IMEMORY (CPLB_COMMON) |
| 63 | #define L2_DMEMORY (CPLB_COMMON) | 69 | #define L2_DMEMORY (CPLB_COMMON) |
| 64 | #endif | 70 | #endif /* CONFIG_BFIN_L2_CACHEABLE */ |
| 71 | |||
| 72 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) | ||
| 73 | #endif /* CONFIG_SMP */ | ||
| 74 | |||
| 65 | #define SDRAM_DNON_CHBL (CPLB_COMMON) | 75 | #define SDRAM_DNON_CHBL (CPLB_COMMON) |
| 66 | #define SDRAM_EBIU (CPLB_COMMON) | 76 | #define SDRAM_EBIU (CPLB_COMMON) |
| 67 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) | 77 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) |
| @@ -71,14 +81,7 @@ | |||
| 71 | #define SIZE_1M 0x00100000 /* 1M */ | 81 | #define SIZE_1M 0x00100000 /* 1M */ |
| 72 | #define SIZE_4M 0x00400000 /* 4M */ | 82 | #define SIZE_4M 0x00400000 /* 4M */ |
| 73 | 83 | ||
| 74 | #ifdef CONFIG_MPU | ||
| 75 | #define MAX_CPLBS 16 | 84 | #define MAX_CPLBS 16 |
| 76 | #else | ||
| 77 | #define MAX_CPLBS (16 * 2) | ||
| 78 | #endif | ||
| 79 | |||
| 80 | #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ | ||
| 81 | ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) | ||
| 82 | 85 | ||
| 83 | #define CPLB_ENABLE_ICACHE_P 0 | 86 | #define CPLB_ENABLE_ICACHE_P 0 |
| 84 | #define CPLB_ENABLE_DCACHE_P 1 | 87 | #define CPLB_ENABLE_DCACHE_P 1 |
| @@ -113,4 +116,8 @@ | |||
| 113 | #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID | 116 | #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID |
| 114 | #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL | 117 | #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL |
| 115 | 118 | ||
| 119 | #define FAULT_RW (1 << 16) | ||
| 120 | #define FAULT_USERSUPV (1 << 17) | ||
| 121 | #define FAULT_CPLBBITS 0x0000ffff | ||
| 122 | |||
| 116 | #endif /* _CPLB_H */ | 123 | #endif /* _CPLB_H */ |
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h index f845b41147ba..05b14a631d0c 100644 --- a/arch/blackfin/include/asm/cplbinit.h +++ b/arch/blackfin/include/asm/cplbinit.h | |||
| @@ -32,61 +32,56 @@ | |||
| 32 | 32 | ||
| 33 | #include <asm/blackfin.h> | 33 | #include <asm/blackfin.h> |
| 34 | #include <asm/cplb.h> | 34 | #include <asm/cplb.h> |
| 35 | #include <linux/threads.h> | ||
| 35 | 36 | ||
| 36 | #ifdef CONFIG_MPU | 37 | #ifdef CONFIG_CPLB_SWITCH_TAB_L1 |
| 37 | 38 | # define PDT_ATTR __attribute__((l1_data)) | |
| 38 | #include <asm/cplb-mpu.h> | ||
| 39 | |||
| 40 | #else | 39 | #else |
| 40 | # define PDT_ATTR | ||
| 41 | #endif | ||
| 41 | 42 | ||
| 42 | #define INITIAL_T 0x1 | 43 | struct cplb_entry { |
| 43 | #define SWITCH_T 0x2 | 44 | unsigned long data, addr; |
| 44 | #define I_CPLB 0x4 | ||
| 45 | #define D_CPLB 0x8 | ||
| 46 | |||
| 47 | #define IN_KERNEL 1 | ||
| 48 | |||
| 49 | enum | ||
| 50 | {ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM}; | ||
| 51 | |||
| 52 | struct cplb_desc { | ||
| 53 | u32 start; /* start address */ | ||
| 54 | u32 end; /* end address */ | ||
| 55 | u32 psize; /* prefered size if any otherwise 1MB or 4MB*/ | ||
| 56 | u16 attr;/* attributes */ | ||
| 57 | u16 i_conf;/* I-CPLB DATA */ | ||
| 58 | u16 d_conf;/* D-CPLB DATA */ | ||
| 59 | u16 valid;/* valid */ | ||
| 60 | const s8 name[30];/* name */ | ||
| 61 | }; | 45 | }; |
| 62 | 46 | ||
| 63 | struct cplb_tab { | 47 | struct cplb_boundary { |
| 64 | u_long *tab; | 48 | unsigned long eaddr; /* End of this region. */ |
| 65 | u16 pos; | 49 | unsigned long data; /* CPLB data value. */ |
| 66 | u16 size; | ||
| 67 | }; | 50 | }; |
| 68 | 51 | ||
| 69 | extern u_long icplb_table[]; | 52 | extern struct cplb_boundary dcplb_bounds[]; |
| 70 | extern u_long dcplb_table[]; | 53 | extern struct cplb_boundary icplb_bounds[]; |
| 54 | extern int dcplb_nr_bounds, icplb_nr_bounds; | ||
| 71 | 55 | ||
| 72 | /* Till here we are discussing about the static memory management model. | 56 | extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS]; |
| 73 | * However, the operating envoronments commonly define more CPLB | 57 | extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS]; |
| 74 | * descriptors to cover the entire addressable memory than will fit into | 58 | extern int first_switched_icplb; |
| 75 | * the available on-chip 16 CPLB MMRs. When this happens, the below table | 59 | extern int first_switched_dcplb; |
| 76 | * will be used which will hold all the potentially required CPLB descriptors | ||
| 77 | * | ||
| 78 | * This is how Page descriptor Table is implemented in uClinux/Blackfin. | ||
| 79 | */ | ||
| 80 | 60 | ||
| 81 | extern u_long ipdt_table[]; | 61 | extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[]; |
| 82 | extern u_long dpdt_table[]; | 62 | extern int nr_dcplb_prot[], nr_cplb_flush[]; |
| 83 | #ifdef CONFIG_CPLB_INFO | 63 | |
| 84 | extern u_long ipdt_swapcount_table[]; | 64 | #ifdef CONFIG_MPU |
| 85 | extern u_long dpdt_swapcount_table[]; | 65 | |
| 86 | #endif | 66 | extern int first_mask_dcplb; |
| 67 | |||
| 68 | extern int page_mask_order; | ||
| 69 | extern int page_mask_nelts; | ||
| 70 | |||
| 71 | extern unsigned long *current_rwx_mask[NR_CPUS]; | ||
| 72 | |||
| 73 | extern void flush_switched_cplbs(unsigned int); | ||
| 74 | extern void set_mask_dcplbs(unsigned long *, unsigned int); | ||
| 75 | |||
| 76 | extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *); | ||
| 87 | 77 | ||
| 88 | #endif /* CONFIG_MPU */ | 78 | #endif /* CONFIG_MPU */ |
| 89 | 79 | ||
| 90 | extern void generate_cplb_tables(void); | 80 | extern void bfin_icache_init(struct cplb_entry *icplb_tbl); |
| 81 | extern void bfin_dcache_init(struct cplb_entry *icplb_tbl); | ||
| 91 | 82 | ||
| 83 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) | ||
| 84 | extern void generate_cplb_tables_all(void); | ||
| 85 | extern void generate_cplb_tables_cpu(unsigned int cpu); | ||
| 86 | #endif | ||
| 92 | #endif | 87 | #endif |
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h new file mode 100644 index 000000000000..c2594ef877f6 --- /dev/null +++ b/arch/blackfin/include/asm/cpu.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/include/asm/cpu.h. | ||
| 3 | * Author: Philippe Gerum <rpm@xenomai.org> | ||
| 4 | * | ||
| 5 | * Copyright 2007 Analog Devices Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, see the file COPYING, or write | ||
| 19 | * to the Free Software Foundation, Inc., | ||
| 20 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __ASM_BLACKFIN_CPU_H | ||
| 24 | #define __ASM_BLACKFIN_CPU_H | ||
| 25 | |||
| 26 | #include <linux/percpu.h> | ||
| 27 | |||
| 28 | struct task_struct; | ||
| 29 | |||
| 30 | struct blackfin_cpudata { | ||
| 31 | struct cpu cpu; | ||
| 32 | struct task_struct *idle; | ||
| 33 | unsigned int imemctl; | ||
| 34 | unsigned int dmemctl; | ||
| 35 | unsigned long loops_per_jiffy; | ||
| 36 | unsigned long dcache_invld_count; | ||
| 37 | }; | ||
| 38 | |||
| 39 | DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data); | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h index 6509733bb0f6..e4f7b8043f02 100644 --- a/arch/blackfin/include/asm/dma.h +++ b/arch/blackfin/include/asm/dma.h | |||
| @@ -1,44 +1,17 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: include/asm-blackfin/simple_bf533_dma.h | 2 | * dma.h - Blackfin DMA defines/structures/etc... |
| 3 | * Based on: none - original work | ||
| 4 | * Author: LG Soft India | ||
| 5 | * Copyright (C) 2004-2005 Analog Devices Inc. | ||
| 6 | * Created: Tue Sep 21 2004 | ||
| 7 | * Description: This file contains the major Data structures and constants | ||
| 8 | * used for DMA Implementation in BF533 | ||
| 9 | * Modified: | ||
| 10 | * | 3 | * |
| 11 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 12 | * | 5 | * Licensed under the GPL-2 or later. |
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License as published by | ||
| 15 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 16 | * any later version. | ||
| 17 | * | ||
| 18 | * This program is distributed in the hope that it will be useful, | ||
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 21 | * GNU General Public License for more details. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License | ||
| 24 | * along with this program; see the file COPYING. | ||
| 25 | * If not, write to the Free Software Foundation, | ||
| 26 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 27 | */ | 6 | */ |
| 28 | 7 | ||
| 29 | #ifndef _BLACKFIN_DMA_H_ | 8 | #ifndef _BLACKFIN_DMA_H_ |
| 30 | #define _BLACKFIN_DMA_H_ | 9 | #define _BLACKFIN_DMA_H_ |
| 31 | 10 | ||
| 32 | #include <asm/io.h> | ||
| 33 | #include <linux/slab.h> | ||
| 34 | #include <asm/irq.h> | ||
| 35 | #include <asm/signal.h> | ||
| 36 | |||
| 37 | #include <linux/kernel.h> | ||
| 38 | #include <mach/dma.h> | ||
| 39 | #include <linux/mm.h> | ||
| 40 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
| 12 | #include <mach/dma.h> | ||
| 41 | #include <asm/blackfin.h> | 13 | #include <asm/blackfin.h> |
| 14 | #include <asm/page.h> | ||
| 42 | 15 | ||
| 43 | #define MAX_DMA_ADDRESS PAGE_OFFSET | 16 | #define MAX_DMA_ADDRESS PAGE_OFFSET |
| 44 | 17 | ||
| @@ -79,7 +52,7 @@ enum dma_chan_status { | |||
| 79 | #define DMA_SYNC_RESTART 1 | 52 | #define DMA_SYNC_RESTART 1 |
| 80 | 53 | ||
| 81 | struct dmasg { | 54 | struct dmasg { |
| 82 | unsigned long next_desc_addr; | 55 | void *next_desc_addr; |
| 83 | unsigned long start_addr; | 56 | unsigned long start_addr; |
| 84 | unsigned short cfg; | 57 | unsigned short cfg; |
| 85 | unsigned short x_count; | 58 | unsigned short x_count; |
| @@ -89,7 +62,7 @@ struct dmasg { | |||
| 89 | } __attribute__((packed)); | 62 | } __attribute__((packed)); |
| 90 | 63 | ||
| 91 | struct dma_register { | 64 | struct dma_register { |
| 92 | unsigned long next_desc_ptr; /* DMA Next Descriptor Pointer register */ | 65 | void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ |
| 93 | unsigned long start_addr; /* DMA Start address register */ | 66 | unsigned long start_addr; /* DMA Start address register */ |
| 94 | 67 | ||
| 95 | unsigned short cfg; /* DMA Configuration register */ | 68 | unsigned short cfg; /* DMA Configuration register */ |
| @@ -109,7 +82,7 @@ struct dma_register { | |||
| 109 | short y_modify; /* DMA y_modify register */ | 82 | short y_modify; /* DMA y_modify register */ |
| 110 | unsigned short dummy5; | 83 | unsigned short dummy5; |
| 111 | 84 | ||
| 112 | unsigned long curr_desc_ptr; /* DMA Current Descriptor Pointer | 85 | void *curr_desc_ptr; /* DMA Current Descriptor Pointer |
| 113 | register */ | 86 | register */ |
| 114 | unsigned long curr_addr_ptr; /* DMA Current Address Pointer | 87 | unsigned long curr_addr_ptr; /* DMA Current Address Pointer |
| 115 | register */ | 88 | register */ |
| @@ -131,19 +104,15 @@ struct dma_register { | |||
| 131 | 104 | ||
| 132 | }; | 105 | }; |
| 133 | 106 | ||
| 134 | typedef irqreturn_t(*dma_interrupt_t) (int irq, void *dev_id); | 107 | struct mutex; |
| 135 | |||
| 136 | struct dma_channel { | 108 | struct dma_channel { |
| 137 | struct mutex dmalock; | 109 | struct mutex dmalock; |
| 138 | char *device_id; | 110 | const char *device_id; |
| 139 | enum dma_chan_status chan_status; | 111 | enum dma_chan_status chan_status; |
| 140 | struct dma_register *regs; | 112 | volatile struct dma_register *regs; |
| 141 | struct dmasg *sg; /* large mode descriptor */ | 113 | struct dmasg *sg; /* large mode descriptor */ |
| 142 | unsigned int ctrl_num; /* controller number */ | 114 | unsigned int irq; |
| 143 | dma_interrupt_t irq_callback; | ||
| 144 | void *data; | 115 | void *data; |
| 145 | unsigned int dma_enable_flag; | ||
| 146 | unsigned int loopback_flag; | ||
| 147 | #ifdef CONFIG_PM | 116 | #ifdef CONFIG_PM |
| 148 | unsigned short saved_peripheral_map; | 117 | unsigned short saved_peripheral_map; |
| 149 | #endif | 118 | #endif |
| @@ -157,49 +126,132 @@ void blackfin_dma_resume(void); | |||
| 157 | /******************************************************************************* | 126 | /******************************************************************************* |
| 158 | * DMA API's | 127 | * DMA API's |
| 159 | *******************************************************************************/ | 128 | *******************************************************************************/ |
| 160 | /* functions to set register mode */ | 129 | extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; |
| 161 | void set_dma_start_addr(unsigned int channel, unsigned long addr); | 130 | extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS]; |
| 162 | void set_dma_next_desc_addr(unsigned int channel, unsigned long addr); | 131 | extern int channel2irq(unsigned int channel); |
| 163 | void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr); | 132 | |
| 164 | void set_dma_x_count(unsigned int channel, unsigned short x_count); | 133 | static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) |
| 165 | void set_dma_x_modify(unsigned int channel, short x_modify); | 134 | { |
| 166 | void set_dma_y_count(unsigned int channel, unsigned short y_count); | 135 | dma_ch[channel].regs->start_addr = addr; |
| 167 | void set_dma_y_modify(unsigned int channel, short y_modify); | 136 | } |
| 168 | void set_dma_config(unsigned int channel, unsigned short config); | 137 | static inline void set_dma_next_desc_addr(unsigned int channel, void *addr) |
| 169 | unsigned short set_bfin_dma_config(char direction, char flow_mode, | 138 | { |
| 170 | char intr_mode, char dma_mode, char width, | 139 | dma_ch[channel].regs->next_desc_ptr = addr; |
| 171 | char syncmode); | 140 | } |
| 172 | void set_dma_curr_addr(unsigned int channel, unsigned long addr); | 141 | static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr) |
| 173 | 142 | { | |
| 174 | /* get curr status for polling */ | 143 | dma_ch[channel].regs->curr_desc_ptr = addr; |
| 175 | unsigned short get_dma_curr_irqstat(unsigned int channel); | 144 | } |
| 176 | unsigned short get_dma_curr_xcount(unsigned int channel); | 145 | static inline void set_dma_x_count(unsigned int channel, unsigned short x_count) |
| 177 | unsigned short get_dma_curr_ycount(unsigned int channel); | 146 | { |
| 178 | unsigned long get_dma_next_desc_ptr(unsigned int channel); | 147 | dma_ch[channel].regs->x_count = x_count; |
| 179 | unsigned long get_dma_curr_desc_ptr(unsigned int channel); | 148 | } |
| 180 | unsigned long get_dma_curr_addr(unsigned int channel); | 149 | static inline void set_dma_y_count(unsigned int channel, unsigned short y_count) |
| 181 | 150 | { | |
| 182 | /* set large DMA mode descriptor */ | 151 | dma_ch[channel].regs->y_count = y_count; |
| 183 | void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg); | 152 | } |
| 184 | 153 | static inline void set_dma_x_modify(unsigned int channel, short x_modify) | |
| 185 | /* check if current channel is in use */ | 154 | { |
| 186 | int dma_channel_active(unsigned int channel); | 155 | dma_ch[channel].regs->x_modify = x_modify; |
| 187 | 156 | } | |
| 188 | /* common functions must be called in any mode */ | 157 | static inline void set_dma_y_modify(unsigned int channel, short y_modify) |
| 158 | { | ||
| 159 | dma_ch[channel].regs->y_modify = y_modify; | ||
| 160 | } | ||
| 161 | static inline void set_dma_config(unsigned int channel, unsigned short config) | ||
| 162 | { | ||
| 163 | dma_ch[channel].regs->cfg = config; | ||
| 164 | } | ||
| 165 | static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr) | ||
| 166 | { | ||
| 167 | dma_ch[channel].regs->curr_addr_ptr = addr; | ||
| 168 | } | ||
| 169 | |||
| 170 | static inline unsigned short | ||
| 171 | set_bfin_dma_config(char direction, char flow_mode, | ||
| 172 | char intr_mode, char dma_mode, char width, char syncmode) | ||
| 173 | { | ||
| 174 | return (direction << 1) | (width << 2) | (dma_mode << 4) | | ||
| 175 | (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); | ||
| 176 | } | ||
| 177 | |||
| 178 | static inline unsigned short get_dma_curr_irqstat(unsigned int channel) | ||
| 179 | { | ||
| 180 | return dma_ch[channel].regs->irq_status; | ||
| 181 | } | ||
| 182 | static inline unsigned short get_dma_curr_xcount(unsigned int channel) | ||
| 183 | { | ||
| 184 | return dma_ch[channel].regs->curr_x_count; | ||
| 185 | } | ||
| 186 | static inline unsigned short get_dma_curr_ycount(unsigned int channel) | ||
| 187 | { | ||
| 188 | return dma_ch[channel].regs->curr_y_count; | ||
| 189 | } | ||
| 190 | static inline void *get_dma_next_desc_ptr(unsigned int channel) | ||
| 191 | { | ||
| 192 | return dma_ch[channel].regs->next_desc_ptr; | ||
| 193 | } | ||
| 194 | static inline void *get_dma_curr_desc_ptr(unsigned int channel) | ||
| 195 | { | ||
| 196 | return dma_ch[channel].regs->curr_desc_ptr; | ||
| 197 | } | ||
| 198 | static inline unsigned short get_dma_config(unsigned int channel) | ||
| 199 | { | ||
| 200 | return dma_ch[channel].regs->cfg; | ||
| 201 | } | ||
| 202 | static inline unsigned long get_dma_curr_addr(unsigned int channel) | ||
| 203 | { | ||
| 204 | return dma_ch[channel].regs->curr_addr_ptr; | ||
| 205 | } | ||
| 206 | |||
| 207 | static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize) | ||
| 208 | { | ||
| 209 | dma_ch[channel].regs->cfg = | ||
| 210 | (dma_ch[channel].regs->cfg & ~(0xf << 8)) | | ||
| 211 | ((ndsize & 0xf) << 8); | ||
| 212 | dma_ch[channel].regs->next_desc_ptr = sg; | ||
| 213 | } | ||
| 214 | |||
| 215 | static inline int dma_channel_active(unsigned int channel) | ||
| 216 | { | ||
| 217 | if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) | ||
| 218 | return 0; | ||
| 219 | else | ||
| 220 | return 1; | ||
| 221 | } | ||
| 222 | |||
| 223 | static inline void disable_dma(unsigned int channel) | ||
| 224 | { | ||
| 225 | dma_ch[channel].regs->cfg &= ~DMAEN; | ||
| 226 | SSYNC(); | ||
| 227 | dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED; | ||
| 228 | } | ||
| 229 | static inline void enable_dma(unsigned int channel) | ||
| 230 | { | ||
| 231 | dma_ch[channel].regs->curr_x_count = 0; | ||
| 232 | dma_ch[channel].regs->curr_y_count = 0; | ||
| 233 | dma_ch[channel].regs->cfg |= DMAEN; | ||
| 234 | dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED; | ||
| 235 | } | ||
| 189 | void free_dma(unsigned int channel); | 236 | void free_dma(unsigned int channel); |
| 190 | int dma_channel_active(unsigned int channel); /* check if a channel is in use */ | 237 | int request_dma(unsigned int channel, const char *device_id); |
| 191 | void disable_dma(unsigned int channel); | 238 | int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data); |
| 192 | void enable_dma(unsigned int channel); | 239 | |
| 193 | int request_dma(unsigned int channel, char *device_id); | 240 | static inline void dma_disable_irq(unsigned int channel) |
| 194 | int set_dma_callback(unsigned int channel, dma_interrupt_t callback, | 241 | { |
| 195 | void *data); | 242 | disable_irq(dma_ch[channel].irq); |
| 196 | void dma_disable_irq(unsigned int channel); | 243 | } |
| 197 | void dma_enable_irq(unsigned int channel); | 244 | static inline void dma_enable_irq(unsigned int channel) |
| 198 | void clear_dma_irqstat(unsigned int channel); | 245 | { |
| 246 | enable_irq(dma_ch[channel].irq); | ||
| 247 | } | ||
| 248 | static inline void clear_dma_irqstat(unsigned int channel) | ||
| 249 | { | ||
| 250 | dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR; | ||
| 251 | } | ||
| 252 | |||
| 199 | void *dma_memcpy(void *dest, const void *src, size_t count); | 253 | void *dma_memcpy(void *dest, const void *src, size_t count); |
| 200 | void *safe_dma_memcpy(void *dest, const void *src, size_t count); | 254 | void *safe_dma_memcpy(void *dest, const void *src, size_t count); |
| 201 | 255 | void blackfin_dma_early_init(void); | |
| 202 | extern int channel2irq(unsigned int channel); | ||
| 203 | extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL]; | ||
| 204 | 256 | ||
| 205 | #endif | 257 | #endif |
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h index c4f721e0d00d..b30a2968e274 100644 --- a/arch/blackfin/include/asm/entry.h +++ b/arch/blackfin/include/asm/entry.h | |||
| @@ -27,6 +27,14 @@ | |||
| 27 | #define SAVE_ALL_SYS save_context_no_interrupts | 27 | #define SAVE_ALL_SYS save_context_no_interrupts |
| 28 | /* This is used for all normal interrupts. It saves a minimum of registers | 28 | /* This is used for all normal interrupts. It saves a minimum of registers |
| 29 | to the stack, loads the IRQ number, and jumps to common code. */ | 29 | to the stack, loads the IRQ number, and jumps to common code. */ |
| 30 | #ifdef CONFIG_IPIPE | ||
| 31 | # define LOAD_IPIPE_IPEND \ | ||
| 32 | P0.l = lo(IPEND); \ | ||
| 33 | P0.h = hi(IPEND); \ | ||
| 34 | R1 = [P0]; | ||
| 35 | #else | ||
| 36 | # define LOAD_IPIPE_IPEND | ||
| 37 | #endif | ||
| 30 | #define INTERRUPT_ENTRY(N) \ | 38 | #define INTERRUPT_ENTRY(N) \ |
| 31 | [--sp] = SYSCFG; \ | 39 | [--sp] = SYSCFG; \ |
| 32 | \ | 40 | \ |
| @@ -34,6 +42,7 @@ | |||
| 34 | [--sp] = R0; /*orig_r0*/ \ | 42 | [--sp] = R0; /*orig_r0*/ \ |
| 35 | [--sp] = (R7:0,P5:0); \ | 43 | [--sp] = (R7:0,P5:0); \ |
| 36 | R0 = (N); \ | 44 | R0 = (N); \ |
| 45 | LOAD_IPIPE_IPEND \ | ||
| 37 | jump __common_int_entry; | 46 | jump __common_int_entry; |
| 38 | 47 | ||
| 39 | /* For timer interrupts, we need to save IPEND, since the user_mode | 48 | /* For timer interrupts, we need to save IPEND, since the user_mode |
| @@ -53,9 +62,11 @@ | |||
| 53 | /* This one pushes RETI without using CLI. Interrupts are enabled. */ | 62 | /* This one pushes RETI without using CLI. Interrupts are enabled. */ |
| 54 | #define SAVE_CONTEXT_SYSCALL save_context_syscall | 63 | #define SAVE_CONTEXT_SYSCALL save_context_syscall |
| 55 | #define SAVE_CONTEXT save_context_with_interrupts | 64 | #define SAVE_CONTEXT save_context_with_interrupts |
| 65 | #define SAVE_CONTEXT_CPLB save_context_cplb | ||
| 56 | 66 | ||
| 57 | #define RESTORE_ALL_SYS restore_context_no_interrupts | 67 | #define RESTORE_ALL_SYS restore_context_no_interrupts |
| 58 | #define RESTORE_CONTEXT restore_context_with_interrupts | 68 | #define RESTORE_CONTEXT restore_context_with_interrupts |
| 69 | #define RESTORE_CONTEXT_CPLB restore_context_cplb | ||
| 59 | 70 | ||
| 60 | #endif /* __ASSEMBLY__ */ | 71 | #endif /* __ASSEMBLY__ */ |
| 61 | #endif /* __BFIN_ENTRY_H */ | 72 | #endif /* __BFIN_ENTRY_H */ |
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index ad33ac271fd9..9477d82fcad2 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h | |||
| @@ -84,11 +84,14 @@ | |||
| 84 | #ifndef __ARCH_BLACKFIN_GPIO_H__ | 84 | #ifndef __ARCH_BLACKFIN_GPIO_H__ |
| 85 | #define __ARCH_BLACKFIN_GPIO_H__ | 85 | #define __ARCH_BLACKFIN_GPIO_H__ |
| 86 | 86 | ||
| 87 | #define gpio_bank(x) ((x) >> 4) | 87 | #define gpio_bank(x) ((x) >> 4) |
| 88 | #define gpio_bit(x) (1<<((x) & 0xF)) | 88 | #define gpio_bit(x) (1<<((x) & 0xF)) |
| 89 | #define gpio_sub_n(x) ((x) & 0xF) | 89 | #define gpio_sub_n(x) ((x) & 0xF) |
| 90 | 90 | ||
| 91 | #define GPIO_BANKSIZE 16 | 91 | #define GPIO_BANKSIZE 16 |
| 92 | #define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) | ||
| 93 | |||
| 94 | #include <mach/gpio.h> | ||
| 92 | 95 | ||
| 93 | #define GPIO_0 0 | 96 | #define GPIO_0 0 |
| 94 | #define GPIO_1 1 | 97 | #define GPIO_1 1 |
| @@ -139,151 +142,9 @@ | |||
| 139 | #define GPIO_46 46 | 142 | #define GPIO_46 46 |
| 140 | #define GPIO_47 47 | 143 | #define GPIO_47 47 |
| 141 | 144 | ||
| 142 | |||
| 143 | #define PERIPHERAL_USAGE 1 | 145 | #define PERIPHERAL_USAGE 1 |
| 144 | #define GPIO_USAGE 0 | 146 | #define GPIO_USAGE 0 |
| 145 | 147 | ||
| 146 | #ifdef BF533_FAMILY | ||
| 147 | #define MAX_BLACKFIN_GPIOS 16 | ||
| 148 | |||
| 149 | #define GPIO_PF0 0 | ||
| 150 | #define GPIO_PF1 1 | ||
| 151 | #define GPIO_PF2 2 | ||
| 152 | #define GPIO_PF3 3 | ||
| 153 | #define GPIO_PF4 4 | ||
| 154 | #define GPIO_PF5 5 | ||
| 155 | #define GPIO_PF6 6 | ||
| 156 | #define GPIO_PF7 7 | ||
| 157 | #define GPIO_PF8 8 | ||
| 158 | #define GPIO_PF9 9 | ||
| 159 | #define GPIO_PF10 10 | ||
| 160 | #define GPIO_PF11 11 | ||
| 161 | #define GPIO_PF12 12 | ||
| 162 | #define GPIO_PF13 13 | ||
| 163 | #define GPIO_PF14 14 | ||
| 164 | #define GPIO_PF15 15 | ||
| 165 | |||
| 166 | #endif | ||
| 167 | |||
| 168 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) | ||
| 169 | #define MAX_BLACKFIN_GPIOS 48 | ||
| 170 | |||
| 171 | #define GPIO_PF0 0 | ||
| 172 | #define GPIO_PF1 1 | ||
| 173 | #define GPIO_PF2 2 | ||
| 174 | #define GPIO_PF3 3 | ||
| 175 | #define GPIO_PF4 4 | ||
| 176 | #define GPIO_PF5 5 | ||
| 177 | #define GPIO_PF6 6 | ||
| 178 | #define GPIO_PF7 7 | ||
| 179 | #define GPIO_PF8 8 | ||
| 180 | #define GPIO_PF9 9 | ||
| 181 | #define GPIO_PF10 10 | ||
| 182 | #define GPIO_PF11 11 | ||
| 183 | #define GPIO_PF12 12 | ||
| 184 | #define GPIO_PF13 13 | ||
| 185 | #define GPIO_PF14 14 | ||
| 186 | #define GPIO_PF15 15 | ||
| 187 | #define GPIO_PG0 16 | ||
| 188 | #define GPIO_PG1 17 | ||
| 189 | #define GPIO_PG2 18 | ||
| 190 | #define GPIO_PG3 19 | ||
| 191 | #define GPIO_PG4 20 | ||
| 192 | #define GPIO_PG5 21 | ||
| 193 | #define GPIO_PG6 22 | ||
| 194 | #define GPIO_PG7 23 | ||
| 195 | #define GPIO_PG8 24 | ||
| 196 | #define GPIO_PG9 25 | ||
| 197 | #define GPIO_PG10 26 | ||
| 198 | #define GPIO_PG11 27 | ||
| 199 | #define GPIO_PG12 28 | ||
| 200 | #define GPIO_PG13 29 | ||
| 201 | #define GPIO_PG14 30 | ||
| 202 | #define GPIO_PG15 31 | ||
| 203 | #define GPIO_PH0 32 | ||
| 204 | #define GPIO_PH1 33 | ||
| 205 | #define GPIO_PH2 34 | ||
| 206 | #define GPIO_PH3 35 | ||
| 207 | #define GPIO_PH4 36 | ||
| 208 | #define GPIO_PH5 37 | ||
| 209 | #define GPIO_PH6 38 | ||
| 210 | #define GPIO_PH7 39 | ||
| 211 | #define GPIO_PH8 40 | ||
| 212 | #define GPIO_PH9 41 | ||
| 213 | #define GPIO_PH10 42 | ||
| 214 | #define GPIO_PH11 43 | ||
| 215 | #define GPIO_PH12 44 | ||
| 216 | #define GPIO_PH13 45 | ||
| 217 | #define GPIO_PH14 46 | ||
| 218 | #define GPIO_PH15 47 | ||
| 219 | |||
| 220 | #define PORT_F GPIO_PF0 | ||
| 221 | #define PORT_G GPIO_PG0 | ||
| 222 | #define PORT_H GPIO_PH0 | ||
| 223 | |||
| 224 | #endif | ||
| 225 | |||
| 226 | #ifdef BF548_FAMILY | ||
| 227 | #include <mach/gpio.h> | ||
| 228 | #endif | ||
| 229 | |||
| 230 | #ifdef BF561_FAMILY | ||
| 231 | #define MAX_BLACKFIN_GPIOS 48 | ||
| 232 | |||
| 233 | #define GPIO_PF0 0 | ||
| 234 | #define GPIO_PF1 1 | ||
| 235 | #define GPIO_PF2 2 | ||
| 236 | #define GPIO_PF3 3 | ||
| 237 | #define GPIO_PF4 4 | ||
| 238 | #define GPIO_PF5 5 | ||
| 239 | #define GPIO_PF6 6 | ||
| 240 | #define GPIO_PF7 7 | ||
| 241 | #define GPIO_PF8 8 | ||
| 242 | #define GPIO_PF9 9 | ||
| 243 | #define GPIO_PF10 10 | ||
| 244 | #define GPIO_PF11 11 | ||
| 245 | #define GPIO_PF12 12 | ||
| 246 | #define GPIO_PF13 13 | ||
| 247 | #define GPIO_PF14 14 | ||
| 248 | #define GPIO_PF15 15 | ||
| 249 | #define GPIO_PF16 16 | ||
| 250 | #define GPIO_PF17 17 | ||
| 251 | #define GPIO_PF18 18 | ||
| 252 | #define GPIO_PF19 19 | ||
| 253 | #define GPIO_PF20 20 | ||
| 254 | #define GPIO_PF21 21 | ||
| 255 | #define GPIO_PF22 22 | ||
| 256 | #define GPIO_PF23 23 | ||
| 257 | #define GPIO_PF24 24 | ||
| 258 | #define GPIO_PF25 25 | ||
| 259 | #define GPIO_PF26 26 | ||
| 260 | #define GPIO_PF27 27 | ||
| 261 | #define GPIO_PF28 28 | ||
| 262 | #define GPIO_PF29 29 | ||
| 263 | #define GPIO_PF30 30 | ||
| 264 | #define GPIO_PF31 31 | ||
| 265 | #define GPIO_PF32 32 | ||
| 266 | #define GPIO_PF33 33 | ||
| 267 | #define GPIO_PF34 34 | ||
| 268 | #define GPIO_PF35 35 | ||
| 269 | #define GPIO_PF36 36 | ||
| 270 | #define GPIO_PF37 37 | ||
| 271 | #define GPIO_PF38 38 | ||
| 272 | #define GPIO_PF39 39 | ||
| 273 | #define GPIO_PF40 40 | ||
| 274 | #define GPIO_PF41 41 | ||
| 275 | #define GPIO_PF42 42 | ||
| 276 | #define GPIO_PF43 43 | ||
| 277 | #define GPIO_PF44 44 | ||
| 278 | #define GPIO_PF45 45 | ||
| 279 | #define GPIO_PF46 46 | ||
| 280 | #define GPIO_PF47 47 | ||
| 281 | |||
| 282 | #define PORT_FIO0 GPIO_0 | ||
| 283 | #define PORT_FIO1 GPIO_16 | ||
| 284 | #define PORT_FIO2 GPIO_32 | ||
| 285 | #endif | ||
| 286 | |||
| 287 | #ifndef __ASSEMBLY__ | 148 | #ifndef __ASSEMBLY__ |
| 288 | 149 | ||
| 289 | /*********************************************************** | 150 | /*********************************************************** |
| @@ -425,20 +286,77 @@ struct gpio_port_s { | |||
| 425 | * MODIFICATION HISTORY : | 286 | * MODIFICATION HISTORY : |
| 426 | **************************************************************/ | 287 | **************************************************************/ |
| 427 | 288 | ||
| 428 | int gpio_request(unsigned, const char *); | 289 | int bfin_gpio_request(unsigned gpio, const char *label); |
| 429 | void gpio_free(unsigned); | 290 | void bfin_gpio_free(unsigned gpio); |
| 430 | 291 | int bfin_gpio_irq_request(unsigned gpio, const char *label); | |
| 431 | void gpio_set_value(unsigned gpio, int arg); | 292 | void bfin_gpio_irq_free(unsigned gpio); |
| 432 | int gpio_get_value(unsigned gpio); | 293 | int bfin_gpio_direction_input(unsigned gpio); |
| 294 | int bfin_gpio_direction_output(unsigned gpio, int value); | ||
| 295 | int bfin_gpio_get_value(unsigned gpio); | ||
| 296 | void bfin_gpio_set_value(unsigned gpio, int value); | ||
| 433 | 297 | ||
| 434 | #ifndef BF548_FAMILY | 298 | #ifndef BF548_FAMILY |
| 435 | #define gpio_set_value(gpio, value) set_gpio_data(gpio, value) | 299 | #define bfin_gpio_set_value(gpio, value) set_gpio_data(gpio, value) |
| 436 | #endif | 300 | #endif |
| 437 | 301 | ||
| 438 | int gpio_direction_input(unsigned gpio); | 302 | #ifdef CONFIG_GPIOLIB |
| 439 | int gpio_direction_output(unsigned gpio, int value); | 303 | #include <asm-generic/gpio.h> /* cansleep wrappers */ |
| 304 | |||
| 305 | static inline int gpio_get_value(unsigned int gpio) | ||
| 306 | { | ||
| 307 | if (gpio < MAX_BLACKFIN_GPIOS) | ||
| 308 | return bfin_gpio_get_value(gpio); | ||
| 309 | else | ||
| 310 | return __gpio_get_value(gpio); | ||
| 311 | } | ||
| 312 | |||
| 313 | static inline void gpio_set_value(unsigned int gpio, int value) | ||
| 314 | { | ||
| 315 | if (gpio < MAX_BLACKFIN_GPIOS) | ||
| 316 | bfin_gpio_set_value(gpio, value); | ||
| 317 | else | ||
| 318 | __gpio_set_value(gpio, value); | ||
| 319 | } | ||
| 320 | |||
| 321 | static inline int gpio_cansleep(unsigned int gpio) | ||
| 322 | { | ||
| 323 | return __gpio_cansleep(gpio); | ||
| 324 | } | ||
| 325 | |||
| 326 | #else /* !CONFIG_GPIOLIB */ | ||
| 327 | |||
| 328 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 329 | { | ||
| 330 | return bfin_gpio_request(gpio, label); | ||
| 331 | } | ||
| 332 | |||
| 333 | static inline void gpio_free(unsigned gpio) | ||
| 334 | { | ||
| 335 | return bfin_gpio_free(gpio); | ||
| 336 | } | ||
| 337 | |||
| 338 | static inline int gpio_direction_input(unsigned gpio) | ||
| 339 | { | ||
| 340 | return bfin_gpio_direction_input(gpio); | ||
| 341 | } | ||
| 342 | |||
| 343 | static inline int gpio_direction_output(unsigned gpio, int value) | ||
| 344 | { | ||
| 345 | return bfin_gpio_direction_output(gpio, value); | ||
| 346 | } | ||
| 347 | |||
| 348 | static inline int gpio_get_value(unsigned gpio) | ||
| 349 | { | ||
| 350 | return bfin_gpio_get_value(gpio); | ||
| 351 | } | ||
| 352 | |||
| 353 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 354 | { | ||
| 355 | return bfin_gpio_set_value(gpio, value); | ||
| 356 | } | ||
| 440 | 357 | ||
| 441 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | 358 | #include <asm-generic/gpio.h> /* cansleep wrappers */ |
| 359 | #endif /* !CONFIG_GPIOLIB */ | ||
| 442 | #include <asm/irq.h> | 360 | #include <asm/irq.h> |
| 443 | 361 | ||
| 444 | static inline int gpio_to_irq(unsigned gpio) | 362 | static inline int gpio_to_irq(unsigned gpio) |
diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h index b6b19f1b9dab..717181a1749b 100644 --- a/arch/blackfin/include/asm/hardirq.h +++ b/arch/blackfin/include/asm/hardirq.h | |||
| @@ -42,4 +42,6 @@ typedef struct { | |||
| 42 | 42 | ||
| 43 | #define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 | 43 | #define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 |
| 44 | 44 | ||
| 45 | extern void ack_bad_irq(unsigned int irq); | ||
| 46 | |||
| 45 | #endif | 47 | #endif |
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index 7dc77a21fdf3..63b2d8c78570 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h | |||
| @@ -94,12 +94,12 @@ static inline unsigned int readl(const volatile void __iomem *addr) | |||
| 94 | #define outw_p(x,addr) outw(x,addr) | 94 | #define outw_p(x,addr) outw(x,addr) |
| 95 | #define outl_p(x,addr) outl(x,addr) | 95 | #define outl_p(x,addr) outl(x,addr) |
| 96 | 96 | ||
| 97 | #define ioread8_rep(a,d,c) insb(a,d,c) | 97 | #define ioread8_rep(a,d,c) readsb(a,d,c) |
| 98 | #define ioread16_rep(a,d,c) insw(a,d,c) | 98 | #define ioread16_rep(a,d,c) readsw(a,d,c) |
| 99 | #define ioread32_rep(a,d,c) insl(a,d,c) | 99 | #define ioread32_rep(a,d,c) readsl(a,d,c) |
| 100 | #define iowrite8_rep(a,s,c) outsb(a,s,c) | 100 | #define iowrite8_rep(a,s,c) writesb(a,s,c) |
| 101 | #define iowrite16_rep(a,s,c) outsw(a,s,c) | 101 | #define iowrite16_rep(a,s,c) writesw(a,s,c) |
| 102 | #define iowrite32_rep(a,s,c) outsl(a,s,c) | 102 | #define iowrite32_rep(a,s,c) writesl(a,s,c) |
| 103 | 103 | ||
| 104 | #define ioread8(X) readb(X) | 104 | #define ioread8(X) readb(X) |
| 105 | #define ioread16(X) readw(X) | 105 | #define ioread16(X) readw(X) |
| @@ -108,6 +108,8 @@ static inline unsigned int readl(const volatile void __iomem *addr) | |||
| 108 | #define iowrite16(val,X) writew(val,X) | 108 | #define iowrite16(val,X) writew(val,X) |
| 109 | #define iowrite32(val,X) writel(val,X) | 109 | #define iowrite32(val,X) writel(val,X) |
| 110 | 110 | ||
| 111 | #define mmiowb() wmb() | ||
| 112 | |||
| 111 | #define IO_SPACE_LIMIT 0xffffffff | 113 | #define IO_SPACE_LIMIT 0xffffffff |
| 112 | 114 | ||
| 113 | /* Values for nocacheflag and cmode */ | 115 | /* Values for nocacheflag and cmode */ |
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h new file mode 100644 index 000000000000..76f53d8b9a0d --- /dev/null +++ b/arch/blackfin/include/asm/ipipe.h | |||
| @@ -0,0 +1,278 @@ | |||
| 1 | /* -*- linux-c -*- | ||
| 2 | * include/asm-blackfin/ipipe.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002-2007 Philippe Gerum. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, | ||
| 9 | * USA; either version 2 of the License, or (at your option) any later | ||
| 10 | * version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ASM_BLACKFIN_IPIPE_H | ||
| 23 | #define __ASM_BLACKFIN_IPIPE_H | ||
| 24 | |||
| 25 | #ifdef CONFIG_IPIPE | ||
| 26 | |||
| 27 | #include <linux/cpumask.h> | ||
| 28 | #include <linux/list.h> | ||
| 29 | #include <linux/threads.h> | ||
| 30 | #include <linux/irq.h> | ||
| 31 | #include <linux/ipipe_percpu.h> | ||
| 32 | #include <asm/ptrace.h> | ||
| 33 | #include <asm/irq.h> | ||
| 34 | #include <asm/bitops.h> | ||
| 35 | #include <asm/atomic.h> | ||
| 36 | #include <asm/traps.h> | ||
| 37 | |||
| 38 | #define IPIPE_ARCH_STRING "1.8-00" | ||
| 39 | #define IPIPE_MAJOR_NUMBER 1 | ||
| 40 | #define IPIPE_MINOR_NUMBER 8 | ||
| 41 | #define IPIPE_PATCH_NUMBER 0 | ||
| 42 | |||
| 43 | #ifdef CONFIG_SMP | ||
| 44 | #error "I-pipe/blackfin: SMP not implemented" | ||
| 45 | #else /* !CONFIG_SMP */ | ||
| 46 | #define ipipe_processor_id() 0 | ||
| 47 | #endif /* CONFIG_SMP */ | ||
| 48 | |||
| 49 | #define prepare_arch_switch(next) \ | ||
| 50 | do { \ | ||
| 51 | ipipe_schedule_notify(current, next); \ | ||
| 52 | local_irq_disable_hw(); \ | ||
| 53 | } while (0) | ||
| 54 | |||
| 55 | #define task_hijacked(p) \ | ||
| 56 | ({ \ | ||
| 57 | int __x__ = ipipe_current_domain != ipipe_root_domain; \ | ||
| 58 | /* We would need to clear the SYNC flag for the root domain */ \ | ||
| 59 | /* over the current processor in SMP mode. */ \ | ||
| 60 | local_irq_enable_hw(); __x__; \ | ||
| 61 | }) | ||
| 62 | |||
| 63 | struct ipipe_domain; | ||
| 64 | |||
| 65 | struct ipipe_sysinfo { | ||
| 66 | |||
| 67 | int ncpus; /* Number of CPUs on board */ | ||
| 68 | u64 cpufreq; /* CPU frequency (in Hz) */ | ||
| 69 | |||
| 70 | /* Arch-dependent block */ | ||
| 71 | |||
| 72 | struct { | ||
| 73 | unsigned tmirq; /* Timer tick IRQ */ | ||
| 74 | u64 tmfreq; /* Timer frequency */ | ||
| 75 | } archdep; | ||
| 76 | }; | ||
| 77 | |||
| 78 | #define ipipe_read_tsc(t) \ | ||
| 79 | ({ \ | ||
| 80 | unsigned long __cy2; \ | ||
| 81 | __asm__ __volatile__ ("1: %0 = CYCLES2\n" \ | ||
| 82 | "%1 = CYCLES\n" \ | ||
| 83 | "%2 = CYCLES2\n" \ | ||
| 84 | "CC = %2 == %0\n" \ | ||
| 85 | "if ! CC jump 1b\n" \ | ||
| 86 | : "=r" (((unsigned long *)&t)[1]), \ | ||
| 87 | "=r" (((unsigned long *)&t)[0]), \ | ||
| 88 | "=r" (__cy2) \ | ||
| 89 | : /*no input*/ : "CC"); \ | ||
| 90 | t; \ | ||
| 91 | }) | ||
| 92 | |||
| 93 | #define ipipe_cpu_freq() __ipipe_core_clock | ||
| 94 | #define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale) | ||
| 95 | #define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1) | ||
| 96 | |||
| 97 | /* Private interface -- Internal use only */ | ||
| 98 | |||
| 99 | #define __ipipe_check_platform() do { } while (0) | ||
| 100 | |||
| 101 | #define __ipipe_init_platform() do { } while (0) | ||
| 102 | |||
| 103 | extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; | ||
| 104 | |||
| 105 | extern unsigned long __ipipe_irq_lvmask; | ||
| 106 | |||
| 107 | extern struct ipipe_domain ipipe_root; | ||
| 108 | |||
| 109 | /* enable/disable_irqdesc _must_ be used in pairs. */ | ||
| 110 | |||
| 111 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, | ||
| 112 | unsigned irq); | ||
| 113 | |||
| 114 | void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, | ||
| 115 | unsigned irq); | ||
| 116 | |||
| 117 | #define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq)) | ||
| 118 | |||
| 119 | #define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) | ||
| 120 | |||
| 121 | #define __ipipe_lock_root() \ | ||
| 122 | set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) | ||
| 123 | |||
| 124 | #define __ipipe_unlock_root() \ | ||
| 125 | clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) | ||
| 126 | |||
| 127 | void __ipipe_enable_pipeline(void); | ||
| 128 | |||
| 129 | #define __ipipe_hook_critical_ipi(ipd) do { } while (0) | ||
| 130 | |||
| 131 | #define __ipipe_sync_pipeline(syncmask) \ | ||
| 132 | do { \ | ||
| 133 | struct ipipe_domain *ipd = ipipe_current_domain; \ | ||
| 134 | if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \ | ||
| 135 | __ipipe_sync_stage(syncmask); \ | ||
| 136 | } while (0) | ||
| 137 | |||
| 138 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); | ||
| 139 | |||
| 140 | int __ipipe_get_irq_priority(unsigned irq); | ||
| 141 | |||
| 142 | int __ipipe_get_irqthread_priority(unsigned irq); | ||
| 143 | |||
| 144 | void __ipipe_stall_root_raw(void); | ||
| 145 | |||
| 146 | void __ipipe_unstall_root_raw(void); | ||
| 147 | |||
| 148 | void __ipipe_serial_debug(const char *fmt, ...); | ||
| 149 | |||
| 150 | DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); | ||
| 151 | |||
| 152 | extern unsigned long __ipipe_core_clock; | ||
| 153 | |||
| 154 | extern unsigned long __ipipe_freq_scale; | ||
| 155 | |||
| 156 | extern unsigned long __ipipe_irq_tail_hook; | ||
| 157 | |||
| 158 | static inline unsigned long __ipipe_ffnz(unsigned long ul) | ||
| 159 | { | ||
| 160 | return ffs(ul) - 1; | ||
| 161 | } | ||
| 162 | |||
| 163 | #define __ipipe_run_irqtail() /* Must be a macro */ \ | ||
| 164 | do { \ | ||
| 165 | asmlinkage void __ipipe_call_irqtail(void); \ | ||
| 166 | unsigned long __pending; \ | ||
| 167 | CSYNC(); \ | ||
| 168 | __pending = bfin_read_IPEND(); \ | ||
| 169 | if (__pending & 0x8000) { \ | ||
| 170 | __pending &= ~0x8010; \ | ||
| 171 | if (__pending && (__pending & (__pending - 1)) == 0) \ | ||
| 172 | __ipipe_call_irqtail(); \ | ||
| 173 | } \ | ||
| 174 | } while (0) | ||
| 175 | |||
| 176 | #define __ipipe_run_isr(ipd, irq) \ | ||
| 177 | do { \ | ||
| 178 | if (ipd == ipipe_root_domain) { \ | ||
| 179 | /* \ | ||
| 180 | * Note: the I-pipe implements a threaded interrupt model on \ | ||
| 181 | * this arch for Linux external IRQs. The interrupt handler we \ | ||
| 182 | * call here only wakes up the associated IRQ thread. \ | ||
| 183 | */ \ | ||
| 184 | if (ipipe_virtual_irq_p(irq)) { \ | ||
| 185 | /* No irqtail here; virtual interrupts have no effect \ | ||
| 186 | on IPEND so there is no need for processing \ | ||
| 187 | deferral. */ \ | ||
| 188 | local_irq_enable_nohead(ipd); \ | ||
| 189 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ | ||
| 190 | local_irq_disable_nohead(ipd); \ | ||
| 191 | } else \ | ||
| 192 | /* \ | ||
| 193 | * No need to run the irqtail here either; \ | ||
| 194 | * we can't be preempted by hw IRQs, so \ | ||
| 195 | * non-Linux IRQs cannot stack over the short \ | ||
| 196 | * thread wakeup code. Which in turn means \ | ||
| 197 | * that no irqtail condition could be pending \ | ||
| 198 | * for domains above Linux in the pipeline. \ | ||
| 199 | */ \ | ||
| 200 | ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ | ||
| 201 | } else { \ | ||
| 202 | __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ | ||
| 203 | local_irq_enable_nohead(ipd); \ | ||
| 204 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ | ||
| 205 | /* Attempt to exit the outer interrupt level before \ | ||
| 206 | * starting the deferred IRQ processing. */ \ | ||
| 207 | local_irq_disable_nohead(ipd); \ | ||
| 208 | __ipipe_run_irqtail(); \ | ||
| 209 | __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ | ||
| 210 | } \ | ||
| 211 | } while (0) | ||
| 212 | |||
| 213 | #define __ipipe_syscall_watched_p(p, sc) \ | ||
| 214 | (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls) | ||
| 215 | |||
| 216 | void ipipe_init_irq_threads(void); | ||
| 217 | |||
| 218 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); | ||
| 219 | |||
| 220 | #define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS) | ||
| 221 | #define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS) | ||
| 222 | |||
| 223 | #define IRQ_SYSTMR IRQ_TIMER0 | ||
| 224 | #define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 | ||
| 225 | |||
| 226 | #if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) | ||
| 227 | #define PRIO_GPIODEMUX(irq) CONFIG_PFA | ||
| 228 | #elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) | ||
| 229 | #define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA | ||
| 230 | #elif defined(CONFIG_BF52x) | ||
| 231 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \ | ||
| 232 | (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \ | ||
| 233 | (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \ | ||
| 234 | -1) | ||
| 235 | #elif defined(CONFIG_BF561) | ||
| 236 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \ | ||
| 237 | (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \ | ||
| 238 | (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \ | ||
| 239 | -1) | ||
| 240 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) | ||
| 241 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) | ||
| 242 | #define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) | ||
| 243 | #define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() | ||
| 244 | #elif defined(CONFIG_BF54x) | ||
| 245 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \ | ||
| 246 | (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \ | ||
| 247 | (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \ | ||
| 248 | (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \ | ||
| 249 | -1) | ||
| 250 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) | ||
| 251 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) | ||
| 252 | #define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) | ||
| 253 | #define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) | ||
| 254 | #else | ||
| 255 | # error "no PRIO_GPIODEMUX() for this part" | ||
| 256 | #endif | ||
| 257 | |||
| 258 | #define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) | ||
| 259 | |||
| 260 | #else /* !CONFIG_IPIPE */ | ||
| 261 | |||
| 262 | #define task_hijacked(p) 0 | ||
| 263 | #define ipipe_trap_notify(t, r) 0 | ||
| 264 | |||
| 265 | #define __ipipe_stall_root_raw() do { } while (0) | ||
| 266 | #define __ipipe_unstall_root_raw() do { } while (0) | ||
| 267 | |||
| 268 | #define ipipe_init_irq_threads() do { } while (0) | ||
| 269 | #define ipipe_start_irq_thread(irq, desc) 0 | ||
| 270 | |||
| 271 | #define IRQ_SYSTMR IRQ_CORETMR | ||
| 272 | #define IRQ_PRIOTMR IRQ_CORETMR | ||
| 273 | |||
| 274 | #define __ipipe_root_tick_p(regs) 1 | ||
| 275 | |||
| 276 | #endif /* !CONFIG_IPIPE */ | ||
| 277 | |||
| 278 | #endif /* !__ASM_BLACKFIN_IPIPE_H */ | ||
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h new file mode 100644 index 000000000000..cb1025aeabcf --- /dev/null +++ b/arch/blackfin/include/asm/ipipe_base.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /* -*- linux-c -*- | ||
| 2 | * include/asm-blackfin/_baseipipe.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Philippe Gerum. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, | ||
| 9 | * USA; either version 2 of the License, or (at your option) any later | ||
| 10 | * version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ASM_BLACKFIN_IPIPE_BASE_H | ||
| 23 | #define __ASM_BLACKFIN_IPIPE_BASE_H | ||
| 24 | |||
| 25 | #ifdef CONFIG_IPIPE | ||
| 26 | |||
| 27 | #define IPIPE_NR_XIRQS NR_IRQS | ||
| 28 | #define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ | ||
| 29 | |||
| 30 | /* Blackfin-specific, global domain flags */ | ||
| 31 | #define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */ | ||
| 32 | |||
| 33 | /* Blackfin traps -- i.e. exception vector numbers */ | ||
| 34 | #define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ | ||
| 35 | /* Pseudo-vectors used for kernel events */ | ||
| 36 | #define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS | ||
| 37 | #define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT) | ||
| 38 | #define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1) | ||
| 39 | #define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2) | ||
| 40 | #define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3) | ||
| 41 | #define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4) | ||
| 42 | #define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5) | ||
| 43 | #define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6) | ||
| 44 | #define IPIPE_LAST_EVENT IPIPE_EVENT_CLEANUP | ||
| 45 | #define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1) | ||
| 46 | |||
| 47 | #define IPIPE_TIMER_IRQ IRQ_CORETMR | ||
| 48 | |||
| 49 | #ifndef __ASSEMBLY__ | ||
| 50 | |||
| 51 | #include <linux/bitops.h> | ||
| 52 | |||
| 53 | extern int test_bit(int nr, const void *addr); | ||
| 54 | |||
| 55 | |||
| 56 | extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ | ||
| 57 | |||
| 58 | static inline void __ipipe_stall_root(void) | ||
| 59 | { | ||
| 60 | volatile unsigned long *p = &__ipipe_root_status; | ||
| 61 | set_bit(0, p); | ||
| 62 | } | ||
| 63 | |||
| 64 | static inline unsigned long __ipipe_test_and_stall_root(void) | ||
| 65 | { | ||
| 66 | volatile unsigned long *p = &__ipipe_root_status; | ||
| 67 | return test_and_set_bit(0, p); | ||
| 68 | } | ||
| 69 | |||
| 70 | static inline unsigned long __ipipe_test_root(void) | ||
| 71 | { | ||
| 72 | const unsigned long *p = &__ipipe_root_status; | ||
| 73 | return test_bit(0, p); | ||
| 74 | } | ||
| 75 | |||
| 76 | #endif /* !__ASSEMBLY__ */ | ||
| 77 | |||
| 78 | #endif /* CONFIG_IPIPE */ | ||
| 79 | |||
| 80 | #endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */ | ||
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 89f59e18af93..3d977909ce7d 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h | |||
| @@ -17,56 +17,272 @@ | |||
| 17 | #ifndef _BFIN_IRQ_H_ | 17 | #ifndef _BFIN_IRQ_H_ |
| 18 | #define _BFIN_IRQ_H_ | 18 | #define _BFIN_IRQ_H_ |
| 19 | 19 | ||
| 20 | /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/ | ||
| 20 | #include <mach/irq.h> | 21 | #include <mach/irq.h> |
| 21 | #include <asm/ptrace.h> | 22 | #include <asm/pda.h> |
| 22 | 23 | #include <asm/processor.h> | |
| 23 | /******************************************************************************* | ||
| 24 | ***** INTRODUCTION *********** | ||
| 25 | * On the Blackfin, the interrupt structure allows remmapping of the hardware | ||
| 26 | * levels. | ||
| 27 | * - I'm going to assume that the H/W level is going to stay at the default | ||
| 28 | * settings. If someone wants to go through and abstart this out, feel free | ||
| 29 | * to mod the interrupt numbering scheme. | ||
| 30 | * - I'm abstracting the interrupts so that uClinux does not know anything | ||
| 31 | * about the H/W levels. If you want to change the H/W AND keep the abstracted | ||
| 32 | * levels that uClinux sees, you should be able to do most of it here. | ||
| 33 | * - I've left the "abstract" numbering sparce in case someone wants to pull the | ||
| 34 | * interrupts apart (just the TX/RX for the various devices) | ||
| 35 | *******************************************************************************/ | ||
| 36 | 24 | ||
| 37 | /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/ | 25 | #ifdef CONFIG_SMP |
| 26 | /* Forward decl needed due to cdef inter dependencies */ | ||
| 27 | static inline uint32_t __pure bfin_dspid(void); | ||
| 28 | # define blackfin_core_id() (bfin_dspid() & 0xff) | ||
| 29 | # define bfin_irq_flags cpu_pda[blackfin_core_id()].imask | ||
| 30 | #else | ||
| 31 | extern unsigned long bfin_irq_flags; | ||
| 32 | #endif | ||
| 38 | 33 | ||
| 39 | /* | 34 | #ifdef CONFIG_IPIPE |
| 40 | * Machine specific interrupt sources. | 35 | |
| 41 | * | 36 | #include <linux/ipipe_trace.h> |
| 42 | * Adding an interrupt service routine for a source with this bit | 37 | |
| 43 | * set indicates a special machine specific interrupt source. | 38 | void __ipipe_unstall_root(void); |
| 44 | * The machine specific files define these sources. | 39 | |
| 45 | * | 40 | void __ipipe_restore_root(unsigned long flags); |
| 46 | * The IRQ_MACHSPEC bit is now gone - the only thing it did was to | 41 | |
| 47 | * introduce unnecessary overhead. | 42 | #ifdef CONFIG_DEBUG_HWERR |
| 48 | * | 43 | # define __all_masked_irq_flags 0x3f |
| 49 | * All interrupt handling is actually machine specific so it is better | 44 | # define __save_and_cli_hw(x) \ |
| 50 | * to use function pointers, as used by the Sparc port, and select the | 45 | __asm__ __volatile__( \ |
| 51 | * interrupt handling functions when initializing the kernel. This way | 46 | "cli %0;" \ |
| 52 | * we save some unnecessary overhead at run-time. | 47 | "sti %1;" \ |
| 53 | * 01/11/97 - Jes | 48 | : "=&d"(x) \ |
| 54 | */ | 49 | : "d" (0x3F) \ |
| 50 | ) | ||
| 51 | #else | ||
| 52 | # define __all_masked_irq_flags 0x1f | ||
| 53 | # define __save_and_cli_hw(x) \ | ||
| 54 | __asm__ __volatile__( \ | ||
| 55 | "cli %0;" \ | ||
| 56 | : "=&d"(x) \ | ||
| 57 | ) | ||
| 58 | #endif | ||
| 59 | |||
| 60 | #define irqs_enabled_from_flags_hw(x) ((x) != __all_masked_irq_flags) | ||
| 61 | #define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) | ||
| 62 | #define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) | ||
| 55 | 63 | ||
| 56 | extern void ack_bad_irq(unsigned int irq); | 64 | #define local_save_flags(x) \ |
| 65 | do { \ | ||
| 66 | (x) = __ipipe_test_root() ? \ | ||
| 67 | __all_masked_irq_flags : bfin_irq_flags; \ | ||
| 68 | } while (0) | ||
| 57 | 69 | ||
| 58 | static __inline__ int irq_canonicalize(int irq) | 70 | #define local_irq_save(x) \ |
| 71 | do { \ | ||
| 72 | (x) = __ipipe_test_and_stall_root(); \ | ||
| 73 | } while (0) | ||
| 74 | |||
| 75 | #define local_irq_restore(x) __ipipe_restore_root(x) | ||
| 76 | #define local_irq_disable() __ipipe_stall_root() | ||
| 77 | #define local_irq_enable() __ipipe_unstall_root() | ||
| 78 | #define irqs_disabled() __ipipe_test_root() | ||
| 79 | |||
| 80 | #define local_save_flags_hw(x) \ | ||
| 81 | __asm__ __volatile__( \ | ||
| 82 | "cli %0;" \ | ||
| 83 | "sti %0;" \ | ||
| 84 | : "=d"(x) \ | ||
| 85 | ) | ||
| 86 | |||
| 87 | #define irqs_disabled_hw() \ | ||
| 88 | ({ \ | ||
| 89 | unsigned long flags; \ | ||
| 90 | local_save_flags_hw(flags); \ | ||
| 91 | !irqs_enabled_from_flags_hw(flags); \ | ||
| 92 | }) | ||
| 93 | |||
| 94 | static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) | ||
| 59 | { | 95 | { |
| 60 | return irq; | 96 | /* Merge virtual and real interrupt mask bits into a single |
| 97 | 32bit word. */ | ||
| 98 | return (real & ~(1 << 31)) | ((virt != 0) << 31); | ||
| 99 | } | ||
| 100 | |||
| 101 | static inline int raw_demangle_irq_bits(unsigned long *x) | ||
| 102 | { | ||
| 103 | int virt = (*x & (1 << 31)) != 0; | ||
| 104 | *x &= ~(1L << 31); | ||
| 105 | return virt; | ||
| 61 | } | 106 | } |
| 62 | 107 | ||
| 63 | /* count of spurious interrupts */ | 108 | #ifdef CONFIG_IPIPE_TRACE_IRQSOFF |
| 64 | /* extern volatile unsigned int num_spurious; */ | 109 | |
| 110 | #define local_irq_disable_hw() \ | ||
| 111 | do { \ | ||
| 112 | int _tmp_dummy; \ | ||
| 113 | if (!irqs_disabled_hw()) \ | ||
| 114 | ipipe_trace_begin(0x80000000); \ | ||
| 115 | __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : ); \ | ||
| 116 | } while (0) | ||
| 117 | |||
| 118 | #define local_irq_enable_hw() \ | ||
| 119 | do { \ | ||
| 120 | if (irqs_disabled_hw()) \ | ||
| 121 | ipipe_trace_end(0x80000000); \ | ||
| 122 | __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags)); \ | ||
| 123 | } while (0) | ||
| 124 | |||
| 125 | #define local_irq_save_hw(x) \ | ||
| 126 | do { \ | ||
| 127 | __save_and_cli_hw(x); \ | ||
| 128 | if (local_test_iflag_hw(x)) \ | ||
| 129 | ipipe_trace_begin(0x80000001); \ | ||
| 130 | } while (0) | ||
| 131 | |||
| 132 | #define local_irq_restore_hw(x) \ | ||
| 133 | do { \ | ||
| 134 | if (local_test_iflag_hw(x)) { \ | ||
| 135 | ipipe_trace_end(0x80000001); \ | ||
| 136 | local_irq_enable_hw_notrace(); \ | ||
| 137 | } \ | ||
| 138 | } while (0) | ||
| 139 | |||
| 140 | #define local_irq_disable_hw_notrace() \ | ||
| 141 | do { \ | ||
| 142 | int _tmp_dummy; \ | ||
| 143 | __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : ); \ | ||
| 144 | } while (0) | ||
| 145 | |||
| 146 | #define local_irq_enable_hw_notrace() \ | ||
| 147 | __asm__ __volatile__( \ | ||
| 148 | "sti %0;" \ | ||
| 149 | : \ | ||
| 150 | : "d"(bfin_irq_flags) \ | ||
| 151 | ) | ||
| 65 | 152 | ||
| 66 | #ifndef NO_IRQ | 153 | #define local_irq_save_hw_notrace(x) __save_and_cli_hw(x) |
| 67 | #define NO_IRQ ((unsigned int)(-1)) | 154 | |
| 155 | #define local_irq_restore_hw_notrace(x) \ | ||
| 156 | do { \ | ||
| 157 | if (local_test_iflag_hw(x)) \ | ||
| 158 | local_irq_enable_hw_notrace(); \ | ||
| 159 | } while (0) | ||
| 160 | |||
| 161 | #else /* CONFIG_IPIPE_TRACE_IRQSOFF */ | ||
| 162 | |||
| 163 | #define local_irq_enable_hw() \ | ||
| 164 | __asm__ __volatile__( \ | ||
| 165 | "sti %0;" \ | ||
| 166 | : \ | ||
| 167 | : "d"(bfin_irq_flags) \ | ||
| 168 | ) | ||
| 169 | |||
| 170 | #define local_irq_disable_hw() \ | ||
| 171 | do { \ | ||
| 172 | int _tmp_dummy; \ | ||
| 173 | __asm__ __volatile__ ( \ | ||
| 174 | "cli %0;" \ | ||
| 175 | : "=d" (_tmp_dummy)); \ | ||
| 176 | } while (0) | ||
| 177 | |||
| 178 | #define local_irq_restore_hw(x) \ | ||
| 179 | do { \ | ||
| 180 | if (irqs_enabled_from_flags_hw(x)) \ | ||
| 181 | local_irq_enable_hw(); \ | ||
| 182 | } while (0) | ||
| 183 | |||
| 184 | #define local_irq_save_hw(x) __save_and_cli_hw(x) | ||
| 185 | |||
| 186 | #define local_irq_disable_hw_notrace() local_irq_disable_hw() | ||
| 187 | #define local_irq_enable_hw_notrace() local_irq_enable_hw() | ||
| 188 | #define local_irq_save_hw_notrace(x) local_irq_save_hw(x) | ||
| 189 | #define local_irq_restore_hw_notrace(x) local_irq_restore_hw(x) | ||
| 190 | |||
| 191 | #endif /* CONFIG_IPIPE_TRACE_IRQSOFF */ | ||
| 192 | |||
| 193 | #else /* !CONFIG_IPIPE */ | ||
| 194 | |||
| 195 | /* | ||
| 196 | * Interrupt configuring macros. | ||
| 197 | */ | ||
| 198 | #define local_irq_disable() \ | ||
| 199 | do { \ | ||
| 200 | int __tmp_dummy; \ | ||
| 201 | __asm__ __volatile__( \ | ||
| 202 | "cli %0;" \ | ||
| 203 | : "=d" (__tmp_dummy) \ | ||
| 204 | ); \ | ||
| 205 | } while (0) | ||
| 206 | |||
| 207 | #define local_irq_enable() \ | ||
| 208 | __asm__ __volatile__( \ | ||
| 209 | "sti %0;" \ | ||
| 210 | : \ | ||
| 211 | : "d" (bfin_irq_flags) \ | ||
| 212 | ) | ||
| 213 | |||
| 214 | #ifdef CONFIG_DEBUG_HWERR | ||
| 215 | # define __save_and_cli(x) \ | ||
| 216 | __asm__ __volatile__( \ | ||
| 217 | "cli %0;" \ | ||
| 218 | "sti %1;" \ | ||
| 219 | : "=&d" (x) \ | ||
| 220 | : "d" (0x3F) \ | ||
| 221 | ) | ||
| 222 | #else | ||
| 223 | # define __save_and_cli(x) \ | ||
| 224 | __asm__ __volatile__( \ | ||
| 225 | "cli %0;" \ | ||
| 226 | : "=&d" (x) \ | ||
| 227 | ) | ||
| 68 | #endif | 228 | #endif |
| 69 | 229 | ||
| 70 | #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) | 230 | #define local_save_flags(x) \ |
| 231 | __asm__ __volatile__( \ | ||
| 232 | "cli %0;" \ | ||
| 233 | "sti %0;" \ | ||
| 234 | : "=d" (x) \ | ||
| 235 | ) | ||
| 236 | |||
| 237 | #ifdef CONFIG_DEBUG_HWERR | ||
| 238 | #define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0) | ||
| 239 | #else | ||
| 240 | #define irqs_enabled_from_flags(x) ((x) != 0x1f) | ||
| 241 | #endif | ||
| 242 | |||
| 243 | #define local_irq_restore(x) \ | ||
| 244 | do { \ | ||
| 245 | if (irqs_enabled_from_flags(x)) \ | ||
| 246 | local_irq_enable(); \ | ||
| 247 | } while (0) | ||
| 248 | |||
| 249 | /* For spinlocks etc */ | ||
| 250 | #define local_irq_save(x) __save_and_cli(x) | ||
| 251 | |||
| 252 | #define irqs_disabled() \ | ||
| 253 | ({ \ | ||
| 254 | unsigned long flags; \ | ||
| 255 | local_save_flags(flags); \ | ||
| 256 | !irqs_enabled_from_flags(flags); \ | ||
| 257 | }) | ||
| 258 | |||
| 259 | #define local_irq_save_hw(x) local_irq_save(x) | ||
| 260 | #define local_irq_restore_hw(x) local_irq_restore(x) | ||
| 261 | #define local_irq_enable_hw() local_irq_enable() | ||
| 262 | #define local_irq_disable_hw() local_irq_disable() | ||
| 263 | #define irqs_disabled_hw() irqs_disabled() | ||
| 264 | |||
| 265 | #endif /* !CONFIG_IPIPE */ | ||
| 266 | |||
| 267 | #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) | ||
| 268 | # define NOP_PAD_ANOMALY_05000244 "nop; nop;" | ||
| 269 | #else | ||
| 270 | # define NOP_PAD_ANOMALY_05000244 | ||
| 271 | #endif | ||
| 272 | |||
| 273 | #define idle_with_irq_disabled() \ | ||
| 274 | __asm__ __volatile__( \ | ||
| 275 | NOP_PAD_ANOMALY_05000244 \ | ||
| 276 | ".align 8;" \ | ||
| 277 | "sti %0;" \ | ||
| 278 | "idle;" \ | ||
| 279 | : \ | ||
| 280 | : "d" (bfin_irq_flags) \ | ||
| 281 | ) | ||
| 282 | |||
| 283 | static inline int irq_canonicalize(int irq) | ||
| 284 | { | ||
| 285 | return irq; | ||
| 286 | } | ||
| 71 | 287 | ||
| 72 | #endif /* _BFIN_IRQ_H_ */ | 288 | #endif /* _BFIN_IRQ_H_ */ |
diff --git a/arch/blackfin/include/asm/l1layout.h b/arch/blackfin/include/asm/l1layout.h index c13ded777828..79dbefaa5bef 100644 --- a/arch/blackfin/include/asm/l1layout.h +++ b/arch/blackfin/include/asm/l1layout.h | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | 8 | ||
| 9 | #include <asm/blackfin.h> | 9 | #include <asm/blackfin.h> |
| 10 | 10 | ||
| 11 | #ifndef CONFIG_SMP | ||
| 11 | #ifndef __ASSEMBLY__ | 12 | #ifndef __ASSEMBLY__ |
| 12 | 13 | ||
| 13 | /* Data that is "mapped" into the process VM at the start of the L1 scratch | 14 | /* Data that is "mapped" into the process VM at the start of the L1 scratch |
| @@ -24,8 +25,10 @@ struct l1_scratch_task_info | |||
| 24 | }; | 25 | }; |
| 25 | 26 | ||
| 26 | /* A pointer to the structure in memory. */ | 27 | /* A pointer to the structure in memory. */ |
| 27 | #define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)L1_SCRATCH_START) | 28 | #define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)\ |
| 29 | get_l1_scratch_start()) | ||
| 28 | 30 | ||
| 29 | #endif | 31 | #endif |
| 32 | #endif | ||
| 30 | 33 | ||
| 31 | #endif | 34 | #endif |
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_init.h b/arch/blackfin/include/asm/mem_init.h index cbe03f4a5698..255a9316ad36 100644 --- a/arch/blackfin/mach-bf527/include/mach/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h | |||
| @@ -1,35 +1,20 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf527/mem_init.h | 2 | * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory |
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | 3 | * |
| 6 | * Created: | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 7 | * Description: | ||
| 8 | * | 5 | * |
| 9 | * Rev: | 6 | * Licensed under the GPL-2 or later. |
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * Copyright 2004-2007 Analog Devices Inc. | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | 7 | */ |
| 31 | 8 | ||
| 32 | #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75) | 9 | #if defined(EBIU_SDGCTL) |
| 10 | #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ | ||
| 11 | defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ | ||
| 12 | defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ | ||
| 13 | defined(CONFIG_MEM_GENERIC_BOARD) || \ | ||
| 14 | defined(CONFIG_MEM_MT48LC32M8A2_75) || \ | ||
| 15 | defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ | ||
| 16 | defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ | ||
| 17 | defined(CONFIG_MEM_MT48LC32M8A2_75) | ||
| 33 | #if (CONFIG_SCLK_HZ > 119402985) | 18 | #if (CONFIG_SCLK_HZ > 119402985) |
| 34 | #define SDRAM_tRP TRP_2 | 19 | #define SDRAM_tRP TRP_2 |
| 35 | #define SDRAM_tRP_num 2 | 20 | #define SDRAM_tRP_num 2 |
| @@ -104,53 +89,114 @@ | |||
| 104 | #endif | 89 | #endif |
| 105 | #endif | 90 | #endif |
| 106 | 91 | ||
| 107 | #if (CONFIG_MEM_MT48LC16M16A2TG_75) | 92 | #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ |
| 108 | /*SDRAM INFORMATION: */ | 93 | defined(CONFIG_MEM_MT48LC8M32B2B5_7) |
| 109 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 110 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 111 | #define SDRAM_CL CL_3 | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #if (CONFIG_MEM_MT48LC16M8A2TG_75) | ||
| 115 | /*SDRAM INFORMATION: */ | 94 | /*SDRAM INFORMATION: */ |
| 116 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | 95 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ |
| 117 | #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ | 96 | #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ |
| 118 | #define SDRAM_CL CL_3 | 97 | #define SDRAM_CL CL_3 |
| 119 | #endif | 98 | #endif |
| 120 | 99 | ||
| 121 | #if (CONFIG_MEM_MT48LC32M8A2_75) | 100 | #if defined(CONFIG_MEM_MT48LC32M8A2_75) || \ |
| 101 | defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ | ||
| 102 | defined(CONFIG_MEM_GENERIC_BOARD) || \ | ||
| 103 | defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ | ||
| 104 | defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ | ||
| 105 | defined(CONFIG_MEM_MT48LC32M8A2_75) | ||
| 122 | /*SDRAM INFORMATION: */ | 106 | /*SDRAM INFORMATION: */ |
| 123 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | 107 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ |
| 124 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | 108 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ |
| 125 | #define SDRAM_CL CL_3 | 109 | #define SDRAM_CL CL_3 |
| 126 | #endif | 110 | #endif |
| 127 | 111 | ||
| 128 | #if (CONFIG_MEM_MT48LC64M4A2FB_7E) | 112 | |
| 129 | /*SDRAM INFORMATION: */ | 113 | #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC |
| 130 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | 114 | /* Equation from section 17 (p17-46) of BF533 HRM */ |
| 131 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | 115 | #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) |
| 132 | #define SDRAM_CL CL_3 | 116 | |
| 117 | /* Enable SCLK Out */ | ||
| 118 | #define mem_SDGCTL (0x80000000 | SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) | ||
| 119 | #else | ||
| 120 | #define mem_SDRRC CONFIG_MEM_SDRRC | ||
| 121 | #define mem_SDGCTL CONFIG_MEM_SDGCTL | ||
| 122 | #endif | ||
| 133 | #endif | 123 | #endif |
| 134 | 124 | ||
| 135 | #if (CONFIG_MEM_GENERIC_BOARD) | 125 | |
| 136 | /*SDRAM INFORMATION: Modify this for your board */ | 126 | #if defined(EBIU_DDRCTL0) |
| 137 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | 127 | #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) |
| 138 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | 128 | #define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) |
| 139 | #define SDRAM_CL CL_3 | 129 | #define DDR_CLK_HZ(x) (1000*1000*1000/x) |
| 130 | |||
| 131 | #if defined(CONFIG_MEM_MT46V32M16_6T) | ||
| 132 | #define DDR_SIZE DEVSZ_512 | ||
| 133 | #define DDR_WIDTH DEVWD_16 | ||
| 134 | #define DDR_MAX_tCK 13 | ||
| 135 | |||
| 136 | #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) | ||
| 137 | #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) | ||
| 138 | #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) | ||
| 139 | #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) | ||
| 140 | #define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) | ||
| 141 | |||
| 142 | #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) | ||
| 143 | #define DDR_tWTR DDR_TWTR(1) | ||
| 144 | #define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) | ||
| 145 | #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) | ||
| 140 | #endif | 146 | #endif |
| 141 | 147 | ||
| 142 | #if (CONFIG_MEM_MT48LC32M16A2TG_75) | 148 | #if defined(CONFIG_MEM_MT46V32M16_5B) |
| 143 | /*SDRAM INFORMATION: */ | 149 | #define DDR_SIZE DEVSZ_512 |
| 144 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | 150 | #define DDR_WIDTH DEVWD_16 |
| 145 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | 151 | #define DDR_MAX_tCK 13 |
| 146 | #define SDRAM_CL CL_3 | 152 | |
| 153 | #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) | ||
| 154 | #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) | ||
| 155 | #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) | ||
| 156 | #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) | ||
| 157 | #define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) | ||
| 158 | |||
| 159 | #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) | ||
| 160 | #define DDR_tWTR DDR_TWTR(2) | ||
| 161 | #define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) | ||
| 162 | #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) | ||
| 147 | #endif | 163 | #endif |
| 148 | 164 | ||
| 149 | /* Equation from section 17 (p17-46) of BF533 HRM */ | 165 | #if defined(CONFIG_MEM_GENERIC_BOARD) |
| 150 | #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) | 166 | #define DDR_SIZE DEVSZ_512 |
| 167 | #define DDR_WIDTH DEVWD_16 | ||
| 168 | #define DDR_MAX_tCK 13 | ||
| 151 | 169 | ||
| 152 | /* Enable SCLK Out */ | 170 | #define DDR_tRCD DDR_TRCD(3) |
| 153 | #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) | 171 | #define DDR_tWTR DDR_TWTR(2) |
| 172 | #define DDR_tWR DDR_TWR(2) | ||
| 173 | #define DDR_tMRD DDR_TMRD(2) | ||
| 174 | #define DDR_tRP DDR_TRP(3) | ||
| 175 | #define DDR_tRAS DDR_TRAS(7) | ||
| 176 | #define DDR_tRC DDR_TRC(10) | ||
| 177 | #define DDR_tRFC DDR_TRFC(12) | ||
| 178 | #define DDR_tREFI DDR_TREFI(1288) | ||
| 179 | #endif | ||
| 180 | |||
| 181 | #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) | ||
| 182 | # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." | ||
| 183 | #elif(CONFIG_SCLK_HZ <= 133333333) | ||
| 184 | # define DDR_CL CL_2 | ||
| 185 | #else | ||
| 186 | # error "CONFIG_SCLK_HZ is too large (>133333333 Hz)." | ||
| 187 | #endif | ||
| 188 | |||
| 189 | #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC | ||
| 190 | #define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) | ||
| 191 | #define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ | ||
| 192 | | DDR_tMRD | DDR_tWR | DDR_tRCD) | ||
| 193 | #define mem_DDRCTL2 DDR_CL | ||
| 194 | #else | ||
| 195 | #define mem_DDRCTL0 CONFIG_MEM_DDRCTL0 | ||
| 196 | #define mem_DDRCTL1 CONFIG_MEM_DDRCTL1 | ||
| 197 | #define mem_DDRCTL2 CONFIG_MEM_DDRCTL2 | ||
| 198 | #endif | ||
| 199 | #endif | ||
| 154 | 200 | ||
| 155 | #if defined CONFIG_CLKIN_HALF | 201 | #if defined CONFIG_CLKIN_HALF |
| 156 | #define CLKIN_HALF 1 | 202 | #define CLKIN_HALF 1 |
| @@ -165,6 +211,13 @@ | |||
| 165 | #endif | 211 | #endif |
| 166 | 212 | ||
| 167 | /***************************************Currently Not Being Used *********************************/ | 213 | /***************************************Currently Not Being Used *********************************/ |
| 214 | |||
| 215 | #if defined(CONFIG_FLASH_SPEED_BWAT) && \ | ||
| 216 | defined(CONFIG_FLASH_SPEED_BRAT) && \ | ||
| 217 | defined(CONFIG_FLASH_SPEED_BHT) && \ | ||
| 218 | defined(CONFIG_FLASH_SPEED_BST) && \ | ||
| 219 | defined(CONFIG_FLASH_SPEED_BTT) | ||
| 220 | |||
| 168 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | 221 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 |
| 169 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | 222 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 |
| 170 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) | 223 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) |
| @@ -308,3 +361,4 @@ | |||
| 308 | #define flash_EBIU_AMBCTL0 \ | 361 | #define flash_EBIU_AMBCTL0 \ |
| 309 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ | 362 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ |
| 310 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) | 363 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) |
| 364 | #endif | ||
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h index 88d04a707708..e92b31051bb7 100644 --- a/arch/blackfin/include/asm/mem_map.h +++ b/arch/blackfin/include/asm/mem_map.h | |||
| @@ -9,4 +9,79 @@ | |||
| 9 | 9 | ||
| 10 | #include <mach/mem_map.h> | 10 | #include <mach/mem_map.h> |
| 11 | 11 | ||
| 12 | #ifndef __ASSEMBLY__ | ||
| 13 | |||
| 14 | #ifdef CONFIG_SMP | ||
| 15 | static inline ulong get_l1_scratch_start_cpu(int cpu) | ||
| 16 | { | ||
| 17 | return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; | ||
| 18 | } | ||
| 19 | static inline ulong get_l1_code_start_cpu(int cpu) | ||
| 20 | { | ||
| 21 | return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START; | ||
| 22 | } | ||
| 23 | static inline ulong get_l1_data_a_start_cpu(int cpu) | ||
| 24 | { | ||
| 25 | return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; | ||
| 26 | } | ||
| 27 | static inline ulong get_l1_data_b_start_cpu(int cpu) | ||
| 28 | { | ||
| 29 | return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; | ||
| 30 | } | ||
| 31 | |||
| 32 | static inline ulong get_l1_scratch_start(void) | ||
| 33 | { | ||
| 34 | return get_l1_scratch_start_cpu(blackfin_core_id()); | ||
| 35 | } | ||
| 36 | static inline ulong get_l1_code_start(void) | ||
| 37 | { | ||
| 38 | return get_l1_code_start_cpu(blackfin_core_id()); | ||
| 39 | } | ||
| 40 | static inline ulong get_l1_data_a_start(void) | ||
| 41 | { | ||
| 42 | return get_l1_data_a_start_cpu(blackfin_core_id()); | ||
| 43 | } | ||
| 44 | static inline ulong get_l1_data_b_start(void) | ||
| 45 | { | ||
| 46 | return get_l1_data_b_start_cpu(blackfin_core_id()); | ||
| 47 | } | ||
| 48 | |||
| 49 | #else /* !CONFIG_SMP */ | ||
| 50 | |||
| 51 | static inline ulong get_l1_scratch_start_cpu(int cpu) | ||
| 52 | { | ||
| 53 | return L1_SCRATCH_START; | ||
| 54 | } | ||
| 55 | static inline ulong get_l1_code_start_cpu(int cpu) | ||
| 56 | { | ||
| 57 | return L1_CODE_START; | ||
| 58 | } | ||
| 59 | static inline ulong get_l1_data_a_start_cpu(int cpu) | ||
| 60 | { | ||
| 61 | return L1_DATA_A_START; | ||
| 62 | } | ||
| 63 | static inline ulong get_l1_data_b_start_cpu(int cpu) | ||
| 64 | { | ||
| 65 | return L1_DATA_B_START; | ||
| 66 | } | ||
| 67 | static inline ulong get_l1_scratch_start(void) | ||
| 68 | { | ||
| 69 | return get_l1_scratch_start_cpu(0); | ||
| 70 | } | ||
| 71 | static inline ulong get_l1_code_start(void) | ||
| 72 | { | ||
| 73 | return get_l1_code_start_cpu(0); | ||
| 74 | } | ||
| 75 | static inline ulong get_l1_data_a_start(void) | ||
| 76 | { | ||
| 77 | return get_l1_data_a_start_cpu(0); | ||
| 78 | } | ||
| 79 | static inline ulong get_l1_data_b_start(void) | ||
| 80 | { | ||
| 81 | return get_l1_data_b_start_cpu(0); | ||
| 82 | } | ||
| 83 | |||
| 84 | #endif /* CONFIG_SMP */ | ||
| 85 | #endif /* __ASSEMBLY__ */ | ||
| 86 | |||
| 12 | #endif /* _MEM_MAP_H_ */ | 87 | #endif /* _MEM_MAP_H_ */ |
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h index 35593dda2a4d..944e29faae48 100644 --- a/arch/blackfin/include/asm/mmu_context.h +++ b/arch/blackfin/include/asm/mmu_context.h | |||
| @@ -37,6 +37,10 @@ | |||
| 37 | #include <asm/pgalloc.h> | 37 | #include <asm/pgalloc.h> |
| 38 | #include <asm/cplbinit.h> | 38 | #include <asm/cplbinit.h> |
| 39 | 39 | ||
| 40 | /* Note: L1 stacks are CPU-private things, so we bluntly disable this | ||
| 41 | feature in SMP mode, and use the per-CPU scratch SRAM bank only to | ||
| 42 | store the PDA instead. */ | ||
| 43 | |||
| 40 | extern void *current_l1_stack_save; | 44 | extern void *current_l1_stack_save; |
| 41 | extern int nr_l1stack_tasks; | 45 | extern int nr_l1stack_tasks; |
| 42 | extern void *l1_stack_base; | 46 | extern void *l1_stack_base; |
| @@ -88,12 +92,15 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base) | |||
| 88 | static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, | 92 | static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, |
| 89 | struct task_struct *tsk) | 93 | struct task_struct *tsk) |
| 90 | { | 94 | { |
| 95 | #ifdef CONFIG_MPU | ||
| 96 | unsigned int cpu = smp_processor_id(); | ||
| 97 | #endif | ||
| 91 | if (prev_mm == next_mm) | 98 | if (prev_mm == next_mm) |
| 92 | return; | 99 | return; |
| 93 | #ifdef CONFIG_MPU | 100 | #ifdef CONFIG_MPU |
| 94 | if (prev_mm->context.page_rwx_mask == current_rwx_mask) { | 101 | if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) { |
| 95 | flush_switched_cplbs(); | 102 | flush_switched_cplbs(cpu); |
| 96 | set_mask_dcplbs(next_mm->context.page_rwx_mask); | 103 | set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu); |
| 97 | } | 104 | } |
| 98 | #endif | 105 | #endif |
| 99 | 106 | ||
| @@ -138,9 +145,10 @@ static inline void protect_page(struct mm_struct *mm, unsigned long addr, | |||
| 138 | 145 | ||
| 139 | static inline void update_protections(struct mm_struct *mm) | 146 | static inline void update_protections(struct mm_struct *mm) |
| 140 | { | 147 | { |
| 141 | if (mm->context.page_rwx_mask == current_rwx_mask) { | 148 | unsigned int cpu = smp_processor_id(); |
| 142 | flush_switched_cplbs(); | 149 | if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) { |
| 143 | set_mask_dcplbs(mm->context.page_rwx_mask); | 150 | flush_switched_cplbs(cpu); |
| 151 | set_mask_dcplbs(mm->context.page_rwx_mask, cpu); | ||
| 144 | } | 152 | } |
| 145 | } | 153 | } |
| 146 | #endif | 154 | #endif |
| @@ -165,6 +173,9 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) | |||
| 165 | static inline void destroy_context(struct mm_struct *mm) | 173 | static inline void destroy_context(struct mm_struct *mm) |
| 166 | { | 174 | { |
| 167 | struct sram_list_struct *tmp; | 175 | struct sram_list_struct *tmp; |
| 176 | #ifdef CONFIG_MPU | ||
| 177 | unsigned int cpu = smp_processor_id(); | ||
| 178 | #endif | ||
| 168 | 179 | ||
| 169 | #ifdef CONFIG_APP_STACK_L1 | 180 | #ifdef CONFIG_APP_STACK_L1 |
| 170 | if (current_l1_stack_save == mm->context.l1_stack_save) | 181 | if (current_l1_stack_save == mm->context.l1_stack_save) |
| @@ -179,8 +190,8 @@ static inline void destroy_context(struct mm_struct *mm) | |||
| 179 | kfree(tmp); | 190 | kfree(tmp); |
| 180 | } | 191 | } |
| 181 | #ifdef CONFIG_MPU | 192 | #ifdef CONFIG_MPU |
| 182 | if (current_rwx_mask == mm->context.page_rwx_mask) | 193 | if (current_rwx_mask[cpu] == mm->context.page_rwx_mask) |
| 183 | current_rwx_mask = NULL; | 194 | current_rwx_mask[cpu] = NULL; |
| 184 | free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order); | 195 | free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order); |
| 185 | #endif | 196 | #endif |
| 186 | } | 197 | } |
diff --git a/arch/blackfin/include/asm/mutex-dec.h b/arch/blackfin/include/asm/mutex-dec.h new file mode 100644 index 000000000000..0134151656af --- /dev/null +++ b/arch/blackfin/include/asm/mutex-dec.h | |||
| @@ -0,0 +1,112 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-generic/mutex-dec.h | ||
| 3 | * | ||
| 4 | * Generic implementation of the mutex fastpath, based on atomic | ||
| 5 | * decrement/increment. | ||
| 6 | */ | ||
| 7 | #ifndef _ASM_GENERIC_MUTEX_DEC_H | ||
| 8 | #define _ASM_GENERIC_MUTEX_DEC_H | ||
| 9 | |||
| 10 | /** | ||
| 11 | * __mutex_fastpath_lock - try to take the lock by moving the count | ||
| 12 | * from 1 to a 0 value | ||
| 13 | * @count: pointer of type atomic_t | ||
| 14 | * @fail_fn: function to call if the original value was not 1 | ||
| 15 | * | ||
| 16 | * Change the count from 1 to a value lower than 1, and call <fail_fn> if | ||
| 17 | * it wasn't 1 originally. This function MUST leave the value lower than | ||
| 18 | * 1 even when the "1" assertion wasn't true. | ||
| 19 | */ | ||
| 20 | static inline void | ||
| 21 | __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | ||
| 22 | { | ||
| 23 | if (unlikely(atomic_dec_return(count) < 0)) | ||
| 24 | fail_fn(count); | ||
| 25 | else | ||
| 26 | smp_mb(); | ||
| 27 | } | ||
| 28 | |||
| 29 | /** | ||
| 30 | * __mutex_fastpath_lock_retval - try to take the lock by moving the count | ||
| 31 | * from 1 to a 0 value | ||
| 32 | * @count: pointer of type atomic_t | ||
| 33 | * @fail_fn: function to call if the original value was not 1 | ||
| 34 | * | ||
| 35 | * Change the count from 1 to a value lower than 1, and call <fail_fn> if | ||
| 36 | * it wasn't 1 originally. This function returns 0 if the fastpath succeeds, | ||
| 37 | * or anything the slow path function returns. | ||
| 38 | */ | ||
| 39 | static inline int | ||
| 40 | __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) | ||
| 41 | { | ||
| 42 | if (unlikely(atomic_dec_return(count) < 0)) | ||
| 43 | return fail_fn(count); | ||
| 44 | else { | ||
| 45 | smp_mb(); | ||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | } | ||
| 49 | |||
| 50 | /** | ||
| 51 | * __mutex_fastpath_unlock - try to promote the count from 0 to 1 | ||
| 52 | * @count: pointer of type atomic_t | ||
| 53 | * @fail_fn: function to call if the original value was not 0 | ||
| 54 | * | ||
| 55 | * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>. | ||
| 56 | * In the failure case, this function is allowed to either set the value to | ||
| 57 | * 1, or to set it to a value lower than 1. | ||
| 58 | * | ||
| 59 | * If the implementation sets it to a value of lower than 1, then the | ||
| 60 | * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs | ||
| 61 | * to return 0 otherwise. | ||
| 62 | */ | ||
| 63 | static inline void | ||
| 64 | __mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | ||
| 65 | { | ||
| 66 | smp_mb(); | ||
| 67 | if (unlikely(atomic_inc_return(count) <= 0)) | ||
| 68 | fail_fn(count); | ||
| 69 | } | ||
| 70 | |||
| 71 | #define __mutex_slowpath_needs_to_unlock() 1 | ||
| 72 | |||
| 73 | /** | ||
| 74 | * __mutex_fastpath_trylock - try to acquire the mutex, without waiting | ||
| 75 | * | ||
| 76 | * @count: pointer of type atomic_t | ||
| 77 | * @fail_fn: fallback function | ||
| 78 | * | ||
| 79 | * Change the count from 1 to a value lower than 1, and return 0 (failure) | ||
| 80 | * if it wasn't 1 originally, or return 1 (success) otherwise. This function | ||
| 81 | * MUST leave the value lower than 1 even when the "1" assertion wasn't true. | ||
| 82 | * Additionally, if the value was < 0 originally, this function must not leave | ||
| 83 | * it to 0 on failure. | ||
| 84 | * | ||
| 85 | * If the architecture has no effective trylock variant, it should call the | ||
| 86 | * <fail_fn> spinlock-based trylock variant unconditionally. | ||
| 87 | */ | ||
| 88 | static inline int | ||
| 89 | __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) | ||
| 90 | { | ||
| 91 | /* | ||
| 92 | * We have two variants here. The cmpxchg based one is the best one | ||
| 93 | * because it never induce a false contention state. It is included | ||
| 94 | * here because architectures using the inc/dec algorithms over the | ||
| 95 | * xchg ones are much more likely to support cmpxchg natively. | ||
| 96 | * | ||
| 97 | * If not we fall back to the spinlock based variant - that is | ||
| 98 | * just as efficient (and simpler) as a 'destructive' probing of | ||
| 99 | * the mutex state would be. | ||
| 100 | */ | ||
| 101 | #ifdef __HAVE_ARCH_CMPXCHG | ||
| 102 | if (likely(atomic_cmpxchg(count, 1, 0) == 1)) { | ||
| 103 | smp_mb(); | ||
| 104 | return 1; | ||
| 105 | } | ||
| 106 | return 0; | ||
| 107 | #else | ||
| 108 | return fail_fn(count); | ||
| 109 | #endif | ||
| 110 | } | ||
| 111 | |||
| 112 | #endif | ||
diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h index 458c1f7fbc18..5d399256bf06 100644 --- a/arch/blackfin/include/asm/mutex.h +++ b/arch/blackfin/include/asm/mutex.h | |||
| @@ -6,4 +6,67 @@ | |||
| 6 | * implementation. (see asm-generic/mutex-xchg.h for details) | 6 | * implementation. (see asm-generic/mutex-xchg.h for details) |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #ifndef _ASM_MUTEX_H | ||
| 10 | #define _ASM_MUTEX_H | ||
| 11 | |||
| 12 | #ifndef CONFIG_SMP | ||
| 9 | #include <asm-generic/mutex-dec.h> | 13 | #include <asm-generic/mutex-dec.h> |
| 14 | #else | ||
| 15 | |||
| 16 | static inline void | ||
| 17 | __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) | ||
| 18 | { | ||
| 19 | if (unlikely(atomic_dec_return(count) < 0)) | ||
| 20 | fail_fn(count); | ||
| 21 | else | ||
| 22 | smp_mb(); | ||
| 23 | } | ||
| 24 | |||
| 25 | static inline int | ||
| 26 | __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) | ||
| 27 | { | ||
| 28 | if (unlikely(atomic_dec_return(count) < 0)) | ||
| 29 | return fail_fn(count); | ||
| 30 | else { | ||
| 31 | smp_mb(); | ||
| 32 | return 0; | ||
| 33 | } | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline void | ||
| 37 | __mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) | ||
| 38 | { | ||
| 39 | smp_mb(); | ||
| 40 | if (unlikely(atomic_inc_return(count) <= 0)) | ||
| 41 | fail_fn(count); | ||
| 42 | } | ||
| 43 | |||
| 44 | #define __mutex_slowpath_needs_to_unlock() 1 | ||
| 45 | |||
| 46 | static inline int | ||
| 47 | __mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *)) | ||
| 48 | { | ||
| 49 | /* | ||
| 50 | * We have two variants here. The cmpxchg based one is the best one | ||
| 51 | * because it never induce a false contention state. It is included | ||
| 52 | * here because architectures using the inc/dec algorithms over the | ||
| 53 | * xchg ones are much more likely to support cmpxchg natively. | ||
| 54 | * | ||
| 55 | * If not we fall back to the spinlock based variant - that is | ||
| 56 | * just as efficient (and simpler) as a 'destructive' probing of | ||
| 57 | * the mutex state would be. | ||
| 58 | */ | ||
| 59 | #ifdef __HAVE_ARCH_CMPXCHG | ||
| 60 | if (likely(atomic_cmpxchg(count, 1, 0) == 1)) { | ||
| 61 | smp_mb(); | ||
| 62 | return 1; | ||
| 63 | } | ||
| 64 | return 0; | ||
| 65 | #else | ||
| 66 | return fail_fn(count); | ||
| 67 | #endif | ||
| 68 | } | ||
| 69 | |||
| 70 | #endif | ||
| 71 | |||
| 72 | #endif | ||
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h new file mode 100644 index 000000000000..bd8d4a7efeb2 --- /dev/null +++ b/arch/blackfin/include/asm/pda.h | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/include/asm/pda.h | ||
| 3 | * Author: Philippe Gerum <rpm@xenomai.org> | ||
| 4 | * | ||
| 5 | * Copyright 2007 Analog Devices Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, see the file COPYING, or write | ||
| 19 | * to the Free Software Foundation, Inc., | ||
| 20 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _ASM_BLACKFIN_PDA_H | ||
| 24 | #define _ASM_BLACKFIN_PDA_H | ||
| 25 | |||
| 26 | #include <mach/anomaly.h> | ||
| 27 | |||
| 28 | #ifndef __ASSEMBLY__ | ||
| 29 | |||
| 30 | struct blackfin_pda { /* Per-processor Data Area */ | ||
| 31 | struct blackfin_pda *next; | ||
| 32 | |||
| 33 | unsigned long syscfg; | ||
| 34 | #ifdef CONFIG_SMP | ||
| 35 | unsigned long imask; /* Current IMASK value */ | ||
| 36 | #endif | ||
| 37 | |||
| 38 | unsigned long *ipdt; /* Start of switchable I-CPLB table */ | ||
| 39 | unsigned long *ipdt_swapcount; /* Number of swaps in ipdt */ | ||
| 40 | unsigned long *dpdt; /* Start of switchable D-CPLB table */ | ||
| 41 | unsigned long *dpdt_swapcount; /* Number of swaps in dpdt */ | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Single instructions can have multiple faults, which | ||
| 45 | * need to be handled by traps.c, in irq5. We store | ||
| 46 | * the exception cause to ensure we don't miss a | ||
| 47 | * double fault condition | ||
| 48 | */ | ||
| 49 | unsigned long ex_iptr; | ||
| 50 | unsigned long ex_optr; | ||
| 51 | unsigned long ex_buf[4]; | ||
| 52 | unsigned long ex_imask; /* Saved imask from exception */ | ||
| 53 | unsigned long *ex_stack; /* Exception stack space */ | ||
| 54 | |||
| 55 | #ifdef ANOMALY_05000261 | ||
| 56 | unsigned long last_cplb_fault_retx; | ||
| 57 | #endif | ||
| 58 | unsigned long dcplb_fault_addr; | ||
| 59 | unsigned long icplb_fault_addr; | ||
| 60 | unsigned long retx; | ||
| 61 | unsigned long seqstat; | ||
| 62 | }; | ||
| 63 | |||
| 64 | extern struct blackfin_pda cpu_pda[]; | ||
| 65 | |||
| 66 | void reserve_pda(void); | ||
| 67 | |||
| 68 | #endif /* __ASSEMBLY__ */ | ||
| 69 | |||
| 70 | #endif /* _ASM_BLACKFIN_PDA_H */ | ||
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h index 78dd61f6b39f..797c0c165069 100644 --- a/arch/blackfin/include/asm/percpu.h +++ b/arch/blackfin/include/asm/percpu.h | |||
| @@ -3,4 +3,14 @@ | |||
| 3 | 3 | ||
| 4 | #include <asm-generic/percpu.h> | 4 | #include <asm-generic/percpu.h> |
| 5 | 5 | ||
| 6 | #endif /* __ARCH_BLACKFIN_PERCPU__ */ | 6 | #ifdef CONFIG_MODULES |
| 7 | #define PERCPU_MODULE_RESERVE 8192 | ||
| 8 | #else | ||
| 9 | #define PERCPU_MODULE_RESERVE 0 | ||
| 10 | #endif | ||
| 11 | |||
| 12 | #define PERCPU_ENOUGH_ROOM \ | ||
| 13 | (ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES) + \ | ||
| 14 | PERCPU_MODULE_RESERVE) | ||
| 15 | |||
| 16 | #endif /* __ARCH_BLACKFIN_PERCPU__ */ | ||
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h index f11684e4ade7..783c8f7f8f8c 100644 --- a/arch/blackfin/include/asm/pgtable.h +++ b/arch/blackfin/include/asm/pgtable.h | |||
| @@ -29,6 +29,7 @@ typedef pte_t *pte_addr_t; | |||
| 29 | #define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */ | 29 | #define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */ |
| 30 | #define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */ | 30 | #define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */ |
| 31 | #define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */ | 31 | #define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */ |
| 32 | #define pgprot_noncached(prot) (prot) | ||
| 32 | 33 | ||
| 33 | extern void paging_init(void); | 34 | extern void paging_init(void); |
| 34 | 35 | ||
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h index e3e9b41fa8db..0eece23b41c7 100644 --- a/arch/blackfin/include/asm/processor.h +++ b/arch/blackfin/include/asm/processor.h | |||
| @@ -24,6 +24,14 @@ static inline void wrusp(unsigned long usp) | |||
| 24 | __asm__ __volatile__("usp = %0;\n\t"::"da"(usp)); | 24 | __asm__ __volatile__("usp = %0;\n\t"::"da"(usp)); |
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | static inline unsigned long __get_SP(void) | ||
| 28 | { | ||
| 29 | unsigned long sp; | ||
| 30 | |||
| 31 | __asm__ __volatile__("%0 = sp;\n\t" : "=da"(sp)); | ||
| 32 | return sp; | ||
| 33 | } | ||
| 34 | |||
| 27 | /* | 35 | /* |
| 28 | * User space process size: 1st byte beyond user address space. | 36 | * User space process size: 1st byte beyond user address space. |
| 29 | * Fairly meaningless on nommu. Parts of user programs can be scattered | 37 | * Fairly meaningless on nommu. Parts of user programs can be scattered |
| @@ -57,6 +65,7 @@ struct thread_struct { | |||
| 57 | * pass the data segment into user programs if it exists, | 65 | * pass the data segment into user programs if it exists, |
| 58 | * it can't hurt anything as far as I can tell | 66 | * it can't hurt anything as far as I can tell |
| 59 | */ | 67 | */ |
| 68 | #ifndef CONFIG_SMP | ||
| 60 | #define start_thread(_regs, _pc, _usp) \ | 69 | #define start_thread(_regs, _pc, _usp) \ |
| 61 | do { \ | 70 | do { \ |
| 62 | set_fs(USER_DS); \ | 71 | set_fs(USER_DS); \ |
| @@ -70,6 +79,16 @@ do { \ | |||
| 70 | sizeof(*L1_SCRATCH_TASK_INFO)); \ | 79 | sizeof(*L1_SCRATCH_TASK_INFO)); \ |
| 71 | wrusp(_usp); \ | 80 | wrusp(_usp); \ |
| 72 | } while(0) | 81 | } while(0) |
| 82 | #else | ||
| 83 | #define start_thread(_regs, _pc, _usp) \ | ||
| 84 | do { \ | ||
| 85 | set_fs(USER_DS); \ | ||
| 86 | (_regs)->pc = (_pc); \ | ||
| 87 | if (current->mm) \ | ||
| 88 | (_regs)->p5 = current->mm->start_data; \ | ||
| 89 | wrusp(_usp); \ | ||
| 90 | } while (0) | ||
| 91 | #endif | ||
| 73 | 92 | ||
| 74 | /* Forward declaration, a strange C thing */ | 93 | /* Forward declaration, a strange C thing */ |
| 75 | struct task_struct; | 94 | struct task_struct; |
| @@ -106,7 +125,8 @@ unsigned long get_wchan(struct task_struct *p); | |||
| 106 | eip; }) | 125 | eip; }) |
| 107 | #define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) | 126 | #define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) |
| 108 | 127 | ||
| 109 | #define cpu_relax() barrier() | 128 | #define cpu_relax() smp_mb() |
| 129 | |||
| 110 | 130 | ||
| 111 | /* Get the Silicon Revision of the chip */ | 131 | /* Get the Silicon Revision of the chip */ |
| 112 | static inline uint32_t __pure bfin_revid(void) | 132 | static inline uint32_t __pure bfin_revid(void) |
| @@ -137,7 +157,11 @@ static inline uint32_t __pure bfin_revid(void) | |||
| 137 | static inline uint16_t __pure bfin_cpuid(void) | 157 | static inline uint16_t __pure bfin_cpuid(void) |
| 138 | { | 158 | { |
| 139 | return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12; | 159 | return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12; |
| 160 | } | ||
| 140 | 161 | ||
| 162 | static inline uint32_t __pure bfin_dspid(void) | ||
| 163 | { | ||
| 164 | return bfin_read_DSPID(); | ||
| 141 | } | 165 | } |
| 142 | 166 | ||
| 143 | static inline uint32_t __pure bfin_compiled_revid(void) | 167 | static inline uint32_t __pure bfin_compiled_revid(void) |
| @@ -154,6 +178,8 @@ static inline uint32_t __pure bfin_compiled_revid(void) | |||
| 154 | return 4; | 178 | return 4; |
| 155 | #elif defined(CONFIG_BF_REV_0_5) | 179 | #elif defined(CONFIG_BF_REV_0_5) |
| 156 | return 5; | 180 | return 5; |
| 181 | #elif defined(CONFIG_BF_REV_0_6) | ||
| 182 | return 6; | ||
| 157 | #elif defined(CONFIG_BF_REV_ANY) | 183 | #elif defined(CONFIG_BF_REV_ANY) |
| 158 | return 0xffff; | 184 | return 0xffff; |
| 159 | #else | 185 | #else |
diff --git a/arch/blackfin/include/asm/reboot.h b/arch/blackfin/include/asm/reboot.h index 6d448b5f5985..4856d62b7467 100644 --- a/arch/blackfin/include/asm/reboot.h +++ b/arch/blackfin/include/asm/reboot.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/asm-blackfin/reboot.h - shutdown/reboot header | 2 | * reboot.h - shutdown/reboot header |
| 3 | * | 3 | * |
| 4 | * Copyright 2004-2007 Analog Devices Inc. | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 5 | * | 5 | * |
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
diff --git a/arch/blackfin/include/asm/rwlock.h b/arch/blackfin/include/asm/rwlock.h new file mode 100644 index 000000000000..4a724b378971 --- /dev/null +++ b/arch/blackfin/include/asm/rwlock.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_BLACKFIN_RWLOCK_H | ||
| 2 | #define _ASM_BLACKFIN_RWLOCK_H | ||
| 3 | |||
| 4 | #define RW_LOCK_BIAS 0x01000000 | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h index 994dd869558c..3a47606c858b 100644 --- a/arch/blackfin/include/asm/serial.h +++ b/arch/blackfin/include/asm/serial.h | |||
| @@ -3,3 +3,4 @@ | |||
| 3 | */ | 3 | */ |
| 4 | 4 | ||
| 5 | #define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH | 5 | #define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH |
| 6 | #define BASE_BAUD (1843200 / 16) | ||
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h new file mode 100644 index 000000000000..118deeeae7c0 --- /dev/null +++ b/arch/blackfin/include/asm/smp.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/include/asm/smp.h | ||
| 3 | * Author: Philippe Gerum <rpm@xenomai.org> | ||
| 4 | * | ||
| 5 | * Copyright 2007 Analog Devices Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, see the file COPYING, or write | ||
| 19 | * to the Free Software Foundation, Inc., | ||
| 20 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __ASM_BLACKFIN_SMP_H | ||
| 24 | #define __ASM_BLACKFIN_SMP_H | ||
| 25 | |||
| 26 | #include <linux/kernel.h> | ||
| 27 | #include <linux/threads.h> | ||
| 28 | #include <linux/cpumask.h> | ||
| 29 | #include <linux/cache.h> | ||
| 30 | #include <asm/blackfin.h> | ||
| 31 | #include <mach/smp.h> | ||
| 32 | |||
| 33 | #define raw_smp_processor_id() blackfin_core_id() | ||
| 34 | |||
| 35 | extern char coreb_trampoline_start, coreb_trampoline_end; | ||
| 36 | |||
| 37 | struct corelock_slot { | ||
| 38 | int lock; | ||
| 39 | }; | ||
| 40 | |||
| 41 | void smp_icache_flush_range_others(unsigned long start, | ||
| 42 | unsigned long end); | ||
| 43 | |||
| 44 | #endif /* !__ASM_BLACKFIN_SMP_H */ | ||
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h index 64e908a50646..0249ac319476 100644 --- a/arch/blackfin/include/asm/spinlock.h +++ b/arch/blackfin/include/asm/spinlock.h | |||
| @@ -1,6 +1,89 @@ | |||
| 1 | #ifndef __BFIN_SPINLOCK_H | 1 | #ifndef __BFIN_SPINLOCK_H |
| 2 | #define __BFIN_SPINLOCK_H | 2 | #define __BFIN_SPINLOCK_H |
| 3 | 3 | ||
| 4 | #error blackfin architecture does not support SMP spin lock yet | 4 | #include <asm/atomic.h> |
| 5 | 5 | ||
| 6 | #endif | 6 | asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr); |
| 7 | asmlinkage void __raw_spin_lock_asm(volatile int *ptr); | ||
| 8 | asmlinkage int __raw_spin_trylock_asm(volatile int *ptr); | ||
| 9 | asmlinkage void __raw_spin_unlock_asm(volatile int *ptr); | ||
| 10 | asmlinkage void __raw_read_lock_asm(volatile int *ptr); | ||
| 11 | asmlinkage int __raw_read_trylock_asm(volatile int *ptr); | ||
| 12 | asmlinkage void __raw_read_unlock_asm(volatile int *ptr); | ||
| 13 | asmlinkage void __raw_write_lock_asm(volatile int *ptr); | ||
| 14 | asmlinkage int __raw_write_trylock_asm(volatile int *ptr); | ||
| 15 | asmlinkage void __raw_write_unlock_asm(volatile int *ptr); | ||
| 16 | |||
| 17 | static inline int __raw_spin_is_locked(raw_spinlock_t *lock) | ||
| 18 | { | ||
| 19 | return __raw_spin_is_locked_asm(&lock->lock); | ||
| 20 | } | ||
| 21 | |||
| 22 | static inline void __raw_spin_lock(raw_spinlock_t *lock) | ||
| 23 | { | ||
| 24 | __raw_spin_lock_asm(&lock->lock); | ||
| 25 | } | ||
| 26 | |||
| 27 | #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) | ||
| 28 | |||
| 29 | static inline int __raw_spin_trylock(raw_spinlock_t *lock) | ||
| 30 | { | ||
| 31 | return __raw_spin_trylock_asm(&lock->lock); | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) | ||
| 35 | { | ||
| 36 | __raw_spin_unlock_asm(&lock->lock); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) | ||
| 40 | { | ||
| 41 | while (__raw_spin_is_locked(lock)) | ||
| 42 | cpu_relax(); | ||
| 43 | } | ||
| 44 | |||
| 45 | static inline int __raw_read_can_lock(raw_rwlock_t *rw) | ||
| 46 | { | ||
| 47 | return __raw_uncached_fetch_asm(&rw->lock) > 0; | ||
| 48 | } | ||
| 49 | |||
| 50 | static inline int __raw_write_can_lock(raw_rwlock_t *rw) | ||
| 51 | { | ||
| 52 | return __raw_uncached_fetch_asm(&rw->lock) == RW_LOCK_BIAS; | ||
| 53 | } | ||
| 54 | |||
| 55 | static inline void __raw_read_lock(raw_rwlock_t *rw) | ||
| 56 | { | ||
| 57 | __raw_read_lock_asm(&rw->lock); | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline int __raw_read_trylock(raw_rwlock_t *rw) | ||
| 61 | { | ||
| 62 | return __raw_read_trylock_asm(&rw->lock); | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline void __raw_read_unlock(raw_rwlock_t *rw) | ||
| 66 | { | ||
| 67 | __raw_read_unlock_asm(&rw->lock); | ||
| 68 | } | ||
| 69 | |||
| 70 | static inline void __raw_write_lock(raw_rwlock_t *rw) | ||
| 71 | { | ||
| 72 | __raw_write_lock_asm(&rw->lock); | ||
| 73 | } | ||
| 74 | |||
| 75 | static inline int __raw_write_trylock(raw_rwlock_t *rw) | ||
| 76 | { | ||
| 77 | return __raw_write_trylock_asm(&rw->lock); | ||
| 78 | } | ||
| 79 | |||
| 80 | static inline void __raw_write_unlock(raw_rwlock_t *rw) | ||
| 81 | { | ||
| 82 | __raw_write_unlock_asm(&rw->lock); | ||
| 83 | } | ||
| 84 | |||
| 85 | #define _raw_spin_relax(lock) cpu_relax() | ||
| 86 | #define _raw_read_relax(lock) cpu_relax() | ||
| 87 | #define _raw_write_relax(lock) cpu_relax() | ||
| 88 | |||
| 89 | #endif /* !__BFIN_SPINLOCK_H */ | ||
diff --git a/arch/blackfin/include/asm/spinlock_types.h b/arch/blackfin/include/asm/spinlock_types.h new file mode 100644 index 000000000000..b1e3c4c7b382 --- /dev/null +++ b/arch/blackfin/include/asm/spinlock_types.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | #ifndef __ASM_SPINLOCK_TYPES_H | ||
| 2 | #define __ASM_SPINLOCK_TYPES_H | ||
| 3 | |||
| 4 | #ifndef __LINUX_SPINLOCK_TYPES_H | ||
| 5 | # error "please don't include this file directly" | ||
| 6 | #endif | ||
| 7 | |||
| 8 | #include <asm/rwlock.h> | ||
| 9 | |||
| 10 | typedef struct { | ||
| 11 | volatile unsigned int lock; | ||
| 12 | } raw_spinlock_t; | ||
| 13 | |||
| 14 | #define __RAW_SPIN_LOCK_UNLOCKED { 0 } | ||
| 15 | |||
| 16 | typedef struct { | ||
| 17 | volatile unsigned int lock; | ||
| 18 | } raw_rwlock_t; | ||
| 19 | |||
| 20 | #define __RAW_RW_LOCK_UNLOCKED { RW_LOCK_BIAS } | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index 8f1627d8bf09..a4c8254bec55 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h | |||
| @@ -37,114 +37,98 @@ | |||
| 37 | #include <linux/linkage.h> | 37 | #include <linux/linkage.h> |
| 38 | #include <linux/compiler.h> | 38 | #include <linux/compiler.h> |
| 39 | #include <mach/anomaly.h> | 39 | #include <mach/anomaly.h> |
| 40 | #include <asm/pda.h> | ||
| 41 | #include <asm/processor.h> | ||
| 42 | #include <asm/irq.h> | ||
| 40 | 43 | ||
| 41 | /* | 44 | /* |
| 42 | * Interrupt configuring macros. | 45 | * Force strict CPU ordering. |
| 43 | */ | 46 | */ |
| 47 | #define nop() __asm__ __volatile__ ("nop;\n\t" : : ) | ||
| 48 | #define mb() __asm__ __volatile__ ("" : : : "memory") | ||
| 49 | #define rmb() __asm__ __volatile__ ("" : : : "memory") | ||
| 50 | #define wmb() __asm__ __volatile__ ("" : : : "memory") | ||
| 51 | #define set_mb(var, value) do { (void) xchg(&var, value); } while (0) | ||
| 52 | #define read_barrier_depends() do { } while(0) | ||
| 44 | 53 | ||
| 45 | extern unsigned long irq_flags; | 54 | #ifdef CONFIG_SMP |
| 46 | 55 | asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value); | |
| 47 | #define local_irq_enable() \ | 56 | asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value); |
| 48 | __asm__ __volatile__( \ | 57 | asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value); |
| 49 | "sti %0;" \ | 58 | asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr, |
| 50 | : \ | 59 | unsigned long new, unsigned long old); |
| 51 | : "d" (irq_flags) \ | 60 | asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr, |
| 52 | ) | 61 | unsigned long new, unsigned long old); |
| 53 | 62 | asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr, | |
| 54 | #define local_irq_disable() \ | 63 | unsigned long new, unsigned long old); |
| 55 | do { \ | 64 | |
| 56 | int __tmp_dummy; \ | 65 | #ifdef __ARCH_SYNC_CORE_DCACHE |
| 57 | __asm__ __volatile__( \ | 66 | # define smp_mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) |
| 58 | "cli %0;" \ | 67 | # define smp_rmb() do { barrier(); smp_check_barrier(); } while (0) |
| 59 | : "=d" (__tmp_dummy) \ | 68 | # define smp_wmb() do { barrier(); smp_mark_barrier(); } while (0) |
| 60 | ); \ | 69 | #define smp_read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) |
| 61 | } while (0) | ||
| 62 | |||
| 63 | #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) | ||
| 64 | # define NOP_PAD_ANOMALY_05000244 "nop; nop;" | ||
| 65 | #else | ||
| 66 | # define NOP_PAD_ANOMALY_05000244 | ||
| 67 | #endif | ||
| 68 | |||
| 69 | #define idle_with_irq_disabled() \ | ||
| 70 | __asm__ __volatile__( \ | ||
| 71 | NOP_PAD_ANOMALY_05000244 \ | ||
| 72 | ".align 8;" \ | ||
| 73 | "sti %0;" \ | ||
| 74 | "idle;" \ | ||
| 75 | : \ | ||
| 76 | : "d" (irq_flags) \ | ||
| 77 | ) | ||
| 78 | |||
| 79 | #ifdef CONFIG_DEBUG_HWERR | ||
| 80 | # define __save_and_cli(x) \ | ||
| 81 | __asm__ __volatile__( \ | ||
| 82 | "cli %0;" \ | ||
| 83 | "sti %1;" \ | ||
| 84 | : "=&d" (x) \ | ||
| 85 | : "d" (0x3F) \ | ||
| 86 | ) | ||
| 87 | #else | ||
| 88 | # define __save_and_cli(x) \ | ||
| 89 | __asm__ __volatile__( \ | ||
| 90 | "cli %0;" \ | ||
| 91 | : "=&d" (x) \ | ||
| 92 | ) | ||
| 93 | #endif | ||
| 94 | |||
| 95 | #define local_save_flags(x) \ | ||
| 96 | __asm__ __volatile__( \ | ||
| 97 | "cli %0;" \ | ||
| 98 | "sti %0;" \ | ||
| 99 | : "=d" (x) \ | ||
| 100 | ) | ||
| 101 | 70 | ||
| 102 | #ifdef CONFIG_DEBUG_HWERR | ||
| 103 | #define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0) | ||
| 104 | #else | 71 | #else |
| 105 | #define irqs_enabled_from_flags(x) ((x) != 0x1f) | 72 | # define smp_mb() barrier() |
| 73 | # define smp_rmb() barrier() | ||
| 74 | # define smp_wmb() barrier() | ||
| 75 | #define smp_read_barrier_depends() barrier() | ||
| 106 | #endif | 76 | #endif |
| 107 | 77 | ||
| 108 | #define local_irq_restore(x) \ | 78 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, |
| 109 | do { \ | 79 | int size) |
| 110 | if (irqs_enabled_from_flags(x)) \ | 80 | { |
| 111 | local_irq_enable(); \ | 81 | unsigned long tmp; |
| 112 | } while (0) | ||
| 113 | 82 | ||
| 114 | /* For spinlocks etc */ | 83 | switch (size) { |
| 115 | #define local_irq_save(x) __save_and_cli(x) | 84 | case 1: |
| 85 | tmp = __raw_xchg_1_asm(ptr, x); | ||
| 86 | break; | ||
| 87 | case 2: | ||
| 88 | tmp = __raw_xchg_2_asm(ptr, x); | ||
| 89 | break; | ||
| 90 | case 4: | ||
| 91 | tmp = __raw_xchg_4_asm(ptr, x); | ||
| 92 | break; | ||
| 93 | } | ||
| 116 | 94 | ||
| 117 | #define irqs_disabled() \ | 95 | return tmp; |
| 118 | ({ \ | 96 | } |
| 119 | unsigned long flags; \ | ||
| 120 | local_save_flags(flags); \ | ||
| 121 | !irqs_enabled_from_flags(flags); \ | ||
| 122 | }) | ||
| 123 | 97 | ||
| 124 | /* | 98 | /* |
| 125 | * Force strict CPU ordering. | 99 | * Atomic compare and exchange. Compare OLD with MEM, if identical, |
| 100 | * store NEW in MEM. Return the initial value in MEM. Success is | ||
| 101 | * indicated by comparing RETURN with OLD. | ||
| 126 | */ | 102 | */ |
| 127 | #define nop() asm volatile ("nop;\n\t"::) | 103 | static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, |
| 128 | #define mb() asm volatile ("" : : :"memory") | 104 | unsigned long new, int size) |
| 129 | #define rmb() asm volatile ("" : : :"memory") | 105 | { |
| 130 | #define wmb() asm volatile ("" : : :"memory") | 106 | unsigned long tmp; |
| 131 | #define set_mb(var, value) do { (void) xchg(&var, value); } while (0) | ||
| 132 | 107 | ||
| 133 | #define read_barrier_depends() do { } while(0) | 108 | switch (size) { |
| 109 | case 1: | ||
| 110 | tmp = __raw_cmpxchg_1_asm(ptr, new, old); | ||
| 111 | break; | ||
| 112 | case 2: | ||
| 113 | tmp = __raw_cmpxchg_2_asm(ptr, new, old); | ||
| 114 | break; | ||
| 115 | case 4: | ||
| 116 | tmp = __raw_cmpxchg_4_asm(ptr, new, old); | ||
| 117 | break; | ||
| 118 | } | ||
| 119 | |||
| 120 | return tmp; | ||
| 121 | } | ||
| 122 | #define cmpxchg(ptr, o, n) \ | ||
| 123 | ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ | ||
| 124 | (unsigned long)(n), sizeof(*(ptr)))) | ||
| 125 | |||
| 126 | #else /* !CONFIG_SMP */ | ||
| 134 | 127 | ||
| 135 | #ifdef CONFIG_SMP | ||
| 136 | #define smp_mb() mb() | ||
| 137 | #define smp_rmb() rmb() | ||
| 138 | #define smp_wmb() wmb() | ||
| 139 | #define smp_read_barrier_depends() read_barrier_depends() | ||
| 140 | #else | ||
| 141 | #define smp_mb() barrier() | 128 | #define smp_mb() barrier() |
| 142 | #define smp_rmb() barrier() | 129 | #define smp_rmb() barrier() |
| 143 | #define smp_wmb() barrier() | 130 | #define smp_wmb() barrier() |
| 144 | #define smp_read_barrier_depends() do { } while(0) | 131 | #define smp_read_barrier_depends() do { } while(0) |
| 145 | #endif | ||
| 146 | |||
| 147 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | ||
| 148 | 132 | ||
| 149 | struct __xchg_dummy { | 133 | struct __xchg_dummy { |
| 150 | unsigned long a[100]; | 134 | unsigned long a[100]; |
| @@ -157,7 +141,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, | |||
| 157 | unsigned long tmp = 0; | 141 | unsigned long tmp = 0; |
| 158 | unsigned long flags = 0; | 142 | unsigned long flags = 0; |
| 159 | 143 | ||
| 160 | local_irq_save(flags); | 144 | local_irq_save_hw(flags); |
| 161 | 145 | ||
| 162 | switch (size) { | 146 | switch (size) { |
| 163 | case 1: | 147 | case 1: |
| @@ -179,7 +163,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, | |||
| 179 | : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); | 163 | : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); |
| 180 | break; | 164 | break; |
| 181 | } | 165 | } |
| 182 | local_irq_restore(flags); | 166 | local_irq_restore_hw(flags); |
| 183 | return tmp; | 167 | return tmp; |
| 184 | } | 168 | } |
| 185 | 169 | ||
| @@ -194,9 +178,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, | |||
| 194 | (unsigned long)(n), sizeof(*(ptr)))) | 178 | (unsigned long)(n), sizeof(*(ptr)))) |
| 195 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | 179 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) |
| 196 | 180 | ||
| 197 | #ifndef CONFIG_SMP | ||
| 198 | #include <asm-generic/cmpxchg.h> | 181 | #include <asm-generic/cmpxchg.h> |
| 199 | #endif | 182 | |
| 183 | #endif /* !CONFIG_SMP */ | ||
| 184 | |||
| 185 | #define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) | ||
| 186 | #define tas(ptr) ((void)xchg((ptr), 1)) | ||
| 200 | 187 | ||
| 201 | #define prepare_to_switch() do { } while(0) | 188 | #define prepare_to_switch() do { } while(0) |
| 202 | 189 | ||
| @@ -205,10 +192,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, | |||
| 205 | * ptr isn't the current task, in which case it does nothing. | 192 | * ptr isn't the current task, in which case it does nothing. |
| 206 | */ | 193 | */ |
| 207 | 194 | ||
| 208 | #include <asm/blackfin.h> | 195 | #include <asm/l1layout.h> |
| 196 | #include <asm/mem_map.h> | ||
| 209 | 197 | ||
| 210 | asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next); | 198 | asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next); |
| 211 | 199 | ||
| 200 | #ifndef CONFIG_SMP | ||
| 212 | #define switch_to(prev,next,last) \ | 201 | #define switch_to(prev,next,last) \ |
| 213 | do { \ | 202 | do { \ |
| 214 | memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \ | 203 | memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \ |
| @@ -217,5 +206,11 @@ do { \ | |||
| 217 | sizeof *L1_SCRATCH_TASK_INFO); \ | 206 | sizeof *L1_SCRATCH_TASK_INFO); \ |
| 218 | (last) = resume (prev, next); \ | 207 | (last) = resume (prev, next); \ |
| 219 | } while (0) | 208 | } while (0) |
| 209 | #else | ||
| 210 | #define switch_to(prev, next, last) \ | ||
| 211 | do { \ | ||
| 212 | (last) = resume(prev, next); \ | ||
| 213 | } while (0) | ||
| 214 | #endif | ||
| 220 | 215 | ||
| 221 | #endif /* _BLACKFIN_SYSTEM_H */ | 216 | #endif /* _BLACKFIN_SYSTEM_H */ |
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h index 642769329d12..e721ce55956c 100644 --- a/arch/blackfin/include/asm/thread_info.h +++ b/arch/blackfin/include/asm/thread_info.h | |||
| @@ -44,6 +44,7 @@ | |||
| 44 | */ | 44 | */ |
| 45 | #define THREAD_SIZE_ORDER 1 | 45 | #define THREAD_SIZE_ORDER 1 |
| 46 | #define THREAD_SIZE 8192 /* 2 pages */ | 46 | #define THREAD_SIZE 8192 /* 2 pages */ |
| 47 | #define STACK_WARN (THREAD_SIZE/8) | ||
| 47 | 48 | ||
| 48 | #ifndef __ASSEMBLY__ | 49 | #ifndef __ASSEMBLY__ |
| 49 | 50 | ||
| @@ -62,7 +63,9 @@ struct thread_info { | |||
| 62 | int preempt_count; /* 0 => preemptable, <0 => BUG */ | 63 | int preempt_count; /* 0 => preemptable, <0 => BUG */ |
| 63 | mm_segment_t addr_limit; /* address limit */ | 64 | mm_segment_t addr_limit; /* address limit */ |
| 64 | struct restart_block restart_block; | 65 | struct restart_block restart_block; |
| 66 | #ifndef CONFIG_SMP | ||
| 65 | struct l1_scratch_task_info l1_task_info; | 67 | struct l1_scratch_task_info l1_task_info; |
| 68 | #endif | ||
| 66 | }; | 69 | }; |
| 67 | 70 | ||
| 68 | /* | 71 | /* |
| @@ -90,7 +93,7 @@ __attribute_const__ | |||
| 90 | static inline struct thread_info *current_thread_info(void) | 93 | static inline struct thread_info *current_thread_info(void) |
| 91 | { | 94 | { |
| 92 | struct thread_info *ti; | 95 | struct thread_info *ti; |
| 93 | __asm__("%0 = sp;": "=&d"(ti): | 96 | __asm__("%0 = sp;" : "=da"(ti) : |
| 94 | ); | 97 | ); |
| 95 | return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1)); | 98 | return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1)); |
| 96 | } | 99 | } |
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index d928b8099056..3248033531e6 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h | |||
| @@ -149,54 +149,42 @@ static inline int bad_user_access_length(void) | |||
| 149 | : /* no outputs */ \ | 149 | : /* no outputs */ \ |
| 150 | :"d" (x),"a" (__ptr(p)) : "memory") | 150 | :"d" (x),"a" (__ptr(p)) : "memory") |
| 151 | 151 | ||
| 152 | #define get_user(x,p) \ | 152 | #define get_user(x, ptr) \ |
| 153 | ({ \ | 153 | ({ \ |
| 154 | int _err = 0; \ | 154 | int _err = 0; \ |
| 155 | typeof(*(p)) *_p = (p); \ | 155 | unsigned long _val = 0; \ |
| 156 | if (!access_ok(VERIFY_READ, _p, sizeof(*(_p)))) { \ | 156 | const typeof(*(ptr)) __user *_p = (ptr); \ |
| 157 | _err = -EFAULT; \ | 157 | const size_t ptr_size = sizeof(*(_p)); \ |
| 158 | } \ | 158 | if (likely(access_ok(VERIFY_READ, _p, ptr_size))) { \ |
| 159 | else { \ | 159 | BUILD_BUG_ON(ptr_size >= 8); \ |
| 160 | switch (sizeof(*(_p))) { \ | 160 | switch (ptr_size) { \ |
| 161 | case 1: \ | 161 | case 1: \ |
| 162 | __get_user_asm(x, _p, B,(Z)); \ | 162 | __get_user_asm(_val, _p, B,(Z)); \ |
| 163 | break; \ | 163 | break; \ |
| 164 | case 2: \ | 164 | case 2: \ |
| 165 | __get_user_asm(x, _p, W,(Z)); \ | 165 | __get_user_asm(_val, _p, W,(Z)); \ |
| 166 | break; \ | 166 | break; \ |
| 167 | case 4: \ | 167 | case 4: \ |
| 168 | __get_user_asm(x, _p, , ); \ | 168 | __get_user_asm(_val, _p, , ); \ |
| 169 | break; \ | 169 | break; \ |
| 170 | case 8: { \ | 170 | } \ |
| 171 | unsigned long _xl, _xh; \ | 171 | } else \ |
| 172 | __get_user_asm(_xl, ((unsigned long *)_p)+0, , ); \ | 172 | _err = -EFAULT; \ |
| 173 | __get_user_asm(_xh, ((unsigned long *)_p)+1, , ); \ | 173 | x = (typeof(*(ptr)))_val; \ |
| 174 | ((unsigned long *)&x)[0] = _xl; \ | 174 | _err; \ |
| 175 | ((unsigned long *)&x)[1] = _xh; \ | 175 | }) |
| 176 | } break; \ | ||
| 177 | default: \ | ||
| 178 | x = 0; \ | ||
| 179 | printk(KERN_INFO "get_user_bad: %s:%d %s\n", \ | ||
| 180 | __FILE__, __LINE__, __func__); \ | ||
| 181 | _err = __get_user_bad(); \ | ||
| 182 | break; \ | ||
| 183 | } \ | ||
| 184 | } \ | ||
| 185 | _err; \ | ||
| 186 | }) | ||
| 187 | 176 | ||
| 188 | #define __get_user(x,p) get_user(x,p) | 177 | #define __get_user(x,p) get_user(x,p) |
| 189 | 178 | ||
| 190 | #define __get_user_bad() (bad_user_access_length(), (-EFAULT)) | 179 | #define __get_user_bad() (bad_user_access_length(), (-EFAULT)) |
| 191 | 180 | ||
| 192 | #define __get_user_asm(x,p,bhw,option) \ | 181 | #define __get_user_asm(x, ptr, bhw, option) \ |
| 193 | { \ | 182 | ({ \ |
| 194 | unsigned long _tmp; \ | 183 | __asm__ __volatile__ ( \ |
| 195 | __asm__ ("%0 =" #bhw "[%1]"#option";\n\t" \ | 184 | "%0 =" #bhw "[%1]" #option ";" \ |
| 196 | : "=d" (_tmp) \ | 185 | : "=d" (x) \ |
| 197 | : "a" (__ptr(p))); \ | 186 | : "a" (__ptr(ptr))); \ |
| 198 | (x) = (__typeof__(*(p))) _tmp; \ | 187 | }) |
| 199 | } | ||
| 200 | 188 | ||
| 201 | #define __copy_from_user(to, from, n) copy_from_user(to, from, n) | 189 | #define __copy_from_user(to, from, n) copy_from_user(to, from, n) |
| 202 | #define __copy_to_user(to, from, n) copy_to_user(to, from, n) | 190 | #define __copy_to_user(to, from, n) copy_to_user(to, from, n) |
| @@ -209,8 +197,8 @@ static inline int bad_user_access_length(void) | |||
| 209 | #define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\ | 197 | #define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\ |
| 210 | return retval; }) | 198 | return retval; }) |
| 211 | 199 | ||
| 212 | static inline long copy_from_user(void *to, | 200 | static inline unsigned long __must_check |
| 213 | const void __user * from, unsigned long n) | 201 | copy_from_user(void *to, const void __user *from, unsigned long n) |
| 214 | { | 202 | { |
| 215 | if (access_ok(VERIFY_READ, from, n)) | 203 | if (access_ok(VERIFY_READ, from, n)) |
| 216 | memcpy(to, from, n); | 204 | memcpy(to, from, n); |
| @@ -219,8 +207,8 @@ static inline long copy_from_user(void *to, | |||
| 219 | return 0; | 207 | return 0; |
| 220 | } | 208 | } |
| 221 | 209 | ||
| 222 | static inline long copy_to_user(void *to, | 210 | static inline unsigned long __must_check |
| 223 | const void __user * from, unsigned long n) | 211 | copy_to_user(void *to, const void __user *from, unsigned long n) |
| 224 | { | 212 | { |
| 225 | if (access_ok(VERIFY_WRITE, to, n)) | 213 | if (access_ok(VERIFY_WRITE, to, n)) |
| 226 | memcpy(to, from, n); | 214 | memcpy(to, from, n); |
| @@ -233,8 +221,8 @@ static inline long copy_to_user(void *to, | |||
| 233 | * Copy a null terminated string from userspace. | 221 | * Copy a null terminated string from userspace. |
| 234 | */ | 222 | */ |
| 235 | 223 | ||
| 236 | static inline long strncpy_from_user(char *dst, | 224 | static inline long __must_check |
| 237 | const char *src, long count) | 225 | strncpy_from_user(char *dst, const char *src, long count) |
| 238 | { | 226 | { |
| 239 | char *tmp; | 227 | char *tmp; |
| 240 | if (!access_ok(VERIFY_READ, src, 1)) | 228 | if (!access_ok(VERIFY_READ, src, 1)) |
| @@ -260,7 +248,8 @@ static inline long strnlen_user(const char *src, long n) | |||
| 260 | * Zero Userspace | 248 | * Zero Userspace |
| 261 | */ | 249 | */ |
| 262 | 250 | ||
| 263 | static inline unsigned long __clear_user(void *to, unsigned long n) | 251 | static inline unsigned long __must_check |
| 252 | __clear_user(void *to, unsigned long n) | ||
| 264 | { | 253 | { |
| 265 | memset(to, 0, n); | 254 | memset(to, 0, n); |
| 266 | return 0; | 255 | return 0; |
diff --git a/arch/blackfin/include/asm/xor.h b/arch/blackfin/include/asm/xor.h new file mode 100644 index 000000000000..c82eb12a5b18 --- /dev/null +++ b/arch/blackfin/include/asm/xor.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/xor.h> | |||
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 606adc78aa85..38a233374f07 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile | |||
| @@ -7,7 +7,7 @@ extra-y := init_task.o vmlinux.lds | |||
| 7 | obj-y := \ | 7 | obj-y := \ |
| 8 | entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ | 8 | entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ |
| 9 | sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ | 9 | sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ |
| 10 | fixed_code.o reboot.o bfin_gpio.o | 10 | fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o |
| 11 | 11 | ||
| 12 | ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) | 12 | ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) |
| 13 | obj-y += time-ts.o | 13 | obj-y += time-ts.o |
| @@ -15,8 +15,11 @@ else | |||
| 15 | obj-y += time.o | 15 | obj-y += time.o |
| 16 | endif | 16 | endif |
| 17 | 17 | ||
| 18 | obj-$(CONFIG_IPIPE) += ipipe.o | ||
| 19 | obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o | ||
| 18 | obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o | 20 | obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o |
| 21 | obj-$(CONFIG_CPLB_INFO) += cplbinfo.o | ||
| 19 | obj-$(CONFIG_MODULES) += module.o | 22 | obj-$(CONFIG_MODULES) += module.o |
| 20 | obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o | ||
| 21 | obj-$(CONFIG_KGDB) += kgdb.o | 23 | obj-$(CONFIG_KGDB) += kgdb.o |
| 24 | obj-$(CONFIG_KGDB_TESTCASE) += kgdb_test.o | ||
| 22 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o | 25 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c index 9bb85dd5ccb3..b5df9459d6d5 100644 --- a/arch/blackfin/kernel/asm-offsets.c +++ b/arch/blackfin/kernel/asm-offsets.c | |||
| @@ -56,6 +56,9 @@ int main(void) | |||
| 56 | /* offsets into the thread struct */ | 56 | /* offsets into the thread struct */ |
| 57 | DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp)); | 57 | DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp)); |
| 58 | DEFINE(THREAD_USP, offsetof(struct thread_struct, usp)); | 58 | DEFINE(THREAD_USP, offsetof(struct thread_struct, usp)); |
| 59 | DEFINE(THREAD_SR, offsetof(struct thread_struct, seqstat)); | ||
| 60 | DEFINE(PT_SR, offsetof(struct thread_struct, seqstat)); | ||
| 61 | DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0)); | ||
| 59 | DEFINE(THREAD_PC, offsetof(struct thread_struct, pc)); | 62 | DEFINE(THREAD_PC, offsetof(struct thread_struct, pc)); |
| 60 | DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE); | 63 | DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE); |
| 61 | 64 | ||
| @@ -128,5 +131,31 @@ int main(void) | |||
| 128 | DEFINE(SIGSEGV, SIGSEGV); | 131 | DEFINE(SIGSEGV, SIGSEGV); |
| 129 | DEFINE(SIGTRAP, SIGTRAP); | 132 | DEFINE(SIGTRAP, SIGTRAP); |
| 130 | 133 | ||
| 134 | /* PDA management (in L1 scratchpad) */ | ||
| 135 | DEFINE(PDA_SYSCFG, offsetof(struct blackfin_pda, syscfg)); | ||
| 136 | #ifdef CONFIG_SMP | ||
| 137 | DEFINE(PDA_IRQFLAGS, offsetof(struct blackfin_pda, imask)); | ||
| 138 | #endif | ||
| 139 | DEFINE(PDA_IPDT, offsetof(struct blackfin_pda, ipdt)); | ||
| 140 | DEFINE(PDA_IPDT_SWAPCOUNT, offsetof(struct blackfin_pda, ipdt_swapcount)); | ||
| 141 | DEFINE(PDA_DPDT, offsetof(struct blackfin_pda, dpdt)); | ||
| 142 | DEFINE(PDA_DPDT_SWAPCOUNT, offsetof(struct blackfin_pda, dpdt_swapcount)); | ||
| 143 | DEFINE(PDA_EXIPTR, offsetof(struct blackfin_pda, ex_iptr)); | ||
| 144 | DEFINE(PDA_EXOPTR, offsetof(struct blackfin_pda, ex_optr)); | ||
| 145 | DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf)); | ||
| 146 | DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask)); | ||
| 147 | DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack)); | ||
| 148 | #ifdef ANOMALY_05000261 | ||
| 149 | DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx)); | ||
| 150 | #endif | ||
| 151 | DEFINE(PDA_DCPLB, offsetof(struct blackfin_pda, dcplb_fault_addr)); | ||
| 152 | DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr)); | ||
| 153 | DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx)); | ||
| 154 | DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat)); | ||
| 155 | #ifdef CONFIG_SMP | ||
| 156 | /* Inter-core lock (in L2 SRAM) */ | ||
| 157 | DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot)); | ||
| 158 | #endif | ||
| 159 | |||
| 131 | return 0; | 160 | return 0; |
| 132 | } | 161 | } |
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c index 339293d677cc..07e02c0d1c07 100644 --- a/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/arch/blackfin/kernel/bfin_dma_5xx.c | |||
| @@ -1,63 +1,27 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: arch/blackfin/kernel/bfin_dma_5xx.c | 2 | * bfin_dma_5xx.c - Blackfin DMA implementation |
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | 3 | * |
| 6 | * Created: | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 7 | * Description: This file contains the simple DMA Implementation for Blackfin | 5 | * Licensed under the GPL-2 or later. |
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | 6 | */ |
| 29 | 7 | ||
| 30 | #include <linux/errno.h> | 8 | #include <linux/errno.h> |
| 31 | #include <linux/module.h> | ||
| 32 | #include <linux/sched.h> | ||
| 33 | #include <linux/interrupt.h> | 9 | #include <linux/interrupt.h> |
| 34 | #include <linux/kernel.h> | 10 | #include <linux/kernel.h> |
| 11 | #include <linux/module.h> | ||
| 35 | #include <linux/param.h> | 12 | #include <linux/param.h> |
| 13 | #include <linux/proc_fs.h> | ||
| 14 | #include <linux/sched.h> | ||
| 15 | #include <linux/seq_file.h> | ||
| 16 | #include <linux/spinlock.h> | ||
| 36 | 17 | ||
| 37 | #include <asm/blackfin.h> | 18 | #include <asm/blackfin.h> |
| 38 | #include <asm/dma.h> | ||
| 39 | #include <asm/cacheflush.h> | 19 | #include <asm/cacheflush.h> |
| 20 | #include <asm/dma.h> | ||
| 21 | #include <asm/uaccess.h> | ||
| 40 | 22 | ||
| 41 | /* Remove unused code not exported by symbol or internally called */ | 23 | struct dma_channel dma_ch[MAX_DMA_CHANNELS]; |
| 42 | #define REMOVE_DEAD_CODE | 24 | EXPORT_SYMBOL(dma_ch); |
| 43 | |||
| 44 | /************************************************************************** | ||
| 45 | * Global Variables | ||
| 46 | ***************************************************************************/ | ||
| 47 | |||
| 48 | static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL]; | ||
| 49 | |||
| 50 | /*------------------------------------------------------------------------------ | ||
| 51 | * Set the Buffer Clear bit in the Configuration register of specific DMA | ||
| 52 | * channel. This will stop the descriptor based DMA operation. | ||
| 53 | *-----------------------------------------------------------------------------*/ | ||
| 54 | static void clear_dma_buffer(unsigned int channel) | ||
| 55 | { | ||
| 56 | dma_ch[channel].regs->cfg |= RESTART; | ||
| 57 | SSYNC(); | ||
| 58 | dma_ch[channel].regs->cfg &= ~RESTART; | ||
| 59 | SSYNC(); | ||
| 60 | } | ||
| 61 | 25 | ||
| 62 | static int __init blackfin_dma_init(void) | 26 | static int __init blackfin_dma_init(void) |
| 63 | { | 27 | { |
| @@ -65,32 +29,67 @@ static int __init blackfin_dma_init(void) | |||
| 65 | 29 | ||
| 66 | printk(KERN_INFO "Blackfin DMA Controller\n"); | 30 | printk(KERN_INFO "Blackfin DMA Controller\n"); |
| 67 | 31 | ||
| 68 | for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) { | 32 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { |
| 69 | dma_ch[i].chan_status = DMA_CHANNEL_FREE; | 33 | dma_ch[i].chan_status = DMA_CHANNEL_FREE; |
| 70 | dma_ch[i].regs = dma_io_base_addr[i]; | 34 | dma_ch[i].regs = dma_io_base_addr[i]; |
| 71 | mutex_init(&(dma_ch[i].dmalock)); | 35 | mutex_init(&(dma_ch[i].dmalock)); |
| 72 | } | 36 | } |
| 73 | /* Mark MEMDMA Channel 0 as requested since we're using it internally */ | 37 | /* Mark MEMDMA Channel 0 as requested since we're using it internally */ |
| 74 | dma_ch[CH_MEM_STREAM0_DEST].chan_status = DMA_CHANNEL_REQUESTED; | 38 | request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); |
| 75 | dma_ch[CH_MEM_STREAM0_SRC].chan_status = DMA_CHANNEL_REQUESTED; | 39 | request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy"); |
| 76 | 40 | ||
| 77 | #if defined(CONFIG_DEB_DMA_URGENT) | 41 | #if defined(CONFIG_DEB_DMA_URGENT) |
| 78 | bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | 42 | bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() |
| 79 | | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT); | 43 | | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT); |
| 80 | #endif | 44 | #endif |
| 45 | |||
| 81 | return 0; | 46 | return 0; |
| 82 | } | 47 | } |
| 83 | |||
| 84 | arch_initcall(blackfin_dma_init); | 48 | arch_initcall(blackfin_dma_init); |
| 85 | 49 | ||
| 86 | /*------------------------------------------------------------------------------ | 50 | #ifdef CONFIG_PROC_FS |
| 87 | * Request the specific DMA channel from the system. | 51 | static int proc_dma_show(struct seq_file *m, void *v) |
| 88 | *-----------------------------------------------------------------------------*/ | ||
| 89 | int request_dma(unsigned int channel, char *device_id) | ||
| 90 | { | 52 | { |
| 53 | int i; | ||
| 54 | |||
| 55 | for (i = 0; i < MAX_DMA_CHANNELS; ++i) | ||
| 56 | if (dma_ch[i].chan_status != DMA_CHANNEL_FREE) | ||
| 57 | seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id); | ||
| 58 | |||
| 59 | return 0; | ||
| 60 | } | ||
| 91 | 61 | ||
| 62 | static int proc_dma_open(struct inode *inode, struct file *file) | ||
| 63 | { | ||
| 64 | return single_open(file, proc_dma_show, NULL); | ||
| 65 | } | ||
| 66 | |||
| 67 | static const struct file_operations proc_dma_operations = { | ||
| 68 | .open = proc_dma_open, | ||
| 69 | .read = seq_read, | ||
| 70 | .llseek = seq_lseek, | ||
| 71 | .release = single_release, | ||
| 72 | }; | ||
| 73 | |||
| 74 | static int __init proc_dma_init(void) | ||
| 75 | { | ||
| 76 | return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL; | ||
| 77 | } | ||
| 78 | late_initcall(proc_dma_init); | ||
| 79 | #endif | ||
| 80 | |||
| 81 | /** | ||
| 82 | * request_dma - request a DMA channel | ||
| 83 | * | ||
| 84 | * Request the specific DMA channel from the system if it's available. | ||
| 85 | */ | ||
| 86 | int request_dma(unsigned int channel, const char *device_id) | ||
| 87 | { | ||
| 92 | pr_debug("request_dma() : BEGIN \n"); | 88 | pr_debug("request_dma() : BEGIN \n"); |
| 93 | 89 | ||
| 90 | if (device_id == NULL) | ||
| 91 | printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel); | ||
| 92 | |||
| 94 | #if defined(CONFIG_BF561) && ANOMALY_05000182 | 93 | #if defined(CONFIG_BF561) && ANOMALY_05000182 |
| 95 | if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) { | 94 | if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) { |
| 96 | if (get_cclk() > 500000000) { | 95 | if (get_cclk() > 500000000) { |
| @@ -129,60 +128,63 @@ int request_dma(unsigned int channel, char *device_id) | |||
| 129 | #endif | 128 | #endif |
| 130 | 129 | ||
| 131 | dma_ch[channel].device_id = device_id; | 130 | dma_ch[channel].device_id = device_id; |
| 132 | dma_ch[channel].irq_callback = NULL; | 131 | dma_ch[channel].irq = 0; |
| 133 | 132 | ||
| 134 | /* This is to be enabled by putting a restriction - | 133 | /* This is to be enabled by putting a restriction - |
| 135 | * you have to request DMA, before doing any operations on | 134 | * you have to request DMA, before doing any operations on |
| 136 | * descriptor/channel | 135 | * descriptor/channel |
| 137 | */ | 136 | */ |
| 138 | pr_debug("request_dma() : END \n"); | 137 | pr_debug("request_dma() : END \n"); |
| 139 | return channel; | 138 | return 0; |
| 140 | } | 139 | } |
| 141 | EXPORT_SYMBOL(request_dma); | 140 | EXPORT_SYMBOL(request_dma); |
| 142 | 141 | ||
| 143 | int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data) | 142 | int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) |
| 144 | { | 143 | { |
| 145 | int ret_irq = 0; | ||
| 146 | |||
| 147 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | 144 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE |
| 148 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | 145 | && channel < MAX_DMA_CHANNELS)); |
| 149 | 146 | ||
| 150 | if (callback != NULL) { | 147 | if (callback != NULL) { |
| 151 | int ret_val; | 148 | int ret; |
| 152 | ret_irq = channel2irq(channel); | 149 | unsigned int irq = channel2irq(channel); |
| 153 | 150 | ||
| 154 | dma_ch[channel].data = data; | 151 | ret = request_irq(irq, callback, IRQF_DISABLED, |
| 152 | dma_ch[channel].device_id, data); | ||
| 153 | if (ret) | ||
| 154 | return ret; | ||
| 155 | 155 | ||
| 156 | ret_val = | 156 | dma_ch[channel].irq = irq; |
| 157 | request_irq(ret_irq, (void *)callback, IRQF_DISABLED, | 157 | dma_ch[channel].data = data; |
| 158 | dma_ch[channel].device_id, data); | ||
| 159 | if (ret_val) { | ||
| 160 | printk(KERN_NOTICE | ||
| 161 | "Request irq in DMA engine failed.\n"); | ||
| 162 | return -EPERM; | ||
| 163 | } | ||
| 164 | dma_ch[channel].irq_callback = callback; | ||
| 165 | } | 158 | } |
| 166 | return 0; | 159 | return 0; |
| 167 | } | 160 | } |
| 168 | EXPORT_SYMBOL(set_dma_callback); | 161 | EXPORT_SYMBOL(set_dma_callback); |
| 169 | 162 | ||
| 170 | void free_dma(unsigned int channel) | 163 | /** |
| 164 | * clear_dma_buffer - clear DMA fifos for specified channel | ||
| 165 | * | ||
| 166 | * Set the Buffer Clear bit in the Configuration register of specific DMA | ||
| 167 | * channel. This will stop the descriptor based DMA operation. | ||
| 168 | */ | ||
| 169 | static void clear_dma_buffer(unsigned int channel) | ||
| 171 | { | 170 | { |
| 172 | int ret_irq; | 171 | dma_ch[channel].regs->cfg |= RESTART; |
| 172 | SSYNC(); | ||
| 173 | dma_ch[channel].regs->cfg &= ~RESTART; | ||
| 174 | } | ||
| 173 | 175 | ||
| 176 | void free_dma(unsigned int channel) | ||
| 177 | { | ||
| 174 | pr_debug("freedma() : BEGIN \n"); | 178 | pr_debug("freedma() : BEGIN \n"); |
| 175 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | 179 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE |
| 176 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | 180 | && channel < MAX_DMA_CHANNELS)); |
| 177 | 181 | ||
| 178 | /* Halt the DMA */ | 182 | /* Halt the DMA */ |
| 179 | disable_dma(channel); | 183 | disable_dma(channel); |
| 180 | clear_dma_buffer(channel); | 184 | clear_dma_buffer(channel); |
| 181 | 185 | ||
| 182 | if (dma_ch[channel].irq_callback != NULL) { | 186 | if (dma_ch[channel].irq) |
| 183 | ret_irq = channel2irq(channel); | 187 | free_irq(dma_ch[channel].irq, dma_ch[channel].data); |
| 184 | free_irq(ret_irq, dma_ch[channel].data); | ||
| 185 | } | ||
| 186 | 188 | ||
| 187 | /* Clear the DMA Variable in the Channel */ | 189 | /* Clear the DMA Variable in the Channel */ |
| 188 | mutex_lock(&(dma_ch[channel].dmalock)); | 190 | mutex_lock(&(dma_ch[channel].dmalock)); |
| @@ -193,294 +195,15 @@ void free_dma(unsigned int channel) | |||
| 193 | } | 195 | } |
| 194 | EXPORT_SYMBOL(free_dma); | 196 | EXPORT_SYMBOL(free_dma); |
| 195 | 197 | ||
| 196 | void dma_enable_irq(unsigned int channel) | ||
| 197 | { | ||
| 198 | int ret_irq; | ||
| 199 | |||
| 200 | pr_debug("dma_enable_irq() : BEGIN \n"); | ||
| 201 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 202 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 203 | |||
| 204 | ret_irq = channel2irq(channel); | ||
| 205 | enable_irq(ret_irq); | ||
| 206 | } | ||
| 207 | EXPORT_SYMBOL(dma_enable_irq); | ||
| 208 | |||
| 209 | void dma_disable_irq(unsigned int channel) | ||
| 210 | { | ||
| 211 | int ret_irq; | ||
| 212 | |||
| 213 | pr_debug("dma_disable_irq() : BEGIN \n"); | ||
| 214 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 215 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 216 | |||
| 217 | ret_irq = channel2irq(channel); | ||
| 218 | disable_irq(ret_irq); | ||
| 219 | } | ||
| 220 | EXPORT_SYMBOL(dma_disable_irq); | ||
| 221 | |||
| 222 | int dma_channel_active(unsigned int channel) | ||
| 223 | { | ||
| 224 | if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) { | ||
| 225 | return 0; | ||
| 226 | } else { | ||
| 227 | return 1; | ||
| 228 | } | ||
| 229 | } | ||
| 230 | EXPORT_SYMBOL(dma_channel_active); | ||
| 231 | |||
| 232 | /*------------------------------------------------------------------------------ | ||
| 233 | * stop the specific DMA channel. | ||
| 234 | *-----------------------------------------------------------------------------*/ | ||
| 235 | void disable_dma(unsigned int channel) | ||
| 236 | { | ||
| 237 | pr_debug("stop_dma() : BEGIN \n"); | ||
| 238 | |||
| 239 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 240 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 241 | |||
| 242 | dma_ch[channel].regs->cfg &= ~DMAEN; /* Clean the enable bit */ | ||
| 243 | SSYNC(); | ||
| 244 | dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED; | ||
| 245 | /* Needs to be enabled Later */ | ||
| 246 | pr_debug("stop_dma() : END \n"); | ||
| 247 | return; | ||
| 248 | } | ||
| 249 | EXPORT_SYMBOL(disable_dma); | ||
| 250 | |||
| 251 | void enable_dma(unsigned int channel) | ||
| 252 | { | ||
| 253 | pr_debug("enable_dma() : BEGIN \n"); | ||
| 254 | |||
| 255 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 256 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 257 | |||
| 258 | dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED; | ||
| 259 | dma_ch[channel].regs->curr_x_count = 0; | ||
| 260 | dma_ch[channel].regs->curr_y_count = 0; | ||
| 261 | |||
| 262 | dma_ch[channel].regs->cfg |= DMAEN; /* Set the enable bit */ | ||
| 263 | SSYNC(); | ||
| 264 | pr_debug("enable_dma() : END \n"); | ||
| 265 | return; | ||
| 266 | } | ||
| 267 | EXPORT_SYMBOL(enable_dma); | ||
| 268 | |||
| 269 | /*------------------------------------------------------------------------------ | ||
| 270 | * Set the Start Address register for the specific DMA channel | ||
| 271 | * This function can be used for register based DMA, | ||
| 272 | * to setup the start address | ||
| 273 | * addr: Starting address of the DMA Data to be transferred. | ||
| 274 | *-----------------------------------------------------------------------------*/ | ||
| 275 | void set_dma_start_addr(unsigned int channel, unsigned long addr) | ||
| 276 | { | ||
| 277 | pr_debug("set_dma_start_addr() : BEGIN \n"); | ||
| 278 | |||
| 279 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 280 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 281 | |||
| 282 | dma_ch[channel].regs->start_addr = addr; | ||
| 283 | SSYNC(); | ||
| 284 | pr_debug("set_dma_start_addr() : END\n"); | ||
| 285 | } | ||
| 286 | EXPORT_SYMBOL(set_dma_start_addr); | ||
| 287 | |||
| 288 | void set_dma_next_desc_addr(unsigned int channel, unsigned long addr) | ||
| 289 | { | ||
| 290 | pr_debug("set_dma_next_desc_addr() : BEGIN \n"); | ||
| 291 | |||
| 292 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 293 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 294 | |||
| 295 | dma_ch[channel].regs->next_desc_ptr = addr; | ||
| 296 | SSYNC(); | ||
| 297 | pr_debug("set_dma_next_desc_addr() : END\n"); | ||
| 298 | } | ||
| 299 | EXPORT_SYMBOL(set_dma_next_desc_addr); | ||
| 300 | |||
| 301 | void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr) | ||
| 302 | { | ||
| 303 | pr_debug("set_dma_curr_desc_addr() : BEGIN \n"); | ||
| 304 | |||
| 305 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 306 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 307 | |||
| 308 | dma_ch[channel].regs->curr_desc_ptr = addr; | ||
| 309 | SSYNC(); | ||
| 310 | pr_debug("set_dma_curr_desc_addr() : END\n"); | ||
| 311 | } | ||
| 312 | EXPORT_SYMBOL(set_dma_curr_desc_addr); | ||
| 313 | |||
| 314 | void set_dma_x_count(unsigned int channel, unsigned short x_count) | ||
| 315 | { | ||
| 316 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 317 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 318 | |||
| 319 | dma_ch[channel].regs->x_count = x_count; | ||
| 320 | SSYNC(); | ||
| 321 | } | ||
| 322 | EXPORT_SYMBOL(set_dma_x_count); | ||
| 323 | |||
| 324 | void set_dma_y_count(unsigned int channel, unsigned short y_count) | ||
| 325 | { | ||
| 326 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 327 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 328 | |||
| 329 | dma_ch[channel].regs->y_count = y_count; | ||
| 330 | SSYNC(); | ||
| 331 | } | ||
| 332 | EXPORT_SYMBOL(set_dma_y_count); | ||
| 333 | |||
| 334 | void set_dma_x_modify(unsigned int channel, short x_modify) | ||
| 335 | { | ||
| 336 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 337 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 338 | |||
| 339 | dma_ch[channel].regs->x_modify = x_modify; | ||
| 340 | SSYNC(); | ||
| 341 | } | ||
| 342 | EXPORT_SYMBOL(set_dma_x_modify); | ||
| 343 | |||
| 344 | void set_dma_y_modify(unsigned int channel, short y_modify) | ||
| 345 | { | ||
| 346 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 347 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 348 | |||
| 349 | dma_ch[channel].regs->y_modify = y_modify; | ||
| 350 | SSYNC(); | ||
| 351 | } | ||
| 352 | EXPORT_SYMBOL(set_dma_y_modify); | ||
| 353 | |||
| 354 | void set_dma_config(unsigned int channel, unsigned short config) | ||
| 355 | { | ||
| 356 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 357 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 358 | |||
| 359 | dma_ch[channel].regs->cfg = config; | ||
| 360 | SSYNC(); | ||
| 361 | } | ||
| 362 | EXPORT_SYMBOL(set_dma_config); | ||
| 363 | |||
| 364 | unsigned short | ||
| 365 | set_bfin_dma_config(char direction, char flow_mode, | ||
| 366 | char intr_mode, char dma_mode, char width, char syncmode) | ||
| 367 | { | ||
| 368 | unsigned short config; | ||
| 369 | |||
| 370 | config = | ||
| 371 | ((direction << 1) | (width << 2) | (dma_mode << 4) | | ||
| 372 | (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5)); | ||
| 373 | return config; | ||
| 374 | } | ||
| 375 | EXPORT_SYMBOL(set_bfin_dma_config); | ||
| 376 | |||
| 377 | void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg) | ||
| 378 | { | ||
| 379 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 380 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 381 | |||
| 382 | dma_ch[channel].regs->cfg |= ((nr_sg & 0x0F) << 8); | ||
| 383 | |||
| 384 | dma_ch[channel].regs->next_desc_ptr = (unsigned int)sg; | ||
| 385 | |||
| 386 | SSYNC(); | ||
| 387 | } | ||
| 388 | EXPORT_SYMBOL(set_dma_sg); | ||
| 389 | |||
| 390 | void set_dma_curr_addr(unsigned int channel, unsigned long addr) | ||
| 391 | { | ||
| 392 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 393 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 394 | |||
| 395 | dma_ch[channel].regs->curr_addr_ptr = addr; | ||
| 396 | SSYNC(); | ||
| 397 | } | ||
| 398 | EXPORT_SYMBOL(set_dma_curr_addr); | ||
| 399 | |||
| 400 | /*------------------------------------------------------------------------------ | ||
| 401 | * Get the DMA status of a specific DMA channel from the system. | ||
| 402 | *-----------------------------------------------------------------------------*/ | ||
| 403 | unsigned short get_dma_curr_irqstat(unsigned int channel) | ||
| 404 | { | ||
| 405 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 406 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 407 | |||
| 408 | return dma_ch[channel].regs->irq_status; | ||
| 409 | } | ||
| 410 | EXPORT_SYMBOL(get_dma_curr_irqstat); | ||
| 411 | |||
| 412 | /*------------------------------------------------------------------------------ | ||
| 413 | * Clear the DMA_DONE bit in DMA status. Stop the DMA completion interrupt. | ||
| 414 | *-----------------------------------------------------------------------------*/ | ||
| 415 | void clear_dma_irqstat(unsigned int channel) | ||
| 416 | { | ||
| 417 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 418 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 419 | dma_ch[channel].regs->irq_status |= 3; | ||
| 420 | } | ||
| 421 | EXPORT_SYMBOL(clear_dma_irqstat); | ||
| 422 | |||
| 423 | /*------------------------------------------------------------------------------ | ||
| 424 | * Get current DMA xcount of a specific DMA channel from the system. | ||
| 425 | *-----------------------------------------------------------------------------*/ | ||
| 426 | unsigned short get_dma_curr_xcount(unsigned int channel) | ||
| 427 | { | ||
| 428 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 429 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 430 | |||
| 431 | return dma_ch[channel].regs->curr_x_count; | ||
| 432 | } | ||
| 433 | EXPORT_SYMBOL(get_dma_curr_xcount); | ||
| 434 | |||
| 435 | /*------------------------------------------------------------------------------ | ||
| 436 | * Get current DMA ycount of a specific DMA channel from the system. | ||
| 437 | *-----------------------------------------------------------------------------*/ | ||
| 438 | unsigned short get_dma_curr_ycount(unsigned int channel) | ||
| 439 | { | ||
| 440 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 441 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 442 | |||
| 443 | return dma_ch[channel].regs->curr_y_count; | ||
| 444 | } | ||
| 445 | EXPORT_SYMBOL(get_dma_curr_ycount); | ||
| 446 | |||
| 447 | unsigned long get_dma_next_desc_ptr(unsigned int channel) | ||
| 448 | { | ||
| 449 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 450 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 451 | |||
| 452 | return dma_ch[channel].regs->next_desc_ptr; | ||
| 453 | } | ||
| 454 | EXPORT_SYMBOL(get_dma_next_desc_ptr); | ||
| 455 | |||
| 456 | unsigned long get_dma_curr_desc_ptr(unsigned int channel) | ||
| 457 | { | ||
| 458 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 459 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 460 | |||
| 461 | return dma_ch[channel].regs->curr_desc_ptr; | ||
| 462 | } | ||
| 463 | EXPORT_SYMBOL(get_dma_curr_desc_ptr); | ||
| 464 | |||
| 465 | unsigned long get_dma_curr_addr(unsigned int channel) | ||
| 466 | { | ||
| 467 | BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE | ||
| 468 | && channel < MAX_BLACKFIN_DMA_CHANNEL)); | ||
| 469 | |||
| 470 | return dma_ch[channel].regs->curr_addr_ptr; | ||
| 471 | } | ||
| 472 | EXPORT_SYMBOL(get_dma_curr_addr); | ||
| 473 | |||
| 474 | #ifdef CONFIG_PM | 198 | #ifdef CONFIG_PM |
| 199 | # ifndef MAX_DMA_SUSPEND_CHANNELS | ||
| 200 | # define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS | ||
| 201 | # endif | ||
| 475 | int blackfin_dma_suspend(void) | 202 | int blackfin_dma_suspend(void) |
| 476 | { | 203 | { |
| 477 | int i; | 204 | int i; |
| 478 | 205 | ||
| 479 | #ifdef CONFIG_BF561 /* IMDMA channels doesn't have a PERIPHERAL_MAP */ | 206 | for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) { |
| 480 | for (i = 0; i <= CH_MEM_STREAM3_SRC; i++) { | ||
| 481 | #else | ||
| 482 | for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) { | ||
| 483 | #endif | ||
| 484 | if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) { | 207 | if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) { |
| 485 | printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); | 208 | printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); |
| 486 | return -EBUSY; | 209 | return -EBUSY; |
| @@ -495,388 +218,201 @@ int blackfin_dma_suspend(void) | |||
| 495 | void blackfin_dma_resume(void) | 218 | void blackfin_dma_resume(void) |
| 496 | { | 219 | { |
| 497 | int i; | 220 | int i; |
| 498 | 221 | for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) | |
| 499 | #ifdef CONFIG_BF561 /* IMDMA channels doesn't have a PERIPHERAL_MAP */ | ||
| 500 | for (i = 0; i <= CH_MEM_STREAM3_SRC; i++) | ||
| 501 | #else | ||
| 502 | for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) | ||
| 503 | #endif | ||
| 504 | dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map; | 222 | dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map; |
| 505 | } | 223 | } |
| 506 | #endif | 224 | #endif |
| 507 | 225 | ||
| 508 | static void *__dma_memcpy(void *dest, const void *src, size_t size) | 226 | /** |
| 227 | * blackfin_dma_early_init - minimal DMA init | ||
| 228 | * | ||
| 229 | * Setup a few DMA registers so we can safely do DMA transfers early on in | ||
| 230 | * the kernel booting process. Really this just means using dma_memcpy(). | ||
| 231 | */ | ||
| 232 | void __init blackfin_dma_early_init(void) | ||
| 509 | { | 233 | { |
| 510 | int direction; /* 1 - address decrease, 0 - address increase */ | ||
| 511 | int flag_align; /* 1 - address aligned, 0 - address unaligned */ | ||
| 512 | int flag_2D; /* 1 - 2D DMA needed, 0 - 1D DMA needed */ | ||
| 513 | unsigned long flags; | ||
| 514 | |||
| 515 | if (size <= 0) | ||
| 516 | return NULL; | ||
| 517 | |||
| 518 | local_irq_save(flags); | ||
| 519 | |||
| 520 | if ((unsigned long)src < memory_end) | ||
| 521 | blackfin_dcache_flush_range((unsigned int)src, | ||
| 522 | (unsigned int)(src + size)); | ||
| 523 | |||
| 524 | if ((unsigned long)dest < memory_end) | ||
| 525 | blackfin_dcache_invalidate_range((unsigned int)dest, | ||
| 526 | (unsigned int)(dest + size)); | ||
| 527 | |||
| 528 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 529 | |||
| 530 | if ((unsigned long)src < (unsigned long)dest) | ||
| 531 | direction = 1; | ||
| 532 | else | ||
| 533 | direction = 0; | ||
| 534 | |||
| 535 | if ((((unsigned long)dest % 2) == 0) && (((unsigned long)src % 2) == 0) | ||
| 536 | && ((size % 2) == 0)) | ||
| 537 | flag_align = 1; | ||
| 538 | else | ||
| 539 | flag_align = 0; | ||
| 540 | |||
| 541 | if (size > 0x10000) /* size > 64K */ | ||
| 542 | flag_2D = 1; | ||
| 543 | else | ||
| 544 | flag_2D = 0; | ||
| 545 | |||
| 546 | /* Setup destination and source start address */ | ||
| 547 | if (direction) { | ||
| 548 | if (flag_align) { | ||
| 549 | bfin_write_MDMA_D0_START_ADDR(dest + size - 2); | ||
| 550 | bfin_write_MDMA_S0_START_ADDR(src + size - 2); | ||
| 551 | } else { | ||
| 552 | bfin_write_MDMA_D0_START_ADDR(dest + size - 1); | ||
| 553 | bfin_write_MDMA_S0_START_ADDR(src + size - 1); | ||
| 554 | } | ||
| 555 | } else { | ||
| 556 | bfin_write_MDMA_D0_START_ADDR(dest); | ||
| 557 | bfin_write_MDMA_S0_START_ADDR(src); | ||
| 558 | } | ||
| 559 | |||
| 560 | /* Setup destination and source xcount */ | ||
| 561 | if (flag_2D) { | ||
| 562 | if (flag_align) { | ||
| 563 | bfin_write_MDMA_D0_X_COUNT(1024 / 2); | ||
| 564 | bfin_write_MDMA_S0_X_COUNT(1024 / 2); | ||
| 565 | } else { | ||
| 566 | bfin_write_MDMA_D0_X_COUNT(1024); | ||
| 567 | bfin_write_MDMA_S0_X_COUNT(1024); | ||
| 568 | } | ||
| 569 | bfin_write_MDMA_D0_Y_COUNT(size >> 10); | ||
| 570 | bfin_write_MDMA_S0_Y_COUNT(size >> 10); | ||
| 571 | } else { | ||
| 572 | if (flag_align) { | ||
| 573 | bfin_write_MDMA_D0_X_COUNT(size / 2); | ||
| 574 | bfin_write_MDMA_S0_X_COUNT(size / 2); | ||
| 575 | } else { | ||
| 576 | bfin_write_MDMA_D0_X_COUNT(size); | ||
| 577 | bfin_write_MDMA_S0_X_COUNT(size); | ||
| 578 | } | ||
| 579 | } | ||
| 580 | |||
| 581 | /* Setup destination and source xmodify and ymodify */ | ||
| 582 | if (direction) { | ||
| 583 | if (flag_align) { | ||
| 584 | bfin_write_MDMA_D0_X_MODIFY(-2); | ||
| 585 | bfin_write_MDMA_S0_X_MODIFY(-2); | ||
| 586 | if (flag_2D) { | ||
| 587 | bfin_write_MDMA_D0_Y_MODIFY(-2); | ||
| 588 | bfin_write_MDMA_S0_Y_MODIFY(-2); | ||
| 589 | } | ||
| 590 | } else { | ||
| 591 | bfin_write_MDMA_D0_X_MODIFY(-1); | ||
| 592 | bfin_write_MDMA_S0_X_MODIFY(-1); | ||
| 593 | if (flag_2D) { | ||
| 594 | bfin_write_MDMA_D0_Y_MODIFY(-1); | ||
| 595 | bfin_write_MDMA_S0_Y_MODIFY(-1); | ||
| 596 | } | ||
| 597 | } | ||
| 598 | } else { | ||
| 599 | if (flag_align) { | ||
| 600 | bfin_write_MDMA_D0_X_MODIFY(2); | ||
| 601 | bfin_write_MDMA_S0_X_MODIFY(2); | ||
| 602 | if (flag_2D) { | ||
| 603 | bfin_write_MDMA_D0_Y_MODIFY(2); | ||
| 604 | bfin_write_MDMA_S0_Y_MODIFY(2); | ||
| 605 | } | ||
| 606 | } else { | ||
| 607 | bfin_write_MDMA_D0_X_MODIFY(1); | ||
| 608 | bfin_write_MDMA_S0_X_MODIFY(1); | ||
| 609 | if (flag_2D) { | ||
| 610 | bfin_write_MDMA_D0_Y_MODIFY(1); | ||
| 611 | bfin_write_MDMA_S0_Y_MODIFY(1); | ||
| 612 | } | ||
| 613 | } | ||
| 614 | } | ||
| 615 | |||
| 616 | /* Enable source DMA */ | ||
| 617 | if (flag_2D) { | ||
| 618 | if (flag_align) { | ||
| 619 | bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D | WDSIZE_16); | ||
| 620 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D | WDSIZE_16); | ||
| 621 | } else { | ||
| 622 | bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D); | ||
| 623 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D); | ||
| 624 | } | ||
| 625 | } else { | ||
| 626 | if (flag_align) { | ||
| 627 | bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16); | ||
| 628 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16); | ||
| 629 | } else { | ||
| 630 | bfin_write_MDMA_S0_CONFIG(DMAEN); | ||
| 631 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN); | ||
| 632 | } | ||
| 633 | } | ||
| 634 | |||
| 635 | SSYNC(); | ||
| 636 | |||
| 637 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) | ||
| 638 | ; | ||
| 639 | |||
| 640 | bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | | ||
| 641 | (DMA_DONE | DMA_ERR)); | ||
| 642 | |||
| 643 | bfin_write_MDMA_S0_CONFIG(0); | 234 | bfin_write_MDMA_S0_CONFIG(0); |
| 644 | bfin_write_MDMA_D0_CONFIG(0); | ||
| 645 | |||
| 646 | local_irq_restore(flags); | ||
| 647 | |||
| 648 | return dest; | ||
| 649 | } | 235 | } |
| 650 | 236 | ||
| 651 | void *dma_memcpy(void *dest, const void *src, size_t size) | 237 | /** |
| 652 | { | 238 | * __dma_memcpy - program the MDMA registers |
| 653 | size_t bulk; | 239 | * |
| 654 | size_t rest; | 240 | * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs |
| 655 | void * addr; | 241 | * while programming registers so that everything is fully configured. Wait |
| 656 | 242 | * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE | |
| 657 | bulk = (size >> 16) << 16; | 243 | * check will make sure we don't clobber any existing transfer. |
| 658 | rest = size - bulk; | 244 | */ |
| 659 | if (bulk) | 245 | static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf) |
| 660 | __dma_memcpy(dest, src, bulk); | ||
| 661 | addr = __dma_memcpy(dest+bulk, src+bulk, rest); | ||
| 662 | return addr; | ||
| 663 | } | ||
| 664 | EXPORT_SYMBOL(dma_memcpy); | ||
| 665 | |||
| 666 | void *safe_dma_memcpy(void *dest, const void *src, size_t size) | ||
| 667 | { | ||
| 668 | void *addr; | ||
| 669 | addr = dma_memcpy(dest, src, size); | ||
| 670 | return addr; | ||
| 671 | } | ||
| 672 | EXPORT_SYMBOL(safe_dma_memcpy); | ||
| 673 | |||
| 674 | void dma_outsb(unsigned long addr, const void *buf, unsigned short len) | ||
| 675 | { | 246 | { |
| 247 | static DEFINE_SPINLOCK(mdma_lock); | ||
| 676 | unsigned long flags; | 248 | unsigned long flags; |
| 677 | 249 | ||
| 678 | local_irq_save(flags); | 250 | spin_lock_irqsave(&mdma_lock, flags); |
| 679 | 251 | ||
| 680 | blackfin_dcache_flush_range((unsigned int)buf, | 252 | if (bfin_read_MDMA_S0_CONFIG()) |
| 681 | (unsigned int)(buf) + len); | 253 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) |
| 254 | continue; | ||
| 255 | |||
| 256 | if (conf & DMA2D) { | ||
| 257 | /* For larger bit sizes, we've already divided down cnt so it | ||
| 258 | * is no longer a multiple of 64k. So we have to break down | ||
| 259 | * the limit here so it is a multiple of the incoming size. | ||
| 260 | * There is no limitation here in terms of total size other | ||
| 261 | * than the hardware though as the bits lost in the shift are | ||
| 262 | * made up by MODIFY (== we can hit the whole address space). | ||
| 263 | * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4 | ||
| 264 | */ | ||
| 265 | u32 shift = abs(dmod) >> 1; | ||
| 266 | size_t ycnt = cnt >> (16 - shift); | ||
| 267 | cnt = 1 << (16 - shift); | ||
| 268 | bfin_write_MDMA_D0_Y_COUNT(ycnt); | ||
| 269 | bfin_write_MDMA_S0_Y_COUNT(ycnt); | ||
| 270 | bfin_write_MDMA_D0_Y_MODIFY(dmod); | ||
| 271 | bfin_write_MDMA_S0_Y_MODIFY(smod); | ||
| 272 | } | ||
| 682 | 273 | ||
| 683 | bfin_write_MDMA_D0_START_ADDR(addr); | 274 | bfin_write_MDMA_D0_START_ADDR(daddr); |
| 684 | bfin_write_MDMA_D0_X_COUNT(len); | 275 | bfin_write_MDMA_D0_X_COUNT(cnt); |
| 685 | bfin_write_MDMA_D0_X_MODIFY(0); | 276 | bfin_write_MDMA_D0_X_MODIFY(dmod); |
| 686 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | 277 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
| 687 | 278 | ||
| 688 | bfin_write_MDMA_S0_START_ADDR(buf); | 279 | bfin_write_MDMA_S0_START_ADDR(saddr); |
| 689 | bfin_write_MDMA_S0_X_COUNT(len); | 280 | bfin_write_MDMA_S0_X_COUNT(cnt); |
| 690 | bfin_write_MDMA_S0_X_MODIFY(1); | 281 | bfin_write_MDMA_S0_X_MODIFY(smod); |
| 691 | bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); | 282 | bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
| 692 | 283 | ||
| 693 | bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8); | 284 | bfin_write_MDMA_S0_CONFIG(DMAEN | conf); |
| 694 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8); | 285 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf); |
| 286 | |||
| 287 | spin_unlock_irqrestore(&mdma_lock, flags); | ||
| 695 | 288 | ||
| 696 | SSYNC(); | 289 | SSYNC(); |
| 697 | 290 | ||
| 698 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)); | 291 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) |
| 292 | if (bfin_read_MDMA_S0_CONFIG()) | ||
| 293 | continue; | ||
| 294 | else | ||
| 295 | return; | ||
| 699 | 296 | ||
| 700 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | 297 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
| 701 | 298 | ||
| 702 | bfin_write_MDMA_S0_CONFIG(0); | 299 | bfin_write_MDMA_S0_CONFIG(0); |
| 703 | bfin_write_MDMA_D0_CONFIG(0); | 300 | bfin_write_MDMA_D0_CONFIG(0); |
| 704 | local_irq_restore(flags); | ||
| 705 | |||
| 706 | } | 301 | } |
| 707 | EXPORT_SYMBOL(dma_outsb); | ||
| 708 | |||
| 709 | 302 | ||
| 710 | void dma_insb(unsigned long addr, void *buf, unsigned short len) | 303 | /** |
| 304 | * _dma_memcpy - translate C memcpy settings into MDMA settings | ||
| 305 | * | ||
| 306 | * Handle all the high level steps before we touch the MDMA registers. So | ||
| 307 | * handle direction, tweaking of sizes, and formatting of addresses. | ||
| 308 | */ | ||
| 309 | static void *_dma_memcpy(void *pdst, const void *psrc, size_t size) | ||
| 711 | { | 310 | { |
| 712 | unsigned long flags; | 311 | u32 conf, shift; |
| 713 | 312 | s16 mod; | |
| 714 | blackfin_dcache_invalidate_range((unsigned int)buf, | 313 | unsigned long dst = (unsigned long)pdst; |
| 715 | (unsigned int)(buf) + len); | 314 | unsigned long src = (unsigned long)psrc; |
| 716 | |||
| 717 | local_irq_save(flags); | ||
| 718 | bfin_write_MDMA_D0_START_ADDR(buf); | ||
| 719 | bfin_write_MDMA_D0_X_COUNT(len); | ||
| 720 | bfin_write_MDMA_D0_X_MODIFY(1); | ||
| 721 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 722 | |||
| 723 | bfin_write_MDMA_S0_START_ADDR(addr); | ||
| 724 | bfin_write_MDMA_S0_X_COUNT(len); | ||
| 725 | bfin_write_MDMA_S0_X_MODIFY(0); | ||
| 726 | bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 727 | 315 | ||
| 728 | bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8); | 316 | if (size == 0) |
| 729 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8); | 317 | return NULL; |
| 730 | 318 | ||
| 731 | SSYNC(); | 319 | if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) { |
| 320 | conf = WDSIZE_32; | ||
| 321 | shift = 2; | ||
| 322 | } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) { | ||
| 323 | conf = WDSIZE_16; | ||
| 324 | shift = 1; | ||
| 325 | } else { | ||
| 326 | conf = WDSIZE_8; | ||
| 327 | shift = 0; | ||
| 328 | } | ||
| 732 | 329 | ||
| 733 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)); | 330 | /* If the two memory regions have a chance of overlapping, make |
| 331 | * sure the memcpy still works as expected. Do this by having the | ||
| 332 | * copy run backwards instead. | ||
| 333 | */ | ||
| 334 | mod = 1 << shift; | ||
| 335 | if (src < dst) { | ||
| 336 | mod *= -1; | ||
| 337 | dst += size + mod; | ||
| 338 | src += size + mod; | ||
| 339 | } | ||
| 340 | size >>= shift; | ||
| 734 | 341 | ||
| 735 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | 342 | if (size > 0x10000) |
| 343 | conf |= DMA2D; | ||
| 736 | 344 | ||
| 737 | bfin_write_MDMA_S0_CONFIG(0); | 345 | __dma_memcpy(dst, mod, src, mod, size, conf); |
| 738 | bfin_write_MDMA_D0_CONFIG(0); | ||
| 739 | local_irq_restore(flags); | ||
| 740 | 346 | ||
| 347 | return pdst; | ||
| 741 | } | 348 | } |
| 742 | EXPORT_SYMBOL(dma_insb); | ||
| 743 | 349 | ||
| 744 | void dma_outsw(unsigned long addr, const void *buf, unsigned short len) | 350 | /** |
| 351 | * dma_memcpy - DMA memcpy under mutex lock | ||
| 352 | * | ||
| 353 | * Do not check arguments before starting the DMA memcpy. Break the transfer | ||
| 354 | * up into two pieces. The first transfer is in multiples of 64k and the | ||
| 355 | * second transfer is the piece smaller than 64k. | ||
| 356 | */ | ||
| 357 | void *dma_memcpy(void *pdst, const void *psrc, size_t size) | ||
| 745 | { | 358 | { |
| 746 | unsigned long flags; | 359 | unsigned long dst = (unsigned long)pdst; |
| 747 | 360 | unsigned long src = (unsigned long)psrc; | |
| 748 | local_irq_save(flags); | 361 | size_t bulk, rest; |
| 749 | 362 | ||
| 750 | blackfin_dcache_flush_range((unsigned int)buf, | 363 | if (bfin_addr_dcachable(src)) |
| 751 | (unsigned int)(buf) + len * sizeof(short)); | 364 | blackfin_dcache_flush_range(src, src + size); |
| 752 | 365 | ||
| 753 | bfin_write_MDMA_D0_START_ADDR(addr); | 366 | if (bfin_addr_dcachable(dst)) |
| 754 | bfin_write_MDMA_D0_X_COUNT(len); | 367 | blackfin_dcache_invalidate_range(dst, dst + size); |
| 755 | bfin_write_MDMA_D0_X_MODIFY(0); | ||
| 756 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 757 | |||
| 758 | bfin_write_MDMA_S0_START_ADDR(buf); | ||
| 759 | bfin_write_MDMA_S0_X_COUNT(len); | ||
| 760 | bfin_write_MDMA_S0_X_MODIFY(2); | ||
| 761 | bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 762 | |||
| 763 | bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16); | ||
| 764 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16); | ||
| 765 | |||
| 766 | SSYNC(); | ||
| 767 | |||
| 768 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)); | ||
| 769 | |||
| 770 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 771 | |||
| 772 | bfin_write_MDMA_S0_CONFIG(0); | ||
| 773 | bfin_write_MDMA_D0_CONFIG(0); | ||
| 774 | local_irq_restore(flags); | ||
| 775 | 368 | ||
| 369 | bulk = size & ~0xffff; | ||
| 370 | rest = size - bulk; | ||
| 371 | if (bulk) | ||
| 372 | _dma_memcpy(pdst, psrc, bulk); | ||
| 373 | _dma_memcpy(pdst + bulk, psrc + bulk, rest); | ||
| 374 | return pdst; | ||
| 776 | } | 375 | } |
| 777 | EXPORT_SYMBOL(dma_outsw); | 376 | EXPORT_SYMBOL(dma_memcpy); |
| 778 | 377 | ||
| 779 | void dma_insw(unsigned long addr, void *buf, unsigned short len) | 378 | /** |
| 379 | * safe_dma_memcpy - DMA memcpy w/argument checking | ||
| 380 | * | ||
| 381 | * Verify arguments are safe before heading to dma_memcpy(). | ||
| 382 | */ | ||
| 383 | void *safe_dma_memcpy(void *dst, const void *src, size_t size) | ||
| 780 | { | 384 | { |
| 781 | unsigned long flags; | 385 | if (!access_ok(VERIFY_WRITE, dst, size)) |
| 782 | 386 | return NULL; | |
| 783 | blackfin_dcache_invalidate_range((unsigned int)buf, | 387 | if (!access_ok(VERIFY_READ, src, size)) |
| 784 | (unsigned int)(buf) + len * sizeof(short)); | 388 | return NULL; |
| 785 | 389 | return dma_memcpy(dst, src, size); | |
| 786 | local_irq_save(flags); | ||
| 787 | |||
| 788 | bfin_write_MDMA_D0_START_ADDR(buf); | ||
| 789 | bfin_write_MDMA_D0_X_COUNT(len); | ||
| 790 | bfin_write_MDMA_D0_X_MODIFY(2); | ||
| 791 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 792 | |||
| 793 | bfin_write_MDMA_S0_START_ADDR(addr); | ||
| 794 | bfin_write_MDMA_S0_X_COUNT(len); | ||
| 795 | bfin_write_MDMA_S0_X_MODIFY(0); | ||
| 796 | bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 797 | |||
| 798 | bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16); | ||
| 799 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16); | ||
| 800 | |||
| 801 | SSYNC(); | ||
| 802 | |||
| 803 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)); | ||
| 804 | |||
| 805 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 806 | |||
| 807 | bfin_write_MDMA_S0_CONFIG(0); | ||
| 808 | bfin_write_MDMA_D0_CONFIG(0); | ||
| 809 | local_irq_restore(flags); | ||
| 810 | |||
| 811 | } | 390 | } |
| 812 | EXPORT_SYMBOL(dma_insw); | 391 | EXPORT_SYMBOL(safe_dma_memcpy); |
| 813 | 392 | ||
| 814 | void dma_outsl(unsigned long addr, const void *buf, unsigned short len) | 393 | static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len, |
| 394 | u16 size, u16 dma_size) | ||
| 815 | { | 395 | { |
| 816 | unsigned long flags; | 396 | blackfin_dcache_flush_range(buf, buf + len * size); |
| 817 | 397 | __dma_memcpy(addr, 0, buf, size, len, dma_size); | |
| 818 | local_irq_save(flags); | ||
| 819 | |||
| 820 | blackfin_dcache_flush_range((unsigned int)buf, | ||
| 821 | (unsigned int)(buf) + len * sizeof(long)); | ||
| 822 | |||
| 823 | bfin_write_MDMA_D0_START_ADDR(addr); | ||
| 824 | bfin_write_MDMA_D0_X_COUNT(len); | ||
| 825 | bfin_write_MDMA_D0_X_MODIFY(0); | ||
| 826 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 827 | |||
| 828 | bfin_write_MDMA_S0_START_ADDR(buf); | ||
| 829 | bfin_write_MDMA_S0_X_COUNT(len); | ||
| 830 | bfin_write_MDMA_S0_X_MODIFY(4); | ||
| 831 | bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 832 | |||
| 833 | bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32); | ||
| 834 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32); | ||
| 835 | |||
| 836 | SSYNC(); | ||
| 837 | |||
| 838 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)); | ||
| 839 | |||
| 840 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 841 | |||
| 842 | bfin_write_MDMA_S0_CONFIG(0); | ||
| 843 | bfin_write_MDMA_D0_CONFIG(0); | ||
| 844 | local_irq_restore(flags); | ||
| 845 | |||
| 846 | } | 398 | } |
| 847 | EXPORT_SYMBOL(dma_outsl); | ||
| 848 | 399 | ||
| 849 | void dma_insl(unsigned long addr, void *buf, unsigned short len) | 400 | static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len, |
| 401 | u16 size, u16 dma_size) | ||
| 850 | { | 402 | { |
| 851 | unsigned long flags; | 403 | blackfin_dcache_invalidate_range(buf, buf + len * size); |
| 852 | 404 | __dma_memcpy(buf, size, addr, 0, len, dma_size); | |
| 853 | blackfin_dcache_invalidate_range((unsigned int)buf, | ||
| 854 | (unsigned int)(buf) + len * sizeof(long)); | ||
| 855 | |||
| 856 | local_irq_save(flags); | ||
| 857 | |||
| 858 | bfin_write_MDMA_D0_START_ADDR(buf); | ||
| 859 | bfin_write_MDMA_D0_X_COUNT(len); | ||
| 860 | bfin_write_MDMA_D0_X_MODIFY(4); | ||
| 861 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 862 | |||
| 863 | bfin_write_MDMA_S0_START_ADDR(addr); | ||
| 864 | bfin_write_MDMA_S0_X_COUNT(len); | ||
| 865 | bfin_write_MDMA_S0_X_MODIFY(0); | ||
| 866 | bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 867 | |||
| 868 | bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32); | ||
| 869 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32); | ||
| 870 | |||
| 871 | SSYNC(); | ||
| 872 | |||
| 873 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)); | ||
| 874 | |||
| 875 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | ||
| 876 | |||
| 877 | bfin_write_MDMA_S0_CONFIG(0); | ||
| 878 | bfin_write_MDMA_D0_CONFIG(0); | ||
| 879 | local_irq_restore(flags); | ||
| 880 | |||
| 881 | } | 405 | } |
| 882 | EXPORT_SYMBOL(dma_insl); | 406 | |
| 407 | #define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \ | ||
| 408 | void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \ | ||
| 409 | { \ | ||
| 410 | _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \ | ||
| 411 | } \ | ||
| 412 | EXPORT_SYMBOL(dma_##io##s##bwl) | ||
| 413 | MAKE_DMA_IO(out, b, 1, 8, const); | ||
| 414 | MAKE_DMA_IO(in, b, 1, 8, ); | ||
| 415 | MAKE_DMA_IO(out, w, 2, 16, const); | ||
| 416 | MAKE_DMA_IO(in, w, 2, 16, ); | ||
| 417 | MAKE_DMA_IO(out, l, 4, 32, const); | ||
| 418 | MAKE_DMA_IO(in, l, 4, 32, ); | ||
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index 5c0800adb4dd..4c14331978f6 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c | |||
| @@ -119,28 +119,28 @@ enum { | |||
| 119 | #define AWA_DUMMY_READ(...) do { } while (0) | 119 | #define AWA_DUMMY_READ(...) do { } while (0) |
| 120 | #endif | 120 | #endif |
| 121 | 121 | ||
| 122 | #ifdef BF533_FAMILY | 122 | #if defined(BF533_FAMILY) || defined(BF538_FAMILY) |
| 123 | static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = { | 123 | static struct gpio_port_t *gpio_bankb[] = { |
| 124 | (struct gpio_port_t *) FIO_FLAG_D, | 124 | (struct gpio_port_t *) FIO_FLAG_D, |
| 125 | }; | 125 | }; |
| 126 | #endif | 126 | #endif |
| 127 | 127 | ||
| 128 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) | 128 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY) |
| 129 | static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = { | 129 | static struct gpio_port_t *gpio_bankb[] = { |
| 130 | (struct gpio_port_t *) PORTFIO, | 130 | (struct gpio_port_t *) PORTFIO, |
| 131 | (struct gpio_port_t *) PORTGIO, | 131 | (struct gpio_port_t *) PORTGIO, |
| 132 | (struct gpio_port_t *) PORTHIO, | 132 | (struct gpio_port_t *) PORTHIO, |
| 133 | }; | 133 | }; |
| 134 | 134 | ||
| 135 | static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = { | 135 | static unsigned short *port_fer[] = { |
| 136 | (unsigned short *) PORTF_FER, | 136 | (unsigned short *) PORTF_FER, |
| 137 | (unsigned short *) PORTG_FER, | 137 | (unsigned short *) PORTG_FER, |
| 138 | (unsigned short *) PORTH_FER, | 138 | (unsigned short *) PORTH_FER, |
| 139 | }; | 139 | }; |
| 140 | #endif | 140 | #endif |
| 141 | 141 | ||
| 142 | #ifdef BF527_FAMILY | 142 | #if defined(BF527_FAMILY) || defined(BF518_FAMILY) |
| 143 | static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = { | 143 | static unsigned short *port_mux[] = { |
| 144 | (unsigned short *) PORTF_MUX, | 144 | (unsigned short *) PORTF_MUX, |
| 145 | (unsigned short *) PORTG_MUX, | 145 | (unsigned short *) PORTG_MUX, |
| 146 | (unsigned short *) PORTH_MUX, | 146 | (unsigned short *) PORTH_MUX, |
| @@ -155,7 +155,7 @@ u8 pmux_offset[][16] = | |||
| 155 | #endif | 155 | #endif |
| 156 | 156 | ||
| 157 | #ifdef BF561_FAMILY | 157 | #ifdef BF561_FAMILY |
| 158 | static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = { | 158 | static struct gpio_port_t *gpio_bankb[] = { |
| 159 | (struct gpio_port_t *) FIO0_FLAG_D, | 159 | (struct gpio_port_t *) FIO0_FLAG_D, |
| 160 | (struct gpio_port_t *) FIO1_FLAG_D, | 160 | (struct gpio_port_t *) FIO1_FLAG_D, |
| 161 | (struct gpio_port_t *) FIO2_FLAG_D, | 161 | (struct gpio_port_t *) FIO2_FLAG_D, |
| @@ -163,7 +163,7 @@ static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = { | |||
| 163 | #endif | 163 | #endif |
| 164 | 164 | ||
| 165 | #ifdef BF548_FAMILY | 165 | #ifdef BF548_FAMILY |
| 166 | static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = { | 166 | static struct gpio_port_t *gpio_array[] = { |
| 167 | (struct gpio_port_t *)PORTA_FER, | 167 | (struct gpio_port_t *)PORTA_FER, |
| 168 | (struct gpio_port_t *)PORTB_FER, | 168 | (struct gpio_port_t *)PORTB_FER, |
| 169 | (struct gpio_port_t *)PORTC_FER, | 169 | (struct gpio_port_t *)PORTC_FER, |
| @@ -177,8 +177,9 @@ static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = { | |||
| 177 | }; | 177 | }; |
| 178 | #endif | 178 | #endif |
| 179 | 179 | ||
| 180 | static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; | 180 | static unsigned short reserved_gpio_map[GPIO_BANK_NUM]; |
| 181 | static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)]; | 181 | static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)]; |
| 182 | static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM]; | ||
| 182 | 183 | ||
| 183 | #define RESOURCE_LABEL_SIZE 16 | 184 | #define RESOURCE_LABEL_SIZE 16 |
| 184 | 185 | ||
| @@ -188,48 +189,46 @@ static struct str_ident { | |||
| 188 | 189 | ||
| 189 | #if defined(CONFIG_PM) | 190 | #if defined(CONFIG_PM) |
| 190 | #if defined(CONFIG_BF54x) | 191 | #if defined(CONFIG_BF54x) |
| 191 | static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)]; | 192 | static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM]; |
| 192 | #else | 193 | #else |
| 193 | static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; | 194 | static unsigned short wakeup_map[GPIO_BANK_NUM]; |
| 194 | static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS]; | 195 | static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS]; |
| 195 | static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)]; | 196 | static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM]; |
| 196 | 197 | ||
| 197 | #ifdef BF533_FAMILY | 198 | #ifdef BF533_FAMILY |
| 198 | static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB}; | 199 | static unsigned int sic_iwr_irqs[] = {IRQ_PROG_INTB}; |
| 199 | #endif | 200 | #endif |
| 200 | 201 | ||
| 201 | #ifdef BF537_FAMILY | 202 | #ifdef BF537_FAMILY |
| 202 | static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX}; | 203 | static unsigned int sic_iwr_irqs[] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX}; |
| 204 | #endif | ||
| 205 | |||
| 206 | #ifdef BF538_FAMILY | ||
| 207 | static unsigned int sic_iwr_irqs[] = {IRQ_PORTF_INTB}; | ||
| 203 | #endif | 208 | #endif |
| 204 | 209 | ||
| 205 | #ifdef BF527_FAMILY | 210 | #if defined(BF527_FAMILY) || defined(BF518_FAMILY) |
| 206 | static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB}; | 211 | static unsigned int sic_iwr_irqs[] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB}; |
| 207 | #endif | 212 | #endif |
| 208 | 213 | ||
| 209 | #ifdef BF561_FAMILY | 214 | #ifdef BF561_FAMILY |
| 210 | static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB}; | 215 | static unsigned int sic_iwr_irqs[] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB}; |
| 211 | #endif | 216 | #endif |
| 212 | #endif | 217 | #endif |
| 213 | #endif /* CONFIG_PM */ | 218 | #endif /* CONFIG_PM */ |
| 214 | 219 | ||
| 215 | #if defined(BF548_FAMILY) | ||
| 216 | inline int check_gpio(unsigned gpio) | 220 | inline int check_gpio(unsigned gpio) |
| 217 | { | 221 | { |
| 222 | #if defined(BF548_FAMILY) | ||
| 218 | if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 | 223 | if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 |
| 219 | || gpio == GPIO_PH14 || gpio == GPIO_PH15 | 224 | || gpio == GPIO_PH14 || gpio == GPIO_PH15 |
| 220 | || gpio == GPIO_PJ14 || gpio == GPIO_PJ15 | 225 | || gpio == GPIO_PJ14 || gpio == GPIO_PJ15) |
| 221 | || gpio >= MAX_BLACKFIN_GPIOS) | ||
| 222 | return -EINVAL; | 226 | return -EINVAL; |
| 223 | return 0; | 227 | #endif |
| 224 | } | ||
| 225 | #else | ||
| 226 | inline int check_gpio(unsigned gpio) | ||
| 227 | { | ||
| 228 | if (gpio >= MAX_BLACKFIN_GPIOS) | 228 | if (gpio >= MAX_BLACKFIN_GPIOS) |
| 229 | return -EINVAL; | 229 | return -EINVAL; |
| 230 | return 0; | 230 | return 0; |
| 231 | } | 231 | } |
| 232 | #endif | ||
| 233 | 232 | ||
| 234 | static void gpio_error(unsigned gpio) | 233 | static void gpio_error(unsigned gpio) |
| 235 | { | 234 | { |
| @@ -258,35 +257,30 @@ static int cmp_label(unsigned short ident, const char *label) | |||
| 258 | } | 257 | } |
| 259 | 258 | ||
| 260 | if (label) | 259 | if (label) |
| 261 | return strncmp(str_ident[ident].name, | 260 | return strcmp(str_ident[ident].name, label); |
| 262 | label, strlen(label)); | ||
| 263 | else | 261 | else |
| 264 | return -EINVAL; | 262 | return -EINVAL; |
| 265 | } | 263 | } |
| 266 | 264 | ||
| 267 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) | ||
| 268 | static void port_setup(unsigned gpio, unsigned short usage) | 265 | static void port_setup(unsigned gpio, unsigned short usage) |
| 269 | { | 266 | { |
| 270 | if (!check_gpio(gpio)) { | 267 | if (check_gpio(gpio)) |
| 271 | if (usage == GPIO_USAGE) | 268 | return; |
| 272 | *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); | 269 | |
| 273 | else | 270 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY) |
| 274 | *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); | 271 | if (usage == GPIO_USAGE) |
| 275 | SSYNC(); | 272 | *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); |
| 276 | } | 273 | else |
| 277 | } | 274 | *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); |
| 275 | SSYNC(); | ||
| 278 | #elif defined(BF548_FAMILY) | 276 | #elif defined(BF548_FAMILY) |
| 279 | static void port_setup(unsigned gpio, unsigned short usage) | ||
| 280 | { | ||
| 281 | if (usage == GPIO_USAGE) | 277 | if (usage == GPIO_USAGE) |
| 282 | gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); | 278 | gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); |
| 283 | else | 279 | else |
| 284 | gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); | 280 | gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); |
| 285 | SSYNC(); | 281 | SSYNC(); |
| 286 | } | ||
| 287 | #else | ||
| 288 | # define port_setup(...) do { } while (0) | ||
| 289 | #endif | 282 | #endif |
| 283 | } | ||
| 290 | 284 | ||
| 291 | #ifdef BF537_FAMILY | 285 | #ifdef BF537_FAMILY |
| 292 | static struct { | 286 | static struct { |
| @@ -379,7 +373,7 @@ inline u16 get_portmux(unsigned short portno) | |||
| 379 | 373 | ||
| 380 | return (pmux >> (2 * gpio_sub_n(portno)) & 0x3); | 374 | return (pmux >> (2 * gpio_sub_n(portno)) & 0x3); |
| 381 | } | 375 | } |
| 382 | #elif defined(BF527_FAMILY) | 376 | #elif defined(BF527_FAMILY) || defined(BF518_FAMILY) |
| 383 | inline void portmux_setup(unsigned short portno, unsigned short function) | 377 | inline void portmux_setup(unsigned short portno, unsigned short function) |
| 384 | { | 378 | { |
| 385 | u16 pmux, ident = P_IDENT(portno); | 379 | u16 pmux, ident = P_IDENT(portno); |
| @@ -428,13 +422,13 @@ arch_initcall(bfin_gpio_init); | |||
| 428 | void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ | 422 | void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ |
| 429 | { \ | 423 | { \ |
| 430 | unsigned long flags; \ | 424 | unsigned long flags; \ |
| 431 | local_irq_save(flags); \ | 425 | local_irq_save_hw(flags); \ |
| 432 | if (arg) \ | 426 | if (arg) \ |
| 433 | gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ | 427 | gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ |
| 434 | else \ | 428 | else \ |
| 435 | gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \ | 429 | gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \ |
| 436 | AWA_DUMMY_READ(name); \ | 430 | AWA_DUMMY_READ(name); \ |
| 437 | local_irq_restore(flags); \ | 431 | local_irq_restore_hw(flags); \ |
| 438 | } \ | 432 | } \ |
| 439 | EXPORT_SYMBOL(set_gpio_ ## name); | 433 | EXPORT_SYMBOL(set_gpio_ ## name); |
| 440 | 434 | ||
| @@ -450,13 +444,13 @@ SET_GPIO(both) | |||
| 450 | void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ | 444 | void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ |
| 451 | { \ | 445 | { \ |
| 452 | unsigned long flags; \ | 446 | unsigned long flags; \ |
| 453 | local_irq_save(flags); \ | 447 | local_irq_save_hw(flags); \ |
| 454 | if (arg) \ | 448 | if (arg) \ |
| 455 | gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ | 449 | gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ |
| 456 | else \ | 450 | else \ |
| 457 | gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \ | 451 | gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \ |
| 458 | AWA_DUMMY_READ(name); \ | 452 | AWA_DUMMY_READ(name); \ |
| 459 | local_irq_restore(flags); \ | 453 | local_irq_restore_hw(flags); \ |
| 460 | } \ | 454 | } \ |
| 461 | EXPORT_SYMBOL(set_gpio_ ## name); | 455 | EXPORT_SYMBOL(set_gpio_ ## name); |
| 462 | #else | 456 | #else |
| @@ -479,10 +473,10 @@ SET_GPIO_SC(data) | |||
| 479 | void set_gpio_toggle(unsigned gpio) | 473 | void set_gpio_toggle(unsigned gpio) |
| 480 | { | 474 | { |
| 481 | unsigned long flags; | 475 | unsigned long flags; |
| 482 | local_irq_save(flags); | 476 | local_irq_save_hw(flags); |
| 483 | gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio); | 477 | gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio); |
| 484 | AWA_DUMMY_READ(toggle); | 478 | AWA_DUMMY_READ(toggle); |
| 485 | local_irq_restore(flags); | 479 | local_irq_restore_hw(flags); |
| 486 | } | 480 | } |
| 487 | #else | 481 | #else |
| 488 | void set_gpio_toggle(unsigned gpio) | 482 | void set_gpio_toggle(unsigned gpio) |
| @@ -500,10 +494,10 @@ EXPORT_SYMBOL(set_gpio_toggle); | |||
| 500 | void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ | 494 | void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ |
| 501 | { \ | 495 | { \ |
| 502 | unsigned long flags; \ | 496 | unsigned long flags; \ |
| 503 | local_irq_save(flags); \ | 497 | local_irq_save_hw(flags); \ |
| 504 | gpio_bankb[gpio_bank(gpio)]->name = arg; \ | 498 | gpio_bankb[gpio_bank(gpio)]->name = arg; \ |
| 505 | AWA_DUMMY_READ(name); \ | 499 | AWA_DUMMY_READ(name); \ |
| 506 | local_irq_restore(flags); \ | 500 | local_irq_restore_hw(flags); \ |
| 507 | } \ | 501 | } \ |
| 508 | EXPORT_SYMBOL(set_gpiop_ ## name); | 502 | EXPORT_SYMBOL(set_gpiop_ ## name); |
| 509 | #else | 503 | #else |
| @@ -531,10 +525,10 @@ unsigned short get_gpio_ ## name(unsigned gpio) \ | |||
| 531 | { \ | 525 | { \ |
| 532 | unsigned long flags; \ | 526 | unsigned long flags; \ |
| 533 | unsigned short ret; \ | 527 | unsigned short ret; \ |
| 534 | local_irq_save(flags); \ | 528 | local_irq_save_hw(flags); \ |
| 535 | ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \ | 529 | ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \ |
| 536 | AWA_DUMMY_READ(name); \ | 530 | AWA_DUMMY_READ(name); \ |
| 537 | local_irq_restore(flags); \ | 531 | local_irq_restore_hw(flags); \ |
| 538 | return ret; \ | 532 | return ret; \ |
| 539 | } \ | 533 | } \ |
| 540 | EXPORT_SYMBOL(get_gpio_ ## name); | 534 | EXPORT_SYMBOL(get_gpio_ ## name); |
| @@ -564,10 +558,10 @@ unsigned short get_gpiop_ ## name(unsigned gpio) \ | |||
| 564 | { \ | 558 | { \ |
| 565 | unsigned long flags; \ | 559 | unsigned long flags; \ |
| 566 | unsigned short ret; \ | 560 | unsigned short ret; \ |
| 567 | local_irq_save(flags); \ | 561 | local_irq_save_hw(flags); \ |
| 568 | ret = (gpio_bankb[gpio_bank(gpio)]->name); \ | 562 | ret = (gpio_bankb[gpio_bank(gpio)]->name); \ |
| 569 | AWA_DUMMY_READ(name); \ | 563 | AWA_DUMMY_READ(name); \ |
| 570 | local_irq_restore(flags); \ | 564 | local_irq_restore_hw(flags); \ |
| 571 | return ret; \ | 565 | return ret; \ |
| 572 | } \ | 566 | } \ |
| 573 | EXPORT_SYMBOL(get_gpiop_ ## name); | 567 | EXPORT_SYMBOL(get_gpiop_ ## name); |
| @@ -617,10 +611,10 @@ int gpio_pm_wakeup_request(unsigned gpio, unsigned char type) | |||
| 617 | if ((check_gpio(gpio) < 0) || !type) | 611 | if ((check_gpio(gpio) < 0) || !type) |
| 618 | return -EINVAL; | 612 | return -EINVAL; |
| 619 | 613 | ||
| 620 | local_irq_save(flags); | 614 | local_irq_save_hw(flags); |
| 621 | wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); | 615 | wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); |
| 622 | wakeup_flags_map[gpio] = type; | 616 | wakeup_flags_map[gpio] = type; |
| 623 | local_irq_restore(flags); | 617 | local_irq_restore_hw(flags); |
| 624 | 618 | ||
| 625 | return 0; | 619 | return 0; |
| 626 | } | 620 | } |
| @@ -633,11 +627,11 @@ void gpio_pm_wakeup_free(unsigned gpio) | |||
| 633 | if (check_gpio(gpio) < 0) | 627 | if (check_gpio(gpio) < 0) |
| 634 | return; | 628 | return; |
| 635 | 629 | ||
| 636 | local_irq_save(flags); | 630 | local_irq_save_hw(flags); |
| 637 | 631 | ||
| 638 | wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); | 632 | wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); |
| 639 | 633 | ||
| 640 | local_irq_restore(flags); | 634 | local_irq_restore_hw(flags); |
| 641 | } | 635 | } |
| 642 | EXPORT_SYMBOL(gpio_pm_wakeup_free); | 636 | EXPORT_SYMBOL(gpio_pm_wakeup_free); |
| 643 | 637 | ||
| @@ -679,7 +673,7 @@ u32 bfin_pm_standby_setup(void) | |||
| 679 | gpio_bankb[bank]->maskb = 0; | 673 | gpio_bankb[bank]->maskb = 0; |
| 680 | 674 | ||
| 681 | if (mask) { | 675 | if (mask) { |
| 682 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) | 676 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY) |
| 683 | gpio_bank_saved[bank].fer = *port_fer[bank]; | 677 | gpio_bank_saved[bank].fer = *port_fer[bank]; |
| 684 | #endif | 678 | #endif |
| 685 | gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen; | 679 | gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen; |
| @@ -724,7 +718,7 @@ void bfin_pm_standby_restore(void) | |||
| 724 | bank = gpio_bank(i); | 718 | bank = gpio_bank(i); |
| 725 | 719 | ||
| 726 | if (mask) { | 720 | if (mask) { |
| 727 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) | 721 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY) |
| 728 | *port_fer[bank] = gpio_bank_saved[bank].fer; | 722 | *port_fer[bank] = gpio_bank_saved[bank].fer; |
| 729 | #endif | 723 | #endif |
| 730 | gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen; | 724 | gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen; |
| @@ -750,9 +744,9 @@ void bfin_gpio_pm_hibernate_suspend(void) | |||
| 750 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { | 744 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { |
| 751 | bank = gpio_bank(i); | 745 | bank = gpio_bank(i); |
| 752 | 746 | ||
| 753 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) | 747 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY) |
| 754 | gpio_bank_saved[bank].fer = *port_fer[bank]; | 748 | gpio_bank_saved[bank].fer = *port_fer[bank]; |
| 755 | #ifdef BF527_FAMILY | 749 | #if defined(BF527_FAMILY) || defined(BF518_FAMILY) |
| 756 | gpio_bank_saved[bank].mux = *port_mux[bank]; | 750 | gpio_bank_saved[bank].mux = *port_mux[bank]; |
| 757 | #else | 751 | #else |
| 758 | if (bank == 0) | 752 | if (bank == 0) |
| @@ -778,8 +772,8 @@ void bfin_gpio_pm_hibernate_restore(void) | |||
| 778 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { | 772 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { |
| 779 | bank = gpio_bank(i); | 773 | bank = gpio_bank(i); |
| 780 | 774 | ||
| 781 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) | 775 | #if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY) |
| 782 | #ifdef BF527_FAMILY | 776 | #if defined(BF527_FAMILY) || defined(BF518_FAMILY) |
| 783 | *port_mux[bank] = gpio_bank_saved[bank].mux; | 777 | *port_mux[bank] = gpio_bank_saved[bank].mux; |
| 784 | #else | 778 | #else |
| 785 | if (bank == 0) | 779 | if (bank == 0) |
| @@ -873,7 +867,6 @@ EXPORT_SYMBOL(get_gpio_dir); | |||
| 873 | * MODIFICATION HISTORY : | 867 | * MODIFICATION HISTORY : |
| 874 | **************************************************************/ | 868 | **************************************************************/ |
| 875 | 869 | ||
| 876 | #ifdef BF548_FAMILY | ||
| 877 | int peripheral_request(unsigned short per, const char *label) | 870 | int peripheral_request(unsigned short per, const char *label) |
| 878 | { | 871 | { |
| 879 | unsigned long flags; | 872 | unsigned long flags; |
| @@ -889,31 +882,35 @@ int peripheral_request(unsigned short per, const char *label) | |||
| 889 | if (!(per & P_DEFINED)) | 882 | if (!(per & P_DEFINED)) |
| 890 | return -ENODEV; | 883 | return -ENODEV; |
| 891 | 884 | ||
| 892 | if (check_gpio(ident) < 0) | 885 | local_irq_save_hw(flags); |
| 893 | return -EINVAL; | ||
| 894 | 886 | ||
| 895 | local_irq_save(flags); | 887 | /* If a pin can be muxed as either GPIO or peripheral, make |
| 896 | 888 | * sure it is not already a GPIO pin when we request it. | |
| 897 | if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { | 889 | */ |
| 890 | if (unlikely(!check_gpio(ident) && | ||
| 891 | reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { | ||
| 898 | dump_stack(); | 892 | dump_stack(); |
| 899 | printk(KERN_ERR | 893 | printk(KERN_ERR |
| 900 | "%s: Peripheral %d is already reserved as GPIO by %s !\n", | 894 | "%s: Peripheral %d is already reserved as GPIO by %s !\n", |
| 901 | __func__, ident, get_label(ident)); | 895 | __func__, ident, get_label(ident)); |
| 902 | local_irq_restore(flags); | 896 | local_irq_restore_hw(flags); |
| 903 | return -EBUSY; | 897 | return -EBUSY; |
| 904 | } | 898 | } |
| 905 | 899 | ||
| 906 | if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) { | 900 | if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) { |
| 907 | 901 | ||
| 908 | u16 funct = get_portmux(ident); | ||
| 909 | |||
| 910 | /* | 902 | /* |
| 911 | * Pin functions like AMC address strobes my | 903 | * Pin functions like AMC address strobes my |
| 912 | * be requested and used by several drivers | 904 | * be requested and used by several drivers |
| 913 | */ | 905 | */ |
| 914 | 906 | ||
| 915 | if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) { | 907 | #ifdef BF548_FAMILY |
| 908 | u16 funct = get_portmux(ident); | ||
| 916 | 909 | ||
| 910 | if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) { | ||
| 911 | #else | ||
| 912 | if (!(per & P_MAYSHARE)) { | ||
| 913 | #endif | ||
| 917 | /* | 914 | /* |
| 918 | * Allow that the identical pin function can | 915 | * Allow that the identical pin function can |
| 919 | * be requested from the same driver twice | 916 | * be requested from the same driver twice |
| @@ -926,7 +923,7 @@ int peripheral_request(unsigned short per, const char *label) | |||
| 926 | printk(KERN_ERR | 923 | printk(KERN_ERR |
| 927 | "%s: Peripheral %d function %d is already reserved by %s !\n", | 924 | "%s: Peripheral %d function %d is already reserved by %s !\n", |
| 928 | __func__, ident, P_FUNCT2MUX(per), get_label(ident)); | 925 | __func__, ident, P_FUNCT2MUX(per), get_label(ident)); |
| 929 | local_irq_restore(flags); | 926 | local_irq_restore_hw(flags); |
| 930 | return -EBUSY; | 927 | return -EBUSY; |
| 931 | } | 928 | } |
| 932 | } | 929 | } |
| @@ -934,89 +931,19 @@ int peripheral_request(unsigned short per, const char *label) | |||
| 934 | anyway: | 931 | anyway: |
| 935 | reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident); | 932 | reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident); |
| 936 | 933 | ||
| 934 | #ifdef BF548_FAMILY | ||
| 937 | portmux_setup(ident, P_FUNCT2MUX(per)); | 935 | portmux_setup(ident, P_FUNCT2MUX(per)); |
| 938 | port_setup(ident, PERIPHERAL_USAGE); | ||
| 939 | |||
| 940 | local_irq_restore(flags); | ||
| 941 | set_label(ident, label); | ||
| 942 | |||
| 943 | return 0; | ||
| 944 | } | ||
| 945 | EXPORT_SYMBOL(peripheral_request); | ||
| 946 | #else | 936 | #else |
| 947 | |||
| 948 | int peripheral_request(unsigned short per, const char *label) | ||
| 949 | { | ||
| 950 | unsigned long flags; | ||
| 951 | unsigned short ident = P_IDENT(per); | ||
| 952 | |||
| 953 | /* | ||
| 954 | * Don't cares are pins with only one dedicated function | ||
| 955 | */ | ||
| 956 | |||
| 957 | if (per & P_DONTCARE) | ||
| 958 | return 0; | ||
| 959 | |||
| 960 | if (!(per & P_DEFINED)) | ||
| 961 | return -ENODEV; | ||
| 962 | |||
| 963 | local_irq_save(flags); | ||
| 964 | |||
| 965 | if (!check_gpio(ident)) { | ||
| 966 | |||
| 967 | if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { | ||
| 968 | dump_stack(); | ||
| 969 | printk(KERN_ERR | ||
| 970 | "%s: Peripheral %d is already reserved as GPIO by %s !\n", | ||
| 971 | __func__, ident, get_label(ident)); | ||
| 972 | local_irq_restore(flags); | ||
| 973 | return -EBUSY; | ||
| 974 | } | ||
| 975 | |||
| 976 | } | ||
| 977 | |||
| 978 | if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) { | ||
| 979 | |||
| 980 | /* | ||
| 981 | * Pin functions like AMC address strobes my | ||
| 982 | * be requested and used by several drivers | ||
| 983 | */ | ||
| 984 | |||
| 985 | if (!(per & P_MAYSHARE)) { | ||
| 986 | |||
| 987 | /* | ||
| 988 | * Allow that the identical pin function can | ||
| 989 | * be requested from the same driver twice | ||
| 990 | */ | ||
| 991 | |||
| 992 | if (cmp_label(ident, label) == 0) | ||
| 993 | goto anyway; | ||
| 994 | |||
| 995 | dump_stack(); | ||
| 996 | printk(KERN_ERR | ||
| 997 | "%s: Peripheral %d function %d is already" | ||
| 998 | " reserved by %s !\n", | ||
| 999 | __func__, ident, P_FUNCT2MUX(per), | ||
| 1000 | get_label(ident)); | ||
| 1001 | local_irq_restore(flags); | ||
| 1002 | return -EBUSY; | ||
| 1003 | } | ||
| 1004 | |||
| 1005 | } | ||
| 1006 | |||
| 1007 | anyway: | ||
| 1008 | portmux_setup(per, P_FUNCT2MUX(per)); | 937 | portmux_setup(per, P_FUNCT2MUX(per)); |
| 1009 | 938 | #endif | |
| 1010 | port_setup(ident, PERIPHERAL_USAGE); | 939 | port_setup(ident, PERIPHERAL_USAGE); |
| 1011 | 940 | ||
| 1012 | reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident); | 941 | local_irq_restore_hw(flags); |
| 1013 | local_irq_restore(flags); | ||
| 1014 | set_label(ident, label); | 942 | set_label(ident, label); |
| 1015 | 943 | ||
| 1016 | return 0; | 944 | return 0; |
| 1017 | } | 945 | } |
| 1018 | EXPORT_SYMBOL(peripheral_request); | 946 | EXPORT_SYMBOL(peripheral_request); |
| 1019 | #endif | ||
| 1020 | 947 | ||
| 1021 | int peripheral_request_list(const unsigned short per[], const char *label) | 948 | int peripheral_request_list(const unsigned short per[], const char *label) |
| 1022 | { | 949 | { |
| @@ -1053,10 +980,10 @@ void peripheral_free(unsigned short per) | |||
| 1053 | if (check_gpio(ident) < 0) | 980 | if (check_gpio(ident) < 0) |
| 1054 | return; | 981 | return; |
| 1055 | 982 | ||
| 1056 | local_irq_save(flags); | 983 | local_irq_save_hw(flags); |
| 1057 | 984 | ||
| 1058 | if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) { | 985 | if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) { |
| 1059 | local_irq_restore(flags); | 986 | local_irq_restore_hw(flags); |
| 1060 | return; | 987 | return; |
| 1061 | } | 988 | } |
| 1062 | 989 | ||
| @@ -1067,7 +994,7 @@ void peripheral_free(unsigned short per) | |||
| 1067 | 994 | ||
| 1068 | set_label(ident, "free"); | 995 | set_label(ident, "free"); |
| 1069 | 996 | ||
| 1070 | local_irq_restore(flags); | 997 | local_irq_restore_hw(flags); |
| 1071 | } | 998 | } |
| 1072 | EXPORT_SYMBOL(peripheral_free); | 999 | EXPORT_SYMBOL(peripheral_free); |
| 1073 | 1000 | ||
| @@ -1094,14 +1021,14 @@ EXPORT_SYMBOL(peripheral_free_list); | |||
| 1094 | * MODIFICATION HISTORY : | 1021 | * MODIFICATION HISTORY : |
| 1095 | **************************************************************/ | 1022 | **************************************************************/ |
| 1096 | 1023 | ||
| 1097 | int gpio_request(unsigned gpio, const char *label) | 1024 | int bfin_gpio_request(unsigned gpio, const char *label) |
| 1098 | { | 1025 | { |
| 1099 | unsigned long flags; | 1026 | unsigned long flags; |
| 1100 | 1027 | ||
| 1101 | if (check_gpio(gpio) < 0) | 1028 | if (check_gpio(gpio) < 0) |
| 1102 | return -EINVAL; | 1029 | return -EINVAL; |
| 1103 | 1030 | ||
| 1104 | local_irq_save(flags); | 1031 | local_irq_save_hw(flags); |
| 1105 | 1032 | ||
| 1106 | /* | 1033 | /* |
| 1107 | * Allow that the identical GPIO can | 1034 | * Allow that the identical GPIO can |
| @@ -1110,15 +1037,15 @@ int gpio_request(unsigned gpio, const char *label) | |||
| 1110 | */ | 1037 | */ |
| 1111 | 1038 | ||
| 1112 | if (cmp_label(gpio, label) == 0) { | 1039 | if (cmp_label(gpio, label) == 0) { |
| 1113 | local_irq_restore(flags); | 1040 | local_irq_restore_hw(flags); |
| 1114 | return 0; | 1041 | return 0; |
| 1115 | } | 1042 | } |
| 1116 | 1043 | ||
| 1117 | if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | 1044 | if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { |
| 1118 | dump_stack(); | 1045 | dump_stack(); |
| 1119 | printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", | 1046 | printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", |
| 1120 | gpio, get_label(gpio)); | 1047 | gpio, get_label(gpio)); |
| 1121 | local_irq_restore(flags); | 1048 | local_irq_restore_hw(flags); |
| 1122 | return -EBUSY; | 1049 | return -EBUSY; |
| 1123 | } | 1050 | } |
| 1124 | if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | 1051 | if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { |
| @@ -1126,34 +1053,37 @@ int gpio_request(unsigned gpio, const char *label) | |||
| 1126 | printk(KERN_ERR | 1053 | printk(KERN_ERR |
| 1127 | "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", | 1054 | "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", |
| 1128 | gpio, get_label(gpio)); | 1055 | gpio, get_label(gpio)); |
| 1129 | local_irq_restore(flags); | 1056 | local_irq_restore_hw(flags); |
| 1130 | return -EBUSY; | 1057 | return -EBUSY; |
| 1131 | } | 1058 | } |
| 1059 | if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) | ||
| 1060 | printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!" | ||
| 1061 | " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio); | ||
| 1132 | 1062 | ||
| 1133 | reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); | 1063 | reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); |
| 1064 | set_label(gpio, label); | ||
| 1134 | 1065 | ||
| 1135 | local_irq_restore(flags); | 1066 | local_irq_restore_hw(flags); |
| 1136 | 1067 | ||
| 1137 | port_setup(gpio, GPIO_USAGE); | 1068 | port_setup(gpio, GPIO_USAGE); |
| 1138 | set_label(gpio, label); | ||
| 1139 | 1069 | ||
| 1140 | return 0; | 1070 | return 0; |
| 1141 | } | 1071 | } |
| 1142 | EXPORT_SYMBOL(gpio_request); | 1072 | EXPORT_SYMBOL(bfin_gpio_request); |
| 1143 | 1073 | ||
| 1144 | void gpio_free(unsigned gpio) | 1074 | void bfin_gpio_free(unsigned gpio) |
| 1145 | { | 1075 | { |
| 1146 | unsigned long flags; | 1076 | unsigned long flags; |
| 1147 | 1077 | ||
| 1148 | if (check_gpio(gpio) < 0) | 1078 | if (check_gpio(gpio) < 0) |
| 1149 | return; | 1079 | return; |
| 1150 | 1080 | ||
| 1151 | local_irq_save(flags); | 1081 | local_irq_save_hw(flags); |
| 1152 | 1082 | ||
| 1153 | if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { | 1083 | if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { |
| 1154 | dump_stack(); | 1084 | dump_stack(); |
| 1155 | gpio_error(gpio); | 1085 | gpio_error(gpio); |
| 1156 | local_irq_restore(flags); | 1086 | local_irq_restore_hw(flags); |
| 1157 | return; | 1087 | return; |
| 1158 | } | 1088 | } |
| 1159 | 1089 | ||
| @@ -1161,13 +1091,76 @@ void gpio_free(unsigned gpio) | |||
| 1161 | 1091 | ||
| 1162 | set_label(gpio, "free"); | 1092 | set_label(gpio, "free"); |
| 1163 | 1093 | ||
| 1164 | local_irq_restore(flags); | 1094 | local_irq_restore_hw(flags); |
| 1095 | } | ||
| 1096 | EXPORT_SYMBOL(bfin_gpio_free); | ||
| 1097 | |||
| 1098 | int bfin_gpio_irq_request(unsigned gpio, const char *label) | ||
| 1099 | { | ||
| 1100 | unsigned long flags; | ||
| 1101 | |||
| 1102 | if (check_gpio(gpio) < 0) | ||
| 1103 | return -EINVAL; | ||
| 1104 | |||
| 1105 | local_irq_save_hw(flags); | ||
| 1106 | |||
| 1107 | if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | ||
| 1108 | dump_stack(); | ||
| 1109 | printk(KERN_ERR | ||
| 1110 | "bfin-gpio: GPIO %d is already reserved as gpio-irq !\n", | ||
| 1111 | gpio); | ||
| 1112 | local_irq_restore_hw(flags); | ||
| 1113 | return -EBUSY; | ||
| 1114 | } | ||
| 1115 | if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | ||
| 1116 | dump_stack(); | ||
| 1117 | printk(KERN_ERR | ||
| 1118 | "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", | ||
| 1119 | gpio, get_label(gpio)); | ||
| 1120 | local_irq_restore_hw(flags); | ||
| 1121 | return -EBUSY; | ||
| 1122 | } | ||
| 1123 | if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) | ||
| 1124 | printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! " | ||
| 1125 | "(Documentation/blackfin/bfin-gpio-notes.txt)\n", | ||
| 1126 | gpio, get_label(gpio)); | ||
| 1127 | |||
| 1128 | reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio); | ||
| 1129 | set_label(gpio, label); | ||
| 1130 | |||
| 1131 | local_irq_restore_hw(flags); | ||
| 1132 | |||
| 1133 | port_setup(gpio, GPIO_USAGE); | ||
| 1134 | |||
| 1135 | return 0; | ||
| 1136 | } | ||
| 1137 | |||
| 1138 | void bfin_gpio_irq_free(unsigned gpio) | ||
| 1139 | { | ||
| 1140 | unsigned long flags; | ||
| 1141 | |||
| 1142 | if (check_gpio(gpio) < 0) | ||
| 1143 | return; | ||
| 1144 | |||
| 1145 | local_irq_save_hw(flags); | ||
| 1146 | |||
| 1147 | if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { | ||
| 1148 | dump_stack(); | ||
| 1149 | gpio_error(gpio); | ||
| 1150 | local_irq_restore_hw(flags); | ||
| 1151 | return; | ||
| 1152 | } | ||
| 1153 | |||
| 1154 | reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); | ||
| 1155 | |||
| 1156 | set_label(gpio, "free"); | ||
| 1157 | |||
| 1158 | local_irq_restore_hw(flags); | ||
| 1165 | } | 1159 | } |
| 1166 | EXPORT_SYMBOL(gpio_free); | ||
| 1167 | 1160 | ||
| 1168 | 1161 | ||
| 1169 | #ifdef BF548_FAMILY | 1162 | #ifdef BF548_FAMILY |
| 1170 | int gpio_direction_input(unsigned gpio) | 1163 | int bfin_gpio_direction_input(unsigned gpio) |
| 1171 | { | 1164 | { |
| 1172 | unsigned long flags; | 1165 | unsigned long flags; |
| 1173 | 1166 | ||
| @@ -1176,16 +1169,16 @@ int gpio_direction_input(unsigned gpio) | |||
| 1176 | return -EINVAL; | 1169 | return -EINVAL; |
| 1177 | } | 1170 | } |
| 1178 | 1171 | ||
| 1179 | local_irq_save(flags); | 1172 | local_irq_save_hw(flags); |
| 1180 | gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); | 1173 | gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); |
| 1181 | gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); | 1174 | gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); |
| 1182 | local_irq_restore(flags); | 1175 | local_irq_restore_hw(flags); |
| 1183 | 1176 | ||
| 1184 | return 0; | 1177 | return 0; |
| 1185 | } | 1178 | } |
| 1186 | EXPORT_SYMBOL(gpio_direction_input); | 1179 | EXPORT_SYMBOL(bfin_gpio_direction_input); |
| 1187 | 1180 | ||
| 1188 | int gpio_direction_output(unsigned gpio, int value) | 1181 | int bfin_gpio_direction_output(unsigned gpio, int value) |
| 1189 | { | 1182 | { |
| 1190 | unsigned long flags; | 1183 | unsigned long flags; |
| 1191 | 1184 | ||
| @@ -1194,30 +1187,30 @@ int gpio_direction_output(unsigned gpio, int value) | |||
| 1194 | return -EINVAL; | 1187 | return -EINVAL; |
| 1195 | } | 1188 | } |
| 1196 | 1189 | ||
| 1197 | local_irq_save(flags); | 1190 | local_irq_save_hw(flags); |
| 1198 | gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio); | 1191 | gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio); |
| 1199 | gpio_set_value(gpio, value); | 1192 | gpio_set_value(gpio, value); |
| 1200 | gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio); | 1193 | gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio); |
| 1201 | local_irq_restore(flags); | 1194 | local_irq_restore_hw(flags); |
| 1202 | 1195 | ||
| 1203 | return 0; | 1196 | return 0; |
| 1204 | } | 1197 | } |
| 1205 | EXPORT_SYMBOL(gpio_direction_output); | 1198 | EXPORT_SYMBOL(bfin_gpio_direction_output); |
| 1206 | 1199 | ||
| 1207 | void gpio_set_value(unsigned gpio, int arg) | 1200 | void bfin_gpio_set_value(unsigned gpio, int arg) |
| 1208 | { | 1201 | { |
| 1209 | if (arg) | 1202 | if (arg) |
| 1210 | gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio); | 1203 | gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio); |
| 1211 | else | 1204 | else |
| 1212 | gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio); | 1205 | gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio); |
| 1213 | } | 1206 | } |
| 1214 | EXPORT_SYMBOL(gpio_set_value); | 1207 | EXPORT_SYMBOL(bfin_gpio_set_value); |
| 1215 | 1208 | ||
| 1216 | int gpio_get_value(unsigned gpio) | 1209 | int bfin_gpio_get_value(unsigned gpio) |
| 1217 | { | 1210 | { |
| 1218 | return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio))); | 1211 | return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio))); |
| 1219 | } | 1212 | } |
| 1220 | EXPORT_SYMBOL(gpio_get_value); | 1213 | EXPORT_SYMBOL(bfin_gpio_get_value); |
| 1221 | 1214 | ||
| 1222 | void bfin_gpio_irq_prepare(unsigned gpio) | 1215 | void bfin_gpio_irq_prepare(unsigned gpio) |
| 1223 | { | 1216 | { |
| @@ -1225,34 +1218,34 @@ void bfin_gpio_irq_prepare(unsigned gpio) | |||
| 1225 | 1218 | ||
| 1226 | port_setup(gpio, GPIO_USAGE); | 1219 | port_setup(gpio, GPIO_USAGE); |
| 1227 | 1220 | ||
| 1228 | local_irq_save(flags); | 1221 | local_irq_save_hw(flags); |
| 1229 | gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); | 1222 | gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); |
| 1230 | gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); | 1223 | gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio); |
| 1231 | local_irq_restore(flags); | 1224 | local_irq_restore_hw(flags); |
| 1232 | } | 1225 | } |
| 1233 | 1226 | ||
| 1234 | #else | 1227 | #else |
| 1235 | 1228 | ||
| 1236 | int gpio_get_value(unsigned gpio) | 1229 | int bfin_gpio_get_value(unsigned gpio) |
| 1237 | { | 1230 | { |
| 1238 | unsigned long flags; | 1231 | unsigned long flags; |
| 1239 | int ret; | 1232 | int ret; |
| 1240 | 1233 | ||
| 1241 | if (unlikely(get_gpio_edge(gpio))) { | 1234 | if (unlikely(get_gpio_edge(gpio))) { |
| 1242 | local_irq_save(flags); | 1235 | local_irq_save_hw(flags); |
| 1243 | set_gpio_edge(gpio, 0); | 1236 | set_gpio_edge(gpio, 0); |
| 1244 | ret = get_gpio_data(gpio); | 1237 | ret = get_gpio_data(gpio); |
| 1245 | set_gpio_edge(gpio, 1); | 1238 | set_gpio_edge(gpio, 1); |
| 1246 | local_irq_restore(flags); | 1239 | local_irq_restore_hw(flags); |
| 1247 | 1240 | ||
| 1248 | return ret; | 1241 | return ret; |
| 1249 | } else | 1242 | } else |
| 1250 | return get_gpio_data(gpio); | 1243 | return get_gpio_data(gpio); |
| 1251 | } | 1244 | } |
| 1252 | EXPORT_SYMBOL(gpio_get_value); | 1245 | EXPORT_SYMBOL(bfin_gpio_get_value); |
| 1253 | 1246 | ||
| 1254 | 1247 | ||
| 1255 | int gpio_direction_input(unsigned gpio) | 1248 | int bfin_gpio_direction_input(unsigned gpio) |
| 1256 | { | 1249 | { |
| 1257 | unsigned long flags; | 1250 | unsigned long flags; |
| 1258 | 1251 | ||
| @@ -1261,17 +1254,17 @@ int gpio_direction_input(unsigned gpio) | |||
| 1261 | return -EINVAL; | 1254 | return -EINVAL; |
| 1262 | } | 1255 | } |
| 1263 | 1256 | ||
| 1264 | local_irq_save(flags); | 1257 | local_irq_save_hw(flags); |
| 1265 | gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); | 1258 | gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); |
| 1266 | gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio); | 1259 | gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio); |
| 1267 | AWA_DUMMY_READ(inen); | 1260 | AWA_DUMMY_READ(inen); |
| 1268 | local_irq_restore(flags); | 1261 | local_irq_restore_hw(flags); |
| 1269 | 1262 | ||
| 1270 | return 0; | 1263 | return 0; |
| 1271 | } | 1264 | } |
| 1272 | EXPORT_SYMBOL(gpio_direction_input); | 1265 | EXPORT_SYMBOL(bfin_gpio_direction_input); |
| 1273 | 1266 | ||
| 1274 | int gpio_direction_output(unsigned gpio, int value) | 1267 | int bfin_gpio_direction_output(unsigned gpio, int value) |
| 1275 | { | 1268 | { |
| 1276 | unsigned long flags; | 1269 | unsigned long flags; |
| 1277 | 1270 | ||
| @@ -1280,7 +1273,7 @@ int gpio_direction_output(unsigned gpio, int value) | |||
| 1280 | return -EINVAL; | 1273 | return -EINVAL; |
| 1281 | } | 1274 | } |
| 1282 | 1275 | ||
| 1283 | local_irq_save(flags); | 1276 | local_irq_save_hw(flags); |
| 1284 | gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); | 1277 | gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); |
| 1285 | 1278 | ||
| 1286 | if (value) | 1279 | if (value) |
| @@ -1290,11 +1283,11 @@ int gpio_direction_output(unsigned gpio, int value) | |||
| 1290 | 1283 | ||
| 1291 | gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio); | 1284 | gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio); |
| 1292 | AWA_DUMMY_READ(dir); | 1285 | AWA_DUMMY_READ(dir); |
| 1293 | local_irq_restore(flags); | 1286 | local_irq_restore_hw(flags); |
| 1294 | 1287 | ||
| 1295 | return 0; | 1288 | return 0; |
| 1296 | } | 1289 | } |
| 1297 | EXPORT_SYMBOL(gpio_direction_output); | 1290 | EXPORT_SYMBOL(bfin_gpio_direction_output); |
| 1298 | 1291 | ||
| 1299 | /* If we are booting from SPI and our board lacks a strong enough pull up, | 1292 | /* If we are booting from SPI and our board lacks a strong enough pull up, |
| 1300 | * the core can reset and execute the bootrom faster than the resistor can | 1293 | * the core can reset and execute the bootrom faster than the resistor can |
| @@ -1327,14 +1320,17 @@ void bfin_gpio_irq_prepare(unsigned gpio) | |||
| 1327 | static int gpio_proc_read(char *buf, char **start, off_t offset, | 1320 | static int gpio_proc_read(char *buf, char **start, off_t offset, |
| 1328 | int len, int *unused_i, void *unused_v) | 1321 | int len, int *unused_i, void *unused_v) |
| 1329 | { | 1322 | { |
| 1330 | int c, outlen = 0; | 1323 | int c, irq, gpio, outlen = 0; |
| 1331 | 1324 | ||
| 1332 | for (c = 0; c < MAX_RESOURCES; c++) { | 1325 | for (c = 0; c < MAX_RESOURCES; c++) { |
| 1333 | if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c))) | 1326 | irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c); |
| 1334 | len = sprintf(buf, "GPIO_%d: %s \t\tGPIO %s\n", c, | 1327 | gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c); |
| 1335 | get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT"); | 1328 | if (!check_gpio(c) && (gpio || irq)) |
| 1329 | len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c, | ||
| 1330 | get_label(c), (gpio && irq) ? " *" : "", | ||
| 1331 | get_gpio_dir(c) ? "OUTPUT" : "INPUT"); | ||
| 1336 | else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c)) | 1332 | else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c)) |
| 1337 | len = sprintf(buf, "GPIO_%d: %s \t\tPeripheral\n", c, get_label(c)); | 1333 | len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c)); |
| 1338 | else | 1334 | else |
| 1339 | continue; | 1335 | continue; |
| 1340 | buf += len; | 1336 | buf += len; |
| @@ -1354,3 +1350,57 @@ static __init int gpio_register_proc(void) | |||
| 1354 | } | 1350 | } |
| 1355 | __initcall(gpio_register_proc); | 1351 | __initcall(gpio_register_proc); |
| 1356 | #endif | 1352 | #endif |
| 1353 | |||
| 1354 | #ifdef CONFIG_GPIOLIB | ||
| 1355 | int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio) | ||
| 1356 | { | ||
| 1357 | return bfin_gpio_direction_input(gpio); | ||
| 1358 | } | ||
| 1359 | |||
| 1360 | int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level) | ||
| 1361 | { | ||
| 1362 | return bfin_gpio_direction_output(gpio, level); | ||
| 1363 | } | ||
| 1364 | |||
| 1365 | int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio) | ||
| 1366 | { | ||
| 1367 | return bfin_gpio_get_value(gpio); | ||
| 1368 | } | ||
| 1369 | |||
| 1370 | void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value) | ||
| 1371 | { | ||
| 1372 | #ifdef BF548_FAMILY | ||
| 1373 | return bfin_gpio_set_value(gpio, value); | ||
| 1374 | #else | ||
| 1375 | return set_gpio_data(gpio, value); | ||
| 1376 | #endif | ||
| 1377 | } | ||
| 1378 | |||
| 1379 | int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio) | ||
| 1380 | { | ||
| 1381 | return bfin_gpio_request(gpio, chip->label); | ||
| 1382 | } | ||
| 1383 | |||
| 1384 | void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio) | ||
| 1385 | { | ||
| 1386 | return bfin_gpio_free(gpio); | ||
| 1387 | } | ||
| 1388 | |||
| 1389 | static struct gpio_chip bfin_chip = { | ||
| 1390 | .label = "Blackfin-GPIOlib", | ||
| 1391 | .direction_input = bfin_gpiolib_direction_input, | ||
| 1392 | .get = bfin_gpiolib_get_value, | ||
| 1393 | .direction_output = bfin_gpiolib_direction_output, | ||
| 1394 | .set = bfin_gpiolib_set_value, | ||
| 1395 | .request = bfin_gpiolib_gpio_request, | ||
| 1396 | .free = bfin_gpiolib_gpio_free, | ||
| 1397 | .base = 0, | ||
| 1398 | .ngpio = MAX_BLACKFIN_GPIOS, | ||
| 1399 | }; | ||
| 1400 | |||
| 1401 | static int __init bfin_gpiolib_setup(void) | ||
| 1402 | { | ||
| 1403 | return gpiochip_add(&bfin_chip); | ||
| 1404 | } | ||
| 1405 | arch_initcall(bfin_gpiolib_setup); | ||
| 1406 | #endif | ||
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c index 4367330909b2..01f917d58b59 100644 --- a/arch/blackfin/kernel/bfin_ksyms.c +++ b/arch/blackfin/kernel/bfin_ksyms.c | |||
| @@ -1,52 +1,25 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: arch/blackfin/kernel/bfin_ksyms.c | 2 | * arch/blackfin/kernel/bfin_ksyms.c - exports for random symbols |
| 3 | * Based on: none - original work | ||
| 4 | * Author: | ||
| 5 | * | 3 | * |
| 6 | * Created: | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 7 | * Description: | ||
| 8 | * | 5 | * |
| 9 | * Modified: | 6 | * Licensed under the GPL-2 or later. |
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | 7 | */ |
| 29 | 8 | ||
| 30 | #include <linux/module.h> | 9 | #include <linux/module.h> |
| 31 | #include <linux/irq.h> | ||
| 32 | #include <linux/uaccess.h> | 10 | #include <linux/uaccess.h> |
| 33 | 11 | ||
| 34 | #include <asm/checksum.h> | ||
| 35 | #include <asm/cacheflush.h> | 12 | #include <asm/cacheflush.h> |
| 36 | 13 | ||
| 37 | /* platform dependent support */ | 14 | /* Allow people to have their own Blackfin exception handler in a module */ |
| 38 | |||
| 39 | EXPORT_SYMBOL(__ioremap); | ||
| 40 | |||
| 41 | EXPORT_SYMBOL(ip_fast_csum); | ||
| 42 | |||
| 43 | EXPORT_SYMBOL(kernel_thread); | ||
| 44 | |||
| 45 | EXPORT_SYMBOL(is_in_rom); | ||
| 46 | EXPORT_SYMBOL(bfin_return_from_exception); | 15 | EXPORT_SYMBOL(bfin_return_from_exception); |
| 47 | 16 | ||
| 48 | /* Networking helper routines. */ | 17 | /* All the Blackfin cache functions: mach-common/cache.S */ |
| 49 | EXPORT_SYMBOL(csum_partial_copy); | 18 | EXPORT_SYMBOL(blackfin_dcache_invalidate_range); |
| 19 | EXPORT_SYMBOL(blackfin_icache_dcache_flush_range); | ||
| 20 | EXPORT_SYMBOL(blackfin_icache_flush_range); | ||
| 21 | EXPORT_SYMBOL(blackfin_dcache_flush_range); | ||
| 22 | EXPORT_SYMBOL(blackfin_dflush_page); | ||
| 50 | 23 | ||
| 51 | /* The following are special because they're not called | 24 | /* The following are special because they're not called |
| 52 | * explicitly (the C compiler generates them). Fortunately, | 25 | * explicitly (the C compiler generates them). Fortunately, |
| @@ -74,8 +47,6 @@ extern void __modsi3(void); | |||
| 74 | extern void __muldi3(void); | 47 | extern void __muldi3(void); |
| 75 | extern void __udivsi3(void); | 48 | extern void __udivsi3(void); |
| 76 | extern void __umodsi3(void); | 49 | extern void __umodsi3(void); |
| 77 | |||
| 78 | /* gcc lib functions */ | ||
| 79 | EXPORT_SYMBOL(__ashldi3); | 50 | EXPORT_SYMBOL(__ashldi3); |
| 80 | EXPORT_SYMBOL(__ashrdi3); | 51 | EXPORT_SYMBOL(__ashrdi3); |
| 81 | EXPORT_SYMBOL(__umulsi3_highpart); | 52 | EXPORT_SYMBOL(__umulsi3_highpart); |
| @@ -87,6 +58,7 @@ EXPORT_SYMBOL(__muldi3); | |||
| 87 | EXPORT_SYMBOL(__udivsi3); | 58 | EXPORT_SYMBOL(__udivsi3); |
| 88 | EXPORT_SYMBOL(__umodsi3); | 59 | EXPORT_SYMBOL(__umodsi3); |
| 89 | 60 | ||
| 61 | /* Input/output symbols: lib/{in,out}s.S */ | ||
| 90 | EXPORT_SYMBOL(outsb); | 62 | EXPORT_SYMBOL(outsb); |
| 91 | EXPORT_SYMBOL(insb); | 63 | EXPORT_SYMBOL(insb); |
| 92 | EXPORT_SYMBOL(outsw); | 64 | EXPORT_SYMBOL(outsw); |
| @@ -96,20 +68,39 @@ EXPORT_SYMBOL(insw_8); | |||
| 96 | EXPORT_SYMBOL(outsl); | 68 | EXPORT_SYMBOL(outsl); |
| 97 | EXPORT_SYMBOL(insl); | 69 | EXPORT_SYMBOL(insl); |
| 98 | EXPORT_SYMBOL(insl_16); | 70 | EXPORT_SYMBOL(insl_16); |
| 99 | EXPORT_SYMBOL(irq_flags); | ||
| 100 | EXPORT_SYMBOL(iounmap); | ||
| 101 | EXPORT_SYMBOL(blackfin_dcache_invalidate_range); | ||
| 102 | EXPORT_SYMBOL(blackfin_icache_dcache_flush_range); | ||
| 103 | EXPORT_SYMBOL(blackfin_icache_flush_range); | ||
| 104 | EXPORT_SYMBOL(blackfin_dcache_flush_range); | ||
| 105 | EXPORT_SYMBOL(blackfin_dflush_page); | ||
| 106 | 71 | ||
| 107 | EXPORT_SYMBOL(csum_partial); | 72 | #ifdef CONFIG_SMP |
| 108 | EXPORT_SYMBOL(__init_begin); | 73 | EXPORT_SYMBOL(__raw_atomic_update_asm); |
| 109 | EXPORT_SYMBOL(__init_end); | 74 | EXPORT_SYMBOL(__raw_atomic_clear_asm); |
| 110 | EXPORT_SYMBOL(_ebss_l1); | 75 | EXPORT_SYMBOL(__raw_atomic_set_asm); |
| 111 | EXPORT_SYMBOL(_stext_l1); | 76 | EXPORT_SYMBOL(__raw_atomic_xor_asm); |
| 112 | EXPORT_SYMBOL(_etext_l1); | 77 | EXPORT_SYMBOL(__raw_atomic_test_asm); |
| 113 | EXPORT_SYMBOL(_sdata_l1); | 78 | EXPORT_SYMBOL(__raw_xchg_1_asm); |
| 114 | EXPORT_SYMBOL(_ebss_b_l1); | 79 | EXPORT_SYMBOL(__raw_xchg_2_asm); |
| 115 | EXPORT_SYMBOL(_sdata_b_l1); | 80 | EXPORT_SYMBOL(__raw_xchg_4_asm); |
| 81 | EXPORT_SYMBOL(__raw_cmpxchg_1_asm); | ||
| 82 | EXPORT_SYMBOL(__raw_cmpxchg_2_asm); | ||
| 83 | EXPORT_SYMBOL(__raw_cmpxchg_4_asm); | ||
| 84 | EXPORT_SYMBOL(__raw_spin_is_locked_asm); | ||
| 85 | EXPORT_SYMBOL(__raw_spin_lock_asm); | ||
| 86 | EXPORT_SYMBOL(__raw_spin_trylock_asm); | ||
| 87 | EXPORT_SYMBOL(__raw_spin_unlock_asm); | ||
| 88 | EXPORT_SYMBOL(__raw_read_lock_asm); | ||
| 89 | EXPORT_SYMBOL(__raw_read_trylock_asm); | ||
| 90 | EXPORT_SYMBOL(__raw_read_unlock_asm); | ||
| 91 | EXPORT_SYMBOL(__raw_write_lock_asm); | ||
| 92 | EXPORT_SYMBOL(__raw_write_trylock_asm); | ||
| 93 | EXPORT_SYMBOL(__raw_write_unlock_asm); | ||
| 94 | EXPORT_SYMBOL(__raw_bit_set_asm); | ||
| 95 | EXPORT_SYMBOL(__raw_bit_clear_asm); | ||
| 96 | EXPORT_SYMBOL(__raw_bit_toggle_asm); | ||
| 97 | EXPORT_SYMBOL(__raw_bit_test_asm); | ||
| 98 | EXPORT_SYMBOL(__raw_bit_test_set_asm); | ||
| 99 | EXPORT_SYMBOL(__raw_bit_test_clear_asm); | ||
| 100 | EXPORT_SYMBOL(__raw_bit_test_toggle_asm); | ||
| 101 | EXPORT_SYMBOL(__raw_uncached_fetch_asm); | ||
| 102 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 103 | EXPORT_SYMBOL(__raw_smp_mark_barrier_asm); | ||
| 104 | EXPORT_SYMBOL(__raw_smp_check_barrier_asm); | ||
| 105 | #endif | ||
| 106 | #endif | ||
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile index 286b69357f97..7d70d3bf3212 100644 --- a/arch/blackfin/kernel/cplb-mpu/Makefile +++ b/arch/blackfin/kernel/cplb-mpu/Makefile | |||
| @@ -4,5 +4,7 @@ | |||
| 4 | 4 | ||
| 5 | obj-y := cplbinit.o cacheinit.o cplbmgr.o | 5 | obj-y := cplbinit.o cacheinit.o cplbmgr.o |
| 6 | 6 | ||
| 7 | obj-$(CONFIG_CPLB_INFO) += cplbinfo.o | 7 | CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ |
| 8 | 8 | -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ | |
| 9 | -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \ | ||
| 10 | -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3 | ||
diff --git a/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c index a8b712a24c59..c6ff947f9d37 100644 --- a/arch/blackfin/kernel/cplb-mpu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | #include <asm/cplbinit.h> | 25 | #include <asm/cplbinit.h> |
| 26 | 26 | ||
| 27 | #if defined(CONFIG_BFIN_ICACHE) | 27 | #if defined(CONFIG_BFIN_ICACHE) |
| 28 | void __init bfin_icache_init(void) | 28 | void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) |
| 29 | { | 29 | { |
| 30 | unsigned long ctrl; | 30 | unsigned long ctrl; |
| 31 | int i; | 31 | int i; |
| @@ -43,7 +43,7 @@ void __init bfin_icache_init(void) | |||
| 43 | #endif | 43 | #endif |
| 44 | 44 | ||
| 45 | #if defined(CONFIG_BFIN_DCACHE) | 45 | #if defined(CONFIG_BFIN_DCACHE) |
| 46 | void __init bfin_dcache_init(void) | 46 | void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) |
| 47 | { | 47 | { |
| 48 | unsigned long ctrl; | 48 | unsigned long ctrl; |
| 49 | int i; | 49 | int i; |
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c deleted file mode 100644 index 822beefa3a4b..000000000000 --- a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c +++ /dev/null | |||
| @@ -1,136 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-common/cplbinfo.c | ||
| 3 | * Based on: | ||
| 4 | * Author: Sonic Zhang <sonic.zhang@analog.com> | ||
| 5 | * | ||
| 6 | * Created: Jan. 2005 | ||
| 7 | * Description: Display CPLB status | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/module.h> | ||
| 31 | #include <linux/kernel.h> | ||
| 32 | #include <linux/init.h> | ||
| 33 | #include <linux/proc_fs.h> | ||
| 34 | #include <linux/uaccess.h> | ||
| 35 | |||
| 36 | #include <asm/current.h> | ||
| 37 | #include <asm/system.h> | ||
| 38 | #include <asm/cplb.h> | ||
| 39 | #include <asm/cplbinit.h> | ||
| 40 | #include <asm/blackfin.h> | ||
| 41 | |||
| 42 | static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" }; | ||
| 43 | |||
| 44 | static char *cplb_print_entry(char *buf, struct cplb_entry *tbl, int switched) | ||
| 45 | { | ||
| 46 | int i; | ||
| 47 | buf += sprintf(buf, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n"); | ||
| 48 | for (i = 0; i < MAX_CPLBS; i++) { | ||
| 49 | unsigned long data = tbl[i].data; | ||
| 50 | unsigned long addr = tbl[i].addr; | ||
| 51 | if (!(data & CPLB_VALID)) | ||
| 52 | continue; | ||
| 53 | |||
| 54 | buf += | ||
| 55 | sprintf(buf, | ||
| 56 | "%d\t0x%08lx\t%06lx\t%s\t%c\t%c\t%c\t%c\n", | ||
| 57 | i, addr, data, | ||
| 58 | page_size_string_table[(data & 0x30000) >> 16], | ||
| 59 | (data & CPLB_USER_RD) ? 'Y' : 'N', | ||
| 60 | (data & CPLB_USER_WR) ? 'Y' : 'N', | ||
| 61 | (data & CPLB_SUPV_WR) ? 'Y' : 'N', | ||
| 62 | i < switched ? 'N' : 'Y'); | ||
| 63 | } | ||
| 64 | buf += sprintf(buf, "\n"); | ||
| 65 | |||
| 66 | return buf; | ||
| 67 | } | ||
| 68 | |||
| 69 | int cplbinfo_proc_output(char *buf) | ||
| 70 | { | ||
| 71 | char *p; | ||
| 72 | |||
| 73 | p = buf; | ||
| 74 | |||
| 75 | p += sprintf(p, "------------------ CPLB Information ------------------\n\n"); | ||
| 76 | |||
| 77 | if (bfin_read_IMEM_CONTROL() & ENICPLB) { | ||
| 78 | p += sprintf(p, "Instruction CPLB entry:\n"); | ||
| 79 | p = cplb_print_entry(p, icplb_tbl, first_switched_icplb); | ||
| 80 | } else | ||
| 81 | p += sprintf(p, "Instruction CPLB is disabled.\n\n"); | ||
| 82 | |||
| 83 | if (1 || bfin_read_DMEM_CONTROL() & ENDCPLB) { | ||
| 84 | p += sprintf(p, "Data CPLB entry:\n"); | ||
| 85 | p = cplb_print_entry(p, dcplb_tbl, first_switched_dcplb); | ||
| 86 | } else | ||
| 87 | p += sprintf(p, "Data CPLB is disabled.\n"); | ||
| 88 | |||
| 89 | p += sprintf(p, "ICPLB miss: %d\nICPLB supervisor miss: %d\n", | ||
| 90 | nr_icplb_miss, nr_icplb_supv_miss); | ||
| 91 | p += sprintf(p, "DCPLB miss: %d\nDCPLB protection fault:%d\n", | ||
| 92 | nr_dcplb_miss, nr_dcplb_prot); | ||
| 93 | p += sprintf(p, "CPLB flushes: %d\n", | ||
| 94 | nr_cplb_flush); | ||
| 95 | |||
| 96 | return p - buf; | ||
| 97 | } | ||
| 98 | |||
| 99 | static int cplbinfo_read_proc(char *page, char **start, off_t off, | ||
| 100 | int count, int *eof, void *data) | ||
| 101 | { | ||
| 102 | int len; | ||
| 103 | |||
| 104 | len = cplbinfo_proc_output(page); | ||
| 105 | if (len <= off + count) | ||
| 106 | *eof = 1; | ||
| 107 | *start = page + off; | ||
| 108 | len -= off; | ||
| 109 | if (len > count) | ||
| 110 | len = count; | ||
| 111 | if (len < 0) | ||
| 112 | len = 0; | ||
| 113 | return len; | ||
| 114 | } | ||
| 115 | |||
| 116 | static int __init cplbinfo_init(void) | ||
| 117 | { | ||
| 118 | struct proc_dir_entry *entry; | ||
| 119 | |||
| 120 | entry = create_proc_entry("cplbinfo", 0, NULL); | ||
| 121 | if (!entry) | ||
| 122 | return -ENOMEM; | ||
| 123 | |||
| 124 | entry->read_proc = cplbinfo_read_proc; | ||
| 125 | entry->data = NULL; | ||
| 126 | |||
| 127 | return 0; | ||
| 128 | } | ||
| 129 | |||
| 130 | static void __exit cplbinfo_exit(void) | ||
| 131 | { | ||
| 132 | remove_proc_entry("cplbinfo", NULL); | ||
| 133 | } | ||
| 134 | |||
| 135 | module_init(cplbinfo_init); | ||
| 136 | module_exit(cplbinfo_exit); | ||
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c index 55af729f8495..bdb958486e76 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c | |||
| @@ -25,18 +25,19 @@ | |||
| 25 | #include <asm/blackfin.h> | 25 | #include <asm/blackfin.h> |
| 26 | #include <asm/cplb.h> | 26 | #include <asm/cplb.h> |
| 27 | #include <asm/cplbinit.h> | 27 | #include <asm/cplbinit.h> |
| 28 | #include <asm/mem_map.h> | ||
| 28 | 29 | ||
| 29 | #if ANOMALY_05000263 | 30 | #if ANOMALY_05000263 |
| 30 | # error the MPU will not function safely while Anomaly 05000263 applies | 31 | # error the MPU will not function safely while Anomaly 05000263 applies |
| 31 | #endif | 32 | #endif |
| 32 | 33 | ||
| 33 | struct cplb_entry icplb_tbl[MAX_CPLBS]; | 34 | struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS]; |
| 34 | struct cplb_entry dcplb_tbl[MAX_CPLBS]; | 35 | struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS]; |
| 35 | 36 | ||
| 36 | int first_switched_icplb, first_switched_dcplb; | 37 | int first_switched_icplb, first_switched_dcplb; |
| 37 | int first_mask_dcplb; | 38 | int first_mask_dcplb; |
| 38 | 39 | ||
| 39 | void __init generate_cplb_tables(void) | 40 | void __init generate_cplb_tables_cpu(unsigned int cpu) |
| 40 | { | 41 | { |
| 41 | int i_d, i_i; | 42 | int i_d, i_i; |
| 42 | unsigned long addr; | 43 | unsigned long addr; |
| @@ -55,15 +56,16 @@ void __init generate_cplb_tables(void) | |||
| 55 | d_cache |= CPLB_L1_AOW | CPLB_WT; | 56 | d_cache |= CPLB_L1_AOW | CPLB_WT; |
| 56 | #endif | 57 | #endif |
| 57 | #endif | 58 | #endif |
| 59 | |||
| 58 | i_d = i_i = 0; | 60 | i_d = i_i = 0; |
| 59 | 61 | ||
| 60 | /* Set up the zero page. */ | 62 | /* Set up the zero page. */ |
| 61 | dcplb_tbl[i_d].addr = 0; | 63 | dcplb_tbl[cpu][i_d].addr = 0; |
| 62 | dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; | 64 | dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; |
| 63 | 65 | ||
| 64 | #if 0 | 66 | #if 0 |
| 65 | icplb_tbl[i_i].addr = 0; | 67 | icplb_tbl[cpu][i_i].addr = 0; |
| 66 | icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB; | 68 | icplb_tbl[cpu][i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB; |
| 67 | #endif | 69 | #endif |
| 68 | 70 | ||
| 69 | /* Cover kernel memory with 4M pages. */ | 71 | /* Cover kernel memory with 4M pages. */ |
| @@ -72,28 +74,28 @@ void __init generate_cplb_tables(void) | |||
| 72 | i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB; | 74 | i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB; |
| 73 | 75 | ||
| 74 | for (; addr < memory_start; addr += 4 * 1024 * 1024) { | 76 | for (; addr < memory_start; addr += 4 * 1024 * 1024) { |
| 75 | dcplb_tbl[i_d].addr = addr; | 77 | dcplb_tbl[cpu][i_d].addr = addr; |
| 76 | dcplb_tbl[i_d++].data = d_data; | 78 | dcplb_tbl[cpu][i_d++].data = d_data; |
| 77 | icplb_tbl[i_i].addr = addr; | 79 | icplb_tbl[cpu][i_i].addr = addr; |
| 78 | icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0); | 80 | icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0); |
| 79 | } | 81 | } |
| 80 | 82 | ||
| 81 | /* Cover L1 memory. One 4M area for code and data each is enough. */ | 83 | /* Cover L1 memory. One 4M area for code and data each is enough. */ |
| 82 | #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0 | 84 | #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0 |
| 83 | dcplb_tbl[i_d].addr = L1_DATA_A_START; | 85 | dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu); |
| 84 | dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; | 86 | dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; |
| 85 | #endif | 87 | #endif |
| 86 | #if L1_CODE_LENGTH > 0 | 88 | #if L1_CODE_LENGTH > 0 |
| 87 | icplb_tbl[i_i].addr = L1_CODE_START; | 89 | icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu); |
| 88 | icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; | 90 | icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; |
| 89 | #endif | 91 | #endif |
| 90 | 92 | ||
| 91 | /* Cover L2 memory */ | 93 | /* Cover L2 memory */ |
| 92 | #if L2_LENGTH > 0 | 94 | #if L2_LENGTH > 0 |
| 93 | dcplb_tbl[i_d].addr = L2_START; | 95 | dcplb_tbl[cpu][i_d].addr = L2_START; |
| 94 | dcplb_tbl[i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB; | 96 | dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB; |
| 95 | icplb_tbl[i_i].addr = L2_START; | 97 | icplb_tbl[cpu][i_i].addr = L2_START; |
| 96 | icplb_tbl[i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; | 98 | icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; |
| 97 | #endif | 99 | #endif |
| 98 | 100 | ||
| 99 | first_mask_dcplb = i_d; | 101 | first_mask_dcplb = i_d; |
| @@ -101,7 +103,11 @@ void __init generate_cplb_tables(void) | |||
| 101 | first_switched_icplb = i_i; | 103 | first_switched_icplb = i_i; |
| 102 | 104 | ||
| 103 | while (i_d < MAX_CPLBS) | 105 | while (i_d < MAX_CPLBS) |
| 104 | dcplb_tbl[i_d++].data = 0; | 106 | dcplb_tbl[cpu][i_d++].data = 0; |
| 105 | while (i_i < MAX_CPLBS) | 107 | while (i_i < MAX_CPLBS) |
| 106 | icplb_tbl[i_i++].data = 0; | 108 | icplb_tbl[cpu][i_i++].data = 0; |
| 109 | } | ||
| 110 | |||
| 111 | void generate_cplb_tables_all(void) | ||
| 112 | { | ||
| 107 | } | 113 | } |
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index baa52e261f0d..87463ce87f5a 100644 --- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c | |||
| @@ -25,15 +25,21 @@ | |||
| 25 | #include <asm/cplbinit.h> | 25 | #include <asm/cplbinit.h> |
| 26 | #include <asm/mmu_context.h> | 26 | #include <asm/mmu_context.h> |
| 27 | 27 | ||
| 28 | #define FAULT_RW (1 << 16) | 28 | /* |
| 29 | #define FAULT_USERSUPV (1 << 17) | 29 | * WARNING |
| 30 | * | ||
| 31 | * This file is compiled with certain -ffixed-reg options. We have to | ||
| 32 | * make sure not to call any functions here that could clobber these | ||
| 33 | * registers. | ||
| 34 | */ | ||
| 30 | 35 | ||
| 31 | int page_mask_nelts; | 36 | int page_mask_nelts; |
| 32 | int page_mask_order; | 37 | int page_mask_order; |
| 33 | unsigned long *current_rwx_mask; | 38 | unsigned long *current_rwx_mask[NR_CPUS]; |
| 34 | 39 | ||
| 35 | int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot; | 40 | int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS]; |
| 36 | int nr_cplb_flush; | 41 | int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS]; |
| 42 | int nr_cplb_flush[NR_CPUS]; | ||
| 37 | 43 | ||
| 38 | static inline void disable_dcplb(void) | 44 | static inline void disable_dcplb(void) |
| 39 | { | 45 | { |
| @@ -98,42 +104,42 @@ static inline int write_permitted(int status, unsigned long data) | |||
| 98 | } | 104 | } |
| 99 | 105 | ||
| 100 | /* Counters to implement round-robin replacement. */ | 106 | /* Counters to implement round-robin replacement. */ |
| 101 | static int icplb_rr_index, dcplb_rr_index; | 107 | static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS]; |
| 102 | 108 | ||
| 103 | /* | 109 | /* |
| 104 | * Find an ICPLB entry to be evicted and return its index. | 110 | * Find an ICPLB entry to be evicted and return its index. |
| 105 | */ | 111 | */ |
| 106 | static int evict_one_icplb(void) | 112 | static int evict_one_icplb(unsigned int cpu) |
| 107 | { | 113 | { |
| 108 | int i; | 114 | int i; |
| 109 | for (i = first_switched_icplb; i < MAX_CPLBS; i++) | 115 | for (i = first_switched_icplb; i < MAX_CPLBS; i++) |
| 110 | if ((icplb_tbl[i].data & CPLB_VALID) == 0) | 116 | if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0) |
| 111 | return i; | 117 | return i; |
| 112 | i = first_switched_icplb + icplb_rr_index; | 118 | i = first_switched_icplb + icplb_rr_index[cpu]; |
| 113 | if (i >= MAX_CPLBS) { | 119 | if (i >= MAX_CPLBS) { |
| 114 | i -= MAX_CPLBS - first_switched_icplb; | 120 | i -= MAX_CPLBS - first_switched_icplb; |
| 115 | icplb_rr_index -= MAX_CPLBS - first_switched_icplb; | 121 | icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb; |
| 116 | } | 122 | } |
| 117 | icplb_rr_index++; | 123 | icplb_rr_index[cpu]++; |
| 118 | return i; | 124 | return i; |
| 119 | } | 125 | } |
| 120 | 126 | ||
| 121 | static int evict_one_dcplb(void) | 127 | static int evict_one_dcplb(unsigned int cpu) |
| 122 | { | 128 | { |
| 123 | int i; | 129 | int i; |
| 124 | for (i = first_switched_dcplb; i < MAX_CPLBS; i++) | 130 | for (i = first_switched_dcplb; i < MAX_CPLBS; i++) |
| 125 | if ((dcplb_tbl[i].data & CPLB_VALID) == 0) | 131 | if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0) |
| 126 | return i; | 132 | return i; |
| 127 | i = first_switched_dcplb + dcplb_rr_index; | 133 | i = first_switched_dcplb + dcplb_rr_index[cpu]; |
| 128 | if (i >= MAX_CPLBS) { | 134 | if (i >= MAX_CPLBS) { |
| 129 | i -= MAX_CPLBS - first_switched_dcplb; | 135 | i -= MAX_CPLBS - first_switched_dcplb; |
| 130 | dcplb_rr_index -= MAX_CPLBS - first_switched_dcplb; | 136 | dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb; |
| 131 | } | 137 | } |
| 132 | dcplb_rr_index++; | 138 | dcplb_rr_index[cpu]++; |
| 133 | return i; | 139 | return i; |
| 134 | } | 140 | } |
| 135 | 141 | ||
| 136 | static noinline int dcplb_miss(void) | 142 | static noinline int dcplb_miss(unsigned int cpu) |
| 137 | { | 143 | { |
| 138 | unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); | 144 | unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); |
| 139 | int status = bfin_read_DCPLB_STATUS(); | 145 | int status = bfin_read_DCPLB_STATUS(); |
| @@ -141,7 +147,7 @@ static noinline int dcplb_miss(void) | |||
| 141 | int idx; | 147 | int idx; |
| 142 | unsigned long d_data; | 148 | unsigned long d_data; |
| 143 | 149 | ||
| 144 | nr_dcplb_miss++; | 150 | nr_dcplb_miss[cpu]++; |
| 145 | 151 | ||
| 146 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; | 152 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; |
| 147 | #ifdef CONFIG_BFIN_DCACHE | 153 | #ifdef CONFIG_BFIN_DCACHE |
| @@ -168,25 +174,25 @@ static noinline int dcplb_miss(void) | |||
| 168 | } else if (addr >= _ramend) { | 174 | } else if (addr >= _ramend) { |
| 169 | d_data |= CPLB_USER_RD | CPLB_USER_WR; | 175 | d_data |= CPLB_USER_RD | CPLB_USER_WR; |
| 170 | } else { | 176 | } else { |
| 171 | mask = current_rwx_mask; | 177 | mask = current_rwx_mask[cpu]; |
| 172 | if (mask) { | 178 | if (mask) { |
| 173 | int page = addr >> PAGE_SHIFT; | 179 | int page = addr >> PAGE_SHIFT; |
| 174 | int offs = page >> 5; | 180 | int idx = page >> 5; |
| 175 | int bit = 1 << (page & 31); | 181 | int bit = 1 << (page & 31); |
| 176 | 182 | ||
| 177 | if (mask[offs] & bit) | 183 | if (mask[idx] & bit) |
| 178 | d_data |= CPLB_USER_RD; | 184 | d_data |= CPLB_USER_RD; |
| 179 | 185 | ||
| 180 | mask += page_mask_nelts; | 186 | mask += page_mask_nelts; |
| 181 | if (mask[offs] & bit) | 187 | if (mask[idx] & bit) |
| 182 | d_data |= CPLB_USER_WR; | 188 | d_data |= CPLB_USER_WR; |
| 183 | } | 189 | } |
| 184 | } | 190 | } |
| 185 | idx = evict_one_dcplb(); | 191 | idx = evict_one_dcplb(cpu); |
| 186 | 192 | ||
| 187 | addr &= PAGE_MASK; | 193 | addr &= PAGE_MASK; |
| 188 | dcplb_tbl[idx].addr = addr; | 194 | dcplb_tbl[cpu][idx].addr = addr; |
| 189 | dcplb_tbl[idx].data = d_data; | 195 | dcplb_tbl[cpu][idx].data = d_data; |
| 190 | 196 | ||
| 191 | disable_dcplb(); | 197 | disable_dcplb(); |
| 192 | bfin_write32(DCPLB_DATA0 + idx * 4, d_data); | 198 | bfin_write32(DCPLB_DATA0 + idx * 4, d_data); |
| @@ -196,21 +202,21 @@ static noinline int dcplb_miss(void) | |||
| 196 | return 0; | 202 | return 0; |
| 197 | } | 203 | } |
| 198 | 204 | ||
| 199 | static noinline int icplb_miss(void) | 205 | static noinline int icplb_miss(unsigned int cpu) |
| 200 | { | 206 | { |
| 201 | unsigned long addr = bfin_read_ICPLB_FAULT_ADDR(); | 207 | unsigned long addr = bfin_read_ICPLB_FAULT_ADDR(); |
| 202 | int status = bfin_read_ICPLB_STATUS(); | 208 | int status = bfin_read_ICPLB_STATUS(); |
| 203 | int idx; | 209 | int idx; |
| 204 | unsigned long i_data; | 210 | unsigned long i_data; |
| 205 | 211 | ||
| 206 | nr_icplb_miss++; | 212 | nr_icplb_miss[cpu]++; |
| 207 | 213 | ||
| 208 | /* If inside the uncached DMA region, fault. */ | 214 | /* If inside the uncached DMA region, fault. */ |
| 209 | if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend) | 215 | if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend) |
| 210 | return CPLB_PROT_VIOL; | 216 | return CPLB_PROT_VIOL; |
| 211 | 217 | ||
| 212 | if (status & FAULT_USERSUPV) | 218 | if (status & FAULT_USERSUPV) |
| 213 | nr_icplb_supv_miss++; | 219 | nr_icplb_supv_miss[cpu]++; |
| 214 | 220 | ||
| 215 | /* | 221 | /* |
| 216 | * First, try to find a CPLB that matches this address. If we | 222 | * First, try to find a CPLB that matches this address. If we |
| @@ -218,8 +224,8 @@ static noinline int icplb_miss(void) | |||
| 218 | * that the instruction crosses a page boundary. | 224 | * that the instruction crosses a page boundary. |
| 219 | */ | 225 | */ |
| 220 | for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) { | 226 | for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) { |
| 221 | if (icplb_tbl[idx].data & CPLB_VALID) { | 227 | if (icplb_tbl[cpu][idx].data & CPLB_VALID) { |
| 222 | unsigned long this_addr = icplb_tbl[idx].addr; | 228 | unsigned long this_addr = icplb_tbl[cpu][idx].addr; |
| 223 | if (this_addr <= addr && this_addr + PAGE_SIZE > addr) { | 229 | if (this_addr <= addr && this_addr + PAGE_SIZE > addr) { |
| 224 | addr += PAGE_SIZE; | 230 | addr += PAGE_SIZE; |
| 225 | break; | 231 | break; |
| @@ -257,23 +263,23 @@ static noinline int icplb_miss(void) | |||
| 257 | * Otherwise, check the x bitmap of the current process. | 263 | * Otherwise, check the x bitmap of the current process. |
| 258 | */ | 264 | */ |
| 259 | if (!(status & FAULT_USERSUPV)) { | 265 | if (!(status & FAULT_USERSUPV)) { |
| 260 | unsigned long *mask = current_rwx_mask; | 266 | unsigned long *mask = current_rwx_mask[cpu]; |
| 261 | 267 | ||
| 262 | if (mask) { | 268 | if (mask) { |
| 263 | int page = addr >> PAGE_SHIFT; | 269 | int page = addr >> PAGE_SHIFT; |
| 264 | int offs = page >> 5; | 270 | int idx = page >> 5; |
| 265 | int bit = 1 << (page & 31); | 271 | int bit = 1 << (page & 31); |
| 266 | 272 | ||
| 267 | mask += 2 * page_mask_nelts; | 273 | mask += 2 * page_mask_nelts; |
| 268 | if (mask[offs] & bit) | 274 | if (mask[idx] & bit) |
| 269 | i_data |= CPLB_USER_RD; | 275 | i_data |= CPLB_USER_RD; |
| 270 | } | 276 | } |
| 271 | } | 277 | } |
| 272 | } | 278 | } |
| 273 | idx = evict_one_icplb(); | 279 | idx = evict_one_icplb(cpu); |
| 274 | addr &= PAGE_MASK; | 280 | addr &= PAGE_MASK; |
| 275 | icplb_tbl[idx].addr = addr; | 281 | icplb_tbl[cpu][idx].addr = addr; |
| 276 | icplb_tbl[idx].data = i_data; | 282 | icplb_tbl[cpu][idx].data = i_data; |
| 277 | 283 | ||
| 278 | disable_icplb(); | 284 | disable_icplb(); |
| 279 | bfin_write32(ICPLB_DATA0 + idx * 4, i_data); | 285 | bfin_write32(ICPLB_DATA0 + idx * 4, i_data); |
| @@ -283,19 +289,19 @@ static noinline int icplb_miss(void) | |||
| 283 | return 0; | 289 | return 0; |
| 284 | } | 290 | } |
| 285 | 291 | ||
| 286 | static noinline int dcplb_protection_fault(void) | 292 | static noinline int dcplb_protection_fault(unsigned int cpu) |
| 287 | { | 293 | { |
| 288 | int status = bfin_read_DCPLB_STATUS(); | 294 | int status = bfin_read_DCPLB_STATUS(); |
| 289 | 295 | ||
| 290 | nr_dcplb_prot++; | 296 | nr_dcplb_prot[cpu]++; |
| 291 | 297 | ||
| 292 | if (status & FAULT_RW) { | 298 | if (status & FAULT_RW) { |
| 293 | int idx = faulting_cplb_index(status); | 299 | int idx = faulting_cplb_index(status); |
| 294 | unsigned long data = dcplb_tbl[idx].data; | 300 | unsigned long data = dcplb_tbl[cpu][idx].data; |
| 295 | if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) && | 301 | if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) && |
| 296 | write_permitted(status, data)) { | 302 | write_permitted(status, data)) { |
| 297 | data |= CPLB_DIRTY; | 303 | data |= CPLB_DIRTY; |
| 298 | dcplb_tbl[idx].data = data; | 304 | dcplb_tbl[cpu][idx].data = data; |
| 299 | bfin_write32(DCPLB_DATA0 + idx * 4, data); | 305 | bfin_write32(DCPLB_DATA0 + idx * 4, data); |
| 300 | return 0; | 306 | return 0; |
| 301 | } | 307 | } |
| @@ -306,44 +312,45 @@ static noinline int dcplb_protection_fault(void) | |||
| 306 | int cplb_hdr(int seqstat, struct pt_regs *regs) | 312 | int cplb_hdr(int seqstat, struct pt_regs *regs) |
| 307 | { | 313 | { |
| 308 | int cause = seqstat & 0x3f; | 314 | int cause = seqstat & 0x3f; |
| 315 | unsigned int cpu = smp_processor_id(); | ||
| 309 | switch (cause) { | 316 | switch (cause) { |
| 310 | case 0x23: | 317 | case 0x23: |
| 311 | return dcplb_protection_fault(); | 318 | return dcplb_protection_fault(cpu); |
| 312 | case 0x2C: | 319 | case 0x2C: |
| 313 | return icplb_miss(); | 320 | return icplb_miss(cpu); |
| 314 | case 0x26: | 321 | case 0x26: |
| 315 | return dcplb_miss(); | 322 | return dcplb_miss(cpu); |
| 316 | default: | 323 | default: |
| 317 | return 1; | 324 | return 1; |
| 318 | } | 325 | } |
| 319 | } | 326 | } |
| 320 | 327 | ||
| 321 | void flush_switched_cplbs(void) | 328 | void flush_switched_cplbs(unsigned int cpu) |
| 322 | { | 329 | { |
| 323 | int i; | 330 | int i; |
| 324 | unsigned long flags; | 331 | unsigned long flags; |
| 325 | 332 | ||
| 326 | nr_cplb_flush++; | 333 | nr_cplb_flush[cpu]++; |
| 327 | 334 | ||
| 328 | local_irq_save(flags); | 335 | local_irq_save_hw(flags); |
| 329 | disable_icplb(); | 336 | disable_icplb(); |
| 330 | for (i = first_switched_icplb; i < MAX_CPLBS; i++) { | 337 | for (i = first_switched_icplb; i < MAX_CPLBS; i++) { |
| 331 | icplb_tbl[i].data = 0; | 338 | icplb_tbl[cpu][i].data = 0; |
| 332 | bfin_write32(ICPLB_DATA0 + i * 4, 0); | 339 | bfin_write32(ICPLB_DATA0 + i * 4, 0); |
| 333 | } | 340 | } |
| 334 | enable_icplb(); | 341 | enable_icplb(); |
| 335 | 342 | ||
| 336 | disable_dcplb(); | 343 | disable_dcplb(); |
| 337 | for (i = first_switched_dcplb; i < MAX_CPLBS; i++) { | 344 | for (i = first_switched_dcplb; i < MAX_CPLBS; i++) { |
| 338 | dcplb_tbl[i].data = 0; | 345 | dcplb_tbl[cpu][i].data = 0; |
| 339 | bfin_write32(DCPLB_DATA0 + i * 4, 0); | 346 | bfin_write32(DCPLB_DATA0 + i * 4, 0); |
| 340 | } | 347 | } |
| 341 | enable_dcplb(); | 348 | enable_dcplb(); |
| 342 | local_irq_restore(flags); | 349 | local_irq_restore_hw(flags); |
| 343 | 350 | ||
| 344 | } | 351 | } |
| 345 | 352 | ||
| 346 | void set_mask_dcplbs(unsigned long *masks) | 353 | void set_mask_dcplbs(unsigned long *masks, unsigned int cpu) |
| 347 | { | 354 | { |
| 348 | int i; | 355 | int i; |
| 349 | unsigned long addr = (unsigned long)masks; | 356 | unsigned long addr = (unsigned long)masks; |
| @@ -351,12 +358,12 @@ void set_mask_dcplbs(unsigned long *masks) | |||
| 351 | unsigned long flags; | 358 | unsigned long flags; |
| 352 | 359 | ||
| 353 | if (!masks) { | 360 | if (!masks) { |
| 354 | current_rwx_mask = masks; | 361 | current_rwx_mask[cpu] = masks; |
| 355 | return; | 362 | return; |
| 356 | } | 363 | } |
| 357 | 364 | ||
| 358 | local_irq_save(flags); | 365 | local_irq_save_hw(flags); |
| 359 | current_rwx_mask = masks; | 366 | current_rwx_mask[cpu] = masks; |
| 360 | 367 | ||
| 361 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; | 368 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; |
| 362 | #ifdef CONFIG_BFIN_DCACHE | 369 | #ifdef CONFIG_BFIN_DCACHE |
| @@ -368,12 +375,12 @@ void set_mask_dcplbs(unsigned long *masks) | |||
| 368 | 375 | ||
| 369 | disable_dcplb(); | 376 | disable_dcplb(); |
| 370 | for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { | 377 | for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { |
| 371 | dcplb_tbl[i].addr = addr; | 378 | dcplb_tbl[cpu][i].addr = addr; |
| 372 | dcplb_tbl[i].data = d_data; | 379 | dcplb_tbl[cpu][i].data = d_data; |
| 373 | bfin_write32(DCPLB_DATA0 + i * 4, d_data); | 380 | bfin_write32(DCPLB_DATA0 + i * 4, d_data); |
| 374 | bfin_write32(DCPLB_ADDR0 + i * 4, addr); | 381 | bfin_write32(DCPLB_ADDR0 + i * 4, addr); |
| 375 | addr += PAGE_SIZE; | 382 | addr += PAGE_SIZE; |
| 376 | } | 383 | } |
| 377 | enable_dcplb(); | 384 | enable_dcplb(); |
| 378 | local_irq_restore(flags); | 385 | local_irq_restore_hw(flags); |
| 379 | } | 386 | } |
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile index d36ea9b5382e..7d70d3bf3212 100644 --- a/arch/blackfin/kernel/cplb-nompu/Makefile +++ b/arch/blackfin/kernel/cplb-nompu/Makefile | |||
| @@ -2,7 +2,9 @@ | |||
| 2 | # arch/blackfin/kernel/cplb-nompu/Makefile | 2 | # arch/blackfin/kernel/cplb-nompu/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y := cplbinit.o cacheinit.o cplbhdlr.o cplbmgr.o | 5 | obj-y := cplbinit.o cacheinit.o cplbmgr.o |
| 6 | |||
| 7 | obj-$(CONFIG_CPLB_INFO) += cplbinfo.o | ||
| 8 | 6 | ||
| 7 | CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \ | ||
| 8 | -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \ | ||
| 9 | -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \ | ||
| 10 | -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3 | ||
diff --git a/arch/blackfin/kernel/cplb-nompu/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c index bd0831592c2c..c6ff947f9d37 100644 --- a/arch/blackfin/kernel/cplb-nompu/cacheinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c | |||
| @@ -25,19 +25,15 @@ | |||
| 25 | #include <asm/cplbinit.h> | 25 | #include <asm/cplbinit.h> |
| 26 | 26 | ||
| 27 | #if defined(CONFIG_BFIN_ICACHE) | 27 | #if defined(CONFIG_BFIN_ICACHE) |
| 28 | void __init bfin_icache_init(void) | 28 | void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl) |
| 29 | { | 29 | { |
| 30 | unsigned long *table = icplb_table; | ||
| 31 | unsigned long ctrl; | 30 | unsigned long ctrl; |
| 32 | int i; | 31 | int i; |
| 33 | 32 | ||
| 33 | SSYNC(); | ||
| 34 | for (i = 0; i < MAX_CPLBS; i++) { | 34 | for (i = 0; i < MAX_CPLBS; i++) { |
| 35 | unsigned long addr = *table++; | 35 | bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr); |
| 36 | unsigned long data = *table++; | 36 | bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data); |
| 37 | if (addr == (unsigned long)-1) | ||
| 38 | break; | ||
| 39 | bfin_write32(ICPLB_ADDR0 + i * 4, addr); | ||
| 40 | bfin_write32(ICPLB_DATA0 + i * 4, data); | ||
| 41 | } | 37 | } |
| 42 | ctrl = bfin_read_IMEM_CONTROL(); | 38 | ctrl = bfin_read_IMEM_CONTROL(); |
| 43 | ctrl |= IMC | ENICPLB; | 39 | ctrl |= IMC | ENICPLB; |
| @@ -47,20 +43,17 @@ void __init bfin_icache_init(void) | |||
| 47 | #endif | 43 | #endif |
| 48 | 44 | ||
| 49 | #if defined(CONFIG_BFIN_DCACHE) | 45 | #if defined(CONFIG_BFIN_DCACHE) |
| 50 | void __init bfin_dcache_init(void) | 46 | void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) |
| 51 | { | 47 | { |
| 52 | unsigned long *table = dcplb_table; | ||
| 53 | unsigned long ctrl; | 48 | unsigned long ctrl; |
| 54 | int i; | 49 | int i; |
| 55 | 50 | ||
| 51 | SSYNC(); | ||
| 56 | for (i = 0; i < MAX_CPLBS; i++) { | 52 | for (i = 0; i < MAX_CPLBS; i++) { |
| 57 | unsigned long addr = *table++; | 53 | bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr); |
| 58 | unsigned long data = *table++; | 54 | bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data); |
| 59 | if (addr == (unsigned long)-1) | ||
| 60 | break; | ||
| 61 | bfin_write32(DCPLB_ADDR0 + i * 4, addr); | ||
| 62 | bfin_write32(DCPLB_DATA0 + i * 4, data); | ||
| 63 | } | 55 | } |
| 56 | |||
| 64 | ctrl = bfin_read_DMEM_CONTROL(); | 57 | ctrl = bfin_read_DMEM_CONTROL(); |
| 65 | ctrl |= DMEM_CNTR; | 58 | ctrl |= DMEM_CNTR; |
| 66 | bfin_write_DMEM_CONTROL(ctrl); | 59 | bfin_write_DMEM_CONTROL(ctrl); |
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S deleted file mode 100644 index ecbabc0a1fed..000000000000 --- a/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S +++ /dev/null | |||
| @@ -1,130 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-common/cplbhdlr.S | ||
| 3 | * Based on: | ||
| 4 | * Author: LG Soft India | ||
| 5 | * | ||
| 6 | * Created: ? | ||
| 7 | * Description: CPLB exception handler | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/linkage.h> | ||
| 31 | #include <asm/cplb.h> | ||
| 32 | #include <asm/entry.h> | ||
| 33 | |||
| 34 | #ifdef CONFIG_EXCPT_IRQ_SYSC_L1 | ||
| 35 | .section .l1.text | ||
| 36 | #else | ||
| 37 | .text | ||
| 38 | #endif | ||
| 39 | |||
| 40 | .type _cplb_mgr, STT_FUNC; | ||
| 41 | .type _panic_cplb_error, STT_FUNC; | ||
| 42 | |||
| 43 | .align 2 | ||
| 44 | |||
| 45 | ENTRY(__cplb_hdr) | ||
| 46 | R2 = SEQSTAT; | ||
| 47 | |||
| 48 | /* Mask the contents of SEQSTAT and leave only EXCAUSE in R2 */ | ||
| 49 | R2 <<= 26; | ||
| 50 | R2 >>= 26; | ||
| 51 | |||
| 52 | R1 = 0x23; /* Data access CPLB protection violation */ | ||
| 53 | CC = R2 == R1; | ||
| 54 | IF !CC JUMP .Lnot_data_write; | ||
| 55 | R0 = 2; /* is a write to data space*/ | ||
| 56 | JUMP .Lis_icplb_miss; | ||
| 57 | |||
| 58 | .Lnot_data_write: | ||
| 59 | R1 = 0x2C; /* CPLB miss on an instruction fetch */ | ||
| 60 | CC = R2 == R1; | ||
| 61 | R0 = 0; /* is_data_miss == False*/ | ||
| 62 | IF CC JUMP .Lis_icplb_miss; | ||
| 63 | |||
| 64 | R1 = 0x26; | ||
| 65 | CC = R2 == R1; | ||
| 66 | IF !CC JUMP .Lunknown; | ||
| 67 | |||
| 68 | R0 = 1; /* is_data_miss == True*/ | ||
| 69 | |||
| 70 | .Lis_icplb_miss: | ||
| 71 | |||
| 72 | #if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE) | ||
| 73 | # if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE) | ||
| 74 | R1 = CPLB_ENABLE_ICACHE; | ||
| 75 | # endif | ||
| 76 | # if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE) | ||
| 77 | R1 = CPLB_ENABLE_DCACHE; | ||
| 78 | # endif | ||
| 79 | # if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE) | ||
| 80 | R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; | ||
| 81 | # endif | ||
| 82 | #else | ||
| 83 | R1 = 0; | ||
| 84 | #endif | ||
| 85 | |||
| 86 | [--SP] = RETS; | ||
| 87 | CALL _cplb_mgr; | ||
| 88 | RETS = [SP++]; | ||
| 89 | CC = R0 == 0; | ||
| 90 | IF !CC JUMP .Lnot_replaced; | ||
| 91 | RTS; | ||
| 92 | |||
| 93 | /* | ||
| 94 | * Diagnostic exception handlers | ||
| 95 | */ | ||
| 96 | .Lunknown: | ||
| 97 | R0 = CPLB_UNKNOWN_ERR; | ||
| 98 | JUMP .Lcplb_error; | ||
| 99 | |||
| 100 | .Lnot_replaced: | ||
| 101 | CC = R0 == CPLB_NO_UNLOCKED; | ||
| 102 | IF !CC JUMP .Lnext_check; | ||
| 103 | R0 = CPLB_NO_UNLOCKED; | ||
| 104 | JUMP .Lcplb_error; | ||
| 105 | |||
| 106 | .Lnext_check: | ||
| 107 | CC = R0 == CPLB_NO_ADDR_MATCH; | ||
| 108 | IF !CC JUMP .Lnext_check2; | ||
| 109 | R0 = CPLB_NO_ADDR_MATCH; | ||
| 110 | JUMP .Lcplb_error; | ||
| 111 | |||
| 112 | .Lnext_check2: | ||
| 113 | CC = R0 == CPLB_PROT_VIOL; | ||
| 114 | IF !CC JUMP .Lstrange_return_from_cplb_mgr; | ||
| 115 | R0 = CPLB_PROT_VIOL; | ||
| 116 | JUMP .Lcplb_error; | ||
| 117 | |||
| 118 | .Lstrange_return_from_cplb_mgr: | ||
| 119 | IDLE; | ||
| 120 | CSYNC; | ||
| 121 | JUMP .Lstrange_return_from_cplb_mgr; | ||
| 122 | |||
| 123 | .Lcplb_error: | ||
| 124 | R1 = sp; | ||
| 125 | SP += -12; | ||
| 126 | call _panic_cplb_error; | ||
| 127 | SP += 12; | ||
| 128 | JUMP.L _handle_bad_cplb; | ||
| 129 | |||
| 130 | ENDPROC(__cplb_hdr) | ||
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c deleted file mode 100644 index 1e74f0b97996..000000000000 --- a/arch/blackfin/kernel/cplb-nompu/cplbinfo.c +++ /dev/null | |||
| @@ -1,195 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-common/cplbinfo.c | ||
| 3 | * Based on: | ||
| 4 | * Author: Sonic Zhang <sonic.zhang@analog.com> | ||
| 5 | * | ||
| 6 | * Created: Jan. 2005 | ||
| 7 | * Description: Display CPLB status | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/module.h> | ||
| 31 | #include <linux/kernel.h> | ||
| 32 | #include <linux/init.h> | ||
| 33 | #include <linux/proc_fs.h> | ||
| 34 | #include <linux/uaccess.h> | ||
| 35 | |||
| 36 | #include <asm/cplbinit.h> | ||
| 37 | #include <asm/blackfin.h> | ||
| 38 | |||
| 39 | #define CPLB_I 1 | ||
| 40 | #define CPLB_D 2 | ||
| 41 | |||
| 42 | #define SYNC_SYS SSYNC() | ||
| 43 | #define SYNC_CORE CSYNC() | ||
| 44 | |||
| 45 | #define CPLB_BIT_PAGESIZE 0x30000 | ||
| 46 | |||
| 47 | static int page_size_table[4] = { | ||
| 48 | 0x00000400, /* 1K */ | ||
| 49 | 0x00001000, /* 4K */ | ||
| 50 | 0x00100000, /* 1M */ | ||
| 51 | 0x00400000 /* 4M */ | ||
| 52 | }; | ||
| 53 | |||
| 54 | static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" }; | ||
| 55 | |||
| 56 | static int cplb_find_entry(unsigned long *cplb_addr, | ||
| 57 | unsigned long *cplb_data, unsigned long addr, | ||
| 58 | unsigned long data) | ||
| 59 | { | ||
| 60 | int ii; | ||
| 61 | |||
| 62 | for (ii = 0; ii < 16; ii++) | ||
| 63 | if (addr >= cplb_addr[ii] && addr < cplb_addr[ii] + | ||
| 64 | page_size_table[(cplb_data[ii] & CPLB_BIT_PAGESIZE) >> 16] | ||
| 65 | && (cplb_data[ii] == data)) | ||
| 66 | return ii; | ||
| 67 | |||
| 68 | return -1; | ||
| 69 | } | ||
| 70 | |||
| 71 | static char *cplb_print_entry(char *buf, int type) | ||
| 72 | { | ||
| 73 | unsigned long *p_addr = dpdt_table; | ||
| 74 | unsigned long *p_data = dpdt_table + 1; | ||
| 75 | unsigned long *p_icount = dpdt_swapcount_table; | ||
| 76 | unsigned long *p_ocount = dpdt_swapcount_table + 1; | ||
| 77 | unsigned long *cplb_addr = (unsigned long *)DCPLB_ADDR0; | ||
| 78 | unsigned long *cplb_data = (unsigned long *)DCPLB_DATA0; | ||
| 79 | int entry = 0, used_cplb = 0; | ||
| 80 | |||
| 81 | if (type == CPLB_I) { | ||
| 82 | buf += sprintf(buf, "Instruction CPLB entry:\n"); | ||
| 83 | p_addr = ipdt_table; | ||
| 84 | p_data = ipdt_table + 1; | ||
| 85 | p_icount = ipdt_swapcount_table; | ||
| 86 | p_ocount = ipdt_swapcount_table + 1; | ||
| 87 | cplb_addr = (unsigned long *)ICPLB_ADDR0; | ||
| 88 | cplb_data = (unsigned long *)ICPLB_DATA0; | ||
| 89 | } else | ||
| 90 | buf += sprintf(buf, "Data CPLB entry:\n"); | ||
| 91 | |||
| 92 | buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\tiCount\toCount\n"); | ||
| 93 | |||
| 94 | while (*p_addr != 0xffffffff) { | ||
| 95 | entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data); | ||
| 96 | if (entry >= 0) | ||
| 97 | used_cplb |= 1 << entry; | ||
| 98 | |||
| 99 | buf += | ||
| 100 | sprintf(buf, | ||
| 101 | "0x%08lx\t0x%05lx\t%s\t%c\t%c\t%2d\t%ld\t%ld\n", | ||
| 102 | *p_addr, *p_data, | ||
| 103 | page_size_string_table[(*p_data & 0x30000) >> 16], | ||
| 104 | (*p_data & CPLB_VALID) ? 'Y' : 'N', | ||
| 105 | (*p_data & CPLB_LOCK) ? 'Y' : 'N', entry, *p_icount, | ||
| 106 | *p_ocount); | ||
| 107 | |||
| 108 | p_addr += 2; | ||
| 109 | p_data += 2; | ||
| 110 | p_icount += 2; | ||
| 111 | p_ocount += 2; | ||
| 112 | } | ||
| 113 | |||
| 114 | if (used_cplb != 0xffff) { | ||
| 115 | buf += sprintf(buf, "Unused/mismatched CPLBs:\n"); | ||
| 116 | |||
| 117 | for (entry = 0; entry < 16; entry++) | ||
| 118 | if (0 == ((1 << entry) & used_cplb)) { | ||
| 119 | int flags = cplb_data[entry]; | ||
| 120 | buf += | ||
| 121 | sprintf(buf, | ||
| 122 | "%2d: 0x%08lx\t0x%05x\t%s\t%c\t%c\n", | ||
| 123 | entry, cplb_addr[entry], flags, | ||
| 124 | page_size_string_table[(flags & | ||
| 125 | 0x30000) >> | ||
| 126 | 16], | ||
| 127 | (flags & CPLB_VALID) ? 'Y' : 'N', | ||
| 128 | (flags & CPLB_LOCK) ? 'Y' : 'N'); | ||
| 129 | } | ||
| 130 | } | ||
| 131 | |||
| 132 | buf += sprintf(buf, "\n"); | ||
| 133 | |||
| 134 | return buf; | ||
| 135 | } | ||
| 136 | |||
| 137 | static int cplbinfo_proc_output(char *buf) | ||
| 138 | { | ||
| 139 | char *p; | ||
| 140 | |||
| 141 | p = buf; | ||
| 142 | |||
| 143 | p += sprintf(p, "------------------ CPLB Information ------------------\n\n"); | ||
| 144 | |||
| 145 | if (bfin_read_IMEM_CONTROL() & ENICPLB) | ||
| 146 | p = cplb_print_entry(p, CPLB_I); | ||
| 147 | else | ||
| 148 | p += sprintf(p, "Instruction CPLB is disabled.\n\n"); | ||
| 149 | |||
| 150 | if (bfin_read_DMEM_CONTROL() & ENDCPLB) | ||
| 151 | p = cplb_print_entry(p, CPLB_D); | ||
| 152 | else | ||
| 153 | p += sprintf(p, "Data CPLB is disabled.\n"); | ||
| 154 | |||
| 155 | return p - buf; | ||
| 156 | } | ||
| 157 | |||
| 158 | static int cplbinfo_read_proc(char *page, char **start, off_t off, | ||
| 159 | int count, int *eof, void *data) | ||
| 160 | { | ||
| 161 | int len; | ||
| 162 | |||
| 163 | len = cplbinfo_proc_output(page); | ||
| 164 | if (len <= off + count) | ||
| 165 | *eof = 1; | ||
| 166 | *start = page + off; | ||
| 167 | len -= off; | ||
| 168 | if (len > count) | ||
| 169 | len = count; | ||
| 170 | if (len < 0) | ||
| 171 | len = 0; | ||
| 172 | return len; | ||
| 173 | } | ||
| 174 | |||
| 175 | static int __init cplbinfo_init(void) | ||
| 176 | { | ||
| 177 | struct proc_dir_entry *entry; | ||
| 178 | |||
| 179 | entry = create_proc_entry("cplbinfo", 0, NULL); | ||
| 180 | if (!entry) | ||
| 181 | return -ENOMEM; | ||
| 182 | |||
| 183 | entry->read_proc = cplbinfo_read_proc; | ||
| 184 | entry->data = NULL; | ||
| 185 | |||
| 186 | return 0; | ||
| 187 | } | ||
| 188 | |||
| 189 | static void __exit cplbinfo_exit(void) | ||
| 190 | { | ||
| 191 | remove_proc_entry("cplbinfo", NULL); | ||
| 192 | } | ||
| 193 | |||
| 194 | module_init(cplbinfo_init); | ||
| 195 | module_exit(cplbinfo_exit); | ||
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 2debc900e246..0e28f7595733 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c | |||
| @@ -20,445 +20,152 @@ | |||
| 20 | * to the Free Software Foundation, Inc., | 20 | * to the Free Software Foundation, Inc., |
| 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 22 | */ | 22 | */ |
| 23 | |||
| 23 | #include <linux/module.h> | 24 | #include <linux/module.h> |
| 24 | 25 | ||
| 25 | #include <asm/blackfin.h> | 26 | #include <asm/blackfin.h> |
| 26 | #include <asm/cacheflush.h> | 27 | #include <asm/cacheflush.h> |
| 27 | #include <asm/cplb.h> | 28 | #include <asm/cplb.h> |
| 28 | #include <asm/cplbinit.h> | 29 | #include <asm/cplbinit.h> |
| 30 | #include <asm/mem_map.h> | ||
| 29 | 31 | ||
| 30 | #define CPLB_MEM CONFIG_MAX_MEM_SIZE | 32 | struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR; |
| 31 | 33 | struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR; | |
| 32 | /* | ||
| 33 | * Number of required data CPLB switchtable entries | ||
| 34 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | ||
| 35 | * approx 16 for smaller 1MB page size CPLBs for allignment purposes | ||
| 36 | * 1 for L1 Data Memory | ||
| 37 | * possibly 1 for L2 Data Memory | ||
| 38 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | ||
| 39 | * 1 for ASYNC Memory | ||
| 40 | */ | ||
| 41 | #define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \ | ||
| 42 | + ASYNC_MEMORY_CPLB_COVERAGE) * 2) | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Number of required instruction CPLB switchtable entries | ||
| 46 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | ||
| 47 | * approx 12 for smaller 1MB page size CPLBs for allignment purposes | ||
| 48 | * 1 for L1 Instruction Memory | ||
| 49 | * possibly 1 for L2 Instruction Memory | ||
| 50 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | ||
| 51 | */ | ||
| 52 | #define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2) | ||
| 53 | |||
| 54 | |||
| 55 | u_long icplb_table[MAX_CPLBS + 1]; | ||
| 56 | u_long dcplb_table[MAX_CPLBS + 1]; | ||
| 57 | |||
| 58 | #ifdef CONFIG_CPLB_SWITCH_TAB_L1 | ||
| 59 | # define PDT_ATTR __attribute__((l1_data)) | ||
| 60 | #else | ||
| 61 | # define PDT_ATTR | ||
| 62 | #endif | ||
| 63 | |||
| 64 | u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR; | ||
| 65 | u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR; | ||
| 66 | 34 | ||
| 67 | #ifdef CONFIG_CPLB_INFO | 35 | int first_switched_icplb PDT_ATTR; |
| 68 | u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR; | 36 | int first_switched_dcplb PDT_ATTR; |
| 69 | u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR; | ||
| 70 | #endif | ||
| 71 | 37 | ||
| 72 | struct s_cplb { | 38 | struct cplb_boundary dcplb_bounds[9] PDT_ATTR; |
| 73 | struct cplb_tab init_i; | 39 | struct cplb_boundary icplb_bounds[7] PDT_ATTR; |
| 74 | struct cplb_tab init_d; | ||
| 75 | struct cplb_tab switch_i; | ||
| 76 | struct cplb_tab switch_d; | ||
| 77 | }; | ||
| 78 | 40 | ||
| 79 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) | 41 | int icplb_nr_bounds PDT_ATTR; |
| 80 | static struct cplb_desc cplb_data[] = { | 42 | int dcplb_nr_bounds PDT_ATTR; |
| 81 | { | ||
| 82 | .start = 0, | ||
| 83 | .end = SIZE_1K, | ||
| 84 | .psize = SIZE_1K, | ||
| 85 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, | ||
| 86 | .i_conf = SDRAM_OOPS, | ||
| 87 | .d_conf = SDRAM_OOPS, | ||
| 88 | #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) | ||
| 89 | .valid = 1, | ||
| 90 | #else | ||
| 91 | .valid = 0, | ||
| 92 | #endif | ||
| 93 | .name = "Zero Pointer Guard Page", | ||
| 94 | }, | ||
| 95 | { | ||
| 96 | .start = L1_CODE_START, | ||
| 97 | .end = L1_CODE_START + L1_CODE_LENGTH, | ||
| 98 | .psize = SIZE_4M, | ||
| 99 | .attr = INITIAL_T | SWITCH_T | I_CPLB, | ||
| 100 | .i_conf = L1_IMEMORY, | ||
| 101 | .d_conf = 0, | ||
| 102 | .valid = 1, | ||
| 103 | .name = "L1 I-Memory", | ||
| 104 | }, | ||
| 105 | { | ||
| 106 | .start = L1_DATA_A_START, | ||
| 107 | .end = L1_DATA_B_START + L1_DATA_B_LENGTH, | ||
| 108 | .psize = SIZE_4M, | ||
| 109 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | ||
| 110 | .i_conf = 0, | ||
| 111 | .d_conf = L1_DMEMORY, | ||
| 112 | #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) | ||
| 113 | .valid = 1, | ||
| 114 | #else | ||
| 115 | .valid = 0, | ||
| 116 | #endif | ||
| 117 | .name = "L1 D-Memory", | ||
| 118 | }, | ||
| 119 | { | ||
| 120 | .start = 0, | ||
| 121 | .end = 0, /* dynamic */ | ||
| 122 | .psize = 0, | ||
| 123 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, | ||
| 124 | .i_conf = SDRAM_IGENERIC, | ||
| 125 | .d_conf = SDRAM_DGENERIC, | ||
| 126 | .valid = 1, | ||
| 127 | .name = "Kernel Memory", | ||
| 128 | }, | ||
| 129 | { | ||
| 130 | .start = 0, /* dynamic */ | ||
| 131 | .end = 0, /* dynamic */ | ||
| 132 | .psize = 0, | ||
| 133 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | ||
| 134 | .i_conf = SDRAM_IGENERIC, | ||
| 135 | .d_conf = SDRAM_DNON_CHBL, | ||
| 136 | .valid = 1, | ||
| 137 | .name = "uClinux MTD Memory", | ||
| 138 | }, | ||
| 139 | { | ||
| 140 | .start = 0, /* dynamic */ | ||
| 141 | .end = 0, /* dynamic */ | ||
| 142 | .psize = SIZE_1M, | ||
| 143 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | ||
| 144 | .d_conf = SDRAM_DNON_CHBL, | ||
| 145 | .valid = 1, | ||
| 146 | .name = "Uncached DMA Zone", | ||
| 147 | }, | ||
| 148 | { | ||
| 149 | .start = 0, /* dynamic */ | ||
| 150 | .end = 0, /* dynamic */ | ||
| 151 | .psize = 0, | ||
| 152 | .attr = SWITCH_T | D_CPLB, | ||
| 153 | .i_conf = 0, /* dynamic */ | ||
| 154 | .d_conf = 0, /* dynamic */ | ||
| 155 | .valid = 1, | ||
| 156 | .name = "Reserved Memory", | ||
| 157 | }, | ||
| 158 | { | ||
| 159 | .start = ASYNC_BANK0_BASE, | ||
| 160 | .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, | ||
| 161 | .psize = 0, | ||
| 162 | .attr = SWITCH_T | D_CPLB, | ||
| 163 | .d_conf = SDRAM_EBIU, | ||
| 164 | .valid = 1, | ||
| 165 | .name = "Asynchronous Memory Banks", | ||
| 166 | }, | ||
| 167 | { | ||
| 168 | .start = L2_START, | ||
| 169 | .end = L2_START + L2_LENGTH, | ||
| 170 | .psize = SIZE_1M, | ||
| 171 | .attr = SWITCH_T | I_CPLB | D_CPLB, | ||
| 172 | .i_conf = L2_IMEMORY, | ||
| 173 | .d_conf = L2_DMEMORY, | ||
| 174 | .valid = (L2_LENGTH > 0), | ||
| 175 | .name = "L2 Memory", | ||
| 176 | }, | ||
| 177 | { | ||
| 178 | .start = BOOT_ROM_START, | ||
| 179 | .end = BOOT_ROM_START + BOOT_ROM_LENGTH, | ||
| 180 | .psize = SIZE_1M, | ||
| 181 | .attr = SWITCH_T | I_CPLB | D_CPLB, | ||
| 182 | .i_conf = SDRAM_IGENERIC, | ||
| 183 | .d_conf = SDRAM_DGENERIC, | ||
| 184 | .valid = 1, | ||
| 185 | .name = "On-Chip BootROM", | ||
| 186 | }, | ||
| 187 | }; | ||
| 188 | 43 | ||
| 189 | static u16 __init lock_kernel_check(u32 start, u32 end) | 44 | void __init generate_cplb_tables_cpu(unsigned int cpu) |
| 190 | { | 45 | { |
| 191 | if (start >= (u32)_end || end <= (u32)_stext) | 46 | int i_d, i_i; |
| 192 | return 0; | 47 | unsigned long addr; |
| 193 | 48 | ||
| 194 | /* This cplb block overlapped with kernel area. */ | 49 | struct cplb_entry *d_tbl = dcplb_tbl[cpu]; |
| 195 | return IN_KERNEL; | 50 | struct cplb_entry *i_tbl = icplb_tbl[cpu]; |
| 196 | } | ||
| 197 | 51 | ||
| 198 | static unsigned short __init | 52 | printk(KERN_INFO "NOMPU: setting up cplb tables\n"); |
| 199 | fill_cplbtab(struct cplb_tab *table, | ||
| 200 | unsigned long start, unsigned long end, | ||
| 201 | unsigned long block_size, unsigned long cplb_data) | ||
| 202 | { | ||
| 203 | int i; | ||
| 204 | 53 | ||
| 205 | switch (block_size) { | 54 | i_d = i_i = 0; |
| 206 | case SIZE_4M: | ||
| 207 | i = 3; | ||
| 208 | break; | ||
| 209 | case SIZE_1M: | ||
| 210 | i = 2; | ||
| 211 | break; | ||
| 212 | case SIZE_4K: | ||
| 213 | i = 1; | ||
| 214 | break; | ||
| 215 | case SIZE_1K: | ||
| 216 | default: | ||
| 217 | i = 0; | ||
| 218 | break; | ||
| 219 | } | ||
| 220 | |||
| 221 | cplb_data = (cplb_data & ~(3 << 16)) | (i << 16); | ||
| 222 | |||
| 223 | while ((start < end) && (table->pos < table->size)) { | ||
| 224 | 55 | ||
| 225 | table->tab[table->pos++] = start; | 56 | /* Set up the zero page. */ |
| 57 | d_tbl[i_d].addr = 0; | ||
| 58 | d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; | ||
| 226 | 59 | ||
| 227 | if (lock_kernel_check(start, start + block_size) == IN_KERNEL) | 60 | /* Cover kernel memory with 4M pages. */ |
| 228 | table->tab[table->pos++] = | 61 | addr = 0; |
| 229 | cplb_data | CPLB_LOCK | CPLB_DIRTY; | ||
| 230 | else | ||
| 231 | table->tab[table->pos++] = cplb_data; | ||
| 232 | 62 | ||
| 233 | start += block_size; | 63 | for (; addr < memory_start; addr += 4 * 1024 * 1024) { |
| 64 | d_tbl[i_d].addr = addr; | ||
| 65 | d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; | ||
| 66 | i_tbl[i_i].addr = addr; | ||
| 67 | i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; | ||
| 234 | } | 68 | } |
| 235 | return 0; | ||
| 236 | } | ||
| 237 | 69 | ||
| 238 | static unsigned short __init | 70 | /* Cover L1 memory. One 4M area for code and data each is enough. */ |
| 239 | close_cplbtab(struct cplb_tab *table) | 71 | if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { |
| 240 | { | 72 | d_tbl[i_d].addr = L1_DATA_A_START; |
| 241 | 73 | d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; | |
| 242 | while (table->pos < table->size) { | ||
| 243 | |||
| 244 | table->tab[table->pos++] = 0; | ||
| 245 | table->tab[table->pos++] = 0; /* !CPLB_VALID */ | ||
| 246 | } | 74 | } |
| 247 | return 0; | 75 | i_tbl[i_i].addr = L1_CODE_START; |
| 248 | } | 76 | i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; |
| 249 | 77 | ||
| 250 | /* helper function */ | 78 | first_switched_dcplb = i_d; |
| 251 | static void __init | 79 | first_switched_icplb = i_i; |
| 252 | __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) | ||
| 253 | { | ||
| 254 | if (cplb_data[i].psize) { | ||
| 255 | fill_cplbtab(t, | ||
| 256 | cplb_data[i].start, | ||
| 257 | cplb_data[i].end, | ||
| 258 | cplb_data[i].psize, | ||
| 259 | cplb_data[i].i_conf); | ||
| 260 | } else { | ||
| 261 | #if defined(CONFIG_BFIN_ICACHE) | ||
| 262 | if (ANOMALY_05000263 && i == SDRAM_KERN) { | ||
| 263 | fill_cplbtab(t, | ||
| 264 | cplb_data[i].start, | ||
| 265 | cplb_data[i].end, | ||
| 266 | SIZE_4M, | ||
| 267 | cplb_data[i].i_conf); | ||
| 268 | } else | ||
| 269 | #endif | ||
| 270 | { | ||
| 271 | fill_cplbtab(t, | ||
| 272 | cplb_data[i].start, | ||
| 273 | a_start, | ||
| 274 | SIZE_1M, | ||
| 275 | cplb_data[i].i_conf); | ||
| 276 | fill_cplbtab(t, | ||
| 277 | a_start, | ||
| 278 | a_end, | ||
| 279 | SIZE_4M, | ||
| 280 | cplb_data[i].i_conf); | ||
| 281 | fill_cplbtab(t, a_end, | ||
| 282 | cplb_data[i].end, | ||
| 283 | SIZE_1M, | ||
| 284 | cplb_data[i].i_conf); | ||
| 285 | } | ||
| 286 | } | ||
| 287 | } | ||
| 288 | 80 | ||
| 289 | static void __init | 81 | BUG_ON(first_switched_dcplb > MAX_CPLBS); |
| 290 | __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) | 82 | BUG_ON(first_switched_icplb > MAX_CPLBS); |
| 291 | { | 83 | |
| 292 | if (cplb_data[i].psize) { | 84 | while (i_d < MAX_CPLBS) |
| 293 | fill_cplbtab(t, | 85 | d_tbl[i_d++].data = 0; |
| 294 | cplb_data[i].start, | 86 | while (i_i < MAX_CPLBS) |
| 295 | cplb_data[i].end, | 87 | i_tbl[i_i++].data = 0; |
| 296 | cplb_data[i].psize, | ||
| 297 | cplb_data[i].d_conf); | ||
| 298 | } else { | ||
| 299 | fill_cplbtab(t, | ||
| 300 | cplb_data[i].start, | ||
| 301 | a_start, SIZE_1M, | ||
| 302 | cplb_data[i].d_conf); | ||
| 303 | fill_cplbtab(t, a_start, | ||
| 304 | a_end, SIZE_4M, | ||
| 305 | cplb_data[i].d_conf); | ||
| 306 | fill_cplbtab(t, a_end, | ||
| 307 | cplb_data[i].end, | ||
| 308 | SIZE_1M, | ||
| 309 | cplb_data[i].d_conf); | ||
| 310 | } | ||
| 311 | } | 88 | } |
| 312 | 89 | ||
| 313 | void __init generate_cplb_tables(void) | 90 | void __init generate_cplb_tables_all(void) |
| 314 | { | 91 | { |
| 92 | int i_d, i_i; | ||
| 315 | 93 | ||
| 316 | u16 i, j, process; | 94 | i_d = 0; |
| 317 | u32 a_start, a_end, as, ae, as_1m; | 95 | /* Normal RAM, including MTD FS. */ |
| 318 | |||
| 319 | struct cplb_tab *t_i = NULL; | ||
| 320 | struct cplb_tab *t_d = NULL; | ||
| 321 | struct s_cplb cplb; | ||
| 322 | |||
| 323 | printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n"); | ||
| 324 | |||
| 325 | cplb.init_i.size = MAX_CPLBS; | ||
| 326 | cplb.init_d.size = MAX_CPLBS; | ||
| 327 | cplb.switch_i.size = MAX_SWITCH_I_CPLBS; | ||
| 328 | cplb.switch_d.size = MAX_SWITCH_D_CPLBS; | ||
| 329 | |||
| 330 | cplb.init_i.pos = 0; | ||
| 331 | cplb.init_d.pos = 0; | ||
| 332 | cplb.switch_i.pos = 0; | ||
| 333 | cplb.switch_d.pos = 0; | ||
| 334 | |||
| 335 | cplb.init_i.tab = icplb_table; | ||
| 336 | cplb.init_d.tab = dcplb_table; | ||
| 337 | cplb.switch_i.tab = ipdt_table; | ||
| 338 | cplb.switch_d.tab = dpdt_table; | ||
| 339 | |||
| 340 | cplb_data[SDRAM_KERN].end = memory_end; | ||
| 341 | |||
| 342 | #ifdef CONFIG_MTD_UCLINUX | 96 | #ifdef CONFIG_MTD_UCLINUX |
| 343 | cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start; | 97 | dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size; |
| 344 | cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size; | ||
| 345 | cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0; | ||
| 346 | # if defined(CONFIG_ROMFS_FS) | ||
| 347 | cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB; | ||
| 348 | |||
| 349 | /* | ||
| 350 | * The ROMFS_FS size is often not multiple of 1MB. | ||
| 351 | * This can cause multiple CPLB sets covering the same memory area. | ||
| 352 | * This will then cause multiple CPLB hit exceptions. | ||
| 353 | * Workaround: We ensure a contiguous memory area by extending the kernel | ||
| 354 | * memory section over the mtd section. | ||
| 355 | * For ROMFS_FS memory must be covered with ICPLBs anyways. | ||
| 356 | * So there is no difference between kernel and mtd memory setup. | ||
| 357 | */ | ||
| 358 | |||
| 359 | cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;; | ||
| 360 | cplb_data[SDRAM_RAM_MTD].valid = 0; | ||
| 361 | |||
| 362 | # endif | ||
| 363 | #else | 98 | #else |
| 364 | cplb_data[SDRAM_RAM_MTD].valid = 0; | 99 | dcplb_bounds[i_d].eaddr = memory_end; |
| 365 | #endif | 100 | #endif |
| 101 | dcplb_bounds[i_d++].data = SDRAM_DGENERIC; | ||
| 102 | /* DMA uncached region. */ | ||
| 103 | if (DMA_UNCACHED_REGION) { | ||
| 104 | dcplb_bounds[i_d].eaddr = _ramend; | ||
| 105 | dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL; | ||
| 106 | } | ||
| 107 | if (_ramend != physical_mem_end) { | ||
| 108 | /* Reserved memory. */ | ||
| 109 | dcplb_bounds[i_d].eaddr = physical_mem_end; | ||
| 110 | dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ? | ||
| 111 | SDRAM_DGENERIC : SDRAM_DNON_CHBL); | ||
| 112 | } | ||
| 113 | /* Addressing hole up to the async bank. */ | ||
| 114 | dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE; | ||
| 115 | dcplb_bounds[i_d++].data = 0; | ||
| 116 | /* ASYNC banks. */ | ||
| 117 | dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; | ||
| 118 | dcplb_bounds[i_d++].data = SDRAM_EBIU; | ||
| 119 | /* Addressing hole up to BootROM. */ | ||
| 120 | dcplb_bounds[i_d].eaddr = BOOT_ROM_START; | ||
| 121 | dcplb_bounds[i_d++].data = 0; | ||
| 122 | /* BootROM -- largest one should be less than 1 meg. */ | ||
| 123 | dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); | ||
| 124 | dcplb_bounds[i_d++].data = SDRAM_DGENERIC; | ||
| 125 | if (L2_LENGTH) { | ||
| 126 | /* Addressing hole up to L2 SRAM. */ | ||
| 127 | dcplb_bounds[i_d].eaddr = L2_START; | ||
| 128 | dcplb_bounds[i_d++].data = 0; | ||
| 129 | /* L2 SRAM. */ | ||
| 130 | dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH; | ||
| 131 | dcplb_bounds[i_d++].data = L2_DMEMORY; | ||
| 132 | } | ||
| 133 | dcplb_nr_bounds = i_d; | ||
| 134 | BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds)); | ||
| 366 | 135 | ||
| 367 | cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION; | 136 | i_i = 0; |
| 368 | cplb_data[SDRAM_DMAZ].end = _ramend; | 137 | /* Normal RAM, including MTD FS. */ |
| 369 | |||
| 370 | cplb_data[RES_MEM].start = _ramend; | ||
| 371 | cplb_data[RES_MEM].end = physical_mem_end; | ||
| 372 | |||
| 373 | if (reserved_mem_dcache_on) | ||
| 374 | cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC; | ||
| 375 | else | ||
| 376 | cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL; | ||
| 377 | |||
| 378 | if (reserved_mem_icache_on) | ||
| 379 | cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC; | ||
| 380 | else | ||
| 381 | cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; | ||
| 382 | |||
| 383 | for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) { | ||
| 384 | if (!cplb_data[i].valid) | ||
| 385 | continue; | ||
| 386 | |||
| 387 | as_1m = cplb_data[i].start % SIZE_1M; | ||
| 388 | |||
| 389 | /* We need to make sure all sections are properly 1M aligned | ||
| 390 | * However between Kernel Memory and the Kernel mtd section, depending on the | ||
| 391 | * rootfs size, there can be overlapping memory areas. | ||
| 392 | */ | ||
| 393 | |||
| 394 | if (as_1m && i != L1I_MEM && i != L1D_MEM) { | ||
| 395 | #ifdef CONFIG_MTD_UCLINUX | 138 | #ifdef CONFIG_MTD_UCLINUX |
| 396 | if (i == SDRAM_RAM_MTD) { | 139 | icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size; |
| 397 | if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start) | 140 | #else |
| 398 | cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M; | 141 | icplb_bounds[i_i].eaddr = memory_end; |
| 399 | else | ||
| 400 | cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)); | ||
| 401 | } else | ||
| 402 | #endif | 142 | #endif |
| 403 | printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n", | 143 | icplb_bounds[i_i++].data = SDRAM_IGENERIC; |
| 404 | cplb_data[i].name, cplb_data[i].start); | 144 | /* DMA uncached region. */ |
| 405 | } | 145 | if (DMA_UNCACHED_REGION) { |
| 406 | 146 | icplb_bounds[i_i].eaddr = _ramend; | |
| 407 | as = cplb_data[i].start % SIZE_4M; | 147 | icplb_bounds[i_i++].data = 0; |
| 408 | ae = cplb_data[i].end % SIZE_4M; | ||
| 409 | |||
| 410 | if (as) | ||
| 411 | a_start = cplb_data[i].start + (SIZE_4M - (as)); | ||
| 412 | else | ||
| 413 | a_start = cplb_data[i].start; | ||
| 414 | |||
| 415 | a_end = cplb_data[i].end - ae; | ||
| 416 | |||
| 417 | for (j = INITIAL_T; j <= SWITCH_T; j++) { | ||
| 418 | |||
| 419 | switch (j) { | ||
| 420 | case INITIAL_T: | ||
| 421 | if (cplb_data[i].attr & INITIAL_T) { | ||
| 422 | t_i = &cplb.init_i; | ||
| 423 | t_d = &cplb.init_d; | ||
| 424 | process = 1; | ||
| 425 | } else | ||
| 426 | process = 0; | ||
| 427 | break; | ||
| 428 | case SWITCH_T: | ||
| 429 | if (cplb_data[i].attr & SWITCH_T) { | ||
| 430 | t_i = &cplb.switch_i; | ||
| 431 | t_d = &cplb.switch_d; | ||
| 432 | process = 1; | ||
| 433 | } else | ||
| 434 | process = 0; | ||
| 435 | break; | ||
| 436 | default: | ||
| 437 | process = 0; | ||
| 438 | break; | ||
| 439 | } | ||
| 440 | |||
| 441 | if (!process) | ||
| 442 | continue; | ||
| 443 | if (cplb_data[i].attr & I_CPLB) | ||
| 444 | __fill_code_cplbtab(t_i, i, a_start, a_end); | ||
| 445 | |||
| 446 | if (cplb_data[i].attr & D_CPLB) | ||
| 447 | __fill_data_cplbtab(t_d, i, a_start, a_end); | ||
| 448 | } | ||
| 449 | } | 148 | } |
| 450 | 149 | if (_ramend != physical_mem_end) { | |
| 451 | /* close tables */ | 150 | /* Reserved memory. */ |
| 452 | 151 | icplb_bounds[i_i].eaddr = physical_mem_end; | |
| 453 | close_cplbtab(&cplb.init_i); | 152 | icplb_bounds[i_i++].data = (reserved_mem_icache_on ? |
| 454 | close_cplbtab(&cplb.init_d); | 153 | SDRAM_IGENERIC : SDRAM_INON_CHBL); |
| 455 | 154 | } | |
| 456 | cplb.init_i.tab[cplb.init_i.pos] = -1; | 155 | /* Addressing hole up to BootROM. */ |
| 457 | cplb.init_d.tab[cplb.init_d.pos] = -1; | 156 | icplb_bounds[i_i].eaddr = BOOT_ROM_START; |
| 458 | cplb.switch_i.tab[cplb.switch_i.pos] = -1; | 157 | icplb_bounds[i_i++].data = 0; |
| 459 | cplb.switch_d.tab[cplb.switch_d.pos] = -1; | 158 | /* BootROM -- largest one should be less than 1 meg. */ |
| 460 | 159 | icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); | |
| 160 | icplb_bounds[i_i++].data = SDRAM_IGENERIC; | ||
| 161 | if (L2_LENGTH) { | ||
| 162 | /* Addressing hole up to L2 SRAM, including the async bank. */ | ||
| 163 | icplb_bounds[i_i].eaddr = L2_START; | ||
| 164 | icplb_bounds[i_i++].data = 0; | ||
| 165 | /* L2 SRAM. */ | ||
| 166 | icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH; | ||
| 167 | icplb_bounds[i_i++].data = L2_IMEMORY; | ||
| 168 | } | ||
| 169 | icplb_nr_bounds = i_i; | ||
| 170 | BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds)); | ||
| 461 | } | 171 | } |
| 462 | |||
| 463 | #endif | ||
| 464 | |||
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S deleted file mode 100644 index f5cf3accef37..000000000000 --- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S +++ /dev/null | |||
| @@ -1,646 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-common/cplbmgtr.S | ||
| 3 | * Based on: | ||
| 4 | * Author: LG Soft India | ||
| 5 | * | ||
| 6 | * Created: ? | ||
| 7 | * Description: CPLB replacement routine for CPLB mismatch | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | /* Usage: int _cplb_mgr(is_data_miss,int enable_cache) | ||
| 31 | * is_data_miss==2 => Mark as Dirty, write to the clean data page | ||
| 32 | * is_data_miss==1 => Replace a data CPLB. | ||
| 33 | * is_data_miss==0 => Replace an instruction CPLB. | ||
| 34 | * | ||
| 35 | * Returns: | ||
| 36 | * CPLB_RELOADED => Successfully updated CPLB table. | ||
| 37 | * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted. | ||
| 38 | * This indicates that the CPLBs in the configuration | ||
| 39 | * tablei are badly configured, as this should never | ||
| 40 | * occur. | ||
| 41 | * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the | ||
| 42 | * exception, is not covered by any of the CPLBs in | ||
| 43 | * the configuration table. The application is | ||
| 44 | * presumably misbehaving. | ||
| 45 | * CPLB_PROT_VIOL => The address being accessed, that triggered the | ||
| 46 | * exception, was not a first-write to a clean Write | ||
| 47 | * Back Data page, and so presumably is a genuine | ||
| 48 | * violation of the page's protection attributes. | ||
| 49 | * The application is misbehaving. | ||
| 50 | */ | ||
| 51 | |||
| 52 | #include <linux/linkage.h> | ||
| 53 | #include <asm/blackfin.h> | ||
| 54 | #include <asm/cplb.h> | ||
| 55 | |||
| 56 | #ifdef CONFIG_EXCPT_IRQ_SYSC_L1 | ||
| 57 | .section .l1.text | ||
| 58 | #else | ||
| 59 | .text | ||
| 60 | #endif | ||
| 61 | |||
| 62 | .align 2; | ||
| 63 | ENTRY(_cplb_mgr) | ||
| 64 | |||
| 65 | [--SP]=( R7:4,P5:3 ); | ||
| 66 | |||
| 67 | CC = R0 == 2; | ||
| 68 | IF CC JUMP .Ldcplb_write; | ||
| 69 | |||
| 70 | CC = R0 == 0; | ||
| 71 | IF !CC JUMP .Ldcplb_miss_compare; | ||
| 72 | |||
| 73 | /* ICPLB Miss Exception. We need to choose one of the | ||
| 74 | * currently-installed CPLBs, and replace it with one | ||
| 75 | * from the configuration table. | ||
| 76 | */ | ||
| 77 | |||
| 78 | /* A multi-word instruction can cross a page boundary. This means the | ||
| 79 | * first part of the instruction can be in a valid page, but the | ||
| 80 | * second part is not, and hence generates the instruction miss. | ||
| 81 | * However, the fault address is for the start of the instruction, | ||
| 82 | * not the part that's in the bad page. Therefore, we have to check | ||
| 83 | * whether the fault address applies to a page that is already present | ||
| 84 | * in the table. | ||
| 85 | */ | ||
| 86 | |||
| 87 | P4.L = LO(ICPLB_FAULT_ADDR); | ||
| 88 | P4.H = HI(ICPLB_FAULT_ADDR); | ||
| 89 | |||
| 90 | P1 = 16; | ||
| 91 | P5.L = _page_size_table; | ||
| 92 | P5.H = _page_size_table; | ||
| 93 | |||
| 94 | P0.L = LO(ICPLB_DATA0); | ||
| 95 | P0.H = HI(ICPLB_DATA0); | ||
| 96 | R4 = [P4]; /* Get faulting address*/ | ||
| 97 | R6 = 64; /* Advance past the fault address, which*/ | ||
| 98 | R6 = R6 + R4; /* we'll use if we find a match*/ | ||
| 99 | R3 = ((16 << 8) | 2); /* Extract mask, two bits at posn 16 */ | ||
| 100 | |||
| 101 | R5 = 0; | ||
| 102 | .Lisearch: | ||
| 103 | |||
| 104 | R1 = [P0-0x100]; /* Address for this CPLB */ | ||
| 105 | |||
| 106 | R0 = [P0++]; /* Info for this CPLB*/ | ||
| 107 | CC = BITTST(R0,0); /* Is the CPLB valid?*/ | ||
| 108 | IF !CC JUMP .Lnomatch; /* Skip it, if not.*/ | ||
| 109 | CC = R4 < R1(IU); /* If fault address less than page start*/ | ||
| 110 | IF CC JUMP .Lnomatch; /* then skip this one.*/ | ||
| 111 | R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/ | ||
| 112 | P1 = R2; | ||
| 113 | P1 = P5 + (P1<<2); /* index into page-size table*/ | ||
| 114 | R2 = [P1]; /* Get the page size*/ | ||
| 115 | R1 = R1 + R2; /* and add to page start, to get page end*/ | ||
| 116 | CC = R4 < R1(IU); /* and see whether fault addr is in page.*/ | ||
| 117 | IF !CC R4 = R6; /* If so, advance the address and finish loop.*/ | ||
| 118 | IF !CC JUMP .Lisearch_done; | ||
| 119 | .Lnomatch: | ||
| 120 | /* Go around again*/ | ||
| 121 | R5 += 1; | ||
| 122 | CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/ | ||
| 123 | IF !CC JUMP .Lisearch; | ||
| 124 | |||
| 125 | .Lisearch_done: | ||
| 126 | I0 = R4; /* Fault address we'll search for*/ | ||
| 127 | |||
| 128 | /* set up pointers */ | ||
| 129 | P0.L = LO(ICPLB_DATA0); | ||
| 130 | P0.H = HI(ICPLB_DATA0); | ||
| 131 | |||
| 132 | /* The replacement procedure for ICPLBs */ | ||
| 133 | |||
| 134 | P4.L = LO(IMEM_CONTROL); | ||
| 135 | P4.H = HI(IMEM_CONTROL); | ||
| 136 | |||
| 137 | /* Turn off CPLBs while we work, necessary according to HRM before | ||
| 138 | * modifying CPLB descriptors | ||
| 139 | */ | ||
| 140 | R5 = [P4]; /* Control Register*/ | ||
| 141 | BITCLR(R5,ENICPLB_P); | ||
| 142 | CLI R1; | ||
| 143 | SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ | ||
| 144 | .align 8; | ||
| 145 | [P4] = R5; | ||
| 146 | SSYNC; | ||
| 147 | STI R1; | ||
| 148 | |||
| 149 | R1 = -1; /* end point comparison */ | ||
| 150 | R3 = 16; /* counter */ | ||
| 151 | |||
| 152 | /* Search through CPLBs for first non-locked entry */ | ||
| 153 | /* Overwrite it by moving everyone else up by 1 */ | ||
| 154 | .Licheck_lock: | ||
| 155 | R0 = [P0++]; | ||
| 156 | R3 = R3 + R1; | ||
| 157 | CC = R3 == R1; | ||
| 158 | IF CC JUMP .Lall_locked; | ||
| 159 | CC = BITTST(R0, 0); /* an invalid entry is good */ | ||
| 160 | IF !CC JUMP .Lifound_victim; | ||
| 161 | CC = BITTST(R0,1); /* but a locked entry isn't */ | ||
| 162 | IF CC JUMP .Licheck_lock; | ||
| 163 | |||
| 164 | .Lifound_victim: | ||
| 165 | #ifdef CONFIG_CPLB_INFO | ||
| 166 | R7 = [P0 - 0x104]; | ||
| 167 | P2.L = _ipdt_table; | ||
| 168 | P2.H = _ipdt_table; | ||
| 169 | P3.L = _ipdt_swapcount_table; | ||
| 170 | P3.H = _ipdt_swapcount_table; | ||
| 171 | P3 += -4; | ||
| 172 | .Licount: | ||
| 173 | R2 = [P2]; /* address from config table */ | ||
| 174 | P2 += 8; | ||
| 175 | P3 += 8; | ||
| 176 | CC = R2==-1; | ||
| 177 | IF CC JUMP .Licount_done; | ||
| 178 | CC = R7==R2; | ||
| 179 | IF !CC JUMP .Licount; | ||
| 180 | R7 = [P3]; | ||
| 181 | R7 += 1; | ||
| 182 | [P3] = R7; | ||
| 183 | CSYNC; | ||
| 184 | .Licount_done: | ||
| 185 | #endif | ||
| 186 | LC0=R3; | ||
| 187 | LSETUP(.Lis_move,.Lie_move) LC0; | ||
| 188 | .Lis_move: | ||
| 189 | R0 = [P0]; | ||
| 190 | [P0 - 4] = R0; | ||
| 191 | R0 = [P0 - 0x100]; | ||
| 192 | [P0-0x104] = R0; | ||
| 193 | .Lie_move: | ||
| 194 | P0+=4; | ||
| 195 | |||
| 196 | /* Clear ICPLB_DATA15, in case we don't find a replacement | ||
| 197 | * otherwise, we would have a duplicate entry, and will crash | ||
| 198 | */ | ||
| 199 | R0 = 0; | ||
| 200 | [P0 - 4] = R0; | ||
| 201 | |||
| 202 | /* We've made space in the ICPLB table, so that ICPLB15 | ||
| 203 | * is now free to be overwritten. Next, we have to determine | ||
| 204 | * which CPLB we need to install, from the configuration | ||
| 205 | * table. This is a matter of getting the start-of-page | ||
| 206 | * addresses and page-lengths from the config table, and | ||
| 207 | * determining whether the fault address falls within that | ||
| 208 | * range. | ||
| 209 | */ | ||
| 210 | |||
| 211 | P2.L = _ipdt_table; | ||
| 212 | P2.H = _ipdt_table; | ||
| 213 | #ifdef CONFIG_CPLB_INFO | ||
| 214 | P3.L = _ipdt_swapcount_table; | ||
| 215 | P3.H = _ipdt_swapcount_table; | ||
| 216 | P3 += -8; | ||
| 217 | #endif | ||
| 218 | P0.L = _page_size_table; | ||
| 219 | P0.H = _page_size_table; | ||
| 220 | |||
| 221 | /* Retrieve our fault address (which may have been advanced | ||
| 222 | * because the faulting instruction crossed a page boundary). | ||
| 223 | */ | ||
| 224 | |||
| 225 | R0 = I0; | ||
| 226 | |||
| 227 | /* An extraction pattern, to get the page-size bits from | ||
| 228 | * the CPLB data entry. Bits 16-17, so two bits at posn 16. | ||
| 229 | */ | ||
| 230 | |||
| 231 | R1 = ((16<<8)|2); | ||
| 232 | .Linext: R4 = [P2++]; /* address from config table */ | ||
| 233 | R2 = [P2++]; /* data from config table */ | ||
| 234 | #ifdef CONFIG_CPLB_INFO | ||
| 235 | P3 += 8; | ||
| 236 | #endif | ||
| 237 | |||
| 238 | CC = R4 == -1; /* End of config table*/ | ||
| 239 | IF CC JUMP .Lno_page_in_table; | ||
| 240 | |||
| 241 | /* See if failed address > start address */ | ||
| 242 | CC = R4 <= R0(IU); | ||
| 243 | IF !CC JUMP .Linext; | ||
| 244 | |||
| 245 | /* extract page size (17:16)*/ | ||
| 246 | R3 = EXTRACT(R2, R1.L) (Z); | ||
| 247 | |||
| 248 | /* add page size to addr to get range */ | ||
| 249 | |||
| 250 | P5 = R3; | ||
| 251 | P5 = P0 + (P5 << 2); /* scaled, for int access*/ | ||
| 252 | R3 = [P5]; | ||
| 253 | R3 = R3 + R4; | ||
| 254 | |||
| 255 | /* See if failed address < (start address + page size) */ | ||
| 256 | CC = R0 < R3(IU); | ||
| 257 | IF !CC JUMP .Linext; | ||
| 258 | |||
| 259 | /* We've found a CPLB in the config table that covers | ||
| 260 | * the faulting address, so install this CPLB into the | ||
| 261 | * last entry of the table. | ||
| 262 | */ | ||
| 263 | |||
| 264 | P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */ | ||
| 265 | P1.H = HI(ICPLB_DATA15); | ||
| 266 | [P1] = R2; | ||
| 267 | [P1-0x100] = R4; | ||
| 268 | #ifdef CONFIG_CPLB_INFO | ||
| 269 | R3 = [P3]; | ||
| 270 | R3 += 1; | ||
| 271 | [P3] = R3; | ||
| 272 | #endif | ||
| 273 | |||
| 274 | /* P4 points to IMEM_CONTROL, and R5 contains its old | ||
| 275 | * value, after we disabled ICPLBS. Re-enable them. | ||
| 276 | */ | ||
| 277 | |||
| 278 | BITSET(R5,ENICPLB_P); | ||
| 279 | CLI R2; | ||
| 280 | SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ | ||
| 281 | .align 8; | ||
| 282 | [P4] = R5; | ||
| 283 | SSYNC; | ||
| 284 | STI R2; | ||
| 285 | |||
| 286 | ( R7:4,P5:3 ) = [SP++]; | ||
| 287 | R0 = CPLB_RELOADED; | ||
| 288 | RTS; | ||
| 289 | |||
| 290 | /* FAILED CASES*/ | ||
| 291 | .Lno_page_in_table: | ||
| 292 | R0 = CPLB_NO_ADDR_MATCH; | ||
| 293 | JUMP .Lfail_ret; | ||
| 294 | |||
| 295 | .Lall_locked: | ||
| 296 | R0 = CPLB_NO_UNLOCKED; | ||
| 297 | JUMP .Lfail_ret; | ||
| 298 | |||
| 299 | .Lprot_violation: | ||
| 300 | R0 = CPLB_PROT_VIOL; | ||
| 301 | |||
| 302 | .Lfail_ret: | ||
| 303 | /* Make sure we turn protection/cache back on, even in the failing case */ | ||
| 304 | BITSET(R5,ENICPLB_P); | ||
| 305 | CLI R2; | ||
| 306 | SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ | ||
| 307 | .align 8; | ||
| 308 | [P4] = R5; | ||
| 309 | SSYNC; | ||
| 310 | STI R2; | ||
| 311 | |||
| 312 | ( R7:4,P5:3 ) = [SP++]; | ||
| 313 | RTS; | ||
| 314 | |||
| 315 | .Ldcplb_write: | ||
| 316 | |||
| 317 | /* if a DCPLB is marked as write-back (CPLB_WT==0), and | ||
| 318 | * it is clean (CPLB_DIRTY==0), then a write to the | ||
| 319 | * CPLB's page triggers a protection violation. We have to | ||
| 320 | * mark the CPLB as dirty, to indicate that there are | ||
| 321 | * pending writes associated with the CPLB. | ||
| 322 | */ | ||
| 323 | |||
| 324 | P4.L = LO(DCPLB_STATUS); | ||
| 325 | P4.H = HI(DCPLB_STATUS); | ||
| 326 | P3.L = LO(DCPLB_DATA0); | ||
| 327 | P3.H = HI(DCPLB_DATA0); | ||
| 328 | R5 = [P4]; | ||
| 329 | |||
| 330 | /* A protection violation can be caused by more than just writes | ||
| 331 | * to a clean WB page, so we have to ensure that: | ||
| 332 | * - It's a write | ||
| 333 | * - to a clean WB page | ||
| 334 | * - and is allowed in the mode the access occurred. | ||
| 335 | */ | ||
| 336 | |||
| 337 | CC = BITTST(R5, 16); /* ensure it was a write*/ | ||
| 338 | IF !CC JUMP .Lprot_violation; | ||
| 339 | |||
| 340 | /* to check the rest, we have to retrieve the DCPLB.*/ | ||
| 341 | |||
| 342 | /* The low half of DCPLB_STATUS is a bit mask*/ | ||
| 343 | |||
| 344 | R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/ | ||
| 345 | R3 = 30; /* so we can use this to determine the offset*/ | ||
| 346 | R2.L = SIGNBITS R2; | ||
| 347 | R2 = R2.L (Z); /* into the DCPLB table.*/ | ||
| 348 | R3 = R3 - R2; | ||
| 349 | P4 = R3; | ||
| 350 | P3 = P3 + (P4<<2); | ||
| 351 | R3 = [P3]; /* Retrieve the CPLB*/ | ||
| 352 | |||
| 353 | /* Now we can check whether it's a clean WB page*/ | ||
| 354 | |||
| 355 | CC = BITTST(R3, 14); /* 0==WB, 1==WT*/ | ||
| 356 | IF CC JUMP .Lprot_violation; | ||
| 357 | CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/ | ||
| 358 | IF CC JUMP .Lprot_violation; | ||
| 359 | |||
| 360 | /* Check whether the write is allowed in the mode that was active.*/ | ||
| 361 | |||
| 362 | R2 = 1<<3; /* checking write in user mode*/ | ||
| 363 | CC = BITTST(R5, 17); /* 0==was user, 1==was super*/ | ||
| 364 | R5 = CC; | ||
| 365 | R2 <<= R5; /* if was super, check write in super mode*/ | ||
| 366 | R2 = R3 & R2; | ||
| 367 | CC = R2 == 0; | ||
| 368 | IF CC JUMP .Lprot_violation; | ||
| 369 | |||
| 370 | /* It's a genuine write-to-clean-page.*/ | ||
| 371 | |||
| 372 | BITSET(R3, 7); /* mark as dirty*/ | ||
| 373 | [P3] = R3; /* and write back.*/ | ||
| 374 | NOP; | ||
| 375 | CSYNC; | ||
| 376 | ( R7:4,P5:3 ) = [SP++]; | ||
| 377 | R0 = CPLB_RELOADED; | ||
| 378 | RTS; | ||
| 379 | |||
| 380 | .Ldcplb_miss_compare: | ||
| 381 | |||
| 382 | /* Data CPLB Miss event. We need to choose a CPLB to | ||
| 383 | * evict, and then locate a new CPLB to install from the | ||
| 384 | * config table, that covers the faulting address. | ||
| 385 | */ | ||
| 386 | |||
| 387 | P1.L = LO(DCPLB_DATA15); | ||
| 388 | P1.H = HI(DCPLB_DATA15); | ||
| 389 | |||
| 390 | P4.L = LO(DCPLB_FAULT_ADDR); | ||
| 391 | P4.H = HI(DCPLB_FAULT_ADDR); | ||
| 392 | R4 = [P4]; | ||
| 393 | I0 = R4; | ||
| 394 | |||
| 395 | /* The replacement procedure for DCPLBs*/ | ||
| 396 | |||
| 397 | R6 = R1; /* Save for later*/ | ||
| 398 | |||
| 399 | /* Turn off CPLBs while we work.*/ | ||
| 400 | P4.L = LO(DMEM_CONTROL); | ||
| 401 | P4.H = HI(DMEM_CONTROL); | ||
| 402 | R5 = [P4]; | ||
| 403 | BITCLR(R5,ENDCPLB_P); | ||
| 404 | CLI R0; | ||
| 405 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ | ||
| 406 | .align 8; | ||
| 407 | [P4] = R5; | ||
| 408 | SSYNC; | ||
| 409 | STI R0; | ||
| 410 | |||
| 411 | /* Start looking for a CPLB to evict. Our order of preference | ||
| 412 | * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs | ||
| 413 | * are no good. | ||
| 414 | */ | ||
| 415 | |||
| 416 | I1.L = LO(DCPLB_DATA0); | ||
| 417 | I1.H = HI(DCPLB_DATA0); | ||
| 418 | P1 = 2; | ||
| 419 | P2 = 16; | ||
| 420 | I2.L = _dcplb_preference; | ||
| 421 | I2.H = _dcplb_preference; | ||
| 422 | LSETUP(.Lsdsearch1, .Ledsearch1) LC0 = P1; | ||
| 423 | .Lsdsearch1: | ||
| 424 | R0 = [I2++]; /* Get the bits we're interested in*/ | ||
| 425 | P0 = I1; /* Go back to start of table*/ | ||
| 426 | LSETUP (.Lsdsearch2, .Ledsearch2) LC1 = P2; | ||
| 427 | .Lsdsearch2: | ||
| 428 | R1 = [P0++]; /* Fetch each installed CPLB in turn*/ | ||
| 429 | R2 = R1 & R0; /* and test for interesting bits.*/ | ||
| 430 | CC = R2 == 0; /* If none are set, it'll do.*/ | ||
| 431 | IF !CC JUMP .Lskip_stack_check; | ||
| 432 | |||
| 433 | R2 = [P0 - 0x104]; /* R2 - PageStart */ | ||
| 434 | P3.L = _page_size_table; /* retrieve end address */ | ||
| 435 | P3.H = _page_size_table; /* retrieve end address */ | ||
| 436 | R3 = 0x1002; /* 16th - position, 2 bits -length */ | ||
| 437 | #if ANOMALY_05000209 | ||
| 438 | nop; /* Anomaly 05000209 */ | ||
| 439 | #endif | ||
| 440 | R7 = EXTRACT(R1,R3.l); | ||
| 441 | R7 = R7 << 2; /* Page size index offset */ | ||
| 442 | P5 = R7; | ||
| 443 | P3 = P3 + P5; | ||
| 444 | R7 = [P3]; /* page size in bytes */ | ||
| 445 | |||
| 446 | R7 = R2 + R7; /* R7 - PageEnd */ | ||
| 447 | R4 = SP; /* Test SP is in range */ | ||
| 448 | |||
| 449 | CC = R7 < R4; /* if PageEnd < SP */ | ||
| 450 | IF CC JUMP .Ldfound_victim; | ||
| 451 | R3 = 0x284; /* stack length from start of trap till | ||
| 452 | * the point. | ||
| 453 | * 20 stack locations for future modifications | ||
| 454 | */ | ||
| 455 | R4 = R4 + R3; | ||
| 456 | CC = R4 < R2; /* if SP + stacklen < PageStart */ | ||
| 457 | IF CC JUMP .Ldfound_victim; | ||
| 458 | .Lskip_stack_check: | ||
| 459 | |||
| 460 | .Ledsearch2: NOP; | ||
| 461 | .Ledsearch1: NOP; | ||
| 462 | |||
| 463 | /* If we got here, we didn't find a DCPLB we considered | ||
| 464 | * replacable, which means all of them were locked. | ||
| 465 | */ | ||
| 466 | |||
| 467 | JUMP .Lall_locked; | ||
| 468 | .Ldfound_victim: | ||
| 469 | |||
| 470 | #ifdef CONFIG_CPLB_INFO | ||
| 471 | R7 = [P0 - 0x104]; | ||
| 472 | P2.L = _dpdt_table; | ||
| 473 | P2.H = _dpdt_table; | ||
| 474 | P3.L = _dpdt_swapcount_table; | ||
| 475 | P3.H = _dpdt_swapcount_table; | ||
| 476 | P3 += -4; | ||
| 477 | .Ldicount: | ||
| 478 | R2 = [P2]; | ||
| 479 | P2 += 8; | ||
| 480 | P3 += 8; | ||
| 481 | CC = R2==-1; | ||
| 482 | IF CC JUMP .Ldicount_done; | ||
| 483 | CC = R7==R2; | ||
| 484 | IF !CC JUMP .Ldicount; | ||
| 485 | R7 = [P3]; | ||
| 486 | R7 += 1; | ||
| 487 | [P3] = R7; | ||
| 488 | .Ldicount_done: | ||
| 489 | #endif | ||
| 490 | |||
| 491 | /* Clean down the hardware loops*/ | ||
| 492 | R2 = 0; | ||
| 493 | LC1 = R2; | ||
| 494 | LC0 = R2; | ||
| 495 | |||
| 496 | /* There's a suitable victim in [P0-4] (because we've | ||
| 497 | * advanced already). | ||
| 498 | */ | ||
| 499 | |||
| 500 | .LDdoverwrite: | ||
| 501 | |||
| 502 | /* [P0-4] is a suitable victim CPLB, so we want to | ||
| 503 | * overwrite it by moving all the following CPLBs | ||
| 504 | * one space closer to the start. | ||
| 505 | */ | ||
| 506 | |||
| 507 | R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */ | ||
| 508 | R1.H = HI(DCPLB_DATA16); | ||
| 509 | R0 = P0; | ||
| 510 | |||
| 511 | /* If the victim happens to be in DCPLB15, | ||
| 512 | * we don't need to move anything. | ||
| 513 | */ | ||
| 514 | |||
| 515 | CC = R1 == R0; | ||
| 516 | IF CC JUMP .Lde_moved; | ||
| 517 | R1 = R1 - R0; | ||
| 518 | R1 >>= 2; | ||
| 519 | P1 = R1; | ||
| 520 | LSETUP(.Lds_move, .Lde_move) LC0=P1; | ||
| 521 | .Lds_move: | ||
| 522 | R0 = [P0++]; /* move data */ | ||
| 523 | [P0 - 8] = R0; | ||
| 524 | R0 = [P0-0x104] /* move address */ | ||
| 525 | .Lde_move: | ||
| 526 | [P0-0x108] = R0; | ||
| 527 | |||
| 528 | .Lde_moved: | ||
| 529 | NOP; | ||
| 530 | |||
| 531 | /* Clear DCPLB_DATA15, in case we don't find a replacement | ||
| 532 | * otherwise, we would have a duplicate entry, and will crash | ||
| 533 | */ | ||
| 534 | R0 = 0; | ||
| 535 | [P0 - 0x4] = R0; | ||
| 536 | |||
| 537 | /* We've now made space in DCPLB15 for the new CPLB to be | ||
| 538 | * installed. The next stage is to locate a CPLB in the | ||
| 539 | * config table that covers the faulting address. | ||
| 540 | */ | ||
| 541 | |||
| 542 | R0 = I0; /* Our faulting address */ | ||
| 543 | |||
| 544 | P2.L = _dpdt_table; | ||
| 545 | P2.H = _dpdt_table; | ||
| 546 | #ifdef CONFIG_CPLB_INFO | ||
| 547 | P3.L = _dpdt_swapcount_table; | ||
| 548 | P3.H = _dpdt_swapcount_table; | ||
| 549 | P3 += -8; | ||
| 550 | #endif | ||
| 551 | |||
| 552 | P1.L = _page_size_table; | ||
| 553 | P1.H = _page_size_table; | ||
| 554 | |||
| 555 | /* An extraction pattern, to retrieve bits 17:16.*/ | ||
| 556 | |||
| 557 | R1 = (16<<8)|2; | ||
| 558 | .Ldnext: R4 = [P2++]; /* address */ | ||
| 559 | R2 = [P2++]; /* data */ | ||
| 560 | #ifdef CONFIG_CPLB_INFO | ||
| 561 | P3 += 8; | ||
| 562 | #endif | ||
| 563 | |||
| 564 | CC = R4 == -1; | ||
| 565 | IF CC JUMP .Lno_page_in_table; | ||
| 566 | |||
| 567 | /* See if failed address > start address */ | ||
| 568 | CC = R4 <= R0(IU); | ||
| 569 | IF !CC JUMP .Ldnext; | ||
| 570 | |||
| 571 | /* extract page size (17:16)*/ | ||
| 572 | R3 = EXTRACT(R2, R1.L) (Z); | ||
| 573 | |||
| 574 | /* add page size to addr to get range */ | ||
| 575 | |||
| 576 | P5 = R3; | ||
| 577 | P5 = P1 + (P5 << 2); | ||
| 578 | R3 = [P5]; | ||
| 579 | R3 = R3 + R4; | ||
| 580 | |||
| 581 | /* See if failed address < (start address + page size) */ | ||
| 582 | CC = R0 < R3(IU); | ||
| 583 | IF !CC JUMP .Ldnext; | ||
| 584 | |||
| 585 | /* We've found the CPLB that should be installed, so | ||
| 586 | * write it into CPLB15, masking off any caching bits | ||
| 587 | * if necessary. | ||
| 588 | */ | ||
| 589 | |||
| 590 | P1.L = LO(DCPLB_DATA15); | ||
| 591 | P1.H = HI(DCPLB_DATA15); | ||
| 592 | |||
| 593 | /* If the DCPLB has cache bits set, but caching hasn't | ||
| 594 | * been enabled, then we want to mask off the cache-in-L1 | ||
| 595 | * bit before installing. Moreover, if caching is off, we | ||
| 596 | * also want to ensure that the DCPLB has WT mode set, rather | ||
| 597 | * than WB, since WB pages still trigger first-write exceptions | ||
| 598 | * even when not caching is off, and the page isn't marked as | ||
| 599 | * cachable. Finally, we could mark the page as clean, not dirty, | ||
| 600 | * but we choose to leave that decision to the user; if the user | ||
| 601 | * chooses to have a CPLB pre-defined as dirty, then they always | ||
| 602 | * pay the cost of flushing during eviction, but don't pay the | ||
| 603 | * cost of first-write exceptions to mark the page as dirty. | ||
| 604 | */ | ||
| 605 | |||
| 606 | #ifdef CONFIG_BFIN_WT | ||
| 607 | BITSET(R6, 14); /* Set WT*/ | ||
| 608 | #endif | ||
| 609 | |||
| 610 | [P1] = R2; | ||
| 611 | [P1-0x100] = R4; | ||
| 612 | #ifdef CONFIG_CPLB_INFO | ||
| 613 | R3 = [P3]; | ||
| 614 | R3 += 1; | ||
| 615 | [P3] = R3; | ||
| 616 | #endif | ||
| 617 | |||
| 618 | /* We've installed the CPLB, so re-enable CPLBs. P4 | ||
| 619 | * points to DMEM_CONTROL, and R5 is the value we | ||
| 620 | * last wrote to it, when we were disabling CPLBs. | ||
| 621 | */ | ||
| 622 | |||
| 623 | BITSET(R5,ENDCPLB_P); | ||
| 624 | CLI R2; | ||
| 625 | .align 8; | ||
| 626 | [P4] = R5; | ||
| 627 | SSYNC; | ||
| 628 | STI R2; | ||
| 629 | |||
| 630 | ( R7:4,P5:3 ) = [SP++]; | ||
| 631 | R0 = CPLB_RELOADED; | ||
| 632 | RTS; | ||
| 633 | ENDPROC(_cplb_mgr) | ||
| 634 | |||
| 635 | .data | ||
| 636 | .align 4; | ||
| 637 | _page_size_table: | ||
| 638 | .byte4 0x00000400; /* 1K */ | ||
| 639 | .byte4 0x00001000; /* 4K */ | ||
| 640 | .byte4 0x00100000; /* 1M */ | ||
| 641 | .byte4 0x00400000; /* 4M */ | ||
| 642 | |||
| 643 | .align 4; | ||
| 644 | _dcplb_preference: | ||
| 645 | .byte4 0x00000001; /* valid bit */ | ||
| 646 | .byte4 0x00000002; /* lock bit */ | ||
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c new file mode 100644 index 000000000000..376249ab2694 --- /dev/null +++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c | |||
| @@ -0,0 +1,283 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/kernel/cplb-nompu-c/cplbmgr.c | ||
| 3 | * Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c | ||
| 4 | * Author: Michael McTernan <mmcternan@airvana.com> | ||
| 5 | * | ||
| 6 | * Created: 01Nov2008 | ||
| 7 | * Description: CPLB miss handler. | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2008 Airvana Inc. | ||
| 11 | * Copyright 2004-2007 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | */ | ||
| 25 | |||
| 26 | #include <linux/kernel.h> | ||
| 27 | #include <asm/blackfin.h> | ||
| 28 | #include <asm/cplbinit.h> | ||
| 29 | #include <asm/cplb.h> | ||
| 30 | #include <asm/mmu_context.h> | ||
| 31 | |||
| 32 | /* | ||
| 33 | * WARNING | ||
| 34 | * | ||
| 35 | * This file is compiled with certain -ffixed-reg options. We have to | ||
| 36 | * make sure not to call any functions here that could clobber these | ||
| 37 | * registers. | ||
| 38 | */ | ||
| 39 | |||
| 40 | int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS]; | ||
| 41 | int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS]; | ||
| 42 | int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS]; | ||
| 43 | |||
| 44 | #ifdef CONFIG_EXCPT_IRQ_SYSC_L1 | ||
| 45 | #define MGR_ATTR __attribute__((l1_text)) | ||
| 46 | #else | ||
| 47 | #define MGR_ATTR | ||
| 48 | #endif | ||
| 49 | |||
| 50 | /* | ||
| 51 | * We're in an exception handler. The normal cli nop nop workaround | ||
| 52 | * isn't going to do very much, as the only thing that can interrupt | ||
| 53 | * us is an NMI, and the cli isn't going to stop that. | ||
| 54 | */ | ||
| 55 | #define NOWA_SSYNC __asm__ __volatile__ ("ssync;") | ||
| 56 | |||
| 57 | /* Anomaly handlers provide SSYNCs, so avoid extra if anomaly is present */ | ||
| 58 | #if ANOMALY_05000125 | ||
| 59 | |||
| 60 | #define bfin_write_DMEM_CONTROL_SSYNC(v) bfin_write_DMEM_CONTROL(v) | ||
| 61 | #define bfin_write_IMEM_CONTROL_SSYNC(v) bfin_write_IMEM_CONTROL(v) | ||
| 62 | |||
| 63 | #else | ||
| 64 | |||
| 65 | #define bfin_write_DMEM_CONTROL_SSYNC(v) \ | ||
| 66 | do { NOWA_SSYNC; bfin_write_DMEM_CONTROL(v); NOWA_SSYNC; } while (0) | ||
| 67 | #define bfin_write_IMEM_CONTROL_SSYNC(v) \ | ||
| 68 | do { NOWA_SSYNC; bfin_write_IMEM_CONTROL(v); NOWA_SSYNC; } while (0) | ||
| 69 | |||
| 70 | #endif | ||
| 71 | |||
| 72 | static inline void write_dcplb_data(int cpu, int idx, unsigned long data, | ||
| 73 | unsigned long addr) | ||
| 74 | { | ||
| 75 | unsigned long ctrl = bfin_read_DMEM_CONTROL(); | ||
| 76 | bfin_write_DMEM_CONTROL_SSYNC(ctrl & ~ENDCPLB); | ||
| 77 | bfin_write32(DCPLB_DATA0 + idx * 4, data); | ||
| 78 | bfin_write32(DCPLB_ADDR0 + idx * 4, addr); | ||
| 79 | bfin_write_DMEM_CONTROL_SSYNC(ctrl); | ||
| 80 | |||
| 81 | #ifdef CONFIG_CPLB_INFO | ||
| 82 | dcplb_tbl[cpu][idx].addr = addr; | ||
| 83 | dcplb_tbl[cpu][idx].data = data; | ||
| 84 | #endif | ||
| 85 | } | ||
| 86 | |||
| 87 | static inline void write_icplb_data(int cpu, int idx, unsigned long data, | ||
| 88 | unsigned long addr) | ||
| 89 | { | ||
| 90 | unsigned long ctrl = bfin_read_IMEM_CONTROL(); | ||
| 91 | |||
| 92 | bfin_write_IMEM_CONTROL_SSYNC(ctrl & ~ENICPLB); | ||
| 93 | bfin_write32(ICPLB_DATA0 + idx * 4, data); | ||
| 94 | bfin_write32(ICPLB_ADDR0 + idx * 4, addr); | ||
| 95 | bfin_write_IMEM_CONTROL_SSYNC(ctrl); | ||
| 96 | |||
| 97 | #ifdef CONFIG_CPLB_INFO | ||
| 98 | icplb_tbl[cpu][idx].addr = addr; | ||
| 99 | icplb_tbl[cpu][idx].data = data; | ||
| 100 | #endif | ||
| 101 | } | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Given the contents of the status register, return the index of the | ||
| 105 | * CPLB that caused the fault. | ||
| 106 | */ | ||
| 107 | static inline int faulting_cplb_index(int status) | ||
| 108 | { | ||
| 109 | int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF); | ||
| 110 | return 30 - signbits; | ||
| 111 | } | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Given the contents of the status register and the DCPLB_DATA contents, | ||
| 115 | * return true if a write access should be permitted. | ||
| 116 | */ | ||
| 117 | static inline int write_permitted(int status, unsigned long data) | ||
| 118 | { | ||
| 119 | if (status & FAULT_USERSUPV) | ||
| 120 | return !!(data & CPLB_SUPV_WR); | ||
| 121 | else | ||
| 122 | return !!(data & CPLB_USER_WR); | ||
| 123 | } | ||
| 124 | |||
| 125 | /* Counters to implement round-robin replacement. */ | ||
| 126 | static int icplb_rr_index[NR_CPUS] PDT_ATTR; | ||
| 127 | static int dcplb_rr_index[NR_CPUS] PDT_ATTR; | ||
| 128 | |||
| 129 | /* | ||
| 130 | * Find an ICPLB entry to be evicted and return its index. | ||
| 131 | */ | ||
| 132 | static int evict_one_icplb(int cpu) | ||
| 133 | { | ||
| 134 | int i = first_switched_icplb + icplb_rr_index[cpu]; | ||
| 135 | if (i >= MAX_CPLBS) { | ||
| 136 | i -= MAX_CPLBS - first_switched_icplb; | ||
| 137 | icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb; | ||
| 138 | } | ||
| 139 | icplb_rr_index[cpu]++; | ||
| 140 | return i; | ||
| 141 | } | ||
| 142 | |||
| 143 | static int evict_one_dcplb(int cpu) | ||
| 144 | { | ||
| 145 | int i = first_switched_dcplb + dcplb_rr_index[cpu]; | ||
| 146 | if (i >= MAX_CPLBS) { | ||
| 147 | i -= MAX_CPLBS - first_switched_dcplb; | ||
| 148 | dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb; | ||
| 149 | } | ||
| 150 | dcplb_rr_index[cpu]++; | ||
| 151 | return i; | ||
| 152 | } | ||
| 153 | |||
| 154 | MGR_ATTR static int icplb_miss(int cpu) | ||
| 155 | { | ||
| 156 | unsigned long addr = bfin_read_ICPLB_FAULT_ADDR(); | ||
| 157 | int status = bfin_read_ICPLB_STATUS(); | ||
| 158 | int idx; | ||
| 159 | unsigned long i_data, base, addr1, eaddr; | ||
| 160 | |||
| 161 | nr_icplb_miss[cpu]++; | ||
| 162 | if (unlikely(status & FAULT_USERSUPV)) | ||
| 163 | nr_icplb_supv_miss[cpu]++; | ||
| 164 | |||
| 165 | base = 0; | ||
| 166 | for (idx = 0; idx < icplb_nr_bounds; idx++) { | ||
| 167 | eaddr = icplb_bounds[idx].eaddr; | ||
| 168 | if (addr < eaddr) | ||
| 169 | break; | ||
| 170 | base = eaddr; | ||
| 171 | } | ||
| 172 | if (unlikely(idx == icplb_nr_bounds)) | ||
| 173 | return CPLB_NO_ADDR_MATCH; | ||
| 174 | |||
| 175 | i_data = icplb_bounds[idx].data; | ||
| 176 | if (unlikely(i_data == 0)) | ||
| 177 | return CPLB_NO_ADDR_MATCH; | ||
| 178 | |||
| 179 | addr1 = addr & ~(SIZE_4M - 1); | ||
| 180 | addr &= ~(SIZE_1M - 1); | ||
| 181 | i_data |= PAGE_SIZE_1MB; | ||
| 182 | if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) { | ||
| 183 | /* | ||
| 184 | * This works because | ||
| 185 | * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB. | ||
| 186 | */ | ||
| 187 | i_data |= PAGE_SIZE_4MB; | ||
| 188 | addr = addr1; | ||
| 189 | } | ||
| 190 | |||
| 191 | /* Pick entry to evict */ | ||
| 192 | idx = evict_one_icplb(cpu); | ||
| 193 | |||
| 194 | write_icplb_data(cpu, idx, i_data, addr); | ||
| 195 | |||
| 196 | return CPLB_RELOADED; | ||
| 197 | } | ||
| 198 | |||
| 199 | MGR_ATTR static int dcplb_miss(int cpu) | ||
| 200 | { | ||
| 201 | unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); | ||
| 202 | int status = bfin_read_DCPLB_STATUS(); | ||
| 203 | int idx; | ||
| 204 | unsigned long d_data, base, addr1, eaddr; | ||
| 205 | |||
| 206 | nr_dcplb_miss[cpu]++; | ||
| 207 | if (unlikely(status & FAULT_USERSUPV)) | ||
| 208 | nr_dcplb_supv_miss[cpu]++; | ||
| 209 | |||
| 210 | base = 0; | ||
| 211 | for (idx = 0; idx < dcplb_nr_bounds; idx++) { | ||
| 212 | eaddr = dcplb_bounds[idx].eaddr; | ||
| 213 | if (addr < eaddr) | ||
| 214 | break; | ||
| 215 | base = eaddr; | ||
| 216 | } | ||
| 217 | if (unlikely(idx == dcplb_nr_bounds)) | ||
| 218 | return CPLB_NO_ADDR_MATCH; | ||
| 219 | |||
| 220 | d_data = dcplb_bounds[idx].data; | ||
| 221 | if (unlikely(d_data == 0)) | ||
| 222 | return CPLB_NO_ADDR_MATCH; | ||
| 223 | |||
| 224 | addr1 = addr & ~(SIZE_4M - 1); | ||
| 225 | addr &= ~(SIZE_1M - 1); | ||
| 226 | d_data |= PAGE_SIZE_1MB; | ||
| 227 | if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) { | ||
| 228 | /* | ||
| 229 | * This works because | ||
| 230 | * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB. | ||
| 231 | */ | ||
| 232 | d_data |= PAGE_SIZE_4MB; | ||
| 233 | addr = addr1; | ||
| 234 | } | ||
| 235 | |||
| 236 | /* Pick entry to evict */ | ||
| 237 | idx = evict_one_dcplb(cpu); | ||
| 238 | |||
| 239 | write_dcplb_data(cpu, idx, d_data, addr); | ||
| 240 | |||
| 241 | return CPLB_RELOADED; | ||
| 242 | } | ||
| 243 | |||
| 244 | MGR_ATTR static noinline int dcplb_protection_fault(int cpu) | ||
| 245 | { | ||
| 246 | int status = bfin_read_DCPLB_STATUS(); | ||
| 247 | |||
| 248 | nr_dcplb_prot[cpu]++; | ||
| 249 | |||
| 250 | if (likely(status & FAULT_RW)) { | ||
| 251 | int idx = faulting_cplb_index(status); | ||
| 252 | unsigned long regaddr = DCPLB_DATA0 + idx * 4; | ||
| 253 | unsigned long data = bfin_read32(regaddr); | ||
| 254 | |||
| 255 | /* Check if fault is to dirty a clean page */ | ||
| 256 | if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) && | ||
| 257 | write_permitted(status, data)) { | ||
| 258 | |||
| 259 | dcplb_tbl[cpu][idx].data = data; | ||
| 260 | bfin_write32(regaddr, data); | ||
| 261 | return CPLB_RELOADED; | ||
| 262 | } | ||
| 263 | } | ||
| 264 | |||
| 265 | return CPLB_PROT_VIOL; | ||
| 266 | } | ||
| 267 | |||
| 268 | MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs) | ||
| 269 | { | ||
| 270 | int cause = seqstat & 0x3f; | ||
| 271 | unsigned int cpu = smp_processor_id(); | ||
| 272 | switch (cause) { | ||
| 273 | case 0x2C: | ||
| 274 | return icplb_miss(cpu); | ||
| 275 | case 0x26: | ||
| 276 | return dcplb_miss(cpu); | ||
| 277 | default: | ||
| 278 | if (unlikely(cause == 0x23)) | ||
| 279 | return dcplb_protection_fault(cpu); | ||
| 280 | |||
| 281 | return CPLB_UNKNOWN_ERR; | ||
| 282 | } | ||
| 283 | } | ||
diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c new file mode 100644 index 000000000000..64d78300dd08 --- /dev/null +++ b/arch/blackfin/kernel/cplbinfo.c | |||
| @@ -0,0 +1,177 @@ | |||
| 1 | /* | ||
| 2 | * arch/blackfin/kernel/cplbinfo.c - display CPLB status | ||
| 3 | * | ||
| 4 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/ctype.h> | ||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/proc_fs.h> | ||
| 13 | #include <linux/seq_file.h> | ||
| 14 | #include <linux/uaccess.h> | ||
| 15 | |||
| 16 | #include <asm/cplbinit.h> | ||
| 17 | #include <asm/blackfin.h> | ||
| 18 | |||
| 19 | static char const page_strtbl[][3] = { "1K", "4K", "1M", "4M" }; | ||
| 20 | #define page(flags) (((flags) & 0x30000) >> 16) | ||
| 21 | #define strpage(flags) page_strtbl[page(flags)] | ||
| 22 | |||
| 23 | struct cplbinfo_data { | ||
| 24 | loff_t pos; | ||
| 25 | char cplb_type; | ||
| 26 | u32 mem_control; | ||
| 27 | struct cplb_entry *tbl; | ||
| 28 | int switched; | ||
| 29 | }; | ||
| 30 | |||
| 31 | static void cplbinfo_print_header(struct seq_file *m) | ||
| 32 | { | ||
| 33 | seq_printf(m, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n"); | ||
| 34 | } | ||
| 35 | |||
| 36 | static int cplbinfo_nomore(struct cplbinfo_data *cdata) | ||
| 37 | { | ||
| 38 | return cdata->pos >= MAX_CPLBS; | ||
| 39 | } | ||
| 40 | |||
| 41 | static int cplbinfo_show(struct seq_file *m, void *p) | ||
| 42 | { | ||
| 43 | struct cplbinfo_data *cdata; | ||
| 44 | unsigned long data, addr; | ||
| 45 | loff_t pos; | ||
| 46 | |||
| 47 | cdata = p; | ||
| 48 | pos = cdata->pos; | ||
| 49 | addr = cdata->tbl[pos].addr; | ||
| 50 | data = cdata->tbl[pos].data; | ||
| 51 | |||
| 52 | seq_printf(m, | ||
| 53 | "%d\t0x%08lx\t%05lx\t%s\t%c\t%c\t%c\t%c\n", | ||
| 54 | (int)pos, addr, data, strpage(data), | ||
| 55 | (data & CPLB_USER_RD) ? 'Y' : 'N', | ||
| 56 | (data & CPLB_USER_WR) ? 'Y' : 'N', | ||
| 57 | (data & CPLB_SUPV_WR) ? 'Y' : 'N', | ||
| 58 | pos < cdata->switched ? 'N' : 'Y'); | ||
| 59 | |||
| 60 | return 0; | ||
| 61 | } | ||
| 62 | |||
| 63 | static void cplbinfo_seq_init(struct cplbinfo_data *cdata, unsigned int cpu) | ||
| 64 | { | ||
| 65 | if (cdata->cplb_type == 'I') { | ||
| 66 | cdata->mem_control = bfin_read_IMEM_CONTROL(); | ||
| 67 | cdata->tbl = icplb_tbl[cpu]; | ||
| 68 | cdata->switched = first_switched_icplb; | ||
| 69 | } else { | ||
| 70 | cdata->mem_control = bfin_read_DMEM_CONTROL(); | ||
| 71 | cdata->tbl = dcplb_tbl[cpu]; | ||
| 72 | cdata->switched = first_switched_dcplb; | ||
| 73 | } | ||
| 74 | } | ||
| 75 | |||
| 76 | static void *cplbinfo_start(struct seq_file *m, loff_t *pos) | ||
| 77 | { | ||
| 78 | struct cplbinfo_data *cdata = m->private; | ||
| 79 | |||
| 80 | if (!*pos) { | ||
| 81 | seq_printf(m, "%cCPLBs are %sabled: 0x%x\n", cdata->cplb_type, | ||
| 82 | (cdata->mem_control & ENDCPLB ? "en" : "dis"), | ||
| 83 | cdata->mem_control); | ||
| 84 | cplbinfo_print_header(m); | ||
| 85 | } else if (cplbinfo_nomore(cdata)) | ||
| 86 | return NULL; | ||
| 87 | |||
| 88 | get_cpu(); | ||
| 89 | return cdata; | ||
| 90 | } | ||
| 91 | |||
| 92 | static void *cplbinfo_next(struct seq_file *m, void *p, loff_t *pos) | ||
| 93 | { | ||
| 94 | struct cplbinfo_data *cdata = p; | ||
| 95 | cdata->pos = ++(*pos); | ||
| 96 | if (cplbinfo_nomore(cdata)) | ||
| 97 | return NULL; | ||
| 98 | else | ||
| 99 | return cdata; | ||
| 100 | } | ||
| 101 | |||
| 102 | static void cplbinfo_stop(struct seq_file *m, void *p) | ||
| 103 | { | ||
| 104 | put_cpu(); | ||
| 105 | } | ||
| 106 | |||
| 107 | static const struct seq_operations cplbinfo_sops = { | ||
| 108 | .start = cplbinfo_start, | ||
| 109 | .next = cplbinfo_next, | ||
| 110 | .stop = cplbinfo_stop, | ||
| 111 | .show = cplbinfo_show, | ||
| 112 | }; | ||
| 113 | |||
| 114 | static int cplbinfo_open(struct inode *inode, struct file *file) | ||
| 115 | { | ||
| 116 | char buf[256], *path, *p; | ||
| 117 | unsigned int cpu; | ||
| 118 | char *s_cpu, *s_cplb; | ||
| 119 | int ret; | ||
| 120 | struct seq_file *m; | ||
| 121 | struct cplbinfo_data *cdata; | ||
| 122 | |||
| 123 | path = d_path(&file->f_path, buf, sizeof(buf)); | ||
| 124 | if (IS_ERR(path)) | ||
| 125 | return PTR_ERR(path); | ||
| 126 | s_cpu = strstr(path, "/cpu"); | ||
| 127 | s_cplb = strrchr(path, '/'); | ||
| 128 | if (!s_cpu || !s_cplb) | ||
| 129 | return -EINVAL; | ||
| 130 | |||
| 131 | cpu = simple_strtoul(s_cpu + 4, &p, 10); | ||
| 132 | if (!cpu_online(cpu)) | ||
| 133 | return -ENODEV; | ||
| 134 | |||
| 135 | ret = seq_open_private(file, &cplbinfo_sops, sizeof(*cdata)); | ||
| 136 | if (ret) | ||
| 137 | return ret; | ||
| 138 | m = file->private_data; | ||
| 139 | cdata = m->private; | ||
| 140 | |||
| 141 | cdata->pos = 0; | ||
| 142 | cdata->cplb_type = toupper(s_cplb[1]); | ||
| 143 | cplbinfo_seq_init(cdata, cpu); | ||
| 144 | |||
| 145 | return 0; | ||
| 146 | } | ||
| 147 | |||
| 148 | static const struct file_operations cplbinfo_fops = { | ||
| 149 | .open = cplbinfo_open, | ||
| 150 | .read = seq_read, | ||
| 151 | .llseek = seq_lseek, | ||
| 152 | .release = seq_release_private, | ||
| 153 | }; | ||
| 154 | |||
| 155 | static int __init cplbinfo_init(void) | ||
| 156 | { | ||
| 157 | struct proc_dir_entry *cplb_dir, *cpu_dir; | ||
| 158 | char buf[10]; | ||
| 159 | unsigned int cpu; | ||
| 160 | |||
| 161 | cplb_dir = proc_mkdir("cplbinfo", NULL); | ||
| 162 | if (!cplb_dir) | ||
| 163 | return -ENOMEM; | ||
| 164 | |||
| 165 | for_each_possible_cpu(cpu) { | ||
| 166 | sprintf(buf, "cpu%i", cpu); | ||
| 167 | cpu_dir = proc_mkdir(buf, cplb_dir); | ||
| 168 | if (!cpu_dir) | ||
| 169 | return -ENOMEM; | ||
| 170 | |||
| 171 | proc_create("icplb", S_IRUGO, cpu_dir, &cplbinfo_fops); | ||
| 172 | proc_create("dcplb", S_IRUGO, cpu_dir, &cplbinfo_fops); | ||
| 173 | } | ||
| 174 | |||
| 175 | return 0; | ||
| 176 | } | ||
| 177 | late_initcall(cplbinfo_init); | ||
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c index 1f4e3d2e0901..c8ad051742e2 100644 --- a/arch/blackfin/kernel/early_printk.c +++ b/arch/blackfin/kernel/early_printk.c | |||
| @@ -105,10 +105,10 @@ static struct console * __init earlyserial_init(char *buf) | |||
| 105 | cflag |= CS5; | 105 | cflag |= CS5; |
| 106 | break; | 106 | break; |
| 107 | case 6: | 107 | case 6: |
| 108 | cflag |= CS5; | 108 | cflag |= CS6; |
| 109 | break; | 109 | break; |
| 110 | case 7: | 110 | case 7: |
| 111 | cflag |= CS5; | 111 | cflag |= CS7; |
| 112 | break; | 112 | break; |
| 113 | default: | 113 | default: |
| 114 | cflag |= CS8; | 114 | cflag |= CS8; |
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S index faea88ebb2ef..a9cfba9946b5 100644 --- a/arch/blackfin/kernel/entry.S +++ b/arch/blackfin/kernel/entry.S | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <linux/linkage.h> | 30 | #include <linux/linkage.h> |
| 31 | #include <asm/thread_info.h> | 31 | #include <asm/thread_info.h> |
| 32 | #include <asm/errno.h> | 32 | #include <asm/errno.h> |
| 33 | #include <asm/blackfin.h> | ||
| 33 | #include <asm/asm-offsets.h> | 34 | #include <asm/asm-offsets.h> |
| 34 | 35 | ||
| 35 | #include <asm/context.S> | 36 | #include <asm/context.S> |
| @@ -41,6 +42,10 @@ | |||
| 41 | #endif | 42 | #endif |
| 42 | 43 | ||
| 43 | ENTRY(_ret_from_fork) | 44 | ENTRY(_ret_from_fork) |
| 45 | #ifdef CONFIG_IPIPE | ||
| 46 | [--sp] = reti; /* IRQs on. */ | ||
| 47 | SP += 4; | ||
| 48 | #endif /* CONFIG_IPIPE */ | ||
| 44 | SP += -12; | 49 | SP += -12; |
| 45 | call _schedule_tail; | 50 | call _schedule_tail; |
| 46 | SP += 12; | 51 | SP += 12; |
diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S index 4b03ba025488..0d2d9e0968c8 100644 --- a/arch/blackfin/kernel/fixed_code.S +++ b/arch/blackfin/kernel/fixed_code.S | |||
| @@ -8,10 +8,12 @@ | |||
| 8 | * BF561 SMP). | 8 | * BF561 SMP). |
| 9 | */ | 9 | */ |
| 10 | #include <linux/linkage.h> | 10 | #include <linux/linkage.h> |
| 11 | #include <linux/init.h> | ||
| 11 | #include <linux/unistd.h> | 12 | #include <linux/unistd.h> |
| 12 | #include <asm/entry.h> | 13 | #include <asm/entry.h> |
| 13 | 14 | ||
| 14 | .text | 15 | __INIT |
| 16 | |||
| 15 | ENTRY(_fixed_code_start) | 17 | ENTRY(_fixed_code_start) |
| 16 | 18 | ||
| 17 | .align 16 | 19 | .align 16 |
| @@ -144,3 +146,5 @@ ENTRY(_safe_user_instruction) | |||
| 144 | ENDPROC(_safe_user_instruction) | 146 | ENDPROC(_safe_user_instruction) |
| 145 | 147 | ||
| 146 | ENTRY(_fixed_code_end) | 148 | ENTRY(_fixed_code_end) |
| 149 | |||
| 150 | __FINIT | ||
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c new file mode 100644 index 000000000000..339be5a3ae6a --- /dev/null +++ b/arch/blackfin/kernel/ipipe.c | |||
| @@ -0,0 +1,428 @@ | |||
| 1 | /* -*- linux-c -*- | ||
| 2 | * linux/arch/blackfin/kernel/ipipe.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2007 Philippe Gerum. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, | ||
| 9 | * USA; either version 2 of the License, or (at your option) any later | ||
| 10 | * version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 20 | * | ||
| 21 | * Architecture-dependent I-pipe support for the Blackfin. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/sched.h> | ||
| 26 | #include <linux/module.h> | ||
| 27 | #include <linux/interrupt.h> | ||
| 28 | #include <linux/percpu.h> | ||
| 29 | #include <linux/bitops.h> | ||
| 30 | #include <linux/slab.h> | ||
| 31 | #include <linux/errno.h> | ||
| 32 | #include <linux/kthread.h> | ||
| 33 | #include <asm/unistd.h> | ||
| 34 | #include <asm/system.h> | ||
| 35 | #include <asm/atomic.h> | ||
| 36 | #include <asm/io.h> | ||
| 37 | |||
| 38 | static int create_irq_threads; | ||
| 39 | |||
| 40 | DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); | ||
| 41 | |||
| 42 | static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask); | ||
| 43 | |||
| 44 | static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count); | ||
| 45 | |||
| 46 | asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); | ||
| 47 | |||
| 48 | static void __ipipe_no_irqtail(void); | ||
| 49 | |||
| 50 | unsigned long __ipipe_irq_tail_hook = (unsigned long)&__ipipe_no_irqtail; | ||
| 51 | EXPORT_SYMBOL(__ipipe_irq_tail_hook); | ||
| 52 | |||
| 53 | unsigned long __ipipe_core_clock; | ||
| 54 | EXPORT_SYMBOL(__ipipe_core_clock); | ||
| 55 | |||
| 56 | unsigned long __ipipe_freq_scale; | ||
| 57 | EXPORT_SYMBOL(__ipipe_freq_scale); | ||
| 58 | |||
| 59 | atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; | ||
| 60 | |||
| 61 | unsigned long __ipipe_irq_lvmask = __all_masked_irq_flags; | ||
| 62 | EXPORT_SYMBOL(__ipipe_irq_lvmask); | ||
| 63 | |||
| 64 | static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc) | ||
| 65 | { | ||
| 66 | desc->ipipe_ack(irq, desc); | ||
| 67 | } | ||
| 68 | |||
| 69 | /* | ||
| 70 | * __ipipe_enable_pipeline() -- We are running on the boot CPU, hw | ||
| 71 | * interrupts are off, and secondary CPUs are still lost in space. | ||
| 72 | */ | ||
| 73 | void __ipipe_enable_pipeline(void) | ||
| 74 | { | ||
| 75 | unsigned irq; | ||
| 76 | |||
| 77 | __ipipe_core_clock = get_cclk(); /* Fetch this once. */ | ||
| 78 | __ipipe_freq_scale = 1000000000UL / __ipipe_core_clock; | ||
| 79 | |||
| 80 | for (irq = 0; irq < NR_IRQS; ++irq) | ||
| 81 | ipipe_virtualize_irq(ipipe_root_domain, | ||
| 82 | irq, | ||
| 83 | (ipipe_irq_handler_t)&asm_do_IRQ, | ||
| 84 | NULL, | ||
| 85 | &__ipipe_ack_irq, | ||
| 86 | IPIPE_HANDLE_MASK | IPIPE_PASS_MASK); | ||
| 87 | } | ||
| 88 | |||
| 89 | /* | ||
| 90 | * __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic | ||
| 91 | * interrupt protection log is maintained here for each domain. Hw | ||
| 92 | * interrupts are masked on entry. | ||
| 93 | */ | ||
| 94 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | ||
| 95 | { | ||
| 96 | struct ipipe_domain *this_domain, *next_domain; | ||
| 97 | struct list_head *head, *pos; | ||
| 98 | int m_ack, s = -1; | ||
| 99 | |||
| 100 | /* | ||
| 101 | * Software-triggered IRQs do not need any ack. The contents | ||
| 102 | * of the register frame should only be used when processing | ||
| 103 | * the timer interrupt, but not for handling any other | ||
| 104 | * interrupt. | ||
| 105 | */ | ||
| 106 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); | ||
| 107 | |||
| 108 | this_domain = ipipe_current_domain; | ||
| 109 | |||
| 110 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) | ||
| 111 | head = &this_domain->p_link; | ||
| 112 | else { | ||
| 113 | head = __ipipe_pipeline.next; | ||
| 114 | next_domain = list_entry(head, struct ipipe_domain, p_link); | ||
| 115 | if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { | ||
| 116 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) | ||
| 117 | next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); | ||
| 118 | if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) | ||
| 119 | s = __test_and_set_bit(IPIPE_STALL_FLAG, | ||
| 120 | &ipipe_root_cpudom_var(status)); | ||
| 121 | __ipipe_dispatch_wired(next_domain, irq); | ||
| 122 | goto finalize; | ||
| 123 | return; | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | /* Ack the interrupt. */ | ||
| 128 | |||
| 129 | pos = head; | ||
| 130 | |||
| 131 | while (pos != &__ipipe_pipeline) { | ||
| 132 | next_domain = list_entry(pos, struct ipipe_domain, p_link); | ||
| 133 | /* | ||
| 134 | * For each domain handling the incoming IRQ, mark it | ||
| 135 | * as pending in its log. | ||
| 136 | */ | ||
| 137 | if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { | ||
| 138 | /* | ||
| 139 | * Domains that handle this IRQ are polled for | ||
| 140 | * acknowledging it by decreasing priority | ||
| 141 | * order. The interrupt must be made pending | ||
| 142 | * _first_ in the domain's status flags before | ||
| 143 | * the PIC is unlocked. | ||
| 144 | */ | ||
| 145 | __ipipe_set_irq_pending(next_domain, irq); | ||
| 146 | |||
| 147 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { | ||
| 148 | next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); | ||
| 149 | m_ack = 1; | ||
| 150 | } | ||
| 151 | } | ||
| 152 | |||
| 153 | /* | ||
| 154 | * If the domain does not want the IRQ to be passed | ||
| 155 | * down the interrupt pipe, exit the loop now. | ||
| 156 | */ | ||
| 157 | if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) | ||
| 158 | break; | ||
| 159 | |||
| 160 | pos = next_domain->p_link.next; | ||
| 161 | } | ||
| 162 | |||
| 163 | /* | ||
| 164 | * Now walk the pipeline, yielding control to the highest | ||
| 165 | * priority domain that has pending interrupt(s) or | ||
| 166 | * immediately to the current domain if the interrupt has been | ||
| 167 | * marked as 'sticky'. This search does not go beyond the | ||
| 168 | * current domain in the pipeline. We also enforce the | ||
| 169 | * additional root stage lock (blackfin-specific). */ | ||
| 170 | |||
| 171 | if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) | ||
| 172 | s = __test_and_set_bit(IPIPE_STALL_FLAG, | ||
| 173 | &ipipe_root_cpudom_var(status)); | ||
| 174 | finalize: | ||
| 175 | |||
| 176 | __ipipe_walk_pipeline(head); | ||
| 177 | |||
| 178 | if (!s) | ||
| 179 | __clear_bit(IPIPE_STALL_FLAG, | ||
| 180 | &ipipe_root_cpudom_var(status)); | ||
| 181 | } | ||
| 182 | |||
| 183 | int __ipipe_check_root(void) | ||
| 184 | { | ||
| 185 | return ipipe_root_domain_p; | ||
| 186 | } | ||
| 187 | |||
| 188 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | ||
| 189 | { | ||
| 190 | struct irq_desc *desc = irq_desc + irq; | ||
| 191 | int prio = desc->ic_prio; | ||
| 192 | |||
| 193 | desc->depth = 0; | ||
| 194 | if (ipd != &ipipe_root && | ||
| 195 | atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1) | ||
| 196 | __set_bit(prio, &__ipipe_irq_lvmask); | ||
| 197 | } | ||
| 198 | EXPORT_SYMBOL(__ipipe_enable_irqdesc); | ||
| 199 | |||
| 200 | void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | ||
| 201 | { | ||
| 202 | struct irq_desc *desc = irq_desc + irq; | ||
| 203 | int prio = desc->ic_prio; | ||
| 204 | |||
| 205 | if (ipd != &ipipe_root && | ||
| 206 | atomic_dec_and_test(&__ipipe_irq_lvdepth[prio])) | ||
| 207 | __clear_bit(prio, &__ipipe_irq_lvmask); | ||
| 208 | } | ||
| 209 | EXPORT_SYMBOL(__ipipe_disable_irqdesc); | ||
| 210 | |||
| 211 | void __ipipe_stall_root_raw(void) | ||
| 212 | { | ||
| 213 | /* | ||
| 214 | * This code is called by the ins{bwl} routines (see | ||
| 215 | * arch/blackfin/lib/ins.S), which are heavily used by the | ||
| 216 | * network stack. It masks all interrupts but those handled by | ||
| 217 | * non-root domains, so that we keep decent network transfer | ||
| 218 | * rates for Linux without inducing pathological jitter for | ||
| 219 | * the real-time domain. | ||
| 220 | */ | ||
| 221 | __asm__ __volatile__ ("sti %0;" : : "d"(__ipipe_irq_lvmask)); | ||
| 222 | |||
| 223 | __set_bit(IPIPE_STALL_FLAG, | ||
| 224 | &ipipe_root_cpudom_var(status)); | ||
| 225 | } | ||
| 226 | |||
| 227 | void __ipipe_unstall_root_raw(void) | ||
| 228 | { | ||
| 229 | __clear_bit(IPIPE_STALL_FLAG, | ||
| 230 | &ipipe_root_cpudom_var(status)); | ||
| 231 | |||
| 232 | __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags)); | ||
| 233 | } | ||
| 234 | |||
| 235 | int __ipipe_syscall_root(struct pt_regs *regs) | ||
| 236 | { | ||
| 237 | unsigned long flags; | ||
| 238 | |||
| 239 | /* We need to run the IRQ tail hook whenever we don't | ||
| 240 | * propagate a syscall to higher domains, because we know that | ||
| 241 | * important operations might be pending there (e.g. Xenomai | ||
| 242 | * deferred rescheduling). */ | ||
| 243 | |||
| 244 | if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) { | ||
| 245 | void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; | ||
| 246 | hook(); | ||
| 247 | return 0; | ||
| 248 | } | ||
| 249 | |||
| 250 | /* | ||
| 251 | * This routine either returns: | ||
| 252 | * 0 -- if the syscall is to be passed to Linux; | ||
| 253 | * 1 -- if the syscall should not be passed to Linux, and no | ||
| 254 | * tail work should be performed; | ||
| 255 | * -1 -- if the syscall should not be passed to Linux but the | ||
| 256 | * tail work has to be performed (for handling signals etc). | ||
| 257 | */ | ||
| 258 | |||
| 259 | if (__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL) && | ||
| 260 | __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs) > 0) { | ||
| 261 | if (ipipe_root_domain_p && !in_atomic()) { | ||
| 262 | /* | ||
| 263 | * Sync pending VIRQs before _TIF_NEED_RESCHED | ||
| 264 | * is tested. | ||
| 265 | */ | ||
| 266 | local_irq_save_hw(flags); | ||
| 267 | if ((ipipe_root_cpudom_var(irqpend_himask) & IPIPE_IRQMASK_VIRT) != 0) | ||
| 268 | __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT); | ||
| 269 | local_irq_restore_hw(flags); | ||
| 270 | return -1; | ||
| 271 | } | ||
| 272 | return 1; | ||
| 273 | } | ||
| 274 | |||
| 275 | return 0; | ||
| 276 | } | ||
| 277 | |||
| 278 | unsigned long ipipe_critical_enter(void (*syncfn) (void)) | ||
| 279 | { | ||
| 280 | unsigned long flags; | ||
| 281 | |||
| 282 | local_irq_save_hw(flags); | ||
| 283 | |||
| 284 | return flags; | ||
| 285 | } | ||
| 286 | |||
| 287 | void ipipe_critical_exit(unsigned long flags) | ||
| 288 | { | ||
| 289 | local_irq_restore_hw(flags); | ||
| 290 | } | ||
| 291 | |||
| 292 | static void __ipipe_no_irqtail(void) | ||
| 293 | { | ||
| 294 | } | ||
| 295 | |||
| 296 | int ipipe_get_sysinfo(struct ipipe_sysinfo *info) | ||
| 297 | { | ||
| 298 | info->ncpus = num_online_cpus(); | ||
| 299 | info->cpufreq = ipipe_cpu_freq(); | ||
| 300 | info->archdep.tmirq = IPIPE_TIMER_IRQ; | ||
| 301 | info->archdep.tmfreq = info->cpufreq; | ||
| 302 | |||
| 303 | return 0; | ||
| 304 | } | ||
| 305 | |||
| 306 | /* | ||
| 307 | * ipipe_trigger_irq() -- Push the interrupt at front of the pipeline | ||
| 308 | * just like if it has been actually received from a hw source. Also | ||
| 309 | * works for virtual interrupts. | ||
| 310 | */ | ||
| 311 | int ipipe_trigger_irq(unsigned irq) | ||
| 312 | { | ||
| 313 | unsigned long flags; | ||
| 314 | |||
| 315 | if (irq >= IPIPE_NR_IRQS || | ||
| 316 | (ipipe_virtual_irq_p(irq) | ||
| 317 | && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) | ||
| 318 | return -EINVAL; | ||
| 319 | |||
| 320 | local_irq_save_hw(flags); | ||
| 321 | |||
| 322 | __ipipe_handle_irq(irq, NULL); | ||
| 323 | |||
| 324 | local_irq_restore_hw(flags); | ||
| 325 | |||
| 326 | return 1; | ||
| 327 | } | ||
| 328 | |||
| 329 | /* Move Linux IRQ to threads. */ | ||
| 330 | |||
| 331 | static int do_irqd(void *__desc) | ||
| 332 | { | ||
| 333 | struct irq_desc *desc = __desc; | ||
| 334 | unsigned irq = desc - irq_desc; | ||
| 335 | int thrprio = desc->thr_prio; | ||
| 336 | int thrmask = 1 << thrprio; | ||
| 337 | int cpu = smp_processor_id(); | ||
| 338 | cpumask_t cpumask; | ||
| 339 | |||
| 340 | sigfillset(¤t->blocked); | ||
| 341 | current->flags |= PF_NOFREEZE; | ||
| 342 | cpumask = cpumask_of_cpu(cpu); | ||
| 343 | set_cpus_allowed(current, cpumask); | ||
| 344 | ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio); | ||
| 345 | |||
| 346 | while (!kthread_should_stop()) { | ||
| 347 | local_irq_disable(); | ||
| 348 | if (!(desc->status & IRQ_SCHEDULED)) { | ||
| 349 | set_current_state(TASK_INTERRUPTIBLE); | ||
| 350 | resched: | ||
| 351 | local_irq_enable(); | ||
| 352 | schedule(); | ||
| 353 | local_irq_disable(); | ||
| 354 | } | ||
| 355 | __set_current_state(TASK_RUNNING); | ||
| 356 | /* | ||
| 357 | * If higher priority interrupt servers are ready to | ||
| 358 | * run, reschedule immediately. We need this for the | ||
| 359 | * GPIO demux IRQ handler to unmask the interrupt line | ||
| 360 | * _last_, after all GPIO IRQs have run. | ||
| 361 | */ | ||
| 362 | if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1))) | ||
| 363 | goto resched; | ||
| 364 | if (--per_cpu(pending_irq_count[thrprio], cpu) == 0) | ||
| 365 | per_cpu(pending_irqthread_mask, cpu) &= ~thrmask; | ||
| 366 | desc->status &= ~IRQ_SCHEDULED; | ||
| 367 | desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); | ||
| 368 | local_irq_enable(); | ||
| 369 | } | ||
| 370 | __set_current_state(TASK_RUNNING); | ||
| 371 | return 0; | ||
| 372 | } | ||
| 373 | |||
| 374 | static void kick_irqd(unsigned irq, void *cookie) | ||
| 375 | { | ||
| 376 | struct irq_desc *desc = irq_desc + irq; | ||
| 377 | int thrprio = desc->thr_prio; | ||
| 378 | int thrmask = 1 << thrprio; | ||
| 379 | int cpu = smp_processor_id(); | ||
| 380 | |||
| 381 | if (!(desc->status & IRQ_SCHEDULED)) { | ||
| 382 | desc->status |= IRQ_SCHEDULED; | ||
| 383 | per_cpu(pending_irqthread_mask, cpu) |= thrmask; | ||
| 384 | ++per_cpu(pending_irq_count[thrprio], cpu); | ||
| 385 | wake_up_process(desc->thread); | ||
| 386 | } | ||
| 387 | } | ||
| 388 | |||
| 389 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc) | ||
| 390 | { | ||
| 391 | if (desc->thread || !create_irq_threads) | ||
| 392 | return 0; | ||
| 393 | |||
| 394 | desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq); | ||
| 395 | if (desc->thread == NULL) { | ||
| 396 | printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq); | ||
| 397 | return -ENOMEM; | ||
| 398 | } | ||
| 399 | |||
| 400 | wake_up_process(desc->thread); | ||
| 401 | |||
| 402 | desc->thr_handler = ipipe_root_domain->irqs[irq].handler; | ||
| 403 | ipipe_root_domain->irqs[irq].handler = &kick_irqd; | ||
| 404 | |||
| 405 | return 0; | ||
| 406 | } | ||
| 407 | |||
| 408 | void __init ipipe_init_irq_threads(void) | ||
| 409 | { | ||
| 410 | unsigned irq; | ||
| 411 | struct irq_desc *desc; | ||
| 412 | |||
| 413 | create_irq_threads = 1; | ||
| 414 | |||
| 415 | for (irq = 0; irq < NR_IRQS; irq++) { | ||
| 416 | desc = irq_desc + irq; | ||
| 417 | if (desc->action != NULL || | ||
| 418 | (desc->status & IRQ_NOREQUEST) != 0) | ||
| 419 | ipipe_start_irq_thread(irq, desc); | ||
| 420 | } | ||
| 421 | } | ||
| 422 | |||
| 423 | EXPORT_SYMBOL(show_stack); | ||
| 424 | |||
| 425 | #ifdef CONFIG_IPIPE_TRACE_MCOUNT | ||
| 426 | void notrace _mcount(void); | ||
| 427 | EXPORT_SYMBOL(_mcount); | ||
| 428 | #endif /* CONFIG_IPIPE_TRACE_MCOUNT */ | ||
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 07402f57c9de..ab8209cbbad0 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c | |||
| @@ -36,7 +36,7 @@ | |||
| 36 | #include <linux/irq.h> | 36 | #include <linux/irq.h> |
| 37 | #include <asm/trace.h> | 37 | #include <asm/trace.h> |
| 38 | 38 | ||
| 39 | static unsigned long irq_err_count; | 39 | static atomic_t irq_err_count; |
| 40 | static spinlock_t irq_controller_lock; | 40 | static spinlock_t irq_controller_lock; |
| 41 | 41 | ||
| 42 | /* | 42 | /* |
| @@ -48,10 +48,9 @@ void dummy_mask_unmask_irq(unsigned int irq) | |||
| 48 | 48 | ||
| 49 | void ack_bad_irq(unsigned int irq) | 49 | void ack_bad_irq(unsigned int irq) |
| 50 | { | 50 | { |
| 51 | irq_err_count += 1; | 51 | atomic_inc(&irq_err_count); |
| 52 | printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); | 52 | printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); |
| 53 | } | 53 | } |
| 54 | EXPORT_SYMBOL(ack_bad_irq); | ||
| 55 | 54 | ||
| 56 | static struct irq_chip bad_chip = { | 55 | static struct irq_chip bad_chip = { |
| 57 | .ack = dummy_mask_unmask_irq, | 56 | .ack = dummy_mask_unmask_irq, |
| @@ -72,7 +71,7 @@ static struct irq_desc bad_irq_desc = { | |||
| 72 | 71 | ||
| 73 | int show_interrupts(struct seq_file *p, void *v) | 72 | int show_interrupts(struct seq_file *p, void *v) |
| 74 | { | 73 | { |
| 75 | int i = *(loff_t *) v; | 74 | int i = *(loff_t *) v, j; |
| 76 | struct irqaction *action; | 75 | struct irqaction *action; |
| 77 | unsigned long flags; | 76 | unsigned long flags; |
| 78 | 77 | ||
| @@ -80,19 +79,20 @@ int show_interrupts(struct seq_file *p, void *v) | |||
| 80 | spin_lock_irqsave(&irq_desc[i].lock, flags); | 79 | spin_lock_irqsave(&irq_desc[i].lock, flags); |
| 81 | action = irq_desc[i].action; | 80 | action = irq_desc[i].action; |
| 82 | if (!action) | 81 | if (!action) |
| 83 | goto unlock; | 82 | goto skip; |
| 84 | 83 | seq_printf(p, "%3d: ", i); | |
| 85 | seq_printf(p, "%3d: %10u ", i, kstat_irqs(i)); | 84 | for_each_online_cpu(j) |
| 85 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | ||
| 86 | seq_printf(p, " %8s", irq_desc[i].chip->name); | ||
| 86 | seq_printf(p, " %s", action->name); | 87 | seq_printf(p, " %s", action->name); |
| 87 | for (action = action->next; action; action = action->next) | 88 | for (action = action->next; action; action = action->next) |
| 88 | seq_printf(p, ", %s", action->name); | 89 | seq_printf(p, " %s", action->name); |
| 89 | 90 | ||
| 90 | seq_putc(p, '\n'); | 91 | seq_putc(p, '\n'); |
| 91 | unlock: | 92 | skip: |
| 92 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | 93 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); |
| 93 | } else if (i == NR_IRQS) { | 94 | } else if (i == NR_IRQS) |
| 94 | seq_printf(p, "Err: %10lu\n", irq_err_count); | 95 | seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count)); |
| 95 | } | ||
| 96 | return 0; | 96 | return 0; |
| 97 | } | 97 | } |
| 98 | 98 | ||
| @@ -101,7 +101,6 @@ int show_interrupts(struct seq_file *p, void *v) | |||
| 101 | * come via this function. Instead, they should provide their | 101 | * come via this function. Instead, they should provide their |
| 102 | * own 'handler' | 102 | * own 'handler' |
| 103 | */ | 103 | */ |
| 104 | |||
| 105 | #ifdef CONFIG_DO_IRQ_L1 | 104 | #ifdef CONFIG_DO_IRQ_L1 |
| 106 | __attribute__((l1_text)) | 105 | __attribute__((l1_text)) |
| 107 | #endif | 106 | #endif |
| @@ -109,8 +108,9 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |||
| 109 | { | 108 | { |
| 110 | struct pt_regs *old_regs; | 109 | struct pt_regs *old_regs; |
| 111 | struct irq_desc *desc = irq_desc + irq; | 110 | struct irq_desc *desc = irq_desc + irq; |
| 111 | #ifndef CONFIG_IPIPE | ||
| 112 | unsigned short pending, other_ints; | 112 | unsigned short pending, other_ints; |
| 113 | 113 | #endif | |
| 114 | old_regs = set_irq_regs(regs); | 114 | old_regs = set_irq_regs(regs); |
| 115 | 115 | ||
| 116 | /* | 116 | /* |
| @@ -121,9 +121,24 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |||
| 121 | desc = &bad_irq_desc; | 121 | desc = &bad_irq_desc; |
| 122 | 122 | ||
| 123 | irq_enter(); | 123 | irq_enter(); |
| 124 | 124 | #ifdef CONFIG_DEBUG_STACKOVERFLOW | |
| 125 | /* Debugging check for stack overflow: is there less than STACK_WARN free? */ | ||
| 126 | { | ||
| 127 | long sp; | ||
| 128 | |||
| 129 | sp = __get_SP() & (THREAD_SIZE-1); | ||
| 130 | |||
| 131 | if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { | ||
| 132 | dump_stack(); | ||
| 133 | printk(KERN_EMERG "%s: possible stack overflow while handling irq %i " | ||
| 134 | " only %ld bytes free\n", | ||
| 135 | __func__, irq, sp - sizeof(struct thread_info)); | ||
| 136 | } | ||
| 137 | } | ||
| 138 | #endif | ||
| 125 | generic_handle_irq(irq); | 139 | generic_handle_irq(irq); |
| 126 | 140 | ||
| 141 | #ifndef CONFIG_IPIPE /* Useless and bugous over the I-pipe: IRQs are threaded. */ | ||
| 127 | /* If we're the only interrupt running (ignoring IRQ15 which is for | 142 | /* If we're the only interrupt running (ignoring IRQ15 which is for |
| 128 | syscalls), lower our priority to IRQ14 so that softirqs run at | 143 | syscalls), lower our priority to IRQ14 so that softirqs run at |
| 129 | that level. If there's another, lower-level interrupt, irq_exit | 144 | that level. If there's another, lower-level interrupt, irq_exit |
| @@ -133,6 +148,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |||
| 133 | other_ints = pending & (pending - 1); | 148 | other_ints = pending & (pending - 1); |
| 134 | if (other_ints == 0) | 149 | if (other_ints == 0) |
| 135 | lower_to_irq14(); | 150 | lower_to_irq14(); |
| 151 | #endif /* !CONFIG_IPIPE */ | ||
| 136 | irq_exit(); | 152 | irq_exit(); |
| 137 | 153 | ||
| 138 | set_irq_regs(old_regs); | 154 | set_irq_regs(old_regs); |
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index 1c5afaeb9504..b163f6d3330d 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c | |||
| @@ -34,9 +34,14 @@ int gdb_bfin_vector = -1; | |||
| 34 | #error change the definition of slavecpulocks | 34 | #error change the definition of slavecpulocks |
| 35 | #endif | 35 | #endif |
| 36 | 36 | ||
| 37 | #ifdef CONFIG_BFIN_WDT | 37 | #define IN_MEM(addr, size, l1_addr, l1_size) \ |
| 38 | # error "Please unselect blackfin watchdog driver before build KGDB." | 38 | ({ \ |
| 39 | #endif | 39 | unsigned long __addr = (unsigned long)(addr); \ |
| 40 | (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \ | ||
| 41 | }) | ||
| 42 | #define ASYNC_BANK_SIZE \ | ||
| 43 | (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ | ||
| 44 | ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) | ||
| 40 | 45 | ||
| 41 | void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) | 46 | void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) |
| 42 | { | 47 | { |
| @@ -219,6 +224,7 @@ int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type) | |||
| 219 | if (bfin_type == breakinfo[breakno].type | 224 | if (bfin_type == breakinfo[breakno].type |
| 220 | && !breakinfo[breakno].occupied) { | 225 | && !breakinfo[breakno].occupied) { |
| 221 | breakinfo[breakno].occupied = 1; | 226 | breakinfo[breakno].occupied = 1; |
| 227 | breakinfo[breakno].skip = 0; | ||
| 222 | breakinfo[breakno].enabled = 1; | 228 | breakinfo[breakno].enabled = 1; |
| 223 | breakinfo[breakno].addr = addr; | 229 | breakinfo[breakno].addr = addr; |
| 224 | breakinfo[breakno].dataacc = dataacc; | 230 | breakinfo[breakno].dataacc = dataacc; |
| @@ -363,12 +369,12 @@ void kgdb_passive_cpu_callback(void *info) | |||
| 363 | 369 | ||
| 364 | void kgdb_roundup_cpus(unsigned long flags) | 370 | void kgdb_roundup_cpus(unsigned long flags) |
| 365 | { | 371 | { |
| 366 | smp_call_function(kgdb_passive_cpu_callback, NULL, 0, 0); | 372 | smp_call_function(kgdb_passive_cpu_callback, NULL, 0); |
| 367 | } | 373 | } |
| 368 | 374 | ||
| 369 | void kgdb_roundup_cpu(int cpu, unsigned long flags) | 375 | void kgdb_roundup_cpu(int cpu, unsigned long flags) |
| 370 | { | 376 | { |
| 371 | smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0, 0); | 377 | smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0); |
| 372 | } | 378 | } |
| 373 | #endif | 379 | #endif |
| 374 | 380 | ||
| @@ -385,10 +391,8 @@ int kgdb_arch_handle_exception(int vector, int signo, | |||
| 385 | struct pt_regs *regs) | 391 | struct pt_regs *regs) |
| 386 | { | 392 | { |
| 387 | long addr; | 393 | long addr; |
| 388 | long breakno; | ||
| 389 | char *ptr; | 394 | char *ptr; |
| 390 | int newPC; | 395 | int newPC; |
| 391 | int wp_status; | ||
| 392 | int i; | 396 | int i; |
| 393 | 397 | ||
| 394 | switch (remcom_in_buffer[0]) { | 398 | switch (remcom_in_buffer[0]) { |
| @@ -426,17 +430,6 @@ int kgdb_arch_handle_exception(int vector, int signo, | |||
| 426 | kgdb_single_step = i + 1; | 430 | kgdb_single_step = i + 1; |
| 427 | } | 431 | } |
| 428 | 432 | ||
| 429 | if (vector == VEC_WATCH) { | ||
| 430 | wp_status = bfin_read_WPSTAT(); | ||
| 431 | for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++) { | ||
| 432 | if (wp_status & (1 << breakno)) { | ||
| 433 | breakinfo->skip = 1; | ||
| 434 | break; | ||
| 435 | } | ||
| 436 | } | ||
| 437 | bfin_write_WPSTAT(0); | ||
| 438 | } | ||
| 439 | |||
| 440 | bfin_correct_hw_break(); | 433 | bfin_correct_hw_break(); |
| 441 | 434 | ||
| 442 | return 0; | 435 | return 0; |
| @@ -478,57 +471,32 @@ static int validate_memory_access_address(unsigned long addr, int size) | |||
| 478 | return 0; | 471 | return 0; |
| 479 | if (addr >= SYSMMR_BASE) | 472 | if (addr >= SYSMMR_BASE) |
| 480 | return 0; | 473 | return 0; |
| 481 | if (addr >= ASYNC_BANK0_BASE | 474 | if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE)) |
| 482 | && addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) | ||
| 483 | return 0; | 475 | return 0; |
| 484 | if (cpu == 0) { | 476 | if (cpu == 0) { |
| 485 | if (addr >= L1_SCRATCH_START | 477 | if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) |
| 486 | && (addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH)) | ||
| 487 | return 0; | 478 | return 0; |
| 488 | #if L1_CODE_LENGTH != 0 | 479 | if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH)) |
| 489 | if (addr >= L1_CODE_START | ||
| 490 | && (addr + size <= L1_CODE_START + L1_CODE_LENGTH)) | ||
| 491 | return 0; | 480 | return 0; |
| 492 | #endif | 481 | if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) |
| 493 | #if L1_DATA_A_LENGTH != 0 | ||
| 494 | if (addr >= L1_DATA_A_START | ||
| 495 | && (addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH)) | ||
| 496 | return 0; | 482 | return 0; |
| 497 | #endif | 483 | if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) |
| 498 | #if L1_DATA_B_LENGTH != 0 | ||
| 499 | if (addr >= L1_DATA_B_START | ||
| 500 | && (addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH)) | ||
| 501 | return 0; | 484 | return 0; |
| 502 | #endif | ||
| 503 | #ifdef CONFIG_SMP | 485 | #ifdef CONFIG_SMP |
| 504 | } else if (cpu == 1) { | 486 | } else if (cpu == 1) { |
| 505 | if (addr >= COREB_L1_SCRATCH_START | 487 | if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) |
| 506 | && (addr + size <= COREB_L1_SCRATCH_START | ||
| 507 | + L1_SCRATCH_LENGTH)) | ||
| 508 | return 0; | 488 | return 0; |
| 509 | # if L1_CODE_LENGTH != 0 | 489 | if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) |
| 510 | if (addr >= COREB_L1_CODE_START | ||
| 511 | && (addr + size <= COREB_L1_CODE_START + L1_CODE_LENGTH)) | ||
| 512 | return 0; | 490 | return 0; |
| 513 | # endif | 491 | if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) |
| 514 | # if L1_DATA_A_LENGTH != 0 | ||
| 515 | if (addr >= COREB_L1_DATA_A_START | ||
| 516 | && (addr + size <= COREB_L1_DATA_A_START + L1_DATA_A_LENGTH)) | ||
| 517 | return 0; | 492 | return 0; |
| 518 | # endif | 493 | if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) |
| 519 | # if L1_DATA_B_LENGTH != 0 | ||
| 520 | if (addr >= COREB_L1_DATA_B_START | ||
| 521 | && (addr + size <= COREB_L1_DATA_B_START + L1_DATA_B_LENGTH)) | ||
| 522 | return 0; | 494 | return 0; |
| 523 | # endif | ||
| 524 | #endif | 495 | #endif |
| 525 | } | 496 | } |
| 526 | 497 | ||
| 527 | #if L2_LENGTH != 0 | 498 | if (IN_MEM(addr, size, L2_START, L2_LENGTH)) |
| 528 | if (addr >= L2_START | ||
| 529 | && addr + size <= L2_START + L2_LENGTH) | ||
| 530 | return 0; | 499 | return 0; |
| 531 | #endif | ||
| 532 | 500 | ||
| 533 | return EFAULT; | 501 | return EFAULT; |
| 534 | } | 502 | } |
| @@ -582,12 +550,9 @@ int kgdb_mem2hex(char *mem, char *buf, int count) | |||
| 582 | default: | 550 | default: |
| 583 | err = EFAULT; | 551 | err = EFAULT; |
| 584 | } | 552 | } |
| 585 | } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START && | 553 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) |
| 586 | (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH | ||
| 587 | #ifdef CONFIG_SMP | 554 | #ifdef CONFIG_SMP |
| 588 | || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && | 555 | || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) |
| 589 | (unsigned int)(mem + count) <= | ||
| 590 | COREB_L1_CODE_START + L1_CODE_LENGTH | ||
| 591 | #endif | 556 | #endif |
| 592 | ) { | 557 | ) { |
| 593 | /* access L1 instruction SRAM*/ | 558 | /* access L1 instruction SRAM*/ |
| @@ -658,12 +623,9 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) | |||
| 658 | default: | 623 | default: |
| 659 | return EFAULT; | 624 | return EFAULT; |
| 660 | } | 625 | } |
| 661 | } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START && | 626 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) |
| 662 | (unsigned int)(mem + count) < L1_CODE_START + L1_CODE_LENGTH | ||
| 663 | #ifdef CONFIG_SMP | 627 | #ifdef CONFIG_SMP |
| 664 | || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && | 628 | || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) |
| 665 | (unsigned int)(mem + count) <= | ||
| 666 | COREB_L1_CODE_START + L1_CODE_LENGTH | ||
| 667 | #endif | 629 | #endif |
| 668 | ) { | 630 | ) { |
| 669 | /* access L1 instruction SRAM */ | 631 | /* access L1 instruction SRAM */ |
| @@ -723,12 +685,9 @@ int kgdb_hex2mem(char *buf, char *mem, int count) | |||
| 723 | default: | 685 | default: |
| 724 | return EFAULT; | 686 | return EFAULT; |
| 725 | } | 687 | } |
| 726 | } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START && | 688 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) |
| 727 | (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH | ||
| 728 | #ifdef CONFIG_SMP | 689 | #ifdef CONFIG_SMP |
| 729 | || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && | 690 | || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) |
| 730 | (unsigned int)(mem + count) <= | ||
| 731 | COREB_L1_CODE_START + L1_CODE_LENGTH | ||
| 732 | #endif | 691 | #endif |
| 733 | ) { | 692 | ) { |
| 734 | /* access L1 instruction SRAM */ | 693 | /* access L1 instruction SRAM */ |
| @@ -745,24 +704,16 @@ int kgdb_validate_break_address(unsigned long addr) | |||
| 745 | 704 | ||
| 746 | if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end) | 705 | if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end) |
| 747 | return 0; | 706 | return 0; |
| 748 | if (addr >= ASYNC_BANK0_BASE | 707 | if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE)) |
| 749 | && addr + BREAK_INSTR_SIZE <= ASYNC_BANK3_BASE + ASYNC_BANK3_BASE) | ||
| 750 | return 0; | 708 | return 0; |
| 751 | #if L1_CODE_LENGTH != 0 | 709 | if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) |
| 752 | if (cpu == 0 && addr >= L1_CODE_START | ||
| 753 | && addr + BREAK_INSTR_SIZE <= L1_CODE_START + L1_CODE_LENGTH) | ||
| 754 | return 0; | 710 | return 0; |
| 755 | # ifdef CONFIG_SMP | 711 | #ifdef CONFIG_SMP |
| 756 | else if (cpu == 1 && addr >= COREB_L1_CODE_START | 712 | else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH)) |
| 757 | && addr + BREAK_INSTR_SIZE <= COREB_L1_CODE_START + L1_CODE_LENGTH) | ||
| 758 | return 0; | 713 | return 0; |
| 759 | # endif | ||
| 760 | #endif | 714 | #endif |
| 761 | #if L2_LENGTH != 0 | 715 | if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH)) |
| 762 | if (addr >= L2_START | ||
| 763 | && addr + BREAK_INSTR_SIZE <= L2_START + L2_LENGTH) | ||
| 764 | return 0; | 716 | return 0; |
| 765 | #endif | ||
| 766 | 717 | ||
| 767 | return EFAULT; | 718 | return EFAULT; |
| 768 | } | 719 | } |
| @@ -772,13 +723,9 @@ int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) | |||
| 772 | int err; | 723 | int err; |
| 773 | int cpu = raw_smp_processor_id(); | 724 | int cpu = raw_smp_processor_id(); |
| 774 | 725 | ||
| 775 | if ((cpu == 0 && (unsigned int)addr >= L1_CODE_START | 726 | if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) |
| 776 | && (unsigned int)(addr + BREAK_INSTR_SIZE) | ||
| 777 | < L1_CODE_START + L1_CODE_LENGTH) | ||
| 778 | #ifdef CONFIG_SMP | 727 | #ifdef CONFIG_SMP |
| 779 | || (cpu == 1 && (unsigned int)addr >= COREB_L1_CODE_START | 728 | || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH)) |
| 780 | && (unsigned int)(addr + BREAK_INSTR_SIZE) | ||
| 781 | < COREB_L1_CODE_START + L1_CODE_LENGTH) | ||
| 782 | #endif | 729 | #endif |
| 783 | ) { | 730 | ) { |
| 784 | /* access L1 instruction SRAM */ | 731 | /* access L1 instruction SRAM */ |
| @@ -804,9 +751,7 @@ int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) | |||
| 804 | 751 | ||
| 805 | int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) | 752 | int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) |
| 806 | { | 753 | { |
| 807 | if ((unsigned int)addr >= L1_CODE_START && | 754 | if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) { |
| 808 | (unsigned int)(addr + BREAK_INSTR_SIZE) < | ||
| 809 | L1_CODE_START + L1_CODE_LENGTH) { | ||
| 810 | /* access L1 instruction SRAM */ | 755 | /* access L1 instruction SRAM */ |
| 811 | if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL) | 756 | if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL) |
| 812 | return -EFAULT; | 757 | return -EFAULT; |
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c new file mode 100644 index 000000000000..3dba9c17304a --- /dev/null +++ b/arch/blackfin/kernel/kgdb_test.c | |||
| @@ -0,0 +1,123 @@ | |||
| 1 | /* | ||
| 2 | * arch/blackfin/kernel/kgdb_test.c - Blackfin kgdb tests | ||
| 3 | * | ||
| 4 | * Copyright 2005-2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/proc_fs.h> | ||
| 13 | |||
| 14 | #include <asm/current.h> | ||
| 15 | #include <asm/uaccess.h> | ||
| 16 | #include <asm/system.h> | ||
| 17 | |||
| 18 | #include <asm/blackfin.h> | ||
| 19 | |||
| 20 | static char cmdline[256]; | ||
| 21 | static unsigned long len; | ||
| 22 | |||
| 23 | static int num1 __attribute__((l1_data)); | ||
| 24 | |||
| 25 | void kgdb_l1_test(void) __attribute__((l1_text)); | ||
| 26 | |||
| 27 | void kgdb_l1_test(void) | ||
| 28 | { | ||
| 29 | printk(KERN_ALERT "L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); | ||
| 30 | printk(KERN_ALERT "L1 : code function addr = 0x%p\n", kgdb_l1_test); | ||
| 31 | num1 = num1 + 10 ; | ||
| 32 | printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); | ||
| 33 | return ; | ||
| 34 | } | ||
| 35 | #if L2_LENGTH | ||
| 36 | |||
| 37 | static int num2 __attribute__((l2)); | ||
| 38 | void kgdb_l2_test(void) __attribute__((l2)); | ||
| 39 | |||
| 40 | void kgdb_l2_test(void) | ||
| 41 | { | ||
| 42 | printk(KERN_ALERT "L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); | ||
| 43 | printk(KERN_ALERT "L2 : code function addr = 0x%p\n", kgdb_l2_test); | ||
| 44 | num2 = num2 + 20 ; | ||
| 45 | printk(KERN_ALERT "L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); | ||
| 46 | return ; | ||
| 47 | } | ||
| 48 | |||
| 49 | #endif | ||
| 50 | |||
| 51 | |||
| 52 | int kgdb_test(char *name, int len, int count, int z) | ||
| 53 | { | ||
| 54 | printk(KERN_DEBUG "kgdb name(%d): %s, %d, %d\n", len, name, count, z); | ||
| 55 | count = z; | ||
| 56 | return count; | ||
| 57 | } | ||
| 58 | |||
| 59 | static int test_proc_output(char *buf) | ||
| 60 | { | ||
| 61 | kgdb_test("hello world!", 12, 0x55, 0x10); | ||
| 62 | kgdb_l1_test(); | ||
| 63 | #if L2_LENGTH | ||
| 64 | kgdb_l2_test(); | ||
| 65 | #endif | ||
| 66 | |||
| 67 | return 0; | ||
| 68 | } | ||
| 69 | |||
| 70 | static int test_read_proc(char *page, char **start, off_t off, | ||
| 71 | int count, int *eof, void *data) | ||
| 72 | { | ||
| 73 | int len; | ||
| 74 | |||
| 75 | len = test_proc_output(page); | ||
| 76 | if (len <= off+count) | ||
| 77 | *eof = 1; | ||
| 78 | *start = page + off; | ||
| 79 | len -= off; | ||
| 80 | if (len > count) | ||
| 81 | len = count; | ||
| 82 | if (len < 0) | ||
| 83 | len = 0; | ||
| 84 | return len; | ||
| 85 | } | ||
| 86 | |||
| 87 | static int test_write_proc(struct file *file, const char *buffer, | ||
| 88 | unsigned long count, void *data) | ||
| 89 | { | ||
| 90 | if (count >= 256) | ||
| 91 | len = 255; | ||
| 92 | else | ||
| 93 | len = count; | ||
| 94 | |||
| 95 | memcpy(cmdline, buffer, count); | ||
| 96 | cmdline[len] = 0; | ||
| 97 | |||
| 98 | return len; | ||
| 99 | } | ||
| 100 | |||
| 101 | static int __init kgdbtest_init(void) | ||
| 102 | { | ||
| 103 | struct proc_dir_entry *entry; | ||
| 104 | |||
| 105 | entry = create_proc_entry("kgdbtest", 0, NULL); | ||
| 106 | if (entry == NULL) | ||
| 107 | return -ENOMEM; | ||
| 108 | |||
| 109 | entry->read_proc = test_read_proc; | ||
| 110 | entry->write_proc = test_write_proc; | ||
| 111 | entry->data = NULL; | ||
| 112 | |||
| 113 | return 0; | ||
| 114 | } | ||
| 115 | |||
| 116 | static void __exit kgdbtest_exit(void) | ||
| 117 | { | ||
| 118 | remove_proc_entry("kgdbtest", NULL); | ||
| 119 | } | ||
| 120 | |||
| 121 | module_init(kgdbtest_init); | ||
| 122 | module_exit(kgdbtest_exit); | ||
| 123 | MODULE_LICENSE("GPL"); | ||
diff --git a/arch/blackfin/kernel/mcount.S b/arch/blackfin/kernel/mcount.S new file mode 100644 index 000000000000..edcfb3865f46 --- /dev/null +++ b/arch/blackfin/kernel/mcount.S | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/blackfin/mcount.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * 2007/04/12 Save index, length, modify and base registers. --rpm | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/linkage.h> | ||
| 10 | #include <asm/blackfin.h> | ||
| 11 | |||
| 12 | .text | ||
| 13 | |||
| 14 | .align 4 /* just in case */ | ||
| 15 | |||
| 16 | ENTRY(__mcount) | ||
| 17 | [--sp] = i0; | ||
| 18 | [--sp] = i1; | ||
| 19 | [--sp] = i2; | ||
| 20 | [--sp] = i3; | ||
| 21 | [--sp] = l0; | ||
| 22 | [--sp] = l1; | ||
| 23 | [--sp] = l2; | ||
| 24 | [--sp] = l3; | ||
| 25 | [--sp] = m0; | ||
| 26 | [--sp] = m1; | ||
| 27 | [--sp] = m2; | ||
| 28 | [--sp] = m3; | ||
| 29 | [--sp] = b0; | ||
| 30 | [--sp] = b1; | ||
| 31 | [--sp] = b2; | ||
| 32 | [--sp] = b3; | ||
| 33 | [--sp] = ( r7:0, p5:0 ); | ||
| 34 | [--sp] = ASTAT; | ||
| 35 | |||
| 36 | p1.L = _ipipe_trace_enable; | ||
| 37 | p1.H = _ipipe_trace_enable; | ||
| 38 | r7 = [p1]; | ||
| 39 | CC = r7 == 0; | ||
| 40 | if CC jump out; | ||
| 41 | link 0x10; | ||
| 42 | r0 = 0x0; | ||
| 43 | [sp + 0xc] = r0; /* v */ | ||
| 44 | r0 = 0x0; /* type: IPIPE_TRACE_FN */ | ||
| 45 | r1 = rets; | ||
| 46 | p0 = [fp]; /* p0: Prior FP */ | ||
| 47 | r2 = [p0 + 4]; /* r2: Prior RETS */ | ||
| 48 | call ___ipipe_trace; | ||
| 49 | unlink; | ||
| 50 | out: | ||
| 51 | ASTAT = [sp++]; | ||
| 52 | ( r7:0, p5:0 ) = [sp++]; | ||
| 53 | b3 = [sp++]; | ||
| 54 | b2 = [sp++]; | ||
| 55 | b1 = [sp++]; | ||
| 56 | b0 = [sp++]; | ||
| 57 | m3 = [sp++]; | ||
| 58 | m2 = [sp++]; | ||
| 59 | m1 = [sp++]; | ||
| 60 | m0 = [sp++]; | ||
| 61 | l3 = [sp++]; | ||
| 62 | l2 = [sp++]; | ||
| 63 | l1 = [sp++]; | ||
| 64 | l0 = [sp++]; | ||
| 65 | i3 = [sp++]; | ||
| 66 | i2 = [sp++]; | ||
| 67 | i1 = [sp++]; | ||
| 68 | i0 = [sp++]; | ||
| 69 | rts; | ||
| 70 | ENDPROC(__mcount) | ||
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c index e1bebc80a5bf..1bd7f2d018a8 100644 --- a/arch/blackfin/kernel/module.c +++ b/arch/blackfin/kernel/module.c | |||
| @@ -37,111 +37,6 @@ | |||
| 37 | #include <asm/dma.h> | 37 | #include <asm/dma.h> |
| 38 | #include <asm/cacheflush.h> | 38 | #include <asm/cacheflush.h> |
| 39 | 39 | ||
| 40 | /* | ||
| 41 | * handle arithmetic relocations. | ||
| 42 | * See binutils/bfd/elf32-bfin.c for more details | ||
| 43 | */ | ||
| 44 | #define RELOC_STACK_SIZE 100 | ||
| 45 | static uint32_t reloc_stack[RELOC_STACK_SIZE]; | ||
| 46 | static unsigned int reloc_stack_tos; | ||
| 47 | |||
| 48 | #define is_reloc_stack_empty() ((reloc_stack_tos > 0)?0:1) | ||
| 49 | |||
| 50 | static void reloc_stack_push(uint32_t value) | ||
| 51 | { | ||
| 52 | reloc_stack[reloc_stack_tos++] = value; | ||
| 53 | } | ||
| 54 | |||
| 55 | static uint32_t reloc_stack_pop(void) | ||
| 56 | { | ||
| 57 | return reloc_stack[--reloc_stack_tos]; | ||
| 58 | } | ||
| 59 | |||
| 60 | static uint32_t reloc_stack_operate(unsigned int oper, struct module *mod) | ||
| 61 | { | ||
| 62 | uint32_t value; | ||
| 63 | |||
| 64 | switch (oper) { | ||
| 65 | case R_add: | ||
| 66 | value = reloc_stack[reloc_stack_tos - 2] + | ||
| 67 | reloc_stack[reloc_stack_tos - 1]; | ||
| 68 | reloc_stack_tos -= 2; | ||
| 69 | break; | ||
| 70 | case R_sub: | ||
| 71 | value = reloc_stack[reloc_stack_tos - 2] - | ||
| 72 | reloc_stack[reloc_stack_tos - 1]; | ||
| 73 | reloc_stack_tos -= 2; | ||
| 74 | break; | ||
| 75 | case R_mult: | ||
| 76 | value = reloc_stack[reloc_stack_tos - 2] * | ||
| 77 | reloc_stack[reloc_stack_tos - 1]; | ||
| 78 | reloc_stack_tos -= 2; | ||
| 79 | break; | ||
| 80 | case R_div: | ||
| 81 | value = reloc_stack[reloc_stack_tos - 2] / | ||
| 82 | reloc_stack[reloc_stack_tos - 1]; | ||
| 83 | reloc_stack_tos -= 2; | ||
| 84 | break; | ||
| 85 | case R_mod: | ||
| 86 | value = reloc_stack[reloc_stack_tos - 2] % | ||
| 87 | reloc_stack[reloc_stack_tos - 1]; | ||
| 88 | reloc_stack_tos -= 2; | ||
| 89 | break; | ||
| 90 | case R_lshift: | ||
| 91 | value = reloc_stack[reloc_stack_tos - 2] << | ||
| 92 | reloc_stack[reloc_stack_tos - 1]; | ||
| 93 | reloc_stack_tos -= 2; | ||
| 94 | break; | ||
| 95 | case R_rshift: | ||
| 96 | value = reloc_stack[reloc_stack_tos - 2] >> | ||
| 97 | reloc_stack[reloc_stack_tos - 1]; | ||
| 98 | reloc_stack_tos -= 2; | ||
| 99 | break; | ||
| 100 | case R_and: | ||
| 101 | value = reloc_stack[reloc_stack_tos - 2] & | ||
| 102 | reloc_stack[reloc_stack_tos - 1]; | ||
| 103 | reloc_stack_tos -= 2; | ||
| 104 | break; | ||
| 105 | case R_or: | ||
| 106 | value = reloc_stack[reloc_stack_tos - 2] | | ||
| 107 | reloc_stack[reloc_stack_tos - 1]; | ||
| 108 | reloc_stack_tos -= 2; | ||
| 109 | break; | ||
| 110 | case R_xor: | ||
| 111 | value = reloc_stack[reloc_stack_tos - 2] ^ | ||
| 112 | reloc_stack[reloc_stack_tos - 1]; | ||
| 113 | reloc_stack_tos -= 2; | ||
| 114 | break; | ||
| 115 | case R_land: | ||
| 116 | value = reloc_stack[reloc_stack_tos - 2] && | ||
| 117 | reloc_stack[reloc_stack_tos - 1]; | ||
| 118 | reloc_stack_tos -= 2; | ||
| 119 | break; | ||
| 120 | case R_lor: | ||
| 121 | value = reloc_stack[reloc_stack_tos - 2] || | ||
| 122 | reloc_stack[reloc_stack_tos - 1]; | ||
| 123 | reloc_stack_tos -= 2; | ||
| 124 | break; | ||
| 125 | case R_neg: | ||
| 126 | value = -reloc_stack[reloc_stack_tos - 1]; | ||
| 127 | reloc_stack_tos--; | ||
| 128 | break; | ||
| 129 | case R_comp: | ||
| 130 | value = ~reloc_stack[reloc_stack_tos - 1]; | ||
| 131 | reloc_stack_tos -= 1; | ||
| 132 | break; | ||
| 133 | default: | ||
| 134 | printk(KERN_WARNING "module %s: unhandled reloction\n", | ||
| 135 | mod->name); | ||
| 136 | return 0; | ||
| 137 | } | ||
| 138 | |||
| 139 | /* now push the new value back on stack */ | ||
| 140 | reloc_stack_push(value); | ||
| 141 | |||
| 142 | return value; | ||
| 143 | } | ||
| 144 | |||
| 145 | void *module_alloc(unsigned long size) | 40 | void *module_alloc(unsigned long size) |
| 146 | { | 41 | { |
| 147 | if (size == 0) | 42 | if (size == 0) |
| @@ -334,16 +229,18 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | |||
| 334 | undefined symbols have been resolved. */ | 229 | undefined symbols have been resolved. */ |
| 335 | sym = (Elf32_Sym *) sechdrs[symindex].sh_addr | 230 | sym = (Elf32_Sym *) sechdrs[symindex].sh_addr |
| 336 | + ELF32_R_SYM(rel[i].r_info); | 231 | + ELF32_R_SYM(rel[i].r_info); |
| 337 | if (is_reloc_stack_empty()) { | 232 | value = sym->st_value; |
| 338 | value = sym->st_value; | ||
| 339 | } else { | ||
| 340 | value = reloc_stack_pop(); | ||
| 341 | } | ||
| 342 | value += rel[i].r_addend; | 233 | value += rel[i].r_addend; |
| 343 | pr_debug("location is %x, value is %x type is %d \n", | 234 | pr_debug("location is %x, value is %x type is %d \n", |
| 344 | (unsigned int) location32, value, | 235 | (unsigned int) location32, value, |
| 345 | ELF32_R_TYPE(rel[i].r_info)); | 236 | ELF32_R_TYPE(rel[i].r_info)); |
| 346 | 237 | #ifdef CONFIG_SMP | |
| 238 | if ((unsigned long)location16 >= COREB_L1_DATA_A_START) { | ||
| 239 | printk(KERN_ERR "module %s: cannot relocate in L1: %u (SMP kernel)", | ||
| 240 | mod->name, ELF32_R_TYPE(rel[i].r_info)); | ||
| 241 | return -ENOEXEC; | ||
| 242 | } | ||
| 243 | #endif | ||
| 347 | switch (ELF32_R_TYPE(rel[i].r_info)) { | 244 | switch (ELF32_R_TYPE(rel[i].r_info)) { |
| 348 | 245 | ||
| 349 | case R_pcrel24: | 246 | case R_pcrel24: |
| @@ -355,6 +252,12 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | |||
| 355 | location32 = (uint32_t *) location16; | 252 | location32 = (uint32_t *) location16; |
| 356 | value -= (uint32_t) location32; | 253 | value -= (uint32_t) location32; |
| 357 | value >>= 1; | 254 | value >>= 1; |
| 255 | if ((value & 0xFF000000) != 0 && | ||
| 256 | (value & 0xFF000000) != 0xFF000000) { | ||
| 257 | printk(KERN_ERR "module %s: relocation overflow\n", | ||
| 258 | mod->name); | ||
| 259 | return -ENOEXEC; | ||
| 260 | } | ||
| 358 | pr_debug("value is %x, before %x-%x after %x-%x\n", value, | 261 | pr_debug("value is %x, before %x-%x after %x-%x\n", value, |
| 359 | *location16, *(location16 + 1), | 262 | *location16, *(location16 + 1), |
| 360 | (*location16 & 0xff00) | (value >> 16 & 0x00ff), | 263 | (*location16 & 0xff00) | (value >> 16 & 0x00ff), |
| @@ -399,28 +302,6 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab, | |||
| 399 | pr_debug("before %x after %x\n", *location32, value); | 302 | pr_debug("before %x after %x\n", *location32, value); |
| 400 | *location32 = value; | 303 | *location32 = value; |
| 401 | break; | 304 | break; |
| 402 | case R_push: | ||
| 403 | reloc_stack_push(value); | ||
| 404 | break; | ||
| 405 | case R_const: | ||
| 406 | reloc_stack_push(rel[i].r_addend); | ||
| 407 | break; | ||
| 408 | case R_add: | ||
| 409 | case R_sub: | ||
| 410 | case R_mult: | ||
| 411 | case R_div: | ||
| 412 | case R_mod: | ||
| 413 | case R_lshift: | ||
| 414 | case R_rshift: | ||
| 415 | case R_and: | ||
| 416 | case R_or: | ||
| 417 | case R_xor: | ||
| 418 | case R_land: | ||
| 419 | case R_lor: | ||
| 420 | case R_neg: | ||
| 421 | case R_comp: | ||
| 422 | reloc_stack_operate(ELF32_R_TYPE(rel[i].r_info), mod); | ||
| 423 | break; | ||
| 424 | default: | 305 | default: |
| 425 | printk(KERN_ERR "module %s: Unknown relocation: %u\n", | 306 | printk(KERN_ERR "module %s: Unknown relocation: %u\n", |
| 426 | mod->name, ELF32_R_TYPE(rel[i].r_info)); | 307 | mod->name, ELF32_R_TYPE(rel[i].r_info)); |
| @@ -436,6 +317,7 @@ module_finalize(const Elf_Ehdr * hdr, | |||
| 436 | { | 317 | { |
| 437 | unsigned int i, strindex = 0, symindex = 0; | 318 | unsigned int i, strindex = 0, symindex = 0; |
| 438 | char *secstrings; | 319 | char *secstrings; |
| 320 | long err = 0; | ||
| 439 | 321 | ||
| 440 | secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; | 322 | secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; |
| 441 | 323 | ||
| @@ -460,8 +342,10 @@ module_finalize(const Elf_Ehdr * hdr, | |||
| 460 | (strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) || | 342 | (strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) || |
| 461 | ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) && | 343 | ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) && |
| 462 | (hdr->e_flags & (EF_BFIN_CODE_IN_L1|EF_BFIN_CODE_IN_L2))))) { | 344 | (hdr->e_flags & (EF_BFIN_CODE_IN_L1|EF_BFIN_CODE_IN_L2))))) { |
| 463 | apply_relocate_add((Elf_Shdr *) sechdrs, strtab, | 345 | err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab, |
| 464 | symindex, i, mod); | 346 | symindex, i, mod); |
| 347 | if (err < 0) | ||
| 348 | return -ENOEXEC; | ||
| 465 | } | 349 | } |
| 466 | } | 350 | } |
| 467 | return 0; | 351 | return 0; |
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index 0c3ea118b657..33e2e8993f7f 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | 39 | ||
| 40 | #include <asm/blackfin.h> | 40 | #include <asm/blackfin.h> |
| 41 | #include <asm/fixed_code.h> | 41 | #include <asm/fixed_code.h> |
| 42 | #include <asm/mem_map.h> | ||
| 42 | 43 | ||
| 43 | asmlinkage void ret_from_fork(void); | 44 | asmlinkage void ret_from_fork(void); |
| 44 | 45 | ||
| @@ -81,11 +82,14 @@ void cpu_idle(void)__attribute__((l1_text)); | |||
| 81 | */ | 82 | */ |
| 82 | static void default_idle(void) | 83 | static void default_idle(void) |
| 83 | { | 84 | { |
| 84 | local_irq_disable(); | 85 | #ifdef CONFIG_IPIPE |
| 86 | ipipe_suspend_domain(); | ||
| 87 | #endif | ||
| 88 | local_irq_disable_hw(); | ||
| 85 | if (!need_resched()) | 89 | if (!need_resched()) |
| 86 | idle_with_irq_disabled(); | 90 | idle_with_irq_disabled(); |
| 87 | 91 | ||
| 88 | local_irq_enable(); | 92 | local_irq_enable_hw(); |
| 89 | } | 93 | } |
| 90 | 94 | ||
| 91 | /* | 95 | /* |
| @@ -154,6 +158,7 @@ pid_t kernel_thread(int (*fn) (void *), void *arg, unsigned long flags) | |||
| 154 | return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, | 158 | return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, |
| 155 | NULL); | 159 | NULL); |
| 156 | } | 160 | } |
| 161 | EXPORT_SYMBOL(kernel_thread); | ||
| 157 | 162 | ||
| 158 | void flush_thread(void) | 163 | void flush_thread(void) |
| 159 | { | 164 | { |
| @@ -170,6 +175,13 @@ asmlinkage int bfin_clone(struct pt_regs *regs) | |||
| 170 | unsigned long clone_flags; | 175 | unsigned long clone_flags; |
| 171 | unsigned long newsp; | 176 | unsigned long newsp; |
| 172 | 177 | ||
| 178 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 179 | if (current->rt.nr_cpus_allowed == num_possible_cpus()) { | ||
| 180 | current->cpus_allowed = cpumask_of_cpu(smp_processor_id()); | ||
| 181 | current->rt.nr_cpus_allowed = 1; | ||
| 182 | } | ||
| 183 | #endif | ||
| 184 | |||
| 173 | /* syscall2 puts clone_flags in r0 and usp in r1 */ | 185 | /* syscall2 puts clone_flags in r0 and usp in r1 */ |
| 174 | clone_flags = regs->r0; | 186 | clone_flags = regs->r0; |
| 175 | newsp = regs->r1; | 187 | newsp = regs->r1; |
| @@ -337,22 +349,22 @@ int _access_ok(unsigned long addr, unsigned long size) | |||
| 337 | if (addr >= (unsigned long)__init_begin && | 349 | if (addr >= (unsigned long)__init_begin && |
| 338 | addr + size <= (unsigned long)__init_end) | 350 | addr + size <= (unsigned long)__init_end) |
| 339 | return 1; | 351 | return 1; |
| 340 | if (addr >= L1_SCRATCH_START | 352 | if (addr >= get_l1_scratch_start() |
| 341 | && addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH) | 353 | && addr + size <= get_l1_scratch_start() + L1_SCRATCH_LENGTH) |
| 342 | return 1; | 354 | return 1; |
| 343 | #if L1_CODE_LENGTH != 0 | 355 | #if L1_CODE_LENGTH != 0 |
| 344 | if (addr >= L1_CODE_START + (_etext_l1 - _stext_l1) | 356 | if (addr >= get_l1_code_start() + (_etext_l1 - _stext_l1) |
| 345 | && addr + size <= L1_CODE_START + L1_CODE_LENGTH) | 357 | && addr + size <= get_l1_code_start() + L1_CODE_LENGTH) |
| 346 | return 1; | 358 | return 1; |
| 347 | #endif | 359 | #endif |
| 348 | #if L1_DATA_A_LENGTH != 0 | 360 | #if L1_DATA_A_LENGTH != 0 |
| 349 | if (addr >= L1_DATA_A_START + (_ebss_l1 - _sdata_l1) | 361 | if (addr >= get_l1_data_a_start() + (_ebss_l1 - _sdata_l1) |
| 350 | && addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH) | 362 | && addr + size <= get_l1_data_a_start() + L1_DATA_A_LENGTH) |
| 351 | return 1; | 363 | return 1; |
| 352 | #endif | 364 | #endif |
| 353 | #if L1_DATA_B_LENGTH != 0 | 365 | #if L1_DATA_B_LENGTH != 0 |
| 354 | if (addr >= L1_DATA_B_START + (_ebss_b_l1 - _sdata_b_l1) | 366 | if (addr >= get_l1_data_b_start() + (_ebss_b_l1 - _sdata_b_l1) |
| 355 | && addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH) | 367 | && addr + size <= get_l1_data_b_start() + L1_DATA_B_LENGTH) |
| 356 | return 1; | 368 | return 1; |
| 357 | #endif | 369 | #endif |
| 358 | #if L2_LENGTH != 0 | 370 | #if L2_LENGTH != 0 |
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 140bf00e9974..d2d388536630 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | #include <asm/asm-offsets.h> | 45 | #include <asm/asm-offsets.h> |
| 46 | #include <asm/dma.h> | 46 | #include <asm/dma.h> |
| 47 | #include <asm/fixed_code.h> | 47 | #include <asm/fixed_code.h> |
| 48 | #include <asm/mem_map.h> | ||
| 48 | 49 | ||
| 49 | #define TEXT_OFFSET 0 | 50 | #define TEXT_OFFSET 0 |
| 50 | /* | 51 | /* |
| @@ -80,10 +81,12 @@ static inline struct pt_regs *get_user_regs(struct task_struct *task) | |||
| 80 | /* | 81 | /* |
| 81 | * Get all user integer registers. | 82 | * Get all user integer registers. |
| 82 | */ | 83 | */ |
| 83 | static inline int ptrace_getregs(struct task_struct *tsk, void __user * uregs) | 84 | static inline int ptrace_getregs(struct task_struct *tsk, void __user *uregs) |
| 84 | { | 85 | { |
| 85 | struct pt_regs *regs = get_user_regs(tsk); | 86 | struct pt_regs regs; |
| 86 | return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0; | 87 | memcpy(®s, get_user_regs(tsk), sizeof(regs)); |
| 88 | regs.usp = tsk->thread.usp; | ||
| 89 | return copy_to_user(uregs, ®s, sizeof(struct pt_regs)) ? -EFAULT : 0; | ||
| 87 | } | 90 | } |
| 88 | 91 | ||
| 89 | /* Mapping from PT_xxx to the stack offset at which the register is | 92 | /* Mapping from PT_xxx to the stack offset at which the register is |
| @@ -220,8 +223,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
| 220 | break; | 223 | break; |
| 221 | pr_debug("ptrace: user address is valid\n"); | 224 | pr_debug("ptrace: user address is valid\n"); |
| 222 | 225 | ||
| 223 | if (L1_CODE_LENGTH != 0 && addr >= L1_CODE_START | 226 | if (L1_CODE_LENGTH != 0 && addr >= get_l1_code_start() |
| 224 | && addr + sizeof(tmp) <= L1_CODE_START + L1_CODE_LENGTH) { | 227 | && addr + sizeof(tmp) <= get_l1_code_start() + L1_CODE_LENGTH) { |
| 225 | safe_dma_memcpy (&tmp, (const void *)(addr), sizeof(tmp)); | 228 | safe_dma_memcpy (&tmp, (const void *)(addr), sizeof(tmp)); |
| 226 | copied = sizeof(tmp); | 229 | copied = sizeof(tmp); |
| 227 | 230 | ||
| @@ -300,8 +303,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
| 300 | break; | 303 | break; |
| 301 | pr_debug("ptrace: user address is valid\n"); | 304 | pr_debug("ptrace: user address is valid\n"); |
| 302 | 305 | ||
| 303 | if (L1_CODE_LENGTH != 0 && addr >= L1_CODE_START | 306 | if (L1_CODE_LENGTH != 0 && addr >= get_l1_code_start() |
| 304 | && addr + sizeof(data) <= L1_CODE_START + L1_CODE_LENGTH) { | 307 | && addr + sizeof(data) <= get_l1_code_start() + L1_CODE_LENGTH) { |
| 305 | safe_dma_memcpy ((void *)(addr), &data, sizeof(data)); | 308 | safe_dma_memcpy ((void *)(addr), &data, sizeof(data)); |
| 306 | copied = sizeof(data); | 309 | copied = sizeof(data); |
| 307 | 310 | ||
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c index ae97ca407b0d..eeee8cb43360 100644 --- a/arch/blackfin/kernel/reboot.c +++ b/arch/blackfin/kernel/reboot.c | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | * the core reset. | 21 | * the core reset. |
| 22 | */ | 22 | */ |
| 23 | __attribute__((l1_text)) | 23 | __attribute__((l1_text)) |
| 24 | static void bfin_reset(void) | 24 | static void _bfin_reset(void) |
| 25 | { | 25 | { |
| 26 | /* Wait for completion of "system" events such as cache line | 26 | /* Wait for completion of "system" events such as cache line |
| 27 | * line fills so that we avoid infinite stalls later on as | 27 | * line fills so that we avoid infinite stalls later on as |
| @@ -66,6 +66,18 @@ static void bfin_reset(void) | |||
| 66 | } | 66 | } |
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | static void bfin_reset(void) | ||
| 70 | { | ||
| 71 | if (ANOMALY_05000353 || ANOMALY_05000386) | ||
| 72 | _bfin_reset(); | ||
| 73 | else | ||
| 74 | /* the bootrom checks to see how it was reset and will | ||
| 75 | * automatically perform a software reset for us when | ||
| 76 | * it starts executing boot | ||
| 77 | */ | ||
| 78 | asm("raise 1;"); | ||
| 79 | } | ||
| 80 | |||
| 69 | __attribute__((weak)) | 81 | __attribute__((weak)) |
| 70 | void native_machine_restart(char *cmd) | 82 | void native_machine_restart(char *cmd) |
| 71 | { | 83 | { |
| @@ -75,14 +87,10 @@ void machine_restart(char *cmd) | |||
| 75 | { | 87 | { |
| 76 | native_machine_restart(cmd); | 88 | native_machine_restart(cmd); |
| 77 | local_irq_disable(); | 89 | local_irq_disable(); |
| 78 | if (ANOMALY_05000353 || ANOMALY_05000386) | 90 | if (smp_processor_id()) |
| 79 | bfin_reset(); | 91 | smp_call_function((void *)bfin_reset, 0, 1); |
| 80 | else | 92 | else |
| 81 | /* the bootrom checks to see how it was reset and will | 93 | bfin_reset(); |
| 82 | * automatically perform a software reset for us when | ||
| 83 | * it starts executing boot | ||
| 84 | */ | ||
| 85 | asm("raise 1;"); | ||
| 86 | } | 94 | } |
| 87 | 95 | ||
| 88 | __attribute__((weak)) | 96 | __attribute__((weak)) |
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index 71a9a8c53cea..b2a811347b65 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <linux/bootmem.h> | 13 | #include <linux/bootmem.h> |
| 14 | #include <linux/seq_file.h> | 14 | #include <linux/seq_file.h> |
| 15 | #include <linux/cpu.h> | 15 | #include <linux/cpu.h> |
| 16 | #include <linux/mm.h> | ||
| 16 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| 17 | #include <linux/tty.h> | 18 | #include <linux/tty.h> |
| 18 | #include <linux/pfn.h> | 19 | #include <linux/pfn.h> |
| @@ -26,11 +27,10 @@ | |||
| 26 | #include <asm/blackfin.h> | 27 | #include <asm/blackfin.h> |
| 27 | #include <asm/cplbinit.h> | 28 | #include <asm/cplbinit.h> |
| 28 | #include <asm/div64.h> | 29 | #include <asm/div64.h> |
| 30 | #include <asm/cpu.h> | ||
| 29 | #include <asm/fixed_code.h> | 31 | #include <asm/fixed_code.h> |
| 30 | #include <asm/early_printk.h> | 32 | #include <asm/early_printk.h> |
| 31 | 33 | ||
| 32 | static DEFINE_PER_CPU(struct cpu, cpu_devices); | ||
| 33 | |||
| 34 | u16 _bfin_swrst; | 34 | u16 _bfin_swrst; |
| 35 | EXPORT_SYMBOL(_bfin_swrst); | 35 | EXPORT_SYMBOL(_bfin_swrst); |
| 36 | 36 | ||
| @@ -79,27 +79,68 @@ static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata; | |||
| 79 | static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; | 79 | static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata; |
| 80 | static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; | 80 | static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata; |
| 81 | 81 | ||
| 82 | void __init bfin_cache_init(void) | 82 | DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data); |
| 83 | { | 83 | |
| 84 | static int early_init_clkin_hz(char *buf); | ||
| 85 | |||
| 84 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) | 86 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) |
| 85 | generate_cplb_tables(); | 87 | void __init generate_cplb_tables(void) |
| 88 | { | ||
| 89 | unsigned int cpu; | ||
| 90 | |||
| 91 | generate_cplb_tables_all(); | ||
| 92 | /* Generate per-CPU I&D CPLB tables */ | ||
| 93 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) | ||
| 94 | generate_cplb_tables_cpu(cpu); | ||
| 95 | } | ||
| 86 | #endif | 96 | #endif |
| 87 | 97 | ||
| 98 | void __cpuinit bfin_setup_caches(unsigned int cpu) | ||
| 99 | { | ||
| 88 | #ifdef CONFIG_BFIN_ICACHE | 100 | #ifdef CONFIG_BFIN_ICACHE |
| 89 | bfin_icache_init(); | 101 | bfin_icache_init(icplb_tbl[cpu]); |
| 90 | printk(KERN_INFO "Instruction Cache Enabled\n"); | ||
| 91 | #endif | 102 | #endif |
| 92 | 103 | ||
| 93 | #ifdef CONFIG_BFIN_DCACHE | 104 | #ifdef CONFIG_BFIN_DCACHE |
| 94 | bfin_dcache_init(); | 105 | bfin_dcache_init(dcplb_tbl[cpu]); |
| 95 | printk(KERN_INFO "Data Cache Enabled" | 106 | #endif |
| 107 | |||
| 108 | /* | ||
| 109 | * In cache coherence emulation mode, we need to have the | ||
| 110 | * D-cache enabled before running any atomic operation which | ||
| 111 | * might invove cache invalidation (i.e. spinlock, rwlock). | ||
| 112 | * So printk's are deferred until then. | ||
| 113 | */ | ||
| 114 | #ifdef CONFIG_BFIN_ICACHE | ||
| 115 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); | ||
| 116 | #endif | ||
| 117 | #ifdef CONFIG_BFIN_DCACHE | ||
| 118 | printk(KERN_INFO "Data Cache Enabled for CPU%u" | ||
| 96 | # if defined CONFIG_BFIN_WB | 119 | # if defined CONFIG_BFIN_WB |
| 97 | " (write-back)" | 120 | " (write-back)" |
| 98 | # elif defined CONFIG_BFIN_WT | 121 | # elif defined CONFIG_BFIN_WT |
| 99 | " (write-through)" | 122 | " (write-through)" |
| 100 | # endif | 123 | # endif |
| 101 | "\n"); | 124 | "\n", cpu); |
| 125 | #endif | ||
| 126 | } | ||
| 127 | |||
| 128 | void __cpuinit bfin_setup_cpudata(unsigned int cpu) | ||
| 129 | { | ||
| 130 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu); | ||
| 131 | |||
| 132 | cpudata->idle = current; | ||
| 133 | cpudata->loops_per_jiffy = loops_per_jiffy; | ||
| 134 | cpudata->imemctl = bfin_read_IMEM_CONTROL(); | ||
| 135 | cpudata->dmemctl = bfin_read_DMEM_CONTROL(); | ||
| 136 | } | ||
| 137 | |||
| 138 | void __init bfin_cache_init(void) | ||
| 139 | { | ||
| 140 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) | ||
| 141 | generate_cplb_tables(); | ||
| 102 | #endif | 142 | #endif |
| 143 | bfin_setup_caches(0); | ||
| 103 | } | 144 | } |
| 104 | 145 | ||
| 105 | void __init bfin_relocate_l1_mem(void) | 146 | void __init bfin_relocate_l1_mem(void) |
| @@ -109,6 +150,8 @@ void __init bfin_relocate_l1_mem(void) | |||
| 109 | unsigned long l1_data_b_length; | 150 | unsigned long l1_data_b_length; |
| 110 | unsigned long l2_length; | 151 | unsigned long l2_length; |
| 111 | 152 | ||
| 153 | blackfin_dma_early_init(); | ||
| 154 | |||
| 112 | l1_code_length = _etext_l1 - _stext_l1; | 155 | l1_code_length = _etext_l1 - _stext_l1; |
| 113 | if (l1_code_length > L1_CODE_LENGTH) | 156 | if (l1_code_length > L1_CODE_LENGTH) |
| 114 | panic("L1 Instruction SRAM Overflow\n"); | 157 | panic("L1 Instruction SRAM Overflow\n"); |
| @@ -230,7 +273,7 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |||
| 230 | /* record all known change-points (starting and ending addresses), | 273 | /* record all known change-points (starting and ending addresses), |
| 231 | omitting those that are for empty memory regions */ | 274 | omitting those that are for empty memory regions */ |
| 232 | chgidx = 0; | 275 | chgidx = 0; |
| 233 | for (i = 0; i < old_nr; i++) { | 276 | for (i = 0; i < old_nr; i++) { |
| 234 | if (map[i].size != 0) { | 277 | if (map[i].size != 0) { |
| 235 | change_point[chgidx]->addr = map[i].addr; | 278 | change_point[chgidx]->addr = map[i].addr; |
| 236 | change_point[chgidx++]->pentry = &map[i]; | 279 | change_point[chgidx++]->pentry = &map[i]; |
| @@ -238,13 +281,13 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |||
| 238 | change_point[chgidx++]->pentry = &map[i]; | 281 | change_point[chgidx++]->pentry = &map[i]; |
| 239 | } | 282 | } |
| 240 | } | 283 | } |
| 241 | chg_nr = chgidx; /* true number of change-points */ | 284 | chg_nr = chgidx; /* true number of change-points */ |
| 242 | 285 | ||
| 243 | /* sort change-point list by memory addresses (low -> high) */ | 286 | /* sort change-point list by memory addresses (low -> high) */ |
| 244 | still_changing = 1; | 287 | still_changing = 1; |
| 245 | while (still_changing) { | 288 | while (still_changing) { |
| 246 | still_changing = 0; | 289 | still_changing = 0; |
| 247 | for (i = 1; i < chg_nr; i++) { | 290 | for (i = 1; i < chg_nr; i++) { |
| 248 | /* if <current_addr> > <last_addr>, swap */ | 291 | /* if <current_addr> > <last_addr>, swap */ |
| 249 | /* or, if current=<start_addr> & last=<end_addr>, swap */ | 292 | /* or, if current=<start_addr> & last=<end_addr>, swap */ |
| 250 | if ((change_point[i]->addr < change_point[i-1]->addr) || | 293 | if ((change_point[i]->addr < change_point[i-1]->addr) || |
| @@ -261,10 +304,10 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |||
| 261 | } | 304 | } |
| 262 | 305 | ||
| 263 | /* create a new memmap, removing overlaps */ | 306 | /* create a new memmap, removing overlaps */ |
| 264 | overlap_entries = 0; /* number of entries in the overlap table */ | 307 | overlap_entries = 0; /* number of entries in the overlap table */ |
| 265 | new_entry = 0; /* index for creating new memmap entries */ | 308 | new_entry = 0; /* index for creating new memmap entries */ |
| 266 | last_type = 0; /* start with undefined memory type */ | 309 | last_type = 0; /* start with undefined memory type */ |
| 267 | last_addr = 0; /* start with 0 as last starting address */ | 310 | last_addr = 0; /* start with 0 as last starting address */ |
| 268 | /* loop through change-points, determining affect on the new memmap */ | 311 | /* loop through change-points, determining affect on the new memmap */ |
| 269 | for (chgidx = 0; chgidx < chg_nr; chgidx++) { | 312 | for (chgidx = 0; chgidx < chg_nr; chgidx++) { |
| 270 | /* keep track of all overlapping memmap entries */ | 313 | /* keep track of all overlapping memmap entries */ |
| @@ -286,14 +329,14 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |||
| 286 | if (overlap_list[i]->type > current_type) | 329 | if (overlap_list[i]->type > current_type) |
| 287 | current_type = overlap_list[i]->type; | 330 | current_type = overlap_list[i]->type; |
| 288 | /* continue building up new memmap based on this information */ | 331 | /* continue building up new memmap based on this information */ |
| 289 | if (current_type != last_type) { | 332 | if (current_type != last_type) { |
| 290 | if (last_type != 0) { | 333 | if (last_type != 0) { |
| 291 | new_map[new_entry].size = | 334 | new_map[new_entry].size = |
| 292 | change_point[chgidx]->addr - last_addr; | 335 | change_point[chgidx]->addr - last_addr; |
| 293 | /* move forward only if the new size was non-zero */ | 336 | /* move forward only if the new size was non-zero */ |
| 294 | if (new_map[new_entry].size != 0) | 337 | if (new_map[new_entry].size != 0) |
| 295 | if (++new_entry >= BFIN_MEMMAP_MAX) | 338 | if (++new_entry >= BFIN_MEMMAP_MAX) |
| 296 | break; /* no more space left for new entries */ | 339 | break; /* no more space left for new entries */ |
| 297 | } | 340 | } |
| 298 | if (current_type != 0) { | 341 | if (current_type != 0) { |
| 299 | new_map[new_entry].addr = change_point[chgidx]->addr; | 342 | new_map[new_entry].addr = change_point[chgidx]->addr; |
| @@ -303,9 +346,9 @@ static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map) | |||
| 303 | last_type = current_type; | 346 | last_type = current_type; |
| 304 | } | 347 | } |
| 305 | } | 348 | } |
| 306 | new_nr = new_entry; /* retain count for new entries */ | 349 | new_nr = new_entry; /* retain count for new entries */ |
| 307 | 350 | ||
| 308 | /* copy new mapping into original location */ | 351 | /* copy new mapping into original location */ |
| 309 | memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry)); | 352 | memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry)); |
| 310 | *pnr_map = new_nr; | 353 | *pnr_map = new_nr; |
| 311 | 354 | ||
| @@ -361,7 +404,6 @@ static __init int parse_memmap(char *arg) | |||
| 361 | * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region | 404 | * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region |
| 362 | * @ from <start> to <start>+<mem>, type RAM | 405 | * @ from <start> to <start>+<mem>, type RAM |
| 363 | * $ from <start> to <start>+<mem>, type RESERVED | 406 | * $ from <start> to <start>+<mem>, type RESERVED |
| 364 | * | ||
| 365 | */ | 407 | */ |
| 366 | static __init void parse_cmdline_early(char *cmdline_p) | 408 | static __init void parse_cmdline_early(char *cmdline_p) |
| 367 | { | 409 | { |
| @@ -383,14 +425,15 @@ static __init void parse_cmdline_early(char *cmdline_p) | |||
| 383 | if (*to != ' ') { | 425 | if (*to != ' ') { |
| 384 | if (*to == '$' | 426 | if (*to == '$' |
| 385 | || *(to + 1) == '$') | 427 | || *(to + 1) == '$') |
| 386 | reserved_mem_dcache_on = | 428 | reserved_mem_dcache_on = 1; |
| 387 | 1; | ||
| 388 | if (*to == '#' | 429 | if (*to == '#' |
| 389 | || *(to + 1) == '#') | 430 | || *(to + 1) == '#') |
| 390 | reserved_mem_icache_on = | 431 | reserved_mem_icache_on = 1; |
| 391 | 1; | ||
| 392 | } | 432 | } |
| 393 | } | 433 | } |
| 434 | } else if (!memcmp(to, "clkin_hz=", 9)) { | ||
| 435 | to += 9; | ||
| 436 | early_init_clkin_hz(to); | ||
| 394 | } else if (!memcmp(to, "earlyprintk=", 12)) { | 437 | } else if (!memcmp(to, "earlyprintk=", 12)) { |
| 395 | to += 12; | 438 | to += 12; |
| 396 | setup_early_printk(to); | 439 | setup_early_printk(to); |
| @@ -417,9 +460,8 @@ static __init void parse_cmdline_early(char *cmdline_p) | |||
| 417 | * [_ramend - DMA_UNCACHED_REGION, | 460 | * [_ramend - DMA_UNCACHED_REGION, |
| 418 | * _ramend]: uncached DMA region | 461 | * _ramend]: uncached DMA region |
| 419 | * [_ramend, physical_mem_end]: memory not managed by kernel | 462 | * [_ramend, physical_mem_end]: memory not managed by kernel |
| 420 | * | ||
| 421 | */ | 463 | */ |
| 422 | static __init void memory_setup(void) | 464 | static __init void memory_setup(void) |
| 423 | { | 465 | { |
| 424 | #ifdef CONFIG_MTD_UCLINUX | 466 | #ifdef CONFIG_MTD_UCLINUX |
| 425 | unsigned long mtd_phys = 0; | 467 | unsigned long mtd_phys = 0; |
| @@ -436,7 +478,7 @@ static __init void memory_setup(void) | |||
| 436 | memory_end = _ramend - DMA_UNCACHED_REGION; | 478 | memory_end = _ramend - DMA_UNCACHED_REGION; |
| 437 | 479 | ||
| 438 | #ifdef CONFIG_MPU | 480 | #ifdef CONFIG_MPU |
| 439 | /* Round up to multiple of 4MB. */ | 481 | /* Round up to multiple of 4MB */ |
| 440 | memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; | 482 | memory_start = (_ramstart + 0x3fffff) & ~0x3fffff; |
| 441 | #else | 483 | #else |
| 442 | memory_start = PAGE_ALIGN(_ramstart); | 484 | memory_start = PAGE_ALIGN(_ramstart); |
| @@ -616,7 +658,7 @@ static __init void setup_bootmem_allocator(void) | |||
| 616 | end_pfn = memory_end >> PAGE_SHIFT; | 658 | end_pfn = memory_end >> PAGE_SHIFT; |
| 617 | 659 | ||
| 618 | /* | 660 | /* |
| 619 | * give all the memory to the bootmap allocator, tell it to put the | 661 | * give all the memory to the bootmap allocator, tell it to put the |
| 620 | * boot mem_map at the start of memory. | 662 | * boot mem_map at the start of memory. |
| 621 | */ | 663 | */ |
| 622 | bootmap_size = init_bootmem_node(NODE_DATA(0), | 664 | bootmap_size = init_bootmem_node(NODE_DATA(0), |
| @@ -791,7 +833,11 @@ void __init setup_arch(char **cmdline_p) | |||
| 791 | bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT); | 833 | bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT); |
| 792 | #endif | 834 | #endif |
| 793 | 835 | ||
| 836 | #ifdef CONFIG_SMP | ||
| 837 | if (_bfin_swrst & SWRST_DBL_FAULT_A) { | ||
| 838 | #else | ||
| 794 | if (_bfin_swrst & RESET_DOUBLE) { | 839 | if (_bfin_swrst & RESET_DOUBLE) { |
| 840 | #endif | ||
| 795 | printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); | 841 | printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); |
| 796 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | 842 | #ifdef CONFIG_DEBUG_DOUBLEFAULT |
| 797 | /* We assume the crashing kernel, and the current symbol table match */ | 843 | /* We assume the crashing kernel, and the current symbol table match */ |
| @@ -823,9 +869,12 @@ void __init setup_arch(char **cmdline_p) | |||
| 823 | if (bfin_compiled_revid() == -1) | 869 | if (bfin_compiled_revid() == -1) |
| 824 | printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", | 870 | printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", |
| 825 | bfin_revid()); | 871 | bfin_revid()); |
| 826 | else if (bfin_compiled_revid() != 0xffff) | 872 | else if (bfin_compiled_revid() != 0xffff) { |
| 827 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", | 873 | printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n", |
| 828 | bfin_compiled_revid(), bfin_revid()); | 874 | bfin_compiled_revid(), bfin_revid()); |
| 875 | if (bfin_compiled_revid() > bfin_revid()) | ||
| 876 | panic("Error: you are missing anomaly workarounds for this rev\n"); | ||
| 877 | } | ||
| 829 | } | 878 | } |
| 830 | if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) | 879 | if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX) |
| 831 | printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", | 880 | printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n", |
| @@ -835,7 +884,7 @@ void __init setup_arch(char **cmdline_p) | |||
| 835 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); | 884 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); |
| 836 | 885 | ||
| 837 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", | 886 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", |
| 838 | cclk / 1000000, sclk / 1000000); | 887 | cclk / 1000000, sclk / 1000000); |
| 839 | 888 | ||
| 840 | if (ANOMALY_05000273 && (cclk >> 1) <= sclk) | 889 | if (ANOMALY_05000273 && (cclk >> 1) <= sclk) |
| 841 | printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n"); | 890 | printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n"); |
| @@ -867,18 +916,21 @@ void __init setup_arch(char **cmdline_p) | |||
| 867 | BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start | 916 | BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start |
| 868 | != SAFE_USER_INSTRUCTION - FIXED_CODE_START); | 917 | != SAFE_USER_INSTRUCTION - FIXED_CODE_START); |
| 869 | 918 | ||
| 919 | #ifdef CONFIG_SMP | ||
| 920 | platform_init_cpus(); | ||
| 921 | #endif | ||
| 870 | init_exception_vectors(); | 922 | init_exception_vectors(); |
| 871 | bfin_cache_init(); | 923 | bfin_cache_init(); /* Initialize caches for the boot CPU */ |
| 872 | } | 924 | } |
| 873 | 925 | ||
| 874 | static int __init topology_init(void) | 926 | static int __init topology_init(void) |
| 875 | { | 927 | { |
| 876 | int cpu; | 928 | unsigned int cpu; |
| 929 | /* Record CPU-private information for the boot processor. */ | ||
| 930 | bfin_setup_cpudata(0); | ||
| 877 | 931 | ||
| 878 | for_each_possible_cpu(cpu) { | 932 | for_each_possible_cpu(cpu) { |
| 879 | struct cpu *c = &per_cpu(cpu_devices, cpu); | 933 | register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu); |
| 880 | |||
| 881 | register_cpu(c, cpu); | ||
| 882 | } | 934 | } |
| 883 | 935 | ||
| 884 | return 0; | 936 | return 0; |
| @@ -886,36 +938,54 @@ static int __init topology_init(void) | |||
| 886 | 938 | ||
| 887 | subsys_initcall(topology_init); | 939 | subsys_initcall(topology_init); |
| 888 | 940 | ||
| 941 | /* Get the input clock frequency */ | ||
| 942 | static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; | ||
| 943 | static u_long get_clkin_hz(void) | ||
| 944 | { | ||
| 945 | return cached_clkin_hz; | ||
| 946 | } | ||
| 947 | static int __init early_init_clkin_hz(char *buf) | ||
| 948 | { | ||
| 949 | cached_clkin_hz = simple_strtoul(buf, NULL, 0); | ||
| 950 | #ifdef BFIN_KERNEL_CLOCK | ||
| 951 | if (cached_clkin_hz != CONFIG_CLKIN_HZ) | ||
| 952 | panic("cannot change clkin_hz when reprogramming clocks"); | ||
| 953 | #endif | ||
| 954 | return 1; | ||
| 955 | } | ||
| 956 | early_param("clkin_hz=", early_init_clkin_hz); | ||
| 957 | |||
| 889 | /* Get the voltage input multiplier */ | 958 | /* Get the voltage input multiplier */ |
| 890 | static u_long cached_vco_pll_ctl, cached_vco; | ||
| 891 | static u_long get_vco(void) | 959 | static u_long get_vco(void) |
| 892 | { | 960 | { |
| 893 | u_long msel; | 961 | static u_long cached_vco; |
| 962 | u_long msel, pll_ctl; | ||
| 894 | 963 | ||
| 895 | u_long pll_ctl = bfin_read_PLL_CTL(); | 964 | /* The assumption here is that VCO never changes at runtime. |
| 896 | if (pll_ctl == cached_vco_pll_ctl) | 965 | * If, someday, we support that, then we'll have to change this. |
| 966 | */ | ||
| 967 | if (cached_vco) | ||
| 897 | return cached_vco; | 968 | return cached_vco; |
| 898 | else | ||
| 899 | cached_vco_pll_ctl = pll_ctl; | ||
| 900 | 969 | ||
| 970 | pll_ctl = bfin_read_PLL_CTL(); | ||
| 901 | msel = (pll_ctl >> 9) & 0x3F; | 971 | msel = (pll_ctl >> 9) & 0x3F; |
| 902 | if (0 == msel) | 972 | if (0 == msel) |
| 903 | msel = 64; | 973 | msel = 64; |
| 904 | 974 | ||
| 905 | cached_vco = CONFIG_CLKIN_HZ; | 975 | cached_vco = get_clkin_hz(); |
| 906 | cached_vco >>= (1 & pll_ctl); /* DF bit */ | 976 | cached_vco >>= (1 & pll_ctl); /* DF bit */ |
| 907 | cached_vco *= msel; | 977 | cached_vco *= msel; |
| 908 | return cached_vco; | 978 | return cached_vco; |
| 909 | } | 979 | } |
| 910 | 980 | ||
| 911 | /* Get the Core clock */ | 981 | /* Get the Core clock */ |
| 912 | static u_long cached_cclk_pll_div, cached_cclk; | ||
| 913 | u_long get_cclk(void) | 982 | u_long get_cclk(void) |
| 914 | { | 983 | { |
| 984 | static u_long cached_cclk_pll_div, cached_cclk; | ||
| 915 | u_long csel, ssel; | 985 | u_long csel, ssel; |
| 916 | 986 | ||
| 917 | if (bfin_read_PLL_STAT() & 0x1) | 987 | if (bfin_read_PLL_STAT() & 0x1) |
| 918 | return CONFIG_CLKIN_HZ; | 988 | return get_clkin_hz(); |
| 919 | 989 | ||
| 920 | ssel = bfin_read_PLL_DIV(); | 990 | ssel = bfin_read_PLL_DIV(); |
| 921 | if (ssel == cached_cclk_pll_div) | 991 | if (ssel == cached_cclk_pll_div) |
| @@ -934,21 +1004,21 @@ u_long get_cclk(void) | |||
| 934 | EXPORT_SYMBOL(get_cclk); | 1004 | EXPORT_SYMBOL(get_cclk); |
| 935 | 1005 | ||
| 936 | /* Get the System clock */ | 1006 | /* Get the System clock */ |
| 937 | static u_long cached_sclk_pll_div, cached_sclk; | ||
| 938 | u_long get_sclk(void) | 1007 | u_long get_sclk(void) |
| 939 | { | 1008 | { |
| 1009 | static u_long cached_sclk; | ||
| 940 | u_long ssel; | 1010 | u_long ssel; |
| 941 | 1011 | ||
| 942 | if (bfin_read_PLL_STAT() & 0x1) | 1012 | /* The assumption here is that SCLK never changes at runtime. |
| 943 | return CONFIG_CLKIN_HZ; | 1013 | * If, someday, we support that, then we'll have to change this. |
| 944 | 1014 | */ | |
| 945 | ssel = bfin_read_PLL_DIV(); | 1015 | if (cached_sclk) |
| 946 | if (ssel == cached_sclk_pll_div) | ||
| 947 | return cached_sclk; | 1016 | return cached_sclk; |
| 948 | else | ||
| 949 | cached_sclk_pll_div = ssel; | ||
| 950 | 1017 | ||
| 951 | ssel &= 0xf; | 1018 | if (bfin_read_PLL_STAT() & 0x1) |
| 1019 | return get_clkin_hz(); | ||
| 1020 | |||
| 1021 | ssel = bfin_read_PLL_DIV() & 0xf; | ||
| 952 | if (0 == ssel) { | 1022 | if (0 == ssel) { |
| 953 | printk(KERN_WARNING "Invalid System Clock\n"); | 1023 | printk(KERN_WARNING "Invalid System Clock\n"); |
| 954 | ssel = 1; | 1024 | ssel = 1; |
| @@ -982,17 +1052,18 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 982 | { | 1052 | { |
| 983 | char *cpu, *mmu, *fpu, *vendor, *cache; | 1053 | char *cpu, *mmu, *fpu, *vendor, *cache; |
| 984 | uint32_t revid; | 1054 | uint32_t revid; |
| 985 | 1055 | int cpu_num = *(unsigned int *)v; | |
| 986 | u_long cclk = 0, sclk = 0; | 1056 | u_long sclk, cclk; |
| 987 | u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; | 1057 | u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0; |
| 1058 | struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num); | ||
| 988 | 1059 | ||
| 989 | cpu = CPU; | 1060 | cpu = CPU; |
| 990 | mmu = "none"; | 1061 | mmu = "none"; |
| 991 | fpu = "none"; | 1062 | fpu = "none"; |
| 992 | revid = bfin_revid(); | 1063 | revid = bfin_revid(); |
| 993 | 1064 | ||
| 994 | cclk = get_cclk(); | ||
| 995 | sclk = get_sclk(); | 1065 | sclk = get_sclk(); |
| 1066 | cclk = get_cclk(); | ||
| 996 | 1067 | ||
| 997 | switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { | 1068 | switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) { |
| 998 | case 0xca: | 1069 | case 0xca: |
| @@ -1003,10 +1074,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1003 | break; | 1074 | break; |
| 1004 | } | 1075 | } |
| 1005 | 1076 | ||
| 1006 | seq_printf(m, "processor\t: %d\n" | 1077 | seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor); |
| 1007 | "vendor_id\t: %s\n", | ||
| 1008 | *(unsigned int *)v, | ||
| 1009 | vendor); | ||
| 1010 | 1078 | ||
| 1011 | if (CPUID == bfin_cpuid()) | 1079 | if (CPUID == bfin_cpuid()) |
| 1012 | seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); | 1080 | seq_printf(m, "cpu family\t: 0x%04x\n", CPUID); |
| @@ -1029,12 +1097,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1029 | sclk/1000000, sclk%1000000); | 1097 | sclk/1000000, sclk%1000000); |
| 1030 | seq_printf(m, "bogomips\t: %lu.%02lu\n" | 1098 | seq_printf(m, "bogomips\t: %lu.%02lu\n" |
| 1031 | "Calibration\t: %lu loops\n", | 1099 | "Calibration\t: %lu loops\n", |
| 1032 | (loops_per_jiffy * HZ) / 500000, | 1100 | (cpudata->loops_per_jiffy * HZ) / 500000, |
| 1033 | ((loops_per_jiffy * HZ) / 5000) % 100, | 1101 | ((cpudata->loops_per_jiffy * HZ) / 5000) % 100, |
| 1034 | (loops_per_jiffy * HZ)); | 1102 | (cpudata->loops_per_jiffy * HZ)); |
| 1035 | 1103 | ||
| 1036 | /* Check Cache configutation */ | 1104 | /* Check Cache configutation */ |
| 1037 | switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) { | 1105 | switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) { |
| 1038 | case ACACHE_BSRAM: | 1106 | case ACACHE_BSRAM: |
| 1039 | cache = "dbank-A/B\t: cache/sram"; | 1107 | cache = "dbank-A/B\t: cache/sram"; |
| 1040 | dcache_size = 16; | 1108 | dcache_size = 16; |
| @@ -1058,10 +1126,10 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1058 | } | 1126 | } |
| 1059 | 1127 | ||
| 1060 | /* Is it turned on? */ | 1128 | /* Is it turned on? */ |
| 1061 | if ((bfin_read_DMEM_CONTROL() & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) | 1129 | if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE)) |
| 1062 | dcache_size = 0; | 1130 | dcache_size = 0; |
| 1063 | 1131 | ||
| 1064 | if ((bfin_read_IMEM_CONTROL() & (IMC | ENICPLB)) != (IMC | ENICPLB)) | 1132 | if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB)) |
| 1065 | icache_size = 0; | 1133 | icache_size = 0; |
| 1066 | 1134 | ||
| 1067 | seq_printf(m, "cache size\t: %d KB(L1 icache) " | 1135 | seq_printf(m, "cache size\t: %d KB(L1 icache) " |
| @@ -1086,8 +1154,11 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1086 | "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", | 1154 | "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n", |
| 1087 | dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, | 1155 | dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS, |
| 1088 | BFIN_DLINES); | 1156 | BFIN_DLINES); |
| 1157 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 1158 | seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count); | ||
| 1159 | #endif | ||
| 1089 | #ifdef CONFIG_BFIN_ICACHE_LOCK | 1160 | #ifdef CONFIG_BFIN_ICACHE_LOCK |
| 1090 | switch ((bfin_read_IMEM_CONTROL() >> 3) & WAYALL_L) { | 1161 | switch ((cpudata->imemctl >> 3) & WAYALL_L) { |
| 1091 | case WAY0_L: | 1162 | case WAY0_L: |
| 1092 | seq_printf(m, "Way0 Locked-Down\n"); | 1163 | seq_printf(m, "Way0 Locked-Down\n"); |
| 1093 | break; | 1164 | break; |
| @@ -1137,6 +1208,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1137 | seq_printf(m, "No Ways are locked\n"); | 1208 | seq_printf(m, "No Ways are locked\n"); |
| 1138 | } | 1209 | } |
| 1139 | #endif | 1210 | #endif |
| 1211 | |||
| 1212 | if (cpu_num != num_possible_cpus() - 1) | ||
| 1213 | return 0; | ||
| 1214 | |||
| 1215 | if (L2_LENGTH) | ||
| 1216 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); | ||
| 1140 | seq_printf(m, "board name\t: %s\n", bfin_board_name); | 1217 | seq_printf(m, "board name\t: %s\n", bfin_board_name); |
| 1141 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", | 1218 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", |
| 1142 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); | 1219 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); |
| @@ -1144,6 +1221,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1144 | ((int)memory_end - (int)_stext) >> 10, | 1221 | ((int)memory_end - (int)_stext) >> 10, |
| 1145 | _stext, | 1222 | _stext, |
| 1146 | (void *)memory_end); | 1223 | (void *)memory_end); |
| 1224 | seq_printf(m, "\n"); | ||
| 1147 | 1225 | ||
| 1148 | return 0; | 1226 | return 0; |
| 1149 | } | 1227 | } |
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index eb2352320454..172b4c588467 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c | |||
| @@ -1,32 +1,11 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: arch/blackfin/kernel/time.c | 2 | * arch/blackfin/kernel/time.c |
| 3 | * Based on: none - original work | ||
| 4 | * Author: | ||
| 5 | * | 3 | * |
| 6 | * Created: | 4 | * This file contains the Blackfin-specific time handling details. |
| 7 | * Description: This file contains the bfin-specific time handling details. | 5 | * Most of the stuff is located in the machine specific files. |
| 8 | * Most of the stuff is located in the machine specific files. | ||
| 9 | * FIXME: (This file is subject for removal) | ||
| 10 | * | 6 | * |
| 11 | * Modified: | 7 | * Copyright 2004-2008 Analog Devices Inc. |
| 12 | * Copyright 2004-2008 Analog Devices Inc. | 8 | * Licensed under the GPL-2 or later. |
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2 of the License, or | ||
| 19 | * (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, see the file COPYING, or write | ||
| 28 | * to the Free Software Foundation, Inc., | ||
| 29 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 30 | */ | 9 | */ |
| 31 | 10 | ||
| 32 | #include <linux/module.h> | 11 | #include <linux/module.h> |
| @@ -34,23 +13,43 @@ | |||
| 34 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
| 35 | #include <linux/time.h> | 14 | #include <linux/time.h> |
| 36 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
| 16 | #include <linux/delay.h> | ||
| 37 | 17 | ||
| 38 | #include <asm/blackfin.h> | 18 | #include <asm/blackfin.h> |
| 39 | #include <asm/time.h> | 19 | #include <asm/time.h> |
| 20 | #include <asm/gptimers.h> | ||
| 40 | 21 | ||
| 41 | /* This is an NTP setting */ | 22 | /* This is an NTP setting */ |
| 42 | #define TICK_SIZE (tick_nsec / 1000) | 23 | #define TICK_SIZE (tick_nsec / 1000) |
| 43 | 24 | ||
| 44 | static void time_sched_init(irq_handler_t timer_routine); | ||
| 45 | static unsigned long gettimeoffset(void); | ||
| 46 | |||
| 47 | static struct irqaction bfin_timer_irq = { | 25 | static struct irqaction bfin_timer_irq = { |
| 48 | .name = "BFIN Timer Tick", | 26 | .name = "Blackfin Timer Tick", |
| 27 | #ifdef CONFIG_IRQ_PER_CPU | ||
| 28 | .flags = IRQF_DISABLED | IRQF_PERCPU, | ||
| 29 | #else | ||
| 49 | .flags = IRQF_DISABLED | 30 | .flags = IRQF_DISABLED |
| 31 | #endif | ||
| 50 | }; | 32 | }; |
| 51 | 33 | ||
| 52 | static void | 34 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) |
| 53 | time_sched_init(irq_handler_t timer_routine) | 35 | void __init setup_system_timer0(void) |
| 36 | { | ||
| 37 | /* Power down the core timer, just to play safe. */ | ||
| 38 | bfin_write_TCNTL(0); | ||
| 39 | |||
| 40 | disable_gptimers(TIMER0bit); | ||
| 41 | set_gptimer_status(0, TIMER_STATUS_TRUN0); | ||
| 42 | while (get_gptimer_status(0) & TIMER_STATUS_TRUN0) | ||
| 43 | udelay(10); | ||
| 44 | |||
| 45 | set_gptimer_config(0, 0x59); /* IRQ enable, periodic, PWM_OUT, SCLKed, OUT PAD disabled */ | ||
| 46 | set_gptimer_period(TIMER0_id, get_sclk() / HZ); | ||
| 47 | set_gptimer_pwidth(TIMER0_id, 1); | ||
| 48 | SSYNC(); | ||
| 49 | enable_gptimers(TIMER0bit); | ||
| 50 | } | ||
| 51 | #else | ||
| 52 | void __init setup_core_timer(void) | ||
| 54 | { | 53 | { |
| 55 | u32 tcount; | 54 | u32 tcount; |
| 56 | 55 | ||
| @@ -58,10 +57,8 @@ time_sched_init(irq_handler_t timer_routine) | |||
| 58 | bfin_write_TCNTL(1); | 57 | bfin_write_TCNTL(1); |
| 59 | CSYNC(); | 58 | CSYNC(); |
| 60 | 59 | ||
| 61 | /* | 60 | /* the TSCALE prescaler counter */ |
| 62 | * the TSCALE prescaler counter. | 61 | bfin_write_TSCALE(TIME_SCALE - 1); |
| 63 | */ | ||
| 64 | bfin_write_TSCALE((TIME_SCALE - 1)); | ||
| 65 | 62 | ||
| 66 | tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); | 63 | tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1); |
| 67 | bfin_write_TPERIOD(tcount); | 64 | bfin_write_TPERIOD(tcount); |
| @@ -71,35 +68,52 @@ time_sched_init(irq_handler_t timer_routine) | |||
| 71 | CSYNC(); | 68 | CSYNC(); |
| 72 | 69 | ||
| 73 | bfin_write_TCNTL(7); | 70 | bfin_write_TCNTL(7); |
| 71 | } | ||
| 72 | #endif | ||
| 74 | 73 | ||
| 75 | bfin_timer_irq.handler = (irq_handler_t)timer_routine; | 74 | static void __init |
| 76 | /* call setup_irq instead of request_irq because request_irq calls | 75 | time_sched_init(irqreturn_t(*timer_routine) (int, void *)) |
| 77 | * kmalloc which has not been initialized yet | 76 | { |
| 78 | */ | 77 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) |
| 78 | setup_system_timer0(); | ||
| 79 | bfin_timer_irq.handler = timer_routine; | ||
| 80 | setup_irq(IRQ_TIMER0, &bfin_timer_irq); | ||
| 81 | #else | ||
| 82 | setup_core_timer(); | ||
| 83 | bfin_timer_irq.handler = timer_routine; | ||
| 79 | setup_irq(IRQ_CORETMR, &bfin_timer_irq); | 84 | setup_irq(IRQ_CORETMR, &bfin_timer_irq); |
| 85 | #endif | ||
| 80 | } | 86 | } |
| 81 | 87 | ||
| 82 | /* | 88 | /* |
| 83 | * Should return useconds since last timer tick | 89 | * Should return useconds since last timer tick |
| 84 | */ | 90 | */ |
| 91 | #ifndef CONFIG_GENERIC_TIME | ||
| 85 | static unsigned long gettimeoffset(void) | 92 | static unsigned long gettimeoffset(void) |
| 86 | { | 93 | { |
| 87 | unsigned long offset; | 94 | unsigned long offset; |
| 88 | unsigned long clocks_per_jiffy; | 95 | unsigned long clocks_per_jiffy; |
| 89 | 96 | ||
| 97 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | ||
| 98 | clocks_per_jiffy = bfin_read_TIMER0_PERIOD(); | ||
| 99 | offset = bfin_read_TIMER0_COUNTER() / \ | ||
| 100 | (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC); | ||
| 101 | |||
| 102 | if ((get_gptimer_status(0) & TIMER_STATUS_TIMIL0) && offset < (100000 / HZ / 2)) | ||
| 103 | offset += (USEC_PER_SEC / HZ); | ||
| 104 | #else | ||
| 90 | clocks_per_jiffy = bfin_read_TPERIOD(); | 105 | clocks_per_jiffy = bfin_read_TPERIOD(); |
| 91 | offset = | 106 | offset = (clocks_per_jiffy - bfin_read_TCOUNT()) / \ |
| 92 | (clocks_per_jiffy - | 107 | (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC); |
| 93 | bfin_read_TCOUNT()) / (((clocks_per_jiffy + 1) * HZ) / | ||
| 94 | USEC_PER_SEC); | ||
| 95 | 108 | ||
| 96 | /* Check if we just wrapped the counters and maybe missed a tick */ | 109 | /* Check if we just wrapped the counters and maybe missed a tick */ |
| 97 | if ((bfin_read_ILAT() & (1 << IRQ_CORETMR)) | 110 | if ((bfin_read_ILAT() & (1 << IRQ_CORETMR)) |
| 98 | && (offset < (100000 / HZ / 2))) | 111 | && (offset < (100000 / HZ / 2))) |
| 99 | offset += (USEC_PER_SEC / HZ); | 112 | offset += (USEC_PER_SEC / HZ); |
| 100 | 113 | #endif | |
| 101 | return offset; | 114 | return offset; |
| 102 | } | 115 | } |
| 116 | #endif | ||
| 103 | 117 | ||
| 104 | static inline int set_rtc_mmss(unsigned long nowtime) | 118 | static inline int set_rtc_mmss(unsigned long nowtime) |
| 105 | { | 119 | { |
| @@ -111,43 +125,49 @@ static inline int set_rtc_mmss(unsigned long nowtime) | |||
| 111 | * as well as call the "do_timer()" routine every clocktick | 125 | * as well as call the "do_timer()" routine every clocktick |
| 112 | */ | 126 | */ |
| 113 | #ifdef CONFIG_CORE_TIMER_IRQ_L1 | 127 | #ifdef CONFIG_CORE_TIMER_IRQ_L1 |
| 114 | irqreturn_t timer_interrupt(int irq, void *dummy)__attribute__((l1_text)); | 128 | __attribute__((l1_text)) |
| 115 | #endif | 129 | #endif |
| 116 | |||
| 117 | irqreturn_t timer_interrupt(int irq, void *dummy) | 130 | irqreturn_t timer_interrupt(int irq, void *dummy) |
| 118 | { | 131 | { |
| 119 | /* last time the cmos clock got updated */ | 132 | /* last time the cmos clock got updated */ |
| 120 | static long last_rtc_update; | 133 | static long last_rtc_update; |
| 121 | 134 | ||
| 122 | write_seqlock(&xtime_lock); | 135 | write_seqlock(&xtime_lock); |
| 123 | 136 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) | |
| 124 | do_timer(1); | 137 | /* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */ |
| 125 | 138 | if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { | |
| 126 | profile_tick(CPU_PROFILING); | 139 | #endif |
| 127 | 140 | do_timer(1); | |
| 128 | /* | 141 | |
| 129 | * If we have an externally synchronized Linux clock, then update | 142 | /* |
| 130 | * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be | 143 | * If we have an externally synchronized Linux clock, then update |
| 131 | * called as close as possible to 500 ms before the new second starts. | 144 | * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be |
| 132 | */ | 145 | * called as close as possible to 500 ms before the new second starts. |
| 133 | 146 | */ | |
| 134 | if (ntp_synced() && | 147 | if (ntp_synced() && |
| 135 | xtime.tv_sec > last_rtc_update + 660 && | 148 | xtime.tv_sec > last_rtc_update + 660 && |
| 136 | (xtime.tv_nsec / NSEC_PER_USEC) >= | 149 | (xtime.tv_nsec / NSEC_PER_USEC) >= |
| 137 | 500000 - ((unsigned)TICK_SIZE) / 2 | 150 | 500000 - ((unsigned)TICK_SIZE) / 2 |
| 138 | && (xtime.tv_nsec / NSEC_PER_USEC) <= | 151 | && (xtime.tv_nsec / NSEC_PER_USEC) <= |
| 139 | 500000 + ((unsigned)TICK_SIZE) / 2) { | 152 | 500000 + ((unsigned)TICK_SIZE) / 2) { |
| 140 | if (set_rtc_mmss(xtime.tv_sec) == 0) | 153 | if (set_rtc_mmss(xtime.tv_sec) == 0) |
| 141 | last_rtc_update = xtime.tv_sec; | 154 | last_rtc_update = xtime.tv_sec; |
| 142 | else | 155 | else |
| 143 | /* Do it again in 60s. */ | 156 | /* Do it again in 60s. */ |
| 144 | last_rtc_update = xtime.tv_sec - 600; | 157 | last_rtc_update = xtime.tv_sec - 600; |
| 158 | } | ||
| 159 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) | ||
| 160 | set_gptimer_status(0, TIMER_STATUS_TIMIL0); | ||
| 145 | } | 161 | } |
| 162 | #endif | ||
| 146 | write_sequnlock(&xtime_lock); | 163 | write_sequnlock(&xtime_lock); |
| 147 | 164 | ||
| 148 | #ifndef CONFIG_SMP | 165 | #ifdef CONFIG_IPIPE |
| 166 | update_root_process_times(get_irq_regs()); | ||
| 167 | #else | ||
| 149 | update_process_times(user_mode(get_irq_regs())); | 168 | update_process_times(user_mode(get_irq_regs())); |
| 150 | #endif | 169 | #endif |
| 170 | profile_tick(CPU_PROFILING); | ||
| 151 | 171 | ||
| 152 | return IRQ_HANDLED; | 172 | return IRQ_HANDLED; |
| 153 | } | 173 | } |
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c index bef025b07443..17d8e4172896 100644 --- a/arch/blackfin/kernel/traps.c +++ b/arch/blackfin/kernel/traps.c | |||
| @@ -75,16 +75,6 @@ void __init trap_init(void) | |||
| 75 | CSYNC(); | 75 | CSYNC(); |
| 76 | } | 76 | } |
| 77 | 77 | ||
| 78 | /* | ||
| 79 | * Used to save the RETX, SEQSTAT, I/D CPLB FAULT ADDR | ||
| 80 | * values across the transition from exception to IRQ5. | ||
| 81 | * We put these in L1, so they are going to be in a valid | ||
| 82 | * location during exception context | ||
| 83 | */ | ||
| 84 | __attribute__((l1_data)) | ||
| 85 | unsigned long saved_retx, saved_seqstat, | ||
| 86 | saved_icplb_fault_addr, saved_dcplb_fault_addr; | ||
| 87 | |||
| 88 | static void decode_address(char *buf, unsigned long address) | 78 | static void decode_address(char *buf, unsigned long address) |
| 89 | { | 79 | { |
| 90 | #ifdef CONFIG_DEBUG_VERBOSE | 80 | #ifdef CONFIG_DEBUG_VERBOSE |
| @@ -211,18 +201,18 @@ asmlinkage void double_fault_c(struct pt_regs *fp) | |||
| 211 | printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n"); | 201 | printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n"); |
| 212 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT | 202 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT |
| 213 | if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) { | 203 | if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) { |
| 204 | unsigned int cpu = smp_processor_id(); | ||
| 214 | char buf[150]; | 205 | char buf[150]; |
| 215 | decode_address(buf, saved_retx); | 206 | decode_address(buf, cpu_pda[cpu].retx); |
| 216 | printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n", | 207 | printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n", |
| 217 | (int)saved_seqstat & SEQSTAT_EXCAUSE, buf); | 208 | (unsigned int)cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE, buf); |
| 218 | decode_address(buf, saved_dcplb_fault_addr); | 209 | decode_address(buf, cpu_pda[cpu].dcplb_fault_addr); |
| 219 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf); | 210 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf); |
| 220 | decode_address(buf, saved_icplb_fault_addr); | 211 | decode_address(buf, cpu_pda[cpu].icplb_fault_addr); |
| 221 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf); | 212 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf); |
| 222 | 213 | ||
| 223 | decode_address(buf, fp->retx); | 214 | decode_address(buf, fp->retx); |
| 224 | printk(KERN_NOTICE "The instruction at %s caused a double exception\n", | 215 | printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf); |
| 225 | buf); | ||
| 226 | } else | 216 | } else |
| 227 | #endif | 217 | #endif |
| 228 | { | 218 | { |
| @@ -240,6 +230,9 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 240 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON | 230 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON |
| 241 | int j; | 231 | int j; |
| 242 | #endif | 232 | #endif |
| 233 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO | ||
| 234 | unsigned int cpu = smp_processor_id(); | ||
| 235 | #endif | ||
| 243 | int sig = 0; | 236 | int sig = 0; |
| 244 | siginfo_t info; | 237 | siginfo_t info; |
| 245 | unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE; | 238 | unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE; |
| @@ -417,7 +410,7 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 417 | info.si_code = ILL_CPLB_MULHIT; | 410 | info.si_code = ILL_CPLB_MULHIT; |
| 418 | sig = SIGSEGV; | 411 | sig = SIGSEGV; |
| 419 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO | 412 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO |
| 420 | if (saved_dcplb_fault_addr < FIXED_CODE_START) | 413 | if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START) |
| 421 | verbose_printk(KERN_NOTICE "NULL pointer access\n"); | 414 | verbose_printk(KERN_NOTICE "NULL pointer access\n"); |
| 422 | else | 415 | else |
| 423 | #endif | 416 | #endif |
| @@ -471,7 +464,7 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 471 | info.si_code = ILL_CPLB_MULHIT; | 464 | info.si_code = ILL_CPLB_MULHIT; |
| 472 | sig = SIGSEGV; | 465 | sig = SIGSEGV; |
| 473 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO | 466 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO |
| 474 | if (saved_icplb_fault_addr < FIXED_CODE_START) | 467 | if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START) |
| 475 | verbose_printk(KERN_NOTICE "Jump to NULL address\n"); | 468 | verbose_printk(KERN_NOTICE "Jump to NULL address\n"); |
| 476 | else | 469 | else |
| 477 | #endif | 470 | #endif |
| @@ -584,10 +577,15 @@ asmlinkage void trap_c(struct pt_regs *fp) | |||
| 584 | } | 577 | } |
| 585 | } | 578 | } |
| 586 | 579 | ||
| 587 | info.si_signo = sig; | 580 | #ifdef CONFIG_IPIPE |
| 588 | info.si_errno = 0; | 581 | if (!ipipe_trap_notify(fp->seqstat & 0x3f, fp)) |
| 589 | info.si_addr = (void __user *)fp->pc; | 582 | #endif |
| 590 | force_sig_info(sig, &info, current); | 583 | { |
| 584 | info.si_signo = sig; | ||
| 585 | info.si_errno = 0; | ||
| 586 | info.si_addr = (void __user *)fp->pc; | ||
| 587 | force_sig_info(sig, &info, current); | ||
| 588 | } | ||
| 591 | 589 | ||
| 592 | trace_buffer_restore(j); | 590 | trace_buffer_restore(j); |
| 593 | return; | 591 | return; |
| @@ -656,13 +654,13 @@ static bool get_instruction(unsigned short *val, unsigned short *address) | |||
| 656 | return false; | 654 | return false; |
| 657 | } | 655 | } |
| 658 | 656 | ||
| 659 | /* | 657 | /* |
| 660 | * decode the instruction if we are printing out the trace, as it | 658 | * decode the instruction if we are printing out the trace, as it |
| 661 | * makes things easier to follow, without running it through objdump | 659 | * makes things easier to follow, without running it through objdump |
| 662 | * These are the normal instructions which cause change of flow, which | 660 | * These are the normal instructions which cause change of flow, which |
| 663 | * would be at the source of the trace buffer | 661 | * would be at the source of the trace buffer |
| 664 | */ | 662 | */ |
| 665 | #ifdef CONFIG_DEBUG_VERBOSE | 663 | #if defined(CONFIG_DEBUG_VERBOSE) && defined(CONFIG_DEBUG_BFIN_HWTRACE_ON) |
| 666 | static void decode_instruction(unsigned short *address) | 664 | static void decode_instruction(unsigned short *address) |
| 667 | { | 665 | { |
| 668 | unsigned short opcode; | 666 | unsigned short opcode; |
| @@ -846,7 +844,7 @@ void show_stack(struct task_struct *task, unsigned long *stack) | |||
| 846 | } | 844 | } |
| 847 | if (fp) { | 845 | if (fp) { |
| 848 | frame = fp; | 846 | frame = fp; |
| 849 | printk(" FP: (0x%p)\n", fp); | 847 | printk(KERN_NOTICE " FP: (0x%p)\n", fp); |
| 850 | } else | 848 | } else |
| 851 | frame = 0; | 849 | frame = 0; |
| 852 | 850 | ||
| @@ -960,6 +958,7 @@ void dump_bfin_process(struct pt_regs *fp) | |||
| 960 | else | 958 | else |
| 961 | verbose_printk(KERN_NOTICE "COMM= invalid\n"); | 959 | verbose_printk(KERN_NOTICE "COMM= invalid\n"); |
| 962 | 960 | ||
| 961 | printk(KERN_NOTICE "CPU = %d\n", current_thread_info()->cpu); | ||
| 963 | if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) | 962 | if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) |
| 964 | verbose_printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" | 963 | verbose_printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" |
| 965 | KERN_NOTICE " BSS = 0x%p-0x%p USER-STACK = 0x%p\n" | 964 | KERN_NOTICE " BSS = 0x%p-0x%p USER-STACK = 0x%p\n" |
| @@ -1053,6 +1052,7 @@ void show_regs(struct pt_regs *fp) | |||
| 1053 | struct irqaction *action; | 1052 | struct irqaction *action; |
| 1054 | unsigned int i; | 1053 | unsigned int i; |
| 1055 | unsigned long flags; | 1054 | unsigned long flags; |
| 1055 | unsigned int cpu = smp_processor_id(); | ||
| 1056 | 1056 | ||
| 1057 | verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted()); | 1057 | verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted()); |
| 1058 | verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", | 1058 | verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", |
| @@ -1112,9 +1112,9 @@ unlock: | |||
| 1112 | 1112 | ||
| 1113 | if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && | 1113 | if (((long)fp->seqstat & SEQSTAT_EXCAUSE) && |
| 1114 | (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { | 1114 | (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) { |
| 1115 | decode_address(buf, saved_dcplb_fault_addr); | 1115 | decode_address(buf, cpu_pda[cpu].dcplb_fault_addr); |
| 1116 | verbose_printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf); | 1116 | verbose_printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf); |
| 1117 | decode_address(buf, saved_icplb_fault_addr); | 1117 | decode_address(buf, cpu_pda[cpu].icplb_fault_addr); |
| 1118 | verbose_printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf); | 1118 | verbose_printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf); |
| 1119 | } | 1119 | } |
| 1120 | 1120 | ||
| @@ -1153,20 +1153,21 @@ unlock: | |||
| 1153 | asmlinkage int sys_bfin_spinlock(int *spinlock)__attribute__((l1_text)); | 1153 | asmlinkage int sys_bfin_spinlock(int *spinlock)__attribute__((l1_text)); |
| 1154 | #endif | 1154 | #endif |
| 1155 | 1155 | ||
| 1156 | asmlinkage int sys_bfin_spinlock(int *spinlock) | 1156 | static DEFINE_SPINLOCK(bfin_spinlock_lock); |
| 1157 | |||
| 1158 | asmlinkage int sys_bfin_spinlock(int *p) | ||
| 1157 | { | 1159 | { |
| 1158 | int ret = 0; | 1160 | int ret, tmp = 0; |
| 1159 | int tmp = 0; | ||
| 1160 | 1161 | ||
| 1161 | local_irq_disable(); | 1162 | spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */ |
| 1162 | ret = get_user(tmp, spinlock); | 1163 | ret = get_user(tmp, p); |
| 1163 | if (ret == 0) { | 1164 | if (likely(ret == 0)) { |
| 1164 | if (tmp) | 1165 | if (unlikely(tmp)) |
| 1165 | ret = 1; | 1166 | ret = 1; |
| 1166 | tmp = 1; | 1167 | else |
| 1167 | put_user(tmp, spinlock); | 1168 | put_user(1, p); |
| 1168 | } | 1169 | } |
| 1169 | local_irq_enable(); | 1170 | spin_unlock(&bfin_spinlock_lock); |
| 1170 | return ret; | 1171 | return ret; |
| 1171 | } | 1172 | } |
| 1172 | 1173 | ||
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S index 7d12c6692a65..4b4341da0585 100644 --- a/arch/blackfin/kernel/vmlinux.lds.S +++ b/arch/blackfin/kernel/vmlinux.lds.S | |||
| @@ -68,6 +68,8 @@ SECTIONS | |||
| 68 | __etext = .; | 68 | __etext = .; |
| 69 | } | 69 | } |
| 70 | 70 | ||
| 71 | NOTES | ||
| 72 | |||
| 71 | /* Just in case the first read only is a 32-bit access */ | 73 | /* Just in case the first read only is a 32-bit access */ |
| 72 | RO_DATA(4) | 74 | RO_DATA(4) |
| 73 | 75 | ||
| @@ -109,7 +111,6 @@ SECTIONS | |||
| 109 | #endif | 111 | #endif |
| 110 | 112 | ||
| 111 | DATA_DATA | 113 | DATA_DATA |
| 112 | *(.data.*) | ||
| 113 | CONSTRUCTORS | 114 | CONSTRUCTORS |
| 114 | 115 | ||
| 115 | /* make sure the init_task is aligned to the | 116 | /* make sure the init_task is aligned to the |
| @@ -161,12 +162,14 @@ SECTIONS | |||
| 161 | *(.con_initcall.init) | 162 | *(.con_initcall.init) |
| 162 | ___con_initcall_end = .; | 163 | ___con_initcall_end = .; |
| 163 | } | 164 | } |
| 165 | PERCPU(4) | ||
| 164 | SECURITY_INIT | 166 | SECURITY_INIT |
| 165 | .init.ramfs : | 167 | .init.ramfs : |
| 166 | { | 168 | { |
| 167 | . = ALIGN(4); | 169 | . = ALIGN(4); |
| 168 | ___initramfs_start = .; | 170 | ___initramfs_start = .; |
| 169 | *(.init.ramfs) | 171 | *(.init.ramfs) |
| 172 | . = ALIGN(4); | ||
| 170 | ___initramfs_end = .; | 173 | ___initramfs_end = .; |
| 171 | } | 174 | } |
| 172 | 175 | ||
| @@ -212,7 +215,7 @@ SECTIONS | |||
| 212 | __ebss_b_l1 = .; | 215 | __ebss_b_l1 = .; |
| 213 | } | 216 | } |
| 214 | 217 | ||
| 215 | __l2_lma_start = .; | 218 | __l2_lma_start = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); |
| 216 | 219 | ||
| 217 | .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1)) | 220 | .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1)) |
| 218 | { | 221 | { |
| @@ -240,7 +243,7 @@ SECTIONS | |||
| 240 | /* Force trailing alignment of our init section so that when we | 243 | /* Force trailing alignment of our init section so that when we |
| 241 | * free our init memory, we don't leave behind a partial page. | 244 | * free our init memory, we don't leave behind a partial page. |
| 242 | */ | 245 | */ |
| 243 | . = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); | 246 | . = LOADADDR(.text_data_l2) + SIZEOF(.text_data_l2); |
| 244 | . = ALIGN(PAGE_SIZE); | 247 | . = ALIGN(PAGE_SIZE); |
| 245 | ___init_end = .; | 248 | ___init_end = .; |
| 246 | 249 | ||
diff --git a/arch/blackfin/lib/checksum.c b/arch/blackfin/lib/checksum.c index 5c87505165d3..762a7f02970a 100644 --- a/arch/blackfin/lib/checksum.c +++ b/arch/blackfin/lib/checksum.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 29 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 30 | */ | 30 | */ |
| 31 | 31 | ||
| 32 | #include <linux/module.h> | ||
| 32 | #include <net/checksum.h> | 33 | #include <net/checksum.h> |
| 33 | #include <asm/checksum.h> | 34 | #include <asm/checksum.h> |
| 34 | 35 | ||
| @@ -76,6 +77,7 @@ __sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl) | |||
| 76 | { | 77 | { |
| 77 | return (__force __sum16)~do_csum(iph, ihl * 4); | 78 | return (__force __sum16)~do_csum(iph, ihl * 4); |
| 78 | } | 79 | } |
| 80 | EXPORT_SYMBOL(ip_fast_csum); | ||
| 79 | 81 | ||
| 80 | /* | 82 | /* |
| 81 | * computes the checksum of a memory block at buff, length len, | 83 | * computes the checksum of a memory block at buff, length len, |
| @@ -104,6 +106,7 @@ __wsum csum_partial(const void *buff, int len, __wsum sum) | |||
| 104 | 106 | ||
| 105 | return sum; | 107 | return sum; |
| 106 | } | 108 | } |
| 109 | EXPORT_SYMBOL(csum_partial); | ||
| 107 | 110 | ||
| 108 | /* | 111 | /* |
| 109 | * this routine is used for miscellaneous IP-like checksums, mainly | 112 | * this routine is used for miscellaneous IP-like checksums, mainly |
| @@ -137,3 +140,4 @@ __wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum) | |||
| 137 | memcpy(dst, src, len); | 140 | memcpy(dst, src, len); |
| 138 | return csum_partial(dst, len, sum); | 141 | return csum_partial(dst, len, sum); |
| 139 | } | 142 | } |
| 143 | EXPORT_SYMBOL(csum_partial_copy); | ||
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S index d60554dce87b..1863a6ba507c 100644 --- a/arch/blackfin/lib/ins.S +++ b/arch/blackfin/lib/ins.S | |||
| @@ -1,31 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: arch/blackfin/lib/ins.S | 2 | * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops |
| 3 | * Based on: | ||
| 4 | * Author: Bas Vermeulen <bas@buyways.nl> | ||
| 5 | * | 3 | * |
| 6 | * Created: Tue Mar 22 15:27:24 CEST 2005 | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 7 | * Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops. | 5 | * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl> |
| 8 | * | 6 | * Licensed under the GPL-2 or later. |
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 11 | * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl> | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | 7 | */ |
| 30 | 8 | ||
| 31 | #include <linux/linkage.h> | 9 | #include <linux/linkage.h> |
| @@ -33,6 +11,46 @@ | |||
| 33 | 11 | ||
| 34 | .align 2 | 12 | .align 2 |
| 35 | 13 | ||
| 14 | #ifdef CONFIG_IPIPE | ||
| 15 | # define DO_CLI \ | ||
| 16 | [--sp] = rets; \ | ||
| 17 | [--sp] = (P5:0); \ | ||
| 18 | sp += -12; \ | ||
| 19 | call ___ipipe_stall_root_raw; \ | ||
| 20 | sp += 12; \ | ||
| 21 | (P5:0) = [sp++]; | ||
| 22 | # define CLI_INNER_NOP | ||
| 23 | #else | ||
| 24 | # define DO_CLI cli R3; | ||
| 25 | # define CLI_INNER_NOP nop; nop; nop; | ||
| 26 | #endif | ||
| 27 | |||
| 28 | #ifdef CONFIG_IPIPE | ||
| 29 | # define DO_STI \ | ||
| 30 | sp += -12; \ | ||
| 31 | call ___ipipe_unstall_root_raw; \ | ||
| 32 | sp += 12; \ | ||
| 33 | 2: rets = [sp++]; | ||
| 34 | #else | ||
| 35 | # define DO_STI 2: sti R3; | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #ifdef CONFIG_BFIN_INS_LOWOVERHEAD | ||
| 39 | # define CLI_OUTER DO_CLI; | ||
| 40 | # define STI_OUTER DO_STI; | ||
| 41 | # define CLI_INNER 1: | ||
| 42 | # if ANOMALY_05000416 | ||
| 43 | # define STI_INNER nop; 2: nop; | ||
| 44 | # else | ||
| 45 | # define STI_INNER 2: | ||
| 46 | # endif | ||
| 47 | #else | ||
| 48 | # define CLI_OUTER | ||
| 49 | # define STI_OUTER | ||
| 50 | # define CLI_INNER 1: DO_CLI; CLI_INNER_NOP; | ||
| 51 | # define STI_INNER DO_STI; | ||
| 52 | #endif | ||
| 53 | |||
| 36 | /* | 54 | /* |
| 37 | * Reads on the Blackfin are speculative. In Blackfin terms, this means they | 55 | * Reads on the Blackfin are speculative. In Blackfin terms, this means they |
| 38 | * can be interrupted at any time (even after they have been issued on to the | 56 | * can be interrupted at any time (even after they have been issued on to the |
| @@ -53,170 +71,48 @@ | |||
| 53 | * buffers in/out of FIFOs. | 71 | * buffers in/out of FIFOs. |
| 54 | */ | 72 | */ |
| 55 | 73 | ||
| 56 | ENTRY(_insl) | 74 | #define COMMON_INS(func, ops) \ |
| 57 | #ifdef CONFIG_BFIN_INS_LOWOVERHEAD | 75 | ENTRY(_ins##func) \ |
| 58 | P0 = R0; /* P0 = port */ | 76 | P0 = R0; /* P0 = port */ \ |
| 59 | cli R3; | 77 | CLI_OUTER; /* 3 instructions before first read access */ \ |
| 60 | P1 = R1; /* P1 = address */ | 78 | P1 = R1; /* P1 = address */ \ |
| 61 | P2 = R2; /* P2 = count */ | 79 | P2 = R2; /* P2 = count */ \ |
| 62 | SSYNC; | 80 | SSYNC; \ |
| 63 | LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2; | 81 | \ |
| 64 | .Llong_loop_s: R0 = [P0]; | 82 | LSETUP(1f, 2f) LC0 = P2; \ |
| 65 | [P1++] = R0; | 83 | CLI_INNER; \ |
| 66 | NOP; | 84 | ops; \ |
| 67 | .Llong_loop_e: NOP; | 85 | STI_INNER; \ |
| 68 | sti R3; | 86 | \ |
| 69 | RTS; | 87 | STI_OUTER; \ |
| 70 | #else | 88 | RTS; \ |
| 71 | P0 = R0; /* P0 = port */ | 89 | ENDPROC(_ins##func) |
| 72 | P1 = R1; /* P1 = address */ | ||
| 73 | P2 = R2; /* P2 = count */ | ||
| 74 | SSYNC; | ||
| 75 | LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2; | ||
| 76 | .Llong_loop_s: | ||
| 77 | CLI R3; | ||
| 78 | NOP; NOP; NOP; | ||
| 79 | R0 = [P0]; | ||
| 80 | [P1++] = R0; | ||
| 81 | .Llong_loop_e: | ||
| 82 | STI R3; | ||
| 83 | 90 | ||
| 84 | RTS; | 91 | COMMON_INS(l, \ |
| 85 | #endif | 92 | R0 = [P0]; \ |
| 86 | ENDPROC(_insl) | 93 | [P1++] = R0; \ |
| 87 | 94 | ) | |
| 88 | ENTRY(_insw) | ||
| 89 | #ifdef CONFIG_BFIN_INS_LOWOVERHEAD | ||
| 90 | P0 = R0; /* P0 = port */ | ||
| 91 | cli R3; | ||
| 92 | P1 = R1; /* P1 = address */ | ||
| 93 | P2 = R2; /* P2 = count */ | ||
| 94 | SSYNC; | ||
| 95 | LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2; | ||
| 96 | .Lword_loop_s: R0 = W[P0]; | ||
| 97 | W[P1++] = R0; | ||
| 98 | NOP; | ||
| 99 | .Lword_loop_e: NOP; | ||
| 100 | sti R3; | ||
| 101 | RTS; | ||
| 102 | #else | ||
| 103 | P0 = R0; /* P0 = port */ | ||
| 104 | P1 = R1; /* P1 = address */ | ||
| 105 | P2 = R2; /* P2 = count */ | ||
| 106 | SSYNC; | ||
| 107 | LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2; | ||
| 108 | .Lword_loop_s: | ||
| 109 | CLI R3; | ||
| 110 | NOP; NOP; NOP; | ||
| 111 | R0 = W[P0]; | ||
| 112 | W[P1++] = R0; | ||
| 113 | .Lword_loop_e: | ||
| 114 | STI R3; | ||
| 115 | RTS; | ||
| 116 | |||
| 117 | #endif | ||
| 118 | ENDPROC(_insw) | ||
| 119 | |||
| 120 | ENTRY(_insw_8) | ||
| 121 | #ifdef CONFIG_BFIN_INS_LOWOVERHEAD | ||
| 122 | P0 = R0; /* P0 = port */ | ||
| 123 | cli R3; | ||
| 124 | P1 = R1; /* P1 = address */ | ||
| 125 | P2 = R2; /* P2 = count */ | ||
| 126 | SSYNC; | ||
| 127 | LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; | ||
| 128 | .Lword8_loop_s: R0 = W[P0]; | ||
| 129 | B[P1++] = R0; | ||
| 130 | R0 = R0 >> 8; | ||
| 131 | B[P1++] = R0; | ||
| 132 | NOP; | ||
| 133 | .Lword8_loop_e: NOP; | ||
| 134 | sti R3; | ||
| 135 | RTS; | ||
| 136 | #else | ||
| 137 | P0 = R0; /* P0 = port */ | ||
| 138 | P1 = R1; /* P1 = address */ | ||
| 139 | P2 = R2; /* P2 = count */ | ||
| 140 | SSYNC; | ||
| 141 | LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; | ||
| 142 | .Lword8_loop_s: | ||
| 143 | CLI R3; | ||
| 144 | NOP; NOP; NOP; | ||
| 145 | R0 = W[P0]; | ||
| 146 | B[P1++] = R0; | ||
| 147 | R0 = R0 >> 8; | ||
| 148 | B[P1++] = R0; | ||
| 149 | NOP; | ||
| 150 | .Lword8_loop_e: | ||
| 151 | STI R3; | ||
| 152 | 95 | ||
| 153 | RTS; | 96 | COMMON_INS(w, \ |
| 154 | #endif | 97 | R0 = W[P0]; \ |
| 155 | ENDPROC(_insw_8) | 98 | W[P1++] = R0; \ |
| 99 | ) | ||
| 156 | 100 | ||
| 157 | ENTRY(_insb) | 101 | COMMON_INS(w_8, \ |
| 158 | #ifdef CONFIG_BFIN_INS_LOWOVERHEAD | 102 | R0 = W[P0]; \ |
| 159 | P0 = R0; /* P0 = port */ | 103 | B[P1++] = R0; \ |
| 160 | cli R3; | 104 | R0 = R0 >> 8; \ |
| 161 | P1 = R1; /* P1 = address */ | 105 | B[P1++] = R0; \ |
| 162 | P2 = R2; /* P2 = count */ | 106 | ) |
| 163 | SSYNC; | ||
| 164 | LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2; | ||
| 165 | .Lbyte_loop_s: R0 = B[P0]; | ||
| 166 | B[P1++] = R0; | ||
| 167 | NOP; | ||
| 168 | .Lbyte_loop_e: NOP; | ||
| 169 | sti R3; | ||
| 170 | RTS; | ||
| 171 | #else | ||
| 172 | P0 = R0; /* P0 = port */ | ||
| 173 | P1 = R1; /* P1 = address */ | ||
| 174 | P2 = R2; /* P2 = count */ | ||
| 175 | SSYNC; | ||
| 176 | LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2; | ||
| 177 | .Lbyte_loop_s: | ||
| 178 | CLI R3; | ||
| 179 | NOP; NOP; NOP; | ||
| 180 | R0 = B[P0]; | ||
| 181 | B[P1++] = R0; | ||
| 182 | .Lbyte_loop_e: | ||
| 183 | STI R3; | ||
| 184 | 107 | ||
| 185 | RTS; | 108 | COMMON_INS(b, \ |
| 186 | #endif | 109 | R0 = B[P0]; \ |
| 187 | ENDPROC(_insb) | 110 | B[P1++] = R0; \ |
| 111 | ) | ||
| 188 | 112 | ||
| 189 | ENTRY(_insl_16) | 113 | COMMON_INS(l_16, \ |
| 190 | #ifdef CONFIG_BFIN_INS_LOWOVERHEAD | 114 | R0 = [P0]; \ |
| 191 | P0 = R0; /* P0 = port */ | 115 | W[P1++] = R0; \ |
| 192 | cli R3; | 116 | R0 = R0 >> 16; \ |
| 193 | P1 = R1; /* P1 = address */ | 117 | W[P1++] = R0; \ |
| 194 | P2 = R2; /* P2 = count */ | 118 | ) |
| 195 | SSYNC; | ||
| 196 | LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2; | ||
| 197 | .Llong16_loop_s: R0 = [P0]; | ||
| 198 | W[P1++] = R0; | ||
| 199 | R0 = R0 >> 16; | ||
| 200 | W[P1++] = R0; | ||
| 201 | NOP; | ||
| 202 | .Llong16_loop_e: NOP; | ||
| 203 | sti R3; | ||
| 204 | RTS; | ||
| 205 | #else | ||
| 206 | P0 = R0; /* P0 = port */ | ||
| 207 | P1 = R1; /* P1 = address */ | ||
| 208 | P2 = R2; /* P2 = count */ | ||
| 209 | SSYNC; | ||
| 210 | LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2; | ||
| 211 | .Llong16_loop_s: | ||
| 212 | CLI R3; | ||
| 213 | NOP; NOP; NOP; | ||
| 214 | R0 = [P0]; | ||
| 215 | W[P1++] = R0; | ||
| 216 | R0 = R0 >> 16; | ||
| 217 | W[P1++] = R0; | ||
| 218 | .Llong16_loop_e: | ||
| 219 | STI R3; | ||
| 220 | RTS; | ||
| 221 | #endif | ||
| 222 | ENDPROC(_insl_16) | ||
diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S new file mode 100644 index 000000000000..abde120ee230 --- /dev/null +++ b/arch/blackfin/lib/muldi3.S | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | .align 2 | ||
| 2 | .global ___muldi3; | ||
| 3 | .type ___muldi3, STT_FUNC; | ||
| 4 | |||
| 5 | #ifdef CONFIG_ARITHMETIC_OPS_L1 | ||
| 6 | .section .l1.text | ||
| 7 | #else | ||
| 8 | .text | ||
| 9 | #endif | ||
| 10 | |||
| 11 | /* | ||
| 12 | R1:R0 * R3:R2 | ||
| 13 | = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l | ||
| 14 | [X] = (R1.h * R3.h) * 2^96 | ||
| 15 | [X] + (R1.h * R3.l + R1.l * R3.h) * 2^80 | ||
| 16 | [X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64 | ||
| 17 | [T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48 | ||
| 18 | [T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32 | ||
| 19 | [T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16 | ||
| 20 | [T4] + (R0.l * R2.l) | ||
| 21 | |||
| 22 | We can discard the first three lines marked "X" since we produce | ||
| 23 | only a 64 bit result. So, we need ten 16-bit multiplies. | ||
| 24 | |||
| 25 | Individual mul-acc results: | ||
| 26 | [E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h | ||
| 27 | [E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h | ||
| 28 | [E3] = R0.l * R2.h + R2.l * R0.h | ||
| 29 | [E4] = R0.l * R2.l | ||
| 30 | |||
| 31 | We also need to add high parts from lower-level results to higher ones: | ||
| 32 | E[n]c = E[n] + (E[n+1]c >> 16), where E4c := E4 | ||
| 33 | |||
| 34 | One interesting property is that all parts of the result that depend | ||
| 35 | on the sign of the multiplication are discarded. Those would be the | ||
| 36 | multiplications involving R1.h and R3.h, but only the top 16 bit of | ||
| 37 | the 32 bit result depend on the sign, and since R1.h and R3.h only | ||
| 38 | occur in E1, the top half of these results is cut off. | ||
| 39 | So, we can just use FU mode for all of the 16-bit multiplies, and | ||
| 40 | ignore questions of when to use mixed mode. */ | ||
| 41 | |||
| 42 | ___muldi3: | ||
| 43 | /* [SP] technically is part of the caller's frame, but we can | ||
| 44 | use it as scratch space. */ | ||
| 45 | A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */ | ||
| 46 | A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */ | ||
| 47 | A0 += A1; /* E1 */ | ||
| 48 | R4 = A0.w; | ||
| 49 | A0 = R0.l * R3.l (FU); /* E2 */ | ||
| 50 | A0 += R2.l * R1.l (FU); /* E2 */ | ||
| 51 | |||
| 52 | A1 = R2.L * R0.L (FU); /* E4 */ | ||
| 53 | R3 = A1.w; | ||
| 54 | A1 = A1 >> 16; /* E3c */ | ||
| 55 | A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */ | ||
| 56 | A1 += R0.L * R2.H (FU); /* E3c */ | ||
| 57 | R0 = A1.w; | ||
| 58 | A1 = A1 >> 16; /* E2c */ | ||
| 59 | A0 += A1; /* E2c */ | ||
| 60 | R1 = A0.w; | ||
| 61 | |||
| 62 | /* low(result) = low(E3c):low(E4) */ | ||
| 63 | R0 = PACK (R0.l, R3.l); | ||
| 64 | /* high(result) = E2c + (E1 << 16) */ | ||
| 65 | R1.h = R1.h + R4.l (NS) || R4 = [SP]; | ||
| 66 | RTS; | ||
| 67 | |||
| 68 | .size ___muldi3, .-___muldi3 | ||
diff --git a/arch/blackfin/lib/muldi3.c b/arch/blackfin/lib/muldi3.c deleted file mode 100644 index 303d0c6a6dba..000000000000 --- a/arch/blackfin/lib/muldi3.c +++ /dev/null | |||
| @@ -1,99 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/lib/muldi3.c | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #ifndef SI_TYPE_SIZE | ||
| 31 | #define SI_TYPE_SIZE 32 | ||
| 32 | #endif | ||
| 33 | #define __ll_b (1L << (SI_TYPE_SIZE / 2)) | ||
| 34 | #define __ll_lowpart(t) ((usitype) (t) % __ll_b) | ||
| 35 | #define __ll_highpart(t) ((usitype) (t) / __ll_b) | ||
| 36 | #define BITS_PER_UNIT 8 | ||
| 37 | |||
| 38 | #if !defined(umul_ppmm) | ||
| 39 | #define umul_ppmm(w1, w0, u, v) \ | ||
| 40 | do { \ | ||
| 41 | usitype __x0, __x1, __x2, __x3; \ | ||
| 42 | usitype __ul, __vl, __uh, __vh; \ | ||
| 43 | \ | ||
| 44 | __ul = __ll_lowpart (u); \ | ||
| 45 | __uh = __ll_highpart (u); \ | ||
| 46 | __vl = __ll_lowpart (v); \ | ||
| 47 | __vh = __ll_highpart (v); \ | ||
| 48 | \ | ||
| 49 | __x0 = (usitype) __ul * __vl; \ | ||
| 50 | __x1 = (usitype) __ul * __vh; \ | ||
| 51 | __x2 = (usitype) __uh * __vl; \ | ||
| 52 | __x3 = (usitype) __uh * __vh; \ | ||
| 53 | \ | ||
| 54 | __x1 += __ll_highpart (__x0);/* this can't give carry */ \ | ||
| 55 | __x1 += __x2; /* but this indeed can */ \ | ||
| 56 | if (__x1 < __x2) /* did we get it? */ \ | ||
| 57 | __x3 += __ll_b; /* yes, add it in the proper pos. */ \ | ||
| 58 | \ | ||
| 59 | (w1) = __x3 + __ll_highpart (__x1); \ | ||
| 60 | (w0) = __ll_lowpart (__x1) * __ll_b + __ll_lowpart (__x0); \ | ||
| 61 | } while (0) | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #if !defined(__umulsidi3) | ||
| 65 | #define __umulsidi3(u, v) \ | ||
| 66 | ({diunion __w; \ | ||
| 67 | umul_ppmm (__w.s.high, __w.s.low, u, v); \ | ||
| 68 | __w.ll; }) | ||
| 69 | #endif | ||
| 70 | |||
| 71 | typedef unsigned int usitype __attribute__ ((mode(SI))); | ||
| 72 | typedef int sitype __attribute__ ((mode(SI))); | ||
| 73 | typedef int ditype __attribute__ ((mode(DI))); | ||
| 74 | typedef int word_type __attribute__ ((mode(__word__))); | ||
| 75 | |||
| 76 | struct distruct { | ||
| 77 | sitype low, high; | ||
| 78 | }; | ||
| 79 | typedef union { | ||
| 80 | struct distruct s; | ||
| 81 | ditype ll; | ||
| 82 | } diunion; | ||
| 83 | |||
| 84 | #ifdef CONFIG_ARITHMETIC_OPS_L1 | ||
| 85 | ditype __muldi3(ditype u, ditype v)__attribute__((l1_text)); | ||
| 86 | #endif | ||
| 87 | |||
| 88 | ditype __muldi3(ditype u, ditype v) | ||
| 89 | { | ||
| 90 | diunion w; | ||
| 91 | diunion uu, vv; | ||
| 92 | |||
| 93 | uu.ll = u, vv.ll = v; | ||
| 94 | w.ll = __umulsidi3(uu.s.low, vv.s.low); | ||
| 95 | w.s.high += ((usitype) uu.s.low * (usitype) vv.s.high | ||
| 96 | + (usitype) uu.s.high * (usitype) vv.s.low); | ||
| 97 | |||
| 98 | return w.ll; | ||
| 99 | } | ||
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig new file mode 100644 index 000000000000..f397ede006bf --- /dev/null +++ b/arch/blackfin/mach-bf518/Kconfig | |||
| @@ -0,0 +1,233 @@ | |||
| 1 | if (BF51x) | ||
| 2 | |||
| 3 | source "arch/blackfin/mach-bf518/boards/Kconfig" | ||
| 4 | |||
| 5 | menu "BF518 Specific Configuration" | ||
| 6 | |||
| 7 | comment "Alternative Multiplexing Scheme" | ||
| 8 | |||
| 9 | choice | ||
| 10 | prompt "SPORT0" | ||
| 11 | default BF518_SPORT0_PORTG | ||
| 12 | help | ||
| 13 | Select PORT used for SPORT0. See Hardware Reference Manual | ||
| 14 | |||
| 15 | config BF518_SPORT0_PORTF | ||
| 16 | bool "PORT F" | ||
| 17 | help | ||
| 18 | PORT F | ||
| 19 | |||
| 20 | config BF518_SPORT0_PORTG | ||
| 21 | bool "PORT G" | ||
| 22 | help | ||
| 23 | PORT G | ||
| 24 | endchoice | ||
| 25 | |||
| 26 | choice | ||
| 27 | prompt "SPORT0 TSCLK Location" | ||
| 28 | depends on BF518_SPORT0_PORTG | ||
| 29 | default BF518_SPORT0_TSCLK_PG10 | ||
| 30 | help | ||
| 31 | Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual | ||
| 32 | |||
| 33 | config BF518_SPORT0_TSCLK_PG10 | ||
| 34 | bool "PORT PG10" | ||
| 35 | help | ||
| 36 | PORT PG10 | ||
| 37 | |||
| 38 | config BF518_SPORT0_TSCLK_PG14 | ||
| 39 | bool "PORT PG14" | ||
| 40 | help | ||
| 41 | PORT PG14 | ||
| 42 | endchoice | ||
| 43 | |||
| 44 | choice | ||
| 45 | prompt "UART1" | ||
| 46 | default BF518_UART1_PORTF | ||
| 47 | help | ||
| 48 | Select PORT used for UART1. See Hardware Reference Manual | ||
| 49 | |||
| 50 | config BF518_UART1_PORTF | ||
| 51 | bool "PORT F" | ||
| 52 | help | ||
| 53 | PORT F | ||
| 54 | |||
| 55 | config BF518_UART1_PORTG | ||
| 56 | bool "PORT G" | ||
| 57 | help | ||
| 58 | PORT G | ||
| 59 | endchoice | ||
| 60 | |||
| 61 | comment "Interrupt Priority Assignment" | ||
| 62 | menu "Priority" | ||
| 63 | |||
| 64 | config IRQ_PLL_WAKEUP | ||
| 65 | int "IRQ_PLL_WAKEUP" | ||
| 66 | default 7 | ||
| 67 | config IRQ_DMA0_ERROR | ||
| 68 | int "IRQ_DMA0_ERROR" | ||
| 69 | default 7 | ||
| 70 | config IRQ_DMAR0_BLK | ||
| 71 | int "IRQ_DMAR0_BLK" | ||
| 72 | default 7 | ||
| 73 | config IRQ_DMAR1_BLK | ||
| 74 | int "IRQ_DMAR1_BLK" | ||
| 75 | default 7 | ||
| 76 | config IRQ_DMAR0_OVR | ||
| 77 | int "IRQ_DMAR0_OVR" | ||
| 78 | default 7 | ||
| 79 | config IRQ_DMAR1_OVR | ||
| 80 | int "IRQ_DMAR1_OVR" | ||
| 81 | default 7 | ||
| 82 | config IRQ_PPI_ERROR | ||
| 83 | int "IRQ_PPI_ERROR" | ||
| 84 | default 7 | ||
| 85 | config IRQ_MAC_ERROR | ||
| 86 | int "IRQ_MAC_ERROR" | ||
| 87 | default 7 | ||
| 88 | config IRQ_SPORT0_ERROR | ||
| 89 | int "IRQ_SPORT0_ERROR" | ||
| 90 | default 7 | ||
| 91 | config IRQ_SPORT1_ERROR | ||
| 92 | int "IRQ_SPORT1_ERROR" | ||
| 93 | default 7 | ||
| 94 | config IRQ_PTP_ERROR | ||
| 95 | int "IRQ_PTP_ERROR" | ||
| 96 | default 7 | ||
| 97 | config IRQ_UART0_ERROR | ||
| 98 | int "IRQ_UART0_ERROR" | ||
| 99 | default 7 | ||
| 100 | config IRQ_UART1_ERROR | ||
| 101 | int "IRQ_UART1_ERROR" | ||
| 102 | default 7 | ||
| 103 | config IRQ_RTC | ||
| 104 | int "IRQ_RTC" | ||
| 105 | default 8 | ||
| 106 | config IRQ_PPI | ||
| 107 | int "IRQ_PPI" | ||
| 108 | default 8 | ||
| 109 | config IRQ_SPORT0_RX | ||
| 110 | int "IRQ_SPORT0_RX" | ||
| 111 | default 9 | ||
| 112 | config IRQ_SPORT0_TX | ||
| 113 | int "IRQ_SPORT0_TX" | ||
| 114 | default 9 | ||
| 115 | config IRQ_SPORT1_RX | ||
| 116 | int "IRQ_SPORT1_RX" | ||
| 117 | default 9 | ||
| 118 | config IRQ_SPORT1_TX | ||
| 119 | int "IRQ_SPORT1_TX" | ||
| 120 | default 9 | ||
| 121 | config IRQ_TWI | ||
| 122 | int "IRQ_TWI" | ||
| 123 | default 10 | ||
| 124 | config IRQ_SPI0 | ||
| 125 | int "IRQ_SPI" | ||
| 126 | default 10 | ||
| 127 | config IRQ_UART0_RX | ||
| 128 | int "IRQ_UART0_RX" | ||
| 129 | default 10 | ||
| 130 | config IRQ_UART0_TX | ||
| 131 | int "IRQ_UART0_TX" | ||
| 132 | default 10 | ||
| 133 | config IRQ_UART1_RX | ||
| 134 | int "IRQ_UART1_RX" | ||
| 135 | default 10 | ||
| 136 | config IRQ_UART1_TX | ||
| 137 | int "IRQ_UART1_TX" | ||
| 138 | default 10 | ||
| 139 | config IRQ_OPTSEC | ||
| 140 | int "IRQ_OPTSEC" | ||
| 141 | default 11 | ||
| 142 | config IRQ_CNT | ||
| 143 | int "IRQ_CNT" | ||
| 144 | default 11 | ||
| 145 | config IRQ_MAC_RX | ||
| 146 | int "IRQ_MAC_RX" | ||
| 147 | default 11 | ||
| 148 | config IRQ_PORTH_INTA | ||
| 149 | int "IRQ_PORTH_INTA" | ||
| 150 | default 11 | ||
| 151 | config IRQ_MAC_TX | ||
| 152 | int "IRQ_MAC_TX/NFC" | ||
| 153 | default 11 | ||
| 154 | config IRQ_PORTH_INTB | ||
| 155 | int "IRQ_PORTH_INTB" | ||
| 156 | default 11 | ||
| 157 | config IRQ_TIMER0 | ||
| 158 | int "IRQ_TIMER0" | ||
| 159 | default 8 | ||
| 160 | config IRQ_TIMER1 | ||
| 161 | int "IRQ_TIMER1" | ||
| 162 | default 12 | ||
| 163 | config IRQ_TIMER2 | ||
| 164 | int "IRQ_TIMER2" | ||
| 165 | default 12 | ||
| 166 | config IRQ_TIMER3 | ||
| 167 | int "IRQ_TIMER3" | ||
| 168 | default 12 | ||
| 169 | config IRQ_TIMER4 | ||
| 170 | int "IRQ_TIMER4" | ||
| 171 | default 12 | ||
| 172 | config IRQ_TIMER5 | ||
| 173 | int "IRQ_TIMER5" | ||
| 174 | default 12 | ||
| 175 | config IRQ_TIMER6 | ||
| 176 | int "IRQ_TIMER6" | ||
| 177 | default 12 | ||
| 178 | config IRQ_TIMER7 | ||
| 179 | int "IRQ_TIMER7" | ||
| 180 | default 12 | ||
| 181 | config IRQ_PORTG_INTA | ||
| 182 | int "IRQ_PORTG_INTA" | ||
| 183 | default 12 | ||
| 184 | config IRQ_PORTG_INTB | ||
| 185 | int "IRQ_PORTG_INTB" | ||
| 186 | default 12 | ||
| 187 | config IRQ_MEM_DMA0 | ||
| 188 | int "IRQ_MEM_DMA0" | ||
| 189 | default 13 | ||
| 190 | config IRQ_MEM_DMA1 | ||
| 191 | int "IRQ_MEM_DMA1" | ||
| 192 | default 13 | ||
| 193 | config IRQ_WATCH | ||
| 194 | int "IRQ_WATCH" | ||
| 195 | default 13 | ||
| 196 | config IRQ_PORTF_INTA | ||
| 197 | int "IRQ_PORTF_INTA" | ||
| 198 | default 13 | ||
| 199 | config IRQ_PORTF_INTB | ||
| 200 | int "IRQ_PORTF_INTB" | ||
| 201 | default 13 | ||
| 202 | config IRQ_SPI0_ERROR | ||
| 203 | int "IRQ_SPI0_ERROR" | ||
| 204 | default 7 | ||
| 205 | config IRQ_SPI1_ERROR | ||
| 206 | int "IRQ_SPI1_ERROR" | ||
| 207 | default 7 | ||
| 208 | config IRQ_RSI_INT0 | ||
| 209 | int "IRQ_RSI_INT0" | ||
| 210 | default 7 | ||
| 211 | config IRQ_RSI_INT1 | ||
| 212 | int "IRQ_RSI_INT1" | ||
| 213 | default 7 | ||
| 214 | config IRQ_PWM_TRIP | ||
| 215 | int "IRQ_PWM_TRIP" | ||
| 216 | default 10 | ||
| 217 | config IRQ_PWM_SYNC | ||
| 218 | int "IRQ_PWM_SYNC" | ||
| 219 | default 10 | ||
| 220 | config IRQ_PTP_STAT | ||
| 221 | int "IRQ_PTP_STAT" | ||
| 222 | default 10 | ||
| 223 | |||
| 224 | help | ||
| 225 | Enter the priority numbers between 7-13 ONLY. Others are Reserved. | ||
| 226 | This applies to all the above. It is not recommended to assign the | ||
| 227 | highest priority number 7 to UART or any other device. | ||
| 228 | |||
| 229 | endmenu | ||
| 230 | |||
| 231 | endmenu | ||
| 232 | |||
| 233 | endif | ||
diff --git a/arch/blackfin/mach-bf518/Makefile b/arch/blackfin/mach-bf518/Makefile new file mode 100644 index 000000000000..168a193f9f9a --- /dev/null +++ b/arch/blackfin/mach-bf518/Makefile | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | # | ||
| 2 | # arch/blackfin/mach-bf518/Makefile | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y := ints-priority.o dma.o | ||
diff --git a/arch/blackfin/mach-bf518/boards/Kconfig b/arch/blackfin/mach-bf518/boards/Kconfig new file mode 100644 index 000000000000..96163514ed22 --- /dev/null +++ b/arch/blackfin/mach-bf518/boards/Kconfig | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | choice | ||
| 2 | prompt "System type" | ||
| 3 | default BFIN518F_EZBRD | ||
| 4 | help | ||
| 5 | Select your board! | ||
| 6 | |||
| 7 | config BFIN518F_EZBRD | ||
| 8 | bool "BF518F-EZBRD" | ||
| 9 | help | ||
| 10 | BF518-EZBRD board support. | ||
| 11 | |||
| 12 | endchoice | ||
diff --git a/arch/blackfin/mach-bf518/boards/Makefile b/arch/blackfin/mach-bf518/boards/Makefile new file mode 100644 index 000000000000..172e859c3a7f --- /dev/null +++ b/arch/blackfin/mach-bf518/boards/Makefile | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | # | ||
| 2 | # arch/blackfin/mach-bf518/boards/Makefile | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-$(CONFIG_BFIN518F_EZBRD) += ezbrd.o | ||
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c new file mode 100644 index 000000000000..15f1351c8645 --- /dev/null +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c | |||
| @@ -0,0 +1,669 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf518/boards/ezbrd.c | ||
| 3 | * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c | ||
| 4 | * Author: Bryan Wu <cooloney@kernel.org> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2005 National ICT Australia (NICTA) | ||
| 11 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/device.h> | ||
| 32 | #include <linux/platform_device.h> | ||
| 33 | #include <linux/mtd/mtd.h> | ||
| 34 | #include <linux/mtd/partitions.h> | ||
| 35 | #include <linux/mtd/physmap.h> | ||
| 36 | #include <linux/spi/spi.h> | ||
| 37 | #include <linux/spi/flash.h> | ||
| 38 | |||
| 39 | #include <linux/i2c.h> | ||
| 40 | #include <linux/irq.h> | ||
| 41 | #include <linux/interrupt.h> | ||
| 42 | #include <asm/dma.h> | ||
| 43 | #include <asm/bfin5xx_spi.h> | ||
| 44 | #include <asm/reboot.h> | ||
| 45 | #include <asm/portmux.h> | ||
| 46 | #include <asm/dpmc.h> | ||
| 47 | #include <asm/bfin_sdh.h> | ||
| 48 | #include <linux/spi/ad7877.h> | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Name the Board for the /proc/cpuinfo | ||
| 52 | */ | ||
| 53 | const char bfin_board_name[] = "ADI BF518F-EZBRD"; | ||
| 54 | |||
| 55 | /* | ||
| 56 | * Driver needs to know address, irq and flag pin. | ||
| 57 | */ | ||
| 58 | |||
| 59 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
| 60 | static struct mtd_partition ezbrd_partitions[] = { | ||
| 61 | { | ||
| 62 | .name = "bootloader(nor)", | ||
| 63 | .size = 0x40000, | ||
| 64 | .offset = 0, | ||
| 65 | }, { | ||
| 66 | .name = "linux kernel(nor)", | ||
| 67 | .size = 0x1C0000, | ||
| 68 | .offset = MTDPART_OFS_APPEND, | ||
| 69 | }, { | ||
| 70 | .name = "file system(nor)", | ||
| 71 | .size = MTDPART_SIZ_FULL, | ||
| 72 | .offset = MTDPART_OFS_APPEND, | ||
| 73 | } | ||
| 74 | }; | ||
| 75 | |||
| 76 | static struct physmap_flash_data ezbrd_flash_data = { | ||
| 77 | .width = 2, | ||
| 78 | .parts = ezbrd_partitions, | ||
| 79 | .nr_parts = ARRAY_SIZE(ezbrd_partitions), | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct resource ezbrd_flash_resource = { | ||
| 83 | .start = 0x20000000, | ||
| 84 | .end = 0x203fffff, | ||
| 85 | .flags = IORESOURCE_MEM, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct platform_device ezbrd_flash_device = { | ||
| 89 | .name = "physmap-flash", | ||
| 90 | .id = 0, | ||
| 91 | .dev = { | ||
| 92 | .platform_data = &ezbrd_flash_data, | ||
| 93 | }, | ||
| 94 | .num_resources = 1, | ||
| 95 | .resource = &ezbrd_flash_resource, | ||
| 96 | }; | ||
| 97 | #endif | ||
| 98 | |||
| 99 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
| 100 | static struct platform_device rtc_device = { | ||
| 101 | .name = "rtc-bfin", | ||
| 102 | .id = -1, | ||
| 103 | }; | ||
| 104 | #endif | ||
| 105 | |||
| 106 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
| 107 | static struct platform_device bfin_mac_device = { | ||
| 108 | .name = "bfin_mac", | ||
| 109 | }; | ||
| 110 | #endif | ||
| 111 | |||
| 112 | #if defined(CONFIG_MTD_M25P80) \ | ||
| 113 | || defined(CONFIG_MTD_M25P80_MODULE) | ||
| 114 | static struct mtd_partition bfin_spi_flash_partitions[] = { | ||
| 115 | { | ||
| 116 | .name = "bootloader(spi)", | ||
| 117 | .size = 0x00040000, | ||
| 118 | .offset = 0, | ||
| 119 | .mask_flags = MTD_CAP_ROM | ||
| 120 | }, { | ||
| 121 | .name = "linux kernel(spi)", | ||
| 122 | .size = MTDPART_SIZ_FULL, | ||
| 123 | .offset = MTDPART_OFS_APPEND, | ||
| 124 | } | ||
| 125 | }; | ||
| 126 | |||
| 127 | static struct flash_platform_data bfin_spi_flash_data = { | ||
| 128 | .name = "m25p80", | ||
| 129 | .parts = bfin_spi_flash_partitions, | ||
| 130 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | ||
| 131 | .type = "m25p16", | ||
| 132 | }; | ||
| 133 | |||
| 134 | /* SPI flash chip (m25p64) */ | ||
| 135 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | ||
| 136 | .enable_dma = 0, /* use dma transfer with this chip*/ | ||
| 137 | .bits_per_word = 8, | ||
| 138 | }; | ||
| 139 | #endif | ||
| 140 | |||
| 141 | #if defined(CONFIG_SPI_ADC_BF533) \ | ||
| 142 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | ||
| 143 | /* SPI ADC chip */ | ||
| 144 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | ||
| 145 | .enable_dma = 1, /* use dma transfer with this chip*/ | ||
| 146 | .bits_per_word = 16, | ||
| 147 | }; | ||
| 148 | #endif | ||
| 149 | |||
| 150 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | ||
| 151 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | ||
| 152 | .enable_dma = 1, | ||
| 153 | .bits_per_word = 8, | ||
| 154 | }; | ||
| 155 | #endif | ||
| 156 | |||
| 157 | #if defined(CONFIG_PBX) | ||
| 158 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | ||
| 159 | .ctl_reg = 0x4, /* send zero */ | ||
| 160 | .enable_dma = 0, | ||
| 161 | .bits_per_word = 8, | ||
| 162 | .cs_change_per_word = 1, | ||
| 163 | }; | ||
| 164 | #endif | ||
| 165 | |||
| 166 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | ||
| 167 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { | ||
| 168 | .enable_dma = 0, | ||
| 169 | .bits_per_word = 16, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { | ||
| 173 | .model = 7877, | ||
| 174 | .vref_delay_usecs = 50, /* internal, no capacitor */ | ||
| 175 | .x_plate_ohms = 419, | ||
| 176 | .y_plate_ohms = 486, | ||
| 177 | .pressure_max = 1000, | ||
| 178 | .pressure_min = 0, | ||
| 179 | .stopacq_polarity = 1, | ||
| 180 | .first_conversion_delay = 3, | ||
| 181 | .acquisition_time = 1, | ||
| 182 | .averaging = 1, | ||
| 183 | .pen_down_acc_interval = 1, | ||
| 184 | }; | ||
| 185 | #endif | ||
| 186 | |||
| 187 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ | ||
| 188 | && defined(CONFIG_SND_SOC_WM8731_SPI) | ||
| 189 | static struct bfin5xx_spi_chip spi_wm8731_chip_info = { | ||
| 190 | .enable_dma = 0, | ||
| 191 | .bits_per_word = 16, | ||
| 192 | }; | ||
| 193 | #endif | ||
| 194 | |||
| 195 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | ||
| 196 | static struct bfin5xx_spi_chip spidev_chip_info = { | ||
| 197 | .enable_dma = 0, | ||
| 198 | .bits_per_word = 8, | ||
| 199 | }; | ||
| 200 | #endif | ||
| 201 | |||
| 202 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | ||
| 203 | #if defined(CONFIG_MTD_M25P80) \ | ||
| 204 | || defined(CONFIG_MTD_M25P80_MODULE) | ||
| 205 | { | ||
| 206 | /* the modalias must be the same as spi device driver name */ | ||
| 207 | .modalias = "m25p80", /* Name of spi_driver for this device */ | ||
| 208 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 209 | .bus_num = 0, /* Framework bus number */ | ||
| 210 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ | ||
| 211 | .platform_data = &bfin_spi_flash_data, | ||
| 212 | .controller_data = &spi_flash_chip_info, | ||
| 213 | .mode = SPI_MODE_3, | ||
| 214 | }, | ||
| 215 | #endif | ||
| 216 | |||
| 217 | #if defined(CONFIG_SPI_ADC_BF533) \ | ||
| 218 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | ||
| 219 | { | ||
| 220 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | ||
| 221 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | ||
| 222 | .bus_num = 0, /* Framework bus number */ | ||
| 223 | .chip_select = 1, /* Framework chip select. */ | ||
| 224 | .platform_data = NULL, /* No spi_driver specific config */ | ||
| 225 | .controller_data = &spi_adc_chip_info, | ||
| 226 | }, | ||
| 227 | #endif | ||
| 228 | |||
| 229 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | ||
| 230 | { | ||
| 231 | .modalias = "spi_mmc_dummy", | ||
| 232 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 233 | .bus_num = 0, | ||
| 234 | .chip_select = 0, | ||
| 235 | .platform_data = NULL, | ||
| 236 | .controller_data = &spi_mmc_chip_info, | ||
| 237 | .mode = SPI_MODE_3, | ||
| 238 | }, | ||
| 239 | { | ||
| 240 | .modalias = "spi_mmc", | ||
| 241 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 242 | .bus_num = 0, | ||
| 243 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | ||
| 244 | .platform_data = NULL, | ||
| 245 | .controller_data = &spi_mmc_chip_info, | ||
| 246 | .mode = SPI_MODE_3, | ||
| 247 | }, | ||
| 248 | #endif | ||
| 249 | #if defined(CONFIG_PBX) | ||
| 250 | { | ||
| 251 | .modalias = "fxs-spi", | ||
| 252 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
| 253 | .bus_num = 0, | ||
| 254 | .chip_select = 8 - CONFIG_J11_JUMPER, | ||
| 255 | .controller_data = &spi_si3xxx_chip_info, | ||
| 256 | .mode = SPI_MODE_3, | ||
| 257 | }, | ||
| 258 | { | ||
| 259 | .modalias = "fxo-spi", | ||
| 260 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
| 261 | .bus_num = 0, | ||
| 262 | .chip_select = 8 - CONFIG_J19_JUMPER, | ||
| 263 | .controller_data = &spi_si3xxx_chip_info, | ||
| 264 | .mode = SPI_MODE_3, | ||
| 265 | }, | ||
| 266 | #endif | ||
| 267 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | ||
| 268 | { | ||
| 269 | .modalias = "ad7877", | ||
| 270 | .platform_data = &bfin_ad7877_ts_info, | ||
| 271 | .irq = IRQ_PF8, | ||
| 272 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
| 273 | .bus_num = 0, | ||
| 274 | .chip_select = 2, | ||
| 275 | .controller_data = &spi_ad7877_chip_info, | ||
| 276 | }, | ||
| 277 | #endif | ||
| 278 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ | ||
| 279 | && defined(CONFIG_SND_SOC_WM8731_SPI) | ||
| 280 | { | ||
| 281 | .modalias = "wm8731", | ||
| 282 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | ||
| 283 | .bus_num = 0, | ||
| 284 | .chip_select = 5, | ||
| 285 | .controller_data = &spi_wm8731_chip_info, | ||
| 286 | .mode = SPI_MODE_0, | ||
| 287 | }, | ||
| 288 | #endif | ||
| 289 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | ||
| 290 | { | ||
| 291 | .modalias = "spidev", | ||
| 292 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | ||
| 293 | .bus_num = 0, | ||
| 294 | .chip_select = 1, | ||
| 295 | .controller_data = &spidev_chip_info, | ||
| 296 | }, | ||
| 297 | #endif | ||
| 298 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) | ||
| 299 | { | ||
| 300 | .modalias = "bfin-lq035q1-spi", | ||
| 301 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 302 | .bus_num = 0, | ||
| 303 | .chip_select = 1, | ||
| 304 | .controller_data = &lq035q1_spi_chip_info, | ||
| 305 | .mode = SPI_CPHA | SPI_CPOL, | ||
| 306 | }, | ||
| 307 | #endif | ||
| 308 | }; | ||
| 309 | |||
| 310 | /* SPI controller data */ | ||
| 311 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 312 | /* SPI (0) */ | ||
| 313 | static struct bfin5xx_spi_master bfin_spi0_info = { | ||
| 314 | .num_chipselect = 5, | ||
| 315 | .enable_dma = 1, /* master has the ability to do dma transfer */ | ||
| 316 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | ||
| 317 | }; | ||
| 318 | |||
| 319 | static struct resource bfin_spi0_resource[] = { | ||
| 320 | [0] = { | ||
| 321 | .start = SPI0_REGBASE, | ||
| 322 | .end = SPI0_REGBASE + 0xFF, | ||
| 323 | .flags = IORESOURCE_MEM, | ||
| 324 | }, | ||
| 325 | [1] = { | ||
| 326 | .start = CH_SPI0, | ||
| 327 | .end = CH_SPI0, | ||
| 328 | .flags = IORESOURCE_IRQ, | ||
| 329 | }, | ||
| 330 | }; | ||
| 331 | |||
| 332 | static struct platform_device bfin_spi0_device = { | ||
| 333 | .name = "bfin-spi", | ||
| 334 | .id = 0, /* Bus number */ | ||
| 335 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | ||
| 336 | .resource = bfin_spi0_resource, | ||
| 337 | .dev = { | ||
| 338 | .platform_data = &bfin_spi0_info, /* Passed to driver */ | ||
| 339 | }, | ||
| 340 | }; | ||
| 341 | |||
| 342 | /* SPI (1) */ | ||
| 343 | static struct bfin5xx_spi_master bfin_spi1_info = { | ||
| 344 | .num_chipselect = 5, | ||
| 345 | .enable_dma = 1, /* master has the ability to do dma transfer */ | ||
| 346 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | ||
| 347 | }; | ||
| 348 | |||
| 349 | static struct resource bfin_spi1_resource[] = { | ||
| 350 | [0] = { | ||
| 351 | .start = SPI1_REGBASE, | ||
| 352 | .end = SPI1_REGBASE + 0xFF, | ||
| 353 | .flags = IORESOURCE_MEM, | ||
| 354 | }, | ||
| 355 | [1] = { | ||
| 356 | .start = CH_SPI1, | ||
| 357 | .end = CH_SPI1, | ||
| 358 | .flags = IORESOURCE_IRQ, | ||
| 359 | }, | ||
| 360 | }; | ||
| 361 | |||
| 362 | static struct platform_device bfin_spi1_device = { | ||
| 363 | .name = "bfin-spi", | ||
| 364 | .id = 1, /* Bus number */ | ||
| 365 | .num_resources = ARRAY_SIZE(bfin_spi1_resource), | ||
| 366 | .resource = bfin_spi1_resource, | ||
| 367 | .dev = { | ||
| 368 | .platform_data = &bfin_spi1_info, /* Passed to driver */ | ||
| 369 | }, | ||
| 370 | }; | ||
| 371 | #endif /* spi master and devices */ | ||
| 372 | |||
| 373 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | ||
| 374 | static struct resource bfin_uart_resources[] = { | ||
| 375 | #ifdef CONFIG_SERIAL_BFIN_UART0 | ||
| 376 | { | ||
| 377 | .start = 0xFFC00400, | ||
| 378 | .end = 0xFFC004FF, | ||
| 379 | .flags = IORESOURCE_MEM, | ||
| 380 | }, | ||
| 381 | #endif | ||
| 382 | #ifdef CONFIG_SERIAL_BFIN_UART1 | ||
| 383 | { | ||
| 384 | .start = 0xFFC02000, | ||
| 385 | .end = 0xFFC020FF, | ||
| 386 | .flags = IORESOURCE_MEM, | ||
| 387 | }, | ||
| 388 | #endif | ||
| 389 | }; | ||
| 390 | |||
| 391 | static struct platform_device bfin_uart_device = { | ||
| 392 | .name = "bfin-uart", | ||
| 393 | .id = 1, | ||
| 394 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | ||
| 395 | .resource = bfin_uart_resources, | ||
| 396 | }; | ||
| 397 | #endif | ||
| 398 | |||
| 399 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 400 | #ifdef CONFIG_BFIN_SIR0 | ||
| 401 | static struct resource bfin_sir0_resources[] = { | ||
| 402 | { | ||
| 403 | .start = 0xFFC00400, | ||
| 404 | .end = 0xFFC004FF, | ||
| 405 | .flags = IORESOURCE_MEM, | ||
| 406 | }, | ||
| 407 | { | ||
| 408 | .start = IRQ_UART0_RX, | ||
| 409 | .end = IRQ_UART0_RX+1, | ||
| 410 | .flags = IORESOURCE_IRQ, | ||
| 411 | }, | ||
| 412 | { | ||
| 413 | .start = CH_UART0_RX, | ||
| 414 | .end = CH_UART0_RX+1, | ||
| 415 | .flags = IORESOURCE_DMA, | ||
| 416 | }, | ||
| 417 | }; | ||
| 418 | |||
| 419 | static struct platform_device bfin_sir0_device = { | ||
| 420 | .name = "bfin_sir", | ||
| 421 | .id = 0, | ||
| 422 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 423 | .resource = bfin_sir0_resources, | ||
| 424 | }; | ||
| 425 | #endif | ||
| 426 | #ifdef CONFIG_BFIN_SIR1 | ||
| 427 | static struct resource bfin_sir1_resources[] = { | ||
| 428 | { | ||
| 429 | .start = 0xFFC02000, | ||
| 430 | .end = 0xFFC020FF, | ||
| 431 | .flags = IORESOURCE_MEM, | ||
| 432 | }, | ||
| 433 | { | ||
| 434 | .start = IRQ_UART1_RX, | ||
| 435 | .end = IRQ_UART1_RX+1, | ||
| 436 | .flags = IORESOURCE_IRQ, | ||
| 437 | }, | ||
| 438 | { | ||
| 439 | .start = CH_UART1_RX, | ||
| 440 | .end = CH_UART1_RX+1, | ||
| 441 | .flags = IORESOURCE_DMA, | ||
| 442 | }, | ||
| 443 | }; | ||
| 444 | |||
| 445 | static struct platform_device bfin_sir1_device = { | ||
| 446 | .name = "bfin_sir", | ||
| 447 | .id = 1, | ||
| 448 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | ||
| 449 | .resource = bfin_sir1_resources, | ||
| 450 | }; | ||
| 451 | #endif | ||
| 452 | #endif | ||
| 453 | |||
| 454 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | ||
| 455 | static struct resource bfin_twi0_resource[] = { | ||
| 456 | [0] = { | ||
| 457 | .start = TWI0_REGBASE, | ||
| 458 | .end = TWI0_REGBASE, | ||
| 459 | .flags = IORESOURCE_MEM, | ||
| 460 | }, | ||
| 461 | [1] = { | ||
| 462 | .start = IRQ_TWI, | ||
| 463 | .end = IRQ_TWI, | ||
| 464 | .flags = IORESOURCE_IRQ, | ||
| 465 | }, | ||
| 466 | }; | ||
| 467 | |||
| 468 | static struct platform_device i2c_bfin_twi_device = { | ||
| 469 | .name = "i2c-bfin-twi", | ||
| 470 | .id = 0, | ||
| 471 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | ||
| 472 | .resource = bfin_twi0_resource, | ||
| 473 | }; | ||
| 474 | #endif | ||
| 475 | |||
| 476 | #ifdef CONFIG_I2C_BOARDINFO | ||
| 477 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | ||
| 478 | #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) | ||
| 479 | { | ||
| 480 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | ||
| 481 | }, | ||
| 482 | #endif | ||
| 483 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | ||
| 484 | { | ||
| 485 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | ||
| 486 | .irq = IRQ_PF8, | ||
| 487 | }, | ||
| 488 | #endif | ||
| 489 | }; | ||
| 490 | #endif | ||
| 491 | |||
| 492 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | ||
| 493 | static struct platform_device bfin_sport0_uart_device = { | ||
| 494 | .name = "bfin-sport-uart", | ||
| 495 | .id = 0, | ||
| 496 | }; | ||
| 497 | |||
| 498 | static struct platform_device bfin_sport1_uart_device = { | ||
| 499 | .name = "bfin-sport-uart", | ||
| 500 | .id = 1, | ||
| 501 | }; | ||
| 502 | #endif | ||
| 503 | |||
| 504 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 505 | #include <linux/input.h> | ||
| 506 | #include <linux/gpio_keys.h> | ||
| 507 | |||
| 508 | static struct gpio_keys_button bfin_gpio_keys_table[] = { | ||
| 509 | {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, | ||
| 510 | {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, | ||
| 511 | }; | ||
| 512 | |||
| 513 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { | ||
| 514 | .buttons = bfin_gpio_keys_table, | ||
| 515 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), | ||
| 516 | }; | ||
| 517 | |||
| 518 | static struct platform_device bfin_device_gpiokeys = { | ||
| 519 | .name = "gpio-keys", | ||
| 520 | .dev = { | ||
| 521 | .platform_data = &bfin_gpio_keys_data, | ||
| 522 | }, | ||
| 523 | }; | ||
| 524 | #endif | ||
| 525 | |||
| 526 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) | ||
| 527 | |||
| 528 | static struct bfin_sd_host bfin_sdh_data = { | ||
| 529 | .dma_chan = CH_RSI, | ||
| 530 | .irq_int0 = IRQ_RSI_INT0, | ||
| 531 | .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0}, | ||
| 532 | }; | ||
| 533 | |||
| 534 | static struct platform_device bf51x_sdh_device = { | ||
| 535 | .name = "bfin-sdh", | ||
| 536 | .id = 0, | ||
| 537 | .dev = { | ||
| 538 | .platform_data = &bfin_sdh_data, | ||
| 539 | }, | ||
| 540 | }; | ||
| 541 | #endif | ||
| 542 | |||
| 543 | static struct resource bfin_gpios_resources = { | ||
| 544 | .start = 0, | ||
| 545 | .end = MAX_BLACKFIN_GPIOS - 1, | ||
| 546 | .flags = IORESOURCE_IRQ, | ||
| 547 | }; | ||
| 548 | |||
| 549 | static struct platform_device bfin_gpios_device = { | ||
| 550 | .name = "simple-gpio", | ||
| 551 | .id = -1, | ||
| 552 | .num_resources = 1, | ||
| 553 | .resource = &bfin_gpios_resources, | ||
| 554 | }; | ||
| 555 | |||
| 556 | static const unsigned int cclk_vlev_datasheet[] = | ||
| 557 | { | ||
| 558 | VRPAIR(VLEV_100, 400000000), | ||
| 559 | VRPAIR(VLEV_105, 426000000), | ||
| 560 | VRPAIR(VLEV_110, 500000000), | ||
| 561 | VRPAIR(VLEV_115, 533000000), | ||
| 562 | VRPAIR(VLEV_120, 600000000), | ||
| 563 | }; | ||
| 564 | |||
| 565 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | ||
| 566 | .tuple_tab = cclk_vlev_datasheet, | ||
| 567 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | ||
| 568 | .vr_settling_time = 25 /* us */, | ||
| 569 | }; | ||
| 570 | |||
| 571 | static struct platform_device bfin_dpmc = { | ||
| 572 | .name = "bfin dpmc", | ||
| 573 | .dev = { | ||
| 574 | .platform_data = &bfin_dmpc_vreg_data, | ||
| 575 | }, | ||
| 576 | }; | ||
| 577 | |||
| 578 | static struct platform_device *stamp_devices[] __initdata = { | ||
| 579 | |||
| 580 | &bfin_dpmc, | ||
| 581 | |||
| 582 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
| 583 | &rtc_device, | ||
| 584 | #endif | ||
| 585 | |||
| 586 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
| 587 | &bfin_mac_device, | ||
| 588 | #endif | ||
| 589 | |||
| 590 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 591 | &bfin_spi0_device, | ||
| 592 | &bfin_spi1_device, | ||
| 593 | #endif | ||
| 594 | |||
| 595 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | ||
| 596 | &bfin_uart_device, | ||
| 597 | #endif | ||
| 598 | |||
| 599 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 600 | #ifdef CONFIG_BFIN_SIR0 | ||
| 601 | &bfin_sir0_device, | ||
| 602 | #endif | ||
| 603 | #ifdef CONFIG_BFIN_SIR1 | ||
| 604 | &bfin_sir1_device, | ||
| 605 | #endif | ||
| 606 | #endif | ||
| 607 | |||
| 608 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | ||
| 609 | &i2c_bfin_twi_device, | ||
| 610 | #endif | ||
| 611 | |||
| 612 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | ||
| 613 | &bfin_sport0_uart_device, | ||
| 614 | &bfin_sport1_uart_device, | ||
| 615 | #endif | ||
| 616 | |||
| 617 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 618 | &bfin_device_gpiokeys, | ||
| 619 | #endif | ||
| 620 | |||
| 621 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) | ||
| 622 | &bf51x_sdh_device, | ||
| 623 | #endif | ||
| 624 | |||
| 625 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
| 626 | &ezbrd_flash_device, | ||
| 627 | #endif | ||
| 628 | |||
| 629 | &bfin_gpios_device, | ||
| 630 | }; | ||
| 631 | |||
| 632 | static int __init ezbrd_init(void) | ||
| 633 | { | ||
| 634 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 635 | |||
| 636 | #ifdef CONFIG_I2C_BOARDINFO | ||
| 637 | i2c_register_board_info(0, bfin_i2c_board_info, | ||
| 638 | ARRAY_SIZE(bfin_i2c_board_info)); | ||
| 639 | #endif | ||
| 640 | |||
| 641 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); | ||
| 642 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | ||
| 643 | return 0; | ||
| 644 | } | ||
| 645 | |||
| 646 | arch_initcall(ezbrd_init); | ||
| 647 | |||
| 648 | void native_machine_restart(char *cmd) | ||
| 649 | { | ||
| 650 | /* workaround reboot hang when booting from SPI */ | ||
| 651 | if ((bfin_read_SYSCR() & 0x7) == 0x3) | ||
| 652 | bfin_gpio_reset_spi0_ssel1(); | ||
| 653 | } | ||
| 654 | |||
| 655 | void bfin_get_ether_addr(char *addr) | ||
| 656 | { | ||
| 657 | /* the MAC is stored in OTP memory page 0xDF */ | ||
| 658 | u32 ret; | ||
| 659 | u64 otp_mac; | ||
| 660 | u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A; | ||
| 661 | |||
| 662 | ret = otp_read(0xDF, 0x00, &otp_mac); | ||
| 663 | if (!(ret & 0x1)) { | ||
| 664 | char *otp_mac_p = (char *)&otp_mac; | ||
| 665 | for (ret = 0; ret < 6; ++ret) | ||
| 666 | addr[ret] = otp_mac_p[5 - ret]; | ||
| 667 | } | ||
| 668 | } | ||
| 669 | EXPORT_SYMBOL(bfin_get_ether_addr); | ||
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c new file mode 100644 index 000000000000..698e88ca5104 --- /dev/null +++ b/arch/blackfin/mach-bf518/dma.c | |||
| @@ -0,0 +1,118 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf518/dma.c | ||
| 3 | * Based on: | ||
| 4 | * Author: Bryan Wu <cooloney@kernel.org> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: This file contains the simple DMA Implementation for Blackfin | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | #include <linux/module.h> | ||
| 30 | |||
| 31 | #include <asm/blackfin.h> | ||
| 32 | #include <asm/dma.h> | ||
| 33 | |||
| 34 | struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { | ||
| 35 | (struct dma_register *) DMA0_NEXT_DESC_PTR, | ||
| 36 | (struct dma_register *) DMA1_NEXT_DESC_PTR, | ||
| 37 | (struct dma_register *) DMA2_NEXT_DESC_PTR, | ||
| 38 | (struct dma_register *) DMA3_NEXT_DESC_PTR, | ||
| 39 | (struct dma_register *) DMA4_NEXT_DESC_PTR, | ||
| 40 | (struct dma_register *) DMA5_NEXT_DESC_PTR, | ||
| 41 | (struct dma_register *) DMA6_NEXT_DESC_PTR, | ||
| 42 | (struct dma_register *) DMA7_NEXT_DESC_PTR, | ||
| 43 | (struct dma_register *) DMA8_NEXT_DESC_PTR, | ||
| 44 | (struct dma_register *) DMA9_NEXT_DESC_PTR, | ||
| 45 | (struct dma_register *) DMA10_NEXT_DESC_PTR, | ||
| 46 | (struct dma_register *) DMA11_NEXT_DESC_PTR, | ||
| 47 | (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, | ||
| 48 | (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, | ||
| 49 | (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, | ||
| 50 | (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, | ||
| 51 | }; | ||
| 52 | EXPORT_SYMBOL(dma_io_base_addr); | ||
| 53 | |||
| 54 | int channel2irq(unsigned int channel) | ||
| 55 | { | ||
| 56 | int ret_irq = -1; | ||
| 57 | |||
| 58 | switch (channel) { | ||
| 59 | case CH_PPI: | ||
| 60 | ret_irq = IRQ_PPI; | ||
| 61 | break; | ||
| 62 | |||
| 63 | case CH_EMAC_RX: | ||
| 64 | ret_irq = IRQ_MAC_RX; | ||
| 65 | break; | ||
| 66 | |||
| 67 | case CH_EMAC_TX: | ||
| 68 | ret_irq = IRQ_MAC_TX; | ||
| 69 | break; | ||
| 70 | |||
| 71 | case CH_UART1_RX: | ||
| 72 | ret_irq = IRQ_UART1_RX; | ||
| 73 | break; | ||
| 74 | |||
| 75 | case CH_UART1_TX: | ||
| 76 | ret_irq = IRQ_UART1_TX; | ||
| 77 | break; | ||
| 78 | |||
| 79 | case CH_SPORT0_RX: | ||
| 80 | ret_irq = IRQ_SPORT0_RX; | ||
| 81 | break; | ||
| 82 | |||
| 83 | case CH_SPORT0_TX: | ||
| 84 | ret_irq = IRQ_SPORT0_TX; | ||
| 85 | break; | ||
| 86 | |||
| 87 | case CH_SPORT1_RX: | ||
| 88 | ret_irq = IRQ_SPORT1_RX; | ||
| 89 | break; | ||
| 90 | |||
| 91 | case CH_SPORT1_TX: | ||
| 92 | ret_irq = IRQ_SPORT1_TX; | ||
| 93 | break; | ||
| 94 | |||
| 95 | case CH_SPI0: | ||
| 96 | ret_irq = IRQ_SPI0; | ||
| 97 | break; | ||
| 98 | |||
| 99 | case CH_UART0_RX: | ||
| 100 | ret_irq = IRQ_UART0_RX; | ||
| 101 | break; | ||
| 102 | |||
| 103 | case CH_UART0_TX: | ||
| 104 | ret_irq = IRQ_UART0_TX; | ||
| 105 | break; | ||
| 106 | |||
| 107 | case CH_MEM_STREAM0_SRC: | ||
| 108 | case CH_MEM_STREAM0_DEST: | ||
| 109 | ret_irq = IRQ_MEM_DMA0; | ||
| 110 | break; | ||
| 111 | |||
| 112 | case CH_MEM_STREAM1_SRC: | ||
| 113 | case CH_MEM_STREAM1_DEST: | ||
| 114 | ret_irq = IRQ_MEM_DMA1; | ||
| 115 | break; | ||
| 116 | } | ||
| 117 | return ret_irq; | ||
| 118 | } | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h new file mode 100644 index 000000000000..e5b4bef0edae --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/anomaly.h | ||
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 4 | * | ||
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* This file shoule be up to date with: | ||
| 10 | * - ???? | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _MACH_ANOMALY_H_ | ||
| 14 | #define _MACH_ANOMALY_H_ | ||
| 15 | |||
| 16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | ||
| 17 | #define ANOMALY_05000074 (1) | ||
| 18 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | ||
| 19 | #define ANOMALY_05000122 (1) | ||
| 20 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ | ||
| 21 | #define ANOMALY_05000245 (1) | ||
| 22 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | ||
| 23 | #define ANOMALY_05000265 (1) | ||
| 24 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | ||
| 25 | #define ANOMALY_05000310 (1) | ||
| 26 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | ||
| 27 | #define ANOMALY_05000366 (1) | ||
| 28 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ | ||
| 29 | #define ANOMALY_05000405 (1) | ||
| 30 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ | ||
| 31 | #define ANOMALY_05000408 (1) | ||
| 32 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | ||
| 33 | #define ANOMALY_05000416 (1) | ||
| 34 | /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ | ||
| 35 | #define ANOMALY_05000421 (1) | ||
| 36 | /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ | ||
| 37 | #define ANOMALY_05000422 (1) | ||
| 38 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | ||
| 39 | #define ANOMALY_05000426 (1) | ||
| 40 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | ||
| 41 | #define ANOMALY_05000430 (1) | ||
| 42 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ | ||
| 43 | #define ANOMALY_05000431 (1) | ||
| 44 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ | ||
| 45 | #define ANOMALY_05000435 (1) | ||
| 46 | /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ | ||
| 47 | #define ANOMALY_05000438 (1) | ||
| 48 | /* Preboot Cannot be Used to Program the PLL_DIV Register */ | ||
| 49 | #define ANOMALY_05000439 (1) | ||
| 50 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ | ||
| 51 | #define ANOMALY_05000440 (1) | ||
| 52 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | ||
| 53 | #define ANOMALY_05000443 (1) | ||
| 54 | /* Incorrect L1 Instruction Bank B Memory Map Location */ | ||
| 55 | #define ANOMALY_05000444 (1) | ||
| 56 | |||
| 57 | /* Anomalies that don't exist on this proc */ | ||
| 58 | #define ANOMALY_05000125 (0) | ||
| 59 | #define ANOMALY_05000158 (0) | ||
| 60 | #define ANOMALY_05000183 (0) | ||
| 61 | #define ANOMALY_05000198 (0) | ||
| 62 | #define ANOMALY_05000230 (0) | ||
| 63 | #define ANOMALY_05000244 (0) | ||
| 64 | #define ANOMALY_05000261 (0) | ||
| 65 | #define ANOMALY_05000263 (0) | ||
| 66 | #define ANOMALY_05000266 (0) | ||
| 67 | #define ANOMALY_05000273 (0) | ||
| 68 | #define ANOMALY_05000285 (0) | ||
| 69 | #define ANOMALY_05000307 (0) | ||
| 70 | #define ANOMALY_05000311 (0) | ||
| 71 | #define ANOMALY_05000312 (0) | ||
| 72 | #define ANOMALY_05000323 (0) | ||
| 73 | #define ANOMALY_05000353 (0) | ||
| 74 | #define ANOMALY_05000363 (0) | ||
| 75 | #define ANOMALY_05000386 (0) | ||
| 76 | #define ANOMALY_05000412 (0) | ||
| 77 | #define ANOMALY_05000432 (0) | ||
| 78 | |||
| 79 | #endif | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h new file mode 100644 index 000000000000..78da1a07ee73 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/bf518.h | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/bf518.h | ||
| 3 | * Based on: include/asm-blackfin/mach-bf527/bf527.h | ||
| 4 | * Author: Michael Hennerich (michael.hennerich@analog.com) | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF518 | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2007 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #ifndef __MACH_BF518_H__ | ||
| 31 | #define __MACH_BF518_H__ | ||
| 32 | |||
| 33 | #define OFFSET_(x) ((x) & 0x0000FFFF) | ||
| 34 | |||
| 35 | /*some misc defines*/ | ||
| 36 | #define IMASK_IVG15 0x8000 | ||
| 37 | #define IMASK_IVG14 0x4000 | ||
| 38 | #define IMASK_IVG13 0x2000 | ||
| 39 | #define IMASK_IVG12 0x1000 | ||
| 40 | |||
| 41 | #define IMASK_IVG11 0x0800 | ||
| 42 | #define IMASK_IVG10 0x0400 | ||
| 43 | #define IMASK_IVG9 0x0200 | ||
| 44 | #define IMASK_IVG8 0x0100 | ||
| 45 | |||
| 46 | #define IMASK_IVG7 0x0080 | ||
| 47 | #define IMASK_IVGTMR 0x0040 | ||
| 48 | #define IMASK_IVGHW 0x0020 | ||
| 49 | |||
| 50 | /***************************/ | ||
| 51 | |||
| 52 | #define BFIN_DSUBBANKS 4 | ||
| 53 | #define BFIN_DWAYS 2 | ||
| 54 | #define BFIN_DLINES 64 | ||
| 55 | #define BFIN_ISUBBANKS 4 | ||
| 56 | #define BFIN_IWAYS 4 | ||
| 57 | #define BFIN_ILINES 32 | ||
| 58 | |||
| 59 | #define WAY0_L 0x1 | ||
| 60 | #define WAY1_L 0x2 | ||
| 61 | #define WAY01_L 0x3 | ||
| 62 | #define WAY2_L 0x4 | ||
| 63 | #define WAY02_L 0x5 | ||
| 64 | #define WAY12_L 0x6 | ||
| 65 | #define WAY012_L 0x7 | ||
| 66 | |||
| 67 | #define WAY3_L 0x8 | ||
| 68 | #define WAY03_L 0x9 | ||
| 69 | #define WAY13_L 0xA | ||
| 70 | #define WAY013_L 0xB | ||
| 71 | |||
| 72 | #define WAY32_L 0xC | ||
| 73 | #define WAY320_L 0xD | ||
| 74 | #define WAY321_L 0xE | ||
| 75 | #define WAYALL_L 0xF | ||
| 76 | |||
| 77 | #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ | ||
| 78 | |||
| 79 | /********************************* EBIU Settings ************************************/ | ||
| 80 | #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) | ||
| 81 | #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) | ||
| 82 | |||
| 83 | #ifdef CONFIG_C_AMBEN_ALL | ||
| 84 | #define V_AMBEN AMBEN_ALL | ||
| 85 | #endif | ||
| 86 | #ifdef CONFIG_C_AMBEN | ||
| 87 | #define V_AMBEN 0x0 | ||
| 88 | #endif | ||
| 89 | #ifdef CONFIG_C_AMBEN_B0 | ||
| 90 | #define V_AMBEN AMBEN_B0 | ||
| 91 | #endif | ||
| 92 | #ifdef CONFIG_C_AMBEN_B0_B1 | ||
| 93 | #define V_AMBEN AMBEN_B0_B1 | ||
| 94 | #endif | ||
| 95 | #ifdef CONFIG_C_AMBEN_B0_B1_B2 | ||
| 96 | #define V_AMBEN AMBEN_B0_B1_B2 | ||
| 97 | #endif | ||
| 98 | #ifdef CONFIG_C_AMCKEN | ||
| 99 | #define V_AMCKEN AMCKEN | ||
| 100 | #else | ||
| 101 | #define V_AMCKEN 0x0 | ||
| 102 | #endif | ||
| 103 | #ifdef CONFIG_C_CDPRIO | ||
| 104 | #define V_CDPRIO 0x100 | ||
| 105 | #else | ||
| 106 | #define V_CDPRIO 0x0 | ||
| 107 | #endif | ||
| 108 | |||
| 109 | #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) | ||
| 110 | |||
| 111 | #ifdef CONFIG_BF518 | ||
| 112 | #define CPU "BF518" | ||
| 113 | #define CPUID 0x27e8 | ||
| 114 | #endif | ||
| 115 | #ifdef CONFIG_BF516 | ||
| 116 | #define CPU "BF516" | ||
| 117 | #define CPUID 0x27e8 | ||
| 118 | #endif | ||
| 119 | #ifdef CONFIG_BF514 | ||
| 120 | #define CPU "BF514" | ||
| 121 | #define CPUID 0x27e8 | ||
| 122 | #endif | ||
| 123 | #ifdef CONFIG_BF512 | ||
| 124 | #define CPU "BF512" | ||
| 125 | #define CPUID 0x27e8 | ||
| 126 | #endif | ||
| 127 | |||
| 128 | #ifndef CPU | ||
| 129 | #error "Unknown CPU type - This kernel doesn't seem to be configured properly" | ||
| 130 | #endif | ||
| 131 | |||
| 132 | #endif /* __MACH_BF518_H__ */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h new file mode 100644 index 000000000000..b50a63b975a2 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h | |||
| @@ -0,0 +1,169 @@ | |||
| 1 | /* | ||
| 2 | * file: include/asm-blackfin/mach-bf518/bfin_serial_5xx.h | ||
| 3 | * based on: | ||
| 4 | * author: | ||
| 5 | * | ||
| 6 | * created: | ||
| 7 | * description: | ||
| 8 | * blackfin serial driver head file | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * this program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the gnu general public license as published by | ||
| 18 | * the free software foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * this program is distributed in the hope that it will be useful, | ||
| 22 | * but without any warranty; without even the implied warranty of | ||
| 23 | * merchantability or fitness for a particular purpose. see the | ||
| 24 | * gnu general public license for more details. | ||
| 25 | * | ||
| 26 | * you should have received a copy of the gnu general public license | ||
| 27 | * along with this program; see the file copying. | ||
| 28 | * if not, write to the free software foundation, | ||
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #include <linux/serial.h> | ||
| 33 | #include <asm/dma.h> | ||
| 34 | #include <asm/portmux.h> | ||
| 35 | |||
| 36 | #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) | ||
| 37 | #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) | ||
| 38 | #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) | ||
| 39 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) | ||
| 40 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) | ||
| 41 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) | ||
| 42 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) | ||
| 43 | |||
| 44 | #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) | ||
| 45 | #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) | ||
| 46 | #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) | ||
| 47 | #define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) | ||
| 48 | #define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) | ||
| 49 | #define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) | ||
| 50 | #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) | ||
| 51 | #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) | ||
| 52 | |||
| 53 | #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) | ||
| 54 | #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) | ||
| 55 | |||
| 56 | #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) | ||
| 57 | #define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) | ||
| 58 | #define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) | ||
| 59 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) | ||
| 60 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) | ||
| 61 | |||
| 62 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) | ||
| 63 | # define CONFIG_SERIAL_BFIN_CTSRTS | ||
| 64 | |||
| 65 | # ifndef CONFIG_UART0_CTS_PIN | ||
| 66 | # define CONFIG_UART0_CTS_PIN -1 | ||
| 67 | # endif | ||
| 68 | |||
| 69 | # ifndef CONFIG_UART0_RTS_PIN | ||
| 70 | # define CONFIG_UART0_RTS_PIN -1 | ||
| 71 | # endif | ||
| 72 | |||
| 73 | # ifndef CONFIG_UART1_CTS_PIN | ||
| 74 | # define CONFIG_UART1_CTS_PIN -1 | ||
| 75 | # endif | ||
| 76 | |||
| 77 | # ifndef CONFIG_UART1_RTS_PIN | ||
| 78 | # define CONFIG_UART1_RTS_PIN -1 | ||
| 79 | # endif | ||
| 80 | #endif | ||
| 81 | |||
| 82 | #define BFIN_UART_TX_FIFO_SIZE 2 | ||
| 83 | |||
| 84 | /* | ||
| 85 | * The pin configuration is different from schematic | ||
| 86 | */ | ||
| 87 | struct bfin_serial_port { | ||
| 88 | struct uart_port port; | ||
| 89 | unsigned int old_status; | ||
| 90 | unsigned int lsr; | ||
| 91 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 92 | int tx_done; | ||
| 93 | int tx_count; | ||
| 94 | struct circ_buf rx_dma_buf; | ||
| 95 | struct timer_list rx_dma_timer; | ||
| 96 | int rx_dma_nrows; | ||
| 97 | unsigned int tx_dma_channel; | ||
| 98 | unsigned int rx_dma_channel; | ||
| 99 | struct work_struct tx_dma_workqueue; | ||
| 100 | #endif | ||
| 101 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 102 | struct timer_list cts_timer; | ||
| 103 | int cts_pin; | ||
| 104 | int rts_pin; | ||
| 105 | #endif | ||
| 106 | }; | ||
| 107 | |||
| 108 | /* The hardware clears the LSR bits upon read, so we need to cache | ||
| 109 | * some of the more fun bits in software so they don't get lost | ||
| 110 | * when checking the LSR in other code paths (TX). | ||
| 111 | */ | ||
| 112 | static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) | ||
| 113 | { | ||
| 114 | unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); | ||
| 115 | uart->lsr |= (lsr & (BI|FE|PE|OE)); | ||
| 116 | return lsr | uart->lsr; | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) | ||
| 120 | { | ||
| 121 | uart->lsr = 0; | ||
| 122 | bfin_write16(uart->port.membase + OFFSET_LSR, -1); | ||
| 123 | } | ||
| 124 | |||
| 125 | struct bfin_serial_res { | ||
| 126 | unsigned long uart_base_addr; | ||
| 127 | int uart_irq; | ||
| 128 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 129 | unsigned int uart_tx_dma_channel; | ||
| 130 | unsigned int uart_rx_dma_channel; | ||
| 131 | #endif | ||
| 132 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 133 | int uart_cts_pin; | ||
| 134 | int uart_rts_pin; | ||
| 135 | #endif | ||
| 136 | }; | ||
| 137 | |||
| 138 | struct bfin_serial_res bfin_serial_resource[] = { | ||
| 139 | #ifdef CONFIG_SERIAL_BFIN_UART0 | ||
| 140 | { | ||
| 141 | 0xFFC00400, | ||
| 142 | IRQ_UART0_RX, | ||
| 143 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 144 | CH_UART0_TX, | ||
| 145 | CH_UART0_RX, | ||
| 146 | #endif | ||
| 147 | #ifdef CONFIG_BFIN_UART0_CTSRTS | ||
| 148 | CONFIG_UART0_CTS_PIN, | ||
| 149 | CONFIG_UART0_RTS_PIN, | ||
| 150 | #endif | ||
| 151 | }, | ||
| 152 | #endif | ||
| 153 | #ifdef CONFIG_SERIAL_BFIN_UART1 | ||
| 154 | { | ||
| 155 | 0xFFC02000, | ||
| 156 | IRQ_UART1_RX, | ||
| 157 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 158 | CH_UART1_TX, | ||
| 159 | CH_UART1_RX, | ||
| 160 | #endif | ||
| 161 | #ifdef CONFIG_BFIN_UART1_CTSRTS | ||
| 162 | CONFIG_UART1_CTS_PIN, | ||
| 163 | CONFIG_UART1_RTS_PIN, | ||
| 164 | #endif | ||
| 165 | }, | ||
| 166 | #endif | ||
| 167 | }; | ||
| 168 | |||
| 169 | #define DRIVER_NAME "bfin-uart" | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h new file mode 100644 index 000000000000..d1a2b9ca6227 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h | |||
| @@ -0,0 +1,105 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/blackfin.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _MACH_BLACKFIN_H_ | ||
| 33 | #define _MACH_BLACKFIN_H_ | ||
| 34 | |||
| 35 | #define BF518_FAMILY | ||
| 36 | |||
| 37 | #include "bf518.h" | ||
| 38 | #include "mem_map.h" | ||
| 39 | #include "defBF512.h" | ||
| 40 | #include "anomaly.h" | ||
| 41 | |||
| 42 | #if defined(CONFIG_BF518) | ||
| 43 | #include "defBF518.h" | ||
| 44 | #endif | ||
| 45 | |||
| 46 | #if defined(CONFIG_BF516) | ||
| 47 | #include "defBF516.h" | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #if defined(CONFIG_BF514) | ||
| 51 | #include "defBF514.h" | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #if defined(CONFIG_BF512) | ||
| 55 | #include "defBF512.h" | ||
| 56 | #endif | ||
| 57 | |||
| 58 | #if !defined(__ASSEMBLY__) | ||
| 59 | #include "cdefBF512.h" | ||
| 60 | |||
| 61 | #if defined(CONFIG_BF518) | ||
| 62 | #include "cdefBF518.h" | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #if defined(CONFIG_BF516) | ||
| 66 | #include "cdefBF516.h" | ||
| 67 | #endif | ||
| 68 | |||
| 69 | #if defined(CONFIG_BF514) | ||
| 70 | #include "cdefBF514.h" | ||
| 71 | #endif | ||
| 72 | #endif | ||
| 73 | |||
| 74 | /* UART_IIR Register */ | ||
| 75 | #define STATUS(x) ((x << 1) & 0x06) | ||
| 76 | #define STATUS_P1 0x02 | ||
| 77 | #define STATUS_P0 0x01 | ||
| 78 | |||
| 79 | #define BFIN_UART_NR_PORTS 2 | ||
| 80 | |||
| 81 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | ||
| 82 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | ||
| 83 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | ||
| 84 | #define OFFSET_IER 0x04 /* Interrupt Enable Register */ | ||
| 85 | #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | ||
| 86 | #define OFFSET_IIR 0x08 /* Interrupt Identification Register */ | ||
| 87 | #define OFFSET_LCR 0x0C /* Line Control Register */ | ||
| 88 | #define OFFSET_MCR 0x10 /* Modem Control Register */ | ||
| 89 | #define OFFSET_LSR 0x14 /* Line Status Register */ | ||
| 90 | #define OFFSET_MSR 0x18 /* Modem Status Register */ | ||
| 91 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | ||
| 92 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | ||
| 93 | |||
| 94 | /* DPMC*/ | ||
| 95 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
| 96 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
| 97 | #define STOPCK_OFF STOPCK | ||
| 98 | |||
| 99 | /* PLL_DIV Masks */ | ||
| 100 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | ||
| 101 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | ||
| 102 | #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ | ||
| 103 | #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ | ||
| 104 | |||
| 105 | #endif | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h new file mode 100644 index 000000000000..820c13c4daaa --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/cdefbf512.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: system mmr register map | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _CDEF_BF512_H | ||
| 33 | #define _CDEF_BF512_H | ||
| 34 | |||
| 35 | /* include all Core registers and bit definitions */ | ||
| 36 | #include "defBF512.h" | ||
| 37 | |||
| 38 | /* include core specific register pointer definitions */ | ||
| 39 | #include <asm/cdef_LPBlackfin.h> | ||
| 40 | |||
| 41 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */ | ||
| 42 | |||
| 43 | /* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | ||
| 44 | #include "cdefBF51x_base.h" | ||
| 45 | |||
| 46 | #endif /* _CDEF_BF512_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h new file mode 100644 index 000000000000..9521e178fb28 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/cdefbf514.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: system mmr register map | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _CDEF_BF514_H | ||
| 33 | #define _CDEF_BF514_H | ||
| 34 | |||
| 35 | /* include all Core registers and bit definitions */ | ||
| 36 | #include "defBF514.h" | ||
| 37 | |||
| 38 | /* include core specific register pointer definitions */ | ||
| 39 | #include <asm/cdef_LPBlackfin.h> | ||
| 40 | |||
| 41 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ | ||
| 42 | |||
| 43 | /* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | ||
| 44 | #include "cdefBF51x_base.h" | ||
| 45 | |||
| 46 | /* The following are the #defines needed by ADSP-BF514 that are not in the common header */ | ||
| 47 | |||
| 48 | #endif /* _CDEF_BF514_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h new file mode 100644 index 000000000000..4e26ccfcef97 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h | |||
| @@ -0,0 +1,213 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/cdefbf516.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: system mmr register map | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _CDEF_BF516_H | ||
| 33 | #define _CDEF_BF516_H | ||
| 34 | |||
| 35 | /* include all Core registers and bit definitions */ | ||
| 36 | #include "defBF516.h" | ||
| 37 | |||
| 38 | /* include core specific register pointer definitions */ | ||
| 39 | #include <asm/cdef_LPBlackfin.h> | ||
| 40 | |||
| 41 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ | ||
| 42 | |||
| 43 | /* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | ||
| 44 | #include "cdefBF51x_base.h" | ||
| 45 | |||
| 46 | /* The following are the #defines needed by ADSP-BF516 that are not in the common header */ | ||
| 47 | |||
| 48 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | ||
| 49 | |||
| 50 | #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) | ||
| 51 | #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) | ||
| 52 | #define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) | ||
| 53 | #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) | ||
| 54 | #define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) | ||
| 55 | #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) | ||
| 56 | #define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) | ||
| 57 | #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) | ||
| 58 | #define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) | ||
| 59 | #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) | ||
| 60 | #define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) | ||
| 61 | #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) | ||
| 62 | #define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) | ||
| 63 | #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) | ||
| 64 | #define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) | ||
| 65 | #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) | ||
| 66 | #define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) | ||
| 67 | #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) | ||
| 68 | #define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) | ||
| 69 | #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) | ||
| 70 | #define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) | ||
| 71 | #define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) | ||
| 72 | #define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) | ||
| 73 | #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) | ||
| 74 | #define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) | ||
| 75 | #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) | ||
| 76 | #define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) | ||
| 77 | #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) | ||
| 78 | #define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) | ||
| 79 | #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) | ||
| 80 | #define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) | ||
| 81 | #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) | ||
| 82 | #define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) | ||
| 83 | #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) | ||
| 84 | #define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) | ||
| 85 | #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) | ||
| 86 | #define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) | ||
| 87 | #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) | ||
| 88 | |||
| 89 | #define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) | ||
| 90 | #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) | ||
| 91 | #define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) | ||
| 92 | #define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) | ||
| 93 | #define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) | ||
| 94 | #define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) | ||
| 95 | #define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) | ||
| 96 | #define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) | ||
| 97 | #define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) | ||
| 98 | #define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) | ||
| 99 | #define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) | ||
| 100 | #define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) | ||
| 101 | #define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) | ||
| 102 | #define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) | ||
| 103 | #define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) | ||
| 104 | #define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) | ||
| 105 | |||
| 106 | #define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) | ||
| 107 | #define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) | ||
| 108 | #define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) | ||
| 109 | #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) | ||
| 110 | #define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) | ||
| 111 | #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) | ||
| 112 | #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) | ||
| 113 | #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) | ||
| 114 | #define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) | ||
| 115 | #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) | ||
| 116 | |||
| 117 | #define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) | ||
| 118 | #define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) | ||
| 119 | #define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) | ||
| 120 | #define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) | ||
| 121 | #define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) | ||
| 122 | #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) | ||
| 123 | #define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) | ||
| 124 | #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) | ||
| 125 | #define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) | ||
| 126 | #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) | ||
| 127 | #define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) | ||
| 128 | #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) | ||
| 129 | #define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) | ||
| 130 | #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) | ||
| 131 | #define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) | ||
| 132 | #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) | ||
| 133 | #define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) | ||
| 134 | #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) | ||
| 135 | #define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) | ||
| 136 | #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) | ||
| 137 | #define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) | ||
| 138 | #define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) | ||
| 139 | #define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) | ||
| 140 | #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) | ||
| 141 | #define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) | ||
| 142 | #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) | ||
| 143 | #define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) | ||
| 144 | #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) | ||
| 145 | #define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) | ||
| 146 | #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) | ||
| 147 | #define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) | ||
| 148 | #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) | ||
| 149 | #define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) | ||
| 150 | #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) | ||
| 151 | #define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) | ||
| 152 | #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) | ||
| 153 | #define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) | ||
| 154 | #define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) | ||
| 155 | #define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) | ||
| 156 | #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) | ||
| 157 | #define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) | ||
| 158 | #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) | ||
| 159 | #define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) | ||
| 160 | #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) | ||
| 161 | #define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) | ||
| 162 | #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) | ||
| 163 | #define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) | ||
| 164 | #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) | ||
| 165 | |||
| 166 | #define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) | ||
| 167 | #define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) | ||
| 168 | #define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) | ||
| 169 | #define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) | ||
| 170 | #define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) | ||
| 171 | #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) | ||
| 172 | #define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) | ||
| 173 | #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) | ||
| 174 | #define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) | ||
| 175 | #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) | ||
| 176 | #define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) | ||
| 177 | #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) | ||
| 178 | #define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) | ||
| 179 | #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) | ||
| 180 | #define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) | ||
| 181 | #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) | ||
| 182 | #define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) | ||
| 183 | #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) | ||
| 184 | #define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) | ||
| 185 | #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) | ||
| 186 | #define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) | ||
| 187 | #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) | ||
| 188 | #define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) | ||
| 189 | #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) | ||
| 190 | #define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) | ||
| 191 | #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) | ||
| 192 | #define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) | ||
| 193 | #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) | ||
| 194 | #define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) | ||
| 195 | #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) | ||
| 196 | #define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) | ||
| 197 | #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) | ||
| 198 | #define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) | ||
| 199 | #define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) | ||
| 200 | #define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) | ||
| 201 | #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) | ||
| 202 | #define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) | ||
| 203 | #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) | ||
| 204 | #define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) | ||
| 205 | #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) | ||
| 206 | #define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) | ||
| 207 | #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) | ||
| 208 | #define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) | ||
| 209 | #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) | ||
| 210 | #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) | ||
| 211 | #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) | ||
| 212 | |||
| 213 | #endif /* _CDEF_BF516_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h new file mode 100644 index 000000000000..bafb370cfb3c --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h | |||
| @@ -0,0 +1,282 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/cdefbf518.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: system mmr register map | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _CDEF_BF518_H | ||
| 33 | #define _CDEF_BF518_H | ||
| 34 | |||
| 35 | /* include all Core registers and bit definitions */ | ||
| 36 | #include "defBF518.h" | ||
| 37 | |||
| 38 | /* include core specific register pointer definitions */ | ||
| 39 | #include <asm/cdef_LPBlackfin.h> | ||
| 40 | |||
| 41 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ | ||
| 42 | |||
| 43 | /* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | ||
| 44 | #include "cdefBF51x_base.h" | ||
| 45 | |||
| 46 | /* The following are the #defines needed by ADSP-BF518 that are not in the common header */ | ||
| 47 | |||
| 48 | |||
| 49 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | ||
| 50 | |||
| 51 | #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) | ||
| 52 | #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) | ||
| 53 | #define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) | ||
| 54 | #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) | ||
| 55 | #define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) | ||
| 56 | #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) | ||
| 57 | #define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) | ||
| 58 | #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) | ||
| 59 | #define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) | ||
| 60 | #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) | ||
| 61 | #define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) | ||
| 62 | #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) | ||
| 63 | #define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) | ||
| 64 | #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) | ||
| 65 | #define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) | ||
| 66 | #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) | ||
| 67 | #define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) | ||
| 68 | #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) | ||
| 69 | #define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) | ||
| 70 | #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) | ||
| 71 | #define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) | ||
| 72 | #define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) | ||
| 73 | #define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) | ||
| 74 | #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) | ||
| 75 | #define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) | ||
| 76 | #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) | ||
| 77 | #define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) | ||
| 78 | #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) | ||
| 79 | #define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) | ||
| 80 | #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) | ||
| 81 | #define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) | ||
| 82 | #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) | ||
| 83 | #define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) | ||
| 84 | #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) | ||
| 85 | #define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) | ||
| 86 | #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) | ||
| 87 | #define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) | ||
| 88 | #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) | ||
| 89 | |||
| 90 | #define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) | ||
| 91 | #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) | ||
| 92 | #define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) | ||
| 93 | #define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) | ||
| 94 | #define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) | ||
| 95 | #define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) | ||
| 96 | #define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) | ||
| 97 | #define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) | ||
| 98 | #define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) | ||
| 99 | #define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) | ||
| 100 | #define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) | ||
| 101 | #define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) | ||
| 102 | #define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) | ||
| 103 | #define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) | ||
| 104 | #define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) | ||
| 105 | #define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) | ||
| 106 | |||
| 107 | #define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) | ||
| 108 | #define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) | ||
| 109 | #define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) | ||
| 110 | #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) | ||
| 111 | #define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) | ||
| 112 | #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) | ||
| 113 | #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) | ||
| 114 | #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) | ||
| 115 | #define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) | ||
| 116 | #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) | ||
| 117 | |||
| 118 | #define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) | ||
| 119 | #define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) | ||
| 120 | #define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) | ||
| 121 | #define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) | ||
| 122 | #define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) | ||
| 123 | #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) | ||
| 124 | #define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) | ||
| 125 | #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) | ||
| 126 | #define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) | ||
| 127 | #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) | ||
| 128 | #define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) | ||
| 129 | #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) | ||
| 130 | #define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) | ||
| 131 | #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) | ||
| 132 | #define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) | ||
| 133 | #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) | ||
| 134 | #define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) | ||
| 135 | #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) | ||
| 136 | #define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) | ||
| 137 | #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) | ||
| 138 | #define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) | ||
| 139 | #define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) | ||
| 140 | #define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) | ||
| 141 | #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) | ||
| 142 | #define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) | ||
| 143 | #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) | ||
| 144 | #define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) | ||
| 145 | #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) | ||
| 146 | #define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) | ||
| 147 | #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) | ||
| 148 | #define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) | ||
| 149 | #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) | ||
| 150 | #define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) | ||
| 151 | #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) | ||
| 152 | #define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) | ||
| 153 | #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) | ||
| 154 | #define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) | ||
| 155 | #define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) | ||
| 156 | #define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) | ||
| 157 | #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) | ||
| 158 | #define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) | ||
| 159 | #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) | ||
| 160 | #define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) | ||
| 161 | #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) | ||
| 162 | #define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) | ||
| 163 | #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) | ||
| 164 | #define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) | ||
| 165 | #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) | ||
| 166 | |||
| 167 | #define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) | ||
| 168 | #define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) | ||
| 169 | #define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) | ||
| 170 | #define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) | ||
| 171 | #define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) | ||
| 172 | #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) | ||
| 173 | #define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) | ||
| 174 | #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) | ||
| 175 | #define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) | ||
| 176 | #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) | ||
| 177 | #define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) | ||
| 178 | #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) | ||
| 179 | #define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) | ||
| 180 | #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) | ||
| 181 | #define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) | ||
| 182 | #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) | ||
| 183 | #define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) | ||
| 184 | #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) | ||
| 185 | #define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) | ||
| 186 | #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) | ||
| 187 | #define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) | ||
| 188 | #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) | ||
| 189 | #define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) | ||
| 190 | #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) | ||
| 191 | #define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) | ||
| 192 | #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) | ||
| 193 | #define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) | ||
| 194 | #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) | ||
| 195 | #define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) | ||
| 196 | #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) | ||
| 197 | #define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) | ||
| 198 | #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) | ||
| 199 | #define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) | ||
| 200 | #define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) | ||
| 201 | #define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) | ||
| 202 | #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) | ||
| 203 | #define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) | ||
| 204 | #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) | ||
| 205 | #define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) | ||
| 206 | #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) | ||
| 207 | #define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) | ||
| 208 | #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) | ||
| 209 | #define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) | ||
| 210 | #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) | ||
| 211 | #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) | ||
| 212 | #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) | ||
| 213 | |||
| 214 | /* Removable Storage Interface Registers */ | ||
| 215 | |||
| 216 | #define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL) | ||
| 217 | #define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) | ||
| 218 | #define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) | ||
| 219 | #define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) | ||
| 220 | #define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) | ||
| 221 | #define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) | ||
| 222 | #define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) | ||
| 223 | #define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) | ||
| 224 | #define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) | ||
| 225 | #define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) | ||
| 226 | #define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) | ||
| 227 | #define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) | ||
| 228 | #define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) | ||
| 229 | #define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) | ||
| 230 | #define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) | ||
| 231 | #define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) | ||
| 232 | #define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) | ||
| 233 | #define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) | ||
| 234 | #define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) | ||
| 235 | #define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) | ||
| 236 | #define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) | ||
| 237 | #define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) | ||
| 238 | #define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) | ||
| 239 | #define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) | ||
| 240 | #define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) | ||
| 241 | #define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) | ||
| 242 | #define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) | ||
| 243 | #define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) | ||
| 244 | #define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) | ||
| 245 | #define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) | ||
| 246 | #define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) | ||
| 247 | #define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) | ||
| 248 | #define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) | ||
| 249 | #define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) | ||
| 250 | #define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) | ||
| 251 | #define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) | ||
| 252 | #define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL) | ||
| 253 | #define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val) | ||
| 254 | #define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) | ||
| 255 | #define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) | ||
| 256 | #define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT) | ||
| 257 | #define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val) | ||
| 258 | #define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK) | ||
| 259 | #define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val) | ||
| 260 | #define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) | ||
| 261 | #define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) | ||
| 262 | #define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) | ||
| 263 | #define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) | ||
| 264 | #define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) | ||
| 265 | #define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) | ||
| 266 | #define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) | ||
| 267 | #define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) | ||
| 268 | #define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) | ||
| 269 | #define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) | ||
| 270 | #define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) | ||
| 271 | #define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) | ||
| 272 | #define bfin_read_RSI_PID4() bfin_read16(RSI_PID4) | ||
| 273 | #define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val) | ||
| 274 | #define bfin_read_RSI_PID5() bfin_read16(RSI_PID5) | ||
| 275 | #define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val) | ||
| 276 | #define bfin_read_RSI_PID6() bfin_read16(RSI_PID6) | ||
| 277 | #define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val) | ||
| 278 | #define bfin_read_RSI_PID7() bfin_read16(RSI_PID7) | ||
| 279 | #define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val) | ||
| 280 | |||
| 281 | |||
| 282 | #endif /* _CDEF_BF518_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h new file mode 100644 index 000000000000..ee3d4733369c --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h | |||
| @@ -0,0 +1,1208 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/cdefBF51x_base.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _CDEF_BF52X_H | ||
| 32 | #define _CDEF_BF52X_H | ||
| 33 | |||
| 34 | #include <asm/blackfin.h> | ||
| 35 | |||
| 36 | #include "defBF51x_base.h" | ||
| 37 | |||
| 38 | /* Include core specific register pointer definitions */ | ||
| 39 | #include <asm/cdef_LPBlackfin.h> | ||
| 40 | |||
| 41 | /* ==== begin from cdefBF534.h ==== */ | ||
| 42 | |||
| 43 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
| 44 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | ||
| 45 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | ||
| 46 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | ||
| 47 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | ||
| 48 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | ||
| 49 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | ||
| 50 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | ||
| 51 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) | ||
| 52 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | ||
| 53 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) | ||
| 54 | |||
| 55 | |||
| 56 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
| 57 | #define bfin_read_SWRST() bfin_read16(SWRST) | ||
| 58 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) | ||
| 59 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | ||
| 60 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) | ||
| 61 | |||
| 62 | #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) | ||
| 63 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) | ||
| 64 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) | ||
| 65 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) | ||
| 66 | #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) | ||
| 67 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) | ||
| 68 | |||
| 69 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | ||
| 70 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) | ||
| 71 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | ||
| 72 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) | ||
| 73 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) | ||
| 74 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) | ||
| 75 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) | ||
| 76 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) | ||
| 77 | |||
| 78 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) | ||
| 79 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) | ||
| 80 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) | ||
| 81 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) | ||
| 82 | |||
| 83 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) | ||
| 84 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) | ||
| 85 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) | ||
| 86 | #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) | ||
| 87 | |||
| 88 | /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ | ||
| 89 | |||
| 90 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) | ||
| 91 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) | ||
| 92 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) | ||
| 93 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) | ||
| 94 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) | ||
| 95 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) | ||
| 96 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) | ||
| 97 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) | ||
| 98 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) | ||
| 99 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) | ||
| 100 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) | ||
| 101 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) | ||
| 102 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) | ||
| 103 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) | ||
| 104 | |||
| 105 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
| 106 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) | ||
| 107 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) | ||
| 108 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) | ||
| 109 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) | ||
| 110 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) | ||
| 111 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) | ||
| 112 | |||
| 113 | |||
| 114 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
| 115 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) | ||
| 116 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) | ||
| 117 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) | ||
| 118 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) | ||
| 119 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) | ||
| 120 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) | ||
| 121 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) | ||
| 122 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) | ||
| 123 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) | ||
| 124 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) | ||
| 125 | #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) | ||
| 126 | #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) | ||
| 127 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | ||
| 128 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) | ||
| 129 | |||
| 130 | |||
| 131 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 132 | #define bfin_read_UART0_THR() bfin_read16(UART0_THR) | ||
| 133 | #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) | ||
| 134 | #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) | ||
| 135 | #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) | ||
| 136 | #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) | ||
| 137 | #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) | ||
| 138 | #define bfin_read_UART0_IER() bfin_read16(UART0_IER) | ||
| 139 | #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) | ||
| 140 | #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) | ||
| 141 | #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) | ||
| 142 | #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) | ||
| 143 | #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) | ||
| 144 | #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) | ||
| 145 | #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) | ||
| 146 | #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) | ||
| 147 | #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) | ||
| 148 | #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) | ||
| 149 | #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) | ||
| 150 | #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) | ||
| 151 | #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) | ||
| 152 | #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) | ||
| 153 | #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) | ||
| 154 | #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) | ||
| 155 | #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) | ||
| 156 | |||
| 157 | |||
| 158 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ | ||
| 159 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) | ||
| 160 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) | ||
| 161 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) | ||
| 162 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) | ||
| 163 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) | ||
| 164 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) | ||
| 165 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) | ||
| 166 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) | ||
| 167 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) | ||
| 168 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) | ||
| 169 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) | ||
| 170 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) | ||
| 171 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) | ||
| 172 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) | ||
| 173 | |||
| 174 | |||
| 175 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
| 176 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | ||
| 177 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) | ||
| 178 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | ||
| 179 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) | ||
| 180 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | ||
| 181 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) | ||
| 182 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | ||
| 183 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) | ||
| 184 | |||
| 185 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | ||
| 186 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) | ||
| 187 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | ||
| 188 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) | ||
| 189 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | ||
| 190 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) | ||
| 191 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | ||
| 192 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) | ||
| 193 | |||
| 194 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | ||
| 195 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) | ||
| 196 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | ||
| 197 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) | ||
| 198 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | ||
| 199 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) | ||
| 200 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | ||
| 201 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) | ||
| 202 | |||
| 203 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) | ||
| 204 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) | ||
| 205 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) | ||
| 206 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) | ||
| 207 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) | ||
| 208 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) | ||
| 209 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) | ||
| 210 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) | ||
| 211 | |||
| 212 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) | ||
| 213 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) | ||
| 214 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) | ||
| 215 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) | ||
| 216 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) | ||
| 217 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) | ||
| 218 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) | ||
| 219 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) | ||
| 220 | |||
| 221 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) | ||
| 222 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) | ||
| 223 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) | ||
| 224 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) | ||
| 225 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) | ||
| 226 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) | ||
| 227 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) | ||
| 228 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) | ||
| 229 | |||
| 230 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) | ||
| 231 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) | ||
| 232 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) | ||
| 233 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) | ||
| 234 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) | ||
| 235 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) | ||
| 236 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) | ||
| 237 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) | ||
| 238 | |||
| 239 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) | ||
| 240 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) | ||
| 241 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) | ||
| 242 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) | ||
| 243 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) | ||
| 244 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) | ||
| 245 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) | ||
| 246 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) | ||
| 247 | |||
| 248 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) | ||
| 249 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) | ||
| 250 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) | ||
| 251 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) | ||
| 252 | #define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) | ||
| 253 | #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) | ||
| 254 | |||
| 255 | |||
| 256 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | ||
| 257 | #define bfin_read_PORTFIO() bfin_read16(PORTFIO) | ||
| 258 | #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) | ||
| 259 | #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) | ||
| 260 | #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) | ||
| 261 | #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) | ||
| 262 | #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) | ||
| 263 | #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) | ||
| 264 | #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) | ||
| 265 | #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) | ||
| 266 | #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) | ||
| 267 | #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) | ||
| 268 | #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) | ||
| 269 | #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) | ||
| 270 | #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) | ||
| 271 | #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) | ||
| 272 | #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) | ||
| 273 | #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) | ||
| 274 | #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) | ||
| 275 | #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) | ||
| 276 | #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) | ||
| 277 | #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) | ||
| 278 | #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) | ||
| 279 | #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) | ||
| 280 | #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) | ||
| 281 | #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) | ||
| 282 | #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) | ||
| 283 | #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) | ||
| 284 | #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) | ||
| 285 | #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) | ||
| 286 | #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) | ||
| 287 | #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) | ||
| 288 | #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) | ||
| 289 | #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) | ||
| 290 | #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) | ||
| 291 | |||
| 292 | |||
| 293 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 294 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | ||
| 295 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) | ||
| 296 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | ||
| 297 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) | ||
| 298 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | ||
| 299 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) | ||
| 300 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | ||
| 301 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) | ||
| 302 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | ||
| 303 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) | ||
| 304 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | ||
| 305 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) | ||
| 306 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) | ||
| 307 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) | ||
| 308 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) | ||
| 309 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) | ||
| 310 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) | ||
| 311 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) | ||
| 312 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) | ||
| 313 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) | ||
| 314 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | ||
| 315 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) | ||
| 316 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | ||
| 317 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) | ||
| 318 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | ||
| 319 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) | ||
| 320 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | ||
| 321 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) | ||
| 322 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | ||
| 323 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) | ||
| 324 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | ||
| 325 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) | ||
| 326 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | ||
| 327 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) | ||
| 328 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | ||
| 329 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) | ||
| 330 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | ||
| 331 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) | ||
| 332 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | ||
| 333 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) | ||
| 334 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | ||
| 335 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) | ||
| 336 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | ||
| 337 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) | ||
| 338 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | ||
| 339 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) | ||
| 340 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | ||
| 341 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) | ||
| 342 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | ||
| 343 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) | ||
| 344 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | ||
| 345 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) | ||
| 346 | |||
| 347 | |||
| 348 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 349 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | ||
| 350 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) | ||
| 351 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | ||
| 352 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) | ||
| 353 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | ||
| 354 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) | ||
| 355 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | ||
| 356 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) | ||
| 357 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | ||
| 358 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) | ||
| 359 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | ||
| 360 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) | ||
| 361 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) | ||
| 362 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) | ||
| 363 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) | ||
| 364 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) | ||
| 365 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) | ||
| 366 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) | ||
| 367 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) | ||
| 368 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) | ||
| 369 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | ||
| 370 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) | ||
| 371 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | ||
| 372 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) | ||
| 373 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | ||
| 374 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) | ||
| 375 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | ||
| 376 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) | ||
| 377 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | ||
| 378 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) | ||
| 379 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | ||
| 380 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) | ||
| 381 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | ||
| 382 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) | ||
| 383 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | ||
| 384 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) | ||
| 385 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | ||
| 386 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) | ||
| 387 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | ||
| 388 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) | ||
| 389 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | ||
| 390 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) | ||
| 391 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | ||
| 392 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) | ||
| 393 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | ||
| 394 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) | ||
| 395 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | ||
| 396 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) | ||
| 397 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | ||
| 398 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) | ||
| 399 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | ||
| 400 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) | ||
| 401 | |||
| 402 | |||
| 403 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 404 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | ||
| 405 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) | ||
| 406 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | ||
| 407 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) | ||
| 408 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | ||
| 409 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) | ||
| 410 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) | ||
| 411 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) | ||
| 412 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) | ||
| 413 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) | ||
| 414 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) | ||
| 415 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) | ||
| 416 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) | ||
| 417 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) | ||
| 418 | |||
| 419 | |||
| 420 | /* DMA Traffic Control Registers */ | ||
| 421 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | ||
| 422 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) | ||
| 423 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | ||
| 424 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) | ||
| 425 | |||
| 426 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
| 427 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | ||
| 428 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) | ||
| 429 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | ||
| 430 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) | ||
| 431 | |||
| 432 | /* DMA Controller */ | ||
| 433 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | ||
| 434 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) | ||
| 435 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) | ||
| 436 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) | ||
| 437 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) | ||
| 438 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) | ||
| 439 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | ||
| 440 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) | ||
| 441 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) | ||
| 442 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) | ||
| 443 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | ||
| 444 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) | ||
| 445 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | ||
| 446 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) | ||
| 447 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) | ||
| 448 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) | ||
| 449 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) | ||
| 450 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) | ||
| 451 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) | ||
| 452 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) | ||
| 453 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) | ||
| 454 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) | ||
| 455 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) | ||
| 456 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) | ||
| 457 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | ||
| 458 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) | ||
| 459 | |||
| 460 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) | ||
| 461 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) | ||
| 462 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) | ||
| 463 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) | ||
| 464 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) | ||
| 465 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) | ||
| 466 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | ||
| 467 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) | ||
| 468 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) | ||
| 469 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) | ||
| 470 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | ||
| 471 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) | ||
| 472 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | ||
| 473 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) | ||
| 474 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) | ||
| 475 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) | ||
| 476 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) | ||
| 477 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) | ||
| 478 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) | ||
| 479 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) | ||
| 480 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) | ||
| 481 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) | ||
| 482 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) | ||
| 483 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) | ||
| 484 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | ||
| 485 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) | ||
| 486 | |||
| 487 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) | ||
| 488 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) | ||
| 489 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) | ||
| 490 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) | ||
| 491 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) | ||
| 492 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) | ||
| 493 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | ||
| 494 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) | ||
| 495 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) | ||
| 496 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) | ||
| 497 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | ||
| 498 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) | ||
| 499 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | ||
| 500 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) | ||
| 501 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) | ||
| 502 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) | ||
| 503 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) | ||
| 504 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) | ||
| 505 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) | ||
| 506 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) | ||
| 507 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) | ||
| 508 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) | ||
| 509 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) | ||
| 510 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) | ||
| 511 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | ||
| 512 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) | ||
| 513 | |||
| 514 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) | ||
| 515 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) | ||
| 516 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) | ||
| 517 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) | ||
| 518 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) | ||
| 519 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) | ||
| 520 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | ||
| 521 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) | ||
| 522 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) | ||
| 523 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) | ||
| 524 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | ||
| 525 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) | ||
| 526 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | ||
| 527 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) | ||
| 528 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) | ||
| 529 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) | ||
| 530 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) | ||
| 531 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) | ||
| 532 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) | ||
| 533 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) | ||
| 534 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) | ||
| 535 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) | ||
| 536 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) | ||
| 537 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) | ||
| 538 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | ||
| 539 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) | ||
| 540 | |||
| 541 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) | ||
| 542 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) | ||
| 543 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) | ||
| 544 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) | ||
| 545 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) | ||
| 546 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) | ||
| 547 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | ||
| 548 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) | ||
| 549 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) | ||
| 550 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) | ||
| 551 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | ||
| 552 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) | ||
| 553 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | ||
| 554 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) | ||
| 555 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) | ||
| 556 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) | ||
| 557 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) | ||
| 558 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) | ||
| 559 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) | ||
| 560 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) | ||
| 561 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) | ||
| 562 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) | ||
| 563 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) | ||
| 564 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) | ||
| 565 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | ||
| 566 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) | ||
| 567 | |||
| 568 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) | ||
| 569 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) | ||
| 570 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) | ||
| 571 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) | ||
| 572 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) | ||
| 573 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) | ||
| 574 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | ||
| 575 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) | ||
| 576 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) | ||
| 577 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) | ||
| 578 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | ||
| 579 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) | ||
| 580 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | ||
| 581 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) | ||
| 582 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) | ||
| 583 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) | ||
| 584 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) | ||
| 585 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) | ||
| 586 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) | ||
| 587 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) | ||
| 588 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) | ||
| 589 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) | ||
| 590 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) | ||
| 591 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) | ||
| 592 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | ||
| 593 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) | ||
| 594 | |||
| 595 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) | ||
| 596 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) | ||
| 597 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) | ||
| 598 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) | ||
| 599 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) | ||
| 600 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) | ||
| 601 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | ||
| 602 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) | ||
| 603 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) | ||
| 604 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) | ||
| 605 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | ||
| 606 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) | ||
| 607 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | ||
| 608 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) | ||
| 609 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) | ||
| 610 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) | ||
| 611 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) | ||
| 612 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) | ||
| 613 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) | ||
| 614 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) | ||
| 615 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) | ||
| 616 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) | ||
| 617 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) | ||
| 618 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) | ||
| 619 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | ||
| 620 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) | ||
| 621 | |||
| 622 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) | ||
| 623 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) | ||
| 624 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) | ||
| 625 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) | ||
| 626 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) | ||
| 627 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) | ||
| 628 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | ||
| 629 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) | ||
| 630 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) | ||
| 631 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) | ||
| 632 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | ||
| 633 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) | ||
| 634 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | ||
| 635 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) | ||
| 636 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) | ||
| 637 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) | ||
| 638 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) | ||
| 639 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) | ||
| 640 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) | ||
| 641 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) | ||
| 642 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) | ||
| 643 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) | ||
| 644 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) | ||
| 645 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) | ||
| 646 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | ||
| 647 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) | ||
| 648 | |||
| 649 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) | ||
| 650 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) | ||
| 651 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) | ||
| 652 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) | ||
| 653 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) | ||
| 654 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) | ||
| 655 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) | ||
| 656 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) | ||
| 657 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) | ||
| 658 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) | ||
| 659 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) | ||
| 660 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) | ||
| 661 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) | ||
| 662 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) | ||
| 663 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) | ||
| 664 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) | ||
| 665 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) | ||
| 666 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) | ||
| 667 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) | ||
| 668 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) | ||
| 669 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) | ||
| 670 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) | ||
| 671 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) | ||
| 672 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) | ||
| 673 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) | ||
| 674 | #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) | ||
| 675 | |||
| 676 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) | ||
| 677 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) | ||
| 678 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) | ||
| 679 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) | ||
| 680 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) | ||
| 681 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) | ||
| 682 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) | ||
| 683 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) | ||
| 684 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) | ||
| 685 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) | ||
| 686 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) | ||
| 687 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) | ||
| 688 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) | ||
| 689 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) | ||
| 690 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) | ||
| 691 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) | ||
| 692 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) | ||
| 693 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) | ||
| 694 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) | ||
| 695 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) | ||
| 696 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) | ||
| 697 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) | ||
| 698 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) | ||
| 699 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) | ||
| 700 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) | ||
| 701 | #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) | ||
| 702 | |||
| 703 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) | ||
| 704 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) | ||
| 705 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) | ||
| 706 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) | ||
| 707 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) | ||
| 708 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) | ||
| 709 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) | ||
| 710 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) | ||
| 711 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) | ||
| 712 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) | ||
| 713 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) | ||
| 714 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) | ||
| 715 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) | ||
| 716 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) | ||
| 717 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) | ||
| 718 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) | ||
| 719 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) | ||
| 720 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) | ||
| 721 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) | ||
| 722 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) | ||
| 723 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) | ||
| 724 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) | ||
| 725 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) | ||
| 726 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) | ||
| 727 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) | ||
| 728 | #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) | ||
| 729 | |||
| 730 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) | ||
| 731 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) | ||
| 732 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) | ||
| 733 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) | ||
| 734 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) | ||
| 735 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) | ||
| 736 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) | ||
| 737 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) | ||
| 738 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) | ||
| 739 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) | ||
| 740 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) | ||
| 741 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) | ||
| 742 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) | ||
| 743 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) | ||
| 744 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) | ||
| 745 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) | ||
| 746 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) | ||
| 747 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) | ||
| 748 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) | ||
| 749 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) | ||
| 750 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) | ||
| 751 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) | ||
| 752 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) | ||
| 753 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) | ||
| 754 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) | ||
| 755 | #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) | ||
| 756 | |||
| 757 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) | ||
| 758 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) | ||
| 759 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) | ||
| 760 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) | ||
| 761 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) | ||
| 762 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) | ||
| 763 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) | ||
| 764 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) | ||
| 765 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) | ||
| 766 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) | ||
| 767 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) | ||
| 768 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) | ||
| 769 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) | ||
| 770 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) | ||
| 771 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) | ||
| 772 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) | ||
| 773 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) | ||
| 774 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) | ||
| 775 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) | ||
| 776 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) | ||
| 777 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) | ||
| 778 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) | ||
| 779 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) | ||
| 780 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) | ||
| 781 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) | ||
| 782 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) | ||
| 783 | |||
| 784 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) | ||
| 785 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) | ||
| 786 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) | ||
| 787 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) | ||
| 788 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) | ||
| 789 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) | ||
| 790 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) | ||
| 791 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) | ||
| 792 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) | ||
| 793 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) | ||
| 794 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) | ||
| 795 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) | ||
| 796 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) | ||
| 797 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) | ||
| 798 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) | ||
| 799 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) | ||
| 800 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) | ||
| 801 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) | ||
| 802 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) | ||
| 803 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) | ||
| 804 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) | ||
| 805 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) | ||
| 806 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) | ||
| 807 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) | ||
| 808 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) | ||
| 809 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) | ||
| 810 | |||
| 811 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) | ||
| 812 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) | ||
| 813 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) | ||
| 814 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) | ||
| 815 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) | ||
| 816 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) | ||
| 817 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) | ||
| 818 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) | ||
| 819 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) | ||
| 820 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) | ||
| 821 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) | ||
| 822 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) | ||
| 823 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) | ||
| 824 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) | ||
| 825 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) | ||
| 826 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) | ||
| 827 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) | ||
| 828 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) | ||
| 829 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) | ||
| 830 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) | ||
| 831 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) | ||
| 832 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) | ||
| 833 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) | ||
| 834 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) | ||
| 835 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) | ||
| 836 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) | ||
| 837 | |||
| 838 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) | ||
| 839 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) | ||
| 840 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) | ||
| 841 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) | ||
| 842 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) | ||
| 843 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) | ||
| 844 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) | ||
| 845 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) | ||
| 846 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) | ||
| 847 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) | ||
| 848 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) | ||
| 849 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) | ||
| 850 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) | ||
| 851 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) | ||
| 852 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) | ||
| 853 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) | ||
| 854 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) | ||
| 855 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) | ||
| 856 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) | ||
| 857 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) | ||
| 858 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) | ||
| 859 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) | ||
| 860 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) | ||
| 861 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) | ||
| 862 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) | ||
| 863 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) | ||
| 864 | |||
| 865 | |||
| 866 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | ||
| 867 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) | ||
| 868 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) | ||
| 869 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | ||
| 870 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) | ||
| 871 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) | ||
| 872 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) | ||
| 873 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) | ||
| 874 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) | ||
| 875 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | ||
| 876 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) | ||
| 877 | |||
| 878 | |||
| 879 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | ||
| 880 | |||
| 881 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | ||
| 882 | #define bfin_read_PORTGIO() bfin_read16(PORTGIO) | ||
| 883 | #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) | ||
| 884 | #define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) | ||
| 885 | #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) | ||
| 886 | #define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) | ||
| 887 | #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) | ||
| 888 | #define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) | ||
| 889 | #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) | ||
| 890 | #define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) | ||
| 891 | #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) | ||
| 892 | #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) | ||
| 893 | #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) | ||
| 894 | #define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) | ||
| 895 | #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) | ||
| 896 | #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) | ||
| 897 | #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) | ||
| 898 | #define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) | ||
| 899 | #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) | ||
| 900 | #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) | ||
| 901 | #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) | ||
| 902 | #define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) | ||
| 903 | #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) | ||
| 904 | #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) | ||
| 905 | #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) | ||
| 906 | #define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) | ||
| 907 | #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) | ||
| 908 | #define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) | ||
| 909 | #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) | ||
| 910 | #define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) | ||
| 911 | #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) | ||
| 912 | #define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) | ||
| 913 | #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) | ||
| 914 | #define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) | ||
| 915 | #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) | ||
| 916 | |||
| 917 | |||
| 918 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | ||
| 919 | #define bfin_read_PORTHIO() bfin_read16(PORTHIO) | ||
| 920 | #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) | ||
| 921 | #define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) | ||
| 922 | #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) | ||
| 923 | #define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) | ||
| 924 | #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) | ||
| 925 | #define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) | ||
| 926 | #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) | ||
| 927 | #define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) | ||
| 928 | #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) | ||
| 929 | #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) | ||
| 930 | #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) | ||
| 931 | #define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) | ||
| 932 | #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) | ||
| 933 | #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) | ||
| 934 | #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) | ||
| 935 | #define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) | ||
| 936 | #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) | ||
| 937 | #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) | ||
| 938 | #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) | ||
| 939 | #define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) | ||
| 940 | #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) | ||
| 941 | #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) | ||
| 942 | #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) | ||
| 943 | #define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) | ||
| 944 | #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) | ||
| 945 | #define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) | ||
| 946 | #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) | ||
| 947 | #define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) | ||
| 948 | #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) | ||
| 949 | #define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) | ||
| 950 | #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) | ||
| 951 | #define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) | ||
| 952 | #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) | ||
| 953 | |||
| 954 | |||
| 955 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
| 956 | #define bfin_read_UART1_THR() bfin_read16(UART1_THR) | ||
| 957 | #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) | ||
| 958 | #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) | ||
| 959 | #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) | ||
| 960 | #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) | ||
| 961 | #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) | ||
| 962 | #define bfin_read_UART1_IER() bfin_read16(UART1_IER) | ||
| 963 | #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) | ||
| 964 | #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) | ||
| 965 | #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) | ||
| 966 | #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) | ||
| 967 | #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) | ||
| 968 | #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) | ||
| 969 | #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) | ||
| 970 | #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) | ||
| 971 | #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) | ||
| 972 | #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) | ||
| 973 | #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) | ||
| 974 | #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) | ||
| 975 | #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) | ||
| 976 | #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) | ||
| 977 | #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) | ||
| 978 | #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) | ||
| 979 | #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) | ||
| 980 | |||
| 981 | /* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */ | ||
| 982 | |||
| 983 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | ||
| 984 | #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) | ||
| 985 | #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) | ||
| 986 | #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) | ||
| 987 | #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) | ||
| 988 | #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) | ||
| 989 | #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) | ||
| 990 | #define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) | ||
| 991 | #define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) | ||
| 992 | |||
| 993 | |||
| 994 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | ||
| 995 | #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) | ||
| 996 | #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) | ||
| 997 | #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) | ||
| 998 | #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) | ||
| 999 | #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) | ||
| 1000 | #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) | ||
| 1001 | #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) | ||
| 1002 | #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) | ||
| 1003 | #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) | ||
| 1004 | #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) | ||
| 1005 | #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) | ||
| 1006 | #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) | ||
| 1007 | #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) | ||
| 1008 | #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) | ||
| 1009 | |||
| 1010 | #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) | ||
| 1011 | #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) | ||
| 1012 | #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) | ||
| 1013 | #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) | ||
| 1014 | #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) | ||
| 1015 | #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) | ||
| 1016 | #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) | ||
| 1017 | #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) | ||
| 1018 | #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) | ||
| 1019 | #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) | ||
| 1020 | #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) | ||
| 1021 | #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) | ||
| 1022 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) | ||
| 1023 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) | ||
| 1024 | |||
| 1025 | /* ==== end from cdefBF534.h ==== */ | ||
| 1026 | |||
| 1027 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | ||
| 1028 | |||
| 1029 | #define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) | ||
| 1030 | #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) | ||
| 1031 | #define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) | ||
| 1032 | #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) | ||
| 1033 | #define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) | ||
| 1034 | #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) | ||
| 1035 | |||
| 1036 | #define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) | ||
| 1037 | #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) | ||
| 1038 | #define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) | ||
| 1039 | #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) | ||
| 1040 | #define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) | ||
| 1041 | #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) | ||
| 1042 | #define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) | ||
| 1043 | #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) | ||
| 1044 | #define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) | ||
| 1045 | #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) | ||
| 1046 | #define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) | ||
| 1047 | #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) | ||
| 1048 | #define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) | ||
| 1049 | #define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) | ||
| 1050 | #define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) | ||
| 1051 | #define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) | ||
| 1052 | #define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) | ||
| 1053 | #define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) | ||
| 1054 | #define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) | ||
| 1055 | #define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) | ||
| 1056 | #define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) | ||
| 1057 | #define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) | ||
| 1058 | #define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) | ||
| 1059 | #define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) | ||
| 1060 | |||
| 1061 | /* HOST Port Registers */ | ||
| 1062 | |||
| 1063 | #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) | ||
| 1064 | #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) | ||
| 1065 | #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) | ||
| 1066 | #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) | ||
| 1067 | #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) | ||
| 1068 | #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) | ||
| 1069 | |||
| 1070 | /* Counter Registers */ | ||
| 1071 | |||
| 1072 | #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) | ||
| 1073 | #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) | ||
| 1074 | #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) | ||
| 1075 | #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) | ||
| 1076 | #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) | ||
| 1077 | #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) | ||
| 1078 | #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) | ||
| 1079 | #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) | ||
| 1080 | #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) | ||
| 1081 | #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) | ||
| 1082 | #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) | ||
| 1083 | #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) | ||
| 1084 | #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) | ||
| 1085 | #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) | ||
| 1086 | #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) | ||
| 1087 | #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) | ||
| 1088 | |||
| 1089 | /* OTP/FUSE Registers */ | ||
| 1090 | |||
| 1091 | #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) | ||
| 1092 | #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) | ||
| 1093 | #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) | ||
| 1094 | #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) | ||
| 1095 | #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) | ||
| 1096 | #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) | ||
| 1097 | #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) | ||
| 1098 | #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) | ||
| 1099 | |||
| 1100 | /* Security Registers */ | ||
| 1101 | |||
| 1102 | #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) | ||
| 1103 | #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) | ||
| 1104 | #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) | ||
| 1105 | #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) | ||
| 1106 | #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) | ||
| 1107 | #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) | ||
| 1108 | |||
| 1109 | /* OTP Read/Write Data Buffer Registers */ | ||
| 1110 | |||
| 1111 | #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) | ||
| 1112 | #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) | ||
| 1113 | #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) | ||
| 1114 | #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) | ||
| 1115 | #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) | ||
| 1116 | #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) | ||
| 1117 | #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) | ||
| 1118 | #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) | ||
| 1119 | |||
| 1120 | /* NFC Registers */ | ||
| 1121 | |||
| 1122 | #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) | ||
| 1123 | #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) | ||
| 1124 | #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) | ||
| 1125 | #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) | ||
| 1126 | #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) | ||
| 1127 | #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) | ||
| 1128 | #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) | ||
| 1129 | #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) | ||
| 1130 | #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) | ||
| 1131 | #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) | ||
| 1132 | #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) | ||
| 1133 | #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) | ||
| 1134 | #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) | ||
| 1135 | #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) | ||
| 1136 | #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) | ||
| 1137 | #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) | ||
| 1138 | #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) | ||
| 1139 | #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) | ||
| 1140 | #define bfin_read_NFC_RST() bfin_read16(NFC_RST) | ||
| 1141 | #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) | ||
| 1142 | #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) | ||
| 1143 | #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) | ||
| 1144 | #define bfin_read_NFC_READ() bfin_read16(NFC_READ) | ||
| 1145 | #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) | ||
| 1146 | #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) | ||
| 1147 | #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) | ||
| 1148 | #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) | ||
| 1149 | #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) | ||
| 1150 | #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) | ||
| 1151 | #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) | ||
| 1152 | #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) | ||
| 1153 | #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) | ||
| 1154 | |||
| 1155 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 1156 | #include <asm/irq.h> | ||
| 1157 | |||
| 1158 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 1159 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 1160 | { | ||
| 1161 | unsigned long flags, iwr0, iwr1; | ||
| 1162 | |||
| 1163 | if (val == bfin_read_PLL_CTL()) | ||
| 1164 | return; | ||
| 1165 | |||
| 1166 | local_irq_save_hw(flags); | ||
| 1167 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 1168 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 1169 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 1170 | /* Only allow PPL Wakeup) */ | ||
| 1171 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 1172 | bfin_write32(SIC_IWR1, 0); | ||
| 1173 | |||
| 1174 | bfin_write16(PLL_CTL, val); | ||
| 1175 | SSYNC(); | ||
| 1176 | asm("IDLE;"); | ||
| 1177 | |||
| 1178 | bfin_write32(SIC_IWR0, iwr0); | ||
| 1179 | bfin_write32(SIC_IWR1, iwr1); | ||
| 1180 | local_irq_restore_hw(flags); | ||
| 1181 | } | ||
| 1182 | |||
| 1183 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 1184 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 1185 | { | ||
| 1186 | unsigned long flags, iwr0, iwr1; | ||
| 1187 | |||
| 1188 | if (val == bfin_read_VR_CTL()) | ||
| 1189 | return; | ||
| 1190 | |||
| 1191 | local_irq_save_hw(flags); | ||
| 1192 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 1193 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 1194 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 1195 | /* Only allow PPL Wakeup) */ | ||
| 1196 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 1197 | bfin_write32(SIC_IWR1, 0); | ||
| 1198 | |||
| 1199 | bfin_write16(VR_CTL, val); | ||
| 1200 | SSYNC(); | ||
| 1201 | asm("IDLE;"); | ||
| 1202 | |||
| 1203 | bfin_write32(SIC_IWR0, iwr0); | ||
| 1204 | bfin_write32(SIC_IWR1, iwr1); | ||
| 1205 | local_irq_restore_hw(flags); | ||
| 1206 | } | ||
| 1207 | |||
| 1208 | #endif /* _CDEF_BF52X_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h new file mode 100644 index 000000000000..a96ca90154dd --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/defBF512.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _DEF_BF512_H | ||
| 32 | #define _DEF_BF512_H | ||
| 33 | |||
| 34 | /* Include all Core registers and bit definitions */ | ||
| 35 | #include <asm/def_LPBlackfin.h> | ||
| 36 | |||
| 37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */ | ||
| 38 | |||
| 39 | /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | ||
| 40 | #include "defBF51x_base.h" | ||
| 41 | |||
| 42 | #endif /* _DEF_BF512_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h new file mode 100644 index 000000000000..543f2913b3f5 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/defBF514.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _DEF_BF514_H | ||
| 32 | #define _DEF_BF514_H | ||
| 33 | |||
| 34 | /* Include all Core registers and bit definitions */ | ||
| 35 | #include <asm/def_LPBlackfin.h> | ||
| 36 | |||
| 37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ | ||
| 38 | |||
| 39 | /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | ||
| 40 | #include "defBF51x_base.h" | ||
| 41 | |||
| 42 | /* The following are the #defines needed by ADSP-BF514 that are not in the common header */ | ||
| 43 | |||
| 44 | /* SDH Registers */ | ||
| 45 | |||
| 46 | #define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ | ||
| 47 | #define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ | ||
| 48 | #define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ | ||
| 49 | #define SDH_COMMAND 0xFFC0390C /* SDH Command */ | ||
| 50 | #define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ | ||
| 51 | #define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ | ||
| 52 | #define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ | ||
| 53 | #define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ | ||
| 54 | #define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ | ||
| 55 | #define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ | ||
| 56 | #define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ | ||
| 57 | #define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ | ||
| 58 | #define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ | ||
| 59 | #define SDH_STATUS 0xFFC03934 /* SDH Status */ | ||
| 60 | #define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ | ||
| 61 | #define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ | ||
| 62 | #define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ | ||
| 63 | #define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ | ||
| 64 | #define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ | ||
| 65 | #define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ | ||
| 66 | #define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ | ||
| 67 | #define SDH_CFG 0xFFC039C8 /* SDH Configuration */ | ||
| 68 | #define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ | ||
| 69 | #define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ | ||
| 70 | #define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ | ||
| 71 | #define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ | ||
| 72 | #define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ | ||
| 73 | #define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ | ||
| 74 | #define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ | ||
| 75 | #define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ | ||
| 76 | #define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ | ||
| 77 | |||
| 78 | /* Removable Storage Interface Registers */ | ||
| 79 | |||
| 80 | #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ | ||
| 81 | #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ | ||
| 82 | #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ | ||
| 83 | #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ | ||
| 84 | #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ | ||
| 85 | #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ | ||
| 86 | #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ | ||
| 87 | #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ | ||
| 88 | #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ | ||
| 89 | #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ | ||
| 90 | #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ | ||
| 91 | #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ | ||
| 92 | #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ | ||
| 93 | #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ | ||
| 94 | #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ | ||
| 95 | #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ | ||
| 96 | #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ | ||
| 97 | #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ | ||
| 98 | #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ | ||
| 99 | #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ | ||
| 100 | #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ | ||
| 101 | #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ | ||
| 102 | #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ | ||
| 103 | #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ | ||
| 104 | #define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ | ||
| 105 | #define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ | ||
| 106 | #define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ | ||
| 107 | #define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ | ||
| 108 | #define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ | ||
| 109 | #define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ | ||
| 110 | #define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ | ||
| 111 | #define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ | ||
| 112 | |||
| 113 | #endif /* _DEF_BF514_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h new file mode 100644 index 000000000000..149a269306c5 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h | |||
| @@ -0,0 +1,490 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/defBF516.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _DEF_BF516_H | ||
| 32 | #define _DEF_BF516_H | ||
| 33 | |||
| 34 | /* Include all Core registers and bit definitions */ | ||
| 35 | #include <asm/def_LPBlackfin.h> | ||
| 36 | |||
| 37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ | ||
| 38 | |||
| 39 | /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | ||
| 40 | #include "defBF51x_base.h" | ||
| 41 | |||
| 42 | /* The following are the #defines needed by ADSP-BF516 that are not in the common header */ | ||
| 43 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | ||
| 44 | |||
| 45 | #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ | ||
| 46 | #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ | ||
| 47 | #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ | ||
| 48 | #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ | ||
| 49 | #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ | ||
| 50 | #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ | ||
| 51 | #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ | ||
| 52 | #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ | ||
| 53 | #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ | ||
| 54 | #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ | ||
| 55 | #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ | ||
| 56 | #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ | ||
| 57 | #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ | ||
| 58 | #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ | ||
| 59 | #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ | ||
| 60 | #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ | ||
| 61 | #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ | ||
| 62 | #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ | ||
| 63 | #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ | ||
| 64 | |||
| 65 | #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ | ||
| 66 | #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ | ||
| 67 | #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ | ||
| 68 | #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ | ||
| 69 | #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ | ||
| 70 | #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ | ||
| 71 | #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ | ||
| 72 | #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ | ||
| 73 | |||
| 74 | #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ | ||
| 75 | #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ | ||
| 76 | #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ | ||
| 77 | #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ | ||
| 78 | #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ | ||
| 79 | |||
| 80 | #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ | ||
| 81 | #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ | ||
| 82 | #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ | ||
| 83 | #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ | ||
| 84 | #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ | ||
| 85 | #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ | ||
| 86 | #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ | ||
| 87 | #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ | ||
| 88 | #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ | ||
| 89 | #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ | ||
| 90 | #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ | ||
| 91 | #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ | ||
| 92 | #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ | ||
| 93 | #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ | ||
| 94 | #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ | ||
| 95 | #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ | ||
| 96 | #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ | ||
| 97 | #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
| 98 | #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ | ||
| 99 | #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ | ||
| 100 | #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 101 | #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 102 | #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 103 | #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
| 104 | |||
| 105 | #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ | ||
| 106 | #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ | ||
| 107 | #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ | ||
| 108 | #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ | ||
| 109 | #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ | ||
| 110 | #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ | ||
| 111 | #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ | ||
| 112 | #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ | ||
| 113 | #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ | ||
| 114 | #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ | ||
| 115 | #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ | ||
| 116 | #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ | ||
| 117 | #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ | ||
| 118 | #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ | ||
| 119 | #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ | ||
| 120 | #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ | ||
| 121 | #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ | ||
| 122 | #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | ||
| 123 | #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 124 | #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 125 | #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 126 | #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
| 127 | #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ | ||
| 128 | |||
| 129 | /* Listing for IEEE-Supported Count Registers */ | ||
| 130 | |||
| 131 | #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ | ||
| 132 | #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ | ||
| 133 | #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ | ||
| 134 | #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ | ||
| 135 | #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ | ||
| 136 | #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ | ||
| 137 | #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ | ||
| 138 | #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ | ||
| 139 | #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ | ||
| 140 | #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ | ||
| 141 | #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ | ||
| 142 | #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ | ||
| 143 | #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ | ||
| 144 | #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ | ||
| 145 | #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ | ||
| 146 | #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ | ||
| 147 | #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ | ||
| 148 | #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
| 149 | #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ | ||
| 150 | #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ | ||
| 151 | #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 152 | #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 153 | #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 154 | #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
| 155 | |||
| 156 | #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ | ||
| 157 | #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ | ||
| 158 | #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ | ||
| 159 | #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ | ||
| 160 | #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ | ||
| 161 | #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ | ||
| 162 | #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ | ||
| 163 | #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ | ||
| 164 | #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ | ||
| 165 | #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ | ||
| 166 | #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ | ||
| 167 | #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ | ||
| 168 | #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ | ||
| 169 | #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ | ||
| 170 | #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ | ||
| 171 | #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ | ||
| 172 | #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ | ||
| 173 | #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | ||
| 174 | #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 175 | #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 176 | #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 177 | #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
| 178 | #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ | ||
| 179 | |||
| 180 | /*********************************************************************************** | ||
| 181 | ** System MMR Register Bits And Macros | ||
| 182 | ** | ||
| 183 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
| 184 | ** Use these macros carefully, as any that do left shifts for field | ||
| 185 | ** depositing will result in the lower order bits being destroyed. Any | ||
| 186 | ** macro that shifts left to properly position the bit-field should be | ||
| 187 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
| 188 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
| 189 | ** the macro is used. | ||
| 190 | *************************************************************************************/ | ||
| 191 | |||
| 192 | /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ | ||
| 193 | |||
| 194 | /* EMAC_OPMODE Masks */ | ||
| 195 | |||
| 196 | #define RE 0x00000001 /* Receiver Enable */ | ||
| 197 | #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ | ||
| 198 | #define HU 0x00000010 /* Hash Filter Unicast Address */ | ||
| 199 | #define HM 0x00000020 /* Hash Filter Multicast Address */ | ||
| 200 | #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ | ||
| 201 | #define PR 0x00000080 /* Promiscuous Mode Enable */ | ||
| 202 | #define IFE 0x00000100 /* Inverse Filtering Enable */ | ||
| 203 | #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ | ||
| 204 | #define PBF 0x00000400 /* Pass Bad Frames Enable */ | ||
| 205 | #define PSF 0x00000800 /* Pass Short Frames Enable */ | ||
| 206 | #define RAF 0x00001000 /* Receive-All Mode */ | ||
| 207 | #define TE 0x00010000 /* Transmitter Enable */ | ||
| 208 | #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ | ||
| 209 | #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ | ||
| 210 | #define DC 0x00080000 /* Deferral Check */ | ||
| 211 | #define BOLMT 0x00300000 /* Back-Off Limit */ | ||
| 212 | #define BOLMT_10 0x00000000 /* 10-bit range */ | ||
| 213 | #define BOLMT_8 0x00100000 /* 8-bit range */ | ||
| 214 | #define BOLMT_4 0x00200000 /* 4-bit range */ | ||
| 215 | #define BOLMT_1 0x00300000 /* 1-bit range */ | ||
| 216 | #define DRTY 0x00400000 /* Disable TX Retry On Collision */ | ||
| 217 | #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ | ||
| 218 | #define RMII 0x01000000 /* RMII/MII* Mode */ | ||
| 219 | #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ | ||
| 220 | #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ | ||
| 221 | #define LB 0x08000000 /* Internal Loopback Enable */ | ||
| 222 | #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ | ||
| 223 | |||
| 224 | /* EMAC_STAADD Masks */ | ||
| 225 | |||
| 226 | #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ | ||
| 227 | #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ | ||
| 228 | #define STADISPRE 0x00000004 /* Disable Preamble Generation */ | ||
| 229 | #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ | ||
| 230 | #define REGAD 0x000007C0 /* STA Register Address */ | ||
| 231 | #define PHYAD 0x0000F800 /* PHY Device Address */ | ||
| 232 | |||
| 233 | #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ | ||
| 234 | #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ | ||
| 235 | |||
| 236 | /* EMAC_STADAT Mask */ | ||
| 237 | |||
| 238 | #define STADATA 0x0000FFFF /* Station Management Data */ | ||
| 239 | |||
| 240 | /* EMAC_FLC Masks */ | ||
| 241 | |||
| 242 | #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ | ||
| 243 | #define FLCE 0x00000002 /* Flow Control Enable */ | ||
| 244 | #define PCF 0x00000004 /* Pass Control Frames */ | ||
| 245 | #define BKPRSEN 0x00000008 /* Enable Backpressure */ | ||
| 246 | #define FLCPAUSE 0xFFFF0000 /* Pause Time */ | ||
| 247 | |||
| 248 | #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ | ||
| 249 | |||
| 250 | /* EMAC_WKUP_CTL Masks */ | ||
| 251 | |||
| 252 | #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ | ||
| 253 | #define MPKE 0x00000002 /* Magic Packet Enable */ | ||
| 254 | #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ | ||
| 255 | #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ | ||
| 256 | #define MPKS 0x00000020 /* Magic Packet Received Status */ | ||
| 257 | #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ | ||
| 258 | |||
| 259 | /* EMAC_WKUP_FFCMD Masks */ | ||
| 260 | |||
| 261 | #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ | ||
| 262 | #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ | ||
| 263 | #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ | ||
| 264 | #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ | ||
| 265 | #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ | ||
| 266 | #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ | ||
| 267 | #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ | ||
| 268 | #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ | ||
| 269 | |||
| 270 | /* EMAC_WKUP_FFOFF Masks */ | ||
| 271 | |||
| 272 | #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ | ||
| 273 | #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ | ||
| 274 | #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ | ||
| 275 | #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ | ||
| 276 | |||
| 277 | #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ | ||
| 278 | #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ | ||
| 279 | #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ | ||
| 280 | #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ | ||
| 281 | /* Set ALL Offsets */ | ||
| 282 | #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) | ||
| 283 | |||
| 284 | /* EMAC_WKUP_FFCRC0 Masks */ | ||
| 285 | |||
| 286 | #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ | ||
| 287 | #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ | ||
| 288 | |||
| 289 | #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ | ||
| 290 | #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ | ||
| 291 | |||
| 292 | /* EMAC_WKUP_FFCRC1 Masks */ | ||
| 293 | |||
| 294 | #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ | ||
| 295 | #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ | ||
| 296 | |||
| 297 | #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ | ||
| 298 | #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ | ||
| 299 | |||
| 300 | /* EMAC_SYSCTL Masks */ | ||
| 301 | |||
| 302 | #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ | ||
| 303 | #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ | ||
| 304 | #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ | ||
| 305 | #define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ | ||
| 306 | #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ | ||
| 307 | |||
| 308 | #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ | ||
| 309 | |||
| 310 | /* EMAC_SYSTAT Masks */ | ||
| 311 | |||
| 312 | #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ | ||
| 313 | #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ | ||
| 314 | #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ | ||
| 315 | #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ | ||
| 316 | #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ | ||
| 317 | #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ | ||
| 318 | #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ | ||
| 319 | #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ | ||
| 320 | |||
| 321 | /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ | ||
| 322 | |||
| 323 | #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ | ||
| 324 | #define RX_COMP 0x00001000 /* RX Frame Complete */ | ||
| 325 | #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ | ||
| 326 | #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ | ||
| 327 | #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ | ||
| 328 | #define RX_CRC 0x00010000 /* RX Frame CRC Error */ | ||
| 329 | #define RX_LEN 0x00020000 /* RX Frame Length Error */ | ||
| 330 | #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ | ||
| 331 | #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ | ||
| 332 | #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ | ||
| 333 | #define RX_PHY 0x00200000 /* RX Frame PHY Error */ | ||
| 334 | #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ | ||
| 335 | #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ | ||
| 336 | #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ | ||
| 337 | #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ | ||
| 338 | #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ | ||
| 339 | #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ | ||
| 340 | #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ | ||
| 341 | #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ | ||
| 342 | #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ | ||
| 343 | #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ | ||
| 344 | |||
| 345 | /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ | ||
| 346 | |||
| 347 | #define TX_COMP 0x00000001 /* TX Frame Complete */ | ||
| 348 | #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ | ||
| 349 | #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ | ||
| 350 | #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ | ||
| 351 | #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ | ||
| 352 | #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ | ||
| 353 | #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ | ||
| 354 | #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ | ||
| 355 | #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ | ||
| 356 | #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ | ||
| 357 | #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ | ||
| 358 | #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ | ||
| 359 | #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ | ||
| 360 | #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ | ||
| 361 | #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ | ||
| 362 | |||
| 363 | /* EMAC_MMC_CTL Masks */ | ||
| 364 | #define RSTC 0x00000001 /* Reset All Counters */ | ||
| 365 | #define CROLL 0x00000002 /* Counter Roll-Over Enable */ | ||
| 366 | #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ | ||
| 367 | #define MMCE 0x00000008 /* Enable MMC Counter Operation */ | ||
| 368 | |||
| 369 | /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ | ||
| 370 | #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ | ||
| 371 | #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ | ||
| 372 | #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ | ||
| 373 | #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ | ||
| 374 | #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ | ||
| 375 | #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ | ||
| 376 | #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ | ||
| 377 | #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ | ||
| 378 | #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ | ||
| 379 | #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ | ||
| 380 | #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ | ||
| 381 | #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ | ||
| 382 | #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ | ||
| 383 | #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ | ||
| 384 | #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ | ||
| 385 | #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ | ||
| 386 | #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ | ||
| 387 | #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ | ||
| 388 | #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ | ||
| 389 | #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ | ||
| 390 | #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ | ||
| 391 | #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ | ||
| 392 | #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ | ||
| 393 | #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ | ||
| 394 | |||
| 395 | /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ | ||
| 396 | |||
| 397 | #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ | ||
| 398 | #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ | ||
| 399 | #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ | ||
| 400 | #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ | ||
| 401 | #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ | ||
| 402 | #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ | ||
| 403 | #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ | ||
| 404 | #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ | ||
| 405 | #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ | ||
| 406 | #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ | ||
| 407 | #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ | ||
| 408 | #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ | ||
| 409 | #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ | ||
| 410 | #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ | ||
| 411 | #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ | ||
| 412 | #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ | ||
| 413 | #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ | ||
| 414 | #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ | ||
| 415 | #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ | ||
| 416 | #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ | ||
| 417 | #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ | ||
| 418 | #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ | ||
| 419 | #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ | ||
| 420 | |||
| 421 | /* SDH Registers */ | ||
| 422 | |||
| 423 | #define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ | ||
| 424 | #define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ | ||
| 425 | #define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ | ||
| 426 | #define SDH_COMMAND 0xFFC0390C /* SDH Command */ | ||
| 427 | #define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ | ||
| 428 | #define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ | ||
| 429 | #define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ | ||
| 430 | #define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ | ||
| 431 | #define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ | ||
| 432 | #define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ | ||
| 433 | #define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ | ||
| 434 | #define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ | ||
| 435 | #define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ | ||
| 436 | #define SDH_STATUS 0xFFC03934 /* SDH Status */ | ||
| 437 | #define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ | ||
| 438 | #define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ | ||
| 439 | #define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ | ||
| 440 | #define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ | ||
| 441 | #define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ | ||
| 442 | #define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ | ||
| 443 | #define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ | ||
| 444 | #define SDH_CFG 0xFFC039C8 /* SDH Configuration */ | ||
| 445 | #define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ | ||
| 446 | #define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ | ||
| 447 | #define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ | ||
| 448 | #define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ | ||
| 449 | #define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ | ||
| 450 | #define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ | ||
| 451 | #define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ | ||
| 452 | #define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ | ||
| 453 | #define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ | ||
| 454 | |||
| 455 | /* Removable Storage Interface Registers */ | ||
| 456 | |||
| 457 | #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ | ||
| 458 | #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ | ||
| 459 | #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ | ||
| 460 | #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ | ||
| 461 | #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ | ||
| 462 | #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ | ||
| 463 | #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ | ||
| 464 | #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ | ||
| 465 | #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ | ||
| 466 | #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ | ||
| 467 | #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ | ||
| 468 | #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ | ||
| 469 | #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ | ||
| 470 | #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ | ||
| 471 | #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ | ||
| 472 | #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ | ||
| 473 | #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ | ||
| 474 | #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ | ||
| 475 | #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ | ||
| 476 | #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ | ||
| 477 | #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ | ||
| 478 | #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ | ||
| 479 | #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ | ||
| 480 | #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ | ||
| 481 | #define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ | ||
| 482 | #define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ | ||
| 483 | #define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ | ||
| 484 | #define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ | ||
| 485 | #define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ | ||
| 486 | #define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ | ||
| 487 | #define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ | ||
| 488 | #define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ | ||
| 489 | |||
| 490 | #endif /* _DEF_BF516_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h new file mode 100644 index 000000000000..6e982abf4ede --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h | |||
| @@ -0,0 +1,651 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/defBF518.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _DEF_BF518_H | ||
| 32 | #define _DEF_BF518_H | ||
| 33 | |||
| 34 | /* Include all Core registers and bit definitions */ | ||
| 35 | #include <asm/def_LPBlackfin.h> | ||
| 36 | |||
| 37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ | ||
| 38 | |||
| 39 | /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ | ||
| 40 | #include "defBF51x_base.h" | ||
| 41 | |||
| 42 | /* The following are the #defines needed by ADSP-BF518 that are not in the common header */ | ||
| 43 | /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ | ||
| 44 | |||
| 45 | #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ | ||
| 46 | #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ | ||
| 47 | #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ | ||
| 48 | #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ | ||
| 49 | #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ | ||
| 50 | #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ | ||
| 51 | #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ | ||
| 52 | #define EMAC_FLC 0xFFC0301C /* Flow Control Register */ | ||
| 53 | #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ | ||
| 54 | #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ | ||
| 55 | #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ | ||
| 56 | #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ | ||
| 57 | #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ | ||
| 58 | #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ | ||
| 59 | #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ | ||
| 60 | #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ | ||
| 61 | #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ | ||
| 62 | #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ | ||
| 63 | #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ | ||
| 64 | |||
| 65 | #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ | ||
| 66 | #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ | ||
| 67 | #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ | ||
| 68 | #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ | ||
| 69 | #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ | ||
| 70 | #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ | ||
| 71 | #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ | ||
| 72 | #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ | ||
| 73 | |||
| 74 | #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ | ||
| 75 | #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ | ||
| 76 | #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ | ||
| 77 | #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ | ||
| 78 | #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ | ||
| 79 | |||
| 80 | #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ | ||
| 81 | #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ | ||
| 82 | #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ | ||
| 83 | #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ | ||
| 84 | #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ | ||
| 85 | #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ | ||
| 86 | #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ | ||
| 87 | #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ | ||
| 88 | #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ | ||
| 89 | #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ | ||
| 90 | #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ | ||
| 91 | #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ | ||
| 92 | #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ | ||
| 93 | #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ | ||
| 94 | #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ | ||
| 95 | #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ | ||
| 96 | #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ | ||
| 97 | #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
| 98 | #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ | ||
| 99 | #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ | ||
| 100 | #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 101 | #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 102 | #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 103 | #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
| 104 | |||
| 105 | #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ | ||
| 106 | #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ | ||
| 107 | #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ | ||
| 108 | #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ | ||
| 109 | #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ | ||
| 110 | #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ | ||
| 111 | #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ | ||
| 112 | #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ | ||
| 113 | #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ | ||
| 114 | #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ | ||
| 115 | #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ | ||
| 116 | #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ | ||
| 117 | #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ | ||
| 118 | #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ | ||
| 119 | #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ | ||
| 120 | #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ | ||
| 121 | #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ | ||
| 122 | #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | ||
| 123 | #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 124 | #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 125 | #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 126 | #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
| 127 | #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ | ||
| 128 | |||
| 129 | /* Listing for IEEE-Supported Count Registers */ | ||
| 130 | |||
| 131 | #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ | ||
| 132 | #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ | ||
| 133 | #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ | ||
| 134 | #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ | ||
| 135 | #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ | ||
| 136 | #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ | ||
| 137 | #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ | ||
| 138 | #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ | ||
| 139 | #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ | ||
| 140 | #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ | ||
| 141 | #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ | ||
| 142 | #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ | ||
| 143 | #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ | ||
| 144 | #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ | ||
| 145 | #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ | ||
| 146 | #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ | ||
| 147 | #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ | ||
| 148 | #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ | ||
| 149 | #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ | ||
| 150 | #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ | ||
| 151 | #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 152 | #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 153 | #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 154 | #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ | ||
| 155 | |||
| 156 | #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ | ||
| 157 | #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ | ||
| 158 | #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ | ||
| 159 | #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ | ||
| 160 | #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ | ||
| 161 | #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ | ||
| 162 | #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ | ||
| 163 | #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ | ||
| 164 | #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ | ||
| 165 | #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ | ||
| 166 | #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ | ||
| 167 | #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ | ||
| 168 | #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ | ||
| 169 | #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ | ||
| 170 | #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ | ||
| 171 | #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ | ||
| 172 | #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ | ||
| 173 | #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ | ||
| 174 | #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ | ||
| 175 | #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ | ||
| 176 | #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ | ||
| 177 | #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ | ||
| 178 | #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ | ||
| 179 | |||
| 180 | /*********************************************************************************** | ||
| 181 | ** System MMR Register Bits And Macros | ||
| 182 | ** | ||
| 183 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
| 184 | ** Use these macros carefully, as any that do left shifts for field | ||
| 185 | ** depositing will result in the lower order bits being destroyed. Any | ||
| 186 | ** macro that shifts left to properly position the bit-field should be | ||
| 187 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
| 188 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
| 189 | ** the macro is used. | ||
| 190 | *************************************************************************************/ | ||
| 191 | |||
| 192 | /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ | ||
| 193 | |||
| 194 | /* EMAC_OPMODE Masks */ | ||
| 195 | |||
| 196 | #define RE 0x00000001 /* Receiver Enable */ | ||
| 197 | #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ | ||
| 198 | #define HU 0x00000010 /* Hash Filter Unicast Address */ | ||
| 199 | #define HM 0x00000020 /* Hash Filter Multicast Address */ | ||
| 200 | #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ | ||
| 201 | #define PR 0x00000080 /* Promiscuous Mode Enable */ | ||
| 202 | #define IFE 0x00000100 /* Inverse Filtering Enable */ | ||
| 203 | #define DBF 0x00000200 /* Disable Broadcast Frame Reception */ | ||
| 204 | #define PBF 0x00000400 /* Pass Bad Frames Enable */ | ||
| 205 | #define PSF 0x00000800 /* Pass Short Frames Enable */ | ||
| 206 | #define RAF 0x00001000 /* Receive-All Mode */ | ||
| 207 | #define TE 0x00010000 /* Transmitter Enable */ | ||
| 208 | #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ | ||
| 209 | #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ | ||
| 210 | #define DC 0x00080000 /* Deferral Check */ | ||
| 211 | #define BOLMT 0x00300000 /* Back-Off Limit */ | ||
| 212 | #define BOLMT_10 0x00000000 /* 10-bit range */ | ||
| 213 | #define BOLMT_8 0x00100000 /* 8-bit range */ | ||
| 214 | #define BOLMT_4 0x00200000 /* 4-bit range */ | ||
| 215 | #define BOLMT_1 0x00300000 /* 1-bit range */ | ||
| 216 | #define DRTY 0x00400000 /* Disable TX Retry On Collision */ | ||
| 217 | #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ | ||
| 218 | #define RMII 0x01000000 /* RMII/MII* Mode */ | ||
| 219 | #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ | ||
| 220 | #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ | ||
| 221 | #define LB 0x08000000 /* Internal Loopback Enable */ | ||
| 222 | #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ | ||
| 223 | |||
| 224 | /* EMAC_STAADD Masks */ | ||
| 225 | |||
| 226 | #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ | ||
| 227 | #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ | ||
| 228 | #define STADISPRE 0x00000004 /* Disable Preamble Generation */ | ||
| 229 | #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ | ||
| 230 | #define REGAD 0x000007C0 /* STA Register Address */ | ||
| 231 | #define PHYAD 0x0000F800 /* PHY Device Address */ | ||
| 232 | |||
| 233 | #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ | ||
| 234 | #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ | ||
| 235 | |||
| 236 | /* EMAC_STADAT Mask */ | ||
| 237 | |||
| 238 | #define STADATA 0x0000FFFF /* Station Management Data */ | ||
| 239 | |||
| 240 | /* EMAC_FLC Masks */ | ||
| 241 | |||
| 242 | #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ | ||
| 243 | #define FLCE 0x00000002 /* Flow Control Enable */ | ||
| 244 | #define PCF 0x00000004 /* Pass Control Frames */ | ||
| 245 | #define BKPRSEN 0x00000008 /* Enable Backpressure */ | ||
| 246 | #define FLCPAUSE 0xFFFF0000 /* Pause Time */ | ||
| 247 | |||
| 248 | #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ | ||
| 249 | |||
| 250 | /* EMAC_WKUP_CTL Masks */ | ||
| 251 | |||
| 252 | #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ | ||
| 253 | #define MPKE 0x00000002 /* Magic Packet Enable */ | ||
| 254 | #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ | ||
| 255 | #define GUWKE 0x00000008 /* Global Unicast Wake Enable */ | ||
| 256 | #define MPKS 0x00000020 /* Magic Packet Received Status */ | ||
| 257 | #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ | ||
| 258 | |||
| 259 | /* EMAC_WKUP_FFCMD Masks */ | ||
| 260 | |||
| 261 | #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ | ||
| 262 | #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ | ||
| 263 | #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ | ||
| 264 | #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ | ||
| 265 | #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ | ||
| 266 | #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ | ||
| 267 | #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ | ||
| 268 | #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ | ||
| 269 | |||
| 270 | /* EMAC_WKUP_FFOFF Masks */ | ||
| 271 | |||
| 272 | #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ | ||
| 273 | #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ | ||
| 274 | #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ | ||
| 275 | #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ | ||
| 276 | |||
| 277 | #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ | ||
| 278 | #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ | ||
| 279 | #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ | ||
| 280 | #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ | ||
| 281 | /* Set ALL Offsets */ | ||
| 282 | #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) | ||
| 283 | |||
| 284 | /* EMAC_WKUP_FFCRC0 Masks */ | ||
| 285 | |||
| 286 | #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ | ||
| 287 | #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ | ||
| 288 | |||
| 289 | #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ | ||
| 290 | #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ | ||
| 291 | |||
| 292 | /* EMAC_WKUP_FFCRC1 Masks */ | ||
| 293 | |||
| 294 | #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ | ||
| 295 | #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ | ||
| 296 | |||
| 297 | #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ | ||
| 298 | #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ | ||
| 299 | |||
| 300 | /* EMAC_SYSCTL Masks */ | ||
| 301 | |||
| 302 | #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ | ||
| 303 | #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ | ||
| 304 | #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ | ||
| 305 | #define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ | ||
| 306 | #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ | ||
| 307 | |||
| 308 | #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ | ||
| 309 | |||
| 310 | /* EMAC_SYSTAT Masks */ | ||
| 311 | |||
| 312 | #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ | ||
| 313 | #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ | ||
| 314 | #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ | ||
| 315 | #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ | ||
| 316 | #define WAKEDET 0x00000010 /* Wake-Up Detected Status */ | ||
| 317 | #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ | ||
| 318 | #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ | ||
| 319 | #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ | ||
| 320 | |||
| 321 | /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ | ||
| 322 | |||
| 323 | #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ | ||
| 324 | #define RX_COMP 0x00001000 /* RX Frame Complete */ | ||
| 325 | #define RX_OK 0x00002000 /* RX Frame Received With No Errors */ | ||
| 326 | #define RX_LONG 0x00004000 /* RX Frame Too Long Error */ | ||
| 327 | #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ | ||
| 328 | #define RX_CRC 0x00010000 /* RX Frame CRC Error */ | ||
| 329 | #define RX_LEN 0x00020000 /* RX Frame Length Error */ | ||
| 330 | #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ | ||
| 331 | #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ | ||
| 332 | #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ | ||
| 333 | #define RX_PHY 0x00200000 /* RX Frame PHY Error */ | ||
| 334 | #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ | ||
| 335 | #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ | ||
| 336 | #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ | ||
| 337 | #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ | ||
| 338 | #define RX_CTL 0x04000000 /* RX Control Frame Indicator */ | ||
| 339 | #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ | ||
| 340 | #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ | ||
| 341 | #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ | ||
| 342 | #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ | ||
| 343 | #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ | ||
| 344 | |||
| 345 | /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ | ||
| 346 | |||
| 347 | #define TX_COMP 0x00000001 /* TX Frame Complete */ | ||
| 348 | #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ | ||
| 349 | #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ | ||
| 350 | #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ | ||
| 351 | #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ | ||
| 352 | #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ | ||
| 353 | #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ | ||
| 354 | #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ | ||
| 355 | #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ | ||
| 356 | #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ | ||
| 357 | #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ | ||
| 358 | #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ | ||
| 359 | #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ | ||
| 360 | #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ | ||
| 361 | #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ | ||
| 362 | |||
| 363 | /* EMAC_MMC_CTL Masks */ | ||
| 364 | #define RSTC 0x00000001 /* Reset All Counters */ | ||
| 365 | #define CROLL 0x00000002 /* Counter Roll-Over Enable */ | ||
| 366 | #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ | ||
| 367 | #define MMCE 0x00000008 /* Enable MMC Counter Operation */ | ||
| 368 | |||
| 369 | /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ | ||
| 370 | #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ | ||
| 371 | #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ | ||
| 372 | #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ | ||
| 373 | #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ | ||
| 374 | #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ | ||
| 375 | #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ | ||
| 376 | #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ | ||
| 377 | #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ | ||
| 378 | #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ | ||
| 379 | #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ | ||
| 380 | #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ | ||
| 381 | #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ | ||
| 382 | #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ | ||
| 383 | #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ | ||
| 384 | #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ | ||
| 385 | #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ | ||
| 386 | #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ | ||
| 387 | #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ | ||
| 388 | #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ | ||
| 389 | #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ | ||
| 390 | #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ | ||
| 391 | #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ | ||
| 392 | #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ | ||
| 393 | #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ | ||
| 394 | |||
| 395 | /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ | ||
| 396 | |||
| 397 | #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ | ||
| 398 | #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ | ||
| 399 | #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ | ||
| 400 | #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ | ||
| 401 | #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ | ||
| 402 | #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ | ||
| 403 | #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ | ||
| 404 | #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ | ||
| 405 | #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ | ||
| 406 | #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ | ||
| 407 | #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ | ||
| 408 | #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ | ||
| 409 | #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ | ||
| 410 | #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ | ||
| 411 | #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ | ||
| 412 | #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ | ||
| 413 | #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ | ||
| 414 | #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ | ||
| 415 | #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ | ||
| 416 | #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ | ||
| 417 | #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ | ||
| 418 | #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ | ||
| 419 | #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ | ||
| 420 | |||
| 421 | /* SDH Registers */ | ||
| 422 | |||
| 423 | #define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ | ||
| 424 | #define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ | ||
| 425 | #define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ | ||
| 426 | #define SDH_COMMAND 0xFFC0390C /* SDH Command */ | ||
| 427 | #define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ | ||
| 428 | #define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ | ||
| 429 | #define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ | ||
| 430 | #define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ | ||
| 431 | #define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ | ||
| 432 | #define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ | ||
| 433 | #define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ | ||
| 434 | #define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ | ||
| 435 | #define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ | ||
| 436 | #define SDH_STATUS 0xFFC03934 /* SDH Status */ | ||
| 437 | #define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ | ||
| 438 | #define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ | ||
| 439 | #define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ | ||
| 440 | #define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ | ||
| 441 | #define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ | ||
| 442 | #define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ | ||
| 443 | #define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ | ||
| 444 | #define SDH_CFG 0xFFC039C8 /* SDH Configuration */ | ||
| 445 | #define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ | ||
| 446 | #define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ | ||
| 447 | #define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ | ||
| 448 | #define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ | ||
| 449 | #define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ | ||
| 450 | #define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ | ||
| 451 | #define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ | ||
| 452 | #define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ | ||
| 453 | #define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ | ||
| 454 | |||
| 455 | /* Removable Storage Interface Registers */ | ||
| 456 | |||
| 457 | #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ | ||
| 458 | #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ | ||
| 459 | #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ | ||
| 460 | #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ | ||
| 461 | #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ | ||
| 462 | #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ | ||
| 463 | #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ | ||
| 464 | #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ | ||
| 465 | #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ | ||
| 466 | #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ | ||
| 467 | #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ | ||
| 468 | #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ | ||
| 469 | #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ | ||
| 470 | #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ | ||
| 471 | #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ | ||
| 472 | #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ | ||
| 473 | #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ | ||
| 474 | #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ | ||
| 475 | #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ | ||
| 476 | #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ | ||
| 477 | #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ | ||
| 478 | #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ | ||
| 479 | #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ | ||
| 480 | #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ | ||
| 481 | #define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ | ||
| 482 | #define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ | ||
| 483 | #define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ | ||
| 484 | #define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ | ||
| 485 | #define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ | ||
| 486 | #define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ | ||
| 487 | #define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ | ||
| 488 | #define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ | ||
| 489 | |||
| 490 | /* PTP TSYNC Registers */ | ||
| 491 | |||
| 492 | #define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */ | ||
| 493 | #define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */ | ||
| 494 | #define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */ | ||
| 495 | #define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */ | ||
| 496 | #define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */ | ||
| 497 | #define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */ | ||
| 498 | #define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */ | ||
| 499 | #define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */ | ||
| 500 | #define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */ | ||
| 501 | #define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */ | ||
| 502 | #define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */ | ||
| 503 | #define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */ | ||
| 504 | #define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */ | ||
| 505 | #define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */ | ||
| 506 | #define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */ | ||
| 507 | #define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */ | ||
| 508 | #define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */ | ||
| 509 | #define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */ | ||
| 510 | #define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */ | ||
| 511 | #define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */ | ||
| 512 | #define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */ | ||
| 513 | #define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ | ||
| 514 | #define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ | ||
| 515 | |||
| 516 | /* ********************************************************** */ | ||
| 517 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | ||
| 518 | /* and MULTI BIT READ MACROS */ | ||
| 519 | /* ********************************************************** */ | ||
| 520 | |||
| 521 | /* Bit masks for SDH_COMMAND */ | ||
| 522 | |||
| 523 | #define CMD_IDX 0x3f /* Command Index */ | ||
| 524 | #define CMD_RSP 0x40 /* Response */ | ||
| 525 | #define CMD_L_RSP 0x80 /* Long Response */ | ||
| 526 | #define CMD_INT_E 0x100 /* Command Interrupt */ | ||
| 527 | #define CMD_PEND_E 0x200 /* Command Pending */ | ||
| 528 | #define CMD_E 0x400 /* Command Enable */ | ||
| 529 | |||
| 530 | /* Bit masks for SDH_PWR_CTL */ | ||
| 531 | |||
| 532 | #define PWR_ON 0x3 /* Power On */ | ||
| 533 | #if 0 | ||
| 534 | #define TBD 0x3c /* TBD */ | ||
| 535 | #endif | ||
| 536 | #define SD_CMD_OD 0x40 /* Open Drain Output */ | ||
| 537 | #define ROD_CTL 0x80 /* Rod Control */ | ||
| 538 | |||
| 539 | /* Bit masks for SDH_CLK_CTL */ | ||
| 540 | |||
| 541 | #define CLKDIV 0xff /* MC_CLK Divisor */ | ||
| 542 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ | ||
| 543 | #define PWR_SV_E 0x200 /* Power Save Enable */ | ||
| 544 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ | ||
| 545 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ | ||
| 546 | |||
| 547 | /* Bit masks for SDH_RESP_CMD */ | ||
| 548 | |||
| 549 | #define RESP_CMD 0x3f /* Response Command */ | ||
| 550 | |||
| 551 | /* Bit masks for SDH_DATA_CTL */ | ||
| 552 | |||
| 553 | #define DTX_E 0x1 /* Data Transfer Enable */ | ||
| 554 | #define DTX_DIR 0x2 /* Data Transfer Direction */ | ||
| 555 | #define DTX_MODE 0x4 /* Data Transfer Mode */ | ||
| 556 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ | ||
| 557 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | ||
| 558 | |||
| 559 | /* Bit masks for SDH_STATUS */ | ||
| 560 | |||
| 561 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ | ||
| 562 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ | ||
| 563 | #define CMD_TIME_OUT 0x4 /* CMD Time Out */ | ||
| 564 | #define DAT_TIME_OUT 0x8 /* Data Time Out */ | ||
| 565 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ | ||
| 566 | #define RX_OVERRUN 0x20 /* Receive Overrun */ | ||
| 567 | #define CMD_RESP_END 0x40 /* CMD Response End */ | ||
| 568 | #define CMD_SENT 0x80 /* CMD Sent */ | ||
| 569 | #define DAT_END 0x100 /* Data End */ | ||
| 570 | #define START_BIT_ERR 0x200 /* Start Bit Error */ | ||
| 571 | #define DAT_BLK_END 0x400 /* Data Block End */ | ||
| 572 | #define CMD_ACT 0x800 /* CMD Active */ | ||
| 573 | #define TX_ACT 0x1000 /* Transmit Active */ | ||
| 574 | #define RX_ACT 0x2000 /* Receive Active */ | ||
| 575 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ | ||
| 576 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ | ||
| 577 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ | ||
| 578 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ | ||
| 579 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ | ||
| 580 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ | ||
| 581 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ | ||
| 582 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ | ||
| 583 | |||
| 584 | /* Bit masks for SDH_STATUS_CLR */ | ||
| 585 | |||
| 586 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ | ||
| 587 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ | ||
| 588 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ | ||
| 589 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ | ||
| 590 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ | ||
| 591 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ | ||
| 592 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ | ||
| 593 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ | ||
| 594 | #define DAT_END_STAT 0x100 /* Data End Status */ | ||
| 595 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ | ||
| 596 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ | ||
| 597 | |||
| 598 | /* Bit masks for SDH_MASK0 */ | ||
| 599 | |||
| 600 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ | ||
| 601 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ | ||
| 602 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ | ||
| 603 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ | ||
| 604 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ | ||
| 605 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ | ||
| 606 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ | ||
| 607 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ | ||
| 608 | #define DAT_END_MASK 0x100 /* Data End Mask */ | ||
| 609 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ | ||
| 610 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ | ||
| 611 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ | ||
| 612 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ | ||
| 613 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ | ||
| 614 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ | ||
| 615 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ | ||
| 616 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ | ||
| 617 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ | ||
| 618 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ | ||
| 619 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ | ||
| 620 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ | ||
| 621 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ | ||
| 622 | |||
| 623 | /* Bit masks for SDH_FIFO_CNT */ | ||
| 624 | |||
| 625 | #define FIFO_COUNT 0x7fff /* FIFO Count */ | ||
| 626 | |||
| 627 | /* Bit masks for SDH_E_STATUS */ | ||
| 628 | |||
| 629 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ | ||
| 630 | #define SD_CARD_DET 0x10 /* SD Card Detect */ | ||
| 631 | |||
| 632 | /* Bit masks for SDH_E_MASK */ | ||
| 633 | |||
| 634 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ | ||
| 635 | #define SCD_MSK 0x40 /* Mask Card Detect */ | ||
| 636 | |||
| 637 | /* Bit masks for SDH_CFG */ | ||
| 638 | |||
| 639 | #define CLKS_EN 0x1 /* Clocks Enable */ | ||
| 640 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ | ||
| 641 | #define MWE 0x8 /* Moving Window Enable */ | ||
| 642 | #define SD_RST 0x10 /* SDMMC Reset */ | ||
| 643 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ | ||
| 644 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ | ||
| 645 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ | ||
| 646 | |||
| 647 | /* Bit masks for SDH_RD_WAIT_EN */ | ||
| 648 | |||
| 649 | #define RWR 0x1 /* Read Wait Request */ | ||
| 650 | |||
| 651 | #endif /* _DEF_BF518_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h new file mode 100644 index 000000000000..1bec8d1c2a73 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h | |||
| @@ -0,0 +1,1940 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf518/defBF51x_base.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _DEF_BF51X_H | ||
| 32 | #define _DEF_BF51X_H | ||
| 33 | |||
| 34 | |||
| 35 | /* ************************************************************** */ | ||
| 36 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */ | ||
| 37 | /* ************************************************************** */ | ||
| 38 | |||
| 39 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | ||
| 40 | #define PLL_CTL 0xFFC00000 /* PLL Control Register */ | ||
| 41 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ | ||
| 42 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ | ||
| 43 | #define PLL_STAT 0xFFC0000C /* PLL Status Register */ | ||
| 44 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ | ||
| 45 | #define CHIPID 0xFFC00014 /* Device ID Register */ | ||
| 46 | |||
| 47 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
| 48 | #define SWRST 0xFFC00100 /* Software Reset Register */ | ||
| 49 | #define SYSCR 0xFFC00104 /* System Configuration Register */ | ||
| 50 | #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ | ||
| 51 | |||
| 52 | #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ | ||
| 53 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | ||
| 54 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | ||
| 55 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | ||
| 56 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ | ||
| 57 | #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ | ||
| 58 | #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ | ||
| 59 | |||
| 60 | /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */ | ||
| 61 | #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ | ||
| 62 | #define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ | ||
| 63 | #define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ | ||
| 64 | #define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ | ||
| 65 | #define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ | ||
| 66 | #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ | ||
| 67 | #define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ | ||
| 68 | |||
| 69 | |||
| 70 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
| 71 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ | ||
| 72 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ | ||
| 73 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ | ||
| 74 | |||
| 75 | |||
| 76 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
| 77 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ | ||
| 78 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ | ||
| 79 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ | ||
| 80 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ | ||
| 81 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ | ||
| 82 | #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ | ||
| 83 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ | ||
| 84 | |||
| 85 | |||
| 86 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 87 | #define UART0_THR 0xFFC00400 /* Transmit Holding register */ | ||
| 88 | #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ | ||
| 89 | #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | ||
| 90 | #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ | ||
| 91 | #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | ||
| 92 | #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ | ||
| 93 | #define UART0_LCR 0xFFC0040C /* Line Control Register */ | ||
| 94 | #define UART0_MCR 0xFFC00410 /* Modem Control Register */ | ||
| 95 | #define UART0_LSR 0xFFC00414 /* Line Status Register */ | ||
| 96 | #define UART0_MSR 0xFFC00418 /* Modem Status Register */ | ||
| 97 | #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ | ||
| 98 | #define UART0_GCTL 0xFFC00424 /* Global Control Register */ | ||
| 99 | |||
| 100 | /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ | ||
| 101 | #define SPI0_REGBASE 0xFFC00500 | ||
| 102 | #define SPI0_CTL 0xFFC00500 /* SPI Control Register */ | ||
| 103 | #define SPI0_FLG 0xFFC00504 /* SPI Flag register */ | ||
| 104 | #define SPI0_STAT 0xFFC00508 /* SPI Status register */ | ||
| 105 | #define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ | ||
| 106 | #define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ | ||
| 107 | #define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */ | ||
| 108 | #define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ | ||
| 109 | |||
| 110 | /* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */ | ||
| 111 | #define SPI1_REGBASE 0xFFC03400 | ||
| 112 | #define SPI1_CTL 0xFFC03400 /* SPI Control Register */ | ||
| 113 | #define SPI1_FLG 0xFFC03404 /* SPI Flag register */ | ||
| 114 | #define SPI1_STAT 0xFFC03408 /* SPI Status register */ | ||
| 115 | #define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */ | ||
| 116 | #define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */ | ||
| 117 | #define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */ | ||
| 118 | #define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */ | ||
| 119 | |||
| 120 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
| 121 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ | ||
| 122 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ | ||
| 123 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ | ||
| 124 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ | ||
| 125 | |||
| 126 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ | ||
| 127 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ | ||
| 128 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ | ||
| 129 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ | ||
| 130 | |||
| 131 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ | ||
| 132 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ | ||
| 133 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ | ||
| 134 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ | ||
| 135 | |||
| 136 | #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ | ||
| 137 | #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ | ||
| 138 | #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ | ||
| 139 | #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ | ||
| 140 | |||
| 141 | #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ | ||
| 142 | #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ | ||
| 143 | #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ | ||
| 144 | #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ | ||
| 145 | |||
| 146 | #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ | ||
| 147 | #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ | ||
| 148 | #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ | ||
| 149 | #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ | ||
| 150 | |||
| 151 | #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ | ||
| 152 | #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ | ||
| 153 | #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ | ||
| 154 | #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ | ||
| 155 | |||
| 156 | #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ | ||
| 157 | #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ | ||
| 158 | #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ | ||
| 159 | #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ | ||
| 160 | |||
| 161 | #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ | ||
| 162 | #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ | ||
| 163 | #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ | ||
| 164 | |||
| 165 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ | ||
| 166 | #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ | ||
| 167 | #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ | ||
| 168 | #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ | ||
| 169 | #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ | ||
| 170 | #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ | ||
| 171 | #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ | ||
| 172 | #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ | ||
| 173 | #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ | ||
| 174 | #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ | ||
| 175 | #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ | ||
| 176 | #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ | ||
| 177 | #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ | ||
| 178 | #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ | ||
| 179 | #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ | ||
| 180 | #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ | ||
| 181 | #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ | ||
| 182 | #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ | ||
| 183 | |||
| 184 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 185 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 186 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 187 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | ||
| 188 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | ||
| 189 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | ||
| 190 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | ||
| 191 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 192 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 193 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | ||
| 194 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | ||
| 195 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | ||
| 196 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | ||
| 197 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | ||
| 198 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | ||
| 199 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | ||
| 200 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | ||
| 201 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | ||
| 202 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | ||
| 203 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | ||
| 204 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | ||
| 205 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | ||
| 206 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | ||
| 207 | |||
| 208 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 209 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 210 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 211 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | ||
| 212 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | ||
| 213 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | ||
| 214 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | ||
| 215 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 216 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 217 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | ||
| 218 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | ||
| 219 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | ||
| 220 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | ||
| 221 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | ||
| 222 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | ||
| 223 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | ||
| 224 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | ||
| 225 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | ||
| 226 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | ||
| 227 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | ||
| 228 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | ||
| 229 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | ||
| 230 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | ||
| 231 | |||
| 232 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 233 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | ||
| 234 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | ||
| 235 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | ||
| 236 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | ||
| 237 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | ||
| 238 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | ||
| 239 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | ||
| 240 | |||
| 241 | /* DMA Traffic Control Registers */ | ||
| 242 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
| 243 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
| 244 | |||
| 245 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
| 246 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
| 247 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
| 248 | |||
| 249 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ | ||
| 250 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | ||
| 251 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ | ||
| 252 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | ||
| 253 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ | ||
| 254 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ | ||
| 255 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ | ||
| 256 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ | ||
| 257 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ | ||
| 258 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ | ||
| 259 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ | ||
| 260 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ | ||
| 261 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ | ||
| 262 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ | ||
| 263 | |||
| 264 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ | ||
| 265 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ | ||
| 266 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ | ||
| 267 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ | ||
| 268 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ | ||
| 269 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ | ||
| 270 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ | ||
| 271 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ | ||
| 272 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ | ||
| 273 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ | ||
| 274 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ | ||
| 275 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ | ||
| 276 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ | ||
| 277 | |||
| 278 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ | ||
| 279 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ | ||
| 280 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ | ||
| 281 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ | ||
| 282 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ | ||
| 283 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ | ||
| 284 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ | ||
| 285 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ | ||
| 286 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ | ||
| 287 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ | ||
| 288 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ | ||
| 289 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ | ||
| 290 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ | ||
| 291 | |||
| 292 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ | ||
| 293 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ | ||
| 294 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ | ||
| 295 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ | ||
| 296 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ | ||
| 297 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ | ||
| 298 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ | ||
| 299 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ | ||
| 300 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ | ||
| 301 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ | ||
| 302 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ | ||
| 303 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ | ||
| 304 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ | ||
| 305 | |||
| 306 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ | ||
| 307 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ | ||
| 308 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ | ||
| 309 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ | ||
| 310 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ | ||
| 311 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ | ||
| 312 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ | ||
| 313 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ | ||
| 314 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ | ||
| 315 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ | ||
| 316 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ | ||
| 317 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ | ||
| 318 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ | ||
| 319 | |||
| 320 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ | ||
| 321 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ | ||
| 322 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ | ||
| 323 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ | ||
| 324 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ | ||
| 325 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ | ||
| 326 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ | ||
| 327 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ | ||
| 328 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ | ||
| 329 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ | ||
| 330 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ | ||
| 331 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ | ||
| 332 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ | ||
| 333 | |||
| 334 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ | ||
| 335 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ | ||
| 336 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ | ||
| 337 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ | ||
| 338 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ | ||
| 339 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ | ||
| 340 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ | ||
| 341 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ | ||
| 342 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ | ||
| 343 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ | ||
| 344 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ | ||
| 345 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ | ||
| 346 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ | ||
| 347 | |||
| 348 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ | ||
| 349 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ | ||
| 350 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ | ||
| 351 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ | ||
| 352 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ | ||
| 353 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ | ||
| 354 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ | ||
| 355 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ | ||
| 356 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ | ||
| 357 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ | ||
| 358 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ | ||
| 359 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ | ||
| 360 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ | ||
| 361 | |||
| 362 | #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ | ||
| 363 | #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ | ||
| 364 | #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ | ||
| 365 | #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ | ||
| 366 | #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ | ||
| 367 | #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ | ||
| 368 | #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ | ||
| 369 | #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ | ||
| 370 | #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ | ||
| 371 | #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ | ||
| 372 | #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ | ||
| 373 | #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ | ||
| 374 | #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ | ||
| 375 | |||
| 376 | #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ | ||
| 377 | #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ | ||
| 378 | #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ | ||
| 379 | #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ | ||
| 380 | #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ | ||
| 381 | #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ | ||
| 382 | #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ | ||
| 383 | #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ | ||
| 384 | #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ | ||
| 385 | #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ | ||
| 386 | #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ | ||
| 387 | #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ | ||
| 388 | #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ | ||
| 389 | |||
| 390 | #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ | ||
| 391 | #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ | ||
| 392 | #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ | ||
| 393 | #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ | ||
| 394 | #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ | ||
| 395 | #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ | ||
| 396 | #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ | ||
| 397 | #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ | ||
| 398 | #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ | ||
| 399 | #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ | ||
| 400 | #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ | ||
| 401 | #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ | ||
| 402 | #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ | ||
| 403 | |||
| 404 | #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ | ||
| 405 | #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ | ||
| 406 | #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ | ||
| 407 | #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ | ||
| 408 | #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ | ||
| 409 | #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ | ||
| 410 | #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ | ||
| 411 | #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ | ||
| 412 | #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ | ||
| 413 | #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ | ||
| 414 | #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ | ||
| 415 | #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ | ||
| 416 | #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ | ||
| 417 | |||
| 418 | #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ | ||
| 419 | #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ | ||
| 420 | #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ | ||
| 421 | #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ | ||
| 422 | #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ | ||
| 423 | #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ | ||
| 424 | #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ | ||
| 425 | #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ | ||
| 426 | #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ | ||
| 427 | #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ | ||
| 428 | #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ | ||
| 429 | #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ | ||
| 430 | #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ | ||
| 431 | |||
| 432 | #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ | ||
| 433 | #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ | ||
| 434 | #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ | ||
| 435 | #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ | ||
| 436 | #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ | ||
| 437 | #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ | ||
| 438 | #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ | ||
| 439 | #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ | ||
| 440 | #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ | ||
| 441 | #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ | ||
| 442 | #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ | ||
| 443 | #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ | ||
| 444 | #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ | ||
| 445 | |||
| 446 | #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ | ||
| 447 | #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ | ||
| 448 | #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ | ||
| 449 | #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ | ||
| 450 | #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ | ||
| 451 | #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ | ||
| 452 | #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ | ||
| 453 | #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ | ||
| 454 | #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ | ||
| 455 | #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ | ||
| 456 | #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ | ||
| 457 | #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ | ||
| 458 | #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ | ||
| 459 | |||
| 460 | #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ | ||
| 461 | #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ | ||
| 462 | #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ | ||
| 463 | #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ | ||
| 464 | #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ | ||
| 465 | #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ | ||
| 466 | #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ | ||
| 467 | #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ | ||
| 468 | #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ | ||
| 469 | #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ | ||
| 470 | #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ | ||
| 471 | #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ | ||
| 472 | #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ | ||
| 473 | |||
| 474 | |||
| 475 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ | ||
| 476 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | ||
| 477 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ | ||
| 478 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ | ||
| 479 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ | ||
| 480 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ | ||
| 481 | |||
| 482 | |||
| 483 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ | ||
| 484 | #define TWI0_REGBASE 0xFFC01400 | ||
| 485 | #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | ||
| 486 | #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ | ||
| 487 | #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ | ||
| 488 | #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | ||
| 489 | #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | ||
| 490 | #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ | ||
| 491 | #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | ||
| 492 | #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | ||
| 493 | #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ | ||
| 494 | #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ | ||
| 495 | #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ | ||
| 496 | #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | ||
| 497 | #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | ||
| 498 | #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | ||
| 499 | #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | ||
| 500 | #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | ||
| 501 | |||
| 502 | |||
| 503 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ | ||
| 504 | #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ | ||
| 505 | #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ | ||
| 506 | #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ | ||
| 507 | #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ | ||
| 508 | #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ | ||
| 509 | #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ | ||
| 510 | #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ | ||
| 511 | #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ | ||
| 512 | #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ | ||
| 513 | #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ | ||
| 514 | #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ | ||
| 515 | #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ | ||
| 516 | #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ | ||
| 517 | #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ | ||
| 518 | #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ | ||
| 519 | #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ | ||
| 520 | #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ | ||
| 521 | |||
| 522 | |||
| 523 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ | ||
| 524 | #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ | ||
| 525 | #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ | ||
| 526 | #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ | ||
| 527 | #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ | ||
| 528 | #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ | ||
| 529 | #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ | ||
| 530 | #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ | ||
| 531 | #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ | ||
| 532 | #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ | ||
| 533 | #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ | ||
| 534 | #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ | ||
| 535 | #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ | ||
| 536 | #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ | ||
| 537 | #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ | ||
| 538 | #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ | ||
| 539 | #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ | ||
| 540 | #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ | ||
| 541 | |||
| 542 | |||
| 543 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
| 544 | #define UART1_THR 0xFFC02000 /* Transmit Holding register */ | ||
| 545 | #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ | ||
| 546 | #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ | ||
| 547 | #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ | ||
| 548 | #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ | ||
| 549 | #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ | ||
| 550 | #define UART1_LCR 0xFFC0200C /* Line Control Register */ | ||
| 551 | #define UART1_MCR 0xFFC02010 /* Modem Control Register */ | ||
| 552 | #define UART1_LSR 0xFFC02014 /* Line Status Register */ | ||
| 553 | #define UART1_MSR 0xFFC02018 /* Modem Status Register */ | ||
| 554 | #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ | ||
| 555 | #define UART1_GCTL 0xFFC02024 /* Global Control Register */ | ||
| 556 | |||
| 557 | |||
| 558 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ | ||
| 559 | #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ | ||
| 560 | #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ | ||
| 561 | #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ | ||
| 562 | #define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ | ||
| 563 | |||
| 564 | |||
| 565 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ | ||
| 566 | #define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ | ||
| 567 | #define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ | ||
| 568 | #define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ | ||
| 569 | #define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ | ||
| 570 | #define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ | ||
| 571 | #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ | ||
| 572 | #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ | ||
| 573 | |||
| 574 | #define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ | ||
| 575 | #define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ | ||
| 576 | #define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ | ||
| 577 | #define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ | ||
| 578 | #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ | ||
| 579 | #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ | ||
| 580 | #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ | ||
| 581 | |||
| 582 | |||
| 583 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ | ||
| 584 | #define PORTF_MUX 0xFFC03210 /* Port F mux control */ | ||
| 585 | #define PORTG_MUX 0xFFC03214 /* Port G mux control */ | ||
| 586 | #define PORTH_MUX 0xFFC03218 /* Port H mux control */ | ||
| 587 | #define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ | ||
| 588 | #define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ | ||
| 589 | #define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ | ||
| 590 | #define PORTF_SLEW 0xFFC03230 /* Port F slew control */ | ||
| 591 | #define PORTG_SLEW 0xFFC03234 /* Port G slew control */ | ||
| 592 | #define PORTH_SLEW 0xFFC03238 /* Port H slew control */ | ||
| 593 | #define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */ | ||
| 594 | #define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */ | ||
| 595 | #define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */ | ||
| 596 | #define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */ | ||
| 597 | #define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */ | ||
| 598 | #define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */ | ||
| 599 | |||
| 600 | |||
| 601 | /*********************************************************************************** | ||
| 602 | ** System MMR Register Bits And Macros | ||
| 603 | ** | ||
| 604 | ** Disclaimer: All macros are intended to make C and Assembly code more readable. | ||
| 605 | ** Use these macros carefully, as any that do left shifts for field | ||
| 606 | ** depositing will result in the lower order bits being destroyed. Any | ||
| 607 | ** macro that shifts left to properly position the bit-field should be | ||
| 608 | ** used as part of an OR to initialize a register and NOT as a dynamic | ||
| 609 | ** modifier UNLESS the lower order bits are saved and ORed back in when | ||
| 610 | ** the macro is used. | ||
| 611 | *************************************************************************************/ | ||
| 612 | /* | ||
| 613 | ** ********************* PLL AND RESET MASKS ****************************************/ | ||
| 614 | /* PLL_CTL Masks */ | ||
| 615 | #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ | ||
| 616 | #define PLL_OFF 0x0002 /* PLL Not Powered */ | ||
| 617 | #define STOPCK 0x0008 /* Core Clock Off */ | ||
| 618 | #define PDWN 0x0020 /* Enter Deep Sleep Mode */ | ||
| 619 | #define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ | ||
| 620 | #define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ | ||
| 621 | #define BYPASS 0x0100 /* Bypass the PLL */ | ||
| 622 | #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ | ||
| 623 | /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ | ||
| 624 | #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ | ||
| 625 | |||
| 626 | /* PLL_DIV Masks */ | ||
| 627 | #define SSEL 0x000F /* System Select */ | ||
| 628 | #define CSEL 0x0030 /* Core Select */ | ||
| 629 | #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ | ||
| 630 | #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ | ||
| 631 | #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ | ||
| 632 | #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ | ||
| 633 | /* PLL_DIV Macros */ | ||
| 634 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | ||
| 635 | |||
| 636 | /* VR_CTL Masks */ | ||
| 637 | #define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ | ||
| 638 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | ||
| 639 | |||
| 640 | #define VLEV 0x00F0 /* Internal Voltage Level */ | ||
| 641 | #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ | ||
| 642 | #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ | ||
| 643 | #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ | ||
| 644 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ | ||
| 645 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ | ||
| 646 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ | ||
| 647 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ | ||
| 648 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ | ||
| 649 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ | ||
| 650 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ | ||
| 651 | |||
| 652 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | ||
| 653 | #define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ | ||
| 654 | #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ | ||
| 655 | #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ | ||
| 656 | #define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ | ||
| 657 | #define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ | ||
| 658 | |||
| 659 | /* PLL_STAT Masks */ | ||
| 660 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | ||
| 661 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | ||
| 662 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | ||
| 663 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | ||
| 664 | |||
| 665 | /* CHIPID Masks */ | ||
| 666 | #define CHIPID_VERSION 0xF0000000 | ||
| 667 | #define CHIPID_FAMILY 0x0FFFF000 | ||
| 668 | #define CHIPID_MANUFACTURE 0x00000FFE | ||
| 669 | |||
| 670 | /* SWRST Masks */ | ||
| 671 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ | ||
| 672 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ | ||
| 673 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ | ||
| 674 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ | ||
| 675 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ | ||
| 676 | |||
| 677 | /* SYSCR Masks */ | ||
| 678 | #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ | ||
| 679 | #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ | ||
| 680 | |||
| 681 | |||
| 682 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ | ||
| 683 | /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ | ||
| 684 | |||
| 685 | #if 0 | ||
| 686 | #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ | ||
| 687 | |||
| 688 | #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ | ||
| 689 | #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ | ||
| 690 | #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ | ||
| 691 | #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ | ||
| 692 | #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ | ||
| 693 | #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ | ||
| 694 | #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ | ||
| 695 | |||
| 696 | #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ | ||
| 697 | #define IRQ_TWI 0x00000200 /* TWI Interrupt */ | ||
| 698 | #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ | ||
| 699 | #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ | ||
| 700 | #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ | ||
| 701 | #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ | ||
| 702 | #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ | ||
| 703 | #define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */ | ||
| 704 | |||
| 705 | #define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */ | ||
| 706 | #define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */ | ||
| 707 | #define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */ | ||
| 708 | #define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */ | ||
| 709 | #define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */ | ||
| 710 | #define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */ | ||
| 711 | #define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */ | ||
| 712 | #define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */ | ||
| 713 | #define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */ | ||
| 714 | #define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */ | ||
| 715 | |||
| 716 | #define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */ | ||
| 717 | #define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */ | ||
| 718 | #define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */ | ||
| 719 | #define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */ | ||
| 720 | #define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */ | ||
| 721 | #define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */ | ||
| 722 | #define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */ | ||
| 723 | #define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */ | ||
| 724 | #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ | ||
| 725 | #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ | ||
| 726 | #define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ | ||
| 727 | #endif | ||
| 728 | |||
| 729 | /* SIC_IAR0 Macros */ | ||
| 730 | #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ | ||
| 731 | #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ | ||
| 732 | #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ | ||
| 733 | #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ | ||
| 734 | #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ | ||
| 735 | #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ | ||
| 736 | #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ | ||
| 737 | #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ | ||
| 738 | |||
| 739 | /* SIC_IAR1 Macros */ | ||
| 740 | #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ | ||
| 741 | #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ | ||
| 742 | #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ | ||
| 743 | #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ | ||
| 744 | #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ | ||
| 745 | #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ | ||
| 746 | #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ | ||
| 747 | #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ | ||
| 748 | |||
| 749 | /* SIC_IAR2 Macros */ | ||
| 750 | #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ | ||
| 751 | #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ | ||
| 752 | #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ | ||
| 753 | #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ | ||
| 754 | #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ | ||
| 755 | #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ | ||
| 756 | #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ | ||
| 757 | #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ | ||
| 758 | |||
| 759 | /* SIC_IAR3 Macros */ | ||
| 760 | #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ | ||
| 761 | #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ | ||
| 762 | #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ | ||
| 763 | #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ | ||
| 764 | #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ | ||
| 765 | #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ | ||
| 766 | #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ | ||
| 767 | #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ | ||
| 768 | |||
| 769 | |||
| 770 | /* SIC_IMASK Masks */ | ||
| 771 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | ||
| 772 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | ||
| 773 | #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ | ||
| 774 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ | ||
| 775 | |||
| 776 | /* SIC_IWR Masks */ | ||
| 777 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | ||
| 778 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | ||
| 779 | #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ | ||
| 780 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ | ||
| 781 | |||
| 782 | |||
| 783 | /* ********* WATCHDOG TIMER MASKS ******************** */ | ||
| 784 | |||
| 785 | /* Watchdog Timer WDOG_CTL Register Masks */ | ||
| 786 | |||
| 787 | #define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ | ||
| 788 | #define WDEV_RESET 0x0000 /* generate reset event on roll over */ | ||
| 789 | #define WDEV_NMI 0x0002 /* generate NMI event on roll over */ | ||
| 790 | #define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ | ||
| 791 | #define WDEV_NONE 0x0006 /* no event on roll over */ | ||
| 792 | #define WDEN 0x0FF0 /* enable watchdog */ | ||
| 793 | #define WDDIS 0x0AD0 /* disable watchdog */ | ||
| 794 | #define WDRO 0x8000 /* watchdog rolled over latch */ | ||
| 795 | |||
| 796 | /* depreciated WDOG_CTL Register Masks for legacy code */ | ||
| 797 | |||
| 798 | |||
| 799 | #define ICTL WDEV | ||
| 800 | #define ENABLE_RESET WDEV_RESET | ||
| 801 | #define WDOG_RESET WDEV_RESET | ||
| 802 | #define ENABLE_NMI WDEV_NMI | ||
| 803 | #define WDOG_NMI WDEV_NMI | ||
| 804 | #define ENABLE_GPI WDEV_GPI | ||
| 805 | #define WDOG_GPI WDEV_GPI | ||
| 806 | #define DISABLE_EVT WDEV_NONE | ||
| 807 | #define WDOG_NONE WDEV_NONE | ||
| 808 | |||
| 809 | #define TMR_EN WDEN | ||
| 810 | #define TMR_DIS WDDIS | ||
| 811 | #define TRO WDRO | ||
| 812 | #define ICTL_P0 0x01 | ||
| 813 | #define ICTL_P1 0x02 | ||
| 814 | #define TRO_P 0x0F | ||
| 815 | |||
| 816 | |||
| 817 | |||
| 818 | /* *************** REAL TIME CLOCK MASKS **************************/ | ||
| 819 | /* RTC_STAT and RTC_ALARM Masks */ | ||
| 820 | #define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ | ||
| 821 | #define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ | ||
| 822 | #define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ | ||
| 823 | #define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ | ||
| 824 | |||
| 825 | /* RTC_ALARM Macro z=day y=hr x=min w=sec */ | ||
| 826 | #define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F)) | ||
| 827 | |||
| 828 | /* RTC_ICTL and RTC_ISTAT Masks */ | ||
| 829 | #define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ | ||
| 830 | #define ALARM 0x0002 /* Alarm Interrupt Enable */ | ||
| 831 | #define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ | ||
| 832 | #define MINUTE 0x0008 /* Minutes Interrupt Enable */ | ||
| 833 | #define HOUR 0x0010 /* Hours Interrupt Enable */ | ||
| 834 | #define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ | ||
| 835 | #define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ | ||
| 836 | #define WRITE_PENDING 0x4000 /* Write Pending Status */ | ||
| 837 | #define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ | ||
| 838 | |||
| 839 | /* RTC_FAST / RTC_PREN Mask */ | ||
| 840 | #define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ | ||
| 841 | |||
| 842 | |||
| 843 | /* ************** UART CONTROLLER MASKS *************************/ | ||
| 844 | /* UARTx_LCR Masks */ | ||
| 845 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ | ||
| 846 | #define STB 0x04 /* Stop Bits */ | ||
| 847 | #define PEN 0x08 /* Parity Enable */ | ||
| 848 | #define EPS 0x10 /* Even Parity Select */ | ||
| 849 | #define STP 0x20 /* Stick Parity */ | ||
| 850 | #define SB 0x40 /* Set Break */ | ||
| 851 | #define DLAB 0x80 /* Divisor Latch Access */ | ||
| 852 | |||
| 853 | /* UARTx_MCR Mask */ | ||
| 854 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ | ||
| 855 | #define LOOP_ENA_P 0x04 | ||
| 856 | |||
| 857 | /* UARTx_LSR Masks */ | ||
| 858 | #define DR 0x01 /* Data Ready */ | ||
| 859 | #define OE 0x02 /* Overrun Error */ | ||
| 860 | #define PE 0x04 /* Parity Error */ | ||
| 861 | #define FE 0x08 /* Framing Error */ | ||
| 862 | #define BI 0x10 /* Break Interrupt */ | ||
| 863 | #define THRE 0x20 /* THR Empty */ | ||
| 864 | #define TEMT 0x40 /* TSR and UART_THR Empty */ | ||
| 865 | |||
| 866 | /* UARTx_IER Masks */ | ||
| 867 | #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ | ||
| 868 | #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ | ||
| 869 | #define ELSI 0x04 /* Enable RX Status Interrupt */ | ||
| 870 | |||
| 871 | /* UARTx_IIR Masks */ | ||
| 872 | #define NINT 0x01 /* Pending Interrupt */ | ||
| 873 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | ||
| 874 | #define IIR_RX_READY 0x04 /* Receive data ready */ | ||
| 875 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | ||
| 876 | #define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ | ||
| 877 | |||
| 878 | /* UARTx_GCTL Masks */ | ||
| 879 | #define UCEN 0x01 /* Enable UARTx Clocks */ | ||
| 880 | #define IREN 0x02 /* Enable IrDA Mode */ | ||
| 881 | #define TPOLC 0x04 /* IrDA TX Polarity Change */ | ||
| 882 | #define RPOLC 0x08 /* IrDA RX Polarity Change */ | ||
| 883 | #define FPE 0x10 /* Force Parity Error On Transmit */ | ||
| 884 | #define FFE 0x20 /* Force Framing Error On Transmit */ | ||
| 885 | |||
| 886 | |||
| 887 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ | ||
| 888 | /* SPI_CTL Masks */ | ||
| 889 | #define TIMOD 0x0003 /* Transfer Initiate Mode */ | ||
| 890 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ | ||
| 891 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | ||
| 892 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | ||
| 893 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | ||
| 894 | #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ | ||
| 895 | #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ | ||
| 896 | #define PSSE 0x0010 /* Slave-Select Input Enable */ | ||
| 897 | #define EMISO 0x0020 /* Enable MISO As Output */ | ||
| 898 | #define SIZE 0x0100 /* Size of Words (16/8* Bits) */ | ||
| 899 | #define LSBF 0x0200 /* LSB First */ | ||
| 900 | #define CPHA 0x0400 /* Clock Phase */ | ||
| 901 | #define CPOL 0x0800 /* Clock Polarity */ | ||
| 902 | #define MSTR 0x1000 /* Master/Slave* */ | ||
| 903 | #define WOM 0x2000 /* Write Open Drain Master */ | ||
| 904 | #define SPE 0x4000 /* SPI Enable */ | ||
| 905 | |||
| 906 | /* SPI_FLG Masks */ | ||
| 907 | #define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ | ||
| 908 | #define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ | ||
| 909 | #define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ | ||
| 910 | #define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ | ||
| 911 | #define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ | ||
| 912 | #define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ | ||
| 913 | #define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ | ||
| 914 | #define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ | ||
| 915 | #define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ | ||
| 916 | #define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ | ||
| 917 | #define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ | ||
| 918 | #define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ | ||
| 919 | #define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ | ||
| 920 | #define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ | ||
| 921 | |||
| 922 | /* SPI_STAT Masks */ | ||
| 923 | #define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ | ||
| 924 | #define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ | ||
| 925 | #define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ | ||
| 926 | #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ | ||
| 927 | #define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ | ||
| 928 | #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ | ||
| 929 | #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ | ||
| 930 | |||
| 931 | |||
| 932 | /* **************** GENERAL PURPOSE TIMER MASKS **********************/ | ||
| 933 | /* TIMER_ENABLE Masks */ | ||
| 934 | #define TIMEN0 0x0001 /* Enable Timer 0 */ | ||
| 935 | #define TIMEN1 0x0002 /* Enable Timer 1 */ | ||
| 936 | #define TIMEN2 0x0004 /* Enable Timer 2 */ | ||
| 937 | #define TIMEN3 0x0008 /* Enable Timer 3 */ | ||
| 938 | #define TIMEN4 0x0010 /* Enable Timer 4 */ | ||
| 939 | #define TIMEN5 0x0020 /* Enable Timer 5 */ | ||
| 940 | #define TIMEN6 0x0040 /* Enable Timer 6 */ | ||
| 941 | #define TIMEN7 0x0080 /* Enable Timer 7 */ | ||
| 942 | |||
| 943 | /* TIMER_DISABLE Masks */ | ||
| 944 | #define TIMDIS0 TIMEN0 /* Disable Timer 0 */ | ||
| 945 | #define TIMDIS1 TIMEN1 /* Disable Timer 1 */ | ||
| 946 | #define TIMDIS2 TIMEN2 /* Disable Timer 2 */ | ||
| 947 | #define TIMDIS3 TIMEN3 /* Disable Timer 3 */ | ||
| 948 | #define TIMDIS4 TIMEN4 /* Disable Timer 4 */ | ||
| 949 | #define TIMDIS5 TIMEN5 /* Disable Timer 5 */ | ||
| 950 | #define TIMDIS6 TIMEN6 /* Disable Timer 6 */ | ||
| 951 | #define TIMDIS7 TIMEN7 /* Disable Timer 7 */ | ||
| 952 | |||
| 953 | /* TIMER_STATUS Masks */ | ||
| 954 | #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ | ||
| 955 | #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ | ||
| 956 | #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ | ||
| 957 | #define TIMIL3 0x00000008 /* Timer 3 Interrupt */ | ||
| 958 | #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ | ||
| 959 | #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ | ||
| 960 | #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ | ||
| 961 | #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ | ||
| 962 | #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ | ||
| 963 | #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ | ||
| 964 | #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ | ||
| 965 | #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ | ||
| 966 | #define TIMIL4 0x00010000 /* Timer 4 Interrupt */ | ||
| 967 | #define TIMIL5 0x00020000 /* Timer 5 Interrupt */ | ||
| 968 | #define TIMIL6 0x00040000 /* Timer 6 Interrupt */ | ||
| 969 | #define TIMIL7 0x00080000 /* Timer 7 Interrupt */ | ||
| 970 | #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ | ||
| 971 | #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ | ||
| 972 | #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ | ||
| 973 | #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ | ||
| 974 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ | ||
| 975 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ | ||
| 976 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ | ||
| 977 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ | ||
| 978 | |||
| 979 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
| 980 | #define TOVL_ERR0 TOVF_ERR0 | ||
| 981 | #define TOVL_ERR1 TOVF_ERR1 | ||
| 982 | #define TOVL_ERR2 TOVF_ERR2 | ||
| 983 | #define TOVL_ERR3 TOVF_ERR3 | ||
| 984 | #define TOVL_ERR4 TOVF_ERR4 | ||
| 985 | #define TOVL_ERR5 TOVF_ERR5 | ||
| 986 | #define TOVL_ERR6 TOVF_ERR6 | ||
| 987 | #define TOVL_ERR7 TOVF_ERR7 | ||
| 988 | |||
| 989 | /* TIMERx_CONFIG Masks */ | ||
| 990 | #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ | ||
| 991 | #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ | ||
| 992 | #define EXT_CLK 0x0003 /* External Clock Mode */ | ||
| 993 | #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ | ||
| 994 | #define PERIOD_CNT 0x0008 /* Period Count */ | ||
| 995 | #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ | ||
| 996 | #define TIN_SEL 0x0020 /* Timer Input Select */ | ||
| 997 | #define OUT_DIS 0x0040 /* Output Pad Disable */ | ||
| 998 | #define CLK_SEL 0x0080 /* Timer Clock Select */ | ||
| 999 | #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ | ||
| 1000 | #define EMU_RUN 0x0200 /* Emulation Behavior Select */ | ||
| 1001 | #define ERR_TYP 0xC000 /* Error Type */ | ||
| 1002 | |||
| 1003 | |||
| 1004 | /* ****************** GPIO PORTS F, G, H MASKS ***********************/ | ||
| 1005 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ | ||
| 1006 | /* Port F Masks */ | ||
| 1007 | #define PF0 0x0001 | ||
| 1008 | #define PF1 0x0002 | ||
| 1009 | #define PF2 0x0004 | ||
| 1010 | #define PF3 0x0008 | ||
| 1011 | #define PF4 0x0010 | ||
| 1012 | #define PF5 0x0020 | ||
| 1013 | #define PF6 0x0040 | ||
| 1014 | #define PF7 0x0080 | ||
| 1015 | #define PF8 0x0100 | ||
| 1016 | #define PF9 0x0200 | ||
| 1017 | #define PF10 0x0400 | ||
| 1018 | #define PF11 0x0800 | ||
| 1019 | #define PF12 0x1000 | ||
| 1020 | #define PF13 0x2000 | ||
| 1021 | #define PF14 0x4000 | ||
| 1022 | #define PF15 0x8000 | ||
| 1023 | |||
| 1024 | /* Port G Masks */ | ||
| 1025 | #define PG0 0x0001 | ||
| 1026 | #define PG1 0x0002 | ||
| 1027 | #define PG2 0x0004 | ||
| 1028 | #define PG3 0x0008 | ||
| 1029 | #define PG4 0x0010 | ||
| 1030 | #define PG5 0x0020 | ||
| 1031 | #define PG6 0x0040 | ||
| 1032 | #define PG7 0x0080 | ||
| 1033 | #define PG8 0x0100 | ||
| 1034 | #define PG9 0x0200 | ||
| 1035 | #define PG10 0x0400 | ||
| 1036 | #define PG11 0x0800 | ||
| 1037 | #define PG12 0x1000 | ||
| 1038 | #define PG13 0x2000 | ||
| 1039 | #define PG14 0x4000 | ||
| 1040 | #define PG15 0x8000 | ||
| 1041 | |||
| 1042 | /* Port H Masks */ | ||
| 1043 | #define PH0 0x0001 | ||
| 1044 | #define PH1 0x0002 | ||
| 1045 | #define PH2 0x0004 | ||
| 1046 | #define PH3 0x0008 | ||
| 1047 | #define PH4 0x0010 | ||
| 1048 | #define PH5 0x0020 | ||
| 1049 | #define PH6 0x0040 | ||
| 1050 | #define PH7 0x0080 | ||
| 1051 | |||
| 1052 | |||
| 1053 | /* ******************* SERIAL PORT MASKS **************************************/ | ||
| 1054 | /* SPORTx_TCR1 Masks */ | ||
| 1055 | #define TSPEN 0x0001 /* Transmit Enable */ | ||
| 1056 | #define ITCLK 0x0002 /* Internal Transmit Clock Select */ | ||
| 1057 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ | ||
| 1058 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 1059 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 1060 | #define TLSBIT 0x0010 /* Transmit Bit Order */ | ||
| 1061 | #define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ | ||
| 1062 | #define TFSR 0x0400 /* Transmit Frame Sync Required Select */ | ||
| 1063 | #define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ | ||
| 1064 | #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ | ||
| 1065 | #define LATFS 0x2000 /* Late Transmit Frame Sync Select */ | ||
| 1066 | #define TCKFE 0x4000 /* Clock Falling Edge Select */ | ||
| 1067 | |||
| 1068 | /* SPORTx_TCR2 Masks and Macro */ | ||
| 1069 | #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ | ||
| 1070 | #define TXSE 0x0100 /* TX Secondary Enable */ | ||
| 1071 | #define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ | ||
| 1072 | #define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ | ||
| 1073 | |||
| 1074 | /* SPORTx_RCR1 Masks */ | ||
| 1075 | #define RSPEN 0x0001 /* Receive Enable */ | ||
| 1076 | #define IRCLK 0x0002 /* Internal Receive Clock Select */ | ||
| 1077 | #define DTYPE_NORM 0x0004 /* Data Format Normal */ | ||
| 1078 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 1079 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 1080 | #define RLSBIT 0x0010 /* Receive Bit Order */ | ||
| 1081 | #define IRFS 0x0200 /* Internal Receive Frame Sync Select */ | ||
| 1082 | #define RFSR 0x0400 /* Receive Frame Sync Required Select */ | ||
| 1083 | #define LRFS 0x1000 /* Low Receive Frame Sync Select */ | ||
| 1084 | #define LARFS 0x2000 /* Late Receive Frame Sync Select */ | ||
| 1085 | #define RCKFE 0x4000 /* Clock Falling Edge Select */ | ||
| 1086 | |||
| 1087 | /* SPORTx_RCR2 Masks */ | ||
| 1088 | #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ | ||
| 1089 | #define RXSE 0x0100 /* RX Secondary Enable */ | ||
| 1090 | #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ | ||
| 1091 | #define RRFST 0x0400 /* Right-First Data Order */ | ||
| 1092 | |||
| 1093 | /* SPORTx_STAT Masks */ | ||
| 1094 | #define RXNE 0x0001 /* Receive FIFO Not Empty Status */ | ||
| 1095 | #define RUVF 0x0002 /* Sticky Receive Underflow Status */ | ||
| 1096 | #define ROVF 0x0004 /* Sticky Receive Overflow Status */ | ||
| 1097 | #define TXF 0x0008 /* Transmit FIFO Full Status */ | ||
| 1098 | #define TUVF 0x0010 /* Sticky Transmit Underflow Status */ | ||
| 1099 | #define TOVF 0x0020 /* Sticky Transmit Overflow Status */ | ||
| 1100 | #define TXHRE 0x0040 /* Transmit Hold Register Empty */ | ||
| 1101 | |||
| 1102 | /* SPORTx_MCMC1 Macros */ | ||
| 1103 | #define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ | ||
| 1104 | |||
| 1105 | /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ | ||
| 1106 | #define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ | ||
| 1107 | |||
| 1108 | /* SPORTx_MCMC2 Masks */ | ||
| 1109 | #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ | ||
| 1110 | #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ | ||
| 1111 | #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ | ||
| 1112 | #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ | ||
| 1113 | #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ | ||
| 1114 | #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ | ||
| 1115 | #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ | ||
| 1116 | #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ | ||
| 1117 | #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ | ||
| 1118 | #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ | ||
| 1119 | #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ | ||
| 1120 | #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ | ||
| 1121 | #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ | ||
| 1122 | #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ | ||
| 1123 | #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ | ||
| 1124 | #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ | ||
| 1125 | #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ | ||
| 1126 | #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ | ||
| 1127 | #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ | ||
| 1128 | #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ | ||
| 1129 | #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ | ||
| 1130 | #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ | ||
| 1131 | #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ | ||
| 1132 | |||
| 1133 | |||
| 1134 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ | ||
| 1135 | /* EBIU_AMGCTL Masks */ | ||
| 1136 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | ||
| 1137 | #define AMBEN_NONE 0x0000 /* All Banks Disabled */ | ||
| 1138 | #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ | ||
| 1139 | #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ | ||
| 1140 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ | ||
| 1141 | #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ | ||
| 1142 | |||
| 1143 | /* EBIU_AMBCTL0 Masks */ | ||
| 1144 | #define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ | ||
| 1145 | #define B0RDYPOL 0x00000002 /* B0 RDY Active High */ | ||
| 1146 | #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ | ||
| 1147 | #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ | ||
| 1148 | #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ | ||
| 1149 | #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ | ||
| 1150 | #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 1151 | #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 1152 | #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 1153 | #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 1154 | #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 1155 | #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 1156 | #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 1157 | #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 1158 | #define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ | ||
| 1159 | #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ | ||
| 1160 | #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ | ||
| 1161 | #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ | ||
| 1162 | #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ | ||
| 1163 | #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ | ||
| 1164 | #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ | ||
| 1165 | #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ | ||
| 1166 | #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ | ||
| 1167 | #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ | ||
| 1168 | #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ | ||
| 1169 | #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ | ||
| 1170 | #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ | ||
| 1171 | #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ | ||
| 1172 | #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ | ||
| 1173 | #define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ | ||
| 1174 | #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ | ||
| 1175 | #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ | ||
| 1176 | #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ | ||
| 1177 | #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ | ||
| 1178 | #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ | ||
| 1179 | #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ | ||
| 1180 | #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ | ||
| 1181 | #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ | ||
| 1182 | #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ | ||
| 1183 | #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ | ||
| 1184 | #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ | ||
| 1185 | #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ | ||
| 1186 | #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ | ||
| 1187 | #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ | ||
| 1188 | |||
| 1189 | #define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ | ||
| 1190 | #define B1RDYPOL 0x00020000 /* B1 RDY Active High */ | ||
| 1191 | #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ | ||
| 1192 | #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ | ||
| 1193 | #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ | ||
| 1194 | #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ | ||
| 1195 | #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 1196 | #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 1197 | #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 1198 | #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 1199 | #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 1200 | #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 1201 | #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 1202 | #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 1203 | #define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ | ||
| 1204 | #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ | ||
| 1205 | #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ | ||
| 1206 | #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ | ||
| 1207 | #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ | ||
| 1208 | #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ | ||
| 1209 | #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ | ||
| 1210 | #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ | ||
| 1211 | #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ | ||
| 1212 | #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ | ||
| 1213 | #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ | ||
| 1214 | #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ | ||
| 1215 | #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ | ||
| 1216 | #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ | ||
| 1217 | #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ | ||
| 1218 | #define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ | ||
| 1219 | #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ | ||
| 1220 | #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ | ||
| 1221 | #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ | ||
| 1222 | #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ | ||
| 1223 | #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ | ||
| 1224 | #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ | ||
| 1225 | #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ | ||
| 1226 | #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ | ||
| 1227 | #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ | ||
| 1228 | #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ | ||
| 1229 | #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ | ||
| 1230 | #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ | ||
| 1231 | #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ | ||
| 1232 | #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ | ||
| 1233 | |||
| 1234 | /* EBIU_AMBCTL1 Masks */ | ||
| 1235 | #define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ | ||
| 1236 | #define B2RDYPOL 0x00000002 /* B2 RDY Active High */ | ||
| 1237 | #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ | ||
| 1238 | #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ | ||
| 1239 | #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ | ||
| 1240 | #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ | ||
| 1241 | #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 1242 | #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 1243 | #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 1244 | #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 1245 | #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 1246 | #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 1247 | #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 1248 | #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 1249 | #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ | ||
| 1250 | #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ | ||
| 1251 | #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ | ||
| 1252 | #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ | ||
| 1253 | #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ | ||
| 1254 | #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ | ||
| 1255 | #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ | ||
| 1256 | #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ | ||
| 1257 | #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ | ||
| 1258 | #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ | ||
| 1259 | #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ | ||
| 1260 | #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ | ||
| 1261 | #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ | ||
| 1262 | #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ | ||
| 1263 | #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ | ||
| 1264 | #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ | ||
| 1265 | #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ | ||
| 1266 | #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ | ||
| 1267 | #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ | ||
| 1268 | #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ | ||
| 1269 | #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ | ||
| 1270 | #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ | ||
| 1271 | #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ | ||
| 1272 | #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ | ||
| 1273 | #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ | ||
| 1274 | #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ | ||
| 1275 | #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ | ||
| 1276 | #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ | ||
| 1277 | #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ | ||
| 1278 | #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ | ||
| 1279 | |||
| 1280 | #define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ | ||
| 1281 | #define B3RDYPOL 0x00020000 /* B3 RDY Active High */ | ||
| 1282 | #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ | ||
| 1283 | #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ | ||
| 1284 | #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ | ||
| 1285 | #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ | ||
| 1286 | #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ | ||
| 1287 | #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ | ||
| 1288 | #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ | ||
| 1289 | #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ | ||
| 1290 | #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ | ||
| 1291 | #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ | ||
| 1292 | #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ | ||
| 1293 | #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ | ||
| 1294 | #define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ | ||
| 1295 | #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ | ||
| 1296 | #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ | ||
| 1297 | #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ | ||
| 1298 | #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ | ||
| 1299 | #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ | ||
| 1300 | #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ | ||
| 1301 | #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ | ||
| 1302 | #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ | ||
| 1303 | #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ | ||
| 1304 | #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ | ||
| 1305 | #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ | ||
| 1306 | #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ | ||
| 1307 | #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ | ||
| 1308 | #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ | ||
| 1309 | #define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ | ||
| 1310 | #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ | ||
| 1311 | #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ | ||
| 1312 | #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ | ||
| 1313 | #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ | ||
| 1314 | #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ | ||
| 1315 | #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ | ||
| 1316 | #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ | ||
| 1317 | #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ | ||
| 1318 | #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ | ||
| 1319 | #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ | ||
| 1320 | #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ | ||
| 1321 | #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ | ||
| 1322 | #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ | ||
| 1323 | #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ | ||
| 1324 | |||
| 1325 | |||
| 1326 | /* ********************** SDRAM CONTROLLER MASKS **********************************************/ | ||
| 1327 | /* EBIU_SDGCTL Masks */ | ||
| 1328 | #define SCTLE 0x00000001 /* Enable SDRAM Signals */ | ||
| 1329 | #define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ | ||
| 1330 | #define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ | ||
| 1331 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ | ||
| 1332 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ | ||
| 1333 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ | ||
| 1334 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ | ||
| 1335 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | ||
| 1336 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | ||
| 1337 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | ||
| 1338 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | ||
| 1339 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | ||
| 1340 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | ||
| 1341 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | ||
| 1342 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | ||
| 1343 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | ||
| 1344 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | ||
| 1345 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | ||
| 1346 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | ||
| 1347 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | ||
| 1348 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | ||
| 1349 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | ||
| 1350 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | ||
| 1351 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | ||
| 1352 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | ||
| 1353 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | ||
| 1354 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | ||
| 1355 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | ||
| 1356 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | ||
| 1357 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | ||
| 1358 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | ||
| 1359 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | ||
| 1360 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | ||
| 1361 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | ||
| 1362 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | ||
| 1363 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | ||
| 1364 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | ||
| 1365 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | ||
| 1366 | #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ | ||
| 1367 | #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ | ||
| 1368 | #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ | ||
| 1369 | #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ | ||
| 1370 | #define EBUFE 0x02000000 /* Enable External Buffering Timing */ | ||
| 1371 | #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ | ||
| 1372 | #define EMREN 0x10000000 /* Extended Mode Register Enable */ | ||
| 1373 | #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ | ||
| 1374 | #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ | ||
| 1375 | |||
| 1376 | /* EBIU_SDBCTL Masks */ | ||
| 1377 | #define EBE 0x0001 /* Enable SDRAM External Bank */ | ||
| 1378 | #define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ | ||
| 1379 | #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ | ||
| 1380 | #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ | ||
| 1381 | #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ | ||
| 1382 | #define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ | ||
| 1383 | #define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ | ||
| 1384 | #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ | ||
| 1385 | #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ | ||
| 1386 | #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ | ||
| 1387 | #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ | ||
| 1388 | |||
| 1389 | /* EBIU_SDSTAT Masks */ | ||
| 1390 | #define SDCI 0x0001 /* SDRAM Controller Idle */ | ||
| 1391 | #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ | ||
| 1392 | #define SDPUA 0x0004 /* SDRAM Power-Up Active */ | ||
| 1393 | #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ | ||
| 1394 | #define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ | ||
| 1395 | #define BGSTAT 0x0020 /* Bus Grant Status */ | ||
| 1396 | |||
| 1397 | |||
| 1398 | /* ************************** DMA CONTROLLER MASKS ********************************/ | ||
| 1399 | /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ | ||
| 1400 | #define DMAEN 0x0001 /* DMA Channel Enable */ | ||
| 1401 | #define WNR 0x0002 /* Channel Direction (W/R*) */ | ||
| 1402 | #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ | ||
| 1403 | #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ | ||
| 1404 | #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ | ||
| 1405 | #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ | ||
| 1406 | #define RESTART 0x0020 /* DMA Buffer Clear */ | ||
| 1407 | #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ | ||
| 1408 | #define DI_EN 0x0080 /* Data Interrupt Enable */ | ||
| 1409 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | ||
| 1410 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | ||
| 1411 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | ||
| 1412 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | ||
| 1413 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | ||
| 1414 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | ||
| 1415 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | ||
| 1416 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | ||
| 1417 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | ||
| 1418 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | ||
| 1419 | #define NDSIZE 0x0900 /* Next Descriptor Size */ | ||
| 1420 | #define DMAFLOW 0x7000 /* Flow Control */ | ||
| 1421 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
| 1422 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
| 1423 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | ||
| 1424 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | ||
| 1425 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | ||
| 1426 | |||
| 1427 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | ||
| 1428 | #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ | ||
| 1429 | #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ | ||
| 1430 | #define PMAP_PPI 0x0000 /* PPI Port DMA */ | ||
| 1431 | #define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ | ||
| 1432 | #define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ | ||
| 1433 | #define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ | ||
| 1434 | #define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ | ||
| 1435 | #define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ | ||
| 1436 | #define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ | ||
| 1437 | #define PMAP_SPI 0x7000 /* SPI Port DMA */ | ||
| 1438 | #define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ | ||
| 1439 | #define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ | ||
| 1440 | #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ | ||
| 1441 | #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ | ||
| 1442 | |||
| 1443 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ | ||
| 1444 | #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ | ||
| 1445 | #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ | ||
| 1446 | #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ | ||
| 1447 | #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ | ||
| 1448 | |||
| 1449 | |||
| 1450 | /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ | ||
| 1451 | /* PPI_CONTROL Masks */ | ||
| 1452 | #define PORT_EN 0x0001 /* PPI Port Enable */ | ||
| 1453 | #define PORT_DIR 0x0002 /* PPI Port Direction */ | ||
| 1454 | #define XFR_TYPE 0x000C /* PPI Transfer Type */ | ||
| 1455 | #define PORT_CFG 0x0030 /* PPI Port Configuration */ | ||
| 1456 | #define FLD_SEL 0x0040 /* PPI Active Field Select */ | ||
| 1457 | #define PACK_EN 0x0080 /* PPI Packing Mode */ | ||
| 1458 | #define DMA32 0x0100 /* PPI 32-bit DMA Enable */ | ||
| 1459 | #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ | ||
| 1460 | #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ | ||
| 1461 | #define DLEN_8 0x0000 /* Data Length = 8 Bits */ | ||
| 1462 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ | ||
| 1463 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ | ||
| 1464 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ | ||
| 1465 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ | ||
| 1466 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ | ||
| 1467 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ | ||
| 1468 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ | ||
| 1469 | #define DLENGTH 0x3800 /* PPI Data Length */ | ||
| 1470 | #define POLC 0x4000 /* PPI Clock Polarity */ | ||
| 1471 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | ||
| 1472 | |||
| 1473 | /* PPI_STATUS Masks */ | ||
| 1474 | #define FLD 0x0400 /* Field Indicator */ | ||
| 1475 | #define FT_ERR 0x0800 /* Frame Track Error */ | ||
| 1476 | #define OVR 0x1000 /* FIFO Overflow Error */ | ||
| 1477 | #define UNDR 0x2000 /* FIFO Underrun Error */ | ||
| 1478 | #define ERR_DET 0x4000 /* Error Detected Indicator */ | ||
| 1479 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ | ||
| 1480 | |||
| 1481 | |||
| 1482 | /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ | ||
| 1483 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ | ||
| 1484 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ | ||
| 1485 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ | ||
| 1486 | |||
| 1487 | /* TWI_PRESCALE Masks */ | ||
| 1488 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ | ||
| 1489 | #define TWI_ENA 0x0080 /* TWI Enable */ | ||
| 1490 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | ||
| 1491 | |||
| 1492 | /* TWI_SLAVE_CTRL Masks */ | ||
| 1493 | #define SEN 0x0001 /* Slave Enable */ | ||
| 1494 | #define SADD_LEN 0x0002 /* Slave Address Length */ | ||
| 1495 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | ||
| 1496 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ | ||
| 1497 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ | ||
| 1498 | |||
| 1499 | /* TWI_SLAVE_STAT Masks */ | ||
| 1500 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | ||
| 1501 | #define GCALL 0x0002 /* General Call Indicator */ | ||
| 1502 | |||
| 1503 | /* TWI_MASTER_CTRL Masks */ | ||
| 1504 | #define MEN 0x0001 /* Master Mode Enable */ | ||
| 1505 | #define MADD_LEN 0x0002 /* Master Address Length */ | ||
| 1506 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | ||
| 1507 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ | ||
| 1508 | #define STOP 0x0010 /* Issue Stop Condition */ | ||
| 1509 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ | ||
| 1510 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ | ||
| 1511 | #define SDAOVR 0x4000 /* Serial Data Override */ | ||
| 1512 | #define SCLOVR 0x8000 /* Serial Clock Override */ | ||
| 1513 | |||
| 1514 | /* TWI_MASTER_STAT Masks */ | ||
| 1515 | #define MPROG 0x0001 /* Master Transfer In Progress */ | ||
| 1516 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ | ||
| 1517 | #define ANAK 0x0004 /* Address Not Acknowledged */ | ||
| 1518 | #define DNAK 0x0008 /* Data Not Acknowledged */ | ||
| 1519 | #define BUFRDERR 0x0010 /* Buffer Read Error */ | ||
| 1520 | #define BUFWRERR 0x0020 /* Buffer Write Error */ | ||
| 1521 | #define SDASEN 0x0040 /* Serial Data Sense */ | ||
| 1522 | #define SCLSEN 0x0080 /* Serial Clock Sense */ | ||
| 1523 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ | ||
| 1524 | |||
| 1525 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ | ||
| 1526 | #define SINIT 0x0001 /* Slave Transfer Initiated */ | ||
| 1527 | #define SCOMP 0x0002 /* Slave Transfer Complete */ | ||
| 1528 | #define SERR 0x0004 /* Slave Transfer Error */ | ||
| 1529 | #define SOVF 0x0008 /* Slave Overflow */ | ||
| 1530 | #define MCOMP 0x0010 /* Master Transfer Complete */ | ||
| 1531 | #define MERR 0x0020 /* Master Transfer Error */ | ||
| 1532 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | ||
| 1533 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | ||
| 1534 | |||
| 1535 | /* TWI_FIFO_CTRL Masks */ | ||
| 1536 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | ||
| 1537 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | ||
| 1538 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | ||
| 1539 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ | ||
| 1540 | |||
| 1541 | /* TWI_FIFO_STAT Masks */ | ||
| 1542 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ | ||
| 1543 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ | ||
| 1544 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ | ||
| 1545 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ | ||
| 1546 | |||
| 1547 | #define RCVSTAT 0x000C /* Receive FIFO Status */ | ||
| 1548 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ | ||
| 1549 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ | ||
| 1550 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ | ||
| 1551 | |||
| 1552 | |||
| 1553 | /* ******************* PIN CONTROL REGISTER MASKS ************************/ | ||
| 1554 | /* PORT_MUX Masks */ | ||
| 1555 | #define PJSE 0x0001 /* Port J SPI/SPORT Enable */ | ||
| 1556 | #define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ | ||
| 1557 | #define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ | ||
| 1558 | |||
| 1559 | #define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ | ||
| 1560 | #define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ | ||
| 1561 | #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ | ||
| 1562 | #define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ | ||
| 1563 | |||
| 1564 | #define PFDE 0x0008 /* Port F DMA Request Enable */ | ||
| 1565 | #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ | ||
| 1566 | #define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ | ||
| 1567 | |||
| 1568 | #define PFTE 0x0010 /* Port F Timer Enable */ | ||
| 1569 | #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ | ||
| 1570 | #define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ | ||
| 1571 | |||
| 1572 | #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ | ||
| 1573 | #define PFS6E_TIMER 0x0000 /* Enable TMR5 */ | ||
| 1574 | #define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ | ||
| 1575 | |||
| 1576 | #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ | ||
| 1577 | #define PFS5E_TIMER 0x0000 /* Enable TMR4 */ | ||
| 1578 | #define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ | ||
| 1579 | |||
| 1580 | #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ | ||
| 1581 | #define PFS4E_TIMER 0x0000 /* Enable TMR3 */ | ||
| 1582 | #define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ | ||
| 1583 | |||
| 1584 | #define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ | ||
| 1585 | #define PFFE_TIMER 0x0000 /* Enable TMR2 */ | ||
| 1586 | #define PFFE_PPI 0x0100 /* Enable PPI FS3 */ | ||
| 1587 | |||
| 1588 | #define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ | ||
| 1589 | #define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ | ||
| 1590 | #define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ | ||
| 1591 | |||
| 1592 | #define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ | ||
| 1593 | #define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ | ||
| 1594 | #define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ | ||
| 1595 | |||
| 1596 | #define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ | ||
| 1597 | #define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ | ||
| 1598 | #define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ | ||
| 1599 | |||
| 1600 | |||
| 1601 | /* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ | ||
| 1602 | /* HDMAx_CTL Masks */ | ||
| 1603 | #define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ | ||
| 1604 | #define REP 0x0002 /* HDMA Request Polarity */ | ||
| 1605 | #define UTE 0x0004 /* Urgency Threshold Enable */ | ||
| 1606 | #define OIE 0x0010 /* Overflow Interrupt Enable */ | ||
| 1607 | #define BDIE 0x0020 /* Block Done Interrupt Enable */ | ||
| 1608 | #define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ | ||
| 1609 | #define DRQ 0x0300 /* HDMA Request Type */ | ||
| 1610 | #define DRQ_NONE 0x0000 /* No Request */ | ||
| 1611 | #define DRQ_SINGLE 0x0100 /* Channels Request Single */ | ||
| 1612 | #define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ | ||
| 1613 | #define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ | ||
| 1614 | #define RBC 0x1000 /* Reload BCNT With IBCNT */ | ||
| 1615 | #define PS 0x2000 /* HDMA Pin Status */ | ||
| 1616 | #define OI 0x4000 /* Overflow Interrupt Generated */ | ||
| 1617 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | ||
| 1618 | |||
| 1619 | /* entry addresses of the user-callable Boot ROM functions */ | ||
| 1620 | |||
| 1621 | #define _BOOTROM_RESET 0xEF000000 | ||
| 1622 | #define _BOOTROM_FINAL_INIT 0xEF000002 | ||
| 1623 | #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 | ||
| 1624 | #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 | ||
| 1625 | #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A | ||
| 1626 | #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C | ||
| 1627 | #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 | ||
| 1628 | #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 | ||
| 1629 | #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 | ||
| 1630 | |||
| 1631 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
| 1632 | #define PGDE_UART PFDE_UART | ||
| 1633 | #define PGDE_DMA PFDE_DMA | ||
| 1634 | #define CKELOW SCKELOW | ||
| 1635 | |||
| 1636 | /* HOST Port Registers */ | ||
| 1637 | |||
| 1638 | #define HOST_CONTROL 0xffc03400 /* HOST Control Register */ | ||
| 1639 | #define HOST_STATUS 0xffc03404 /* HOST Status Register */ | ||
| 1640 | #define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */ | ||
| 1641 | |||
| 1642 | /* Counter Registers */ | ||
| 1643 | |||
| 1644 | #define CNT_CONFIG 0xffc03500 /* Configuration Register */ | ||
| 1645 | #define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */ | ||
| 1646 | #define CNT_STATUS 0xffc03508 /* Status Register */ | ||
| 1647 | #define CNT_COMMAND 0xffc0350c /* Command Register */ | ||
| 1648 | #define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */ | ||
| 1649 | #define CNT_COUNTER 0xffc03514 /* Counter Register */ | ||
| 1650 | #define CNT_MAX 0xffc03518 /* Maximal Count Register */ | ||
| 1651 | #define CNT_MIN 0xffc0351c /* Minimal Count Register */ | ||
| 1652 | |||
| 1653 | /* OTP/FUSE Registers */ | ||
| 1654 | |||
| 1655 | #define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */ | ||
| 1656 | #define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */ | ||
| 1657 | #define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */ | ||
| 1658 | #define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */ | ||
| 1659 | |||
| 1660 | /* Security Registers */ | ||
| 1661 | |||
| 1662 | #define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */ | ||
| 1663 | #define SECURE_CONTROL 0xffc03624 /* Secure Control */ | ||
| 1664 | #define SECURE_STATUS 0xffc03628 /* Secure Status */ | ||
| 1665 | |||
| 1666 | /* OTP Read/Write Data Buffer Registers */ | ||
| 1667 | |||
| 1668 | #define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1669 | #define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1670 | #define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1671 | #define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ | ||
| 1672 | |||
| 1673 | /* Motor Control PWM Registers */ | ||
| 1674 | |||
| 1675 | #define PWM_CTRL 0xffc03700 /* PWM Control Register */ | ||
| 1676 | #define PWM_STAT 0xffc03704 /* PWM Status Register */ | ||
| 1677 | #define PWM_TM 0xffc03708 /* PWM Period Register */ | ||
| 1678 | #define PWM_DT 0xffc0370c /* PWM Dead Time Register */ | ||
| 1679 | #define PWM_GATE 0xffc03710 /* PWM Chopping Control */ | ||
| 1680 | #define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */ | ||
| 1681 | #define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */ | ||
| 1682 | #define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */ | ||
| 1683 | #define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */ | ||
| 1684 | #define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */ | ||
| 1685 | #define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */ | ||
| 1686 | #define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */ | ||
| 1687 | #define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */ | ||
| 1688 | #define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */ | ||
| 1689 | #define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */ | ||
| 1690 | |||
| 1691 | |||
| 1692 | /* ********************************************************** */ | ||
| 1693 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | ||
| 1694 | /* and MULTI BIT READ MACROS */ | ||
| 1695 | /* ********************************************************** */ | ||
| 1696 | |||
| 1697 | /* Bit masks for HOST_CONTROL */ | ||
| 1698 | |||
| 1699 | #define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ | ||
| 1700 | #define HOST_CNTR_nHOST_EN 0x0 | ||
| 1701 | #define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ | ||
| 1702 | #define HOST_CNTR_nHOST_END 0x0 | ||
| 1703 | #define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ | ||
| 1704 | #define HOST_CNTR_nDATA_SIZE 0x0 | ||
| 1705 | #define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ | ||
| 1706 | #define HOST_CNTR_nHOST_RST 0x0 | ||
| 1707 | #define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ | ||
| 1708 | #define HOST_CNTR_nHRDY_OVR 0x0 | ||
| 1709 | #define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ | ||
| 1710 | #define HOST_CNTR_nINT_MODE 0x0 | ||
| 1711 | #define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ | ||
| 1712 | #define HOST_CNTR_ nBT_EN 0x0 | ||
| 1713 | #define HOST_CNTR_EHW 0x100 /* Enable Host Write */ | ||
| 1714 | #define HOST_CNTR_nEHW 0x0 | ||
| 1715 | #define HOST_CNTR_EHR 0x200 /* Enable Host Read */ | ||
| 1716 | #define HOST_CNTR_nEHR 0x0 | ||
| 1717 | #define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ | ||
| 1718 | #define HOST_CNTR_nBDR 0x0 | ||
| 1719 | |||
| 1720 | /* Bit masks for HOST_STATUS */ | ||
| 1721 | |||
| 1722 | #define HOST_STAT_READY 0x1 /* DMA Ready */ | ||
| 1723 | #define HOST_STAT_nREADY 0x0 | ||
| 1724 | #define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ | ||
| 1725 | #define HOST_STAT_nFIFOFULL 0x0 | ||
| 1726 | #define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ | ||
| 1727 | #define HOST_STAT_nFIFOEMPTY 0x0 | ||
| 1728 | #define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ | ||
| 1729 | #define HOST_STAT_nCOMPLETE 0x0 | ||
| 1730 | #define HOST_STAT_HSHK 0x10 /* Host Handshake */ | ||
| 1731 | #define HOST_STAT_nHSHK 0x0 | ||
| 1732 | #define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ | ||
| 1733 | #define HOST_STAT_nTIMEOUT 0x0 | ||
| 1734 | #define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ | ||
| 1735 | #define HOST_STAT_nHIRQ 0x0 | ||
| 1736 | #define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ | ||
| 1737 | #define HOST_STAT_nALLOW_CNFG 0x0 | ||
| 1738 | #define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ | ||
| 1739 | #define HOST_STAT_nDMA_DIR 0x0 | ||
| 1740 | #define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ | ||
| 1741 | #define HOST_STAT_nBTE 0x0 | ||
| 1742 | #define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ | ||
| 1743 | #define HOST_STAT_nHOSTRD_DONE 0x0 | ||
| 1744 | |||
| 1745 | /* Bit masks for HOST_TIMEOUT */ | ||
| 1746 | |||
| 1747 | #define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | ||
| 1748 | |||
| 1749 | /* Bit masks for CNT_CONFIG */ | ||
| 1750 | |||
| 1751 | #define CNTE 0x1 /* Counter Enable */ | ||
| 1752 | #define nCNTE 0x0 | ||
| 1753 | #define DEBE 0x2 /* Debounce Enable */ | ||
| 1754 | #define nDEBE 0x0 | ||
| 1755 | #define CDGINV 0x10 /* CDG Pin Polarity Invert */ | ||
| 1756 | #define nCDGINV 0x0 | ||
| 1757 | #define CUDINV 0x20 /* CUD Pin Polarity Invert */ | ||
| 1758 | #define nCUDINV 0x0 | ||
| 1759 | #define CZMINV 0x40 /* CZM Pin Polarity Invert */ | ||
| 1760 | #define nCZMINV 0x0 | ||
| 1761 | #define CNTMODE 0x700 /* Counter Operating Mode */ | ||
| 1762 | #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ | ||
| 1763 | #define nZMZC 0x0 | ||
| 1764 | #define BNDMODE 0x3000 /* Boundary register Mode */ | ||
| 1765 | #define INPDIS 0x8000 /* CUG and CDG Input Disable */ | ||
| 1766 | #define nINPDIS 0x0 | ||
| 1767 | |||
| 1768 | /* Bit masks for CNT_IMASK */ | ||
| 1769 | |||
| 1770 | #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ | ||
| 1771 | #define nICIE 0x0 | ||
| 1772 | #define UCIE 0x2 /* Up count Interrupt Enable */ | ||
| 1773 | #define nUCIE 0x0 | ||
| 1774 | #define DCIE 0x4 /* Down count Interrupt Enable */ | ||
| 1775 | #define nDCIE 0x0 | ||
| 1776 | #define MINCIE 0x8 /* Min Count Interrupt Enable */ | ||
| 1777 | #define nMINCIE 0x0 | ||
| 1778 | #define MAXCIE 0x10 /* Max Count Interrupt Enable */ | ||
| 1779 | #define nMAXCIE 0x0 | ||
| 1780 | #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ | ||
| 1781 | #define nCOV31IE 0x0 | ||
| 1782 | #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ | ||
| 1783 | #define nCOV15IE 0x0 | ||
| 1784 | #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ | ||
| 1785 | #define nCZEROIE 0x0 | ||
| 1786 | #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ | ||
| 1787 | #define nCZMIE 0x0 | ||
| 1788 | #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ | ||
| 1789 | #define nCZMEIE 0x0 | ||
| 1790 | #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ | ||
| 1791 | #define nCZMZIE 0x0 | ||
| 1792 | |||
| 1793 | /* Bit masks for CNT_STATUS */ | ||
| 1794 | |||
| 1795 | #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ | ||
| 1796 | #define nICII 0x0 | ||
| 1797 | #define UCII 0x2 /* Up count Interrupt Identifier */ | ||
| 1798 | #define nUCII 0x0 | ||
| 1799 | #define DCII 0x4 /* Down count Interrupt Identifier */ | ||
| 1800 | #define nDCII 0x0 | ||
| 1801 | #define MINCII 0x8 /* Min Count Interrupt Identifier */ | ||
| 1802 | #define nMINCII 0x0 | ||
| 1803 | #define MAXCII 0x10 /* Max Count Interrupt Identifier */ | ||
| 1804 | #define nMAXCII 0x0 | ||
| 1805 | #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ | ||
| 1806 | #define nCOV31II 0x0 | ||
| 1807 | #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ | ||
| 1808 | #define nCOV15II 0x0 | ||
| 1809 | #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ | ||
| 1810 | #define nCZEROII 0x0 | ||
| 1811 | #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ | ||
| 1812 | #define nCZMII 0x0 | ||
| 1813 | #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ | ||
| 1814 | #define nCZMEII 0x0 | ||
| 1815 | #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ | ||
| 1816 | #define nCZMZII 0x0 | ||
| 1817 | |||
| 1818 | /* Bit masks for CNT_COMMAND */ | ||
| 1819 | |||
| 1820 | #define W1LCNT 0xf /* Load Counter Register */ | ||
| 1821 | #define W1LMIN 0xf0 /* Load Min Register */ | ||
| 1822 | #define W1LMAX 0xf00 /* Load Max Register */ | ||
| 1823 | #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ | ||
| 1824 | #define nW1ZMONCE 0x0 | ||
| 1825 | |||
| 1826 | /* Bit masks for CNT_DEBOUNCE */ | ||
| 1827 | |||
| 1828 | #define DPRESCALE 0xf /* Load Counter Register */ | ||
| 1829 | |||
| 1830 | /* CNT_COMMAND bit field options */ | ||
| 1831 | |||
| 1832 | #define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ | ||
| 1833 | #define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ | ||
| 1834 | #define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ | ||
| 1835 | |||
| 1836 | #define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ | ||
| 1837 | #define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ | ||
| 1838 | #define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ | ||
| 1839 | |||
| 1840 | #define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ | ||
| 1841 | #define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ | ||
| 1842 | #define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ | ||
| 1843 | |||
| 1844 | /* CNT_CONFIG bit field options */ | ||
| 1845 | |||
| 1846 | #define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ | ||
| 1847 | #define CNTMODE_BINENC 0x0100 /* binary encoder mode */ | ||
| 1848 | #define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ | ||
| 1849 | #define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ | ||
| 1850 | #define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ | ||
| 1851 | |||
| 1852 | #define BNDMODE_COMP 0x0000 /* boundary compare mode */ | ||
| 1853 | #define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ | ||
| 1854 | #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ | ||
| 1855 | #define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ | ||
| 1856 | |||
| 1857 | /* Bit masks for OTP_CONTROL */ | ||
| 1858 | |||
| 1859 | #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ | ||
| 1860 | #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ | ||
| 1861 | #define nFIEN 0x0 | ||
| 1862 | #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ | ||
| 1863 | #define nFTESTDEC 0x0 | ||
| 1864 | #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ | ||
| 1865 | #define nFWRTEST 0x0 | ||
| 1866 | #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ | ||
| 1867 | #define nFRDEN 0x0 | ||
| 1868 | #define FWREN 0x8000 /* OTP/Fuse Write Enable */ | ||
| 1869 | #define nFWREN 0x0 | ||
| 1870 | |||
| 1871 | /* Bit masks for OTP_BEN */ | ||
| 1872 | |||
| 1873 | #define FBEN 0xffff /* OTP/Fuse Byte Enable */ | ||
| 1874 | |||
| 1875 | /* Bit masks for OTP_STATUS */ | ||
| 1876 | |||
| 1877 | #define FCOMP 0x1 /* OTP/Fuse Access Complete */ | ||
| 1878 | #define nFCOMP 0x0 | ||
| 1879 | #define FERROR 0x2 /* OTP/Fuse Access Error */ | ||
| 1880 | #define nFERROR 0x0 | ||
| 1881 | #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ | ||
| 1882 | #define nMMRGLOAD 0x0 | ||
| 1883 | #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ | ||
| 1884 | #define nMMRGLOCK 0x0 | ||
| 1885 | #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ | ||
| 1886 | #define nFPGMEN 0x0 | ||
| 1887 | |||
| 1888 | /* Bit masks for OTP_TIMING */ | ||
| 1889 | |||
| 1890 | #define USECDIV 0xff /* Micro Second Divider */ | ||
| 1891 | #define READACC 0x7f00 /* Read Access Time */ | ||
| 1892 | #define CPUMPRL 0x38000 /* Charge Pump Release Time */ | ||
| 1893 | #define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ | ||
| 1894 | #define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ | ||
| 1895 | #define PGMTIME 0xff000000 /* Program Time */ | ||
| 1896 | |||
| 1897 | /* Bit masks for SECURE_SYSSWT */ | ||
| 1898 | |||
| 1899 | #define EMUDABL 0x1 /* Emulation Disable. */ | ||
| 1900 | #define nEMUDABL 0x0 | ||
| 1901 | #define RSTDABL 0x2 /* Reset Disable */ | ||
| 1902 | #define nRSTDABL 0x0 | ||
| 1903 | #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ | ||
| 1904 | #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ | ||
| 1905 | #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ | ||
| 1906 | #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ | ||
| 1907 | #define nDMA0OVR 0x0 | ||
| 1908 | #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ | ||
| 1909 | #define nDMA1OVR 0x0 | ||
| 1910 | #define EMUOVR 0x4000 /* Emulation Override */ | ||
| 1911 | #define nEMUOVR 0x0 | ||
| 1912 | #define OTPSEN 0x8000 /* OTP Secrets Enable. */ | ||
| 1913 | #define nOTPSEN 0x0 | ||
| 1914 | #define L2DABL 0x70000 /* L2 Memory Disable. */ | ||
| 1915 | |||
| 1916 | /* Bit masks for SECURE_CONTROL */ | ||
| 1917 | |||
| 1918 | #define SECURE0 0x1 /* SECURE 0 */ | ||
| 1919 | #define nSECURE0 0x0 | ||
| 1920 | #define SECURE1 0x2 /* SECURE 1 */ | ||
| 1921 | #define nSECURE1 0x0 | ||
| 1922 | #define SECURE2 0x4 /* SECURE 2 */ | ||
| 1923 | #define nSECURE2 0x0 | ||
| 1924 | #define SECURE3 0x8 /* SECURE 3 */ | ||
| 1925 | #define nSECURE3 0x0 | ||
| 1926 | |||
| 1927 | /* Bit masks for SECURE_STATUS */ | ||
| 1928 | |||
| 1929 | #define SECMODE 0x3 /* Secured Mode Control State */ | ||
| 1930 | #define NMI 0x4 /* Non Maskable Interrupt */ | ||
| 1931 | #define nNMI 0x0 | ||
| 1932 | #define AFVALID 0x8 /* Authentication Firmware Valid */ | ||
| 1933 | #define nAFVALID 0x0 | ||
| 1934 | #define AFEXIT 0x10 /* Authentication Firmware Exit */ | ||
| 1935 | #define nAFEXIT 0x0 | ||
| 1936 | #define SECSTAT 0xe0 /* Secure Status */ | ||
| 1937 | |||
| 1938 | |||
| 1939 | |||
| 1940 | #endif /* _DEF_BF51X_H */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/dma.h b/arch/blackfin/mach-bf518/include/mach/dma.h new file mode 100644 index 000000000000..bbd33c1706e2 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/dma.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* mach/dma.h - arch-specific DMA defines | ||
| 2 | * | ||
| 3 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 4 | * | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _MACH_DMA_H_ | ||
| 9 | #define _MACH_DMA_H_ | ||
| 10 | |||
| 11 | #define MAX_DMA_CHANNELS 16 | ||
| 12 | |||
| 13 | #define CH_PPI 0 /* PPI receive/transmit */ | ||
| 14 | #define CH_EMAC_RX 1 /* Ethernet MAC receive */ | ||
| 15 | #define CH_EMAC_TX 2 /* Ethernet MAC transmit */ | ||
| 16 | #define CH_SPORT0_RX 3 /* SPORT0 receive */ | ||
| 17 | #define CH_SPORT0_TX 4 /* SPORT0 transmit */ | ||
| 18 | #define CH_RSI 4 /* RSI */ | ||
| 19 | #define CH_SPORT1_RX 5 /* SPORT1 receive */ | ||
| 20 | #define CH_SPI1 5 /* SPI1 transmit/receive */ | ||
| 21 | #define CH_SPORT1_TX 6 /* SPORT1 transmit */ | ||
| 22 | #define CH_SPI0 7 /* SPI0 transmit/receive */ | ||
| 23 | #define CH_UART0_RX 8 /* UART0 receive */ | ||
| 24 | #define CH_UART0_TX 9 /* UART0 transmit */ | ||
| 25 | #define CH_UART1_RX 10 /* UART1 receive */ | ||
| 26 | #define CH_UART1_TX 11 /* UART1 transmit */ | ||
| 27 | |||
| 28 | #define CH_MEM_STREAM0_SRC 12 /* RX */ | ||
| 29 | #define CH_MEM_STREAM0_DEST 13 /* TX */ | ||
| 30 | #define CH_MEM_STREAM1_SRC 14 /* RX */ | ||
| 31 | #define CH_MEM_STREAM1_DEST 15 /* TX */ | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h new file mode 100644 index 000000000000..9757683c3948 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/gpio.h | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf518/include/mach/gpio.h | ||
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 4 | * | ||
| 5 | * Copyright (C) 2008 Analog Devices Inc. | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | #ifndef _MACH_GPIO_H_ | ||
| 11 | #define _MACH_GPIO_H_ | ||
| 12 | |||
| 13 | #define MAX_BLACKFIN_GPIOS 40 | ||
| 14 | |||
| 15 | #define GPIO_PF0 0 | ||
| 16 | #define GPIO_PF1 1 | ||
| 17 | #define GPIO_PF2 2 | ||
| 18 | #define GPIO_PF3 3 | ||
| 19 | #define GPIO_PF4 4 | ||
| 20 | #define GPIO_PF5 5 | ||
| 21 | #define GPIO_PF6 6 | ||
| 22 | #define GPIO_PF7 7 | ||
| 23 | #define GPIO_PF8 8 | ||
| 24 | #define GPIO_PF9 9 | ||
| 25 | #define GPIO_PF10 10 | ||
| 26 | #define GPIO_PF11 11 | ||
| 27 | #define GPIO_PF12 12 | ||
| 28 | #define GPIO_PF13 13 | ||
| 29 | #define GPIO_PF14 14 | ||
| 30 | #define GPIO_PF15 15 | ||
| 31 | #define GPIO_PG0 16 | ||
| 32 | #define GPIO_PG1 17 | ||
| 33 | #define GPIO_PG2 18 | ||
| 34 | #define GPIO_PG3 19 | ||
| 35 | #define GPIO_PG4 20 | ||
| 36 | #define GPIO_PG5 21 | ||
| 37 | #define GPIO_PG6 22 | ||
| 38 | #define GPIO_PG7 23 | ||
| 39 | #define GPIO_PG8 24 | ||
| 40 | #define GPIO_PG9 25 | ||
| 41 | #define GPIO_PG10 26 | ||
| 42 | #define GPIO_PG11 27 | ||
| 43 | #define GPIO_PG12 28 | ||
| 44 | #define GPIO_PG13 29 | ||
| 45 | #define GPIO_PG14 30 | ||
| 46 | #define GPIO_PG15 31 | ||
| 47 | #define GPIO_PH0 32 | ||
| 48 | #define GPIO_PH1 33 | ||
| 49 | #define GPIO_PH2 34 | ||
| 50 | #define GPIO_PH3 35 | ||
| 51 | #define GPIO_PH4 36 | ||
| 52 | #define GPIO_PH5 37 | ||
| 53 | #define GPIO_PH6 38 | ||
| 54 | #define GPIO_PH7 39 | ||
| 55 | |||
| 56 | #define PORT_F GPIO_PF0 | ||
| 57 | #define PORT_G GPIO_PG0 | ||
| 58 | #define PORT_H GPIO_PH0 | ||
| 59 | |||
| 60 | #endif /* _MACH_GPIO_H_ */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h new file mode 100644 index 000000000000..3ff0f093313d --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/irq.h | |||
| @@ -0,0 +1,260 @@ | |||
| 1 | /* | ||
| 2 | * file: include/asm-blackfin/mach-bf518/irq.h | ||
| 3 | * based on: include/asm-blackfin/mach-bf527/irq.h | ||
| 4 | * author: Michael Hennerich (michael.hennerich@analog.com) | ||
| 5 | * | ||
| 6 | * created: | ||
| 7 | * description: | ||
| 8 | * system mmr register map | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * this program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the gnu general public license as published by | ||
| 18 | * the free software foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * this program is distributed in the hope that it will be useful, | ||
| 22 | * but without any warranty; without even the implied warranty of | ||
| 23 | * merchantability or fitness for a particular purpose. see the | ||
| 24 | * gnu general public license for more details. | ||
| 25 | * | ||
| 26 | * you should have received a copy of the gnu general public license | ||
| 27 | * along with this program; see the file copying. | ||
| 28 | * if not, write to the free software foundation, | ||
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _BF518_IRQ_H_ | ||
| 33 | #define _BF518_IRQ_H_ | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Interrupt source definitions | ||
| 37 | Event Source Core Event Name | ||
| 38 | Core Emulation ** | ||
| 39 | Events (highest priority) EMU 0 | ||
| 40 | Reset RST 1 | ||
| 41 | NMI NMI 2 | ||
| 42 | Exception EVX 3 | ||
| 43 | Reserved -- 4 | ||
| 44 | Hardware Error IVHW 5 | ||
| 45 | Core Timer IVTMR 6 * | ||
| 46 | |||
| 47 | ..... | ||
| 48 | |||
| 49 | Software Interrupt 1 IVG14 31 | ||
| 50 | Software Interrupt 2 -- | ||
| 51 | (lowest priority) IVG15 32 * | ||
| 52 | */ | ||
| 53 | |||
| 54 | #define NR_PERI_INTS (2 * 32) | ||
| 55 | |||
| 56 | /* The ABSTRACT IRQ definitions */ | ||
| 57 | /** the first seven of the following are fixed, the rest you change if you need to **/ | ||
| 58 | #define IRQ_EMU 0 /* Emulation */ | ||
| 59 | #define IRQ_RST 1 /* reset */ | ||
| 60 | #define IRQ_NMI 2 /* Non Maskable */ | ||
| 61 | #define IRQ_EVX 3 /* Exception */ | ||
| 62 | #define IRQ_UNUSED 4 /* - unused interrupt */ | ||
| 63 | #define IRQ_HWERR 5 /* Hardware Error */ | ||
| 64 | #define IRQ_CORETMR 6 /* Core timer */ | ||
| 65 | |||
| 66 | #define BFIN_IRQ(x) ((x) + 7) | ||
| 67 | |||
| 68 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ | ||
| 69 | #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ | ||
| 70 | #define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */ | ||
| 71 | #define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */ | ||
| 72 | #define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */ | ||
| 73 | #define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */ | ||
| 74 | #define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */ | ||
| 75 | #define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */ | ||
| 76 | #define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */ | ||
| 77 | #define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */ | ||
| 78 | #define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */ | ||
| 79 | #define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ | ||
| 80 | #define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ | ||
| 81 | #define IRQ_RTC BFIN_IRQ(14) /* RTC */ | ||
| 82 | #define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */ | ||
| 83 | #define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ | ||
| 84 | #define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ | ||
| 85 | #define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */ | ||
| 86 | #define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */ | ||
| 87 | #define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */ | ||
| 88 | #define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ | ||
| 89 | #define IRQ_TWI BFIN_IRQ(20) /* TWI */ | ||
| 90 | #define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */ | ||
| 91 | #define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ | ||
| 92 | #define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ | ||
| 93 | #define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ | ||
| 94 | #define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ | ||
| 95 | #define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ | ||
| 96 | #define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ | ||
| 97 | #define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */ | ||
| 98 | #define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ | ||
| 99 | #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */ | ||
| 100 | #define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ | ||
| 101 | #define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ | ||
| 102 | #define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */ | ||
| 103 | #define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */ | ||
| 104 | #define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */ | ||
| 105 | #define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */ | ||
| 106 | #define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */ | ||
| 107 | #define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */ | ||
| 108 | #define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */ | ||
| 109 | #define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ | ||
| 110 | #define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ | ||
| 111 | #define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ | ||
| 112 | #define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */ | ||
| 113 | #define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */ | ||
| 114 | #define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */ | ||
| 115 | #define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */ | ||
| 116 | #define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */ | ||
| 117 | #define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */ | ||
| 118 | #define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */ | ||
| 119 | #define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */ | ||
| 120 | #define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */ | ||
| 121 | #define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */ | ||
| 122 | #define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */ | ||
| 123 | |||
| 124 | #define SYS_IRQS BFIN_IRQ(63) /* 70 */ | ||
| 125 | |||
| 126 | #define IRQ_PF0 71 | ||
| 127 | #define IRQ_PF1 72 | ||
| 128 | #define IRQ_PF2 73 | ||
| 129 | #define IRQ_PF3 74 | ||
| 130 | #define IRQ_PF4 75 | ||
| 131 | #define IRQ_PF5 76 | ||
| 132 | #define IRQ_PF6 77 | ||
| 133 | #define IRQ_PF7 78 | ||
| 134 | #define IRQ_PF8 79 | ||
| 135 | #define IRQ_PF9 80 | ||
| 136 | #define IRQ_PF10 81 | ||
| 137 | #define IRQ_PF11 82 | ||
| 138 | #define IRQ_PF12 83 | ||
| 139 | #define IRQ_PF13 84 | ||
| 140 | #define IRQ_PF14 85 | ||
| 141 | #define IRQ_PF15 86 | ||
| 142 | |||
| 143 | #define IRQ_PG0 87 | ||
| 144 | #define IRQ_PG1 88 | ||
| 145 | #define IRQ_PG2 89 | ||
| 146 | #define IRQ_PG3 90 | ||
| 147 | #define IRQ_PG4 91 | ||
| 148 | #define IRQ_PG5 92 | ||
| 149 | #define IRQ_PG6 93 | ||
| 150 | #define IRQ_PG7 94 | ||
| 151 | #define IRQ_PG8 95 | ||
| 152 | #define IRQ_PG9 96 | ||
| 153 | #define IRQ_PG10 97 | ||
| 154 | #define IRQ_PG11 98 | ||
| 155 | #define IRQ_PG12 99 | ||
| 156 | #define IRQ_PG13 100 | ||
| 157 | #define IRQ_PG14 101 | ||
| 158 | #define IRQ_PG15 102 | ||
| 159 | |||
| 160 | #define IRQ_PH0 103 | ||
| 161 | #define IRQ_PH1 104 | ||
| 162 | #define IRQ_PH2 105 | ||
| 163 | #define IRQ_PH3 106 | ||
| 164 | #define IRQ_PH4 107 | ||
| 165 | #define IRQ_PH5 108 | ||
| 166 | #define IRQ_PH6 109 | ||
| 167 | #define IRQ_PH7 110 | ||
| 168 | #define IRQ_PH8 111 | ||
| 169 | #define IRQ_PH9 112 | ||
| 170 | #define IRQ_PH10 113 | ||
| 171 | #define IRQ_PH11 114 | ||
| 172 | #define IRQ_PH12 115 | ||
| 173 | #define IRQ_PH13 116 | ||
| 174 | #define IRQ_PH14 117 | ||
| 175 | #define IRQ_PH15 118 | ||
| 176 | |||
| 177 | #define GPIO_IRQ_BASE IRQ_PF0 | ||
| 178 | |||
| 179 | #define NR_IRQS (IRQ_PH15 + 1) | ||
| 180 | |||
| 181 | #define IVG7 7 | ||
| 182 | #define IVG8 8 | ||
| 183 | #define IVG9 9 | ||
| 184 | #define IVG10 10 | ||
| 185 | #define IVG11 11 | ||
| 186 | #define IVG12 12 | ||
| 187 | #define IVG13 13 | ||
| 188 | #define IVG14 14 | ||
| 189 | #define IVG15 15 | ||
| 190 | |||
| 191 | /* IAR0 BIT FIELDS */ | ||
| 192 | #define IRQ_PLL_WAKEUP_POS 0 | ||
| 193 | #define IRQ_DMA0_ERROR_POS 4 | ||
| 194 | #define IRQ_DMAR0_BLK_POS 8 | ||
| 195 | #define IRQ_DMAR1_BLK_POS 12 | ||
| 196 | #define IRQ_DMAR0_OVR_POS 16 | ||
| 197 | #define IRQ_DMAR1_OVR_POS 20 | ||
| 198 | #define IRQ_PPI_ERROR_POS 24 | ||
| 199 | #define IRQ_MAC_ERROR_POS 28 | ||
| 200 | |||
| 201 | /* IAR1 BIT FIELDS */ | ||
| 202 | #define IRQ_SPORT0_ERROR_POS 0 | ||
| 203 | #define IRQ_SPORT1_ERROR_POS 4 | ||
| 204 | #define IRQ_PTP_ERROR_POS 8 | ||
| 205 | #define IRQ_UART0_ERROR_POS 16 | ||
| 206 | #define IRQ_UART1_ERROR_POS 20 | ||
| 207 | #define IRQ_RTC_POS 24 | ||
| 208 | #define IRQ_PPI_POS 28 | ||
| 209 | |||
| 210 | /* IAR2 BIT FIELDS */ | ||
| 211 | #define IRQ_SPORT0_RX_POS 0 | ||
| 212 | #define IRQ_SPORT0_TX_POS 4 | ||
| 213 | #define IRQ_RSI_POS 4 | ||
| 214 | #define IRQ_SPORT1_RX_POS 8 | ||
| 215 | #define IRQ_SPI1_POS 8 | ||
| 216 | #define IRQ_SPORT1_TX_POS 12 | ||
| 217 | #define IRQ_TWI_POS 16 | ||
| 218 | #define IRQ_SPI0_POS 20 | ||
| 219 | #define IRQ_UART0_RX_POS 24 | ||
| 220 | #define IRQ_UART0_TX_POS 28 | ||
| 221 | |||
| 222 | /* IAR3 BIT FIELDS */ | ||
| 223 | #define IRQ_UART1_RX_POS 0 | ||
| 224 | #define IRQ_UART1_TX_POS 4 | ||
| 225 | #define IRQ_OPTSEC_POS 8 | ||
| 226 | #define IRQ_CNT_POS 12 | ||
| 227 | #define IRQ_MAC_RX_POS 16 | ||
| 228 | #define IRQ_PORTH_INTA_POS 20 | ||
| 229 | #define IRQ_MAC_TX_POS 24 | ||
| 230 | #define IRQ_PORTH_INTB_POS 28 | ||
| 231 | |||
| 232 | /* IAR4 BIT FIELDS */ | ||
| 233 | #define IRQ_TIMER0_POS 0 | ||
| 234 | #define IRQ_TIMER1_POS 4 | ||
| 235 | #define IRQ_TIMER2_POS 8 | ||
| 236 | #define IRQ_TIMER3_POS 12 | ||
| 237 | #define IRQ_TIMER4_POS 16 | ||
| 238 | #define IRQ_TIMER5_POS 20 | ||
| 239 | #define IRQ_TIMER6_POS 24 | ||
| 240 | #define IRQ_TIMER7_POS 28 | ||
| 241 | |||
| 242 | /* IAR5 BIT FIELDS */ | ||
| 243 | #define IRQ_PORTG_INTA_POS 0 | ||
| 244 | #define IRQ_PORTG_INTB_POS 4 | ||
| 245 | #define IRQ_MEM_DMA0_POS 8 | ||
| 246 | #define IRQ_MEM_DMA1_POS 12 | ||
| 247 | #define IRQ_WATCH_POS 16 | ||
| 248 | #define IRQ_PORTF_INTA_POS 20 | ||
| 249 | #define IRQ_PORTF_INTB_POS 24 | ||
| 250 | #define IRQ_SPI0_ERROR_POS 28 | ||
| 251 | |||
| 252 | /* IAR6 BIT FIELDS */ | ||
| 253 | #define IRQ_SPI1_ERROR_POS 0 | ||
| 254 | #define IRQ_RSI_INT0_POS 12 | ||
| 255 | #define IRQ_RSI_INT1_POS 16 | ||
| 256 | #define IRQ_PWM_TRIP_POS 20 | ||
| 257 | #define IRQ_PWM_SYNC_POS 24 | ||
| 258 | #define IRQ_PTP_STAT_POS 28 | ||
| 259 | |||
| 260 | #endif /* _BF518_IRQ_H_ */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h new file mode 100644 index 000000000000..62bcc781bfaa --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/mem_map.h | |||
| @@ -0,0 +1,108 @@ | |||
| 1 | /* | ||
| 2 | * file: include/asm-blackfin/mach-bf518/mem_map.h | ||
| 3 | * based on: include/asm-blackfin/mach-bf527/mem_map.h | ||
| 4 | * author: Bryan Wu <cooloney@kernel.org> | ||
| 5 | * | ||
| 6 | * created: | ||
| 7 | * description: | ||
| 8 | * Memory MAP Common header file for blackfin BF518/6/4/2 of processors. | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * this program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the gnu general public license as published by | ||
| 17 | * the free software foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * this program is distributed in the hope that it will be useful, | ||
| 21 | * but without any warranty; without even the implied warranty of | ||
| 22 | * merchantability or fitness for a particular purpose. see the | ||
| 23 | * gnu general public license for more details. | ||
| 24 | * | ||
| 25 | * you should have received a copy of the gnu general public license | ||
| 26 | * along with this program; see the file copying. | ||
| 27 | * if not, write to the free software foundation, | ||
| 28 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _MEM_MAP_518_H_ | ||
| 32 | #define _MEM_MAP_518_H_ | ||
| 33 | |||
| 34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | ||
| 35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | ||
| 36 | |||
| 37 | /* Async Memory Banks */ | ||
| 38 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | ||
| 39 | #define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ | ||
| 40 | #define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ | ||
| 41 | #define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ | ||
| 42 | #define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ | ||
| 43 | #define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ | ||
| 44 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ | ||
| 45 | #define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ | ||
| 46 | |||
| 47 | /* Boot ROM Memory */ | ||
| 48 | |||
| 49 | #define BOOT_ROM_START 0xEF000000 | ||
| 50 | #define BOOT_ROM_LENGTH 0x8000 | ||
| 51 | |||
| 52 | /* Level 1 Memory */ | ||
| 53 | |||
| 54 | /* Memory Map for ADSP-BF518/6/4/2 processors */ | ||
| 55 | |||
| 56 | #ifdef CONFIG_BFIN_ICACHE | ||
| 57 | #define BFIN_ICACHESIZE (16 * 1024) | ||
| 58 | #else | ||
| 59 | #define BFIN_ICACHESIZE (0) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #define L1_CODE_START 0xFFA00000 | ||
| 63 | #define L1_DATA_A_START 0xFF800000 | ||
| 64 | #define L1_DATA_B_START 0xFF900000 | ||
| 65 | |||
| 66 | #define L1_CODE_LENGTH 0xC000 | ||
| 67 | |||
| 68 | #ifdef CONFIG_BFIN_DCACHE | ||
| 69 | |||
| 70 | #ifdef CONFIG_BFIN_DCACHE_BANKA | ||
| 71 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | ||
| 72 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | ||
| 73 | #define L1_DATA_B_LENGTH 0x8000 | ||
| 74 | #define BFIN_DCACHESIZE (16 * 1024) | ||
| 75 | #define BFIN_DSUPBANKS 1 | ||
| 76 | #else | ||
| 77 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | ||
| 78 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | ||
| 79 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | ||
| 80 | #define BFIN_DCACHESIZE (32 * 1024) | ||
| 81 | #define BFIN_DSUPBANKS 2 | ||
| 82 | #endif | ||
| 83 | |||
| 84 | #else | ||
| 85 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | ||
| 86 | #define L1_DATA_A_LENGTH 0x8000 | ||
| 87 | #define L1_DATA_B_LENGTH 0x8000 | ||
| 88 | #define BFIN_DCACHESIZE 0 | ||
| 89 | #define BFIN_DSUPBANKS 0 | ||
| 90 | #endif /*CONFIG_BFIN_DCACHE */ | ||
| 91 | |||
| 92 | /* Level 2 Memory - none */ | ||
| 93 | |||
| 94 | #define L2_START 0 | ||
| 95 | #define L2_LENGTH 0 | ||
| 96 | |||
| 97 | /* Scratch Pad Memory */ | ||
| 98 | |||
| 99 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 100 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 101 | |||
| 102 | #define GET_PDA_SAFE(preg) \ | ||
| 103 | preg.l = _cpu_pda; \ | ||
| 104 | preg.h = _cpu_pda; | ||
| 105 | |||
| 106 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 107 | |||
| 108 | #endif /* _MEM_MAP_518_H_ */ | ||
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h new file mode 100644 index 000000000000..ac16d54734d4 --- /dev/null +++ b/arch/blackfin/mach-bf518/include/mach/portmux.h | |||
| @@ -0,0 +1,188 @@ | |||
| 1 | #ifndef _MACH_PORTMUX_H_ | ||
| 2 | #define _MACH_PORTMUX_H_ | ||
| 3 | |||
| 4 | #define MAX_RESOURCES MAX_BLACKFIN_GPIOS | ||
| 5 | |||
| 6 | /* EMAC MII/RMII Port Mux */ | ||
| 7 | #define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) | ||
| 8 | #define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) | ||
| 9 | #define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) | ||
| 10 | #define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) | ||
| 11 | #define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) | ||
| 12 | #define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) | ||
| 13 | #define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) | ||
| 14 | |||
| 15 | #define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) | ||
| 16 | #define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) | ||
| 17 | #define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) | ||
| 18 | #define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) | ||
| 19 | #define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) | ||
| 20 | #define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) | ||
| 21 | #define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) | ||
| 22 | #define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) | ||
| 23 | #define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) | ||
| 24 | #define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) | ||
| 25 | #define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) | ||
| 26 | |||
| 27 | #define P_MII0 {\ | ||
| 28 | P_MII0_ETxD0, \ | ||
| 29 | P_MII0_ETxD1, \ | ||
| 30 | P_MII0_ETxD2, \ | ||
| 31 | P_MII0_ETxD3, \ | ||
| 32 | P_MII0_ETxEN, \ | ||
| 33 | P_MII0_TxCLK, \ | ||
| 34 | P_MII0_PHYINT, \ | ||
| 35 | P_MII0_COL, \ | ||
| 36 | P_MII0_ERxD0, \ | ||
| 37 | P_MII0_ERxD1, \ | ||
| 38 | P_MII0_ERxD2, \ | ||
| 39 | P_MII0_ERxD3, \ | ||
| 40 | P_MII0_ERxDV, \ | ||
| 41 | P_MII0_ERxCLK, \ | ||
| 42 | P_MII0_ERxER, \ | ||
| 43 | P_MII0_CRS, \ | ||
| 44 | P_MII0_MDC, \ | ||
| 45 | P_MII0_MDIO, 0} | ||
| 46 | |||
| 47 | #define P_RMII0 {\ | ||
| 48 | P_MII0_ETxD0, \ | ||
| 49 | P_MII0_ETxD1, \ | ||
| 50 | P_MII0_ETxEN, \ | ||
| 51 | P_MII0_ERxD0, \ | ||
| 52 | P_MII0_ERxD1, \ | ||
| 53 | P_MII0_ERxER, \ | ||
| 54 | P_MII0_TxCLK, \ | ||
| 55 | P_MII0_PHYINT, \ | ||
| 56 | P_MII0_CRS, \ | ||
| 57 | P_MII0_MDC, \ | ||
| 58 | P_MII0_MDIO, 0} | ||
| 59 | |||
| 60 | /* PPI Port Mux */ | ||
| 61 | #define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) | ||
| 62 | #define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) | ||
| 63 | #define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) | ||
| 64 | #define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) | ||
| 65 | #define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) | ||
| 66 | #define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) | ||
| 67 | #define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) | ||
| 68 | #define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) | ||
| 69 | #define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) | ||
| 70 | #define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) | ||
| 71 | #define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) | ||
| 72 | #define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) | ||
| 73 | #define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) | ||
| 74 | #define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) | ||
| 75 | #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) | ||
| 76 | #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) | ||
| 77 | |||
| 78 | #define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) | ||
| 79 | #define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) | ||
| 80 | #define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) | ||
| 81 | #define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) | ||
| 82 | |||
| 83 | /* SPI Port Mux */ | ||
| 84 | #define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) | ||
| 85 | #define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) | ||
| 86 | #define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) | ||
| 87 | #define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) | ||
| 88 | |||
| 89 | #define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) | ||
| 90 | #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) | ||
| 91 | #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) | ||
| 92 | #define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2)) | ||
| 93 | #define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) | ||
| 94 | |||
| 95 | #define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) | ||
| 96 | #define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) | ||
| 97 | #define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) | ||
| 98 | #define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) | ||
| 99 | |||
| 100 | #define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2)) | ||
| 101 | #define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) | ||
| 102 | #define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2)) | ||
| 103 | #define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2)) | ||
| 104 | #define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) | ||
| 105 | |||
| 106 | /* SPORT Port Mux */ | ||
| 107 | #define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) | ||
| 108 | #define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) | ||
| 109 | #define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) | ||
| 110 | #define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) | ||
| 111 | #define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) | ||
| 112 | #define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) | ||
| 113 | #define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) | ||
| 114 | #define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) | ||
| 115 | |||
| 116 | #define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) | ||
| 117 | #define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) | ||
| 118 | #define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) | ||
| 119 | #define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) | ||
| 120 | #define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) | ||
| 121 | #define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) | ||
| 122 | #define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) | ||
| 123 | #define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) | ||
| 124 | |||
| 125 | /* UART Port Mux */ | ||
| 126 | #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) | ||
| 127 | #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) | ||
| 128 | |||
| 129 | #define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) | ||
| 130 | #define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) | ||
| 131 | |||
| 132 | /* Timer */ | ||
| 133 | #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) | ||
| 134 | #define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) | ||
| 135 | #define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) | ||
| 136 | #define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) | ||
| 137 | #define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) | ||
| 138 | #define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2)) | ||
| 139 | #define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) | ||
| 140 | #define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2)) | ||
| 141 | #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2)) | ||
| 142 | |||
| 143 | /* DMA */ | ||
| 144 | #define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1)) | ||
| 145 | #define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) | ||
| 146 | |||
| 147 | /* TWI */ | ||
| 148 | #define P_TWI0_SCL (P_DONTCARE) | ||
| 149 | #define P_TWI0_SDA (P_DONTCARE) | ||
| 150 | |||
| 151 | /* PWM */ | ||
| 152 | #define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) | ||
| 153 | #define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) | ||
| 154 | #define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) | ||
| 155 | #define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) | ||
| 156 | #define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) | ||
| 157 | #define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) | ||
| 158 | #define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) | ||
| 159 | |||
| 160 | #define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) | ||
| 161 | #define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) | ||
| 162 | #define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) | ||
| 163 | #define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) | ||
| 164 | #define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) | ||
| 165 | #define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) | ||
| 166 | #define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) | ||
| 167 | |||
| 168 | #define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) | ||
| 169 | |||
| 170 | /* RSI */ | ||
| 171 | #define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) | ||
| 172 | #define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) | ||
| 173 | #define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) | ||
| 174 | #define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) | ||
| 175 | #define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2)) | ||
| 176 | #define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2)) | ||
| 177 | #define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) | ||
| 178 | #define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) | ||
| 179 | #define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) | ||
| 180 | #define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) | ||
| 181 | |||
| 182 | /* PTP */ | ||
| 183 | #define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) | ||
| 184 | #define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) | ||
| 185 | |||
| 186 | #define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1)) | ||
| 187 | |||
| 188 | #endif /* _MACH_PORTMUX_H_ */ | ||
diff --git a/arch/blackfin/mach-bf518/ints-priority.c b/arch/blackfin/mach-bf518/ints-priority.c new file mode 100644 index 000000000000..3151fd5501ca --- /dev/null +++ b/arch/blackfin/mach-bf518/ints-priority.c | |||
| @@ -0,0 +1,99 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf518/ints-priority.c | ||
| 3 | * Based on: arch/blackfin/mach-bf527/ints-priority.c | ||
| 4 | * Author: Bryan Wu <cooloney@kernel.org> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: Set up the interrupt priorities | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2007 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/module.h> | ||
| 31 | #include <linux/irq.h> | ||
| 32 | #include <asm/blackfin.h> | ||
| 33 | |||
| 34 | void __init program_IAR(void) | ||
| 35 | { | ||
| 36 | /* Program the IAR0 Register with the configured priority */ | ||
| 37 | bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | | ||
| 38 | ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) | | ||
| 39 | ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) | | ||
| 40 | ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) | | ||
| 41 | ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) | | ||
| 42 | ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) | | ||
| 43 | ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) | | ||
| 44 | ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS)); | ||
| 45 | |||
| 46 | |||
| 47 | bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | | ||
| 48 | ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) | | ||
| 49 | ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) | | ||
| 50 | ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) | | ||
| 51 | ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) | | ||
| 52 | ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) | | ||
| 53 | ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS)); | ||
| 54 | |||
| 55 | bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | | ||
| 56 | ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | | ||
| 57 | ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) | | ||
| 58 | ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | | ||
| 59 | ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) | | ||
| 60 | ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) | | ||
| 61 | ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | | ||
| 62 | ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); | ||
| 63 | |||
| 64 | bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | | ||
| 65 | ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | | ||
| 66 | ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) | | ||
| 67 | ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) | | ||
| 68 | ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) | | ||
| 69 | ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) | | ||
| 70 | ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | | ||
| 71 | ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); | ||
| 72 | |||
| 73 | bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | | ||
| 74 | ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | | ||
| 75 | ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | | ||
| 76 | ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | | ||
| 77 | ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) | | ||
| 78 | ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | | ||
| 79 | ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | | ||
| 80 | ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS)); | ||
| 81 | |||
| 82 | bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | | ||
| 83 | ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | | ||
| 84 | ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) | | ||
| 85 | ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) | | ||
| 86 | ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) | | ||
| 87 | ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) | | ||
| 88 | ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) | | ||
| 89 | ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS)); | ||
| 90 | |||
| 91 | bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) | | ||
| 92 | ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) | | ||
| 93 | ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) | | ||
| 94 | ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) | | ||
| 95 | ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) | | ||
| 96 | ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS)); | ||
| 97 | |||
| 98 | SSYNC(); | ||
| 99 | } | ||
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig index 3cde4beeb214..8438ec6d6679 100644 --- a/arch/blackfin/mach-bf527/Kconfig +++ b/arch/blackfin/mach-bf527/Kconfig | |||
| @@ -168,29 +168,29 @@ config IRQ_MAC_TX | |||
| 168 | config IRQ_PORTH_INTB | 168 | config IRQ_PORTH_INTB |
| 169 | int "IRQ_PORTH_INTB" | 169 | int "IRQ_PORTH_INTB" |
| 170 | default 11 | 170 | default 11 |
| 171 | config IRQ_TMR0 | 171 | config IRQ_TIMER0 |
| 172 | int "IRQ_TMR0" | 172 | int "IRQ_TIMER0" |
| 173 | default 12 | 173 | default 8 |
| 174 | config IRQ_TMR1 | 174 | config IRQ_TIMER1 |
| 175 | int "IRQ_TMR1" | 175 | int "IRQ_TIMER1" |
| 176 | default 12 | 176 | default 12 |
| 177 | config IRQ_TMR2 | 177 | config IRQ_TIMER2 |
| 178 | int "IRQ_TMR2" | 178 | int "IRQ_TIMER2" |
| 179 | default 12 | 179 | default 12 |
| 180 | config IRQ_TMR3 | 180 | config IRQ_TIMER3 |
| 181 | int "IRQ_TMR3" | 181 | int "IRQ_TIMER3" |
| 182 | default 12 | 182 | default 12 |
| 183 | config IRQ_TMR4 | 183 | config IRQ_TIMER4 |
| 184 | int "IRQ_TMR4" | 184 | int "IRQ_TIMER4" |
| 185 | default 12 | 185 | default 12 |
| 186 | config IRQ_TMR5 | 186 | config IRQ_TIMER5 |
| 187 | int "IRQ_TMR5" | 187 | int "IRQ_TIMER5" |
| 188 | default 12 | 188 | default 12 |
| 189 | config IRQ_TMR6 | 189 | config IRQ_TIMER6 |
| 190 | int "IRQ_TMR6" | 190 | int "IRQ_TIMER6" |
| 191 | default 12 | 191 | default 12 |
| 192 | config IRQ_TMR7 | 192 | config IRQ_TIMER7 |
| 193 | int "IRQ_TMR7" | 193 | int "IRQ_TIMER7" |
| 194 | default 12 | 194 | default 12 |
| 195 | config IRQ_PORTG_INTA | 195 | config IRQ_PORTG_INTA |
| 196 | int "IRQ_PORTG_INTA" | 196 | int "IRQ_PORTG_INTA" |
diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile index 4eddb580319c..4a6cdafab8ce 100644 --- a/arch/blackfin/mach-bf527/Makefile +++ b/arch/blackfin/mach-bf527/Makefile | |||
| @@ -2,6 +2,4 @@ | |||
| 2 | # arch/blackfin/mach-bf527/Makefile | 2 | # arch/blackfin/mach-bf527/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | extra-y := head.o | ||
| 6 | |||
| 7 | obj-y := ints-priority.o dma.o | 5 | obj-y := ints-priority.o dma.o |
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 9ea440bbb13d..a2c3578f4b6c 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c | |||
| @@ -61,51 +61,40 @@ const char bfin_board_name[] = "Bluetechnix CM-BF527"; | |||
| 61 | * Driver needs to know address, irq and flag pin. | 61 | * Driver needs to know address, irq and flag pin. |
| 62 | */ | 62 | */ |
| 63 | 63 | ||
| 64 | #define ISP1761_BASE 0x203C0000 | ||
| 65 | #define ISP1761_IRQ IRQ_PF7 | ||
| 66 | |||
| 67 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | 64 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
| 68 | static struct resource bfin_isp1761_resources[] = { | 65 | #include <linux/usb/isp1760.h> |
| 66 | static struct resource bfin_isp1760_resources[] = { | ||
| 69 | [0] = { | 67 | [0] = { |
| 70 | .name = "isp1761-regs", | 68 | .start = 0x203C0000, |
| 71 | .start = ISP1761_BASE + 0x00000000, | 69 | .end = 0x203C0000 + 0x000fffff, |
| 72 | .end = ISP1761_BASE + 0x000fffff, | ||
| 73 | .flags = IORESOURCE_MEM, | 70 | .flags = IORESOURCE_MEM, |
| 74 | }, | 71 | }, |
| 75 | [1] = { | 72 | [1] = { |
| 76 | .start = ISP1761_IRQ, | 73 | .start = IRQ_PF7, |
| 77 | .end = ISP1761_IRQ, | 74 | .end = IRQ_PF7, |
| 78 | .flags = IORESOURCE_IRQ, | 75 | .flags = IORESOURCE_IRQ, |
| 79 | }, | 76 | }, |
| 80 | }; | 77 | }; |
| 81 | 78 | ||
| 82 | static struct platform_device bfin_isp1761_device = { | 79 | static struct isp1760_platform_data isp1760_priv = { |
| 83 | .name = "isp1761", | 80 | .is_isp1761 = 0, |
| 84 | .id = 0, | 81 | .port1_disable = 0, |
| 85 | .num_resources = ARRAY_SIZE(bfin_isp1761_resources), | 82 | .bus_width_16 = 1, |
| 86 | .resource = bfin_isp1761_resources, | 83 | .port1_otg = 0, |
| 84 | .analog_oc = 0, | ||
| 85 | .dack_polarity_high = 0, | ||
| 86 | .dreq_polarity_high = 0, | ||
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| 89 | static struct platform_device *bfin_isp1761_devices[] = { | 89 | static struct platform_device bfin_isp1760_device = { |
| 90 | &bfin_isp1761_device, | 90 | .name = "isp1760-hcd", |
| 91 | .id = 0, | ||
| 92 | .dev = { | ||
| 93 | .platform_data = &isp1760_priv, | ||
| 94 | }, | ||
| 95 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | ||
| 96 | .resource = bfin_isp1760_resources, | ||
| 91 | }; | 97 | }; |
| 92 | |||
| 93 | int __init bfin_isp1761_init(void) | ||
| 94 | { | ||
| 95 | unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); | ||
| 96 | |||
| 97 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 98 | set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); | ||
| 99 | |||
| 100 | return platform_add_devices(bfin_isp1761_devices, num_devices); | ||
| 101 | } | ||
| 102 | |||
| 103 | void __exit bfin_isp1761_exit(void) | ||
| 104 | { | ||
| 105 | platform_device_unregister(&bfin_isp1761_device); | ||
| 106 | } | ||
| 107 | |||
| 108 | arch_initcall(bfin_isp1761_init); | ||
| 109 | #endif | 98 | #endif |
| 110 | 99 | ||
| 111 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) | 100 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) |
| @@ -132,8 +121,8 @@ static struct musb_hdrc_config musb_config = { | |||
| 132 | .dyn_fifo = 0, | 121 | .dyn_fifo = 0, |
| 133 | .soft_con = 1, | 122 | .soft_con = 1, |
| 134 | .dma = 1, | 123 | .dma = 1, |
| 135 | .num_eps = 7, | 124 | .num_eps = 8, |
| 136 | .dma_channels = 7, | 125 | .dma_channels = 8, |
| 137 | .gpio_vrsel = GPIO_PF11, | 126 | .gpio_vrsel = GPIO_PF11, |
| 138 | }; | 127 | }; |
| 139 | 128 | ||
| @@ -728,30 +717,59 @@ static struct platform_device bfin_uart_device = { | |||
| 728 | #endif | 717 | #endif |
| 729 | 718 | ||
| 730 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 719 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 731 | static struct resource bfin_sir_resources[] = { | ||
| 732 | #ifdef CONFIG_BFIN_SIR0 | 720 | #ifdef CONFIG_BFIN_SIR0 |
| 721 | static struct resource bfin_sir0_resources[] = { | ||
| 733 | { | 722 | { |
| 734 | .start = 0xFFC00400, | 723 | .start = 0xFFC00400, |
| 735 | .end = 0xFFC004FF, | 724 | .end = 0xFFC004FF, |
| 736 | .flags = IORESOURCE_MEM, | 725 | .flags = IORESOURCE_MEM, |
| 737 | }, | 726 | }, |
| 727 | { | ||
| 728 | .start = IRQ_UART0_RX, | ||
| 729 | .end = IRQ_UART0_RX+1, | ||
| 730 | .flags = IORESOURCE_IRQ, | ||
| 731 | }, | ||
| 732 | { | ||
| 733 | .start = CH_UART0_RX, | ||
| 734 | .end = CH_UART0_RX+1, | ||
| 735 | .flags = IORESOURCE_DMA, | ||
| 736 | }, | ||
| 737 | }; | ||
| 738 | |||
| 739 | static struct platform_device bfin_sir0_device = { | ||
| 740 | .name = "bfin_sir", | ||
| 741 | .id = 0, | ||
| 742 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 743 | .resource = bfin_sir0_resources, | ||
| 744 | }; | ||
| 738 | #endif | 745 | #endif |
| 739 | #ifdef CONFIG_BFIN_SIR1 | 746 | #ifdef CONFIG_BFIN_SIR1 |
| 747 | static struct resource bfin_sir1_resources[] = { | ||
| 740 | { | 748 | { |
| 741 | .start = 0xFFC02000, | 749 | .start = 0xFFC02000, |
| 742 | .end = 0xFFC020FF, | 750 | .end = 0xFFC020FF, |
| 743 | .flags = IORESOURCE_MEM, | 751 | .flags = IORESOURCE_MEM, |
| 744 | }, | 752 | }, |
| 745 | #endif | 753 | { |
| 754 | .start = IRQ_UART1_RX, | ||
| 755 | .end = IRQ_UART1_RX+1, | ||
| 756 | .flags = IORESOURCE_IRQ, | ||
| 757 | }, | ||
| 758 | { | ||
| 759 | .start = CH_UART1_RX, | ||
| 760 | .end = CH_UART1_RX+1, | ||
| 761 | .flags = IORESOURCE_DMA, | ||
| 762 | }, | ||
| 746 | }; | 763 | }; |
| 747 | 764 | ||
| 748 | static struct platform_device bfin_sir_device = { | 765 | static struct platform_device bfin_sir1_device = { |
| 749 | .name = "bfin_sir", | 766 | .name = "bfin_sir", |
| 750 | .id = 0, | 767 | .id = 1, |
| 751 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 768 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 752 | .resource = bfin_sir_resources, | 769 | .resource = bfin_sir1_resources, |
| 753 | }; | 770 | }; |
| 754 | #endif | 771 | #endif |
| 772 | #endif | ||
| 755 | 773 | ||
| 756 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 774 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 757 | static struct resource bfin_twi0_resource[] = { | 775 | static struct resource bfin_twi0_resource[] = { |
| @@ -885,6 +903,10 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 885 | &isp1362_hcd_device, | 903 | &isp1362_hcd_device, |
| 886 | #endif | 904 | #endif |
| 887 | 905 | ||
| 906 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | ||
| 907 | &bfin_isp1760_device, | ||
| 908 | #endif | ||
| 909 | |||
| 888 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) | 910 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) |
| 889 | &musb_device, | 911 | &musb_device, |
| 890 | #endif | 912 | #endif |
| @@ -918,7 +940,12 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 918 | #endif | 940 | #endif |
| 919 | 941 | ||
| 920 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 942 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 921 | &bfin_sir_device, | 943 | #ifdef CONFIG_BFIN_SIR0 |
| 944 | &bfin_sir0_device, | ||
| 945 | #endif | ||
| 946 | #ifdef CONFIG_BFIN_SIR1 | ||
| 947 | &bfin_sir1_device, | ||
| 948 | #endif | ||
| 922 | #endif | 949 | #endif |
| 923 | 950 | ||
| 924 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 951 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 36c87b6fbdec..0314bd3355eb 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c | |||
| @@ -51,7 +51,7 @@ | |||
| 51 | /* | 51 | /* |
| 52 | * Name the Board for the /proc/cpuinfo | 52 | * Name the Board for the /proc/cpuinfo |
| 53 | */ | 53 | */ |
| 54 | const char bfin_board_name[] = "BF526-EZBRD"; | 54 | const char bfin_board_name[] = "ADI BF526-EZBRD"; |
| 55 | 55 | ||
| 56 | /* | 56 | /* |
| 57 | * Driver needs to know address, irq and flag pin. | 57 | * Driver needs to know address, irq and flag pin. |
| @@ -81,8 +81,8 @@ static struct musb_hdrc_config musb_config = { | |||
| 81 | .dyn_fifo = 0, | 81 | .dyn_fifo = 0, |
| 82 | .soft_con = 1, | 82 | .soft_con = 1, |
| 83 | .dma = 1, | 83 | .dma = 1, |
| 84 | .num_eps = 7, | 84 | .num_eps = 8, |
| 85 | .dma_channels = 7, | 85 | .dma_channels = 8, |
| 86 | .gpio_vrsel = GPIO_PG13, | 86 | .gpio_vrsel = GPIO_PG13, |
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| @@ -288,6 +288,30 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { | |||
| 288 | }; | 288 | }; |
| 289 | #endif | 289 | #endif |
| 290 | 290 | ||
| 291 | #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) | ||
| 292 | #include <linux/spi/ad7879.h> | ||
| 293 | static const struct ad7879_platform_data bfin_ad7879_ts_info = { | ||
| 294 | .model = 7879, /* Model = AD7879 */ | ||
| 295 | .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ | ||
| 296 | .pressure_max = 10000, | ||
| 297 | .pressure_min = 0, | ||
| 298 | .first_conversion_delay = 3, /* wait 512us before do a first conversion */ | ||
| 299 | .acquisition_time = 1, /* 4us acquisition time per sample */ | ||
| 300 | .median = 2, /* do 8 measurements */ | ||
| 301 | .averaging = 1, /* take the average of 4 middle samples */ | ||
| 302 | .pen_down_acc_interval = 255, /* 9.4 ms */ | ||
| 303 | .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */ | ||
| 304 | .gpio_default = 1, /* During initialization set GPIO = HIGH */ | ||
| 305 | }; | ||
| 306 | #endif | ||
| 307 | |||
| 308 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) | ||
| 309 | static struct bfin5xx_spi_chip spi_ad7879_chip_info = { | ||
| 310 | .enable_dma = 0, | ||
| 311 | .bits_per_word = 16, | ||
| 312 | }; | ||
| 313 | #endif | ||
| 314 | |||
| 291 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ | 315 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ |
| 292 | && defined(CONFIG_SND_SOC_WM8731_SPI) | 316 | && defined(CONFIG_SND_SOC_WM8731_SPI) |
| 293 | static struct bfin5xx_spi_chip spi_wm8731_chip_info = { | 317 | static struct bfin5xx_spi_chip spi_wm8731_chip_info = { |
| @@ -386,6 +410,18 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 386 | .controller_data = &spi_ad7877_chip_info, | 410 | .controller_data = &spi_ad7877_chip_info, |
| 387 | }, | 411 | }, |
| 388 | #endif | 412 | #endif |
| 413 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) | ||
| 414 | { | ||
| 415 | .modalias = "ad7879", | ||
| 416 | .platform_data = &bfin_ad7879_ts_info, | ||
| 417 | .irq = IRQ_PG0, | ||
| 418 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ | ||
| 419 | .bus_num = 0, | ||
| 420 | .chip_select = 5, | ||
| 421 | .controller_data = &spi_ad7879_chip_info, | ||
| 422 | .mode = SPI_CPHA | SPI_CPOL, | ||
| 423 | }, | ||
| 424 | #endif | ||
| 389 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ | 425 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ |
| 390 | && defined(CONFIG_SND_SOC_WM8731_SPI) | 426 | && defined(CONFIG_SND_SOC_WM8731_SPI) |
| 391 | { | 427 | { |
| @@ -478,30 +514,59 @@ static struct platform_device bfin_uart_device = { | |||
| 478 | #endif | 514 | #endif |
| 479 | 515 | ||
| 480 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 516 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 481 | static struct resource bfin_sir_resources[] = { | ||
| 482 | #ifdef CONFIG_BFIN_SIR0 | 517 | #ifdef CONFIG_BFIN_SIR0 |
| 518 | static struct resource bfin_sir0_resources[] = { | ||
| 483 | { | 519 | { |
| 484 | .start = 0xFFC00400, | 520 | .start = 0xFFC00400, |
| 485 | .end = 0xFFC004FF, | 521 | .end = 0xFFC004FF, |
| 486 | .flags = IORESOURCE_MEM, | 522 | .flags = IORESOURCE_MEM, |
| 487 | }, | 523 | }, |
| 524 | { | ||
| 525 | .start = IRQ_UART0_RX, | ||
| 526 | .end = IRQ_UART0_RX+1, | ||
| 527 | .flags = IORESOURCE_IRQ, | ||
| 528 | }, | ||
| 529 | { | ||
| 530 | .start = CH_UART0_RX, | ||
| 531 | .end = CH_UART0_RX+1, | ||
| 532 | .flags = IORESOURCE_DMA, | ||
| 533 | }, | ||
| 534 | }; | ||
| 535 | |||
| 536 | static struct platform_device bfin_sir0_device = { | ||
| 537 | .name = "bfin_sir", | ||
| 538 | .id = 0, | ||
| 539 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 540 | .resource = bfin_sir0_resources, | ||
| 541 | }; | ||
| 488 | #endif | 542 | #endif |
| 489 | #ifdef CONFIG_BFIN_SIR1 | 543 | #ifdef CONFIG_BFIN_SIR1 |
| 544 | static struct resource bfin_sir1_resources[] = { | ||
| 490 | { | 545 | { |
| 491 | .start = 0xFFC02000, | 546 | .start = 0xFFC02000, |
| 492 | .end = 0xFFC020FF, | 547 | .end = 0xFFC020FF, |
| 493 | .flags = IORESOURCE_MEM, | 548 | .flags = IORESOURCE_MEM, |
| 494 | }, | 549 | }, |
| 495 | #endif | 550 | { |
| 551 | .start = IRQ_UART1_RX, | ||
| 552 | .end = IRQ_UART1_RX+1, | ||
| 553 | .flags = IORESOURCE_IRQ, | ||
| 554 | }, | ||
| 555 | { | ||
| 556 | .start = CH_UART1_RX, | ||
| 557 | .end = CH_UART1_RX+1, | ||
| 558 | .flags = IORESOURCE_DMA, | ||
| 559 | }, | ||
| 496 | }; | 560 | }; |
| 497 | 561 | ||
| 498 | static struct platform_device bfin_sir_device = { | 562 | static struct platform_device bfin_sir1_device = { |
| 499 | .name = "bfin_sir", | 563 | .name = "bfin_sir", |
| 500 | .id = 0, | 564 | .id = 1, |
| 501 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 565 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 502 | .resource = bfin_sir_resources, | 566 | .resource = bfin_sir1_resources, |
| 503 | }; | 567 | }; |
| 504 | #endif | 568 | #endif |
| 569 | #endif | ||
| 505 | 570 | ||
| 506 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 571 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 507 | static struct resource bfin_twi0_resource[] = { | 572 | static struct resource bfin_twi0_resource[] = { |
| @@ -671,7 +736,12 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 671 | #endif | 736 | #endif |
| 672 | 737 | ||
| 673 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 738 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 674 | &bfin_sir_device, | 739 | #ifdef CONFIG_BFIN_SIR0 |
| 740 | &bfin_sir0_device, | ||
| 741 | #endif | ||
| 742 | #ifdef CONFIG_BFIN_SIR1 | ||
| 743 | &bfin_sir1_device, | ||
| 744 | #endif | ||
| 675 | #endif | 745 | #endif |
| 676 | 746 | ||
| 677 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 747 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 8ee2b744e234..9454fb7b18c3 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c | |||
| @@ -54,57 +54,46 @@ | |||
| 54 | /* | 54 | /* |
| 55 | * Name the Board for the /proc/cpuinfo | 55 | * Name the Board for the /proc/cpuinfo |
| 56 | */ | 56 | */ |
| 57 | const char bfin_board_name[] = "ADDS-BF527-EZKIT"; | 57 | const char bfin_board_name[] = "ADI BF527-EZKIT"; |
| 58 | 58 | ||
| 59 | /* | 59 | /* |
| 60 | * Driver needs to know address, irq and flag pin. | 60 | * Driver needs to know address, irq and flag pin. |
| 61 | */ | 61 | */ |
| 62 | 62 | ||
| 63 | #define ISP1761_BASE 0x203C0000 | ||
| 64 | #define ISP1761_IRQ IRQ_PF7 | ||
| 65 | |||
| 66 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | 63 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
| 67 | static struct resource bfin_isp1761_resources[] = { | 64 | #include <linux/usb/isp1760.h> |
| 65 | static struct resource bfin_isp1760_resources[] = { | ||
| 68 | [0] = { | 66 | [0] = { |
| 69 | .name = "isp1761-regs", | 67 | .start = 0x203C0000, |
| 70 | .start = ISP1761_BASE + 0x00000000, | 68 | .end = 0x203C0000 + 0x000fffff, |
| 71 | .end = ISP1761_BASE + 0x000fffff, | ||
| 72 | .flags = IORESOURCE_MEM, | 69 | .flags = IORESOURCE_MEM, |
| 73 | }, | 70 | }, |
| 74 | [1] = { | 71 | [1] = { |
| 75 | .start = ISP1761_IRQ, | 72 | .start = IRQ_PF7, |
| 76 | .end = ISP1761_IRQ, | 73 | .end = IRQ_PF7, |
| 77 | .flags = IORESOURCE_IRQ, | 74 | .flags = IORESOURCE_IRQ, |
| 78 | }, | 75 | }, |
| 79 | }; | 76 | }; |
| 80 | 77 | ||
| 81 | static struct platform_device bfin_isp1761_device = { | 78 | static struct isp1760_platform_data isp1760_priv = { |
| 82 | .name = "isp1761", | 79 | .is_isp1761 = 0, |
| 83 | .id = 0, | 80 | .port1_disable = 0, |
| 84 | .num_resources = ARRAY_SIZE(bfin_isp1761_resources), | 81 | .bus_width_16 = 1, |
| 85 | .resource = bfin_isp1761_resources, | 82 | .port1_otg = 0, |
| 83 | .analog_oc = 0, | ||
| 84 | .dack_polarity_high = 0, | ||
| 85 | .dreq_polarity_high = 0, | ||
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | static struct platform_device *bfin_isp1761_devices[] = { | 88 | static struct platform_device bfin_isp1760_device = { |
| 89 | &bfin_isp1761_device, | 89 | .name = "isp1760-hcd", |
| 90 | .id = 0, | ||
| 91 | .dev = { | ||
| 92 | .platform_data = &isp1760_priv, | ||
| 93 | }, | ||
| 94 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | ||
| 95 | .resource = bfin_isp1760_resources, | ||
| 90 | }; | 96 | }; |
| 91 | |||
| 92 | int __init bfin_isp1761_init(void) | ||
| 93 | { | ||
| 94 | unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); | ||
| 95 | |||
| 96 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 97 | set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); | ||
| 98 | |||
| 99 | return platform_add_devices(bfin_isp1761_devices, num_devices); | ||
| 100 | } | ||
| 101 | |||
| 102 | void __exit bfin_isp1761_exit(void) | ||
| 103 | { | ||
| 104 | platform_device_unregister(&bfin_isp1761_device); | ||
| 105 | } | ||
| 106 | |||
| 107 | arch_initcall(bfin_isp1761_init); | ||
| 108 | #endif | 97 | #endif |
| 109 | 98 | ||
| 110 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) | 99 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) |
| @@ -131,8 +120,8 @@ static struct musb_hdrc_config musb_config = { | |||
| 131 | .dyn_fifo = 0, | 120 | .dyn_fifo = 0, |
| 132 | .soft_con = 1, | 121 | .soft_con = 1, |
| 133 | .dma = 1, | 122 | .dma = 1, |
| 134 | .num_eps = 7, | 123 | .num_eps = 8, |
| 135 | .dma_channels = 7, | 124 | .dma_channels = 8, |
| 136 | .gpio_vrsel = GPIO_PG13, | 125 | .gpio_vrsel = GPIO_PG13, |
| 137 | }; | 126 | }; |
| 138 | 127 | ||
| @@ -515,13 +504,6 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |||
| 515 | }; | 504 | }; |
| 516 | #endif | 505 | #endif |
| 517 | 506 | ||
| 518 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | ||
| 519 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | ||
| 520 | .enable_dma = 1, | ||
| 521 | .bits_per_word = 8, | ||
| 522 | }; | ||
| 523 | #endif | ||
| 524 | |||
| 525 | #if defined(CONFIG_PBX) | 507 | #if defined(CONFIG_PBX) |
| 526 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | 508 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { |
| 527 | .ctl_reg = 0x4, /* send zero */ | 509 | .ctl_reg = 0x4, /* send zero */ |
| @@ -552,6 +534,30 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = { | |||
| 552 | }; | 534 | }; |
| 553 | #endif | 535 | #endif |
| 554 | 536 | ||
| 537 | #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) | ||
| 538 | #include <linux/spi/ad7879.h> | ||
| 539 | static const struct ad7879_platform_data bfin_ad7879_ts_info = { | ||
| 540 | .model = 7879, /* Model = AD7879 */ | ||
| 541 | .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ | ||
| 542 | .pressure_max = 10000, | ||
| 543 | .pressure_min = 0, | ||
| 544 | .first_conversion_delay = 3, /* wait 512us before do a first conversion */ | ||
| 545 | .acquisition_time = 1, /* 4us acquisition time per sample */ | ||
| 546 | .median = 2, /* do 8 measurements */ | ||
| 547 | .averaging = 1, /* take the average of 4 middle samples */ | ||
| 548 | .pen_down_acc_interval = 255, /* 9.4 ms */ | ||
| 549 | .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */ | ||
| 550 | .gpio_default = 1, /* During initialization set GPIO = HIGH */ | ||
| 551 | }; | ||
| 552 | #endif | ||
| 553 | |||
| 554 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) | ||
| 555 | static struct bfin5xx_spi_chip spi_ad7879_chip_info = { | ||
| 556 | .enable_dma = 0, | ||
| 557 | .bits_per_word = 16, | ||
| 558 | }; | ||
| 559 | #endif | ||
| 560 | |||
| 555 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ | 561 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ |
| 556 | && defined(CONFIG_SND_SOC_WM8731_SPI) | 562 | && defined(CONFIG_SND_SOC_WM8731_SPI) |
| 557 | static struct bfin5xx_spi_chip spi_wm8731_chip_info = { | 563 | static struct bfin5xx_spi_chip spi_wm8731_chip_info = { |
| @@ -613,26 +619,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 613 | .controller_data = &ad9960_spi_chip_info, | 619 | .controller_data = &ad9960_spi_chip_info, |
| 614 | }, | 620 | }, |
| 615 | #endif | 621 | #endif |
| 616 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | ||
| 617 | { | ||
| 618 | .modalias = "spi_mmc_dummy", | ||
| 619 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 620 | .bus_num = 0, | ||
| 621 | .chip_select = 0, | ||
| 622 | .platform_data = NULL, | ||
| 623 | .controller_data = &spi_mmc_chip_info, | ||
| 624 | .mode = SPI_MODE_3, | ||
| 625 | }, | ||
| 626 | { | ||
| 627 | .modalias = "spi_mmc", | ||
| 628 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 629 | .bus_num = 0, | ||
| 630 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | ||
| 631 | .platform_data = NULL, | ||
| 632 | .controller_data = &spi_mmc_chip_info, | ||
| 633 | .mode = SPI_MODE_3, | ||
| 634 | }, | ||
| 635 | #endif | ||
| 636 | #if defined(CONFIG_PBX) | 622 | #if defined(CONFIG_PBX) |
| 637 | { | 623 | { |
| 638 | .modalias = "fxs-spi", | 624 | .modalias = "fxs-spi", |
| @@ -662,6 +648,18 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 662 | .controller_data = &spi_ad7877_chip_info, | 648 | .controller_data = &spi_ad7877_chip_info, |
| 663 | }, | 649 | }, |
| 664 | #endif | 650 | #endif |
| 651 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) | ||
| 652 | { | ||
| 653 | .modalias = "ad7879", | ||
| 654 | .platform_data = &bfin_ad7879_ts_info, | ||
| 655 | .irq = IRQ_PF8, | ||
| 656 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ | ||
| 657 | .bus_num = 0, | ||
| 658 | .chip_select = 3, | ||
| 659 | .controller_data = &spi_ad7879_chip_info, | ||
| 660 | .mode = SPI_CPHA | SPI_CPOL, | ||
| 661 | }, | ||
| 662 | #endif | ||
| 665 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ | 663 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ |
| 666 | && defined(CONFIG_SND_SOC_WM8731_SPI) | 664 | && defined(CONFIG_SND_SOC_WM8731_SPI) |
| 667 | { | 665 | { |
| @@ -756,30 +754,59 @@ static struct platform_device bfin_uart_device = { | |||
| 756 | #endif | 754 | #endif |
| 757 | 755 | ||
| 758 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 756 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 759 | static struct resource bfin_sir_resources[] = { | ||
| 760 | #ifdef CONFIG_BFIN_SIR0 | 757 | #ifdef CONFIG_BFIN_SIR0 |
| 758 | static struct resource bfin_sir0_resources[] = { | ||
| 761 | { | 759 | { |
| 762 | .start = 0xFFC00400, | 760 | .start = 0xFFC00400, |
| 763 | .end = 0xFFC004FF, | 761 | .end = 0xFFC004FF, |
| 764 | .flags = IORESOURCE_MEM, | 762 | .flags = IORESOURCE_MEM, |
| 765 | }, | 763 | }, |
| 764 | { | ||
| 765 | .start = IRQ_UART0_RX, | ||
| 766 | .end = IRQ_UART0_RX+1, | ||
| 767 | .flags = IORESOURCE_IRQ, | ||
| 768 | }, | ||
| 769 | { | ||
| 770 | .start = CH_UART0_RX, | ||
| 771 | .end = CH_UART0_RX+1, | ||
| 772 | .flags = IORESOURCE_DMA, | ||
| 773 | }, | ||
| 774 | }; | ||
| 775 | |||
| 776 | static struct platform_device bfin_sir0_device = { | ||
| 777 | .name = "bfin_sir", | ||
| 778 | .id = 0, | ||
| 779 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 780 | .resource = bfin_sir0_resources, | ||
| 781 | }; | ||
| 766 | #endif | 782 | #endif |
| 767 | #ifdef CONFIG_BFIN_SIR1 | 783 | #ifdef CONFIG_BFIN_SIR1 |
| 784 | static struct resource bfin_sir1_resources[] = { | ||
| 768 | { | 785 | { |
| 769 | .start = 0xFFC02000, | 786 | .start = 0xFFC02000, |
| 770 | .end = 0xFFC020FF, | 787 | .end = 0xFFC020FF, |
| 771 | .flags = IORESOURCE_MEM, | 788 | .flags = IORESOURCE_MEM, |
| 772 | }, | 789 | }, |
| 773 | #endif | 790 | { |
| 791 | .start = IRQ_UART1_RX, | ||
| 792 | .end = IRQ_UART1_RX+1, | ||
| 793 | .flags = IORESOURCE_IRQ, | ||
| 794 | }, | ||
| 795 | { | ||
| 796 | .start = CH_UART1_RX, | ||
| 797 | .end = CH_UART1_RX+1, | ||
| 798 | .flags = IORESOURCE_DMA, | ||
| 799 | }, | ||
| 774 | }; | 800 | }; |
| 775 | 801 | ||
| 776 | static struct platform_device bfin_sir_device = { | 802 | static struct platform_device bfin_sir1_device = { |
| 777 | .name = "bfin_sir", | 803 | .name = "bfin_sir", |
| 778 | .id = 0, | 804 | .id = 1, |
| 779 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 805 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 780 | .resource = bfin_sir_resources, | 806 | .resource = bfin_sir1_resources, |
| 781 | }; | 807 | }; |
| 782 | #endif | 808 | #endif |
| 809 | #endif | ||
| 783 | 810 | ||
| 784 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 811 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 785 | static struct resource bfin_twi0_resource[] = { | 812 | static struct resource bfin_twi0_resource[] = { |
| @@ -944,6 +971,10 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 944 | &isp1362_hcd_device, | 971 | &isp1362_hcd_device, |
| 945 | #endif | 972 | #endif |
| 946 | 973 | ||
| 974 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | ||
| 975 | &bfin_isp1760_device, | ||
| 976 | #endif | ||
| 977 | |||
| 947 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) | 978 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) |
| 948 | &musb_device, | 979 | &musb_device, |
| 949 | #endif | 980 | #endif |
| @@ -985,7 +1016,12 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 985 | #endif | 1016 | #endif |
| 986 | 1017 | ||
| 987 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 1018 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 988 | &bfin_sir_device, | 1019 | #ifdef CONFIG_BFIN_SIR0 |
| 1020 | &bfin_sir0_device, | ||
| 1021 | #endif | ||
| 1022 | #ifdef CONFIG_BFIN_SIR1 | ||
| 1023 | &bfin_sir1_device, | ||
| 1024 | #endif | ||
| 989 | #endif | 1025 | #endif |
| 990 | 1026 | ||
| 991 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 1027 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c index dfd080cda787..231877578243 100644 --- a/arch/blackfin/mach-bf527/dma.c +++ b/arch/blackfin/mach-bf527/dma.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <asm/blackfin.h> | 31 | #include <asm/blackfin.h> |
| 32 | #include <asm/dma.h> | 32 | #include <asm/dma.h> |
| 33 | 33 | ||
| 34 | struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { | 34 | struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { |
| 35 | (struct dma_register *) DMA0_NEXT_DESC_PTR, | 35 | (struct dma_register *) DMA0_NEXT_DESC_PTR, |
| 36 | (struct dma_register *) DMA1_NEXT_DESC_PTR, | 36 | (struct dma_register *) DMA1_NEXT_DESC_PTR, |
| 37 | (struct dma_register *) DMA2_NEXT_DESC_PTR, | 37 | (struct dma_register *) DMA2_NEXT_DESC_PTR, |
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S deleted file mode 100644 index 0eb1da85db73..000000000000 --- a/arch/blackfin/mach-bf527/head.S +++ /dev/null | |||
| @@ -1,146 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf527/head.S | ||
| 3 | * Based on: arch/blackfin/mach-bf533/head.S | ||
| 4 | * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne | ||
| 5 | * | ||
| 6 | * Created: 1998 | ||
| 7 | * Description: Startup code for Blackfin BF537 | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2007 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/linkage.h> | ||
| 31 | #include <linux/init.h> | ||
| 32 | #include <asm/blackfin.h> | ||
| 33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 34 | #include <asm/clocks.h> | ||
| 35 | #include <mach/mem_init.h> | ||
| 36 | #endif | ||
| 37 | |||
| 38 | .section .l1.text | ||
| 39 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 40 | ENTRY(_start_dma_code) | ||
| 41 | |||
| 42 | /* Enable PHY CLK buffer output */ | ||
| 43 | p0.h = hi(VR_CTL); | ||
| 44 | p0.l = lo(VR_CTL); | ||
| 45 | r0.l = w[p0]; | ||
| 46 | bitset(r0, 14); | ||
| 47 | w[p0] = r0.l; | ||
| 48 | ssync; | ||
| 49 | |||
| 50 | p0.h = hi(SIC_IWR0); | ||
| 51 | p0.l = lo(SIC_IWR0); | ||
| 52 | r0.l = 0x1; | ||
| 53 | r0.h = 0x0; | ||
| 54 | [p0] = r0; | ||
| 55 | SSYNC; | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Set PLL_CTL | ||
| 59 | * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors | ||
| 60 | * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK | ||
| 61 | * - [7] = output delay (add 200ps of delay to mem signals) | ||
| 62 | * - [6] = input delay (add 200ps of input delay to mem signals) | ||
| 63 | * - [5] = PDWN : 1=All Clocks off | ||
| 64 | * - [3] = STOPCK : 1=Core Clock off | ||
| 65 | * - [1] = PLL_OFF : 1=Disable Power to PLL | ||
| 66 | * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL | ||
| 67 | * all other bits set to zero | ||
| 68 | */ | ||
| 69 | |||
| 70 | p0.h = hi(PLL_LOCKCNT); | ||
| 71 | p0.l = lo(PLL_LOCKCNT); | ||
| 72 | r0 = 0x300(Z); | ||
| 73 | w[p0] = r0.l; | ||
| 74 | ssync; | ||
| 75 | |||
| 76 | P2.H = hi(EBIU_SDGCTL); | ||
| 77 | P2.L = lo(EBIU_SDGCTL); | ||
| 78 | R0 = [P2]; | ||
| 79 | BITSET (R0, 24); | ||
| 80 | [P2] = R0; | ||
| 81 | SSYNC; | ||
| 82 | |||
| 83 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ | ||
| 84 | r0 = r0 << 9; /* Shift it over, */ | ||
| 85 | r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ | ||
| 86 | r0 = r1 | r0; | ||
| 87 | r1 = PLL_BYPASS; /* Bypass the PLL? */ | ||
| 88 | r1 = r1 << 8; /* Shift it over */ | ||
| 89 | r0 = r1 | r0; /* add them all together */ | ||
| 90 | #ifdef ANOMALY_05000265 | ||
| 91 | BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */ | ||
| 92 | #endif | ||
| 93 | |||
| 94 | p0.h = hi(PLL_CTL); | ||
| 95 | p0.l = lo(PLL_CTL); /* Load the address */ | ||
| 96 | cli r2; /* Disable interrupts */ | ||
| 97 | ssync; | ||
| 98 | w[p0] = r0.l; /* Set the value */ | ||
| 99 | idle; /* Wait for the PLL to stablize */ | ||
| 100 | sti r2; /* Enable interrupts */ | ||
| 101 | |||
| 102 | .Lcheck_again: | ||
| 103 | p0.h = hi(PLL_STAT); | ||
| 104 | p0.l = lo(PLL_STAT); | ||
| 105 | R0 = W[P0](Z); | ||
| 106 | CC = BITTST(R0,5); | ||
| 107 | if ! CC jump .Lcheck_again; | ||
| 108 | |||
| 109 | /* Configure SCLK & CCLK Dividers */ | ||
| 110 | r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | ||
| 111 | p0.h = hi(PLL_DIV); | ||
| 112 | p0.l = lo(PLL_DIV); | ||
| 113 | w[p0] = r0.l; | ||
| 114 | ssync; | ||
| 115 | |||
| 116 | p0.l = lo(EBIU_SDRRC); | ||
| 117 | p0.h = hi(EBIU_SDRRC); | ||
| 118 | r0 = mem_SDRRC; | ||
| 119 | w[p0] = r0.l; | ||
| 120 | ssync; | ||
| 121 | |||
| 122 | P2.H = hi(EBIU_SDGCTL); | ||
| 123 | P2.L = lo(EBIU_SDGCTL); | ||
| 124 | R0 = [P2]; | ||
| 125 | BITCLR (R0, 24); | ||
| 126 | p0.h = hi(EBIU_SDSTAT); | ||
| 127 | p0.l = lo(EBIU_SDSTAT); | ||
| 128 | r2.l = w[p0]; | ||
| 129 | cc = bittst(r2,3); | ||
| 130 | if !cc jump .Lskip; | ||
| 131 | NOP; | ||
| 132 | BITSET (R0, 23); | ||
| 133 | .Lskip: | ||
| 134 | [P2] = R0; | ||
| 135 | SSYNC; | ||
| 136 | |||
| 137 | R0.L = lo(mem_SDGCTL); | ||
| 138 | R0.H = hi(mem_SDGCTL); | ||
| 139 | R1 = [p2]; | ||
| 140 | R1 = R1 | R0; | ||
| 141 | [P2] = R1; | ||
| 142 | SSYNC; | ||
| 143 | |||
| 144 | RTS; | ||
| 145 | ENDPROC(_start_dma_code) | ||
| 146 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index 62373e61c585..035e8d835058 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 28 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 29 | #define ANOMALY_05000074 (1) | 29 | #define ANOMALY_05000074 (1) |
| 30 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 30 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 31 | #define ANOMALY_05000119 (1) | 31 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
| 32 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 32 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 33 | #define ANOMALY_05000122 (1) | 33 | #define ANOMALY_05000122 (1) |
| 34 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 34 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| @@ -37,8 +37,6 @@ | |||
| 37 | #define ANOMALY_05000265 (1) | 37 | #define ANOMALY_05000265 (1) |
| 38 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 38 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 39 | #define ANOMALY_05000310 (1) | 39 | #define ANOMALY_05000310 (1) |
| 40 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | ||
| 41 | #define ANOMALY_05000312 (ANOMALY_BF527) | ||
| 42 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ | 40 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 43 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) | 41 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) |
| 44 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | 42 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
| @@ -153,6 +151,10 @@ | |||
| 153 | #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) | 151 | #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) |
| 154 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ | 152 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ |
| 155 | #define ANOMALY_05000432 (ANOMALY_BF526) | 153 | #define ANOMALY_05000432 (ANOMALY_BF526) |
| 154 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ | ||
| 155 | #define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) | ||
| 156 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | ||
| 157 | #define ANOMALY_05000443 (1) | ||
| 156 | 158 | ||
| 157 | /* Anomalies that don't exist on this proc */ | 159 | /* Anomalies that don't exist on this proc */ |
| 158 | #define ANOMALY_05000125 (0) | 160 | #define ANOMALY_05000125 (0) |
| @@ -168,7 +170,9 @@ | |||
| 168 | #define ANOMALY_05000285 (0) | 170 | #define ANOMALY_05000285 (0) |
| 169 | #define ANOMALY_05000307 (0) | 171 | #define ANOMALY_05000307 (0) |
| 170 | #define ANOMALY_05000311 (0) | 172 | #define ANOMALY_05000311 (0) |
| 173 | #define ANOMALY_05000312 (0) | ||
| 171 | #define ANOMALY_05000323 (0) | 174 | #define ANOMALY_05000323 (0) |
| 172 | #define ANOMALY_05000363 (0) | 175 | #define ANOMALY_05000363 (0) |
| 176 | #define ANOMALY_05000412 (0) | ||
| 173 | 177 | ||
| 174 | #endif | 178 | #endif |
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h index 144f08d3f8ea..3832aab11e9a 100644 --- a/arch/blackfin/mach-bf527/include/mach/bf527.h +++ b/arch/blackfin/mach-bf527/include/mach/bf527.h | |||
| @@ -110,7 +110,7 @@ | |||
| 110 | 110 | ||
| 111 | #ifdef CONFIG_BF527 | 111 | #ifdef CONFIG_BF527 |
| 112 | #define CPU "BF527" | 112 | #define CPU "BF527" |
| 113 | #define CPUID 0x27e4 | 113 | #define CPUID 0x27e0 |
| 114 | #endif | 114 | #endif |
| 115 | #ifdef CONFIG_BF526 | 115 | #ifdef CONFIG_BF526 |
| 116 | #define CPU "BF526" | 116 | #define CPU "BF526" |
| @@ -118,7 +118,7 @@ | |||
| 118 | #endif | 118 | #endif |
| 119 | #ifdef CONFIG_BF525 | 119 | #ifdef CONFIG_BF525 |
| 120 | #define CPU "BF525" | 120 | #define CPU "BF525" |
| 121 | #define CPUID 0x27e4 | 121 | #define CPUID 0x27e0 |
| 122 | #endif | 122 | #endif |
| 123 | #ifdef CONFIG_BF524 | 123 | #ifdef CONFIG_BF524 |
| 124 | #define CPU "BF524" | 124 | #define CPU "BF524" |
| @@ -126,7 +126,7 @@ | |||
| 126 | #endif | 126 | #endif |
| 127 | #ifdef CONFIG_BF523 | 127 | #ifdef CONFIG_BF523 |
| 128 | #define CPU "BF523" | 128 | #define CPU "BF523" |
| 129 | #define CPUID 0x27e4 | 129 | #define CPUID 0x27e0 |
| 130 | #endif | 130 | #endif |
| 131 | #ifdef CONFIG_BF522 | 131 | #ifdef CONFIG_BF522 |
| 132 | #define CPU "BF522" | 132 | #define CPU "BF522" |
| @@ -134,7 +134,7 @@ | |||
| 134 | #endif | 134 | #endif |
| 135 | 135 | ||
| 136 | #ifndef CPU | 136 | #ifndef CPU |
| 137 | #error Unknown CPU type - This kernel doesn't seem to be configured properly | 137 | #error "Unknown CPU type - This kernel doesn't seem to be configured properly" |
| 138 | #endif | 138 | #endif |
| 139 | 139 | ||
| 140 | #endif /* __MACH_BF527_H__ */ | 140 | #endif /* __MACH_BF527_H__ */ |
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_sir.h b/arch/blackfin/mach-bf527/include/mach/bfin_sir.h deleted file mode 100644 index cfd8ad4f1f2c..000000000000 --- a/arch/blackfin/mach-bf527/include/mach/bfin_sir.h +++ /dev/null | |||
| @@ -1,142 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Blackfin Infra-red Driver | ||
| 3 | * | ||
| 4 | * Copyright 2006-2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Enter bugs at http://blackfin.uclinux.org/ | ||
| 7 | * | ||
| 8 | * Licensed under the GPL-2 or later. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/serial.h> | ||
| 13 | #include <asm/dma.h> | ||
| 14 | #include <asm/portmux.h> | ||
| 15 | |||
| 16 | #define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) | ||
| 17 | #define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) | ||
| 18 | #define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) | ||
| 19 | #define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) | ||
| 20 | #define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) | ||
| 21 | #define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) | ||
| 22 | #define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) | ||
| 23 | |||
| 24 | #define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) | ||
| 25 | #define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) | ||
| 26 | #define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) | ||
| 27 | #define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) | ||
| 28 | #define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) | ||
| 29 | #define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) | ||
| 30 | |||
| 31 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 32 | struct dma_rx_buf { | ||
| 33 | char *buf; | ||
| 34 | int head; | ||
| 35 | int tail; | ||
| 36 | }; | ||
| 37 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 38 | |||
| 39 | struct bfin_sir_port { | ||
| 40 | unsigned char __iomem *membase; | ||
| 41 | unsigned int irq; | ||
| 42 | unsigned int lsr; | ||
| 43 | unsigned long clk; | ||
| 44 | struct net_device *dev; | ||
| 45 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 46 | int tx_done; | ||
| 47 | struct dma_rx_buf rx_dma_buf; | ||
| 48 | struct timer_list rx_dma_timer; | ||
| 49 | int rx_dma_nrows; | ||
| 50 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 51 | unsigned int tx_dma_channel; | ||
| 52 | unsigned int rx_dma_channel; | ||
| 53 | }; | ||
| 54 | |||
| 55 | struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; | ||
| 56 | |||
| 57 | struct bfin_sir_port_res { | ||
| 58 | unsigned long base_addr; | ||
| 59 | int irq; | ||
| 60 | unsigned int rx_dma_channel; | ||
| 61 | unsigned int tx_dma_channel; | ||
| 62 | }; | ||
| 63 | |||
| 64 | struct bfin_sir_port_res bfin_sir_port_resource[] = { | ||
| 65 | #ifdef CONFIG_BFIN_SIR0 | ||
| 66 | { | ||
| 67 | 0xFFC00400, | ||
| 68 | IRQ_UART0_RX, | ||
| 69 | CH_UART0_RX, | ||
| 70 | CH_UART0_TX, | ||
| 71 | }, | ||
| 72 | #endif | ||
| 73 | #ifdef CONFIG_BFIN_SIR1 | ||
| 74 | { | ||
| 75 | 0xFFC02000, | ||
| 76 | IRQ_UART1_RX, | ||
| 77 | CH_UART1_RX, | ||
| 78 | CH_UART1_TX, | ||
| 79 | }, | ||
| 80 | #endif | ||
| 81 | }; | ||
| 82 | |||
| 83 | int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); | ||
| 84 | |||
| 85 | struct bfin_sir_self { | ||
| 86 | struct bfin_sir_port *sir_port; | ||
| 87 | spinlock_t lock; | ||
| 88 | unsigned int open; | ||
| 89 | int speed; | ||
| 90 | int newspeed; | ||
| 91 | |||
| 92 | struct sk_buff *txskb; | ||
| 93 | struct sk_buff *rxskb; | ||
| 94 | struct net_device_stats stats; | ||
| 95 | struct device *dev; | ||
| 96 | struct irlap_cb *irlap; | ||
| 97 | struct qos_info qos; | ||
| 98 | |||
| 99 | iobuff_t tx_buff; | ||
| 100 | iobuff_t rx_buff; | ||
| 101 | |||
| 102 | struct work_struct work; | ||
| 103 | int mtt; | ||
| 104 | }; | ||
| 105 | |||
| 106 | static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) | ||
| 107 | { | ||
| 108 | unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); | ||
| 109 | port->lsr |= (lsr & (BI|FE|PE|OE)); | ||
| 110 | return lsr | port->lsr; | ||
| 111 | } | ||
| 112 | |||
| 113 | static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) | ||
| 114 | { | ||
| 115 | port->lsr = 0; | ||
| 116 | bfin_read16(port->membase + OFFSET_LSR); | ||
| 117 | } | ||
| 118 | |||
| 119 | #define DRIVER_NAME "bfin_sir" | ||
| 120 | |||
| 121 | static int bfin_sir_hw_init(void) | ||
| 122 | { | ||
| 123 | int ret = -ENODEV; | ||
| 124 | #ifdef CONFIG_BFIN_SIR0 | ||
| 125 | ret = peripheral_request(P_UART0_TX, DRIVER_NAME); | ||
| 126 | if (ret) | ||
| 127 | return ret; | ||
| 128 | ret = peripheral_request(P_UART0_RX, DRIVER_NAME); | ||
| 129 | if (ret) | ||
| 130 | return ret; | ||
| 131 | #endif | ||
| 132 | |||
| 133 | #ifdef CONFIG_BFIN_SIR1 | ||
| 134 | ret = peripheral_request(P_UART1_TX, DRIVER_NAME); | ||
| 135 | if (ret) | ||
| 136 | return ret; | ||
| 137 | ret = peripheral_request(P_UART1_RX, DRIVER_NAME); | ||
| 138 | if (ret) | ||
| 139 | return ret; | ||
| 140 | #endif | ||
| 141 | return ret; | ||
| 142 | } | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h index 9a814b9a12b9..1fe76d8e0403 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h | |||
| @@ -31,7 +31,6 @@ | |||
| 31 | #ifndef _CDEF_BF52X_H | 31 | #ifndef _CDEF_BF52X_H |
| 32 | #define _CDEF_BF52X_H | 32 | #define _CDEF_BF52X_H |
| 33 | 33 | ||
| 34 | #include <asm/system.h> | ||
| 35 | #include <asm/blackfin.h> | 34 | #include <asm/blackfin.h> |
| 36 | 35 | ||
| 37 | #include "defBF52x_base.h" | 36 | #include "defBF52x_base.h" |
| @@ -43,57 +42,9 @@ | |||
| 43 | 42 | ||
| 44 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | 43 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ |
| 45 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | 44 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 46 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 47 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 48 | { | ||
| 49 | unsigned long flags, iwr0, iwr1; | ||
| 50 | |||
| 51 | if (val == bfin_read_PLL_CTL()) | ||
| 52 | return; | ||
| 53 | |||
| 54 | local_irq_save(flags); | ||
| 55 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 56 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 57 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 58 | /* Only allow PPL Wakeup) */ | ||
| 59 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 60 | bfin_write32(SIC_IWR1, 0); | ||
| 61 | |||
| 62 | bfin_write16(PLL_CTL, val); | ||
| 63 | SSYNC(); | ||
| 64 | asm("IDLE;"); | ||
| 65 | |||
| 66 | bfin_write32(SIC_IWR0, iwr0); | ||
| 67 | bfin_write32(SIC_IWR1, iwr1); | ||
| 68 | local_irq_restore(flags); | ||
| 69 | } | ||
| 70 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | 45 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 71 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | 46 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) |
| 72 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | 47 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| 73 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 74 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 75 | { | ||
| 76 | unsigned long flags, iwr0, iwr1; | ||
| 77 | |||
| 78 | if (val == bfin_read_VR_CTL()) | ||
| 79 | return; | ||
| 80 | |||
| 81 | local_irq_save(flags); | ||
| 82 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 83 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 84 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 85 | /* Only allow PPL Wakeup) */ | ||
| 86 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 87 | bfin_write32(SIC_IWR1, 0); | ||
| 88 | |||
| 89 | bfin_write16(VR_CTL, val); | ||
| 90 | SSYNC(); | ||
| 91 | asm("IDLE;"); | ||
| 92 | |||
| 93 | bfin_write32(SIC_IWR0, iwr0); | ||
| 94 | bfin_write32(SIC_IWR1, iwr1); | ||
| 95 | local_irq_restore(flags); | ||
| 96 | } | ||
| 97 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | 48 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 98 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | 49 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) |
| 99 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | 50 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| @@ -1201,4 +1152,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1201 | #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) | 1152 | #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) |
| 1202 | #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) | 1153 | #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) |
| 1203 | 1154 | ||
| 1155 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 1156 | #include <asm/irq.h> | ||
| 1157 | |||
| 1158 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 1159 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 1160 | { | ||
| 1161 | unsigned long flags, iwr0, iwr1; | ||
| 1162 | |||
| 1163 | if (val == bfin_read_PLL_CTL()) | ||
| 1164 | return; | ||
| 1165 | |||
| 1166 | local_irq_save_hw(flags); | ||
| 1167 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 1168 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 1169 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 1170 | /* Only allow PPL Wakeup) */ | ||
| 1171 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 1172 | bfin_write32(SIC_IWR1, 0); | ||
| 1173 | |||
| 1174 | bfin_write16(PLL_CTL, val); | ||
| 1175 | SSYNC(); | ||
| 1176 | asm("IDLE;"); | ||
| 1177 | |||
| 1178 | bfin_write32(SIC_IWR0, iwr0); | ||
| 1179 | bfin_write32(SIC_IWR1, iwr1); | ||
| 1180 | local_irq_restore_hw(flags); | ||
| 1181 | } | ||
| 1182 | |||
| 1183 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 1184 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 1185 | { | ||
| 1186 | unsigned long flags, iwr0, iwr1; | ||
| 1187 | |||
| 1188 | if (val == bfin_read_VR_CTL()) | ||
| 1189 | return; | ||
| 1190 | |||
| 1191 | local_irq_save_hw(flags); | ||
| 1192 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 1193 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 1194 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 1195 | /* Only allow PPL Wakeup) */ | ||
| 1196 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 1197 | bfin_write32(SIC_IWR1, 0); | ||
| 1198 | |||
| 1199 | bfin_write16(VR_CTL, val); | ||
| 1200 | SSYNC(); | ||
| 1201 | asm("IDLE;"); | ||
| 1202 | |||
| 1203 | bfin_write32(SIC_IWR0, iwr0); | ||
| 1204 | bfin_write32(SIC_IWR1, iwr1); | ||
| 1205 | local_irq_restore_hw(flags); | ||
| 1206 | } | ||
| 1207 | |||
| 1204 | #endif /* _CDEF_BF52X_H */ | 1208 | #endif /* _CDEF_BF52X_H */ |
diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h index 49dd693223e8..eb287da101a2 100644 --- a/arch/blackfin/mach-bf527/include/mach/dma.h +++ b/arch/blackfin/mach-bf527/include/mach/dma.h | |||
| @@ -1,38 +1,14 @@ | |||
| 1 | /* | 1 | /* mach/dma.h - arch-specific DMA defines |
| 2 | * file: include/asm-blackfin/mach-bf527/dma.h | ||
| 3 | * based on: include/asm-blackfin/mach-bf537/dma.h | ||
| 4 | * author: Michael Hennerich (michael.hennerich@analog.com) | ||
| 5 | * | 2 | * |
| 6 | * created: | 3 | * Copyright 2004-2008 Analog Devices Inc. |
| 7 | * description: | ||
| 8 | * system DMA map | ||
| 9 | * rev: | ||
| 10 | * | 4 | * |
| 11 | * modified: | 5 | * Licensed under the GPL-2 or later. |
| 12 | * | ||
| 13 | * | ||
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * this program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the gnu general public license as published by | ||
| 18 | * the free software foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * this program is distributed in the hope that it will be useful, | ||
| 22 | * but without any warranty; without even the implied warranty of | ||
| 23 | * merchantability or fitness for a particular purpose. see the | ||
| 24 | * gnu general public license for more details. | ||
| 25 | * | ||
| 26 | * you should have received a copy of the gnu general public license | ||
| 27 | * along with this program; see the file copying. | ||
| 28 | * if not, write to the free software foundation, | ||
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 30 | */ | 6 | */ |
| 31 | 7 | ||
| 32 | #ifndef _MACH_DMA_H_ | 8 | #ifndef _MACH_DMA_H_ |
| 33 | #define _MACH_DMA_H_ | 9 | #define _MACH_DMA_H_ |
| 34 | 10 | ||
| 35 | #define MAX_BLACKFIN_DMA_CHANNEL 16 | 11 | #define MAX_DMA_CHANNELS 16 |
| 36 | 12 | ||
| 37 | #define CH_PPI 0 /* PPI receive/transmit or NFC */ | 13 | #define CH_PPI 0 /* PPI receive/transmit or NFC */ |
| 38 | #define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ | 14 | #define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ |
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h new file mode 100644 index 000000000000..06b6eebf0d49 --- /dev/null +++ b/arch/blackfin/mach-bf527/include/mach/gpio.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf527/include/mach/gpio.h | ||
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 4 | * | ||
| 5 | * Copyright (C) 2008 Analog Devices Inc. | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | #ifndef _MACH_GPIO_H_ | ||
| 11 | #define _MACH_GPIO_H_ | ||
| 12 | |||
| 13 | #define MAX_BLACKFIN_GPIOS 48 | ||
| 14 | |||
| 15 | #define GPIO_PF0 0 | ||
| 16 | #define GPIO_PF1 1 | ||
| 17 | #define GPIO_PF2 2 | ||
| 18 | #define GPIO_PF3 3 | ||
| 19 | #define GPIO_PF4 4 | ||
| 20 | #define GPIO_PF5 5 | ||
| 21 | #define GPIO_PF6 6 | ||
| 22 | #define GPIO_PF7 7 | ||
| 23 | #define GPIO_PF8 8 | ||
| 24 | #define GPIO_PF9 9 | ||
| 25 | #define GPIO_PF10 10 | ||
| 26 | #define GPIO_PF11 11 | ||
| 27 | #define GPIO_PF12 12 | ||
| 28 | #define GPIO_PF13 13 | ||
| 29 | #define GPIO_PF14 14 | ||
| 30 | #define GPIO_PF15 15 | ||
| 31 | #define GPIO_PG0 16 | ||
| 32 | #define GPIO_PG1 17 | ||
| 33 | #define GPIO_PG2 18 | ||
| 34 | #define GPIO_PG3 19 | ||
| 35 | #define GPIO_PG4 20 | ||
| 36 | #define GPIO_PG5 21 | ||
| 37 | #define GPIO_PG6 22 | ||
| 38 | #define GPIO_PG7 23 | ||
| 39 | #define GPIO_PG8 24 | ||
| 40 | #define GPIO_PG9 25 | ||
| 41 | #define GPIO_PG10 26 | ||
| 42 | #define GPIO_PG11 27 | ||
| 43 | #define GPIO_PG12 28 | ||
| 44 | #define GPIO_PG13 29 | ||
| 45 | #define GPIO_PG14 30 | ||
| 46 | #define GPIO_PG15 31 | ||
| 47 | #define GPIO_PH0 32 | ||
| 48 | #define GPIO_PH1 33 | ||
| 49 | #define GPIO_PH2 34 | ||
| 50 | #define GPIO_PH3 35 | ||
| 51 | #define GPIO_PH4 36 | ||
| 52 | #define GPIO_PH5 37 | ||
| 53 | #define GPIO_PH6 38 | ||
| 54 | #define GPIO_PH7 39 | ||
| 55 | #define GPIO_PH8 40 | ||
| 56 | #define GPIO_PH9 41 | ||
| 57 | #define GPIO_PH10 42 | ||
| 58 | #define GPIO_PH11 43 | ||
| 59 | #define GPIO_PH12 44 | ||
| 60 | #define GPIO_PH13 45 | ||
| 61 | #define GPIO_PH14 46 | ||
| 62 | #define GPIO_PH15 47 | ||
| 63 | |||
| 64 | #define PORT_F GPIO_PF0 | ||
| 65 | #define PORT_G GPIO_PG0 | ||
| 66 | #define PORT_H GPIO_PH0 | ||
| 67 | |||
| 68 | #endif /* _MACH_GPIO_H_ */ | ||
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h index 4e2b3f2020e5..8ea660d8151f 100644 --- a/arch/blackfin/mach-bf527/include/mach/irq.h +++ b/arch/blackfin/mach-bf527/include/mach/irq.h | |||
| @@ -96,14 +96,14 @@ | |||
| 96 | #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ | 96 | #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ |
| 97 | #define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ | 97 | #define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ |
| 98 | #define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ | 98 | #define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ |
| 99 | #define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */ | 99 | #define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ |
| 100 | #define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */ | 100 | #define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */ |
| 101 | #define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */ | 101 | #define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */ |
| 102 | #define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */ | 102 | #define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */ |
| 103 | #define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */ | 103 | #define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */ |
| 104 | #define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */ | 104 | #define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */ |
| 105 | #define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */ | 105 | #define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */ |
| 106 | #define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */ | 106 | #define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */ |
| 107 | #define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ | 107 | #define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ |
| 108 | #define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ | 108 | #define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ |
| 109 | #define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ | 109 | #define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ |
| @@ -227,14 +227,14 @@ | |||
| 227 | #define IRQ_PORTH_INTB_POS 28 | 227 | #define IRQ_PORTH_INTB_POS 28 |
| 228 | 228 | ||
| 229 | /* IAR4 BIT FIELDS */ | 229 | /* IAR4 BIT FIELDS */ |
| 230 | #define IRQ_TMR0_POS 0 | 230 | #define IRQ_TIMER0_POS 0 |
| 231 | #define IRQ_TMR1_POS 4 | 231 | #define IRQ_TIMER1_POS 4 |
| 232 | #define IRQ_TMR2_POS 8 | 232 | #define IRQ_TIMER2_POS 8 |
| 233 | #define IRQ_TMR3_POS 12 | 233 | #define IRQ_TIMER3_POS 12 |
| 234 | #define IRQ_TMR4_POS 16 | 234 | #define IRQ_TIMER4_POS 16 |
| 235 | #define IRQ_TMR5_POS 20 | 235 | #define IRQ_TIMER5_POS 20 |
| 236 | #define IRQ_TMR6_POS 24 | 236 | #define IRQ_TIMER6_POS 24 |
| 237 | #define IRQ_TMR7_POS 28 | 237 | #define IRQ_TIMER7_POS 28 |
| 238 | 238 | ||
| 239 | /* IAR5 BIT FIELDS */ | 239 | /* IAR5 BIT FIELDS */ |
| 240 | #define IRQ_PORTG_INTA_POS 0 | 240 | #define IRQ_PORTG_INTA_POS 0 |
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h index ef46dc991cd4..019e0017ad81 100644 --- a/arch/blackfin/mach-bf527/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf527/include/mach/mem_map.h | |||
| @@ -99,4 +99,10 @@ | |||
| 99 | #define L1_SCRATCH_START 0xFFB00000 | 99 | #define L1_SCRATCH_START 0xFFB00000 |
| 100 | #define L1_SCRATCH_LENGTH 0x1000 | 100 | #define L1_SCRATCH_LENGTH 0x1000 |
| 101 | 101 | ||
| 102 | #define GET_PDA_SAFE(preg) \ | ||
| 103 | preg.l = _cpu_pda; \ | ||
| 104 | preg.h = _cpu_pda; | ||
| 105 | |||
| 106 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 107 | |||
| 102 | #endif /* _MEM_MAP_527_H_ */ | 108 | #endif /* _MEM_MAP_527_H_ */ |
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c index 8a2367403d2b..f8c8acd73e30 100644 --- a/arch/blackfin/mach-bf527/ints-priority.c +++ b/arch/blackfin/mach-bf527/ints-priority.c | |||
| @@ -69,14 +69,14 @@ void __init program_IAR(void) | |||
| 69 | ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | | 69 | ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | |
| 70 | ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); | 70 | ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS)); |
| 71 | 71 | ||
| 72 | bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | | 72 | bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | |
| 73 | ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | | 73 | ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | |
| 74 | ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | | 74 | ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | |
| 75 | ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) | | 75 | ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | |
| 76 | ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) | | 76 | ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) | |
| 77 | ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) | | 77 | ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | |
| 78 | ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) | | 78 | ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | |
| 79 | ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS)); | 79 | ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS)); |
| 80 | 80 | ||
| 81 | bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | | 81 | bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) | |
| 82 | ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | | 82 | ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | |
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig index 76beb75f12da..14427de7d77f 100644 --- a/arch/blackfin/mach-bf533/Kconfig +++ b/arch/blackfin/mach-bf533/Kconfig | |||
| @@ -59,7 +59,7 @@ config DMA7_UARTTX | |||
| 59 | default 10 | 59 | default 10 |
| 60 | config TIMER0 | 60 | config TIMER0 |
| 61 | int "TIMER0" | 61 | int "TIMER0" |
| 62 | default 11 | 62 | default 8 |
| 63 | config TIMER1 | 63 | config TIMER1 |
| 64 | int "TIMER1" | 64 | int "TIMER1" |
| 65 | default 11 | 65 | default 11 |
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile index aa9f2647ee0c..874840f76028 100644 --- a/arch/blackfin/mach-bf533/Makefile +++ b/arch/blackfin/mach-bf533/Makefile | |||
| @@ -2,6 +2,4 @@ | |||
| 2 | # arch/blackfin/mach-bf533/Makefile | 2 | # arch/blackfin/mach-bf533/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | extra-y := head.o | ||
| 6 | |||
| 7 | obj-y := ints-priority.o dma.o | 5 | obj-y := ints-priority.o dma.o |
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 72ac3ac8ef76..0c66bf44cfab 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c | |||
| @@ -313,23 +313,33 @@ static struct platform_device bfin_uart_device = { | |||
| 313 | #endif | 313 | #endif |
| 314 | 314 | ||
| 315 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 315 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 316 | static struct resource bfin_sir_resources[] = { | ||
| 317 | #ifdef CONFIG_BFIN_SIR0 | 316 | #ifdef CONFIG_BFIN_SIR0 |
| 317 | static struct resource bfin_sir0_resources[] = { | ||
| 318 | { | 318 | { |
| 319 | .start = 0xFFC00400, | 319 | .start = 0xFFC00400, |
| 320 | .end = 0xFFC004FF, | 320 | .end = 0xFFC004FF, |
| 321 | .flags = IORESOURCE_MEM, | 321 | .flags = IORESOURCE_MEM, |
| 322 | }, | 322 | }, |
| 323 | #endif | 323 | { |
| 324 | .start = IRQ_UART0_RX, | ||
| 325 | .end = IRQ_UART0_RX+1, | ||
| 326 | .flags = IORESOURCE_IRQ, | ||
| 327 | }, | ||
| 328 | { | ||
| 329 | .start = CH_UART0_RX, | ||
| 330 | .end = CH_UART0_RX+1, | ||
| 331 | .flags = IORESOURCE_DMA, | ||
| 332 | }, | ||
| 324 | }; | 333 | }; |
| 325 | 334 | ||
| 326 | static struct platform_device bfin_sir_device = { | 335 | static struct platform_device bfin_sir0_device = { |
| 327 | .name = "bfin_sir", | 336 | .name = "bfin_sir", |
| 328 | .id = 0, | 337 | .id = 0, |
| 329 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 338 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 330 | .resource = bfin_sir_resources, | 339 | .resource = bfin_sir0_resources, |
| 331 | }; | 340 | }; |
| 332 | #endif | 341 | #endif |
| 342 | #endif | ||
| 333 | 343 | ||
| 334 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) | 344 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
| 335 | 345 | ||
| @@ -431,7 +441,9 @@ static struct platform_device *h8606_devices[] __initdata = { | |||
| 431 | #endif | 441 | #endif |
| 432 | 442 | ||
| 433 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 443 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 434 | &bfin_sir_device, | 444 | #ifdef CONFIG_BFIN_SIR0 |
| 445 | &bfin_sir0_device, | ||
| 446 | #endif | ||
| 435 | #endif | 447 | #endif |
| 436 | 448 | ||
| 437 | #if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE) | 449 | #if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE) |
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c index d064ded87719..6ee607c259ac 100644 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ b/arch/blackfin/mach-bf533/boards/blackstamp.c | |||
| @@ -212,23 +212,33 @@ static struct platform_device bfin_uart_device = { | |||
| 212 | #endif | 212 | #endif |
| 213 | 213 | ||
| 214 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 214 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 215 | static struct resource bfin_sir_resources[] = { | ||
| 216 | #ifdef CONFIG_BFIN_SIR0 | 215 | #ifdef CONFIG_BFIN_SIR0 |
| 216 | static struct resource bfin_sir0_resources[] = { | ||
| 217 | { | 217 | { |
| 218 | .start = 0xFFC00400, | 218 | .start = 0xFFC00400, |
| 219 | .end = 0xFFC004FF, | 219 | .end = 0xFFC004FF, |
| 220 | .flags = IORESOURCE_MEM, | 220 | .flags = IORESOURCE_MEM, |
| 221 | }, | 221 | }, |
| 222 | #endif | 222 | { |
| 223 | .start = IRQ_UART0_RX, | ||
| 224 | .end = IRQ_UART0_RX+1, | ||
| 225 | .flags = IORESOURCE_IRQ, | ||
| 226 | }, | ||
| 227 | { | ||
| 228 | .start = CH_UART0_RX, | ||
| 229 | .end = CH_UART0_RX+1, | ||
| 230 | .flags = IORESOURCE_DMA, | ||
| 231 | }, | ||
| 223 | }; | 232 | }; |
| 224 | 233 | ||
| 225 | static struct platform_device bfin_sir_device = { | 234 | static struct platform_device bfin_sir0_device = { |
| 226 | .name = "bfin_sir", | 235 | .name = "bfin_sir", |
| 227 | .id = 0, | 236 | .id = 0, |
| 228 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 237 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 229 | .resource = bfin_sir_resources, | 238 | .resource = bfin_sir0_resources, |
| 230 | }; | 239 | }; |
| 231 | #endif | 240 | #endif |
| 241 | #endif | ||
| 232 | 242 | ||
| 233 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | 243 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
| 234 | static struct platform_device bfin_sport0_uart_device = { | 244 | static struct platform_device bfin_sport0_uart_device = { |
| @@ -353,7 +363,9 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 353 | #endif | 363 | #endif |
| 354 | 364 | ||
| 355 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 365 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 356 | &bfin_sir_device, | 366 | #ifdef CONFIG_BFIN_SIR0 |
| 367 | &bfin_sir0_device, | ||
| 368 | #endif | ||
| 357 | #endif | 369 | #endif |
| 358 | 370 | ||
| 359 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | 371 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index 575843f6d9ef..e7061c7e8c42 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c | |||
| @@ -219,6 +219,19 @@ static struct platform_device smc91x_device = { | |||
| 219 | }; | 219 | }; |
| 220 | #endif | 220 | #endif |
| 221 | 221 | ||
| 222 | static struct resource bfin_gpios_resources = { | ||
| 223 | .start = 0, | ||
| 224 | .end = MAX_BLACKFIN_GPIOS - 1, | ||
| 225 | .flags = IORESOURCE_IRQ, | ||
| 226 | }; | ||
| 227 | |||
| 228 | static struct platform_device bfin_gpios_device = { | ||
| 229 | .name = "simple-gpio", | ||
| 230 | .id = -1, | ||
| 231 | .num_resources = 1, | ||
| 232 | .resource = &bfin_gpios_resources, | ||
| 233 | }; | ||
| 234 | |||
| 222 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | 235 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
| 223 | static struct resource bfin_uart_resources[] = { | 236 | static struct resource bfin_uart_resources[] = { |
| 224 | { | 237 | { |
| @@ -237,23 +250,33 @@ static struct platform_device bfin_uart_device = { | |||
| 237 | #endif | 250 | #endif |
| 238 | 251 | ||
| 239 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 252 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 240 | static struct resource bfin_sir_resources[] = { | ||
| 241 | #ifdef CONFIG_BFIN_SIR0 | 253 | #ifdef CONFIG_BFIN_SIR0 |
| 254 | static struct resource bfin_sir0_resources[] = { | ||
| 242 | { | 255 | { |
| 243 | .start = 0xFFC00400, | 256 | .start = 0xFFC00400, |
| 244 | .end = 0xFFC004FF, | 257 | .end = 0xFFC004FF, |
| 245 | .flags = IORESOURCE_MEM, | 258 | .flags = IORESOURCE_MEM, |
| 246 | }, | 259 | }, |
| 247 | #endif | 260 | { |
| 261 | .start = IRQ_UART0_RX, | ||
| 262 | .end = IRQ_UART0_RX+1, | ||
| 263 | .flags = IORESOURCE_IRQ, | ||
| 264 | }, | ||
| 265 | { | ||
| 266 | .start = CH_UART0_RX, | ||
| 267 | .end = CH_UART0_RX+1, | ||
| 268 | .flags = IORESOURCE_DMA, | ||
| 269 | }, | ||
| 248 | }; | 270 | }; |
| 249 | 271 | ||
| 250 | static struct platform_device bfin_sir_device = { | 272 | static struct platform_device bfin_sir0_device = { |
| 251 | .name = "bfin_sir", | 273 | .name = "bfin_sir", |
| 252 | .id = 0, | 274 | .id = 0, |
| 253 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 275 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 254 | .resource = bfin_sir_resources, | 276 | .resource = bfin_sir0_resources, |
| 255 | }; | 277 | }; |
| 256 | #endif | 278 | #endif |
| 279 | #endif | ||
| 257 | 280 | ||
| 258 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | 281 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
| 259 | static struct platform_device bfin_sport0_uart_device = { | 282 | static struct platform_device bfin_sport0_uart_device = { |
| @@ -342,7 +365,9 @@ static struct platform_device *cm_bf533_devices[] __initdata = { | |||
| 342 | #endif | 365 | #endif |
| 343 | 366 | ||
| 344 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 367 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 345 | &bfin_sir_device, | 368 | #ifdef CONFIG_BFIN_SIR0 |
| 369 | &bfin_sir0_device, | ||
| 370 | #endif | ||
| 346 | #endif | 371 | #endif |
| 347 | 372 | ||
| 348 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | 373 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
| @@ -365,6 +390,8 @@ static struct platform_device *cm_bf533_devices[] __initdata = { | |||
| 365 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 390 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 366 | &bfin_spi0_device, | 391 | &bfin_spi0_device, |
| 367 | #endif | 392 | #endif |
| 393 | |||
| 394 | &bfin_gpios_device, | ||
| 368 | }; | 395 | }; |
| 369 | 396 | ||
| 370 | static int __init cm_bf533_init(void) | 397 | static int __init cm_bf533_init(void) |
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index cc2e7eeb1d5a..08cd0969de47 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c | |||
| @@ -46,7 +46,7 @@ | |||
| 46 | /* | 46 | /* |
| 47 | * Name the Board for the /proc/cpuinfo | 47 | * Name the Board for the /proc/cpuinfo |
| 48 | */ | 48 | */ |
| 49 | const char bfin_board_name[] = "ADDS-BF533-EZKIT"; | 49 | const char bfin_board_name[] = "ADI BF533-EZKIT"; |
| 50 | 50 | ||
| 51 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | 51 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
| 52 | static struct platform_device rtc_device = { | 52 | static struct platform_device rtc_device = { |
| @@ -236,23 +236,33 @@ static struct platform_device bfin_uart_device = { | |||
| 236 | #endif | 236 | #endif |
| 237 | 237 | ||
| 238 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 238 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 239 | static struct resource bfin_sir_resources[] = { | ||
| 240 | #ifdef CONFIG_BFIN_SIR0 | 239 | #ifdef CONFIG_BFIN_SIR0 |
| 240 | static struct resource bfin_sir0_resources[] = { | ||
| 241 | { | 241 | { |
| 242 | .start = 0xFFC00400, | 242 | .start = 0xFFC00400, |
| 243 | .end = 0xFFC004FF, | 243 | .end = 0xFFC004FF, |
| 244 | .flags = IORESOURCE_MEM, | 244 | .flags = IORESOURCE_MEM, |
| 245 | }, | 245 | }, |
| 246 | #endif | 246 | { |
| 247 | .start = IRQ_UART0_RX, | ||
| 248 | .end = IRQ_UART0_RX+1, | ||
| 249 | .flags = IORESOURCE_IRQ, | ||
| 250 | }, | ||
| 251 | { | ||
| 252 | .start = CH_UART0_RX, | ||
| 253 | .end = CH_UART0_RX+1, | ||
| 254 | .flags = IORESOURCE_DMA, | ||
| 255 | }, | ||
| 247 | }; | 256 | }; |
| 248 | 257 | ||
| 249 | static struct platform_device bfin_sir_device = { | 258 | static struct platform_device bfin_sir0_device = { |
| 250 | .name = "bfin_sir", | 259 | .name = "bfin_sir", |
| 251 | .id = 0, | 260 | .id = 0, |
| 252 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 261 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 253 | .resource = bfin_sir_resources, | 262 | .resource = bfin_sir0_resources, |
| 254 | }; | 263 | }; |
| 255 | #endif | 264 | #endif |
| 265 | #endif | ||
| 256 | 266 | ||
| 257 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | 267 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
| 258 | #include <linux/input.h> | 268 | #include <linux/input.h> |
| @@ -363,7 +373,9 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
| 363 | #endif | 373 | #endif |
| 364 | 374 | ||
| 365 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 375 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 366 | &bfin_sir_device, | 376 | #ifdef CONFIG_BFIN_SIR0 |
| 377 | &bfin_sir0_device, | ||
| 378 | #endif | ||
| 367 | #endif | 379 | #endif |
| 368 | 380 | ||
| 369 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | 381 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c index 82b1f6a60e3f..986eeec53b1f 100644 --- a/arch/blackfin/mach-bf533/boards/generic_board.c +++ b/arch/blackfin/mach-bf533/boards/generic_board.c | |||
| @@ -72,6 +72,35 @@ static struct platform_device smc91x_device = { | |||
| 72 | }; | 72 | }; |
| 73 | #endif | 73 | #endif |
| 74 | 74 | ||
| 75 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 76 | #ifdef CONFIG_BFIN_SIR0 | ||
| 77 | static struct resource bfin_sir0_resources[] = { | ||
| 78 | { | ||
| 79 | .start = 0xFFC00400, | ||
| 80 | .end = 0xFFC004FF, | ||
| 81 | .flags = IORESOURCE_MEM, | ||
| 82 | }, | ||
| 83 | { | ||
| 84 | .start = IRQ_UART0_RX, | ||
| 85 | .end = IRQ_UART0_RX+1, | ||
| 86 | .flags = IORESOURCE_IRQ, | ||
| 87 | }, | ||
| 88 | { | ||
| 89 | .start = CH_UART0_RX, | ||
| 90 | .end = CH_UART0_RX+1, | ||
| 91 | .flags = IORESOURCE_DMA, | ||
| 92 | }, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static struct platform_device bfin_sir0_device = { | ||
| 96 | .name = "bfin_sir", | ||
| 97 | .id = 0, | ||
| 98 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 99 | .resource = bfin_sir0_resources, | ||
| 100 | }; | ||
| 101 | #endif | ||
| 102 | #endif | ||
| 103 | |||
| 75 | static struct platform_device *generic_board_devices[] __initdata = { | 104 | static struct platform_device *generic_board_devices[] __initdata = { |
| 76 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | 105 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
| 77 | &rtc_device, | 106 | &rtc_device, |
| @@ -80,6 +109,12 @@ static struct platform_device *generic_board_devices[] __initdata = { | |||
| 80 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 109 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
| 81 | &smc91x_device, | 110 | &smc91x_device, |
| 82 | #endif | 111 | #endif |
| 112 | |||
| 113 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 114 | #ifdef CONFIG_BFIN_SIR0 | ||
| 115 | &bfin_sir0_device, | ||
| 116 | #endif | ||
| 117 | #endif | ||
| 83 | }; | 118 | }; |
| 84 | 119 | ||
| 85 | static int __init generic_board_init(void) | 120 | static int __init generic_board_init(void) |
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c index 5864892de314..e30b1b7d1442 100644 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/arch/blackfin/mach-bf533/boards/ip0x.c | |||
| @@ -197,23 +197,33 @@ static struct platform_device bfin_uart_device = { | |||
| 197 | #endif | 197 | #endif |
| 198 | 198 | ||
| 199 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 199 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 200 | static struct resource bfin_sir_resources[] = { | ||
| 201 | #ifdef CONFIG_BFIN_SIR0 | 200 | #ifdef CONFIG_BFIN_SIR0 |
| 201 | static struct resource bfin_sir0_resources[] = { | ||
| 202 | { | 202 | { |
| 203 | .start = 0xFFC00400, | 203 | .start = 0xFFC00400, |
| 204 | .end = 0xFFC004FF, | 204 | .end = 0xFFC004FF, |
| 205 | .flags = IORESOURCE_MEM, | 205 | .flags = IORESOURCE_MEM, |
| 206 | }, | 206 | }, |
| 207 | #endif | 207 | { |
| 208 | .start = IRQ_UART0_RX, | ||
| 209 | .end = IRQ_UART0_RX+1, | ||
| 210 | .flags = IORESOURCE_IRQ, | ||
| 211 | }, | ||
| 212 | { | ||
| 213 | .start = CH_UART0_RX, | ||
| 214 | .end = CH_UART0_RX+1, | ||
| 215 | .flags = IORESOURCE_DMA, | ||
| 216 | }, | ||
| 208 | }; | 217 | }; |
| 209 | 218 | ||
| 210 | static struct platform_device bfin_sir_device = { | 219 | static struct platform_device bfin_sir0_device = { |
| 211 | .name = "bfin_sir", | 220 | .name = "bfin_sir", |
| 212 | .id = 0, | 221 | .id = 0, |
| 213 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 222 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 214 | .resource = bfin_sir_resources, | 223 | .resource = bfin_sir0_resources, |
| 215 | }; | 224 | }; |
| 216 | #endif | 225 | #endif |
| 226 | #endif | ||
| 217 | 227 | ||
| 218 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | 228 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
| 219 | static struct resource isp1362_hcd_resources[] = { | 229 | static struct resource isp1362_hcd_resources[] = { |
| @@ -272,7 +282,9 @@ static struct platform_device *ip0x_devices[] __initdata = { | |||
| 272 | #endif | 282 | #endif |
| 273 | 283 | ||
| 274 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 284 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 275 | &bfin_sir_device, | 285 | #ifdef CONFIG_BFIN_SIR0 |
| 286 | &bfin_sir0_device, | ||
| 287 | #endif | ||
| 276 | #endif | 288 | #endif |
| 277 | 289 | ||
| 278 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | 290 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 050ffca53530..07f9ad1e189c 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c | |||
| @@ -49,7 +49,7 @@ | |||
| 49 | /* | 49 | /* |
| 50 | * Name the Board for the /proc/cpuinfo | 50 | * Name the Board for the /proc/cpuinfo |
| 51 | */ | 51 | */ |
| 52 | const char bfin_board_name[] = "ADDS-BF533-STAMP"; | 52 | const char bfin_board_name[] = "ADI BF533-STAMP"; |
| 53 | 53 | ||
| 54 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | 54 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
| 55 | static struct platform_device rtc_device = { | 55 | static struct platform_device rtc_device = { |
| @@ -118,7 +118,7 @@ static struct mtd_partition stamp_partitions[] = { | |||
| 118 | .offset = 0, | 118 | .offset = 0, |
| 119 | }, { | 119 | }, { |
| 120 | .name = "linux kernel(nor)", | 120 | .name = "linux kernel(nor)", |
| 121 | .size = 0xE0000, | 121 | .size = 0x180000, |
| 122 | .offset = MTDPART_OFS_APPEND, | 122 | .offset = MTDPART_OFS_APPEND, |
| 123 | }, { | 123 | }, { |
| 124 | .name = "file system(nor)", | 124 | .name = "file system(nor)", |
| @@ -169,7 +169,7 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { | |||
| 169 | .mask_flags = MTD_CAP_ROM | 169 | .mask_flags = MTD_CAP_ROM |
| 170 | }, { | 170 | }, { |
| 171 | .name = "linux kernel(spi)", | 171 | .name = "linux kernel(spi)", |
| 172 | .size = 0xe0000, | 172 | .size = 0x180000, |
| 173 | .offset = MTDPART_OFS_APPEND, | 173 | .offset = MTDPART_OFS_APPEND, |
| 174 | }, { | 174 | }, { |
| 175 | .name = "file system(spi)", | 175 | .name = "file system(spi)", |
| @@ -216,13 +216,6 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | |||
| 216 | }; | 216 | }; |
| 217 | #endif | 217 | #endif |
| 218 | 218 | ||
| 219 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | ||
| 220 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | ||
| 221 | .enable_dma = 1, | ||
| 222 | .bits_per_word = 8, | ||
| 223 | }; | ||
| 224 | #endif | ||
| 225 | |||
| 226 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | 219 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
| 227 | static struct bfin5xx_spi_chip spidev_chip_info = { | 220 | static struct bfin5xx_spi_chip spidev_chip_info = { |
| 228 | .enable_dma = 0, | 221 | .enable_dma = 0, |
| @@ -265,27 +258,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 265 | }, | 258 | }, |
| 266 | #endif | 259 | #endif |
| 267 | 260 | ||
| 268 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | ||
| 269 | { | ||
| 270 | .modalias = "spi_mmc_dummy", | ||
| 271 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 272 | .bus_num = 0, | ||
| 273 | .chip_select = 0, | ||
| 274 | .platform_data = NULL, | ||
| 275 | .controller_data = &spi_mmc_chip_info, | ||
| 276 | .mode = SPI_MODE_3, | ||
| 277 | }, | ||
| 278 | { | ||
| 279 | .modalias = "spi_mmc", | ||
| 280 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 281 | .bus_num = 0, | ||
| 282 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | ||
| 283 | .platform_data = NULL, | ||
| 284 | .controller_data = &spi_mmc_chip_info, | ||
| 285 | .mode = SPI_MODE_3, | ||
| 286 | }, | ||
| 287 | #endif | ||
| 288 | |||
| 289 | #if defined(CONFIG_PBX) | 261 | #if defined(CONFIG_PBX) |
| 290 | { | 262 | { |
| 291 | .modalias = "fxs-spi", | 263 | .modalias = "fxs-spi", |
| @@ -373,23 +345,33 @@ static struct platform_device bfin_uart_device = { | |||
| 373 | #endif | 345 | #endif |
| 374 | 346 | ||
| 375 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 347 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 376 | static struct resource bfin_sir_resources[] = { | ||
| 377 | #ifdef CONFIG_BFIN_SIR0 | 348 | #ifdef CONFIG_BFIN_SIR0 |
| 349 | static struct resource bfin_sir0_resources[] = { | ||
| 378 | { | 350 | { |
| 379 | .start = 0xFFC00400, | 351 | .start = 0xFFC00400, |
| 380 | .end = 0xFFC004FF, | 352 | .end = 0xFFC004FF, |
| 381 | .flags = IORESOURCE_MEM, | 353 | .flags = IORESOURCE_MEM, |
| 382 | }, | 354 | }, |
| 383 | #endif | 355 | { |
| 356 | .start = IRQ_UART0_RX, | ||
| 357 | .end = IRQ_UART0_RX+1, | ||
| 358 | .flags = IORESOURCE_IRQ, | ||
| 359 | }, | ||
| 360 | { | ||
| 361 | .start = CH_UART0_RX, | ||
| 362 | .end = CH_UART0_RX+1, | ||
| 363 | .flags = IORESOURCE_DMA, | ||
| 364 | }, | ||
| 384 | }; | 365 | }; |
| 385 | 366 | ||
| 386 | static struct platform_device bfin_sir_device = { | 367 | static struct platform_device bfin_sir0_device = { |
| 387 | .name = "bfin_sir", | 368 | .name = "bfin_sir", |
| 388 | .id = 0, | 369 | .id = 0, |
| 389 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 370 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 390 | .resource = bfin_sir_resources, | 371 | .resource = bfin_sir0_resources, |
| 391 | }; | 372 | }; |
| 392 | #endif | 373 | #endif |
| 374 | #endif | ||
| 393 | 375 | ||
| 394 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | 376 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
| 395 | static struct platform_device bfin_sport0_uart_device = { | 377 | static struct platform_device bfin_sport0_uart_device = { |
| @@ -537,7 +519,9 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 537 | #endif | 519 | #endif |
| 538 | 520 | ||
| 539 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 521 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 540 | &bfin_sir_device, | 522 | #ifdef CONFIG_BFIN_SIR0 |
| 523 | &bfin_sir0_device, | ||
| 524 | #endif | ||
| 541 | #endif | 525 | #endif |
| 542 | 526 | ||
| 543 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | 527 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c index 28655c1cb7dc..0a6eb8f24d98 100644 --- a/arch/blackfin/mach-bf533/dma.c +++ b/arch/blackfin/mach-bf533/dma.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <asm/blackfin.h> | 31 | #include <asm/blackfin.h> |
| 32 | #include <asm/dma.h> | 32 | #include <asm/dma.h> |
| 33 | 33 | ||
| 34 | struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { | 34 | struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { |
| 35 | (struct dma_register *) DMA0_NEXT_DESC_PTR, | 35 | (struct dma_register *) DMA0_NEXT_DESC_PTR, |
| 36 | (struct dma_register *) DMA1_NEXT_DESC_PTR, | 36 | (struct dma_register *) DMA1_NEXT_DESC_PTR, |
| 37 | (struct dma_register *) DMA2_NEXT_DESC_PTR, | 37 | (struct dma_register *) DMA2_NEXT_DESC_PTR, |
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S deleted file mode 100644 index 9fc95aaca439..000000000000 --- a/arch/blackfin/mach-bf533/head.S +++ /dev/null | |||
| @@ -1,137 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf533/head.S | ||
| 3 | * Based on: | ||
| 4 | * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne | ||
| 5 | * | ||
| 6 | * Created: 1998 | ||
| 7 | * Description: bf533 startup file | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/linkage.h> | ||
| 31 | #include <linux/init.h> | ||
| 32 | #include <asm/blackfin.h> | ||
| 33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 34 | #include <asm/clocks.h> | ||
| 35 | #include <mach/mem_init.h> | ||
| 36 | #endif | ||
| 37 | |||
| 38 | .section .l1.text | ||
| 39 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 40 | ENTRY(_start_dma_code) | ||
| 41 | p0.h = hi(SIC_IWR); | ||
| 42 | p0.l = lo(SIC_IWR); | ||
| 43 | r0.l = 0x1; | ||
| 44 | r0.h = 0x0; | ||
| 45 | [p0] = r0; | ||
| 46 | SSYNC; | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Set PLL_CTL | ||
| 50 | * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors | ||
| 51 | * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK | ||
| 52 | * - [7] = output delay (add 200ps of delay to mem signals) | ||
| 53 | * - [6] = input delay (add 200ps of input delay to mem signals) | ||
| 54 | * - [5] = PDWN : 1=All Clocks off | ||
| 55 | * - [3] = STOPCK : 1=Core Clock off | ||
| 56 | * - [1] = PLL_OFF : 1=Disable Power to PLL | ||
| 57 | * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL | ||
| 58 | * all other bits set to zero | ||
| 59 | */ | ||
| 60 | |||
| 61 | p0.h = hi(PLL_LOCKCNT); | ||
| 62 | p0.l = lo(PLL_LOCKCNT); | ||
| 63 | r0 = 0x300(Z); | ||
| 64 | w[p0] = r0.l; | ||
| 65 | ssync; | ||
| 66 | |||
| 67 | P2.H = hi(EBIU_SDGCTL); | ||
| 68 | P2.L = lo(EBIU_SDGCTL); | ||
| 69 | R0 = [P2]; | ||
| 70 | BITSET (R0, 24); | ||
| 71 | [P2] = R0; | ||
| 72 | SSYNC; | ||
| 73 | |||
| 74 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ | ||
| 75 | r0 = r0 << 9; /* Shift it over, */ | ||
| 76 | r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ | ||
| 77 | r0 = r1 | r0; | ||
| 78 | r1 = PLL_BYPASS; /* Bypass the PLL? */ | ||
| 79 | r1 = r1 << 8; /* Shift it over */ | ||
| 80 | r0 = r1 | r0; /* add them all together */ | ||
| 81 | #ifdef ANOMALY_05000265 | ||
| 82 | BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */ | ||
| 83 | #endif | ||
| 84 | |||
| 85 | p0.h = hi(PLL_CTL); | ||
| 86 | p0.l = lo(PLL_CTL); /* Load the address */ | ||
| 87 | cli r2; /* Disable interrupts */ | ||
| 88 | ssync; | ||
| 89 | w[p0] = r0.l; /* Set the value */ | ||
| 90 | idle; /* Wait for the PLL to stablize */ | ||
| 91 | sti r2; /* Enable interrupts */ | ||
| 92 | |||
| 93 | .Lcheck_again: | ||
| 94 | p0.h = hi(PLL_STAT); | ||
| 95 | p0.l = lo(PLL_STAT); | ||
| 96 | R0 = W[P0](Z); | ||
| 97 | CC = BITTST(R0,5); | ||
| 98 | if ! CC jump .Lcheck_again; | ||
| 99 | |||
| 100 | /* Configure SCLK & CCLK Dividers */ | ||
| 101 | r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | ||
| 102 | p0.h = hi(PLL_DIV); | ||
| 103 | p0.l = lo(PLL_DIV); | ||
| 104 | w[p0] = r0.l; | ||
| 105 | ssync; | ||
| 106 | |||
| 107 | p0.l = lo(EBIU_SDRRC); | ||
| 108 | p0.h = hi(EBIU_SDRRC); | ||
| 109 | r0 = mem_SDRRC; | ||
| 110 | w[p0] = r0.l; | ||
| 111 | ssync; | ||
| 112 | |||
| 113 | P2.H = hi(EBIU_SDGCTL); | ||
| 114 | P2.L = lo(EBIU_SDGCTL); | ||
| 115 | R0 = [P2]; | ||
| 116 | BITCLR (R0, 24); | ||
| 117 | p0.h = hi(EBIU_SDSTAT); | ||
| 118 | p0.l = lo(EBIU_SDSTAT); | ||
| 119 | r2.l = w[p0]; | ||
| 120 | cc = bittst(r2,3); | ||
| 121 | if !cc jump .Lskip; | ||
| 122 | NOP; | ||
| 123 | BITSET (R0, 23); | ||
| 124 | .Lskip: | ||
| 125 | [P2] = R0; | ||
| 126 | SSYNC; | ||
| 127 | |||
| 128 | R0.L = lo(mem_SDGCTL); | ||
| 129 | R0.H = hi(mem_SDGCTL); | ||
| 130 | R1 = [p2]; | ||
| 131 | R1 = R1 | R0; | ||
| 132 | [P2] = R1; | ||
| 133 | SSYNC; | ||
| 134 | |||
| 135 | RTS; | ||
| 136 | ENDPROC(_start_dma_code) | ||
| 137 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | ||
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index f544fc56959a..0d3a03429fb9 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file shoule be up to date with: |
| 10 | * - Revision D, 06/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List | 10 | * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
| @@ -194,6 +194,12 @@ | |||
| 194 | #define ANOMALY_05000403 (1) | 194 | #define ANOMALY_05000403 (1) |
| 195 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | 195 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
| 196 | #define ANOMALY_05000416 (1) | 196 | #define ANOMALY_05000416 (1) |
| 197 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ | ||
| 198 | #define ANOMALY_05000425 (1) | ||
| 199 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | ||
| 200 | #define ANOMALY_05000426 (1) | ||
| 201 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | ||
| 202 | #define ANOMALY_05000443 (1) | ||
| 197 | 203 | ||
| 198 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are | 204 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are |
| 199 | * here to show running on older silicon just isn't feasible. | 205 | * here to show running on older silicon just isn't feasible. |
| @@ -273,5 +279,8 @@ | |||
| 273 | #define ANOMALY_05000323 (0) | 279 | #define ANOMALY_05000323 (0) |
| 274 | #define ANOMALY_05000353 (1) | 280 | #define ANOMALY_05000353 (1) |
| 275 | #define ANOMALY_05000386 (1) | 281 | #define ANOMALY_05000386 (1) |
| 282 | #define ANOMALY_05000412 (0) | ||
| 283 | #define ANOMALY_05000432 (0) | ||
| 284 | #define ANOMALY_05000435 (0) | ||
| 276 | 285 | ||
| 277 | #endif | 286 | #endif |
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h index dfc8c1ad2d7a..cf4427cd3f72 100644 --- a/arch/blackfin/mach-bf533/include/mach/bf533.h +++ b/arch/blackfin/mach-bf533/include/mach/bf533.h | |||
| @@ -145,7 +145,7 @@ | |||
| 145 | #endif | 145 | #endif |
| 146 | #ifdef CONFIG_BF532 | 146 | #ifdef CONFIG_BF532 |
| 147 | #define CPU "BF532" | 147 | #define CPU "BF532" |
| 148 | #define CPUID 0x275A | 148 | #define CPUID 0x27a5 |
| 149 | #endif | 149 | #endif |
| 150 | #ifdef CONFIG_BF531 | 150 | #ifdef CONFIG_BF531 |
| 151 | #define CPU "BF531" | 151 | #define CPU "BF531" |
| @@ -153,7 +153,7 @@ | |||
| 153 | #endif | 153 | #endif |
| 154 | 154 | ||
| 155 | #ifndef CPU | 155 | #ifndef CPU |
| 156 | #error Unknown CPU type - This kernel doesn't seem to be configured properly | 156 | #error "Unknown CPU type - This kernel doesn't seem to be configured properly" |
| 157 | #endif | 157 | #endif |
| 158 | 158 | ||
| 159 | #endif /* __MACH_BF533_H__ */ | 159 | #endif /* __MACH_BF533_H__ */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_sir.h b/arch/blackfin/mach-bf533/include/mach/bfin_sir.h deleted file mode 100644 index 9bb87e9e2e9b..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/bfin_sir.h +++ /dev/null | |||
| @@ -1,125 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Blackfin Infra-red Driver | ||
| 3 | * | ||
| 4 | * Copyright 2006-2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Enter bugs at http://blackfin.uclinux.org/ | ||
| 7 | * | ||
| 8 | * Licensed under the GPL-2 or later. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/serial.h> | ||
| 13 | #include <asm/dma.h> | ||
| 14 | #include <asm/portmux.h> | ||
| 15 | |||
| 16 | #define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) | ||
| 17 | #define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) | ||
| 18 | #define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) | ||
| 19 | #define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) | ||
| 20 | #define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) | ||
| 21 | #define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) | ||
| 22 | #define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) | ||
| 23 | |||
| 24 | #define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) | ||
| 25 | #define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) | ||
| 26 | #define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) | ||
| 27 | #define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) | ||
| 28 | #define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) | ||
| 29 | #define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) | ||
| 30 | |||
| 31 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 32 | struct dma_rx_buf { | ||
| 33 | char *buf; | ||
| 34 | int head; | ||
| 35 | int tail; | ||
| 36 | }; | ||
| 37 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 38 | |||
| 39 | struct bfin_sir_port { | ||
| 40 | unsigned char __iomem *membase; | ||
| 41 | unsigned int irq; | ||
| 42 | unsigned int lsr; | ||
| 43 | unsigned long clk; | ||
| 44 | struct net_device *dev; | ||
| 45 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 46 | int tx_done; | ||
| 47 | struct dma_rx_buf rx_dma_buf; | ||
| 48 | struct timer_list rx_dma_timer; | ||
| 49 | int rx_dma_nrows; | ||
| 50 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 51 | unsigned int tx_dma_channel; | ||
| 52 | unsigned int rx_dma_channel; | ||
| 53 | }; | ||
| 54 | |||
| 55 | struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; | ||
| 56 | |||
| 57 | struct bfin_sir_port_res { | ||
| 58 | unsigned long base_addr; | ||
| 59 | int irq; | ||
| 60 | unsigned int rx_dma_channel; | ||
| 61 | unsigned int tx_dma_channel; | ||
| 62 | }; | ||
| 63 | |||
| 64 | struct bfin_sir_port_res bfin_sir_port_resource[] = { | ||
| 65 | #ifdef CONFIG_BFIN_SIR0 | ||
| 66 | { | ||
| 67 | 0xFFC00400, | ||
| 68 | IRQ_UART_RX, | ||
| 69 | CH_UART_RX, | ||
| 70 | CH_UART_TX, | ||
| 71 | }, | ||
| 72 | #endif | ||
| 73 | }; | ||
| 74 | |||
| 75 | int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); | ||
| 76 | |||
| 77 | struct bfin_sir_self { | ||
| 78 | struct bfin_sir_port *sir_port; | ||
| 79 | spinlock_t lock; | ||
| 80 | unsigned int open; | ||
| 81 | int speed; | ||
| 82 | int newspeed; | ||
| 83 | |||
| 84 | struct sk_buff *txskb; | ||
| 85 | struct sk_buff *rxskb; | ||
| 86 | struct net_device_stats stats; | ||
| 87 | struct device *dev; | ||
| 88 | struct irlap_cb *irlap; | ||
| 89 | struct qos_info qos; | ||
| 90 | |||
| 91 | iobuff_t tx_buff; | ||
| 92 | iobuff_t rx_buff; | ||
| 93 | |||
| 94 | struct work_struct work; | ||
| 95 | int mtt; | ||
| 96 | }; | ||
| 97 | |||
| 98 | static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) | ||
| 99 | { | ||
| 100 | unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); | ||
| 101 | port->lsr |= (lsr & (BI|FE|PE|OE)); | ||
| 102 | return lsr | port->lsr; | ||
| 103 | } | ||
| 104 | |||
| 105 | static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) | ||
| 106 | { | ||
| 107 | port->lsr = 0; | ||
| 108 | bfin_read16(port->membase + OFFSET_LSR); | ||
| 109 | } | ||
| 110 | |||
| 111 | #define DRIVER_NAME "bfin_sir" | ||
| 112 | |||
| 113 | static int bfin_sir_hw_init(void) | ||
| 114 | { | ||
| 115 | int ret = -ENODEV; | ||
| 116 | #ifdef CONFIG_BFIN_SIR0 | ||
| 117 | ret = peripheral_request(P_UART0_TX, DRIVER_NAME); | ||
| 118 | if (ret) | ||
| 119 | return ret; | ||
| 120 | ret = peripheral_request(P_UART0_RX, DRIVER_NAME); | ||
| 121 | if (ret) | ||
| 122 | return ret; | ||
| 123 | #endif | ||
| 124 | return ret; | ||
| 125 | } | ||
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h index d80971b4e3aa..045184f81a29 100644 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h | |||
| @@ -44,6 +44,13 @@ | |||
| 44 | 44 | ||
| 45 | #define BFIN_UART_NR_PORTS 1 | 45 | #define BFIN_UART_NR_PORTS 1 |
| 46 | 46 | ||
| 47 | #define CH_UART_RX CH_UART0_RX | ||
| 48 | #define CH_UART_TX CH_UART0_TX | ||
| 49 | |||
| 50 | #define IRQ_UART_ERROR IRQ_UART0_ERROR | ||
| 51 | #define IRQ_UART_RX IRQ_UART0_RX | ||
| 52 | #define IRQ_UART_TX IRQ_UART0_TX | ||
| 53 | |||
| 47 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 54 | #define OFFSET_THR 0x00 /* Transmit Holding register */ |
| 48 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | 55 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ |
| 49 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | 56 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h index 3d8978a52c17..bbc3c8386d48 100644 --- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h | |||
| @@ -39,31 +39,8 @@ | |||
| 39 | /*include core specific register pointer definitions*/ | 39 | /*include core specific register pointer definitions*/ |
| 40 | #include <asm/cdef_LPBlackfin.h> | 40 | #include <asm/cdef_LPBlackfin.h> |
| 41 | 41 | ||
| 42 | #include <asm/system.h> | ||
| 43 | |||
| 44 | /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ | 42 | /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ |
| 45 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | 43 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 46 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 47 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 48 | { | ||
| 49 | unsigned long flags, iwr; | ||
| 50 | |||
| 51 | if (val == bfin_read_PLL_CTL()) | ||
| 52 | return; | ||
| 53 | |||
| 54 | local_irq_save(flags); | ||
| 55 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 56 | iwr = bfin_read32(SIC_IWR); | ||
| 57 | /* Only allow PPL Wakeup) */ | ||
| 58 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
| 59 | |||
| 60 | bfin_write16(PLL_CTL, val); | ||
| 61 | SSYNC(); | ||
| 62 | asm("IDLE;"); | ||
| 63 | |||
| 64 | bfin_write32(SIC_IWR, iwr); | ||
| 65 | local_irq_restore(flags); | ||
| 66 | } | ||
| 67 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | 44 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 68 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) | 45 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) |
| 69 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | 46 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| @@ -72,27 +49,6 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) | |||
| 72 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | 49 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 73 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) | 50 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) |
| 74 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | 51 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| 75 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 76 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 77 | { | ||
| 78 | unsigned long flags, iwr; | ||
| 79 | |||
| 80 | if (val == bfin_read_VR_CTL()) | ||
| 81 | return; | ||
| 82 | |||
| 83 | local_irq_save(flags); | ||
| 84 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 85 | iwr = bfin_read32(SIC_IWR); | ||
| 86 | /* Only allow PPL Wakeup) */ | ||
| 87 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
| 88 | |||
| 89 | bfin_write16(VR_CTL, val); | ||
| 90 | SSYNC(); | ||
| 91 | asm("IDLE;"); | ||
| 92 | |||
| 93 | bfin_write32(SIC_IWR, iwr); | ||
| 94 | local_irq_restore(flags); | ||
| 95 | } | ||
| 96 | 52 | ||
| 97 | /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ | 53 | /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ |
| 98 | #define bfin_read_SWRST() bfin_read16(SWRST) | 54 | #define bfin_read_SWRST() bfin_read16(SWRST) |
| @@ -178,50 +134,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 178 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) | 134 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) |
| 179 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) | 135 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) |
| 180 | 136 | ||
| 181 | |||
| 182 | #if ANOMALY_05000311 | ||
| 183 | #define BFIN_WRITE_FIO_FLAG(name) \ | ||
| 184 | static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\ | ||
| 185 | {\ | ||
| 186 | unsigned long flags;\ | ||
| 187 | local_irq_save(flags);\ | ||
| 188 | bfin_write16(FIO_FLAG_ ## name,val);\ | ||
| 189 | bfin_read_CHIPID();\ | ||
| 190 | local_irq_restore(flags);\ | ||
| 191 | } | ||
| 192 | BFIN_WRITE_FIO_FLAG(D) | ||
| 193 | BFIN_WRITE_FIO_FLAG(C) | ||
| 194 | BFIN_WRITE_FIO_FLAG(S) | ||
| 195 | BFIN_WRITE_FIO_FLAG(T) | ||
| 196 | |||
| 197 | #define BFIN_READ_FIO_FLAG(name) \ | ||
| 198 | static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\ | ||
| 199 | {\ | ||
| 200 | unsigned long flags;\ | ||
| 201 | unsigned short ret;\ | ||
| 202 | local_irq_save(flags);\ | ||
| 203 | ret = bfin_read16(FIO_FLAG_ ## name);\ | ||
| 204 | bfin_read_CHIPID();\ | ||
| 205 | local_irq_restore(flags);\ | ||
| 206 | return ret;\ | ||
| 207 | } | ||
| 208 | BFIN_READ_FIO_FLAG(D) | ||
| 209 | BFIN_READ_FIO_FLAG(C) | ||
| 210 | BFIN_READ_FIO_FLAG(S) | ||
| 211 | BFIN_READ_FIO_FLAG(T) | ||
| 212 | |||
| 213 | #else | ||
| 214 | #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D,val) | ||
| 215 | #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C,val) | ||
| 216 | #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S,val) | ||
| 217 | #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T,val) | ||
| 218 | #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) | ||
| 219 | #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) | ||
| 220 | #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) | ||
| 221 | #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) | ||
| 222 | #endif | ||
| 223 | |||
| 224 | |||
| 225 | /* DMA Controller */ | 137 | /* DMA Controller */ |
| 226 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | 138 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
| 227 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) | 139 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) |
| @@ -764,4 +676,93 @@ BFIN_READ_FIO_FLAG(T) | |||
| 764 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | 676 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) |
| 765 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) | 677 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) |
| 766 | 678 | ||
| 679 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 680 | #include <asm/irq.h> | ||
| 681 | |||
| 682 | #if ANOMALY_05000311 | ||
| 683 | #define BFIN_WRITE_FIO_FLAG(name) \ | ||
| 684 | static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ | ||
| 685 | { \ | ||
| 686 | unsigned long flags; \ | ||
| 687 | local_irq_save_hw(flags); \ | ||
| 688 | bfin_write16(FIO_FLAG_##name, val); \ | ||
| 689 | bfin_read_CHIPID(); \ | ||
| 690 | local_irq_restore_hw(flags); \ | ||
| 691 | } | ||
| 692 | BFIN_WRITE_FIO_FLAG(D) | ||
| 693 | BFIN_WRITE_FIO_FLAG(C) | ||
| 694 | BFIN_WRITE_FIO_FLAG(S) | ||
| 695 | BFIN_WRITE_FIO_FLAG(T) | ||
| 696 | |||
| 697 | #define BFIN_READ_FIO_FLAG(name) \ | ||
| 698 | static inline u16 bfin_read_FIO_FLAG_##name(void) \ | ||
| 699 | { \ | ||
| 700 | unsigned long flags; \ | ||
| 701 | u16 ret; \ | ||
| 702 | local_irq_save_hw(flags); \ | ||
| 703 | ret = bfin_read16(FIO_FLAG_##name); \ | ||
| 704 | bfin_read_CHIPID(); \ | ||
| 705 | local_irq_restore_hw(flags); \ | ||
| 706 | return ret; \ | ||
| 707 | } | ||
| 708 | BFIN_READ_FIO_FLAG(D) | ||
| 709 | BFIN_READ_FIO_FLAG(C) | ||
| 710 | BFIN_READ_FIO_FLAG(S) | ||
| 711 | BFIN_READ_FIO_FLAG(T) | ||
| 712 | |||
| 713 | #else | ||
| 714 | #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) | ||
| 715 | #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) | ||
| 716 | #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) | ||
| 717 | #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) | ||
| 718 | #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) | ||
| 719 | #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) | ||
| 720 | #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) | ||
| 721 | #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) | ||
| 722 | #endif | ||
| 723 | |||
| 724 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 725 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 726 | { | ||
| 727 | unsigned long flags, iwr; | ||
| 728 | |||
| 729 | if (val == bfin_read_PLL_CTL()) | ||
| 730 | return; | ||
| 731 | |||
| 732 | local_irq_save_hw(flags); | ||
| 733 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 734 | iwr = bfin_read32(SIC_IWR); | ||
| 735 | /* Only allow PPL Wakeup) */ | ||
| 736 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
| 737 | |||
| 738 | bfin_write16(PLL_CTL, val); | ||
| 739 | SSYNC(); | ||
| 740 | asm("IDLE;"); | ||
| 741 | |||
| 742 | bfin_write32(SIC_IWR, iwr); | ||
| 743 | local_irq_restore_hw(flags); | ||
| 744 | } | ||
| 745 | |||
| 746 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 747 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 748 | { | ||
| 749 | unsigned long flags, iwr; | ||
| 750 | |||
| 751 | if (val == bfin_read_VR_CTL()) | ||
| 752 | return; | ||
| 753 | |||
| 754 | local_irq_save_hw(flags); | ||
| 755 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 756 | iwr = bfin_read32(SIC_IWR); | ||
| 757 | /* Only allow PPL Wakeup) */ | ||
| 758 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
| 759 | |||
| 760 | bfin_write16(VR_CTL, val); | ||
| 761 | SSYNC(); | ||
| 762 | asm("IDLE;"); | ||
| 763 | |||
| 764 | bfin_write32(SIC_IWR, iwr); | ||
| 765 | local_irq_restore_hw(flags); | ||
| 766 | } | ||
| 767 | |||
| 767 | #endif /* _CDEF_BF532_H */ | 768 | #endif /* _CDEF_BF532_H */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h index bd9d5e94307d..fb34934c5ba8 100644 --- a/arch/blackfin/mach-bf533/include/mach/dma.h +++ b/arch/blackfin/mach-bf533/include/mach/dma.h | |||
| @@ -1,42 +1,14 @@ | |||
| 1 | /***************************************************************************** | 1 | /* mach/dma.h - arch-specific DMA defines |
| 2 | * | ||
| 3 | * BF-533/2/1 Specific Declarations | ||
| 4 | * | ||
| 5 | ****************************************************************************/ | ||
| 6 | /* | ||
| 7 | * File: include/asm-blackfin/mach-bf533/dma.h | ||
| 8 | * Based on: | ||
| 9 | * Author: | ||
| 10 | * | 2 | * |
| 11 | * Created: | 3 | * Copyright 2004-2008 Analog Devices Inc. |
| 12 | * Description: | ||
| 13 | * | 4 | * |
| 14 | * Rev: | 5 | * Licensed under the GPL-2 or later. |
| 15 | * | ||
| 16 | * Modified: | ||
| 17 | * | ||
| 18 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 19 | * | ||
| 20 | * This program is free software; you can redistribute it and/or modify | ||
| 21 | * it under the terms of the GNU General Public License as published by | ||
| 22 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 23 | * any later version. | ||
| 24 | * | ||
| 25 | * This program is distributed in the hope that it will be useful, | ||
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 28 | * GNU General Public License for more details. | ||
| 29 | * | ||
| 30 | * You should have received a copy of the GNU General Public License | ||
| 31 | * along with this program; see the file COPYING. | ||
| 32 | * If not, write to the Free Software Foundation, | ||
| 33 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 34 | */ | 6 | */ |
| 35 | 7 | ||
| 36 | #ifndef _MACH_DMA_H_ | 8 | #ifndef _MACH_DMA_H_ |
| 37 | #define _MACH_DMA_H_ | 9 | #define _MACH_DMA_H_ |
| 38 | 10 | ||
| 39 | #define MAX_BLACKFIN_DMA_CHANNEL 12 | 11 | #define MAX_DMA_CHANNELS 12 |
| 40 | 12 | ||
| 41 | #define CH_PPI 0 | 13 | #define CH_PPI 0 |
| 42 | #define CH_SPORT0_RX 1 | 14 | #define CH_SPORT0_RX 1 |
| @@ -44,8 +16,8 @@ | |||
| 44 | #define CH_SPORT1_RX 3 | 16 | #define CH_SPORT1_RX 3 |
| 45 | #define CH_SPORT1_TX 4 | 17 | #define CH_SPORT1_TX 4 |
| 46 | #define CH_SPI 5 | 18 | #define CH_SPI 5 |
| 47 | #define CH_UART_RX 6 | 19 | #define CH_UART0_RX 6 |
| 48 | #define CH_UART_TX 7 | 20 | #define CH_UART0_TX 7 |
| 49 | #define CH_MEM_STREAM0_DEST 8 /* TX */ | 21 | #define CH_MEM_STREAM0_DEST 8 /* TX */ |
| 50 | #define CH_MEM_STREAM0_SRC 9 /* RX */ | 22 | #define CH_MEM_STREAM0_SRC 9 /* RX */ |
| 51 | #define CH_MEM_STREAM1_DEST 10 /* TX */ | 23 | #define CH_MEM_STREAM1_DEST 10 /* TX */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h new file mode 100644 index 000000000000..e45c17077aff --- /dev/null +++ b/arch/blackfin/mach-bf533/include/mach/gpio.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf533/include/mach/gpio.h | ||
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 4 | * | ||
| 5 | * Copyright (C) 2008 Analog Devices Inc. | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | #ifndef _MACH_GPIO_H_ | ||
| 11 | #define _MACH_GPIO_H_ | ||
| 12 | |||
| 13 | #define MAX_BLACKFIN_GPIOS 16 | ||
| 14 | |||
| 15 | #define GPIO_PF0 0 | ||
| 16 | #define GPIO_PF1 1 | ||
| 17 | #define GPIO_PF2 2 | ||
| 18 | #define GPIO_PF3 3 | ||
| 19 | #define GPIO_PF4 4 | ||
| 20 | #define GPIO_PF5 5 | ||
| 21 | #define GPIO_PF6 6 | ||
| 22 | #define GPIO_PF7 7 | ||
| 23 | #define GPIO_PF8 8 | ||
| 24 | #define GPIO_PF9 9 | ||
| 25 | #define GPIO_PF10 10 | ||
| 26 | #define GPIO_PF11 11 | ||
| 27 | #define GPIO_PF12 12 | ||
| 28 | #define GPIO_PF13 13 | ||
| 29 | #define GPIO_PF14 14 | ||
| 30 | #define GPIO_PF15 15 | ||
| 31 | |||
| 32 | #define PORT_F GPIO_PF0 | ||
| 33 | |||
| 34 | #endif /* _MACH_GPIO_H_ */ | ||
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h index 5aa38e5da6b7..db1e346cd1aa 100644 --- a/arch/blackfin/mach-bf533/include/mach/irq.h +++ b/arch/blackfin/mach-bf533/include/mach/irq.h | |||
| @@ -90,19 +90,19 @@ Core Emulation ** | |||
| 90 | #define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ | 90 | #define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ |
| 91 | #define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ | 91 | #define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ |
| 92 | #define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ | 92 | #define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ |
| 93 | #define IRQ_UART_ERROR 13 /*UART Error Interrupt */ | 93 | #define IRQ_UART0_ERROR 13 /*UART Error Interrupt */ |
| 94 | #define IRQ_RTC 14 /*RTC Interrupt */ | 94 | #define IRQ_RTC 14 /*RTC Interrupt */ |
| 95 | #define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ | 95 | #define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ |
| 96 | #define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ | 96 | #define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ |
| 97 | #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ | 97 | #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ |
| 98 | #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ | 98 | #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ |
| 99 | #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ | 99 | #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ |
| 100 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ | 100 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ |
| 101 | #define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ | 101 | #define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */ |
| 102 | #define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ | 102 | #define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */ |
| 103 | #define IRQ_TMR0 23 /*Timer 0 */ | 103 | #define IRQ_TIMER0 23 /*Timer 0 */ |
| 104 | #define IRQ_TMR1 24 /*Timer 1 */ | 104 | #define IRQ_TIMER1 24 /*Timer 1 */ |
| 105 | #define IRQ_TMR2 25 /*Timer 2 */ | 105 | #define IRQ_TIMER2 25 /*Timer 2 */ |
| 106 | #define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ | 106 | #define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ |
| 107 | #define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ | 107 | #define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ |
| 108 | #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ | 108 | #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_init.h b/arch/blackfin/mach-bf533/include/mach/mem_init.h deleted file mode 100644 index ed2034bf10ec..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/mem_init.h +++ /dev/null | |||
| @@ -1,297 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf533/mem_init.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \ | ||
| 33 | CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD) | ||
| 34 | #if (CONFIG_SCLK_HZ > 119402985) | ||
| 35 | #define SDRAM_tRP TRP_2 | ||
| 36 | #define SDRAM_tRP_num 2 | ||
| 37 | #define SDRAM_tRAS TRAS_7 | ||
| 38 | #define SDRAM_tRAS_num 7 | ||
| 39 | #define SDRAM_tRCD TRCD_2 | ||
| 40 | #define SDRAM_tWR TWR_2 | ||
| 41 | #endif | ||
| 42 | #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) | ||
| 43 | #define SDRAM_tRP TRP_2 | ||
| 44 | #define SDRAM_tRP_num 2 | ||
| 45 | #define SDRAM_tRAS TRAS_6 | ||
| 46 | #define SDRAM_tRAS_num 6 | ||
| 47 | #define SDRAM_tRCD TRCD_2 | ||
| 48 | #define SDRAM_tWR TWR_2 | ||
| 49 | #endif | ||
| 50 | #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) | ||
| 51 | #define SDRAM_tRP TRP_2 | ||
| 52 | #define SDRAM_tRP_num 2 | ||
| 53 | #define SDRAM_tRAS TRAS_5 | ||
| 54 | #define SDRAM_tRAS_num 5 | ||
| 55 | #define SDRAM_tRCD TRCD_2 | ||
| 56 | #define SDRAM_tWR TWR_2 | ||
| 57 | #endif | ||
| 58 | #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) | ||
| 59 | #define SDRAM_tRP TRP_2 | ||
| 60 | #define SDRAM_tRP_num 2 | ||
| 61 | #define SDRAM_tRAS TRAS_4 | ||
| 62 | #define SDRAM_tRAS_num 4 | ||
| 63 | #define SDRAM_tRCD TRCD_2 | ||
| 64 | #define SDRAM_tWR TWR_2 | ||
| 65 | #endif | ||
| 66 | #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) | ||
| 67 | #define SDRAM_tRP TRP_2 | ||
| 68 | #define SDRAM_tRP_num 2 | ||
| 69 | #define SDRAM_tRAS TRAS_3 | ||
| 70 | #define SDRAM_tRAS_num 3 | ||
| 71 | #define SDRAM_tRCD TRCD_2 | ||
| 72 | #define SDRAM_tWR TWR_2 | ||
| 73 | #endif | ||
| 74 | #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) | ||
| 75 | #define SDRAM_tRP TRP_1 | ||
| 76 | #define SDRAM_tRP_num 1 | ||
| 77 | #define SDRAM_tRAS TRAS_4 | ||
| 78 | #define SDRAM_tRAS_num 3 | ||
| 79 | #define SDRAM_tRCD TRCD_1 | ||
| 80 | #define SDRAM_tWR TWR_2 | ||
| 81 | #endif | ||
| 82 | #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) | ||
| 83 | #define SDRAM_tRP TRP_1 | ||
| 84 | #define SDRAM_tRP_num 1 | ||
| 85 | #define SDRAM_tRAS TRAS_3 | ||
| 86 | #define SDRAM_tRAS_num 3 | ||
| 87 | #define SDRAM_tRCD TRCD_1 | ||
| 88 | #define SDRAM_tWR TWR_2 | ||
| 89 | #endif | ||
| 90 | #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) | ||
| 91 | #define SDRAM_tRP TRP_1 | ||
| 92 | #define SDRAM_tRP_num 1 | ||
| 93 | #define SDRAM_tRAS TRAS_2 | ||
| 94 | #define SDRAM_tRAS_num 2 | ||
| 95 | #define SDRAM_tRCD TRCD_1 | ||
| 96 | #define SDRAM_tWR TWR_2 | ||
| 97 | #endif | ||
| 98 | #if (CONFIG_SCLK_HZ <= 29850746) | ||
| 99 | #define SDRAM_tRP TRP_1 | ||
| 100 | #define SDRAM_tRP_num 1 | ||
| 101 | #define SDRAM_tRAS TRAS_1 | ||
| 102 | #define SDRAM_tRAS_num 1 | ||
| 103 | #define SDRAM_tRCD TRCD_1 | ||
| 104 | #define SDRAM_tWR TWR_2 | ||
| 105 | #endif | ||
| 106 | #endif | ||
| 107 | |||
| 108 | #if (CONFIG_MEM_MT48LC16M16A2TG_75) | ||
| 109 | /*SDRAM INFORMATION: */ | ||
| 110 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 111 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 112 | #define SDRAM_CL CL_3 | ||
| 113 | #endif | ||
| 114 | |||
| 115 | #if (CONFIG_MEM_MT48LC64M4A2FB_7E) | ||
| 116 | /*SDRAM INFORMATION: */ | ||
| 117 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 118 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 119 | #define SDRAM_CL CL_3 | ||
| 120 | #endif | ||
| 121 | |||
| 122 | #if (CONFIG_MEM_MT48LC32M16A2TG_75) | ||
| 123 | /*SDRAM INFORMATION: */ | ||
| 124 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 125 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 126 | #define SDRAM_CL CL_3 | ||
| 127 | #endif | ||
| 128 | |||
| 129 | #if (CONFIG_MEM_GENERIC_BOARD) | ||
| 130 | /*SDRAM INFORMATION: Modify this for your board */ | ||
| 131 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 132 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 133 | #define SDRAM_CL CL_3 | ||
| 134 | #endif | ||
| 135 | |||
| 136 | /* Equation from section 17 (p17-46) of BF533 HRM */ | ||
| 137 | #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) | ||
| 138 | |||
| 139 | /* Enable SCLK Out */ | ||
| 140 | #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) | ||
| 141 | |||
| 142 | #if defined CONFIG_CLKIN_HALF | ||
| 143 | #define CLKIN_HALF 1 | ||
| 144 | #else | ||
| 145 | #define CLKIN_HALF 0 | ||
| 146 | #endif | ||
| 147 | |||
| 148 | #if defined CONFIG_PLL_BYPASS | ||
| 149 | #define PLL_BYPASS 1 | ||
| 150 | #else | ||
| 151 | #define PLL_BYPASS 0 | ||
| 152 | #endif | ||
| 153 | |||
| 154 | /***************************************Currently Not Being Used *********************************/ | ||
| 155 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 156 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 157 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) | ||
| 158 | #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 159 | #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 160 | |||
| 161 | #if (flash_EBIU_AMBCTL_TT > 3) | ||
| 162 | #define flash_EBIU_AMBCTL0_TT B0TT_4 | ||
| 163 | #endif | ||
| 164 | #if (flash_EBIU_AMBCTL_TT == 3) | ||
| 165 | #define flash_EBIU_AMBCTL0_TT B0TT_3 | ||
| 166 | #endif | ||
| 167 | #if (flash_EBIU_AMBCTL_TT == 2) | ||
| 168 | #define flash_EBIU_AMBCTL0_TT B0TT_2 | ||
| 169 | #endif | ||
| 170 | #if (flash_EBIU_AMBCTL_TT < 2) | ||
| 171 | #define flash_EBIU_AMBCTL0_TT B0TT_1 | ||
| 172 | #endif | ||
| 173 | |||
| 174 | #if (flash_EBIU_AMBCTL_ST > 3) | ||
| 175 | #define flash_EBIU_AMBCTL0_ST B0ST_4 | ||
| 176 | #endif | ||
| 177 | #if (flash_EBIU_AMBCTL_ST == 3) | ||
| 178 | #define flash_EBIU_AMBCTL0_ST B0ST_3 | ||
| 179 | #endif | ||
| 180 | #if (flash_EBIU_AMBCTL_ST == 2) | ||
| 181 | #define flash_EBIU_AMBCTL0_ST B0ST_2 | ||
| 182 | #endif | ||
| 183 | #if (flash_EBIU_AMBCTL_ST < 2) | ||
| 184 | #define flash_EBIU_AMBCTL0_ST B0ST_1 | ||
| 185 | #endif | ||
| 186 | |||
| 187 | #if (flash_EBIU_AMBCTL_HT > 2) | ||
| 188 | #define flash_EBIU_AMBCTL0_HT B0HT_3 | ||
| 189 | #endif | ||
| 190 | #if (flash_EBIU_AMBCTL_HT == 2) | ||
| 191 | #define flash_EBIU_AMBCTL0_HT B0HT_2 | ||
| 192 | #endif | ||
| 193 | #if (flash_EBIU_AMBCTL_HT == 1) | ||
| 194 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 195 | #endif | ||
| 196 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) | ||
| 197 | #define flash_EBIU_AMBCTL0_HT B0HT_0 | ||
| 198 | #endif | ||
| 199 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) | ||
| 200 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 201 | #endif | ||
| 202 | |||
| 203 | #if (flash_EBIU_AMBCTL_WAT > 14) | ||
| 204 | #define flash_EBIU_AMBCTL0_WAT B0WAT_15 | ||
| 205 | #endif | ||
| 206 | #if (flash_EBIU_AMBCTL_WAT == 14) | ||
| 207 | #define flash_EBIU_AMBCTL0_WAT B0WAT_14 | ||
| 208 | #endif | ||
| 209 | #if (flash_EBIU_AMBCTL_WAT == 13) | ||
| 210 | #define flash_EBIU_AMBCTL0_WAT B0WAT_13 | ||
| 211 | #endif | ||
| 212 | #if (flash_EBIU_AMBCTL_WAT == 12) | ||
| 213 | #define flash_EBIU_AMBCTL0_WAT B0WAT_12 | ||
| 214 | #endif | ||
| 215 | #if (flash_EBIU_AMBCTL_WAT == 11) | ||
| 216 | #define flash_EBIU_AMBCTL0_WAT B0WAT_11 | ||
| 217 | #endif | ||
| 218 | #if (flash_EBIU_AMBCTL_WAT == 10) | ||
| 219 | #define flash_EBIU_AMBCTL0_WAT B0WAT_10 | ||
| 220 | #endif | ||
| 221 | #if (flash_EBIU_AMBCTL_WAT == 9) | ||
| 222 | #define flash_EBIU_AMBCTL0_WAT B0WAT_9 | ||
| 223 | #endif | ||
| 224 | #if (flash_EBIU_AMBCTL_WAT == 8) | ||
| 225 | #define flash_EBIU_AMBCTL0_WAT B0WAT_8 | ||
| 226 | #endif | ||
| 227 | #if (flash_EBIU_AMBCTL_WAT == 7) | ||
| 228 | #define flash_EBIU_AMBCTL0_WAT B0WAT_7 | ||
| 229 | #endif | ||
| 230 | #if (flash_EBIU_AMBCTL_WAT == 6) | ||
| 231 | #define flash_EBIU_AMBCTL0_WAT B0WAT_6 | ||
| 232 | #endif | ||
| 233 | #if (flash_EBIU_AMBCTL_WAT == 5) | ||
| 234 | #define flash_EBIU_AMBCTL0_WAT B0WAT_5 | ||
| 235 | #endif | ||
| 236 | #if (flash_EBIU_AMBCTL_WAT == 4) | ||
| 237 | #define flash_EBIU_AMBCTL0_WAT B0WAT_4 | ||
| 238 | #endif | ||
| 239 | #if (flash_EBIU_AMBCTL_WAT == 3) | ||
| 240 | #define flash_EBIU_AMBCTL0_WAT B0WAT_3 | ||
| 241 | #endif | ||
| 242 | #if (flash_EBIU_AMBCTL_WAT == 2) | ||
| 243 | #define flash_EBIU_AMBCTL0_WAT B0WAT_2 | ||
| 244 | #endif | ||
| 245 | #if (flash_EBIU_AMBCTL_WAT == 1) | ||
| 246 | #define flash_EBIU_AMBCTL0_WAT B0WAT_1 | ||
| 247 | #endif | ||
| 248 | |||
| 249 | #if (flash_EBIU_AMBCTL_RAT > 14) | ||
| 250 | #define flash_EBIU_AMBCTL0_RAT B0RAT_15 | ||
| 251 | #endif | ||
| 252 | #if (flash_EBIU_AMBCTL_RAT == 14) | ||
| 253 | #define flash_EBIU_AMBCTL0_RAT B0RAT_14 | ||
| 254 | #endif | ||
| 255 | #if (flash_EBIU_AMBCTL_RAT == 13) | ||
| 256 | #define flash_EBIU_AMBCTL0_RAT B0RAT_13 | ||
| 257 | #endif | ||
| 258 | #if (flash_EBIU_AMBCTL_RAT == 12) | ||
| 259 | #define flash_EBIU_AMBCTL0_RAT B0RAT_12 | ||
| 260 | #endif | ||
| 261 | #if (flash_EBIU_AMBCTL_RAT == 11) | ||
| 262 | #define flash_EBIU_AMBCTL0_RAT B0RAT_11 | ||
| 263 | #endif | ||
| 264 | #if (flash_EBIU_AMBCTL_RAT == 10) | ||
| 265 | #define flash_EBIU_AMBCTL0_RAT B0RAT_10 | ||
| 266 | #endif | ||
| 267 | #if (flash_EBIU_AMBCTL_RAT == 9) | ||
| 268 | #define flash_EBIU_AMBCTL0_RAT B0RAT_9 | ||
| 269 | #endif | ||
| 270 | #if (flash_EBIU_AMBCTL_RAT == 8) | ||
| 271 | #define flash_EBIU_AMBCTL0_RAT B0RAT_8 | ||
| 272 | #endif | ||
| 273 | #if (flash_EBIU_AMBCTL_RAT == 7) | ||
| 274 | #define flash_EBIU_AMBCTL0_RAT B0RAT_7 | ||
| 275 | #endif | ||
| 276 | #if (flash_EBIU_AMBCTL_RAT == 6) | ||
| 277 | #define flash_EBIU_AMBCTL0_RAT B0RAT_6 | ||
| 278 | #endif | ||
| 279 | #if (flash_EBIU_AMBCTL_RAT == 5) | ||
| 280 | #define flash_EBIU_AMBCTL0_RAT B0RAT_5 | ||
| 281 | #endif | ||
| 282 | #if (flash_EBIU_AMBCTL_RAT == 4) | ||
| 283 | #define flash_EBIU_AMBCTL0_RAT B0RAT_4 | ||
| 284 | #endif | ||
| 285 | #if (flash_EBIU_AMBCTL_RAT == 3) | ||
| 286 | #define flash_EBIU_AMBCTL0_RAT B0RAT_3 | ||
| 287 | #endif | ||
| 288 | #if (flash_EBIU_AMBCTL_RAT == 2) | ||
| 289 | #define flash_EBIU_AMBCTL0_RAT B0RAT_2 | ||
| 290 | #endif | ||
| 291 | #if (flash_EBIU_AMBCTL_RAT == 1) | ||
| 292 | #define flash_EBIU_AMBCTL0_RAT B0RAT_1 | ||
| 293 | #endif | ||
| 294 | |||
| 295 | #define flash_EBIU_AMBCTL0 \ | ||
| 296 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ | ||
| 297 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) | ||
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h index 581fc6eea789..fc33b7cb9937 100644 --- a/arch/blackfin/mach-bf533/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h | |||
| @@ -168,4 +168,10 @@ | |||
| 168 | #define L1_SCRATCH_START 0xFFB00000 | 168 | #define L1_SCRATCH_START 0xFFB00000 |
| 169 | #define L1_SCRATCH_LENGTH 0x1000 | 169 | #define L1_SCRATCH_LENGTH 0x1000 |
| 170 | 170 | ||
| 171 | #define GET_PDA_SAFE(preg) \ | ||
| 172 | preg.l = _cpu_pda; \ | ||
| 173 | preg.h = _cpu_pda; | ||
| 174 | |||
| 175 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 176 | |||
| 171 | #endif /* _MEM_MAP_533_H_ */ | 177 | #endif /* _MEM_MAP_533_H_ */ |
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig index 8255374c04aa..bbc08fd4f122 100644 --- a/arch/blackfin/mach-bf537/Kconfig +++ b/arch/blackfin/mach-bf537/Kconfig | |||
| @@ -64,29 +64,29 @@ config IRQ_MAC_RX | |||
| 64 | config IRQ_MAC_TX | 64 | config IRQ_MAC_TX |
| 65 | int "IRQ_MAC_TX" | 65 | int "IRQ_MAC_TX" |
| 66 | default 11 | 66 | default 11 |
| 67 | config IRQ_TMR0 | 67 | config IRQ_TIMER0 |
| 68 | int "IRQ_TMR0" | 68 | int "IRQ_TIMER0" |
| 69 | default 12 | 69 | default 8 |
| 70 | config IRQ_TMR1 | 70 | config IRQ_TIMER1 |
| 71 | int "IRQ_TMR1" | 71 | int "IRQ_TIMER1" |
| 72 | default 12 | 72 | default 12 |
| 73 | config IRQ_TMR2 | 73 | config IRQ_TIMER2 |
| 74 | int "IRQ_TMR2" | 74 | int "IRQ_TIMER2" |
| 75 | default 12 | 75 | default 12 |
| 76 | config IRQ_TMR3 | 76 | config IRQ_TIMER3 |
| 77 | int "IRQ_TMR3" | 77 | int "IRQ_TIMER3" |
| 78 | default 12 | 78 | default 12 |
| 79 | config IRQ_TMR4 | 79 | config IRQ_TIMER4 |
| 80 | int "IRQ_TMR4" | 80 | int "IRQ_TIMER4" |
| 81 | default 12 | 81 | default 12 |
| 82 | config IRQ_TMR5 | 82 | config IRQ_TIMER5 |
| 83 | int "IRQ_TMR5" | 83 | int "IRQ_TIMER5" |
| 84 | default 12 | 84 | default 12 |
| 85 | config IRQ_TMR6 | 85 | config IRQ_TIMER6 |
| 86 | int "IRQ_TMR6" | 86 | int "IRQ_TIMER6" |
| 87 | default 12 | 87 | default 12 |
| 88 | config IRQ_TMR7 | 88 | config IRQ_TIMER7 |
| 89 | int "IRQ_TMR7" | 89 | int "IRQ_TIMER7" |
| 90 | default 12 | 90 | default 12 |
| 91 | config IRQ_PROG_INTA | 91 | config IRQ_PROG_INTA |
| 92 | int "IRQ_PROG_INTA" | 92 | int "IRQ_PROG_INTA" |
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile index 68e5478e95a9..56994b675f9c 100644 --- a/arch/blackfin/mach-bf537/Makefile +++ b/arch/blackfin/mach-bf537/Makefile | |||
| @@ -2,6 +2,4 @@ | |||
| 2 | # arch/blackfin/mach-bf537/Makefile | 2 | # arch/blackfin/mach-bf537/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | extra-y := head.o | ||
| 6 | |||
| 7 | obj-y := ints-priority.o dma.o | 5 | obj-y := ints-priority.o dma.o |
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index dde14720b0ea..6ac8e4d5bd38 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c | |||
| @@ -308,6 +308,19 @@ static struct platform_device net2272_bfin_device = { | |||
| 308 | }; | 308 | }; |
| 309 | #endif | 309 | #endif |
| 310 | 310 | ||
| 311 | static struct resource bfin_gpios_resources = { | ||
| 312 | .start = 0, | ||
| 313 | .end = MAX_BLACKFIN_GPIOS - 1, | ||
| 314 | .flags = IORESOURCE_IRQ, | ||
| 315 | }; | ||
| 316 | |||
| 317 | static struct platform_device bfin_gpios_device = { | ||
| 318 | .name = "simple-gpio", | ||
| 319 | .id = -1, | ||
| 320 | .num_resources = 1, | ||
| 321 | .resource = &bfin_gpios_resources, | ||
| 322 | }; | ||
| 323 | |||
| 311 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) | 324 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) |
| 312 | static struct mtd_partition cm_partitions[] = { | 325 | static struct mtd_partition cm_partitions[] = { |
| 313 | { | 326 | { |
| @@ -379,30 +392,57 @@ static struct platform_device bfin_uart_device = { | |||
| 379 | #endif | 392 | #endif |
| 380 | 393 | ||
| 381 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 394 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 382 | static struct resource bfin_sir_resources[] = { | ||
| 383 | #ifdef CONFIG_BFIN_SIR0 | 395 | #ifdef CONFIG_BFIN_SIR0 |
| 396 | static struct resource bfin_sir0_resources[] = { | ||
| 384 | { | 397 | { |
| 385 | .start = 0xFFC00400, | 398 | .start = 0xFFC00400, |
| 386 | .end = 0xFFC004FF, | 399 | .end = 0xFFC004FF, |
| 387 | .flags = IORESOURCE_MEM, | 400 | .flags = IORESOURCE_MEM, |
| 388 | }, | 401 | }, |
| 402 | { | ||
| 403 | .start = IRQ_UART0_RX, | ||
| 404 | .end = IRQ_UART0_RX+1, | ||
| 405 | .flags = IORESOURCE_IRQ, | ||
| 406 | }, | ||
| 407 | { | ||
| 408 | .start = CH_UART0_RX, | ||
| 409 | .end = CH_UART0_RX+1, | ||
| 410 | .flags = IORESOURCE_DMA, | ||
| 411 | }, | ||
| 412 | }; | ||
| 413 | static struct platform_device bfin_sir0_device = { | ||
| 414 | .name = "bfin_sir", | ||
| 415 | .id = 0, | ||
| 416 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 417 | .resource = bfin_sir0_resources, | ||
| 418 | }; | ||
| 389 | #endif | 419 | #endif |
| 390 | #ifdef CONFIG_BFIN_SIR1 | 420 | #ifdef CONFIG_BFIN_SIR1 |
| 421 | static struct resource bfin_sir1_resources[] = { | ||
| 391 | { | 422 | { |
| 392 | .start = 0xFFC02000, | 423 | .start = 0xFFC02000, |
| 393 | .end = 0xFFC020FF, | 424 | .end = 0xFFC020FF, |
| 394 | .flags = IORESOURCE_MEM, | 425 | .flags = IORESOURCE_MEM, |
| 395 | }, | 426 | }, |
| 396 | #endif | 427 | { |
| 428 | .start = IRQ_UART1_RX, | ||
| 429 | .end = IRQ_UART1_RX+1, | ||
| 430 | .flags = IORESOURCE_IRQ, | ||
| 431 | }, | ||
| 432 | { | ||
| 433 | .start = CH_UART1_RX, | ||
| 434 | .end = CH_UART1_RX+1, | ||
| 435 | .flags = IORESOURCE_DMA, | ||
| 436 | }, | ||
| 397 | }; | 437 | }; |
| 398 | 438 | static struct platform_device bfin_sir1_device = { | |
| 399 | static struct platform_device bfin_sir_device = { | ||
| 400 | .name = "bfin_sir", | 439 | .name = "bfin_sir", |
| 401 | .id = 0, | 440 | .id = 1, |
| 402 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 441 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 403 | .resource = bfin_sir_resources, | 442 | .resource = bfin_sir1_resources, |
| 404 | }; | 443 | }; |
| 405 | #endif | 444 | #endif |
| 445 | #endif | ||
| 406 | 446 | ||
| 407 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 447 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 408 | static struct resource bfin_twi0_resource[] = { | 448 | static struct resource bfin_twi0_resource[] = { |
| @@ -525,7 +565,12 @@ static struct platform_device *cm_bf537_devices[] __initdata = { | |||
| 525 | #endif | 565 | #endif |
| 526 | 566 | ||
| 527 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 567 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 528 | &bfin_sir_device, | 568 | #ifdef CONFIG_BFIN_SIR0 |
| 569 | &bfin_sir0_device, | ||
| 570 | #endif | ||
| 571 | #ifdef CONFIG_BFIN_SIR1 | ||
| 572 | &bfin_sir1_device, | ||
| 573 | #endif | ||
| 529 | #endif | 574 | #endif |
| 530 | 575 | ||
| 531 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 576 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| @@ -564,6 +609,8 @@ static struct platform_device *cm_bf537_devices[] __initdata = { | |||
| 564 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) | 609 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) |
| 565 | &cm_flash_device, | 610 | &cm_flash_device, |
| 566 | #endif | 611 | #endif |
| 612 | |||
| 613 | &bfin_gpios_device, | ||
| 567 | }; | 614 | }; |
| 568 | 615 | ||
| 569 | static int __init cm_bf537_init(void) | 616 | static int __init cm_bf537_init(void) |
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c index 78a13d5bfd55..dd6e6bfb98ea 100644 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ b/arch/blackfin/mach-bf537/boards/generic_board.c | |||
| @@ -50,57 +50,46 @@ | |||
| 50 | /* | 50 | /* |
| 51 | * Name the Board for the /proc/cpuinfo | 51 | * Name the Board for the /proc/cpuinfo |
| 52 | */ | 52 | */ |
| 53 | const char bfin_board_name[] = "GENERIC Board"; | 53 | const char bfin_board_name[] = "UNKNOWN BOARD"; |
| 54 | 54 | ||
| 55 | /* | 55 | /* |
| 56 | * Driver needs to know address, irq and flag pin. | 56 | * Driver needs to know address, irq and flag pin. |
| 57 | */ | 57 | */ |
| 58 | 58 | ||
| 59 | #define ISP1761_BASE 0x203C0000 | ||
| 60 | #define ISP1761_IRQ IRQ_PF7 | ||
| 61 | |||
| 62 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | 59 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
| 63 | static struct resource bfin_isp1761_resources[] = { | 60 | #include <linux/usb/isp1760.h> |
| 61 | static struct resource bfin_isp1760_resources[] = { | ||
| 64 | [0] = { | 62 | [0] = { |
| 65 | .name = "isp1761-regs", | 63 | .start = 0x203C0000, |
| 66 | .start = ISP1761_BASE + 0x00000000, | 64 | .end = 0x203C0000 + 0x000fffff, |
| 67 | .end = ISP1761_BASE + 0x000fffff, | ||
| 68 | .flags = IORESOURCE_MEM, | 65 | .flags = IORESOURCE_MEM, |
| 69 | }, | 66 | }, |
| 70 | [1] = { | 67 | [1] = { |
| 71 | .start = ISP1761_IRQ, | 68 | .start = IRQ_PF7, |
| 72 | .end = ISP1761_IRQ, | 69 | .end = IRQ_PF7, |
| 73 | .flags = IORESOURCE_IRQ, | 70 | .flags = IORESOURCE_IRQ, |
| 74 | }, | 71 | }, |
| 75 | }; | 72 | }; |
| 76 | 73 | ||
| 77 | static struct platform_device bfin_isp1761_device = { | 74 | static struct isp1760_platform_data isp1760_priv = { |
| 78 | .name = "isp1761", | 75 | .is_isp1761 = 0, |
| 79 | .id = 0, | 76 | .port1_disable = 0, |
| 80 | .num_resources = ARRAY_SIZE(bfin_isp1761_resources), | 77 | .bus_width_16 = 1, |
| 81 | .resource = bfin_isp1761_resources, | 78 | .port1_otg = 0, |
| 79 | .analog_oc = 0, | ||
| 80 | .dack_polarity_high = 0, | ||
| 81 | .dreq_polarity_high = 0, | ||
| 82 | }; | 82 | }; |
| 83 | 83 | ||
| 84 | static struct platform_device *bfin_isp1761_devices[] = { | 84 | static struct platform_device bfin_isp1760_device = { |
| 85 | &bfin_isp1761_device, | 85 | .name = "isp1760-hcd", |
| 86 | .id = 0, | ||
| 87 | .dev = { | ||
| 88 | .platform_data = &isp1760_priv, | ||
| 89 | }, | ||
| 90 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | ||
| 91 | .resource = bfin_isp1760_resources, | ||
| 86 | }; | 92 | }; |
| 87 | |||
| 88 | int __init bfin_isp1761_init(void) | ||
| 89 | { | ||
| 90 | unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); | ||
| 91 | |||
| 92 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 93 | set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); | ||
| 94 | |||
| 95 | return platform_add_devices(bfin_isp1761_devices, num_devices); | ||
| 96 | } | ||
| 97 | |||
| 98 | void __exit bfin_isp1761_exit(void) | ||
| 99 | { | ||
| 100 | platform_device_unregister(&bfin_isp1761_device); | ||
| 101 | } | ||
| 102 | |||
| 103 | arch_initcall(bfin_isp1761_init); | ||
| 104 | #endif | 93 | #endif |
| 105 | 94 | ||
| 106 | #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) | 95 | #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) |
| @@ -559,30 +548,59 @@ static struct platform_device bfin_uart_device = { | |||
| 559 | #endif | 548 | #endif |
| 560 | 549 | ||
| 561 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 550 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 562 | static struct resource bfin_sir_resources[] = { | ||
| 563 | #ifdef CONFIG_BFIN_SIR0 | 551 | #ifdef CONFIG_BFIN_SIR0 |
| 552 | static struct resource bfin_sir0_resources[] = { | ||
| 564 | { | 553 | { |
| 565 | .start = 0xFFC00400, | 554 | .start = 0xFFC00400, |
| 566 | .end = 0xFFC004FF, | 555 | .end = 0xFFC004FF, |
| 567 | .flags = IORESOURCE_MEM, | 556 | .flags = IORESOURCE_MEM, |
| 568 | }, | 557 | }, |
| 558 | { | ||
| 559 | .start = IRQ_UART0_RX, | ||
| 560 | .end = IRQ_UART0_RX+1, | ||
| 561 | .flags = IORESOURCE_IRQ, | ||
| 562 | }, | ||
| 563 | { | ||
| 564 | .start = CH_UART0_RX, | ||
| 565 | .end = CH_UART0_RX+1, | ||
| 566 | .flags = IORESOURCE_DMA, | ||
| 567 | }, | ||
| 568 | }; | ||
| 569 | |||
| 570 | static struct platform_device bfin_sir0_device = { | ||
| 571 | .name = "bfin_sir", | ||
| 572 | .id = 0, | ||
| 573 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 574 | .resource = bfin_sir0_resources, | ||
| 575 | }; | ||
| 569 | #endif | 576 | #endif |
| 570 | #ifdef CONFIG_BFIN_SIR1 | 577 | #ifdef CONFIG_BFIN_SIR1 |
| 578 | static struct resource bfin_sir1_resources[] = { | ||
| 571 | { | 579 | { |
| 572 | .start = 0xFFC02000, | 580 | .start = 0xFFC02000, |
| 573 | .end = 0xFFC020FF, | 581 | .end = 0xFFC020FF, |
| 574 | .flags = IORESOURCE_MEM, | 582 | .flags = IORESOURCE_MEM, |
| 575 | }, | 583 | }, |
| 576 | #endif | 584 | { |
| 585 | .start = IRQ_UART1_RX, | ||
| 586 | .end = IRQ_UART1_RX+1, | ||
| 587 | .flags = IORESOURCE_IRQ, | ||
| 588 | }, | ||
| 589 | { | ||
| 590 | .start = CH_UART1_RX, | ||
| 591 | .end = CH_UART1_RX+1, | ||
| 592 | .flags = IORESOURCE_DMA, | ||
| 593 | }, | ||
| 577 | }; | 594 | }; |
| 578 | 595 | ||
| 579 | static struct platform_device bfin_sir_device = { | 596 | static struct platform_device bfin_sir1_device = { |
| 580 | .name = "bfin_sir", | 597 | .name = "bfin_sir", |
| 581 | .id = 0, | 598 | .id = 1, |
| 582 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 599 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 583 | .resource = bfin_sir_resources, | 600 | .resource = bfin_sir1_resources, |
| 584 | }; | 601 | }; |
| 585 | #endif | 602 | #endif |
| 603 | #endif | ||
| 586 | 604 | ||
| 587 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 605 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 588 | static struct resource bfin_twi0_resource[] = { | 606 | static struct resource bfin_twi0_resource[] = { |
| @@ -651,6 +669,10 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 651 | &net2272_bfin_device, | 669 | &net2272_bfin_device, |
| 652 | #endif | 670 | #endif |
| 653 | 671 | ||
| 672 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | ||
| 673 | &bfin_isp1760_device, | ||
| 674 | #endif | ||
| 675 | |||
| 654 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 676 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 655 | &bfin_spi0_device, | 677 | &bfin_spi0_device, |
| 656 | #endif | 678 | #endif |
| @@ -668,7 +690,12 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 668 | #endif | 690 | #endif |
| 669 | 691 | ||
| 670 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 692 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 671 | &bfin_sir_device, | 693 | #ifdef CONFIG_BFIN_SIR0 |
| 694 | &bfin_sir0_device, | ||
| 695 | #endif | ||
| 696 | #ifdef CONFIG_BFIN_SIR1 | ||
| 697 | &bfin_sir1_device, | ||
| 698 | #endif | ||
| 672 | #endif | 699 | #endif |
| 673 | 700 | ||
| 674 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 701 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index 48c4cd2d1be6..bb795341cb17 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c | |||
| @@ -226,30 +226,59 @@ static struct platform_device bfin_uart_device = { | |||
| 226 | #endif | 226 | #endif |
| 227 | 227 | ||
| 228 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 228 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 229 | static struct resource bfin_sir_resources[] = { | ||
| 230 | #ifdef CONFIG_BFIN_SIR0 | 229 | #ifdef CONFIG_BFIN_SIR0 |
| 230 | static struct resource bfin_sir0_resources[] = { | ||
| 231 | { | 231 | { |
| 232 | .start = 0xFFC00400, | 232 | .start = 0xFFC00400, |
| 233 | .end = 0xFFC004FF, | 233 | .end = 0xFFC004FF, |
| 234 | .flags = IORESOURCE_MEM, | 234 | .flags = IORESOURCE_MEM, |
| 235 | }, | 235 | }, |
| 236 | { | ||
| 237 | .start = IRQ_UART0_RX, | ||
| 238 | .end = IRQ_UART0_RX+1, | ||
| 239 | .flags = IORESOURCE_IRQ, | ||
| 240 | }, | ||
| 241 | { | ||
| 242 | .start = CH_UART0_RX, | ||
| 243 | .end = CH_UART0_RX+1, | ||
| 244 | .flags = IORESOURCE_DMA, | ||
| 245 | }, | ||
| 246 | }; | ||
| 247 | |||
| 248 | static struct platform_device bfin_sir0_device = { | ||
| 249 | .name = "bfin_sir", | ||
| 250 | .id = 0, | ||
| 251 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 252 | .resource = bfin_sir0_resources, | ||
| 253 | }; | ||
| 236 | #endif | 254 | #endif |
| 237 | #ifdef CONFIG_BFIN_SIR1 | 255 | #ifdef CONFIG_BFIN_SIR1 |
| 256 | static struct resource bfin_sir1_resources[] = { | ||
| 238 | { | 257 | { |
| 239 | .start = 0xFFC02000, | 258 | .start = 0xFFC02000, |
| 240 | .end = 0xFFC020FF, | 259 | .end = 0xFFC020FF, |
| 241 | .flags = IORESOURCE_MEM, | 260 | .flags = IORESOURCE_MEM, |
| 242 | }, | 261 | }, |
| 243 | #endif | 262 | { |
| 263 | .start = IRQ_UART1_RX, | ||
| 264 | .end = IRQ_UART1_RX+1, | ||
| 265 | .flags = IORESOURCE_IRQ, | ||
| 266 | }, | ||
| 267 | { | ||
| 268 | .start = CH_UART1_RX, | ||
| 269 | .end = CH_UART1_RX+1, | ||
| 270 | .flags = IORESOURCE_DMA, | ||
| 271 | }, | ||
| 244 | }; | 272 | }; |
| 245 | 273 | ||
| 246 | static struct platform_device bfin_sir_device = { | 274 | static struct platform_device bfin_sir1_device = { |
| 247 | .name = "bfin_sir", | 275 | .name = "bfin_sir", |
| 248 | .id = 0, | 276 | .id = 1, |
| 249 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 277 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 250 | .resource = bfin_sir_resources, | 278 | .resource = bfin_sir1_resources, |
| 251 | }; | 279 | }; |
| 252 | #endif | 280 | #endif |
| 281 | #endif | ||
| 253 | 282 | ||
| 254 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 283 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 255 | static struct resource bfin_twi0_resource[] = { | 284 | static struct resource bfin_twi0_resource[] = { |
| @@ -311,7 +340,12 @@ static struct platform_device *minotaur_devices[] __initdata = { | |||
| 311 | #endif | 340 | #endif |
| 312 | 341 | ||
| 313 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 342 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 314 | &bfin_sir_device, | 343 | #ifdef CONFIG_BFIN_SIR0 |
| 344 | &bfin_sir0_device, | ||
| 345 | #endif | ||
| 346 | #ifdef CONFIG_BFIN_SIR1 | ||
| 347 | &bfin_sir1_device, | ||
| 348 | #endif | ||
| 315 | #endif | 349 | #endif |
| 316 | 350 | ||
| 317 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 351 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index f9174c11cbd4..89de94f4545d 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c | |||
| @@ -49,7 +49,7 @@ | |||
| 49 | /* | 49 | /* |
| 50 | * Name the Board for the /proc/cpuinfo | 50 | * Name the Board for the /proc/cpuinfo |
| 51 | */ | 51 | */ |
| 52 | const char bfin_board_name[] = "PNAV-1.0"; | 52 | const char bfin_board_name[] = "ADI PNAV-1.0"; |
| 53 | 53 | ||
| 54 | /* | 54 | /* |
| 55 | * Driver needs to know address, irq and flag pin. | 55 | * Driver needs to know address, irq and flag pin. |
| @@ -453,30 +453,59 @@ static struct platform_device bfin_uart_device = { | |||
| 453 | #endif | 453 | #endif |
| 454 | 454 | ||
| 455 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 455 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 456 | static struct resource bfin_sir_resources[] = { | ||
| 457 | #ifdef CONFIG_BFIN_SIR0 | 456 | #ifdef CONFIG_BFIN_SIR0 |
| 457 | static struct resource bfin_sir0_resources[] = { | ||
| 458 | { | 458 | { |
| 459 | .start = 0xFFC00400, | 459 | .start = 0xFFC00400, |
| 460 | .end = 0xFFC004FF, | 460 | .end = 0xFFC004FF, |
| 461 | .flags = IORESOURCE_MEM, | 461 | .flags = IORESOURCE_MEM, |
| 462 | }, | 462 | }, |
| 463 | { | ||
| 464 | .start = IRQ_UART0_RX, | ||
| 465 | .end = IRQ_UART0_RX+1, | ||
| 466 | .flags = IORESOURCE_IRQ, | ||
| 467 | }, | ||
| 468 | { | ||
| 469 | .start = CH_UART0_RX, | ||
| 470 | .end = CH_UART0_RX+1, | ||
| 471 | .flags = IORESOURCE_DMA, | ||
| 472 | }, | ||
| 473 | }; | ||
| 474 | |||
| 475 | static struct platform_device bfin_sir0_device = { | ||
| 476 | .name = "bfin_sir", | ||
| 477 | .id = 0, | ||
| 478 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 479 | .resource = bfin_sir0_resources, | ||
| 480 | }; | ||
| 463 | #endif | 481 | #endif |
| 464 | #ifdef CONFIG_BFIN_SIR1 | 482 | #ifdef CONFIG_BFIN_SIR1 |
| 483 | static struct resource bfin_sir1_resources[] = { | ||
| 465 | { | 484 | { |
| 466 | .start = 0xFFC02000, | 485 | .start = 0xFFC02000, |
| 467 | .end = 0xFFC020FF, | 486 | .end = 0xFFC020FF, |
| 468 | .flags = IORESOURCE_MEM, | 487 | .flags = IORESOURCE_MEM, |
| 469 | }, | 488 | }, |
| 470 | #endif | 489 | { |
| 490 | .start = IRQ_UART1_RX, | ||
| 491 | .end = IRQ_UART1_RX+1, | ||
| 492 | .flags = IORESOURCE_IRQ, | ||
| 493 | }, | ||
| 494 | { | ||
| 495 | .start = CH_UART1_RX, | ||
| 496 | .end = CH_UART1_RX+1, | ||
| 497 | .flags = IORESOURCE_DMA, | ||
| 498 | }, | ||
| 471 | }; | 499 | }; |
| 472 | 500 | ||
| 473 | static struct platform_device bfin_sir_device = { | 501 | static struct platform_device bfin_sir1_device = { |
| 474 | .name = "bfin_sir", | 502 | .name = "bfin_sir", |
| 475 | .id = 0, | 503 | .id = 1, |
| 476 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 504 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 477 | .resource = bfin_sir_resources, | 505 | .resource = bfin_sir1_resources, |
| 478 | }; | 506 | }; |
| 479 | #endif | 507 | #endif |
| 508 | #endif | ||
| 480 | 509 | ||
| 481 | static struct platform_device *stamp_devices[] __initdata = { | 510 | static struct platform_device *stamp_devices[] __initdata = { |
| 482 | #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) | 511 | #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) |
| @@ -520,7 +549,12 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 520 | #endif | 549 | #endif |
| 521 | 550 | ||
| 522 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 551 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 523 | &bfin_sir_device, | 552 | #ifdef CONFIG_BFIN_SIR0 |
| 553 | &bfin_sir0_device, | ||
| 554 | #endif | ||
| 555 | #ifdef CONFIG_BFIN_SIR1 | ||
| 556 | &bfin_sir1_device, | ||
| 557 | #endif | ||
| 524 | #endif | 558 | #endif |
| 525 | }; | 559 | }; |
| 526 | 560 | ||
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 8d394393201f..d812e2514a2f 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c | |||
| @@ -46,6 +46,7 @@ | |||
| 46 | #include <linux/interrupt.h> | 46 | #include <linux/interrupt.h> |
| 47 | #include <linux/i2c.h> | 47 | #include <linux/i2c.h> |
| 48 | #include <linux/usb/sl811.h> | 48 | #include <linux/usb/sl811.h> |
| 49 | #include <linux/spi/mmc_spi.h> | ||
| 49 | #include <asm/dma.h> | 50 | #include <asm/dma.h> |
| 50 | #include <asm/bfin5xx_spi.h> | 51 | #include <asm/bfin5xx_spi.h> |
| 51 | #include <asm/reboot.h> | 52 | #include <asm/reboot.h> |
| @@ -55,57 +56,46 @@ | |||
| 55 | /* | 56 | /* |
| 56 | * Name the Board for the /proc/cpuinfo | 57 | * Name the Board for the /proc/cpuinfo |
| 57 | */ | 58 | */ |
| 58 | const char bfin_board_name[] = "ADDS-BF537-STAMP"; | 59 | const char bfin_board_name[] = "ADI BF537-STAMP"; |
| 59 | 60 | ||
| 60 | /* | 61 | /* |
| 61 | * Driver needs to know address, irq and flag pin. | 62 | * Driver needs to know address, irq and flag pin. |
| 62 | */ | 63 | */ |
| 63 | 64 | ||
| 64 | #define ISP1761_BASE 0x203C0000 | ||
| 65 | #define ISP1761_IRQ IRQ_PF7 | ||
| 66 | |||
| 67 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | 65 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
| 68 | static struct resource bfin_isp1761_resources[] = { | 66 | #include <linux/usb/isp1760.h> |
| 67 | static struct resource bfin_isp1760_resources[] = { | ||
| 69 | [0] = { | 68 | [0] = { |
| 70 | .name = "isp1761-regs", | 69 | .start = 0x203C0000, |
| 71 | .start = ISP1761_BASE + 0x00000000, | 70 | .end = 0x203C0000 + 0x000fffff, |
| 72 | .end = ISP1761_BASE + 0x000fffff, | ||
| 73 | .flags = IORESOURCE_MEM, | 71 | .flags = IORESOURCE_MEM, |
| 74 | }, | 72 | }, |
| 75 | [1] = { | 73 | [1] = { |
| 76 | .start = ISP1761_IRQ, | 74 | .start = IRQ_PF7, |
| 77 | .end = ISP1761_IRQ, | 75 | .end = IRQ_PF7, |
| 78 | .flags = IORESOURCE_IRQ, | 76 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, |
| 79 | }, | 77 | }, |
| 80 | }; | 78 | }; |
| 81 | 79 | ||
| 82 | static struct platform_device bfin_isp1761_device = { | 80 | static struct isp1760_platform_data isp1760_priv = { |
| 83 | .name = "isp1761", | 81 | .is_isp1761 = 0, |
| 84 | .id = 0, | 82 | .port1_disable = 0, |
| 85 | .num_resources = ARRAY_SIZE(bfin_isp1761_resources), | 83 | .bus_width_16 = 1, |
| 86 | .resource = bfin_isp1761_resources, | 84 | .port1_otg = 0, |
| 85 | .analog_oc = 0, | ||
| 86 | .dack_polarity_high = 0, | ||
| 87 | .dreq_polarity_high = 0, | ||
| 87 | }; | 88 | }; |
| 88 | 89 | ||
| 89 | static struct platform_device *bfin_isp1761_devices[] = { | 90 | static struct platform_device bfin_isp1760_device = { |
| 90 | &bfin_isp1761_device, | 91 | .name = "isp1760-hcd", |
| 92 | .id = 0, | ||
| 93 | .dev = { | ||
| 94 | .platform_data = &isp1760_priv, | ||
| 95 | }, | ||
| 96 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | ||
| 97 | .resource = bfin_isp1760_resources, | ||
| 91 | }; | 98 | }; |
| 92 | |||
| 93 | int __init bfin_isp1761_init(void) | ||
| 94 | { | ||
| 95 | unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); | ||
| 96 | |||
| 97 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 98 | set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); | ||
| 99 | |||
| 100 | return platform_add_devices(bfin_isp1761_devices, num_devices); | ||
| 101 | } | ||
| 102 | |||
| 103 | void __exit bfin_isp1761_exit(void) | ||
| 104 | { | ||
| 105 | platform_device_unregister(&bfin_isp1761_device); | ||
| 106 | } | ||
| 107 | |||
| 108 | arch_initcall(bfin_isp1761_init); | ||
| 109 | #endif | 99 | #endif |
| 110 | 100 | ||
| 111 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | 101 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
| @@ -443,11 +433,11 @@ static struct mtd_partition stamp_partitions[] = { | |||
| 443 | .offset = 0, | 433 | .offset = 0, |
| 444 | }, { | 434 | }, { |
| 445 | .name = "linux kernel(nor)", | 435 | .name = "linux kernel(nor)", |
| 446 | .size = 0xE0000, | 436 | .size = 0x180000, |
| 447 | .offset = MTDPART_OFS_APPEND, | 437 | .offset = MTDPART_OFS_APPEND, |
| 448 | }, { | 438 | }, { |
| 449 | .name = "file system(nor)", | 439 | .name = "file system(nor)", |
| 450 | .size = 0x400000 - 0x40000 - 0xE0000 - 0x10000, | 440 | .size = 0x400000 - 0x40000 - 0x180000 - 0x10000, |
| 451 | .offset = MTDPART_OFS_APPEND, | 441 | .offset = MTDPART_OFS_APPEND, |
| 452 | }, { | 442 | }, { |
| 453 | .name = "MAC Address(nor)", | 443 | .name = "MAC Address(nor)", |
| @@ -490,7 +480,7 @@ static struct mtd_partition bfin_spi_flash_partitions[] = { | |||
| 490 | .mask_flags = MTD_CAP_ROM | 480 | .mask_flags = MTD_CAP_ROM |
| 491 | }, { | 481 | }, { |
| 492 | .name = "linux kernel(spi)", | 482 | .name = "linux kernel(spi)", |
| 493 | .size = 0xe0000, | 483 | .size = 0x180000, |
| 494 | .offset = MTDPART_OFS_APPEND, | 484 | .offset = MTDPART_OFS_APPEND, |
| 495 | }, { | 485 | }, { |
| 496 | .name = "file system(spi)", | 486 | .name = "file system(spi)", |
| @@ -503,7 +493,7 @@ static struct flash_platform_data bfin_spi_flash_data = { | |||
| 503 | .name = "m25p80", | 493 | .name = "m25p80", |
| 504 | .parts = bfin_spi_flash_partitions, | 494 | .parts = bfin_spi_flash_partitions, |
| 505 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | 495 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), |
| 506 | .type = "m25p64", | 496 | /* .type = "m25p64", */ |
| 507 | }; | 497 | }; |
| 508 | 498 | ||
| 509 | /* SPI flash chip (m25p64) */ | 499 | /* SPI flash chip (m25p64) */ |
| @@ -537,9 +527,29 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |||
| 537 | }; | 527 | }; |
| 538 | #endif | 528 | #endif |
| 539 | 529 | ||
| 540 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 530 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 541 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 531 | #define MMC_SPI_CARD_DETECT_INT IRQ_PF5 |
| 542 | .enable_dma = 1, | 532 | |
| 533 | static int bfin_mmc_spi_init(struct device *dev, | ||
| 534 | irqreturn_t (*detect_int)(int, void *), void *data) | ||
| 535 | { | ||
| 536 | return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int, | ||
| 537 | IRQF_TRIGGER_FALLING, "mmc-spi-detect", data); | ||
| 538 | } | ||
| 539 | |||
| 540 | static void bfin_mmc_spi_exit(struct device *dev, void *data) | ||
| 541 | { | ||
| 542 | free_irq(MMC_SPI_CARD_DETECT_INT, data); | ||
| 543 | } | ||
| 544 | |||
| 545 | static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { | ||
| 546 | .init = bfin_mmc_spi_init, | ||
| 547 | .exit = bfin_mmc_spi_exit, | ||
| 548 | .detect_delay = 100, /* msecs */ | ||
| 549 | }; | ||
| 550 | |||
| 551 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | ||
| 552 | .enable_dma = 0, | ||
| 543 | .bits_per_word = 8, | 553 | .bits_per_word = 8, |
| 544 | }; | 554 | }; |
| 545 | #endif | 555 | #endif |
| @@ -613,6 +623,14 @@ static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { | |||
| 613 | }; | 623 | }; |
| 614 | #endif | 624 | #endif |
| 615 | 625 | ||
| 626 | #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) | ||
| 627 | static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { | ||
| 628 | .enable_dma = 1, | ||
| 629 | .bits_per_word = 8, | ||
| 630 | .cs_gpio = GPIO_PF10, | ||
| 631 | }; | ||
| 632 | #endif | ||
| 633 | |||
| 616 | #if defined(CONFIG_MTD_DATAFLASH) \ | 634 | #if defined(CONFIG_MTD_DATAFLASH) \ |
| 617 | || defined(CONFIG_MTD_DATAFLASH_MODULE) | 635 | || defined(CONFIG_MTD_DATAFLASH_MODULE) |
| 618 | 636 | ||
| @@ -624,7 +642,7 @@ static struct mtd_partition bfin_spi_dataflash_partitions[] = { | |||
| 624 | .mask_flags = MTD_CAP_ROM | 642 | .mask_flags = MTD_CAP_ROM |
| 625 | }, { | 643 | }, { |
| 626 | .name = "linux kernel(spi)", | 644 | .name = "linux kernel(spi)", |
| 627 | .size = 0xe0000, | 645 | .size = 0x180000, |
| 628 | .offset = MTDPART_OFS_APPEND, | 646 | .offset = MTDPART_OFS_APPEND, |
| 629 | }, { | 647 | }, { |
| 630 | .name = "file system(spi)", | 648 | .name = "file system(spi)", |
| @@ -703,23 +721,14 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 703 | .controller_data = &ad9960_spi_chip_info, | 721 | .controller_data = &ad9960_spi_chip_info, |
| 704 | }, | 722 | }, |
| 705 | #endif | 723 | #endif |
| 706 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 724 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 707 | { | 725 | { |
| 708 | .modalias = "spi_mmc_dummy", | 726 | .modalias = "mmc_spi", |
| 709 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | 727 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ |
| 710 | .bus_num = 0, | 728 | .bus_num = 0, |
| 711 | .chip_select = 0, | 729 | .chip_select = 4, |
| 712 | .platform_data = NULL, | 730 | .platform_data = &bfin_mmc_spi_pdata, |
| 713 | .controller_data = &spi_mmc_chip_info, | 731 | .controller_data = &mmc_spi_chip_info, |
| 714 | .mode = SPI_MODE_3, | ||
| 715 | }, | ||
| 716 | { | ||
| 717 | .modalias = "spi_mmc", | ||
| 718 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 719 | .bus_num = 0, | ||
| 720 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | ||
| 721 | .platform_data = NULL, | ||
| 722 | .controller_data = &spi_mmc_chip_info, | ||
| 723 | .mode = SPI_MODE_3, | 732 | .mode = SPI_MODE_3, |
| 724 | }, | 733 | }, |
| 725 | #endif | 734 | #endif |
| @@ -783,6 +792,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 783 | .mode = SPI_CPHA | SPI_CPOL, | 792 | .mode = SPI_CPHA | SPI_CPOL, |
| 784 | }, | 793 | }, |
| 785 | #endif | 794 | #endif |
| 795 | #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) | ||
| 796 | { | ||
| 797 | .modalias = "enc28j60", | ||
| 798 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 799 | .irq = IRQ_PF6, | ||
| 800 | .bus_num = 0, | ||
| 801 | .chip_select = 0, /* GPIO controlled SSEL */ | ||
| 802 | .controller_data = &enc28j60_spi_chip_info, | ||
| 803 | .mode = SPI_MODE_0, | ||
| 804 | }, | ||
| 805 | #endif | ||
| 786 | }; | 806 | }; |
| 787 | 807 | ||
| 788 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 808 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| @@ -885,30 +905,59 @@ static struct platform_device bfin_uart_device = { | |||
| 885 | #endif | 905 | #endif |
| 886 | 906 | ||
| 887 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 907 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 888 | static struct resource bfin_sir_resources[] = { | ||
| 889 | #ifdef CONFIG_BFIN_SIR0 | 908 | #ifdef CONFIG_BFIN_SIR0 |
| 909 | static struct resource bfin_sir0_resources[] = { | ||
| 890 | { | 910 | { |
| 891 | .start = 0xFFC00400, | 911 | .start = 0xFFC00400, |
| 892 | .end = 0xFFC004FF, | 912 | .end = 0xFFC004FF, |
| 893 | .flags = IORESOURCE_MEM, | 913 | .flags = IORESOURCE_MEM, |
| 894 | }, | 914 | }, |
| 915 | { | ||
| 916 | .start = IRQ_UART0_RX, | ||
| 917 | .end = IRQ_UART0_RX+1, | ||
| 918 | .flags = IORESOURCE_IRQ, | ||
| 919 | }, | ||
| 920 | { | ||
| 921 | .start = CH_UART0_RX, | ||
| 922 | .end = CH_UART0_RX+1, | ||
| 923 | .flags = IORESOURCE_DMA, | ||
| 924 | }, | ||
| 925 | }; | ||
| 926 | |||
| 927 | static struct platform_device bfin_sir0_device = { | ||
| 928 | .name = "bfin_sir", | ||
| 929 | .id = 0, | ||
| 930 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 931 | .resource = bfin_sir0_resources, | ||
| 932 | }; | ||
| 895 | #endif | 933 | #endif |
| 896 | #ifdef CONFIG_BFIN_SIR1 | 934 | #ifdef CONFIG_BFIN_SIR1 |
| 935 | static struct resource bfin_sir1_resources[] = { | ||
| 897 | { | 936 | { |
| 898 | .start = 0xFFC02000, | 937 | .start = 0xFFC02000, |
| 899 | .end = 0xFFC020FF, | 938 | .end = 0xFFC020FF, |
| 900 | .flags = IORESOURCE_MEM, | 939 | .flags = IORESOURCE_MEM, |
| 901 | }, | 940 | }, |
| 902 | #endif | 941 | { |
| 942 | .start = IRQ_UART1_RX, | ||
| 943 | .end = IRQ_UART1_RX+1, | ||
| 944 | .flags = IORESOURCE_IRQ, | ||
| 945 | }, | ||
| 946 | { | ||
| 947 | .start = CH_UART1_RX, | ||
| 948 | .end = CH_UART1_RX+1, | ||
| 949 | .flags = IORESOURCE_DMA, | ||
| 950 | }, | ||
| 903 | }; | 951 | }; |
| 904 | 952 | ||
| 905 | static struct platform_device bfin_sir_device = { | 953 | static struct platform_device bfin_sir1_device = { |
| 906 | .name = "bfin_sir", | 954 | .name = "bfin_sir", |
| 907 | .id = 0, | 955 | .id = 1, |
| 908 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 956 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 909 | .resource = bfin_sir_resources, | 957 | .resource = bfin_sir1_resources, |
| 910 | }; | 958 | }; |
| 911 | #endif | 959 | #endif |
| 960 | #endif | ||
| 912 | 961 | ||
| 913 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 962 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 914 | static struct resource bfin_twi0_resource[] = { | 963 | static struct resource bfin_twi0_resource[] = { |
| @@ -932,6 +981,93 @@ static struct platform_device i2c_bfin_twi_device = { | |||
| 932 | }; | 981 | }; |
| 933 | #endif | 982 | #endif |
| 934 | 983 | ||
| 984 | #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) | ||
| 985 | #include <linux/input.h> | ||
| 986 | #include <linux/i2c/adp5588_keys.h> | ||
| 987 | static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { | ||
| 988 | [0] = KEY_GRAVE, | ||
| 989 | [1] = KEY_1, | ||
| 990 | [2] = KEY_2, | ||
| 991 | [3] = KEY_3, | ||
| 992 | [4] = KEY_4, | ||
| 993 | [5] = KEY_5, | ||
| 994 | [6] = KEY_6, | ||
| 995 | [7] = KEY_7, | ||
| 996 | [8] = KEY_8, | ||
| 997 | [9] = KEY_9, | ||
| 998 | [10] = KEY_0, | ||
| 999 | [11] = KEY_MINUS, | ||
| 1000 | [12] = KEY_EQUAL, | ||
| 1001 | [13] = KEY_BACKSLASH, | ||
| 1002 | [15] = KEY_KP0, | ||
| 1003 | [16] = KEY_Q, | ||
| 1004 | [17] = KEY_W, | ||
| 1005 | [18] = KEY_E, | ||
| 1006 | [19] = KEY_R, | ||
| 1007 | [20] = KEY_T, | ||
| 1008 | [21] = KEY_Y, | ||
| 1009 | [22] = KEY_U, | ||
| 1010 | [23] = KEY_I, | ||
| 1011 | [24] = KEY_O, | ||
| 1012 | [25] = KEY_P, | ||
| 1013 | [26] = KEY_LEFTBRACE, | ||
| 1014 | [27] = KEY_RIGHTBRACE, | ||
| 1015 | [29] = KEY_KP1, | ||
| 1016 | [30] = KEY_KP2, | ||
| 1017 | [31] = KEY_KP3, | ||
| 1018 | [32] = KEY_A, | ||
| 1019 | [33] = KEY_S, | ||
| 1020 | [34] = KEY_D, | ||
| 1021 | [35] = KEY_F, | ||
| 1022 | [36] = KEY_G, | ||
| 1023 | [37] = KEY_H, | ||
| 1024 | [38] = KEY_J, | ||
| 1025 | [39] = KEY_K, | ||
| 1026 | [40] = KEY_L, | ||
| 1027 | [41] = KEY_SEMICOLON, | ||
| 1028 | [42] = KEY_APOSTROPHE, | ||
| 1029 | [43] = KEY_BACKSLASH, | ||
| 1030 | [45] = KEY_KP4, | ||
| 1031 | [46] = KEY_KP5, | ||
| 1032 | [47] = KEY_KP6, | ||
| 1033 | [48] = KEY_102ND, | ||
| 1034 | [49] = KEY_Z, | ||
| 1035 | [50] = KEY_X, | ||
| 1036 | [51] = KEY_C, | ||
| 1037 | [52] = KEY_V, | ||
| 1038 | [53] = KEY_B, | ||
| 1039 | [54] = KEY_N, | ||
| 1040 | [55] = KEY_M, | ||
| 1041 | [56] = KEY_COMMA, | ||
| 1042 | [57] = KEY_DOT, | ||
| 1043 | [58] = KEY_SLASH, | ||
| 1044 | [60] = KEY_KPDOT, | ||
| 1045 | [61] = KEY_KP7, | ||
| 1046 | [62] = KEY_KP8, | ||
| 1047 | [63] = KEY_KP9, | ||
| 1048 | [64] = KEY_SPACE, | ||
| 1049 | [65] = KEY_BACKSPACE, | ||
| 1050 | [66] = KEY_TAB, | ||
| 1051 | [67] = KEY_KPENTER, | ||
| 1052 | [68] = KEY_ENTER, | ||
| 1053 | [69] = KEY_ESC, | ||
| 1054 | [70] = KEY_DELETE, | ||
| 1055 | [74] = KEY_KPMINUS, | ||
| 1056 | [76] = KEY_UP, | ||
| 1057 | [77] = KEY_DOWN, | ||
| 1058 | [78] = KEY_RIGHT, | ||
| 1059 | [79] = KEY_LEFT, | ||
| 1060 | }; | ||
| 1061 | |||
| 1062 | static struct adp5588_kpad_platform_data adp5588_kpad_data = { | ||
| 1063 | .rows = 8, | ||
| 1064 | .cols = 10, | ||
| 1065 | .keymap = adp5588_keymap, | ||
| 1066 | .keymapsize = ARRAY_SIZE(adp5588_keymap), | ||
| 1067 | .repeat = 0, | ||
| 1068 | }; | ||
| 1069 | #endif | ||
| 1070 | |||
| 935 | #ifdef CONFIG_I2C_BOARDINFO | 1071 | #ifdef CONFIG_I2C_BOARDINFO |
| 936 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | 1072 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { |
| 937 | #if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE) | 1073 | #if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE) |
| @@ -958,6 +1094,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { | |||
| 958 | .platform_data = (void *)&bfin_ad7879_ts_info, | 1094 | .platform_data = (void *)&bfin_ad7879_ts_info, |
| 959 | }, | 1095 | }, |
| 960 | #endif | 1096 | #endif |
| 1097 | #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) | ||
| 1098 | { | ||
| 1099 | I2C_BOARD_INFO("adp5588-keys", 0x34), | ||
| 1100 | .irq = IRQ_PG0, | ||
| 1101 | .platform_data = (void *)&adp5588_kpad_data, | ||
| 1102 | }, | ||
| 1103 | #endif | ||
| 961 | }; | 1104 | }; |
| 962 | #endif | 1105 | #endif |
| 963 | 1106 | ||
| @@ -1057,6 +1200,10 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 1057 | &isp1362_hcd_device, | 1200 | &isp1362_hcd_device, |
| 1058 | #endif | 1201 | #endif |
| 1059 | 1202 | ||
| 1203 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | ||
| 1204 | &bfin_isp1760_device, | ||
| 1205 | #endif | ||
| 1206 | |||
| 1060 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 1207 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
| 1061 | &smc91x_device, | 1208 | &smc91x_device, |
| 1062 | #endif | 1209 | #endif |
| @@ -1098,7 +1245,12 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 1098 | #endif | 1245 | #endif |
| 1099 | 1246 | ||
| 1100 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 1247 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 1101 | &bfin_sir_device, | 1248 | #ifdef CONFIG_BFIN_SIR0 |
| 1249 | &bfin_sir0_device, | ||
| 1250 | #endif | ||
| 1251 | #ifdef CONFIG_BFIN_SIR1 | ||
| 1252 | &bfin_sir1_device, | ||
| 1253 | #endif | ||
| 1102 | #endif | 1254 | #endif |
| 1103 | 1255 | ||
| 1104 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 1256 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index d5ff705a5129..2f4b066153c5 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c | |||
| @@ -308,6 +308,19 @@ static struct platform_device net2272_bfin_device = { | |||
| 308 | }; | 308 | }; |
| 309 | #endif | 309 | #endif |
| 310 | 310 | ||
| 311 | static struct resource bfin_gpios_resources = { | ||
| 312 | .start = 0, | ||
| 313 | .end = MAX_BLACKFIN_GPIOS - 1, | ||
| 314 | .flags = IORESOURCE_IRQ, | ||
| 315 | }; | ||
| 316 | |||
| 317 | static struct platform_device bfin_gpios_device = { | ||
| 318 | .name = "simple-gpio", | ||
| 319 | .id = -1, | ||
| 320 | .num_resources = 1, | ||
| 321 | .resource = &bfin_gpios_resources, | ||
| 322 | }; | ||
| 323 | |||
| 311 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) | 324 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) |
| 312 | static struct mtd_partition cm_partitions[] = { | 325 | static struct mtd_partition cm_partitions[] = { |
| 313 | { | 326 | { |
| @@ -379,30 +392,59 @@ static struct platform_device bfin_uart_device = { | |||
| 379 | #endif | 392 | #endif |
| 380 | 393 | ||
| 381 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 394 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 382 | static struct resource bfin_sir_resources[] = { | ||
| 383 | #ifdef CONFIG_BFIN_SIR0 | 395 | #ifdef CONFIG_BFIN_SIR0 |
| 396 | static struct resource bfin_sir0_resources[] = { | ||
| 384 | { | 397 | { |
| 385 | .start = 0xFFC00400, | 398 | .start = 0xFFC00400, |
| 386 | .end = 0xFFC004FF, | 399 | .end = 0xFFC004FF, |
| 387 | .flags = IORESOURCE_MEM, | 400 | .flags = IORESOURCE_MEM, |
| 388 | }, | 401 | }, |
| 402 | { | ||
| 403 | .start = IRQ_UART0_RX, | ||
| 404 | .end = IRQ_UART0_RX+1, | ||
| 405 | .flags = IORESOURCE_IRQ, | ||
| 406 | }, | ||
| 407 | { | ||
| 408 | .start = CH_UART0_RX, | ||
| 409 | .end = CH_UART0_RX+1, | ||
| 410 | .flags = IORESOURCE_DMA, | ||
| 411 | }, | ||
| 412 | }; | ||
| 413 | |||
| 414 | static struct platform_device bfin_sir0_device = { | ||
| 415 | .name = "bfin_sir", | ||
| 416 | .id = 0, | ||
| 417 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 418 | .resource = bfin_sir0_resources, | ||
| 419 | }; | ||
| 389 | #endif | 420 | #endif |
| 390 | #ifdef CONFIG_BFIN_SIR1 | 421 | #ifdef CONFIG_BFIN_SIR1 |
| 422 | static struct resource bfin_sir1_resources[] = { | ||
| 391 | { | 423 | { |
| 392 | .start = 0xFFC02000, | 424 | .start = 0xFFC02000, |
| 393 | .end = 0xFFC020FF, | 425 | .end = 0xFFC020FF, |
| 394 | .flags = IORESOURCE_MEM, | 426 | .flags = IORESOURCE_MEM, |
| 395 | }, | 427 | }, |
| 396 | #endif | 428 | { |
| 429 | .start = IRQ_UART1_RX, | ||
| 430 | .end = IRQ_UART1_RX+1, | ||
| 431 | .flags = IORESOURCE_IRQ, | ||
| 432 | }, | ||
| 433 | { | ||
| 434 | .start = CH_UART1_RX, | ||
| 435 | .end = CH_UART1_RX+1, | ||
| 436 | .flags = IORESOURCE_DMA, | ||
| 437 | }, | ||
| 397 | }; | 438 | }; |
| 398 | 439 | ||
| 399 | static struct platform_device bfin_sir_device = { | 440 | static struct platform_device bfin_sir1_device = { |
| 400 | .name = "bfin_sir", | 441 | .name = "bfin_sir", |
| 401 | .id = 0, | 442 | .id = 1, |
| 402 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 443 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), |
| 403 | .resource = bfin_sir_resources, | 444 | .resource = bfin_sir1_resources, |
| 404 | }; | 445 | }; |
| 405 | #endif | 446 | #endif |
| 447 | #endif | ||
| 406 | 448 | ||
| 407 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 449 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 408 | static struct resource bfin_twi0_resource[] = { | 450 | static struct resource bfin_twi0_resource[] = { |
| @@ -525,7 +567,12 @@ static struct platform_device *cm_bf537_devices[] __initdata = { | |||
| 525 | #endif | 567 | #endif |
| 526 | 568 | ||
| 527 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 569 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 528 | &bfin_sir_device, | 570 | #ifdef CONFIG_BFIN_SIR0 |
| 571 | &bfin_sir0_device, | ||
| 572 | #endif | ||
| 573 | #ifdef CONFIG_BFIN_SIR1 | ||
| 574 | &bfin_sir1_device, | ||
| 575 | #endif | ||
| 529 | #endif | 576 | #endif |
| 530 | 577 | ||
| 531 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 578 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| @@ -564,6 +611,8 @@ static struct platform_device *cm_bf537_devices[] __initdata = { | |||
| 564 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) | 611 | #if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) |
| 565 | &cm_flash_device, | 612 | &cm_flash_device, |
| 566 | #endif | 613 | #endif |
| 614 | |||
| 615 | &bfin_gpios_device, | ||
| 567 | }; | 616 | }; |
| 568 | 617 | ||
| 569 | static int __init cm_bf537_init(void) | 618 | static int __init cm_bf537_init(void) |
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c index 4edb363ff99c..81185051de91 100644 --- a/arch/blackfin/mach-bf537/dma.c +++ b/arch/blackfin/mach-bf537/dma.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <asm/blackfin.h> | 31 | #include <asm/blackfin.h> |
| 32 | #include <asm/dma.h> | 32 | #include <asm/dma.h> |
| 33 | 33 | ||
| 34 | struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { | 34 | struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { |
| 35 | (struct dma_register *) DMA0_NEXT_DESC_PTR, | 35 | (struct dma_register *) DMA0_NEXT_DESC_PTR, |
| 36 | (struct dma_register *) DMA1_NEXT_DESC_PTR, | 36 | (struct dma_register *) DMA1_NEXT_DESC_PTR, |
| 37 | (struct dma_register *) DMA2_NEXT_DESC_PTR, | 37 | (struct dma_register *) DMA2_NEXT_DESC_PTR, |
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S deleted file mode 100644 index f5c94bf80e3b..000000000000 --- a/arch/blackfin/mach-bf537/head.S +++ /dev/null | |||
| @@ -1,146 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf537/head.S | ||
| 3 | * Based on: arch/blackfin/mach-bf533/head.S | ||
| 4 | * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne | ||
| 5 | * | ||
| 6 | * Created: 1998 | ||
| 7 | * Description: Startup code for Blackfin BF537 | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/linkage.h> | ||
| 31 | #include <linux/init.h> | ||
| 32 | #include <asm/blackfin.h> | ||
| 33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 34 | #include <asm/clocks.h> | ||
| 35 | #include <mach/mem_init.h> | ||
| 36 | #endif | ||
| 37 | |||
| 38 | .section .l1.text | ||
| 39 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 40 | ENTRY(_start_dma_code) | ||
| 41 | |||
| 42 | /* Enable PHY CLK buffer output */ | ||
| 43 | p0.h = hi(VR_CTL); | ||
| 44 | p0.l = lo(VR_CTL); | ||
| 45 | r0.l = w[p0]; | ||
| 46 | bitset(r0, 14); | ||
| 47 | w[p0] = r0.l; | ||
| 48 | ssync; | ||
| 49 | |||
| 50 | p0.h = hi(SIC_IWR); | ||
| 51 | p0.l = lo(SIC_IWR); | ||
| 52 | r0.l = 0x1; | ||
| 53 | r0.h = 0x0; | ||
| 54 | [p0] = r0; | ||
| 55 | SSYNC; | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Set PLL_CTL | ||
| 59 | * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors | ||
| 60 | * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK | ||
| 61 | * - [7] = output delay (add 200ps of delay to mem signals) | ||
| 62 | * - [6] = input delay (add 200ps of input delay to mem signals) | ||
| 63 | * - [5] = PDWN : 1=All Clocks off | ||
| 64 | * - [3] = STOPCK : 1=Core Clock off | ||
| 65 | * - [1] = PLL_OFF : 1=Disable Power to PLL | ||
| 66 | * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL | ||
| 67 | * all other bits set to zero | ||
| 68 | */ | ||
| 69 | |||
| 70 | p0.h = hi(PLL_LOCKCNT); | ||
| 71 | p0.l = lo(PLL_LOCKCNT); | ||
| 72 | r0 = 0x300(Z); | ||
| 73 | w[p0] = r0.l; | ||
| 74 | ssync; | ||
| 75 | |||
| 76 | P2.H = hi(EBIU_SDGCTL); | ||
| 77 | P2.L = lo(EBIU_SDGCTL); | ||
| 78 | R0 = [P2]; | ||
| 79 | BITSET (R0, 24); | ||
| 80 | [P2] = R0; | ||
| 81 | SSYNC; | ||
| 82 | |||
| 83 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ | ||
| 84 | r0 = r0 << 9; /* Shift it over, */ | ||
| 85 | r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ | ||
| 86 | r0 = r1 | r0; | ||
| 87 | r1 = PLL_BYPASS; /* Bypass the PLL? */ | ||
| 88 | r1 = r1 << 8; /* Shift it over */ | ||
| 89 | r0 = r1 | r0; /* add them all together */ | ||
| 90 | #ifdef ANOMALY_05000265 | ||
| 91 | BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */ | ||
| 92 | #endif | ||
| 93 | |||
| 94 | p0.h = hi(PLL_CTL); | ||
| 95 | p0.l = lo(PLL_CTL); /* Load the address */ | ||
| 96 | cli r2; /* Disable interrupts */ | ||
| 97 | ssync; | ||
| 98 | w[p0] = r0.l; /* Set the value */ | ||
| 99 | idle; /* Wait for the PLL to stablize */ | ||
| 100 | sti r2; /* Enable interrupts */ | ||
| 101 | |||
| 102 | .Lcheck_again: | ||
| 103 | p0.h = hi(PLL_STAT); | ||
| 104 | p0.l = lo(PLL_STAT); | ||
| 105 | R0 = W[P0](Z); | ||
| 106 | CC = BITTST(R0,5); | ||
| 107 | if ! CC jump .Lcheck_again; | ||
| 108 | |||
| 109 | /* Configure SCLK & CCLK Dividers */ | ||
| 110 | r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | ||
| 111 | p0.h = hi(PLL_DIV); | ||
| 112 | p0.l = lo(PLL_DIV); | ||
| 113 | w[p0] = r0.l; | ||
| 114 | ssync; | ||
| 115 | |||
| 116 | p0.l = lo(EBIU_SDRRC); | ||
| 117 | p0.h = hi(EBIU_SDRRC); | ||
| 118 | r0 = mem_SDRRC; | ||
| 119 | w[p0] = r0.l; | ||
| 120 | ssync; | ||
| 121 | |||
| 122 | P2.H = hi(EBIU_SDGCTL); | ||
| 123 | P2.L = lo(EBIU_SDGCTL); | ||
| 124 | R0 = [P2]; | ||
| 125 | BITCLR (R0, 24); | ||
| 126 | p0.h = hi(EBIU_SDSTAT); | ||
| 127 | p0.l = lo(EBIU_SDSTAT); | ||
| 128 | r2.l = w[p0]; | ||
| 129 | cc = bittst(r2,3); | ||
| 130 | if !cc jump .Lskip; | ||
| 131 | NOP; | ||
| 132 | BITSET (R0, 23); | ||
| 133 | .Lskip: | ||
| 134 | [P2] = R0; | ||
| 135 | SSYNC; | ||
| 136 | |||
| 137 | R0.L = lo(mem_SDGCTL); | ||
| 138 | R0.H = hi(mem_SDGCTL); | ||
| 139 | R1 = [p2]; | ||
| 140 | R1 = R1 | R0; | ||
| 141 | [P2] = R1; | ||
| 142 | SSYNC; | ||
| 143 | |||
| 144 | RTS; | ||
| 145 | ENDPROC(_start_dma_code) | ||
| 146 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | ||
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index c68992494f9e..9cb39121d1cb 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file shoule be up to date with: |
| 10 | * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List | 10 | * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
| @@ -148,6 +148,14 @@ | |||
| 148 | #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) | 148 | #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) |
| 149 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 149 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
| 150 | #define ANOMALY_05000403 (1) | 150 | #define ANOMALY_05000403 (1) |
| 151 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | ||
| 152 | #define ANOMALY_05000416 (1) | ||
| 153 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ | ||
| 154 | #define ANOMALY_05000425 (1) | ||
| 155 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | ||
| 156 | #define ANOMALY_05000426 (1) | ||
| 157 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | ||
| 158 | #define ANOMALY_05000443 (1) | ||
| 151 | 159 | ||
| 152 | /* Anomalies that don't exist on this proc */ | 160 | /* Anomalies that don't exist on this proc */ |
| 153 | #define ANOMALY_05000125 (0) | 161 | #define ANOMALY_05000125 (0) |
| @@ -161,5 +169,8 @@ | |||
| 161 | #define ANOMALY_05000353 (1) | 169 | #define ANOMALY_05000353 (1) |
| 162 | #define ANOMALY_05000363 (0) | 170 | #define ANOMALY_05000363 (0) |
| 163 | #define ANOMALY_05000386 (1) | 171 | #define ANOMALY_05000386 (1) |
| 172 | #define ANOMALY_05000412 (0) | ||
| 173 | #define ANOMALY_05000432 (0) | ||
| 174 | #define ANOMALY_05000435 (0) | ||
| 164 | 175 | ||
| 165 | #endif | 176 | #endif |
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h index 24d5c9d42323..f194a848ae8e 100644 --- a/arch/blackfin/mach-bf537/include/mach/bf537.h +++ b/arch/blackfin/mach-bf537/include/mach/bf537.h | |||
| @@ -133,7 +133,7 @@ | |||
| 133 | #endif | 133 | #endif |
| 134 | 134 | ||
| 135 | #ifndef CPU | 135 | #ifndef CPU |
| 136 | #error Unknown CPU type - This kernel doesn't seem to be configured properly | 136 | #error "Unknown CPU type - This kernel doesn't seem to be configured properly" |
| 137 | #endif | 137 | #endif |
| 138 | 138 | ||
| 139 | #endif /* __MACH_BF537_H__ */ | 139 | #endif /* __MACH_BF537_H__ */ |
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_sir.h b/arch/blackfin/mach-bf537/include/mach/bfin_sir.h deleted file mode 100644 index cfd8ad4f1f2c..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/bfin_sir.h +++ /dev/null | |||
| @@ -1,142 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Blackfin Infra-red Driver | ||
| 3 | * | ||
| 4 | * Copyright 2006-2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Enter bugs at http://blackfin.uclinux.org/ | ||
| 7 | * | ||
| 8 | * Licensed under the GPL-2 or later. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/serial.h> | ||
| 13 | #include <asm/dma.h> | ||
| 14 | #include <asm/portmux.h> | ||
| 15 | |||
| 16 | #define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) | ||
| 17 | #define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) | ||
| 18 | #define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) | ||
| 19 | #define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) | ||
| 20 | #define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) | ||
| 21 | #define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) | ||
| 22 | #define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) | ||
| 23 | |||
| 24 | #define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) | ||
| 25 | #define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) | ||
| 26 | #define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) | ||
| 27 | #define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) | ||
| 28 | #define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) | ||
| 29 | #define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) | ||
| 30 | |||
| 31 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 32 | struct dma_rx_buf { | ||
| 33 | char *buf; | ||
| 34 | int head; | ||
| 35 | int tail; | ||
| 36 | }; | ||
| 37 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 38 | |||
| 39 | struct bfin_sir_port { | ||
| 40 | unsigned char __iomem *membase; | ||
| 41 | unsigned int irq; | ||
| 42 | unsigned int lsr; | ||
| 43 | unsigned long clk; | ||
| 44 | struct net_device *dev; | ||
| 45 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 46 | int tx_done; | ||
| 47 | struct dma_rx_buf rx_dma_buf; | ||
| 48 | struct timer_list rx_dma_timer; | ||
| 49 | int rx_dma_nrows; | ||
| 50 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 51 | unsigned int tx_dma_channel; | ||
| 52 | unsigned int rx_dma_channel; | ||
| 53 | }; | ||
| 54 | |||
| 55 | struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; | ||
| 56 | |||
| 57 | struct bfin_sir_port_res { | ||
| 58 | unsigned long base_addr; | ||
| 59 | int irq; | ||
| 60 | unsigned int rx_dma_channel; | ||
| 61 | unsigned int tx_dma_channel; | ||
| 62 | }; | ||
| 63 | |||
| 64 | struct bfin_sir_port_res bfin_sir_port_resource[] = { | ||
| 65 | #ifdef CONFIG_BFIN_SIR0 | ||
| 66 | { | ||
| 67 | 0xFFC00400, | ||
| 68 | IRQ_UART0_RX, | ||
| 69 | CH_UART0_RX, | ||
| 70 | CH_UART0_TX, | ||
| 71 | }, | ||
| 72 | #endif | ||
| 73 | #ifdef CONFIG_BFIN_SIR1 | ||
| 74 | { | ||
| 75 | 0xFFC02000, | ||
| 76 | IRQ_UART1_RX, | ||
| 77 | CH_UART1_RX, | ||
| 78 | CH_UART1_TX, | ||
| 79 | }, | ||
| 80 | #endif | ||
| 81 | }; | ||
| 82 | |||
| 83 | int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); | ||
| 84 | |||
| 85 | struct bfin_sir_self { | ||
| 86 | struct bfin_sir_port *sir_port; | ||
| 87 | spinlock_t lock; | ||
| 88 | unsigned int open; | ||
| 89 | int speed; | ||
| 90 | int newspeed; | ||
| 91 | |||
| 92 | struct sk_buff *txskb; | ||
| 93 | struct sk_buff *rxskb; | ||
| 94 | struct net_device_stats stats; | ||
| 95 | struct device *dev; | ||
| 96 | struct irlap_cb *irlap; | ||
| 97 | struct qos_info qos; | ||
| 98 | |||
| 99 | iobuff_t tx_buff; | ||
| 100 | iobuff_t rx_buff; | ||
| 101 | |||
| 102 | struct work_struct work; | ||
| 103 | int mtt; | ||
| 104 | }; | ||
| 105 | |||
| 106 | static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) | ||
| 107 | { | ||
| 108 | unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); | ||
| 109 | port->lsr |= (lsr & (BI|FE|PE|OE)); | ||
| 110 | return lsr | port->lsr; | ||
| 111 | } | ||
| 112 | |||
| 113 | static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) | ||
| 114 | { | ||
| 115 | port->lsr = 0; | ||
| 116 | bfin_read16(port->membase + OFFSET_LSR); | ||
| 117 | } | ||
| 118 | |||
| 119 | #define DRIVER_NAME "bfin_sir" | ||
| 120 | |||
| 121 | static int bfin_sir_hw_init(void) | ||
| 122 | { | ||
| 123 | int ret = -ENODEV; | ||
| 124 | #ifdef CONFIG_BFIN_SIR0 | ||
| 125 | ret = peripheral_request(P_UART0_TX, DRIVER_NAME); | ||
| 126 | if (ret) | ||
| 127 | return ret; | ||
| 128 | ret = peripheral_request(P_UART0_RX, DRIVER_NAME); | ||
| 129 | if (ret) | ||
| 130 | return ret; | ||
| 131 | #endif | ||
| 132 | |||
| 133 | #ifdef CONFIG_BFIN_SIR1 | ||
| 134 | ret = peripheral_request(P_UART1_TX, DRIVER_NAME); | ||
| 135 | if (ret) | ||
| 136 | return ret; | ||
| 137 | ret = peripheral_request(P_UART1_RX, DRIVER_NAME); | ||
| 138 | if (ret) | ||
| 139 | return ret; | ||
| 140 | #endif | ||
| 141 | return ret; | ||
| 142 | } | ||
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h index cffc786b2a2b..7d6069c886f1 100644 --- a/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h | |||
| @@ -82,7 +82,7 @@ | |||
| 82 | #define STATUS_P1 0x02 | 82 | #define STATUS_P1 0x02 |
| 83 | #define STATUS_P0 0x01 | 83 | #define STATUS_P0 0x01 |
| 84 | 84 | ||
| 85 | /* DMA Channnel */ | 85 | /* DMA Channel */ |
| 86 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() | 86 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX() |
| 87 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) | 87 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val) |
| 88 | #define CH_UART_RX CH_UART0_RX | 88 | #define CH_UART_RX CH_UART0_RX |
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h index 88d491cd9f36..5f8b5f845be6 100644 --- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h | |||
| @@ -40,55 +40,11 @@ | |||
| 40 | /* Include core specific register pointer definitions */ | 40 | /* Include core specific register pointer definitions */ |
| 41 | #include <asm/cdef_LPBlackfin.h> | 41 | #include <asm/cdef_LPBlackfin.h> |
| 42 | 42 | ||
| 43 | #include <asm/system.h> | ||
| 44 | |||
| 45 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | 43 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ |
| 46 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | 44 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 47 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 48 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 49 | { | ||
| 50 | unsigned long flags, iwr; | ||
| 51 | |||
| 52 | if (val == bfin_read_PLL_CTL()) | ||
| 53 | return; | ||
| 54 | |||
| 55 | local_irq_save(flags); | ||
| 56 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 57 | iwr = bfin_read32(SIC_IWR); | ||
| 58 | /* Only allow PPL Wakeup) */ | ||
| 59 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
| 60 | |||
| 61 | bfin_write16(PLL_CTL, val); | ||
| 62 | SSYNC(); | ||
| 63 | asm("IDLE;"); | ||
| 64 | |||
| 65 | bfin_write32(SIC_IWR, iwr); | ||
| 66 | local_irq_restore(flags); | ||
| 67 | } | ||
| 68 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | 45 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 69 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) | 46 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) |
| 70 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | 47 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| 71 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 72 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 73 | { | ||
| 74 | unsigned long flags, iwr; | ||
| 75 | |||
| 76 | if (val == bfin_read_VR_CTL()) | ||
| 77 | return; | ||
| 78 | |||
| 79 | local_irq_save(flags); | ||
| 80 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 81 | iwr = bfin_read32(SIC_IWR); | ||
| 82 | /* Only allow PPL Wakeup) */ | ||
| 83 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
| 84 | |||
| 85 | bfin_write16(VR_CTL, val); | ||
| 86 | SSYNC(); | ||
| 87 | asm("IDLE;"); | ||
| 88 | |||
| 89 | bfin_write32(SIC_IWR, iwr); | ||
| 90 | local_irq_restore(flags); | ||
| 91 | } | ||
| 92 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | 48 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 93 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) | 49 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) |
| 94 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | 50 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| @@ -1816,4 +1772,51 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1816 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) | 1772 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) |
| 1817 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) | 1773 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val) |
| 1818 | 1774 | ||
| 1775 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 1776 | #include <asm/irq.h> | ||
| 1777 | |||
| 1778 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 1779 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 1780 | { | ||
| 1781 | unsigned long flags, iwr; | ||
| 1782 | |||
| 1783 | if (val == bfin_read_PLL_CTL()) | ||
| 1784 | return; | ||
| 1785 | |||
| 1786 | local_irq_save_hw(flags); | ||
| 1787 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 1788 | iwr = bfin_read32(SIC_IWR); | ||
| 1789 | /* Only allow PPL Wakeup) */ | ||
| 1790 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
| 1791 | |||
| 1792 | bfin_write16(PLL_CTL, val); | ||
| 1793 | SSYNC(); | ||
| 1794 | asm("IDLE;"); | ||
| 1795 | |||
| 1796 | bfin_write32(SIC_IWR, iwr); | ||
| 1797 | local_irq_restore_hw(flags); | ||
| 1798 | } | ||
| 1799 | |||
| 1800 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 1801 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 1802 | { | ||
| 1803 | unsigned long flags, iwr; | ||
| 1804 | |||
| 1805 | if (val == bfin_read_VR_CTL()) | ||
| 1806 | return; | ||
| 1807 | |||
| 1808 | local_irq_save_hw(flags); | ||
| 1809 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 1810 | iwr = bfin_read32(SIC_IWR); | ||
| 1811 | /* Only allow PPL Wakeup) */ | ||
| 1812 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
| 1813 | |||
| 1814 | bfin_write16(VR_CTL, val); | ||
| 1815 | SSYNC(); | ||
| 1816 | asm("IDLE;"); | ||
| 1817 | |||
| 1818 | bfin_write32(SIC_IWR, iwr); | ||
| 1819 | local_irq_restore_hw(flags); | ||
| 1820 | } | ||
| 1821 | |||
| 1819 | #endif /* _CDEF_BF534_H */ | 1822 | #endif /* _CDEF_BF534_H */ |
diff --git a/arch/blackfin/mach-bf537/include/mach/dma.h b/arch/blackfin/mach-bf537/include/mach/dma.h index 7a964040870a..5ae83b1183a1 100644 --- a/arch/blackfin/mach-bf537/include/mach/dma.h +++ b/arch/blackfin/mach-bf537/include/mach/dma.h | |||
| @@ -1,38 +1,14 @@ | |||
| 1 | /* | 1 | /* mach/dma.h - arch-specific DMA defines |
| 2 | * file: include/asm-blackfin/mach-bf537/dma.h | ||
| 3 | * based on: | ||
| 4 | * author: | ||
| 5 | * | 2 | * |
| 6 | * created: | 3 | * Copyright 2004-2008 Analog Devices Inc. |
| 7 | * description: | ||
| 8 | * system mmr register map | ||
| 9 | * rev: | ||
| 10 | * | 4 | * |
| 11 | * modified: | 5 | * Licensed under the GPL-2 or later. |
| 12 | * | ||
| 13 | * | ||
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * this program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the gnu general public license as published by | ||
| 18 | * the free software foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * this program is distributed in the hope that it will be useful, | ||
| 22 | * but without any warranty; without even the implied warranty of | ||
| 23 | * merchantability or fitness for a particular purpose. see the | ||
| 24 | * gnu general public license for more details. | ||
| 25 | * | ||
| 26 | * you should have received a copy of the gnu general public license | ||
| 27 | * along with this program; see the file copying. | ||
| 28 | * if not, write to the free software foundation, | ||
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 30 | */ | 6 | */ |
| 31 | 7 | ||
| 32 | #ifndef _MACH_DMA_H_ | 8 | #ifndef _MACH_DMA_H_ |
| 33 | #define _MACH_DMA_H_ | 9 | #define _MACH_DMA_H_ |
| 34 | 10 | ||
| 35 | #define MAX_BLACKFIN_DMA_CHANNEL 16 | 11 | #define MAX_DMA_CHANNELS 16 |
| 36 | 12 | ||
| 37 | #define CH_PPI 0 | 13 | #define CH_PPI 0 |
| 38 | #define CH_EMAC_RX 1 | 14 | #define CH_EMAC_RX 1 |
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h new file mode 100644 index 000000000000..d77a31e45a30 --- /dev/null +++ b/arch/blackfin/mach-bf537/include/mach/gpio.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf537/include/mach/gpio.h | ||
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 4 | * | ||
| 5 | * Copyright (C) 2008 Analog Devices Inc. | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | #ifndef _MACH_GPIO_H_ | ||
| 11 | #define _MACH_GPIO_H_ | ||
| 12 | |||
| 13 | #define MAX_BLACKFIN_GPIOS 48 | ||
| 14 | |||
| 15 | #define GPIO_PF0 0 | ||
| 16 | #define GPIO_PF1 1 | ||
| 17 | #define GPIO_PF2 2 | ||
| 18 | #define GPIO_PF3 3 | ||
| 19 | #define GPIO_PF4 4 | ||
| 20 | #define GPIO_PF5 5 | ||
| 21 | #define GPIO_PF6 6 | ||
| 22 | #define GPIO_PF7 7 | ||
| 23 | #define GPIO_PF8 8 | ||
| 24 | #define GPIO_PF9 9 | ||
| 25 | #define GPIO_PF10 10 | ||
| 26 | #define GPIO_PF11 11 | ||
| 27 | #define GPIO_PF12 12 | ||
| 28 | #define GPIO_PF13 13 | ||
| 29 | #define GPIO_PF14 14 | ||
| 30 | #define GPIO_PF15 15 | ||
| 31 | #define GPIO_PG0 16 | ||
| 32 | #define GPIO_PG1 17 | ||
| 33 | #define GPIO_PG2 18 | ||
| 34 | #define GPIO_PG3 19 | ||
| 35 | #define GPIO_PG4 20 | ||
| 36 | #define GPIO_PG5 21 | ||
| 37 | #define GPIO_PG6 22 | ||
| 38 | #define GPIO_PG7 23 | ||
| 39 | #define GPIO_PG8 24 | ||
| 40 | #define GPIO_PG9 25 | ||
| 41 | #define GPIO_PG10 26 | ||
| 42 | #define GPIO_PG11 27 | ||
| 43 | #define GPIO_PG12 28 | ||
| 44 | #define GPIO_PG13 29 | ||
| 45 | #define GPIO_PG14 30 | ||
| 46 | #define GPIO_PG15 31 | ||
| 47 | #define GPIO_PH0 32 | ||
| 48 | #define GPIO_PH1 33 | ||
| 49 | #define GPIO_PH2 34 | ||
| 50 | #define GPIO_PH3 35 | ||
| 51 | #define GPIO_PH4 36 | ||
| 52 | #define GPIO_PH5 37 | ||
| 53 | #define GPIO_PH6 38 | ||
| 54 | #define GPIO_PH7 39 | ||
| 55 | #define GPIO_PH8 40 | ||
| 56 | #define GPIO_PH9 41 | ||
| 57 | #define GPIO_PH10 42 | ||
| 58 | #define GPIO_PH11 43 | ||
| 59 | #define GPIO_PH12 44 | ||
| 60 | #define GPIO_PH13 45 | ||
| 61 | #define GPIO_PH14 46 | ||
| 62 | #define GPIO_PH15 47 | ||
| 63 | |||
| 64 | #define PORT_F GPIO_PF0 | ||
| 65 | #define PORT_G GPIO_PG0 | ||
| 66 | #define PORT_H GPIO_PH0 | ||
| 67 | |||
| 68 | #endif /* _MACH_GPIO_H_ */ | ||
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h index 2e68a8a1e730..b2a71d5d4e5f 100644 --- a/arch/blackfin/mach-bf537/include/mach/irq.h +++ b/arch/blackfin/mach-bf537/include/mach/irq.h | |||
| @@ -82,14 +82,14 @@ | |||
| 82 | #define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ | 82 | #define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ |
| 83 | #define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ | 83 | #define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ |
| 84 | #define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ | 84 | #define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ |
| 85 | #define IRQ_TMR0 26 /*Timer 0 */ | 85 | #define IRQ_TIMER0 26 /*Timer 0 */ |
| 86 | #define IRQ_TMR1 27 /*Timer 1 */ | 86 | #define IRQ_TIMER1 27 /*Timer 1 */ |
| 87 | #define IRQ_TMR2 28 /*Timer 2 */ | 87 | #define IRQ_TIMER2 28 /*Timer 2 */ |
| 88 | #define IRQ_TMR3 29 /*Timer 3 */ | 88 | #define IRQ_TIMER3 29 /*Timer 3 */ |
| 89 | #define IRQ_TMR4 30 /*Timer 4 */ | 89 | #define IRQ_TIMER4 30 /*Timer 4 */ |
| 90 | #define IRQ_TMR5 31 /*Timer 5 */ | 90 | #define IRQ_TIMER5 31 /*Timer 5 */ |
| 91 | #define IRQ_TMR6 32 /*Timer 6 */ | 91 | #define IRQ_TIMER6 32 /*Timer 6 */ |
| 92 | #define IRQ_TMR7 33 /*Timer 7 */ | 92 | #define IRQ_TIMER7 33 /*Timer 7 */ |
| 93 | #define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ | 93 | #define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ |
| 94 | #define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ | 94 | #define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ |
| 95 | #define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ | 95 | #define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ |
| @@ -195,16 +195,16 @@ | |||
| 195 | #define IRQ_CAN_TX_POS 0 | 195 | #define IRQ_CAN_TX_POS 0 |
| 196 | #define IRQ_MAC_RX_POS 4 | 196 | #define IRQ_MAC_RX_POS 4 |
| 197 | #define IRQ_MAC_TX_POS 8 | 197 | #define IRQ_MAC_TX_POS 8 |
| 198 | #define IRQ_TMR0_POS 12 | 198 | #define IRQ_TIMER0_POS 12 |
| 199 | #define IRQ_TMR1_POS 16 | 199 | #define IRQ_TIMER1_POS 16 |
| 200 | #define IRQ_TMR2_POS 20 | 200 | #define IRQ_TIMER2_POS 20 |
| 201 | #define IRQ_TMR3_POS 24 | 201 | #define IRQ_TIMER3_POS 24 |
| 202 | #define IRQ_TMR4_POS 28 | 202 | #define IRQ_TIMER4_POS 28 |
| 203 | 203 | ||
| 204 | /* IAR3 BIT FIELDS*/ | 204 | /* IAR3 BIT FIELDS*/ |
| 205 | #define IRQ_TMR5_POS 0 | 205 | #define IRQ_TIMER5_POS 0 |
| 206 | #define IRQ_TMR6_POS 4 | 206 | #define IRQ_TIMER6_POS 4 |
| 207 | #define IRQ_TMR7_POS 8 | 207 | #define IRQ_TIMER7_POS 8 |
| 208 | #define IRQ_PROG_INTA_POS 12 | 208 | #define IRQ_PROG_INTA_POS 12 |
| 209 | #define IRQ_PORTG_INTB_POS 16 | 209 | #define IRQ_PORTG_INTB_POS 16 |
| 210 | #define IRQ_MEM_DMA0_POS 20 | 210 | #define IRQ_MEM_DMA0_POS 20 |
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_init.h b/arch/blackfin/mach-bf537/include/mach/mem_init.h deleted file mode 100644 index f67698f670ca..000000000000 --- a/arch/blackfin/mach-bf537/include/mach/mem_init.h +++ /dev/null | |||
| @@ -1,303 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf537/mem_init.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75) | ||
| 33 | #if (CONFIG_SCLK_HZ > 119402985) | ||
| 34 | #define SDRAM_tRP TRP_2 | ||
| 35 | #define SDRAM_tRP_num 2 | ||
| 36 | #define SDRAM_tRAS TRAS_7 | ||
| 37 | #define SDRAM_tRAS_num 7 | ||
| 38 | #define SDRAM_tRCD TRCD_2 | ||
| 39 | #define SDRAM_tWR TWR_2 | ||
| 40 | #endif | ||
| 41 | #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) | ||
| 42 | #define SDRAM_tRP TRP_2 | ||
| 43 | #define SDRAM_tRP_num 2 | ||
| 44 | #define SDRAM_tRAS TRAS_6 | ||
| 45 | #define SDRAM_tRAS_num 6 | ||
| 46 | #define SDRAM_tRCD TRCD_2 | ||
| 47 | #define SDRAM_tWR TWR_2 | ||
| 48 | #endif | ||
| 49 | #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) | ||
| 50 | #define SDRAM_tRP TRP_2 | ||
| 51 | #define SDRAM_tRP_num 2 | ||
| 52 | #define SDRAM_tRAS TRAS_5 | ||
| 53 | #define SDRAM_tRAS_num 5 | ||
| 54 | #define SDRAM_tRCD TRCD_2 | ||
| 55 | #define SDRAM_tWR TWR_2 | ||
| 56 | #endif | ||
| 57 | #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) | ||
| 58 | #define SDRAM_tRP TRP_2 | ||
| 59 | #define SDRAM_tRP_num 2 | ||
| 60 | #define SDRAM_tRAS TRAS_4 | ||
| 61 | #define SDRAM_tRAS_num 4 | ||
| 62 | #define SDRAM_tRCD TRCD_2 | ||
| 63 | #define SDRAM_tWR TWR_2 | ||
| 64 | #endif | ||
| 65 | #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) | ||
| 66 | #define SDRAM_tRP TRP_2 | ||
| 67 | #define SDRAM_tRP_num 2 | ||
| 68 | #define SDRAM_tRAS TRAS_3 | ||
| 69 | #define SDRAM_tRAS_num 3 | ||
| 70 | #define SDRAM_tRCD TRCD_2 | ||
| 71 | #define SDRAM_tWR TWR_2 | ||
| 72 | #endif | ||
| 73 | #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) | ||
| 74 | #define SDRAM_tRP TRP_1 | ||
| 75 | #define SDRAM_tRP_num 1 | ||
| 76 | #define SDRAM_tRAS TRAS_4 | ||
| 77 | #define SDRAM_tRAS_num 3 | ||
| 78 | #define SDRAM_tRCD TRCD_1 | ||
| 79 | #define SDRAM_tWR TWR_2 | ||
| 80 | #endif | ||
| 81 | #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) | ||
| 82 | #define SDRAM_tRP TRP_1 | ||
| 83 | #define SDRAM_tRP_num 1 | ||
| 84 | #define SDRAM_tRAS TRAS_3 | ||
| 85 | #define SDRAM_tRAS_num 3 | ||
| 86 | #define SDRAM_tRCD TRCD_1 | ||
| 87 | #define SDRAM_tWR TWR_2 | ||
| 88 | #endif | ||
| 89 | #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) | ||
| 90 | #define SDRAM_tRP TRP_1 | ||
| 91 | #define SDRAM_tRP_num 1 | ||
| 92 | #define SDRAM_tRAS TRAS_2 | ||
| 93 | #define SDRAM_tRAS_num 2 | ||
| 94 | #define SDRAM_tRCD TRCD_1 | ||
| 95 | #define SDRAM_tWR TWR_2 | ||
| 96 | #endif | ||
| 97 | #if (CONFIG_SCLK_HZ <= 29850746) | ||
| 98 | #define SDRAM_tRP TRP_1 | ||
| 99 | #define SDRAM_tRP_num 1 | ||
| 100 | #define SDRAM_tRAS TRAS_1 | ||
| 101 | #define SDRAM_tRAS_num 1 | ||
| 102 | #define SDRAM_tRCD TRCD_1 | ||
| 103 | #define SDRAM_tWR TWR_2 | ||
| 104 | #endif | ||
| 105 | #endif | ||
| 106 | |||
| 107 | #if (CONFIG_MEM_MT48LC16M16A2TG_75) | ||
| 108 | /*SDRAM INFORMATION: */ | ||
| 109 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 110 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 111 | #define SDRAM_CL CL_3 | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #if (CONFIG_MEM_MT48LC16M8A2TG_75) | ||
| 115 | /*SDRAM INFORMATION: */ | ||
| 116 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 117 | #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ | ||
| 118 | #define SDRAM_CL CL_3 | ||
| 119 | #endif | ||
| 120 | |||
| 121 | #if (CONFIG_MEM_MT48LC32M8A2_75) | ||
| 122 | /*SDRAM INFORMATION: */ | ||
| 123 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 124 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 125 | #define SDRAM_CL CL_3 | ||
| 126 | #endif | ||
| 127 | |||
| 128 | #if (CONFIG_MEM_MT48LC64M4A2FB_7E) | ||
| 129 | /*SDRAM INFORMATION: */ | ||
| 130 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 131 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 132 | #define SDRAM_CL CL_3 | ||
| 133 | #endif | ||
| 134 | |||
| 135 | #if (CONFIG_MEM_GENERIC_BOARD) | ||
| 136 | /*SDRAM INFORMATION: Modify this for your board */ | ||
| 137 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 138 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 139 | #define SDRAM_CL CL_3 | ||
| 140 | #endif | ||
| 141 | |||
| 142 | /* Equation from section 17 (p17-46) of BF533 HRM */ | ||
| 143 | #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) | ||
| 144 | |||
| 145 | /* Enable SCLK Out */ | ||
| 146 | #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) | ||
| 147 | |||
| 148 | #if defined CONFIG_CLKIN_HALF | ||
| 149 | #define CLKIN_HALF 1 | ||
| 150 | #else | ||
| 151 | #define CLKIN_HALF 0 | ||
| 152 | #endif | ||
| 153 | |||
| 154 | #if defined CONFIG_PLL_BYPASS | ||
| 155 | #define PLL_BYPASS 1 | ||
| 156 | #else | ||
| 157 | #define PLL_BYPASS 0 | ||
| 158 | #endif | ||
| 159 | |||
| 160 | /***************************************Currently Not Being Used *********************************/ | ||
| 161 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 162 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 163 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) | ||
| 164 | #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 165 | #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 166 | |||
| 167 | #if (flash_EBIU_AMBCTL_TT > 3) | ||
| 168 | #define flash_EBIU_AMBCTL0_TT B0TT_4 | ||
| 169 | #endif | ||
| 170 | #if (flash_EBIU_AMBCTL_TT == 3) | ||
| 171 | #define flash_EBIU_AMBCTL0_TT B0TT_3 | ||
| 172 | #endif | ||
| 173 | #if (flash_EBIU_AMBCTL_TT == 2) | ||
| 174 | #define flash_EBIU_AMBCTL0_TT B0TT_2 | ||
| 175 | #endif | ||
| 176 | #if (flash_EBIU_AMBCTL_TT < 2) | ||
| 177 | #define flash_EBIU_AMBCTL0_TT B0TT_1 | ||
| 178 | #endif | ||
| 179 | |||
| 180 | #if (flash_EBIU_AMBCTL_ST > 3) | ||
| 181 | #define flash_EBIU_AMBCTL0_ST B0ST_4 | ||
| 182 | #endif | ||
| 183 | #if (flash_EBIU_AMBCTL_ST == 3) | ||
| 184 | #define flash_EBIU_AMBCTL0_ST B0ST_3 | ||
| 185 | #endif | ||
| 186 | #if (flash_EBIU_AMBCTL_ST == 2) | ||
| 187 | #define flash_EBIU_AMBCTL0_ST B0ST_2 | ||
| 188 | #endif | ||
| 189 | #if (flash_EBIU_AMBCTL_ST < 2) | ||
| 190 | #define flash_EBIU_AMBCTL0_ST B0ST_1 | ||
| 191 | #endif | ||
| 192 | |||
| 193 | #if (flash_EBIU_AMBCTL_HT > 2) | ||
| 194 | #define flash_EBIU_AMBCTL0_HT B0HT_3 | ||
| 195 | #endif | ||
| 196 | #if (flash_EBIU_AMBCTL_HT == 2) | ||
| 197 | #define flash_EBIU_AMBCTL0_HT B0HT_2 | ||
| 198 | #endif | ||
| 199 | #if (flash_EBIU_AMBCTL_HT == 1) | ||
| 200 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 201 | #endif | ||
| 202 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) | ||
| 203 | #define flash_EBIU_AMBCTL0_HT B0HT_0 | ||
| 204 | #endif | ||
| 205 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) | ||
| 206 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 207 | #endif | ||
| 208 | |||
| 209 | #if (flash_EBIU_AMBCTL_WAT > 14) | ||
| 210 | #define flash_EBIU_AMBCTL0_WAT B0WAT_15 | ||
| 211 | #endif | ||
| 212 | #if (flash_EBIU_AMBCTL_WAT == 14) | ||
| 213 | #define flash_EBIU_AMBCTL0_WAT B0WAT_14 | ||
| 214 | #endif | ||
| 215 | #if (flash_EBIU_AMBCTL_WAT == 13) | ||
| 216 | #define flash_EBIU_AMBCTL0_WAT B0WAT_13 | ||
| 217 | #endif | ||
| 218 | #if (flash_EBIU_AMBCTL_WAT == 12) | ||
| 219 | #define flash_EBIU_AMBCTL0_WAT B0WAT_12 | ||
| 220 | #endif | ||
| 221 | #if (flash_EBIU_AMBCTL_WAT == 11) | ||
| 222 | #define flash_EBIU_AMBCTL0_WAT B0WAT_11 | ||
| 223 | #endif | ||
| 224 | #if (flash_EBIU_AMBCTL_WAT == 10) | ||
| 225 | #define flash_EBIU_AMBCTL0_WAT B0WAT_10 | ||
| 226 | #endif | ||
| 227 | #if (flash_EBIU_AMBCTL_WAT == 9) | ||
| 228 | #define flash_EBIU_AMBCTL0_WAT B0WAT_9 | ||
| 229 | #endif | ||
| 230 | #if (flash_EBIU_AMBCTL_WAT == 8) | ||
| 231 | #define flash_EBIU_AMBCTL0_WAT B0WAT_8 | ||
| 232 | #endif | ||
| 233 | #if (flash_EBIU_AMBCTL_WAT == 7) | ||
| 234 | #define flash_EBIU_AMBCTL0_WAT B0WAT_7 | ||
| 235 | #endif | ||
| 236 | #if (flash_EBIU_AMBCTL_WAT == 6) | ||
| 237 | #define flash_EBIU_AMBCTL0_WAT B0WAT_6 | ||
| 238 | #endif | ||
| 239 | #if (flash_EBIU_AMBCTL_WAT == 5) | ||
| 240 | #define flash_EBIU_AMBCTL0_WAT B0WAT_5 | ||
| 241 | #endif | ||
| 242 | #if (flash_EBIU_AMBCTL_WAT == 4) | ||
| 243 | #define flash_EBIU_AMBCTL0_WAT B0WAT_4 | ||
| 244 | #endif | ||
| 245 | #if (flash_EBIU_AMBCTL_WAT == 3) | ||
| 246 | #define flash_EBIU_AMBCTL0_WAT B0WAT_3 | ||
| 247 | #endif | ||
| 248 | #if (flash_EBIU_AMBCTL_WAT == 2) | ||
| 249 | #define flash_EBIU_AMBCTL0_WAT B0WAT_2 | ||
| 250 | #endif | ||
| 251 | #if (flash_EBIU_AMBCTL_WAT == 1) | ||
| 252 | #define flash_EBIU_AMBCTL0_WAT B0WAT_1 | ||
| 253 | #endif | ||
| 254 | |||
| 255 | #if (flash_EBIU_AMBCTL_RAT > 14) | ||
| 256 | #define flash_EBIU_AMBCTL0_RAT B0RAT_15 | ||
| 257 | #endif | ||
| 258 | #if (flash_EBIU_AMBCTL_RAT == 14) | ||
| 259 | #define flash_EBIU_AMBCTL0_RAT B0RAT_14 | ||
| 260 | #endif | ||
| 261 | #if (flash_EBIU_AMBCTL_RAT == 13) | ||
| 262 | #define flash_EBIU_AMBCTL0_RAT B0RAT_13 | ||
| 263 | #endif | ||
| 264 | #if (flash_EBIU_AMBCTL_RAT == 12) | ||
| 265 | #define flash_EBIU_AMBCTL0_RAT B0RAT_12 | ||
| 266 | #endif | ||
| 267 | #if (flash_EBIU_AMBCTL_RAT == 11) | ||
| 268 | #define flash_EBIU_AMBCTL0_RAT B0RAT_11 | ||
| 269 | #endif | ||
| 270 | #if (flash_EBIU_AMBCTL_RAT == 10) | ||
| 271 | #define flash_EBIU_AMBCTL0_RAT B0RAT_10 | ||
| 272 | #endif | ||
| 273 | #if (flash_EBIU_AMBCTL_RAT == 9) | ||
| 274 | #define flash_EBIU_AMBCTL0_RAT B0RAT_9 | ||
| 275 | #endif | ||
| 276 | #if (flash_EBIU_AMBCTL_RAT == 8) | ||
| 277 | #define flash_EBIU_AMBCTL0_RAT B0RAT_8 | ||
| 278 | #endif | ||
| 279 | #if (flash_EBIU_AMBCTL_RAT == 7) | ||
| 280 | #define flash_EBIU_AMBCTL0_RAT B0RAT_7 | ||
| 281 | #endif | ||
| 282 | #if (flash_EBIU_AMBCTL_RAT == 6) | ||
| 283 | #define flash_EBIU_AMBCTL0_RAT B0RAT_6 | ||
| 284 | #endif | ||
| 285 | #if (flash_EBIU_AMBCTL_RAT == 5) | ||
| 286 | #define flash_EBIU_AMBCTL0_RAT B0RAT_5 | ||
| 287 | #endif | ||
| 288 | #if (flash_EBIU_AMBCTL_RAT == 4) | ||
| 289 | #define flash_EBIU_AMBCTL0_RAT B0RAT_4 | ||
| 290 | #endif | ||
| 291 | #if (flash_EBIU_AMBCTL_RAT == 3) | ||
| 292 | #define flash_EBIU_AMBCTL0_RAT B0RAT_3 | ||
| 293 | #endif | ||
| 294 | #if (flash_EBIU_AMBCTL_RAT == 2) | ||
| 295 | #define flash_EBIU_AMBCTL0_RAT B0RAT_2 | ||
| 296 | #endif | ||
| 297 | #if (flash_EBIU_AMBCTL_RAT == 1) | ||
| 298 | #define flash_EBIU_AMBCTL0_RAT B0RAT_1 | ||
| 299 | #endif | ||
| 300 | |||
| 301 | #define flash_EBIU_AMBCTL0 \ | ||
| 302 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ | ||
| 303 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) | ||
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h index 5078b669431f..f9010c4b4bf3 100644 --- a/arch/blackfin/mach-bf537/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf537/include/mach/mem_map.h | |||
| @@ -176,4 +176,10 @@ | |||
| 176 | #define L1_SCRATCH_START 0xFFB00000 | 176 | #define L1_SCRATCH_START 0xFFB00000 |
| 177 | #define L1_SCRATCH_LENGTH 0x1000 | 177 | #define L1_SCRATCH_LENGTH 0x1000 |
| 178 | 178 | ||
| 179 | #define GET_PDA_SAFE(preg) \ | ||
| 180 | preg.l = _cpu_pda; \ | ||
| 181 | preg.h = _cpu_pda; | ||
| 182 | |||
| 183 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 184 | |||
| 179 | #endif /* _MEM_MAP_537_H_ */ | 185 | #endif /* _MEM_MAP_537_H_ */ |
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c index b1300b3f1812..51c48087e03b 100644 --- a/arch/blackfin/mach-bf537/ints-priority.c +++ b/arch/blackfin/mach-bf537/ints-priority.c | |||
| @@ -55,15 +55,15 @@ void __init program_IAR(void) | |||
| 55 | bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) | | 55 | bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) | |
| 56 | ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) | | 56 | ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) | |
| 57 | ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | | 57 | ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) | |
| 58 | ((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) | | 58 | ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | |
| 59 | ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) | | 59 | ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | |
| 60 | ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) | | 60 | ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | |
| 61 | ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) | | 61 | ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | |
| 62 | ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS)); | 62 | ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); |
| 63 | 63 | ||
| 64 | bfin_write_SIC_IAR3(((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) | | 64 | bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | |
| 65 | ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) | | 65 | ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | |
| 66 | ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS) | | 66 | ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | |
| 67 | ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) | | 67 | ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) | |
| 68 | ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | | 68 | ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) | |
| 69 | ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) | | 69 | ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) | |
diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig new file mode 100644 index 000000000000..f068c3523cdc --- /dev/null +++ b/arch/blackfin/mach-bf538/Kconfig | |||
| @@ -0,0 +1,164 @@ | |||
| 1 | if (BF538 || BF539) | ||
| 2 | |||
| 3 | source "arch/blackfin/mach-bf538/boards/Kconfig" | ||
| 4 | |||
| 5 | menu "BF538 Specific Configuration" | ||
| 6 | |||
| 7 | comment "Interrupt Priority Assignment" | ||
| 8 | menu "Priority" | ||
| 9 | |||
| 10 | config IRQ_PLL_WAKEUP | ||
| 11 | int "IRQ_PLL_WAKEUP" | ||
| 12 | default 7 | ||
| 13 | config IRQ_DMA0_ERROR | ||
| 14 | int "IRQ_DMA0_ERROR" | ||
| 15 | default 7 | ||
| 16 | config IRQ_PPI_ERROR | ||
| 17 | int "IRQ_PPI_ERROR" | ||
| 18 | default 7 | ||
| 19 | config IRQ_SPORT0_ERROR | ||
| 20 | int "IRQ_SPORT0_ERROR" | ||
| 21 | default 7 | ||
| 22 | config IRQ_SPORT1_ERROR | ||
| 23 | int "IRQ_SPORT1_ERROR" | ||
| 24 | default 7 | ||
| 25 | config IRQ_SPI0_ERROR | ||
| 26 | int "IRQ_SPI0_ERROR" | ||
| 27 | default 7 | ||
| 28 | config IRQ_UART0_ERROR | ||
| 29 | int "IRQ_UART0_ERROR" | ||
| 30 | default 7 | ||
| 31 | config IRQ_RTC | ||
| 32 | int "IRQ_RTC" | ||
| 33 | default 8 | ||
| 34 | config IRQ_PPI | ||
| 35 | int "IRQ_PPI" | ||
| 36 | default 8 | ||
| 37 | config IRQ_SPORT0_RX | ||
| 38 | int "IRQ_SPORT0_RX" | ||
| 39 | default 9 | ||
| 40 | config IRQ_SPORT0_TX | ||
| 41 | int "IRQ_SPORT0_TX" | ||
| 42 | default 9 | ||
| 43 | config IRQ_SPORT1_RX | ||
| 44 | int "IRQ_SPORT1_RX" | ||
| 45 | default 9 | ||
| 46 | config IRQ_SPORT1_TX | ||
| 47 | int "IRQ_SPORT1_TX" | ||
| 48 | default 9 | ||
| 49 | config IRQ_SPI0 | ||
| 50 | int "IRQ_SPI0" | ||
| 51 | default 10 | ||
| 52 | config IRQ_UART0_RX | ||
| 53 | int "IRQ_UART0_RX" | ||
| 54 | default 10 | ||
| 55 | config IRQ_UART0_TX | ||
| 56 | int "IRQ_UART0_TX" | ||
| 57 | default 10 | ||
| 58 | config IRQ_TIMER0 | ||
| 59 | int "IRQ_TIMER0" | ||
| 60 | default 8 | ||
| 61 | config IRQ_TIMER1 | ||
| 62 | int "IRQ_TIMER1" | ||
| 63 | default 11 | ||
| 64 | config IRQ_TIMER2 | ||
| 65 | int "IRQ_TIMER2" | ||
| 66 | default 11 | ||
| 67 | config IRQ_PORTF_INTA | ||
| 68 | int "IRQ_PORTF_INTA" | ||
| 69 | default 12 | ||
| 70 | config IRQ_PORTF_INTB | ||
| 71 | int "IRQ_PORTF_INTB" | ||
| 72 | default 12 | ||
| 73 | config IRQ_MEM0_DMA0 | ||
| 74 | int "IRQ_MEM0_DMA0" | ||
| 75 | default 13 | ||
| 76 | config IRQ_MEM0_DMA1 | ||
| 77 | int "IRQ_MEM0_DMA1" | ||
| 78 | default 13 | ||
| 79 | config IRQ_WATCH | ||
| 80 | int "IRQ_WATCH" | ||
| 81 | default 13 | ||
| 82 | config IRQ_DMA1_ERROR | ||
| 83 | int "IRQ_DMA1_ERROR" | ||
| 84 | default 7 | ||
| 85 | config IRQ_SPORT2_ERROR | ||
| 86 | int "IRQ_SPORT2_ERROR" | ||
| 87 | default 7 | ||
| 88 | config IRQ_SPORT3_ERROR | ||
| 89 | int "IRQ_SPORT3_ERROR" | ||
| 90 | default 7 | ||
| 91 | config IRQ_SPI1_ERROR | ||
| 92 | int "IRQ_SPI1_ERROR" | ||
| 93 | default 7 | ||
| 94 | config IRQ_SPI2_ERROR | ||
| 95 | int "IRQ_SPI2_ERROR" | ||
| 96 | default 7 | ||
| 97 | config IRQ_UART1_ERROR | ||
| 98 | int "IRQ_UART1_ERROR" | ||
| 99 | default 7 | ||
| 100 | config IRQ_UART2_ERROR | ||
| 101 | int "IRQ_UART2_ERROR" | ||
| 102 | default 7 | ||
| 103 | config IRQ_CAN_ERROR | ||
| 104 | int "IRQ_CAN_ERROR" | ||
| 105 | default 7 | ||
| 106 | config IRQ_SPORT2_RX | ||
| 107 | int "IRQ_SPORT2_RX" | ||
| 108 | default 9 | ||
| 109 | config IRQ_SPORT2_TX | ||
| 110 | int "IRQ_SPORT2_TX" | ||
| 111 | default 9 | ||
| 112 | config IRQ_SPORT3_RX | ||
| 113 | int "IRQ_SPORT3_RX" | ||
| 114 | default 9 | ||
| 115 | config IRQ_SPORT3_TX | ||
| 116 | int "IRQ_SPORT3_TX" | ||
| 117 | default 9 | ||
| 118 | config IRQ_SPI1 | ||
| 119 | int "IRQ_SPI1" | ||
| 120 | default 10 | ||
| 121 | config IRQ_SPI2 | ||
| 122 | int "IRQ_SPI2" | ||
| 123 | default 10 | ||
| 124 | config IRQ_UART1_RX | ||
| 125 | int "IRQ_UART1_RX" | ||
| 126 | default 10 | ||
| 127 | config IRQ_UART1_TX | ||
| 128 | int "IRQ_UART1_TX" | ||
| 129 | default 10 | ||
| 130 | config IRQ_UART2_RX | ||
| 131 | int "IRQ_UART2_RX" | ||
| 132 | default 10 | ||
| 133 | config IRQ_UART2_TX | ||
| 134 | int "IRQ_UART2_TX" | ||
| 135 | default 10 | ||
| 136 | config IRQ_TWI0 | ||
| 137 | int "IRQ_TWI0" | ||
| 138 | default 11 | ||
| 139 | config IRQ_TWI1 | ||
| 140 | int "IRQ_TWI1" | ||
| 141 | default 11 | ||
| 142 | config IRQ_CAN_RX | ||
| 143 | int "IRQ_CAN_RX" | ||
| 144 | default 11 | ||
| 145 | config IRQ_CAN_TX | ||
| 146 | int "IRQ_CAN_TX" | ||
| 147 | default 11 | ||
| 148 | config IRQ_MEM1_DMA0 | ||
| 149 | int "IRQ_MEM1_DMA0" | ||
| 150 | default 13 | ||
| 151 | config IRQ_MEM1_DMA1 | ||
| 152 | int "IRQ_MEM1_DMA1" | ||
| 153 | default 13 | ||
| 154 | |||
| 155 | help | ||
| 156 | Enter the priority numbers between 7-13 ONLY. Others are Reserved. | ||
| 157 | This applies to all the above. It is not recommended to assign the | ||
| 158 | highest priority number 7 to UART or any other device. | ||
| 159 | |||
| 160 | endmenu | ||
| 161 | |||
| 162 | endmenu | ||
| 163 | |||
| 164 | endif | ||
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile new file mode 100644 index 000000000000..8cd2719684db --- /dev/null +++ b/arch/blackfin/mach-bf538/Makefile | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | # | ||
| 2 | # arch/blackfin/mach-bf538/Makefile | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y := ints-priority.o dma.o | ||
diff --git a/arch/blackfin/mach-bf538/boards/Kconfig b/arch/blackfin/mach-bf538/boards/Kconfig new file mode 100644 index 000000000000..215249ba58bb --- /dev/null +++ b/arch/blackfin/mach-bf538/boards/Kconfig | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | choice | ||
| 2 | prompt "System type" | ||
| 3 | default BFIN538_EZKIT | ||
| 4 | help | ||
| 5 | Select your board! | ||
| 6 | |||
| 7 | config BFIN538_EZKIT | ||
| 8 | bool "BF538-EZKIT" | ||
| 9 | help | ||
| 10 | BF538-EZKIT-LITE board support. | ||
| 11 | |||
| 12 | endchoice | ||
diff --git a/arch/blackfin/mach-bf538/boards/Makefile b/arch/blackfin/mach-bf538/boards/Makefile new file mode 100644 index 000000000000..6143b320d585 --- /dev/null +++ b/arch/blackfin/mach-bf538/boards/Makefile | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | # | ||
| 2 | # arch/blackfin/mach-bf538/boards/Makefile | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-$(CONFIG_BFIN538_EZKIT) += ezkit.o | ||
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c new file mode 100644 index 000000000000..e37cb9378884 --- /dev/null +++ b/arch/blackfin/mach-bf538/boards/ezkit.c | |||
| @@ -0,0 +1,606 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf538/boards/ezkit.c | ||
| 3 | * Based on: arch/blackfin/mach-bf537/boards/ezkit.c | ||
| 4 | * Author: Aidan Williams <aidan@nicta.com.au> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2005 National ICT Australia (NICTA) | ||
| 11 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/device.h> | ||
| 32 | #include <linux/platform_device.h> | ||
| 33 | #include <linux/mtd/mtd.h> | ||
| 34 | #include <linux/mtd/partitions.h> | ||
| 35 | #include <linux/spi/spi.h> | ||
| 36 | #include <linux/spi/flash.h> | ||
| 37 | #include <linux/irq.h> | ||
| 38 | #include <linux/interrupt.h> | ||
| 39 | #include <asm/bfin5xx_spi.h> | ||
| 40 | #include <asm/dma.h> | ||
| 41 | #include <asm/gpio.h> | ||
| 42 | #include <asm/nand.h> | ||
| 43 | #include <asm/portmux.h> | ||
| 44 | #include <asm/dpmc.h> | ||
| 45 | #include <linux/input.h> | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Name the Board for the /proc/cpuinfo | ||
| 49 | */ | ||
| 50 | const char bfin_board_name[] = "ADI BF538-EZKIT"; | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Driver needs to know address, irq and flag pin. | ||
| 54 | */ | ||
| 55 | |||
| 56 | |||
| 57 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
| 58 | static struct platform_device rtc_device = { | ||
| 59 | .name = "rtc-bfin", | ||
| 60 | .id = -1, | ||
| 61 | }; | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | ||
| 65 | static struct resource bfin_uart_resources[] = { | ||
| 66 | #ifdef CONFIG_SERIAL_BFIN_UART0 | ||
| 67 | { | ||
| 68 | .start = 0xFFC00400, | ||
| 69 | .end = 0xFFC004FF, | ||
| 70 | .flags = IORESOURCE_MEM, | ||
| 71 | }, | ||
| 72 | #endif | ||
| 73 | #ifdef CONFIG_SERIAL_BFIN_UART1 | ||
| 74 | { | ||
| 75 | .start = 0xFFC02000, | ||
| 76 | .end = 0xFFC020FF, | ||
| 77 | .flags = IORESOURCE_MEM, | ||
| 78 | }, | ||
| 79 | #endif | ||
| 80 | #ifdef CONFIG_SERIAL_BFIN_UART2 | ||
| 81 | { | ||
| 82 | .start = 0xFFC02100, | ||
| 83 | .end = 0xFFC021FF, | ||
| 84 | .flags = IORESOURCE_MEM, | ||
| 85 | }, | ||
| 86 | #endif | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct platform_device bfin_uart_device = { | ||
| 90 | .name = "bfin-uart", | ||
| 91 | .id = 1, | ||
| 92 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | ||
| 93 | .resource = bfin_uart_resources, | ||
| 94 | }; | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 98 | #ifdef CONFIG_BFIN_SIR0 | ||
| 99 | static struct resource bfin_sir0_resources[] = { | ||
| 100 | { | ||
| 101 | .start = 0xFFC00400, | ||
| 102 | .end = 0xFFC004FF, | ||
| 103 | .flags = IORESOURCE_MEM, | ||
| 104 | }, | ||
| 105 | { | ||
| 106 | .start = IRQ_UART0_RX, | ||
| 107 | .end = IRQ_UART0_RX+1, | ||
| 108 | .flags = IORESOURCE_IRQ, | ||
| 109 | }, | ||
| 110 | { | ||
| 111 | .start = CH_UART0_RX, | ||
| 112 | .end = CH_UART0_RX+1, | ||
| 113 | .flags = IORESOURCE_DMA, | ||
| 114 | }, | ||
| 115 | }; | ||
| 116 | static struct platform_device bfin_sir0_device = { | ||
| 117 | .name = "bfin_sir", | ||
| 118 | .id = 0, | ||
| 119 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 120 | .resource = bfin_sir0_resources, | ||
| 121 | }; | ||
| 122 | #endif | ||
| 123 | #ifdef CONFIG_BFIN_SIR1 | ||
| 124 | static struct resource bfin_sir1_resources[] = { | ||
| 125 | { | ||
| 126 | .start = 0xFFC02000, | ||
| 127 | .end = 0xFFC020FF, | ||
| 128 | .flags = IORESOURCE_MEM, | ||
| 129 | }, | ||
| 130 | { | ||
| 131 | .start = IRQ_UART1_RX, | ||
| 132 | .end = IRQ_UART1_RX+1, | ||
| 133 | .flags = IORESOURCE_IRQ, | ||
| 134 | }, | ||
| 135 | { | ||
| 136 | .start = CH_UART1_RX, | ||
| 137 | .end = CH_UART1_RX+1, | ||
| 138 | .flags = IORESOURCE_DMA, | ||
| 139 | }, | ||
| 140 | }; | ||
| 141 | static struct platform_device bfin_sir1_device = { | ||
| 142 | .name = "bfin_sir", | ||
| 143 | .id = 1, | ||
| 144 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | ||
| 145 | .resource = bfin_sir1_resources, | ||
| 146 | }; | ||
| 147 | #endif | ||
| 148 | #ifdef CONFIG_BFIN_SIR2 | ||
| 149 | static struct resource bfin_sir2_resources[] = { | ||
| 150 | { | ||
| 151 | .start = 0xFFC02100, | ||
| 152 | .end = 0xFFC021FF, | ||
| 153 | .flags = IORESOURCE_MEM, | ||
| 154 | }, | ||
| 155 | { | ||
| 156 | .start = IRQ_UART2_RX, | ||
| 157 | .end = IRQ_UART2_RX+1, | ||
| 158 | .flags = IORESOURCE_IRQ, | ||
| 159 | }, | ||
| 160 | { | ||
| 161 | .start = CH_UART2_RX, | ||
| 162 | .end = CH_UART2_RX+1, | ||
| 163 | .flags = IORESOURCE_DMA, | ||
| 164 | }, | ||
| 165 | }; | ||
| 166 | static struct platform_device bfin_sir2_device = { | ||
| 167 | .name = "bfin_sir", | ||
| 168 | .id = 2, | ||
| 169 | .num_resources = ARRAY_SIZE(bfin_sir2_resources), | ||
| 170 | .resource = bfin_sir2_resources, | ||
| 171 | }; | ||
| 172 | #endif | ||
| 173 | #endif | ||
| 174 | |||
| 175 | /* | ||
| 176 | * USB-LAN EzExtender board | ||
| 177 | * Driver needs to know address, irq and flag pin. | ||
| 178 | */ | ||
| 179 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
| 180 | static struct resource smc91x_resources[] = { | ||
| 181 | { | ||
| 182 | .name = "smc91x-regs", | ||
| 183 | .start = 0x20310300, | ||
| 184 | .end = 0x20310300 + 16, | ||
| 185 | .flags = IORESOURCE_MEM, | ||
| 186 | }, { | ||
| 187 | .start = IRQ_PF0, | ||
| 188 | .end = IRQ_PF0, | ||
| 189 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 190 | }, | ||
| 191 | }; | ||
| 192 | static struct platform_device smc91x_device = { | ||
| 193 | .name = "smc91x", | ||
| 194 | .id = 0, | ||
| 195 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 196 | .resource = smc91x_resources, | ||
| 197 | }; | ||
| 198 | #endif | ||
| 199 | |||
| 200 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 201 | /* all SPI peripherals info goes here */ | ||
| 202 | #if defined(CONFIG_MTD_M25P80) \ | ||
| 203 | || defined(CONFIG_MTD_M25P80_MODULE) | ||
| 204 | /* SPI flash chip (m25p16) */ | ||
| 205 | static struct mtd_partition bfin_spi_flash_partitions[] = { | ||
| 206 | { | ||
| 207 | .name = "bootloader(spi)", | ||
| 208 | .size = 0x00040000, | ||
| 209 | .offset = 0, | ||
| 210 | .mask_flags = MTD_CAP_ROM | ||
| 211 | }, { | ||
| 212 | .name = "linux kernel(spi)", | ||
| 213 | .size = 0x1c0000, | ||
| 214 | .offset = 0x40000 | ||
| 215 | } | ||
| 216 | }; | ||
| 217 | |||
| 218 | static struct flash_platform_data bfin_spi_flash_data = { | ||
| 219 | .name = "m25p80", | ||
| 220 | .parts = bfin_spi_flash_partitions, | ||
| 221 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | ||
| 222 | .type = "m25p16", | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | ||
| 226 | .enable_dma = 0, /* use dma transfer with this chip*/ | ||
| 227 | .bits_per_word = 8, | ||
| 228 | .cs_change_per_word = 0, | ||
| 229 | }; | ||
| 230 | #endif | ||
| 231 | |||
| 232 | #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) | ||
| 233 | #include <linux/spi/ad7879.h> | ||
| 234 | static const struct ad7879_platform_data bfin_ad7879_ts_info = { | ||
| 235 | .model = 7879, /* Model = AD7879 */ | ||
| 236 | .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ | ||
| 237 | .pressure_max = 10000, | ||
| 238 | .pressure_min = 0, | ||
| 239 | .first_conversion_delay = 3, /* wait 512us before do a first conversion */ | ||
| 240 | .acquisition_time = 1, /* 4us acquisition time per sample */ | ||
| 241 | .median = 2, /* do 8 measurements */ | ||
| 242 | .averaging = 1, /* take the average of 4 middle samples */ | ||
| 243 | .pen_down_acc_interval = 255, /* 9.4 ms */ | ||
| 244 | .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */ | ||
| 245 | .gpio_default = 1, /* During initialization set GPIO = HIGH */ | ||
| 246 | }; | ||
| 247 | #endif | ||
| 248 | |||
| 249 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) | ||
| 250 | static struct bfin5xx_spi_chip spi_ad7879_chip_info = { | ||
| 251 | .enable_dma = 0, | ||
| 252 | .bits_per_word = 16, | ||
| 253 | }; | ||
| 254 | #endif | ||
| 255 | |||
| 256 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) | ||
| 257 | #include <asm/bfin-lq035q1.h> | ||
| 258 | |||
| 259 | static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { | ||
| 260 | .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, | ||
| 261 | .use_bl = 0, /* let something else control the LCD Blacklight */ | ||
| 262 | .gpio_bl = GPIO_PF7, | ||
| 263 | }; | ||
| 264 | |||
| 265 | static struct resource bfin_lq035q1_resources[] = { | ||
| 266 | { | ||
| 267 | .start = IRQ_PPI_ERROR, | ||
| 268 | .end = IRQ_PPI_ERROR, | ||
| 269 | .flags = IORESOURCE_IRQ, | ||
| 270 | }, | ||
| 271 | }; | ||
| 272 | |||
| 273 | static struct platform_device bfin_lq035q1_device = { | ||
| 274 | .name = "bfin-lq035q1", | ||
| 275 | .id = -1, | ||
| 276 | .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), | ||
| 277 | .resource = bfin_lq035q1_resources, | ||
| 278 | .dev = { | ||
| 279 | .platform_data = &bfin_lq035q1_data, | ||
| 280 | }, | ||
| 281 | }; | ||
| 282 | #endif | ||
| 283 | |||
| 284 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | ||
| 285 | static struct bfin5xx_spi_chip spidev_chip_info = { | ||
| 286 | .enable_dma = 0, | ||
| 287 | .bits_per_word = 8, | ||
| 288 | }; | ||
| 289 | #endif | ||
| 290 | |||
| 291 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) | ||
| 292 | static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { | ||
| 293 | .enable_dma = 0, | ||
| 294 | .bits_per_word = 8, | ||
| 295 | }; | ||
| 296 | #endif | ||
| 297 | |||
| 298 | static struct spi_board_info bf538_spi_board_info[] __initdata = { | ||
| 299 | #if defined(CONFIG_MTD_M25P80) \ | ||
| 300 | || defined(CONFIG_MTD_M25P80_MODULE) | ||
| 301 | { | ||
| 302 | /* the modalias must be the same as spi device driver name */ | ||
| 303 | .modalias = "m25p80", /* Name of spi_driver for this device */ | ||
| 304 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 305 | .bus_num = 0, /* Framework bus number */ | ||
| 306 | .chip_select = 1, /* SPI_SSEL1*/ | ||
| 307 | .platform_data = &bfin_spi_flash_data, | ||
| 308 | .controller_data = &spi_flash_chip_info, | ||
| 309 | .mode = SPI_MODE_3, | ||
| 310 | }, | ||
| 311 | #endif | ||
| 312 | #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) | ||
| 313 | { | ||
| 314 | .modalias = "ad7879", | ||
| 315 | .platform_data = &bfin_ad7879_ts_info, | ||
| 316 | .irq = IRQ_PF3, | ||
| 317 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ | ||
| 318 | .bus_num = 0, | ||
| 319 | .chip_select = 1, | ||
| 320 | .controller_data = &spi_ad7879_chip_info, | ||
| 321 | .mode = SPI_CPHA | SPI_CPOL, | ||
| 322 | }, | ||
| 323 | #endif | ||
| 324 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) | ||
| 325 | { | ||
| 326 | .modalias = "bfin-lq035q1-spi", | ||
| 327 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 328 | .bus_num = 0, | ||
| 329 | .chip_select = 2, | ||
| 330 | .controller_data = &lq035q1_spi_chip_info, | ||
| 331 | .mode = SPI_CPHA | SPI_CPOL, | ||
| 332 | }, | ||
| 333 | #endif | ||
| 334 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | ||
| 335 | { | ||
| 336 | .modalias = "spidev", | ||
| 337 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | ||
| 338 | .bus_num = 0, | ||
| 339 | .chip_select = 1, | ||
| 340 | .controller_data = &spidev_chip_info, | ||
| 341 | }, | ||
| 342 | #endif | ||
| 343 | }; | ||
| 344 | |||
| 345 | /* SPI (0) */ | ||
| 346 | static struct resource bfin_spi0_resource[] = { | ||
| 347 | [0] = { | ||
| 348 | .start = SPI0_REGBASE, | ||
| 349 | .end = SPI0_REGBASE + 0xFF, | ||
| 350 | .flags = IORESOURCE_MEM, | ||
| 351 | }, | ||
| 352 | [1] = { | ||
| 353 | .start = CH_SPI0, | ||
| 354 | .end = CH_SPI0, | ||
| 355 | .flags = IORESOURCE_IRQ, | ||
| 356 | } | ||
| 357 | }; | ||
| 358 | |||
| 359 | /* SPI (1) */ | ||
| 360 | static struct resource bfin_spi1_resource[] = { | ||
| 361 | [0] = { | ||
| 362 | .start = SPI1_REGBASE, | ||
| 363 | .end = SPI1_REGBASE + 0xFF, | ||
| 364 | .flags = IORESOURCE_MEM, | ||
| 365 | }, | ||
| 366 | [1] = { | ||
| 367 | .start = CH_SPI1, | ||
| 368 | .end = CH_SPI1, | ||
| 369 | .flags = IORESOURCE_IRQ, | ||
| 370 | } | ||
| 371 | }; | ||
| 372 | |||
| 373 | /* SPI (2) */ | ||
| 374 | static struct resource bfin_spi2_resource[] = { | ||
| 375 | [0] = { | ||
| 376 | .start = SPI2_REGBASE, | ||
| 377 | .end = SPI2_REGBASE + 0xFF, | ||
| 378 | .flags = IORESOURCE_MEM, | ||
| 379 | }, | ||
| 380 | [1] = { | ||
| 381 | .start = CH_SPI2, | ||
| 382 | .end = CH_SPI2, | ||
| 383 | .flags = IORESOURCE_IRQ, | ||
| 384 | } | ||
| 385 | }; | ||
| 386 | |||
| 387 | /* SPI controller data */ | ||
| 388 | static struct bfin5xx_spi_master bf538_spi_master_info0 = { | ||
| 389 | .num_chipselect = 8, | ||
| 390 | .enable_dma = 1, /* master has the ability to do dma transfer */ | ||
| 391 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | ||
| 392 | }; | ||
| 393 | |||
| 394 | static struct platform_device bf538_spi_master0 = { | ||
| 395 | .name = "bfin-spi", | ||
| 396 | .id = 0, /* Bus number */ | ||
| 397 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | ||
| 398 | .resource = bfin_spi0_resource, | ||
| 399 | .dev = { | ||
| 400 | .platform_data = &bf538_spi_master_info0, /* Passed to driver */ | ||
| 401 | }, | ||
| 402 | }; | ||
| 403 | |||
| 404 | static struct bfin5xx_spi_master bf538_spi_master_info1 = { | ||
| 405 | .num_chipselect = 8, | ||
| 406 | .enable_dma = 1, /* master has the ability to do dma transfer */ | ||
| 407 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | ||
| 408 | }; | ||
| 409 | |||
| 410 | static struct platform_device bf538_spi_master1 = { | ||
| 411 | .name = "bfin-spi", | ||
| 412 | .id = 1, /* Bus number */ | ||
| 413 | .num_resources = ARRAY_SIZE(bfin_spi1_resource), | ||
| 414 | .resource = bfin_spi1_resource, | ||
| 415 | .dev = { | ||
| 416 | .platform_data = &bf538_spi_master_info1, /* Passed to driver */ | ||
| 417 | }, | ||
| 418 | }; | ||
| 419 | |||
| 420 | static struct bfin5xx_spi_master bf538_spi_master_info2 = { | ||
| 421 | .num_chipselect = 8, | ||
| 422 | .enable_dma = 1, /* master has the ability to do dma transfer */ | ||
| 423 | .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0}, | ||
| 424 | }; | ||
| 425 | |||
| 426 | static struct platform_device bf538_spi_master2 = { | ||
| 427 | .name = "bfin-spi", | ||
| 428 | .id = 2, /* Bus number */ | ||
| 429 | .num_resources = ARRAY_SIZE(bfin_spi2_resource), | ||
| 430 | .resource = bfin_spi2_resource, | ||
| 431 | .dev = { | ||
| 432 | .platform_data = &bf538_spi_master_info2, /* Passed to driver */ | ||
| 433 | }, | ||
| 434 | }; | ||
| 435 | |||
| 436 | #endif /* spi master and devices */ | ||
| 437 | |||
| 438 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | ||
| 439 | static struct resource bfin_twi0_resource[] = { | ||
| 440 | [0] = { | ||
| 441 | .start = TWI0_REGBASE, | ||
| 442 | .end = TWI0_REGBASE + 0xFF, | ||
| 443 | .flags = IORESOURCE_MEM, | ||
| 444 | }, | ||
| 445 | [1] = { | ||
| 446 | .start = IRQ_TWI0, | ||
| 447 | .end = IRQ_TWI0, | ||
| 448 | .flags = IORESOURCE_IRQ, | ||
| 449 | }, | ||
| 450 | }; | ||
| 451 | |||
| 452 | static struct platform_device i2c_bfin_twi0_device = { | ||
| 453 | .name = "i2c-bfin-twi", | ||
| 454 | .id = 0, | ||
| 455 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | ||
| 456 | .resource = bfin_twi0_resource, | ||
| 457 | }; | ||
| 458 | |||
| 459 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ | ||
| 460 | static struct resource bfin_twi1_resource[] = { | ||
| 461 | [0] = { | ||
| 462 | .start = TWI1_REGBASE, | ||
| 463 | .end = TWI1_REGBASE + 0xFF, | ||
| 464 | .flags = IORESOURCE_MEM, | ||
| 465 | }, | ||
| 466 | [1] = { | ||
| 467 | .start = IRQ_TWI1, | ||
| 468 | .end = IRQ_TWI1, | ||
| 469 | .flags = IORESOURCE_IRQ, | ||
| 470 | }, | ||
| 471 | }; | ||
| 472 | |||
| 473 | static struct platform_device i2c_bfin_twi1_device = { | ||
| 474 | .name = "i2c-bfin-twi", | ||
| 475 | .id = 1, | ||
| 476 | .num_resources = ARRAY_SIZE(bfin_twi1_resource), | ||
| 477 | .resource = bfin_twi1_resource, | ||
| 478 | }; | ||
| 479 | #endif | ||
| 480 | #endif | ||
| 481 | |||
| 482 | static struct resource bfin_gpios_resources = { | ||
| 483 | .start = 0, | ||
| 484 | .end = MAX_BLACKFIN_GPIOS - 1, | ||
| 485 | .flags = IORESOURCE_IRQ, | ||
| 486 | }; | ||
| 487 | |||
| 488 | static struct platform_device bfin_gpios_device = { | ||
| 489 | .name = "simple-gpio", | ||
| 490 | .id = -1, | ||
| 491 | .num_resources = 1, | ||
| 492 | .resource = &bfin_gpios_resources, | ||
| 493 | }; | ||
| 494 | |||
| 495 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 496 | #include <linux/gpio_keys.h> | ||
| 497 | |||
| 498 | static struct gpio_keys_button bfin_gpio_keys_table[] = { | ||
| 499 | {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"}, | ||
| 500 | }; | ||
| 501 | |||
| 502 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { | ||
| 503 | .buttons = bfin_gpio_keys_table, | ||
| 504 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), | ||
| 505 | }; | ||
| 506 | |||
| 507 | static struct platform_device bfin_device_gpiokeys = { | ||
| 508 | .name = "gpio-keys", | ||
| 509 | .dev = { | ||
| 510 | .platform_data = &bfin_gpio_keys_data, | ||
| 511 | }, | ||
| 512 | }; | ||
| 513 | #endif | ||
| 514 | |||
| 515 | static const unsigned int cclk_vlev_datasheet[] = | ||
| 516 | { | ||
| 517 | /* | ||
| 518 | * Internal VLEV BF538SBBC1533 | ||
| 519 | ****temporarily using these values until data sheet is updated | ||
| 520 | */ | ||
| 521 | VRPAIR(VLEV_100, 150000000), | ||
| 522 | VRPAIR(VLEV_100, 250000000), | ||
| 523 | VRPAIR(VLEV_110, 276000000), | ||
| 524 | VRPAIR(VLEV_115, 301000000), | ||
| 525 | VRPAIR(VLEV_120, 525000000), | ||
| 526 | VRPAIR(VLEV_125, 550000000), | ||
| 527 | VRPAIR(VLEV_130, 600000000), | ||
| 528 | }; | ||
| 529 | |||
| 530 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | ||
| 531 | .tuple_tab = cclk_vlev_datasheet, | ||
| 532 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | ||
| 533 | .vr_settling_time = 25 /* us */, | ||
| 534 | }; | ||
| 535 | |||
| 536 | static struct platform_device bfin_dpmc = { | ||
| 537 | .name = "bfin dpmc", | ||
| 538 | .dev = { | ||
| 539 | .platform_data = &bfin_dmpc_vreg_data, | ||
| 540 | }, | ||
| 541 | }; | ||
| 542 | |||
| 543 | static struct platform_device *cm_bf538_devices[] __initdata = { | ||
| 544 | |||
| 545 | &bfin_dpmc, | ||
| 546 | |||
| 547 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
| 548 | &rtc_device, | ||
| 549 | #endif | ||
| 550 | |||
| 551 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | ||
| 552 | &bfin_uart_device, | ||
| 553 | #endif | ||
| 554 | |||
| 555 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 556 | &bf538_spi_master0, | ||
| 557 | &bf538_spi_master1, | ||
| 558 | &bf538_spi_master2, | ||
| 559 | #endif | ||
| 560 | |||
| 561 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | ||
| 562 | &i2c_bfin_twi0_device, | ||
| 563 | &i2c_bfin_twi1_device, | ||
| 564 | #endif | ||
| 565 | |||
| 566 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 567 | #ifdef CONFIG_BFIN_SIR0 | ||
| 568 | &bfin_sir0_device, | ||
| 569 | #endif | ||
| 570 | #ifdef CONFIG_BFIN_SIR1 | ||
| 571 | &bfin_sir1_device, | ||
| 572 | #endif | ||
| 573 | #ifdef CONFIG_BFIN_SIR2 | ||
| 574 | &bfin_sir2_device, | ||
| 575 | #endif | ||
| 576 | #endif | ||
| 577 | |||
| 578 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
| 579 | &smc91x_device, | ||
| 580 | #endif | ||
| 581 | |||
| 582 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) | ||
| 583 | &bfin_lq035q1_device, | ||
| 584 | #endif | ||
| 585 | |||
| 586 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 587 | &bfin_device_gpiokeys, | ||
| 588 | #endif | ||
| 589 | |||
| 590 | &bfin_gpios_device, | ||
| 591 | }; | ||
| 592 | |||
| 593 | static int __init ezkit_init(void) | ||
| 594 | { | ||
| 595 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 596 | platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices)); | ||
| 597 | |||
| 598 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 599 | spi_register_board_info(bf538_spi_board_info, | ||
| 600 | ARRAY_SIZE(bf538_spi_board_info)); | ||
| 601 | #endif | ||
| 602 | |||
| 603 | return 0; | ||
| 604 | } | ||
| 605 | |||
| 606 | arch_initcall(ezkit_init); | ||
diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c new file mode 100644 index 000000000000..d6837fbf94ea --- /dev/null +++ b/arch/blackfin/mach-bf538/dma.c | |||
| @@ -0,0 +1,161 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf538/dma.c | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: This file contains the simple DMA Implementation for Blackfin | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2008 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | #include <linux/module.h> | ||
| 30 | |||
| 31 | #include <asm/blackfin.h> | ||
| 32 | #include <asm/dma.h> | ||
| 33 | |||
| 34 | struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { | ||
| 35 | (struct dma_register *) DMA0_NEXT_DESC_PTR, | ||
| 36 | (struct dma_register *) DMA1_NEXT_DESC_PTR, | ||
| 37 | (struct dma_register *) DMA2_NEXT_DESC_PTR, | ||
| 38 | (struct dma_register *) DMA3_NEXT_DESC_PTR, | ||
| 39 | (struct dma_register *) DMA4_NEXT_DESC_PTR, | ||
| 40 | (struct dma_register *) DMA5_NEXT_DESC_PTR, | ||
| 41 | (struct dma_register *) DMA6_NEXT_DESC_PTR, | ||
| 42 | (struct dma_register *) DMA7_NEXT_DESC_PTR, | ||
| 43 | (struct dma_register *) DMA8_NEXT_DESC_PTR, | ||
| 44 | (struct dma_register *) DMA9_NEXT_DESC_PTR, | ||
| 45 | (struct dma_register *) DMA10_NEXT_DESC_PTR, | ||
| 46 | (struct dma_register *) DMA11_NEXT_DESC_PTR, | ||
| 47 | (struct dma_register *) DMA12_NEXT_DESC_PTR, | ||
| 48 | (struct dma_register *) DMA13_NEXT_DESC_PTR, | ||
| 49 | (struct dma_register *) DMA14_NEXT_DESC_PTR, | ||
| 50 | (struct dma_register *) DMA15_NEXT_DESC_PTR, | ||
| 51 | (struct dma_register *) DMA16_NEXT_DESC_PTR, | ||
| 52 | (struct dma_register *) DMA17_NEXT_DESC_PTR, | ||
| 53 | (struct dma_register *) DMA18_NEXT_DESC_PTR, | ||
| 54 | (struct dma_register *) DMA19_NEXT_DESC_PTR, | ||
| 55 | (struct dma_register *) MDMA0_D0_NEXT_DESC_PTR, | ||
| 56 | (struct dma_register *) MDMA0_S0_NEXT_DESC_PTR, | ||
| 57 | (struct dma_register *) MDMA0_D1_NEXT_DESC_PTR, | ||
| 58 | (struct dma_register *) MDMA0_S1_NEXT_DESC_PTR, | ||
| 59 | (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, | ||
| 60 | (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, | ||
| 61 | (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, | ||
| 62 | (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, | ||
| 63 | }; | ||
| 64 | EXPORT_SYMBOL(dma_io_base_addr); | ||
| 65 | |||
| 66 | int channel2irq(unsigned int channel) | ||
| 67 | { | ||
| 68 | int ret_irq = -1; | ||
| 69 | |||
| 70 | switch (channel) { | ||
| 71 | case CH_PPI: | ||
| 72 | ret_irq = IRQ_PPI; | ||
| 73 | break; | ||
| 74 | |||
| 75 | case CH_UART0_RX: | ||
| 76 | ret_irq = IRQ_UART0_RX; | ||
| 77 | break; | ||
| 78 | |||
| 79 | case CH_UART0_TX: | ||
| 80 | ret_irq = IRQ_UART0_TX; | ||
| 81 | break; | ||
| 82 | |||
| 83 | case CH_UART1_RX: | ||
| 84 | ret_irq = IRQ_UART1_RX; | ||
| 85 | break; | ||
| 86 | |||
| 87 | case CH_UART1_TX: | ||
| 88 | ret_irq = IRQ_UART1_TX; | ||
| 89 | break; | ||
| 90 | |||
| 91 | case CH_UART2_RX: | ||
| 92 | ret_irq = IRQ_UART2_RX; | ||
| 93 | break; | ||
| 94 | |||
| 95 | case CH_UART2_TX: | ||
| 96 | ret_irq = IRQ_UART2_TX; | ||
| 97 | break; | ||
| 98 | |||
| 99 | case CH_SPORT0_RX: | ||
| 100 | ret_irq = IRQ_SPORT0_RX; | ||
| 101 | break; | ||
| 102 | |||
| 103 | case CH_SPORT0_TX: | ||
| 104 | ret_irq = IRQ_SPORT0_TX; | ||
| 105 | break; | ||
| 106 | |||
| 107 | case CH_SPORT1_RX: | ||
| 108 | ret_irq = IRQ_SPORT1_RX; | ||
| 109 | break; | ||
| 110 | |||
| 111 | case CH_SPORT1_TX: | ||
| 112 | ret_irq = IRQ_SPORT1_TX; | ||
| 113 | break; | ||
| 114 | |||
| 115 | case CH_SPORT2_RX: | ||
| 116 | ret_irq = IRQ_SPORT2_RX; | ||
| 117 | break; | ||
| 118 | |||
| 119 | case CH_SPORT2_TX: | ||
| 120 | ret_irq = IRQ_SPORT2_TX; | ||
| 121 | break; | ||
| 122 | |||
| 123 | case CH_SPORT3_RX: | ||
| 124 | ret_irq = IRQ_SPORT3_RX; | ||
| 125 | break; | ||
| 126 | |||
| 127 | case CH_SPORT3_TX: | ||
| 128 | ret_irq = IRQ_SPORT3_TX; | ||
| 129 | break; | ||
| 130 | |||
| 131 | case CH_SPI0: | ||
| 132 | ret_irq = IRQ_SPI0; | ||
| 133 | break; | ||
| 134 | |||
| 135 | case CH_SPI1: | ||
| 136 | ret_irq = IRQ_SPI1; | ||
| 137 | break; | ||
| 138 | |||
| 139 | case CH_SPI2: | ||
| 140 | ret_irq = IRQ_SPI2; | ||
| 141 | break; | ||
| 142 | |||
| 143 | case CH_MEM_STREAM0_SRC: | ||
| 144 | case CH_MEM_STREAM0_DEST: | ||
| 145 | ret_irq = IRQ_MEM0_DMA0; | ||
| 146 | break; | ||
| 147 | case CH_MEM_STREAM1_SRC: | ||
| 148 | case CH_MEM_STREAM1_DEST: | ||
| 149 | ret_irq = IRQ_MEM0_DMA1; | ||
| 150 | break; | ||
| 151 | case CH_MEM_STREAM2_SRC: | ||
| 152 | case CH_MEM_STREAM2_DEST: | ||
| 153 | ret_irq = IRQ_MEM1_DMA0; | ||
| 154 | break; | ||
| 155 | case CH_MEM_STREAM3_SRC: | ||
| 156 | case CH_MEM_STREAM3_DEST: | ||
| 157 | ret_irq = IRQ_MEM1_DMA1; | ||
| 158 | break; | ||
| 159 | } | ||
| 160 | return ret_irq; | ||
| 161 | } | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h new file mode 100644 index 000000000000..e130b4f8a05d --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf538/anomaly.h | ||
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 4 | * | ||
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* This file shoule be up to date with: | ||
| 10 | * - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List | ||
| 11 | * - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _MACH_ANOMALY_H_ | ||
| 15 | #define _MACH_ANOMALY_H_ | ||
| 16 | |||
| 17 | #if __SILICON_REVISION__ < 4 | ||
| 18 | # error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3 | ||
| 19 | #endif | ||
| 20 | |||
| 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | ||
| 22 | #define ANOMALY_05000074 (1) | ||
| 23 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | ||
| 24 | #define ANOMALY_05000119 (1) | ||
| 25 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | ||
| 26 | #define ANOMALY_05000122 (1) | ||
| 27 | /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ | ||
| 28 | #define ANOMALY_05000166 (1) | ||
| 29 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | ||
| 30 | #define ANOMALY_05000179 (1) | ||
| 31 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ | ||
| 32 | #define ANOMALY_05000180 (1) | ||
| 33 | /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ | ||
| 34 | #define ANOMALY_05000193 (1) | ||
| 35 | /* Current DMA Address Shows Wrong Value During Carry Fix */ | ||
| 36 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) | ||
| 37 | /* NMI Event at Boot Time Results in Unpredictable State */ | ||
| 38 | #define ANOMALY_05000219 (1) | ||
| 39 | /* SPI Slave Boot Mode Modifies Registers from Reset Value */ | ||
| 40 | #define ANOMALY_05000229 (1) | ||
| 41 | /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ | ||
| 42 | #define ANOMALY_05000233 (1) | ||
| 43 | /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ | ||
| 44 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) | ||
| 45 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | ||
| 46 | #define ANOMALY_05000245 (1) | ||
| 47 | /* Maximum External Clock Speed for Timers */ | ||
| 48 | #define ANOMALY_05000253 (1) | ||
| 49 | /* DCPLB_FAULT_ADDR MMR register may be corrupted */ | ||
| 50 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) | ||
| 51 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | ||
| 52 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) | ||
| 53 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | ||
| 54 | #define ANOMALY_05000272 (1) | ||
| 55 | /* Writes to Synchronous SDRAM Memory May Be Lost */ | ||
| 56 | #define ANOMALY_05000273 (__SILICON_REVISION__ < 4) | ||
| 57 | /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ | ||
| 58 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) | ||
| 59 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | ||
| 60 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) | ||
| 61 | /* False Hardware Error Exception when ISR Context Is Not Restored */ | ||
| 62 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) | ||
| 63 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ | ||
| 64 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) | ||
| 65 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ | ||
| 66 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) | ||
| 67 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ | ||
| 68 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) | ||
| 69 | /* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */ | ||
| 70 | #define ANOMALY_05000291 (__SILICON_REVISION__ < 4) | ||
| 71 | /* Hibernate Leakage Current Is Higher Than Specified */ | ||
| 72 | #define ANOMALY_05000293 (__SILICON_REVISION__ < 4) | ||
| 73 | /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ | ||
| 74 | #define ANOMALY_05000294 (1) | ||
| 75 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ | ||
| 76 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 4) | ||
| 77 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ | ||
| 78 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 4) | ||
| 79 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ | ||
| 80 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) | ||
| 81 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | ||
| 82 | #define ANOMALY_05000310 (1) | ||
| 83 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | ||
| 84 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) | ||
| 85 | /* PPI Is Level-Sensitive on First Transfer */ | ||
| 86 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) | ||
| 87 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ | ||
| 88 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) | ||
| 89 | /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ | ||
| 90 | #define ANOMALY_05000318 (__SILICON_REVISION__ < 4) | ||
| 91 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | ||
| 92 | #define ANOMALY_05000355 (__SILICON_REVISION__ < 5) | ||
| 93 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | ||
| 94 | #define ANOMALY_05000357 (__SILICON_REVISION__ < 5) | ||
| 95 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | ||
| 96 | #define ANOMALY_05000366 (1) | ||
| 97 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | ||
| 98 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 5) | ||
| 99 | /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ | ||
| 100 | #define ANOMALY_05000374 (__SILICON_REVISION__ == 4) | ||
| 101 | /* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */ | ||
| 102 | #define ANOMALY_05000375 (__SILICON_REVISION__ < 4) | ||
| 103 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | ||
| 104 | #define ANOMALY_05000402 (__SILICON_REVISION__ < 4) | ||
| 105 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | ||
| 106 | #define ANOMALY_05000403 (1) | ||
| 107 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | ||
| 108 | #define ANOMALY_05000416 (1) | ||
| 109 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ | ||
| 110 | #define ANOMALY_05000425 (1) | ||
| 111 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | ||
| 112 | #define ANOMALY_05000426 (1) | ||
| 113 | /* Specific GPIO Pins May Change State when Entering Hibernate */ | ||
| 114 | #define ANOMALY_05000436 (__SILICON_REVISION__ > 3) | ||
| 115 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | ||
| 116 | #define ANOMALY_05000443 (1) | ||
| 117 | |||
| 118 | /* Anomalies that don't exist on this proc */ | ||
| 119 | #define ANOMALY_05000158 (0) | ||
| 120 | #define ANOMALY_05000198 (0) | ||
| 121 | #define ANOMALY_05000230 (0) | ||
| 122 | #define ANOMALY_05000263 (0) | ||
| 123 | #define ANOMALY_05000311 (0) | ||
| 124 | #define ANOMALY_05000323 (0) | ||
| 125 | #define ANOMALY_05000353 (1) | ||
| 126 | #define ANOMALY_05000363 (0) | ||
| 127 | #define ANOMALY_05000386 (1) | ||
| 128 | #define ANOMALY_05000412 (0) | ||
| 129 | #define ANOMALY_05000432 (0) | ||
| 130 | #define ANOMALY_05000435 (0) | ||
| 131 | |||
| 132 | #endif | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/bf538.h b/arch/blackfin/mach-bf538/include/mach/bf538.h new file mode 100644 index 000000000000..9c8abb307908 --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/bf538.h | |||
| @@ -0,0 +1,124 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf538/bf538.h | ||
| 3 | * Based on: include/asm-blackfin/mach-bf537/bf537.h | ||
| 4 | * Author: Michael Hennerich (michael.hennerich@analog.com) | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527 | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2007 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #ifndef __MACH_BF538_H__ | ||
| 31 | #define __MACH_BF538_H__ | ||
| 32 | |||
| 33 | #define OFFSET_(x) ((x) & 0x0000FFFF) | ||
| 34 | |||
| 35 | /*some misc defines*/ | ||
| 36 | #define IMASK_IVG15 0x8000 | ||
| 37 | #define IMASK_IVG14 0x4000 | ||
| 38 | #define IMASK_IVG13 0x2000 | ||
| 39 | #define IMASK_IVG12 0x1000 | ||
| 40 | |||
| 41 | #define IMASK_IVG11 0x0800 | ||
| 42 | #define IMASK_IVG10 0x0400 | ||
| 43 | #define IMASK_IVG9 0x0200 | ||
| 44 | #define IMASK_IVG8 0x0100 | ||
| 45 | |||
| 46 | #define IMASK_IVG7 0x0080 | ||
| 47 | #define IMASK_IVGTMR 0x0040 | ||
| 48 | #define IMASK_IVGHW 0x0020 | ||
| 49 | |||
| 50 | /***************************/ | ||
| 51 | |||
| 52 | #define BFIN_DSUBBANKS 4 | ||
| 53 | #define BFIN_DWAYS 2 | ||
| 54 | #define BFIN_DLINES 64 | ||
| 55 | #define BFIN_ISUBBANKS 4 | ||
| 56 | #define BFIN_IWAYS 4 | ||
| 57 | #define BFIN_ILINES 32 | ||
| 58 | |||
| 59 | #define WAY0_L 0x1 | ||
| 60 | #define WAY1_L 0x2 | ||
| 61 | #define WAY01_L 0x3 | ||
| 62 | #define WAY2_L 0x4 | ||
| 63 | #define WAY02_L 0x5 | ||
| 64 | #define WAY12_L 0x6 | ||
| 65 | #define WAY012_L 0x7 | ||
| 66 | |||
| 67 | #define WAY3_L 0x8 | ||
| 68 | #define WAY03_L 0x9 | ||
| 69 | #define WAY13_L 0xA | ||
| 70 | #define WAY013_L 0xB | ||
| 71 | |||
| 72 | #define WAY32_L 0xC | ||
| 73 | #define WAY320_L 0xD | ||
| 74 | #define WAY321_L 0xE | ||
| 75 | #define WAYALL_L 0xF | ||
| 76 | |||
| 77 | #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ | ||
| 78 | |||
| 79 | /********************************* EBIU Settings ************************************/ | ||
| 80 | #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) | ||
| 81 | #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) | ||
| 82 | |||
| 83 | #ifdef CONFIG_C_AMBEN_ALL | ||
| 84 | #define V_AMBEN AMBEN_ALL | ||
| 85 | #endif | ||
| 86 | #ifdef CONFIG_C_AMBEN | ||
| 87 | #define V_AMBEN 0x0 | ||
| 88 | #endif | ||
| 89 | #ifdef CONFIG_C_AMBEN_B0 | ||
| 90 | #define V_AMBEN AMBEN_B0 | ||
| 91 | #endif | ||
| 92 | #ifdef CONFIG_C_AMBEN_B0_B1 | ||
| 93 | #define V_AMBEN AMBEN_B0_B1 | ||
| 94 | #endif | ||
| 95 | #ifdef CONFIG_C_AMBEN_B0_B1_B2 | ||
| 96 | #define V_AMBEN AMBEN_B0_B1_B2 | ||
| 97 | #endif | ||
| 98 | #ifdef CONFIG_C_AMCKEN | ||
| 99 | #define V_AMCKEN AMCKEN | ||
| 100 | #else | ||
| 101 | #define V_AMCKEN 0x0 | ||
| 102 | #endif | ||
| 103 | #ifdef CONFIG_C_CDPRIO | ||
| 104 | #define V_CDPRIO 0x100 | ||
| 105 | #else | ||
| 106 | #define V_CDPRIO 0x0 | ||
| 107 | #endif | ||
| 108 | |||
| 109 | #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) | ||
| 110 | |||
| 111 | #ifdef CONFIG_BF538 | ||
| 112 | #define CPU "BF538" | ||
| 113 | #define CPUID 0x27C4 | ||
| 114 | #endif | ||
| 115 | #ifdef CONFIG_BF539 | ||
| 116 | #define CPU "BF539" | ||
| 117 | #define CPUID 0x27C4 /* FXIME:? */ | ||
| 118 | #endif | ||
| 119 | |||
| 120 | #ifndef CPU | ||
| 121 | #error "Unknown CPU type - This kernel doesn't seem to be configured properly" | ||
| 122 | #endif | ||
| 123 | |||
| 124 | #endif /* __MACH_BF538_H__ */ | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h new file mode 100644 index 000000000000..40503b6b89a3 --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h | |||
| @@ -0,0 +1,183 @@ | |||
| 1 | /* | ||
| 2 | * file: include/asm-blackfin/mach-bf538/bfin_serial_5xx.h | ||
| 3 | * based on: | ||
| 4 | * author: | ||
| 5 | * | ||
| 6 | * created: | ||
| 7 | * description: | ||
| 8 | * blackfin serial driver header files | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * this program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the gnu general public license as published by | ||
| 18 | * the free software foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * this program is distributed in the hope that it will be useful, | ||
| 22 | * but without any warranty; without even the implied warranty of | ||
| 23 | * merchantability or fitness for a particular purpose. see the | ||
| 24 | * gnu general public license for more details. | ||
| 25 | * | ||
| 26 | * you should have received a copy of the gnu general public license | ||
| 27 | * along with this program; see the file copying. | ||
| 28 | * if not, write to the free software foundation, | ||
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #include <linux/serial.h> | ||
| 33 | #include <asm/dma.h> | ||
| 34 | #include <asm/portmux.h> | ||
| 35 | |||
| 36 | #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) | ||
| 37 | #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) | ||
| 38 | #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) | ||
| 39 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) | ||
| 40 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) | ||
| 41 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) | ||
| 42 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) | ||
| 43 | |||
| 44 | #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) | ||
| 45 | #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) | ||
| 46 | #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) | ||
| 47 | #define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) | ||
| 48 | #define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) | ||
| 49 | #define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) | ||
| 50 | #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) | ||
| 51 | #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) | ||
| 52 | |||
| 53 | #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) | ||
| 54 | #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) | ||
| 55 | |||
| 56 | #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) | ||
| 57 | #define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) | ||
| 58 | #define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) | ||
| 59 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) | ||
| 60 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) | ||
| 61 | |||
| 62 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) | ||
| 63 | # define CONFIG_SERIAL_BFIN_CTSRTS | ||
| 64 | |||
| 65 | # ifndef CONFIG_UART0_CTS_PIN | ||
| 66 | # define CONFIG_UART0_CTS_PIN -1 | ||
| 67 | # endif | ||
| 68 | |||
| 69 | # ifndef CONFIG_UART0_RTS_PIN | ||
| 70 | # define CONFIG_UART0_RTS_PIN -1 | ||
| 71 | # endif | ||
| 72 | |||
| 73 | # ifndef CONFIG_UART1_CTS_PIN | ||
| 74 | # define CONFIG_UART1_CTS_PIN -1 | ||
| 75 | # endif | ||
| 76 | |||
| 77 | # ifndef CONFIG_UART1_RTS_PIN | ||
| 78 | # define CONFIG_UART1_RTS_PIN -1 | ||
| 79 | # endif | ||
| 80 | #endif | ||
| 81 | |||
| 82 | #define BFIN_UART_TX_FIFO_SIZE 2 | ||
| 83 | |||
| 84 | /* | ||
| 85 | * The pin configuration is different from schematic | ||
| 86 | */ | ||
| 87 | struct bfin_serial_port { | ||
| 88 | struct uart_port port; | ||
| 89 | unsigned int old_status; | ||
| 90 | unsigned int lsr; | ||
| 91 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 92 | int tx_done; | ||
| 93 | int tx_count; | ||
| 94 | struct circ_buf rx_dma_buf; | ||
| 95 | struct timer_list rx_dma_timer; | ||
| 96 | int rx_dma_nrows; | ||
| 97 | unsigned int tx_dma_channel; | ||
| 98 | unsigned int rx_dma_channel; | ||
| 99 | struct work_struct tx_dma_workqueue; | ||
| 100 | #endif | ||
| 101 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 102 | struct timer_list cts_timer; | ||
| 103 | int cts_pin; | ||
| 104 | int rts_pin; | ||
| 105 | #endif | ||
| 106 | }; | ||
| 107 | |||
| 108 | /* The hardware clears the LSR bits upon read, so we need to cache | ||
| 109 | * some of the more fun bits in software so they don't get lost | ||
| 110 | * when checking the LSR in other code paths (TX). | ||
| 111 | */ | ||
| 112 | static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) | ||
| 113 | { | ||
| 114 | unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); | ||
| 115 | uart->lsr |= (lsr & (BI|FE|PE|OE)); | ||
| 116 | return lsr | uart->lsr; | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) | ||
| 120 | { | ||
| 121 | uart->lsr = 0; | ||
| 122 | bfin_write16(uart->port.membase + OFFSET_LSR, -1); | ||
| 123 | } | ||
| 124 | |||
| 125 | struct bfin_serial_res { | ||
| 126 | unsigned long uart_base_addr; | ||
| 127 | int uart_irq; | ||
| 128 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 129 | unsigned int uart_tx_dma_channel; | ||
| 130 | unsigned int uart_rx_dma_channel; | ||
| 131 | #endif | ||
| 132 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 133 | int uart_cts_pin; | ||
| 134 | int uart_rts_pin; | ||
| 135 | #endif | ||
| 136 | }; | ||
| 137 | |||
| 138 | struct bfin_serial_res bfin_serial_resource[] = { | ||
| 139 | #ifdef CONFIG_SERIAL_BFIN_UART0 | ||
| 140 | { | ||
| 141 | 0xFFC00400, | ||
| 142 | IRQ_UART0_RX, | ||
| 143 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 144 | CH_UART0_TX, | ||
| 145 | CH_UART0_RX, | ||
| 146 | #endif | ||
| 147 | #ifdef CONFIG_BFIN_UART0_CTSRTS | ||
| 148 | CONFIG_UART0_CTS_PIN, | ||
| 149 | CONFIG_UART0_RTS_PIN, | ||
| 150 | #endif | ||
| 151 | }, | ||
| 152 | #endif | ||
| 153 | #ifdef CONFIG_SERIAL_BFIN_UART1 | ||
| 154 | { | ||
| 155 | 0xFFC02000, | ||
| 156 | IRQ_UART1_RX, | ||
| 157 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 158 | CH_UART1_TX, | ||
| 159 | CH_UART1_RX, | ||
| 160 | #endif | ||
| 161 | #ifdef CONFIG_BFIN_UART1_CTSRTS | ||
| 162 | CONFIG_UART1_CTS_PIN, | ||
| 163 | CONFIG_UART1_RTS_PIN, | ||
| 164 | #endif | ||
| 165 | }, | ||
| 166 | #endif | ||
| 167 | #ifdef CONFIG_SERIAL_BFIN_UART2 | ||
| 168 | { | ||
| 169 | 0xFFC02100, | ||
| 170 | IRQ_UART2_RX, | ||
| 171 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
| 172 | CH_UART2_TX, | ||
| 173 | CH_UART2_RX, | ||
| 174 | #endif | ||
| 175 | #ifdef CONFIG_BFIN_UART2_CTSRTS | ||
| 176 | CONFIG_UART2_CTS_PIN, | ||
| 177 | CONFIG_UART2_RTS_PIN, | ||
| 178 | #endif | ||
| 179 | }, | ||
| 180 | #endif | ||
| 181 | }; | ||
| 182 | |||
| 183 | #define DRIVER_NAME "bfin-uart" | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h new file mode 100644 index 000000000000..ea25371a922b --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h | |||
| @@ -0,0 +1,101 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf538/blackfin.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _MACH_BLACKFIN_H_ | ||
| 33 | #define _MACH_BLACKFIN_H_ | ||
| 34 | |||
| 35 | #define BF538_FAMILY | ||
| 36 | |||
| 37 | #include "bf538.h" | ||
| 38 | #include "mem_map.h" | ||
| 39 | #include "defBF539.h" | ||
| 40 | #include "anomaly.h" | ||
| 41 | |||
| 42 | |||
| 43 | #if !defined(__ASSEMBLY__) | ||
| 44 | #include "cdefBF538.h" | ||
| 45 | |||
| 46 | #if defined(CONFIG_BF539) | ||
| 47 | #include "cdefBF539.h" | ||
| 48 | #endif | ||
| 49 | #endif | ||
| 50 | |||
| 51 | /* UART_IIR Register */ | ||
| 52 | #define STATUS(x) ((x << 1) & 0x06) | ||
| 53 | #define STATUS_P1 0x02 | ||
| 54 | #define STATUS_P0 0x01 | ||
| 55 | |||
| 56 | #define BFIN_UART_NR_PORTS 3 | ||
| 57 | |||
| 58 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | ||
| 59 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | ||
| 60 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | ||
| 61 | #define OFFSET_IER 0x04 /* Interrupt Enable Register */ | ||
| 62 | #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | ||
| 63 | #define OFFSET_IIR 0x08 /* Interrupt Identification Register */ | ||
| 64 | #define OFFSET_LCR 0x0C /* Line Control Register */ | ||
| 65 | #define OFFSET_MCR 0x10 /* Modem Control Register */ | ||
| 66 | #define OFFSET_LSR 0x14 /* Line Status Register */ | ||
| 67 | #define OFFSET_MSR 0x18 /* Modem Status Register */ | ||
| 68 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | ||
| 69 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | ||
| 70 | |||
| 71 | |||
| 72 | #define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_D0_IRQ_STATUS | ||
| 73 | #define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_D0_START_ADDR | ||
| 74 | #define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_S0_START_ADDR | ||
| 75 | #define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_D0_X_COUNT | ||
| 76 | #define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_S0_X_COUNT | ||
| 77 | #define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_D0_Y_COUNT | ||
| 78 | #define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_S0_Y_COUNT | ||
| 79 | #define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_D0_X_MODIFY | ||
| 80 | #define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_S0_X_MODIFY | ||
| 81 | #define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_D0_Y_MODIFY | ||
| 82 | #define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_S0_Y_MODIFY | ||
| 83 | #define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_S0_CONFIG | ||
| 84 | #define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_D0_CONFIG | ||
| 85 | #define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_S0_CONFIG | ||
| 86 | #define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_D0_IRQ_STATUS | ||
| 87 | #define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_S0_IRQ_STATUS | ||
| 88 | |||
| 89 | |||
| 90 | /* DPMC*/ | ||
| 91 | #define bfin_read_STOPCK_OFF() bfin_read_STOPCK() | ||
| 92 | #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) | ||
| 93 | #define STOPCK_OFF STOPCK | ||
| 94 | |||
| 95 | /* PLL_DIV Masks */ | ||
| 96 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | ||
| 97 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | ||
| 98 | #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ | ||
| 99 | #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ | ||
| 100 | |||
| 101 | #endif | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h new file mode 100644 index 000000000000..241725bc6988 --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h | |||
| @@ -0,0 +1,2108 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf538/cdefBF538.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _CDEF_BF538_H | ||
| 32 | #define _CDEF_BF538_H | ||
| 33 | |||
| 34 | #include <asm/blackfin.h> | ||
| 35 | |||
| 36 | /*include all Core registers and bit definitions*/ | ||
| 37 | #include "defBF539.h" | ||
| 38 | |||
| 39 | /*include core specific register pointer definitions*/ | ||
| 40 | #include <asm/cdef_LPBlackfin.h> | ||
| 41 | |||
| 42 | #define bfin_writePTR(addr, val) bfin_write32(addr, val) | ||
| 43 | |||
| 44 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | ||
| 45 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | ||
| 46 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | ||
| 47 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | ||
| 48 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | ||
| 49 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | ||
| 50 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | ||
| 51 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) | ||
| 52 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | ||
| 53 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) | ||
| 54 | #define bfin_read_SWRST() bfin_read16(SWRST) | ||
| 55 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) | ||
| 56 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | ||
| 57 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) | ||
| 58 | #define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT) | ||
| 59 | #define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val) | ||
| 60 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) | ||
| 61 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) | ||
| 62 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) | ||
| 63 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) | ||
| 64 | #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0)) | ||
| 65 | #define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val) | ||
| 66 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) | ||
| 67 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) | ||
| 68 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) | ||
| 69 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) | ||
| 70 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0)) | ||
| 71 | #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val) | ||
| 72 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) | ||
| 73 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) | ||
| 74 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) | ||
| 75 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) | ||
| 76 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0)) | ||
| 77 | #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val) | ||
| 78 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | ||
| 79 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) | ||
| 80 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | ||
| 81 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) | ||
| 82 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) | ||
| 83 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) | ||
| 84 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) | ||
| 85 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) | ||
| 86 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) | ||
| 87 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) | ||
| 88 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) | ||
| 89 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) | ||
| 90 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) | ||
| 91 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) | ||
| 92 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) | ||
| 93 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) | ||
| 94 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) | ||
| 95 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) | ||
| 96 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) | ||
| 97 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) | ||
| 98 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) | ||
| 99 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) | ||
| 100 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) | ||
| 101 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) | ||
| 102 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) | ||
| 103 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) | ||
| 104 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) | ||
| 105 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) | ||
| 106 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) | ||
| 107 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) | ||
| 108 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | ||
| 109 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) | ||
| 110 | #define bfin_read_UART0_THR() bfin_read16(UART0_THR) | ||
| 111 | #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) | ||
| 112 | #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) | ||
| 113 | #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) | ||
| 114 | #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) | ||
| 115 | #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) | ||
| 116 | #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) | ||
| 117 | #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) | ||
| 118 | #define bfin_read_UART0_IER() bfin_read16(UART0_IER) | ||
| 119 | #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) | ||
| 120 | #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) | ||
| 121 | #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) | ||
| 122 | #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) | ||
| 123 | #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) | ||
| 124 | #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) | ||
| 125 | #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) | ||
| 126 | #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) | ||
| 127 | #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) | ||
| 128 | #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) | ||
| 129 | #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) | ||
| 130 | #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) | ||
| 131 | #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) | ||
| 132 | #define bfin_read_UART1_THR() bfin_read16(UART1_THR) | ||
| 133 | #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) | ||
| 134 | #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) | ||
| 135 | #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) | ||
| 136 | #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) | ||
| 137 | #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) | ||
| 138 | #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) | ||
| 139 | #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) | ||
| 140 | #define bfin_read_UART1_IER() bfin_read16(UART1_IER) | ||
| 141 | #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) | ||
| 142 | #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) | ||
| 143 | #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) | ||
| 144 | #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) | ||
| 145 | #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) | ||
| 146 | #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) | ||
| 147 | #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) | ||
| 148 | #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) | ||
| 149 | #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) | ||
| 150 | #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) | ||
| 151 | #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) | ||
| 152 | #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) | ||
| 153 | #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) | ||
| 154 | #define bfin_read_UART2_THR() bfin_read16(UART2_THR) | ||
| 155 | #define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) | ||
| 156 | #define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) | ||
| 157 | #define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) | ||
| 158 | #define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) | ||
| 159 | #define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) | ||
| 160 | #define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) | ||
| 161 | #define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) | ||
| 162 | #define bfin_read_UART2_IER() bfin_read16(UART2_IER) | ||
| 163 | #define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val) | ||
| 164 | #define bfin_read_UART2_IIR() bfin_read16(UART2_IIR) | ||
| 165 | #define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val) | ||
| 166 | #define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) | ||
| 167 | #define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) | ||
| 168 | #define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) | ||
| 169 | #define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) | ||
| 170 | #define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) | ||
| 171 | #define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) | ||
| 172 | #define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) | ||
| 173 | #define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) | ||
| 174 | #define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) | ||
| 175 | #define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) | ||
| 176 | #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) | ||
| 177 | #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) | ||
| 178 | #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) | ||
| 179 | #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) | ||
| 180 | #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) | ||
| 181 | #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) | ||
| 182 | #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) | ||
| 183 | #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) | ||
| 184 | #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) | ||
| 185 | #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) | ||
| 186 | #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) | ||
| 187 | #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) | ||
| 188 | #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) | ||
| 189 | #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) | ||
| 190 | #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) | ||
| 191 | #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) | ||
| 192 | #define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) | ||
| 193 | #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) | ||
| 194 | #define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) | ||
| 195 | #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) | ||
| 196 | #define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) | ||
| 197 | #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) | ||
| 198 | #define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) | ||
| 199 | #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) | ||
| 200 | #define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) | ||
| 201 | #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) | ||
| 202 | #define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) | ||
| 203 | #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) | ||
| 204 | #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) | ||
| 205 | #define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) | ||
| 206 | #define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) | ||
| 207 | #define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) | ||
| 208 | #define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) | ||
| 209 | #define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) | ||
| 210 | #define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) | ||
| 211 | #define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) | ||
| 212 | #define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) | ||
| 213 | #define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) | ||
| 214 | #define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) | ||
| 215 | #define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) | ||
| 216 | #define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) | ||
| 217 | #define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) | ||
| 218 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | ||
| 219 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) | ||
| 220 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | ||
| 221 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) | ||
| 222 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | ||
| 223 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) | ||
| 224 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | ||
| 225 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) | ||
| 226 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | ||
| 227 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) | ||
| 228 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | ||
| 229 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) | ||
| 230 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | ||
| 231 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) | ||
| 232 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | ||
| 233 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) | ||
| 234 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | ||
| 235 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) | ||
| 236 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | ||
| 237 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) | ||
| 238 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | ||
| 239 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) | ||
| 240 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | ||
| 241 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) | ||
| 242 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) | ||
| 243 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) | ||
| 244 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) | ||
| 245 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) | ||
| 246 | #define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) | ||
| 247 | #define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val) | ||
| 248 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | ||
| 249 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) | ||
| 250 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | ||
| 251 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) | ||
| 252 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | ||
| 253 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) | ||
| 254 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | ||
| 255 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) | ||
| 256 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | ||
| 257 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) | ||
| 258 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | ||
| 259 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) | ||
| 260 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | ||
| 261 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) | ||
| 262 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | ||
| 263 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) | ||
| 264 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | ||
| 265 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) | ||
| 266 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | ||
| 267 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) | ||
| 268 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | ||
| 269 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) | ||
| 270 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | ||
| 271 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) | ||
| 272 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | ||
| 273 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) | ||
| 274 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | ||
| 275 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) | ||
| 276 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | ||
| 277 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) | ||
| 278 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | ||
| 279 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) | ||
| 280 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | ||
| 281 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) | ||
| 282 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | ||
| 283 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) | ||
| 284 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | ||
| 285 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) | ||
| 286 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | ||
| 287 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) | ||
| 288 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | ||
| 289 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) | ||
| 290 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | ||
| 291 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) | ||
| 292 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | ||
| 293 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) | ||
| 294 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | ||
| 295 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) | ||
| 296 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | ||
| 297 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) | ||
| 298 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | ||
| 299 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) | ||
| 300 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | ||
| 301 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) | ||
| 302 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | ||
| 303 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) | ||
| 304 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | ||
| 305 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) | ||
| 306 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | ||
| 307 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) | ||
| 308 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | ||
| 309 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) | ||
| 310 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | ||
| 311 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) | ||
| 312 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | ||
| 313 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) | ||
| 314 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | ||
| 315 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) | ||
| 316 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | ||
| 317 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) | ||
| 318 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | ||
| 319 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) | ||
| 320 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | ||
| 321 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) | ||
| 322 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | ||
| 323 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) | ||
| 324 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | ||
| 325 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) | ||
| 326 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | ||
| 327 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) | ||
| 328 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | ||
| 329 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) | ||
| 330 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | ||
| 331 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) | ||
| 332 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | ||
| 333 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) | ||
| 334 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | ||
| 335 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) | ||
| 336 | #define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) | ||
| 337 | #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) | ||
| 338 | #define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) | ||
| 339 | #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) | ||
| 340 | #define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) | ||
| 341 | #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) | ||
| 342 | #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) | ||
| 343 | #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) | ||
| 344 | #define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) | ||
| 345 | #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) | ||
| 346 | #define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) | ||
| 347 | #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) | ||
| 348 | #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) | ||
| 349 | #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) | ||
| 350 | #define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) | ||
| 351 | #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) | ||
| 352 | #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) | ||
| 353 | #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) | ||
| 354 | #define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) | ||
| 355 | #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) | ||
| 356 | #define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) | ||
| 357 | #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) | ||
| 358 | #define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) | ||
| 359 | #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) | ||
| 360 | #define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) | ||
| 361 | #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) | ||
| 362 | #define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) | ||
| 363 | #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) | ||
| 364 | #define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) | ||
| 365 | #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) | ||
| 366 | #define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) | ||
| 367 | #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) | ||
| 368 | #define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) | ||
| 369 | #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) | ||
| 370 | #define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) | ||
| 371 | #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) | ||
| 372 | #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) | ||
| 373 | #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) | ||
| 374 | #define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) | ||
| 375 | #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) | ||
| 376 | #define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) | ||
| 377 | #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) | ||
| 378 | #define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) | ||
| 379 | #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) | ||
| 380 | #define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) | ||
| 381 | #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) | ||
| 382 | #define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) | ||
| 383 | #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) | ||
| 384 | #define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) | ||
| 385 | #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) | ||
| 386 | #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) | ||
| 387 | #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) | ||
| 388 | #define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) | ||
| 389 | #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) | ||
| 390 | #define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) | ||
| 391 | #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) | ||
| 392 | #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) | ||
| 393 | #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) | ||
| 394 | #define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) | ||
| 395 | #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) | ||
| 396 | #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) | ||
| 397 | #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) | ||
| 398 | #define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) | ||
| 399 | #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) | ||
| 400 | #define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) | ||
| 401 | #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) | ||
| 402 | #define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) | ||
| 403 | #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) | ||
| 404 | #define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) | ||
| 405 | #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) | ||
| 406 | #define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) | ||
| 407 | #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) | ||
| 408 | #define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) | ||
| 409 | #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) | ||
| 410 | #define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) | ||
| 411 | #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) | ||
| 412 | #define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) | ||
| 413 | #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) | ||
| 414 | #define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) | ||
| 415 | #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) | ||
| 416 | #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) | ||
| 417 | #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) | ||
| 418 | #define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) | ||
| 419 | #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) | ||
| 420 | #define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) | ||
| 421 | #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) | ||
| 422 | #define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) | ||
| 423 | #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) | ||
| 424 | #define bfin_read_PORTFIO() bfin_read16(PORTFIO) | ||
| 425 | #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) | ||
| 426 | #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) | ||
| 427 | #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) | ||
| 428 | #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) | ||
| 429 | #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) | ||
| 430 | #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) | ||
| 431 | #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) | ||
| 432 | #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) | ||
| 433 | #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) | ||
| 434 | #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) | ||
| 435 | #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) | ||
| 436 | #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) | ||
| 437 | #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) | ||
| 438 | #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) | ||
| 439 | #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) | ||
| 440 | #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) | ||
| 441 | #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) | ||
| 442 | #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) | ||
| 443 | #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) | ||
| 444 | #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) | ||
| 445 | #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) | ||
| 446 | #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) | ||
| 447 | #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) | ||
| 448 | #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) | ||
| 449 | #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) | ||
| 450 | #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) | ||
| 451 | #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) | ||
| 452 | #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) | ||
| 453 | #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) | ||
| 454 | #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) | ||
| 455 | #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) | ||
| 456 | #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) | ||
| 457 | #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) | ||
| 458 | #define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER) | ||
| 459 | #define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val) | ||
| 460 | #define bfin_read_PORTCIO() bfin_read16(PORTCIO) | ||
| 461 | #define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val) | ||
| 462 | #define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR) | ||
| 463 | #define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val) | ||
| 464 | #define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET) | ||
| 465 | #define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val) | ||
| 466 | #define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE) | ||
| 467 | #define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val) | ||
| 468 | #define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR) | ||
| 469 | #define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val) | ||
| 470 | #define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN) | ||
| 471 | #define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val) | ||
| 472 | #define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER) | ||
| 473 | #define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val) | ||
| 474 | #define bfin_read_PORTDIO() bfin_read16(PORTDIO) | ||
| 475 | #define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val) | ||
| 476 | #define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR) | ||
| 477 | #define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val) | ||
| 478 | #define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET) | ||
| 479 | #define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val) | ||
| 480 | #define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE) | ||
| 481 | #define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val) | ||
| 482 | #define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR) | ||
| 483 | #define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val) | ||
| 484 | #define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN) | ||
| 485 | #define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val) | ||
| 486 | #define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER) | ||
| 487 | #define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val) | ||
| 488 | #define bfin_read_PORTEIO() bfin_read16(PORTEIO) | ||
| 489 | #define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val) | ||
| 490 | #define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR) | ||
| 491 | #define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val) | ||
| 492 | #define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET) | ||
| 493 | #define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val) | ||
| 494 | #define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE) | ||
| 495 | #define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val) | ||
| 496 | #define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR) | ||
| 497 | #define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val) | ||
| 498 | #define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN) | ||
| 499 | #define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val) | ||
| 500 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | ||
| 501 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) | ||
| 502 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | ||
| 503 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) | ||
| 504 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | ||
| 505 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) | ||
| 506 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) | ||
| 507 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) | ||
| 508 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) | ||
| 509 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) | ||
| 510 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) | ||
| 511 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) | ||
| 512 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) | ||
| 513 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) | ||
| 514 | #define bfin_read_DMA0_TC_PER() bfin_read16(DMA0_TC_PER) | ||
| 515 | #define bfin_write_DMA0_TC_PER(val) bfin_write16(DMA0_TC_PER, val) | ||
| 516 | #define bfin_read_DMA0_TC_CNT() bfin_read16(DMA0_TC_CNT) | ||
| 517 | #define bfin_write_DMA0_TC_CNT(val) bfin_write16(DMA0_TC_CNT, val) | ||
| 518 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) | ||
| 519 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) | ||
| 520 | #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) | ||
| 521 | #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) | ||
| 522 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | ||
| 523 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) | ||
| 524 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | ||
| 525 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) | ||
| 526 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | ||
| 527 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) | ||
| 528 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) | ||
| 529 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) | ||
| 530 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | ||
| 531 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) | ||
| 532 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) | ||
| 533 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) | ||
| 534 | #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) | ||
| 535 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) | ||
| 536 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) | ||
| 537 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) | ||
| 538 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | ||
| 539 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) | ||
| 540 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) | ||
| 541 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) | ||
| 542 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) | ||
| 543 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) | ||
| 544 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) | ||
| 545 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) | ||
| 546 | #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) | ||
| 547 | #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) | ||
| 548 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) | ||
| 549 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) | ||
| 550 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | ||
| 551 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) | ||
| 552 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | ||
| 553 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) | ||
| 554 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) | ||
| 555 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) | ||
| 556 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | ||
| 557 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) | ||
| 558 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) | ||
| 559 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) | ||
| 560 | #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) | ||
| 561 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) | ||
| 562 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) | ||
| 563 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) | ||
| 564 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | ||
| 565 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) | ||
| 566 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) | ||
| 567 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) | ||
| 568 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) | ||
| 569 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) | ||
| 570 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) | ||
| 571 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) | ||
| 572 | #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) | ||
| 573 | #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) | ||
| 574 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) | ||
| 575 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) | ||
| 576 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | ||
| 577 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) | ||
| 578 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | ||
| 579 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) | ||
| 580 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) | ||
| 581 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) | ||
| 582 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | ||
| 583 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) | ||
| 584 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) | ||
| 585 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) | ||
| 586 | #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) | ||
| 587 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) | ||
| 588 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) | ||
| 589 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) | ||
| 590 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | ||
| 591 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) | ||
| 592 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) | ||
| 593 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) | ||
| 594 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) | ||
| 595 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) | ||
| 596 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) | ||
| 597 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) | ||
| 598 | #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) | ||
| 599 | #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) | ||
| 600 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) | ||
| 601 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) | ||
| 602 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | ||
| 603 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) | ||
| 604 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | ||
| 605 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) | ||
| 606 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) | ||
| 607 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) | ||
| 608 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | ||
| 609 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) | ||
| 610 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) | ||
| 611 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) | ||
| 612 | #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) | ||
| 613 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) | ||
| 614 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) | ||
| 615 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) | ||
| 616 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | ||
| 617 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) | ||
| 618 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) | ||
| 619 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) | ||
| 620 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) | ||
| 621 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) | ||
| 622 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) | ||
| 623 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) | ||
| 624 | #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) | ||
| 625 | #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) | ||
| 626 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) | ||
| 627 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) | ||
| 628 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | ||
| 629 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) | ||
| 630 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | ||
| 631 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) | ||
| 632 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) | ||
| 633 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) | ||
| 634 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | ||
| 635 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) | ||
| 636 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) | ||
| 637 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) | ||
| 638 | #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) | ||
| 639 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) | ||
| 640 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) | ||
| 641 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) | ||
| 642 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | ||
| 643 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) | ||
| 644 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) | ||
| 645 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) | ||
| 646 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) | ||
| 647 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) | ||
| 648 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) | ||
| 649 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) | ||
| 650 | #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) | ||
| 651 | #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) | ||
| 652 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) | ||
| 653 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) | ||
| 654 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | ||
| 655 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) | ||
| 656 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | ||
| 657 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) | ||
| 658 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) | ||
| 659 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) | ||
| 660 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | ||
| 661 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) | ||
| 662 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) | ||
| 663 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) | ||
| 664 | #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) | ||
| 665 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) | ||
| 666 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) | ||
| 667 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) | ||
| 668 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | ||
| 669 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) | ||
| 670 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) | ||
| 671 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) | ||
| 672 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) | ||
| 673 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) | ||
| 674 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) | ||
| 675 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) | ||
| 676 | #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) | ||
| 677 | #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) | ||
| 678 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) | ||
| 679 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) | ||
| 680 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | ||
| 681 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) | ||
| 682 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | ||
| 683 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) | ||
| 684 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) | ||
| 685 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) | ||
| 686 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | ||
| 687 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) | ||
| 688 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) | ||
| 689 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) | ||
| 690 | #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) | ||
| 691 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) | ||
| 692 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) | ||
| 693 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) | ||
| 694 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | ||
| 695 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) | ||
| 696 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) | ||
| 697 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) | ||
| 698 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) | ||
| 699 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) | ||
| 700 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) | ||
| 701 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) | ||
| 702 | #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) | ||
| 703 | #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) | ||
| 704 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) | ||
| 705 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) | ||
| 706 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | ||
| 707 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) | ||
| 708 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | ||
| 709 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) | ||
| 710 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) | ||
| 711 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) | ||
| 712 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | ||
| 713 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) | ||
| 714 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) | ||
| 715 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) | ||
| 716 | #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) | ||
| 717 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) | ||
| 718 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) | ||
| 719 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) | ||
| 720 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | ||
| 721 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) | ||
| 722 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) | ||
| 723 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) | ||
| 724 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) | ||
| 725 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) | ||
| 726 | #define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) | ||
| 727 | #define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val) | ||
| 728 | #define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) | ||
| 729 | #define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val) | ||
| 730 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) | ||
| 731 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) | ||
| 732 | #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) | ||
| 733 | #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) | ||
| 734 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) | ||
| 735 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) | ||
| 736 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) | ||
| 737 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) | ||
| 738 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) | ||
| 739 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) | ||
| 740 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) | ||
| 741 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) | ||
| 742 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) | ||
| 743 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) | ||
| 744 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) | ||
| 745 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) | ||
| 746 | #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) | ||
| 747 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) | ||
| 748 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) | ||
| 749 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) | ||
| 750 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) | ||
| 751 | #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) | ||
| 752 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) | ||
| 753 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) | ||
| 754 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) | ||
| 755 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) | ||
| 756 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) | ||
| 757 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) | ||
| 758 | #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) | ||
| 759 | #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) | ||
| 760 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) | ||
| 761 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) | ||
| 762 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) | ||
| 763 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) | ||
| 764 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) | ||
| 765 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) | ||
| 766 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) | ||
| 767 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) | ||
| 768 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) | ||
| 769 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) | ||
| 770 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) | ||
| 771 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) | ||
| 772 | #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) | ||
| 773 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) | ||
| 774 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) | ||
| 775 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) | ||
| 776 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) | ||
| 777 | #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) | ||
| 778 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) | ||
| 779 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) | ||
| 780 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) | ||
| 781 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) | ||
| 782 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) | ||
| 783 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) | ||
| 784 | #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) | ||
| 785 | #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) | ||
| 786 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) | ||
| 787 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) | ||
| 788 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) | ||
| 789 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) | ||
| 790 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) | ||
| 791 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) | ||
| 792 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) | ||
| 793 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) | ||
| 794 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) | ||
| 795 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) | ||
| 796 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) | ||
| 797 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) | ||
| 798 | #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) | ||
| 799 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) | ||
| 800 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) | ||
| 801 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) | ||
| 802 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) | ||
| 803 | #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) | ||
| 804 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) | ||
| 805 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) | ||
| 806 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) | ||
| 807 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) | ||
| 808 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) | ||
| 809 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) | ||
| 810 | #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) | ||
| 811 | #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) | ||
| 812 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) | ||
| 813 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) | ||
| 814 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) | ||
| 815 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) | ||
| 816 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) | ||
| 817 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) | ||
| 818 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) | ||
| 819 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) | ||
| 820 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) | ||
| 821 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) | ||
| 822 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) | ||
| 823 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) | ||
| 824 | #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) | ||
| 825 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) | ||
| 826 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) | ||
| 827 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) | ||
| 828 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) | ||
| 829 | #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) | ||
| 830 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) | ||
| 831 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) | ||
| 832 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) | ||
| 833 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) | ||
| 834 | #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) | ||
| 835 | #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) | ||
| 836 | #define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) | ||
| 837 | #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) | ||
| 838 | #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) | ||
| 839 | #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) | ||
| 840 | #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) | ||
| 841 | #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) | ||
| 842 | #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) | ||
| 843 | #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) | ||
| 844 | #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) | ||
| 845 | #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) | ||
| 846 | #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) | ||
| 847 | #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) | ||
| 848 | #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) | ||
| 849 | #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) | ||
| 850 | #define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) | ||
| 851 | #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) | ||
| 852 | #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) | ||
| 853 | #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) | ||
| 854 | #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) | ||
| 855 | #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) | ||
| 856 | #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) | ||
| 857 | #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) | ||
| 858 | #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) | ||
| 859 | #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) | ||
| 860 | #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) | ||
| 861 | #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) | ||
| 862 | #define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) | ||
| 863 | #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) | ||
| 864 | #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) | ||
| 865 | #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) | ||
| 866 | #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) | ||
| 867 | #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) | ||
| 868 | #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) | ||
| 869 | #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) | ||
| 870 | #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) | ||
| 871 | #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) | ||
| 872 | #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) | ||
| 873 | #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) | ||
| 874 | #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) | ||
| 875 | #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) | ||
| 876 | #define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) | ||
| 877 | #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) | ||
| 878 | #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) | ||
| 879 | #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) | ||
| 880 | #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) | ||
| 881 | #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) | ||
| 882 | #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) | ||
| 883 | #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) | ||
| 884 | #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) | ||
| 885 | #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) | ||
| 886 | #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) | ||
| 887 | #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) | ||
| 888 | #define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) | ||
| 889 | #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) | ||
| 890 | #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) | ||
| 891 | #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) | ||
| 892 | #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) | ||
| 893 | #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) | ||
| 894 | #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) | ||
| 895 | #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) | ||
| 896 | #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) | ||
| 897 | #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) | ||
| 898 | #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) | ||
| 899 | #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) | ||
| 900 | #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) | ||
| 901 | #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) | ||
| 902 | #define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) | ||
| 903 | #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) | ||
| 904 | #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) | ||
| 905 | #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) | ||
| 906 | #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) | ||
| 907 | #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) | ||
| 908 | #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) | ||
| 909 | #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) | ||
| 910 | #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) | ||
| 911 | #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) | ||
| 912 | #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) | ||
| 913 | #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) | ||
| 914 | #define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) | ||
| 915 | #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) | ||
| 916 | #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) | ||
| 917 | #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) | ||
| 918 | #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) | ||
| 919 | #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) | ||
| 920 | #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) | ||
| 921 | #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) | ||
| 922 | #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) | ||
| 923 | #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) | ||
| 924 | #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) | ||
| 925 | #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) | ||
| 926 | #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) | ||
| 927 | #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) | ||
| 928 | #define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) | ||
| 929 | #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) | ||
| 930 | #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) | ||
| 931 | #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) | ||
| 932 | #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) | ||
| 933 | #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) | ||
| 934 | #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) | ||
| 935 | #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) | ||
| 936 | #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) | ||
| 937 | #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) | ||
| 938 | #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) | ||
| 939 | #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) | ||
| 940 | #define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) | ||
| 941 | #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) | ||
| 942 | #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) | ||
| 943 | #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) | ||
| 944 | #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) | ||
| 945 | #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) | ||
| 946 | #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) | ||
| 947 | #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) | ||
| 948 | #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) | ||
| 949 | #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) | ||
| 950 | #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) | ||
| 951 | #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) | ||
| 952 | #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) | ||
| 953 | #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) | ||
| 954 | #define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) | ||
| 955 | #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) | ||
| 956 | #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) | ||
| 957 | #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) | ||
| 958 | #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) | ||
| 959 | #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) | ||
| 960 | #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) | ||
| 961 | #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) | ||
| 962 | #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) | ||
| 963 | #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) | ||
| 964 | #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) | ||
| 965 | #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) | ||
| 966 | #define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) | ||
| 967 | #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) | ||
| 968 | #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) | ||
| 969 | #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) | ||
| 970 | #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) | ||
| 971 | #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) | ||
| 972 | #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) | ||
| 973 | #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) | ||
| 974 | #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) | ||
| 975 | #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) | ||
| 976 | #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) | ||
| 977 | #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) | ||
| 978 | #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) | ||
| 979 | #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) | ||
| 980 | #define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) | ||
| 981 | #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) | ||
| 982 | #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) | ||
| 983 | #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) | ||
| 984 | #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) | ||
| 985 | #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) | ||
| 986 | #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) | ||
| 987 | #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) | ||
| 988 | #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) | ||
| 989 | #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) | ||
| 990 | #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) | ||
| 991 | #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) | ||
| 992 | #define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) | ||
| 993 | #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) | ||
| 994 | #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) | ||
| 995 | #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) | ||
| 996 | #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) | ||
| 997 | #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) | ||
| 998 | #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) | ||
| 999 | #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) | ||
| 1000 | #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) | ||
| 1001 | #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) | ||
| 1002 | #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) | ||
| 1003 | #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) | ||
| 1004 | #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) | ||
| 1005 | #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) | ||
| 1006 | #define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) | ||
| 1007 | #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) | ||
| 1008 | #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) | ||
| 1009 | #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) | ||
| 1010 | #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) | ||
| 1011 | #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) | ||
| 1012 | #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) | ||
| 1013 | #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) | ||
| 1014 | #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) | ||
| 1015 | #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) | ||
| 1016 | #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) | ||
| 1017 | #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) | ||
| 1018 | #define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) | ||
| 1019 | #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) | ||
| 1020 | #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) | ||
| 1021 | #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) | ||
| 1022 | #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) | ||
| 1023 | #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) | ||
| 1024 | #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) | ||
| 1025 | #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) | ||
| 1026 | #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) | ||
| 1027 | #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) | ||
| 1028 | #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) | ||
| 1029 | #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) | ||
| 1030 | #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) | ||
| 1031 | #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) | ||
| 1032 | #define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) | ||
| 1033 | #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) | ||
| 1034 | #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) | ||
| 1035 | #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) | ||
| 1036 | #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) | ||
| 1037 | #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) | ||
| 1038 | #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) | ||
| 1039 | #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) | ||
| 1040 | #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) | ||
| 1041 | #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) | ||
| 1042 | #define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR) | ||
| 1043 | #define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val) | ||
| 1044 | #define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR) | ||
| 1045 | #define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val) | ||
| 1046 | #define bfin_read_MDMA0_D0_CONFIG() bfin_read16(MDMA0_D0_CONFIG) | ||
| 1047 | #define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val) | ||
| 1048 | #define bfin_read_MDMA0_D0_X_COUNT() bfin_read16(MDMA0_D0_X_COUNT) | ||
| 1049 | #define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val) | ||
| 1050 | #define bfin_read_MDMA0_D0_X_MODIFY() bfin_read16(MDMA0_D0_X_MODIFY) | ||
| 1051 | #define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val) | ||
| 1052 | #define bfin_read_MDMA0_D0_Y_COUNT() bfin_read16(MDMA0_D0_Y_COUNT) | ||
| 1053 | #define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val) | ||
| 1054 | #define bfin_read_MDMA0_D0_Y_MODIFY() bfin_read16(MDMA0_D0_Y_MODIFY) | ||
| 1055 | #define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val) | ||
| 1056 | #define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR) | ||
| 1057 | #define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val) | ||
| 1058 | #define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR) | ||
| 1059 | #define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val) | ||
| 1060 | #define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS) | ||
| 1061 | #define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val) | ||
| 1062 | #define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP) | ||
| 1063 | #define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val) | ||
| 1064 | #define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT) | ||
| 1065 | #define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val) | ||
| 1066 | #define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT) | ||
| 1067 | #define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val) | ||
| 1068 | #define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR) | ||
| 1069 | #define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val) | ||
| 1070 | #define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR) | ||
| 1071 | #define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val) | ||
| 1072 | #define bfin_read_MDMA0_S0_CONFIG() bfin_read16(MDMA0_S0_CONFIG) | ||
| 1073 | #define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val) | ||
| 1074 | #define bfin_read_MDMA0_S0_X_COUNT() bfin_read16(MDMA0_S0_X_COUNT) | ||
| 1075 | #define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val) | ||
| 1076 | #define bfin_read_MDMA0_S0_X_MODIFY() bfin_read16(MDMA0_S0_X_MODIFY) | ||
| 1077 | #define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val) | ||
| 1078 | #define bfin_read_MDMA0_S0_Y_COUNT() bfin_read16(MDMA0_S0_Y_COUNT) | ||
| 1079 | #define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val) | ||
| 1080 | #define bfin_read_MDMA0_S0_Y_MODIFY() bfin_read16(MDMA0_S0_Y_MODIFY) | ||
| 1081 | #define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val) | ||
| 1082 | #define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR) | ||
| 1083 | #define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val) | ||
| 1084 | #define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR) | ||
| 1085 | #define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val) | ||
| 1086 | #define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS) | ||
| 1087 | #define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val) | ||
| 1088 | #define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP) | ||
| 1089 | #define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val) | ||
| 1090 | #define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT) | ||
| 1091 | #define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val) | ||
| 1092 | #define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT) | ||
| 1093 | #define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val) | ||
| 1094 | #define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR) | ||
| 1095 | #define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val) | ||
| 1096 | #define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR) | ||
| 1097 | #define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val) | ||
| 1098 | #define bfin_read_MDMA0_D1_CONFIG() bfin_read16(MDMA0_D1_CONFIG) | ||
| 1099 | #define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val) | ||
| 1100 | #define bfin_read_MDMA0_D1_X_COUNT() bfin_read16(MDMA0_D1_X_COUNT) | ||
| 1101 | #define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val) | ||
| 1102 | #define bfin_read_MDMA0_D1_X_MODIFY() bfin_read16(MDMA0_D1_X_MODIFY) | ||
| 1103 | #define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val) | ||
| 1104 | #define bfin_read_MDMA0_D1_Y_COUNT() bfin_read16(MDMA0_D1_Y_COUNT) | ||
| 1105 | #define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val) | ||
| 1106 | #define bfin_read_MDMA0_D1_Y_MODIFY() bfin_read16(MDMA0_D1_Y_MODIFY) | ||
| 1107 | #define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val) | ||
| 1108 | #define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR) | ||
| 1109 | #define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val) | ||
| 1110 | #define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR) | ||
| 1111 | #define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val) | ||
| 1112 | #define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS) | ||
| 1113 | #define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val) | ||
| 1114 | #define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP) | ||
| 1115 | #define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val) | ||
| 1116 | #define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT) | ||
| 1117 | #define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val) | ||
| 1118 | #define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT) | ||
| 1119 | #define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val) | ||
| 1120 | #define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR) | ||
| 1121 | #define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val) | ||
| 1122 | #define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR) | ||
| 1123 | #define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val) | ||
| 1124 | #define bfin_read_MDMA0_S1_CONFIG() bfin_read16(MDMA0_S1_CONFIG) | ||
| 1125 | #define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val) | ||
| 1126 | #define bfin_read_MDMA0_S1_X_COUNT() bfin_read16(MDMA0_S1_X_COUNT) | ||
| 1127 | #define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val) | ||
| 1128 | #define bfin_read_MDMA0_S1_X_MODIFY() bfin_read16(MDMA0_S1_X_MODIFY) | ||
| 1129 | #define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val) | ||
| 1130 | #define bfin_read_MDMA0_S1_Y_COUNT() bfin_read16(MDMA0_S1_Y_COUNT) | ||
| 1131 | #define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val) | ||
| 1132 | #define bfin_read_MDMA0_S1_Y_MODIFY() bfin_read16(MDMA0_S1_Y_MODIFY) | ||
| 1133 | #define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val) | ||
| 1134 | #define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR) | ||
| 1135 | #define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val) | ||
| 1136 | #define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR) | ||
| 1137 | #define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val) | ||
| 1138 | #define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS) | ||
| 1139 | #define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val) | ||
| 1140 | #define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP) | ||
| 1141 | #define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val) | ||
| 1142 | #define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT) | ||
| 1143 | #define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val) | ||
| 1144 | #define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT) | ||
| 1145 | #define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val) | ||
| 1146 | #define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR) | ||
| 1147 | #define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val) | ||
| 1148 | #define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR) | ||
| 1149 | #define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val) | ||
| 1150 | #define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) | ||
| 1151 | #define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val) | ||
| 1152 | #define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) | ||
| 1153 | #define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val) | ||
| 1154 | #define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) | ||
| 1155 | #define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val) | ||
| 1156 | #define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) | ||
| 1157 | #define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val) | ||
| 1158 | #define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) | ||
| 1159 | #define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val) | ||
| 1160 | #define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR) | ||
| 1161 | #define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val) | ||
| 1162 | #define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR) | ||
| 1163 | #define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val) | ||
| 1164 | #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) | ||
| 1165 | #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val) | ||
| 1166 | #define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) | ||
| 1167 | #define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val) | ||
| 1168 | #define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) | ||
| 1169 | #define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val) | ||
| 1170 | #define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) | ||
| 1171 | #define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val) | ||
| 1172 | #define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR) | ||
| 1173 | #define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val) | ||
| 1174 | #define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR) | ||
| 1175 | #define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val) | ||
| 1176 | #define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) | ||
| 1177 | #define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val) | ||
| 1178 | #define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) | ||
| 1179 | #define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val) | ||
| 1180 | #define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) | ||
| 1181 | #define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val) | ||
| 1182 | #define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) | ||
| 1183 | #define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val) | ||
| 1184 | #define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) | ||
| 1185 | #define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val) | ||
| 1186 | #define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR) | ||
| 1187 | #define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val) | ||
| 1188 | #define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR) | ||
| 1189 | #define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val) | ||
| 1190 | #define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) | ||
| 1191 | #define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val) | ||
| 1192 | #define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) | ||
| 1193 | #define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val) | ||
| 1194 | #define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) | ||
| 1195 | #define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val) | ||
| 1196 | #define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) | ||
| 1197 | #define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val) | ||
| 1198 | #define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR) | ||
| 1199 | #define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val) | ||
| 1200 | #define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR) | ||
| 1201 | #define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val) | ||
| 1202 | #define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) | ||
| 1203 | #define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val) | ||
| 1204 | #define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) | ||
| 1205 | #define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val) | ||
| 1206 | #define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) | ||
| 1207 | #define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val) | ||
| 1208 | #define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) | ||
| 1209 | #define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val) | ||
| 1210 | #define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) | ||
| 1211 | #define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val) | ||
| 1212 | #define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR) | ||
| 1213 | #define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val) | ||
| 1214 | #define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR) | ||
| 1215 | #define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val) | ||
| 1216 | #define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) | ||
| 1217 | #define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val) | ||
| 1218 | #define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) | ||
| 1219 | #define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val) | ||
| 1220 | #define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) | ||
| 1221 | #define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val) | ||
| 1222 | #define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) | ||
| 1223 | #define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val) | ||
| 1224 | #define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR) | ||
| 1225 | #define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val) | ||
| 1226 | #define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR) | ||
| 1227 | #define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val) | ||
| 1228 | #define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) | ||
| 1229 | #define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val) | ||
| 1230 | #define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) | ||
| 1231 | #define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val) | ||
| 1232 | #define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) | ||
| 1233 | #define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val) | ||
| 1234 | #define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) | ||
| 1235 | #define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val) | ||
| 1236 | #define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) | ||
| 1237 | #define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val) | ||
| 1238 | #define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR) | ||
| 1239 | #define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val) | ||
| 1240 | #define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR) | ||
| 1241 | #define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val) | ||
| 1242 | #define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) | ||
| 1243 | #define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val) | ||
| 1244 | #define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) | ||
| 1245 | #define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val) | ||
| 1246 | #define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) | ||
| 1247 | #define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) | ||
| 1248 | #define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) | ||
| 1249 | #define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) | ||
| 1250 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) | ||
| 1251 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) | ||
| 1252 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | ||
| 1253 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) | ||
| 1254 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) | ||
| 1255 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) | ||
| 1256 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) | ||
| 1257 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) | ||
| 1258 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | ||
| 1259 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) | ||
| 1260 | #define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) | ||
| 1261 | #define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) | ||
| 1262 | #define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) | ||
| 1263 | #define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) | ||
| 1264 | #define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) | ||
| 1265 | #define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) | ||
| 1266 | #define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) | ||
| 1267 | #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) | ||
| 1268 | #define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) | ||
| 1269 | #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) | ||
| 1270 | #define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) | ||
| 1271 | #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) | ||
| 1272 | #define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) | ||
| 1273 | #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) | ||
| 1274 | #define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) | ||
| 1275 | #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) | ||
| 1276 | #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) | ||
| 1277 | #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) | ||
| 1278 | #define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) | ||
| 1279 | #define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) | ||
| 1280 | #define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) | ||
| 1281 | #define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) | ||
| 1282 | #define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) | ||
| 1283 | #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) | ||
| 1284 | #define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) | ||
| 1285 | #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) | ||
| 1286 | #define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) | ||
| 1287 | #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) | ||
| 1288 | #define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) | ||
| 1289 | #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) | ||
| 1290 | #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) | ||
| 1291 | #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) | ||
| 1292 | #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) | ||
| 1293 | #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) | ||
| 1294 | #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) | ||
| 1295 | #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) | ||
| 1296 | #define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) | ||
| 1297 | #define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) | ||
| 1298 | #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) | ||
| 1299 | #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) | ||
| 1300 | #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) | ||
| 1301 | #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) | ||
| 1302 | #define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) | ||
| 1303 | #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) | ||
| 1304 | #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) | ||
| 1305 | #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) | ||
| 1306 | #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) | ||
| 1307 | #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) | ||
| 1308 | #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) | ||
| 1309 | #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) | ||
| 1310 | #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) | ||
| 1311 | #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) | ||
| 1312 | #define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) | ||
| 1313 | #define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) | ||
| 1314 | #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) | ||
| 1315 | #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) | ||
| 1316 | #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) | ||
| 1317 | #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) | ||
| 1318 | #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) | ||
| 1319 | #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) | ||
| 1320 | #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) | ||
| 1321 | #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) | ||
| 1322 | #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) | ||
| 1323 | #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) | ||
| 1324 | #define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) | ||
| 1325 | #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) | ||
| 1326 | #define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) | ||
| 1327 | #define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val) | ||
| 1328 | #define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) | ||
| 1329 | #define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val) | ||
| 1330 | #define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) | ||
| 1331 | #define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val) | ||
| 1332 | #define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) | ||
| 1333 | #define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val) | ||
| 1334 | #define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) | ||
| 1335 | #define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val) | ||
| 1336 | #define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) | ||
| 1337 | #define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val) | ||
| 1338 | #define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) | ||
| 1339 | #define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val) | ||
| 1340 | #define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) | ||
| 1341 | #define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val) | ||
| 1342 | #define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) | ||
| 1343 | #define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val) | ||
| 1344 | #define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) | ||
| 1345 | #define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val) | ||
| 1346 | #define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) | ||
| 1347 | #define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val) | ||
| 1348 | #define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) | ||
| 1349 | #define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val) | ||
| 1350 | #define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) | ||
| 1351 | #define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val) | ||
| 1352 | #define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) | ||
| 1353 | #define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val) | ||
| 1354 | #define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) | ||
| 1355 | #define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val) | ||
| 1356 | #define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) | ||
| 1357 | #define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val) | ||
| 1358 | #define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) | ||
| 1359 | #define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val) | ||
| 1360 | #define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) | ||
| 1361 | #define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val) | ||
| 1362 | #define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) | ||
| 1363 | #define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val) | ||
| 1364 | #define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) | ||
| 1365 | #define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val) | ||
| 1366 | #define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) | ||
| 1367 | #define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val) | ||
| 1368 | #define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) | ||
| 1369 | #define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val) | ||
| 1370 | #define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) | ||
| 1371 | #define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val) | ||
| 1372 | #define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) | ||
| 1373 | #define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val) | ||
| 1374 | #define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) | ||
| 1375 | #define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val) | ||
| 1376 | #define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) | ||
| 1377 | #define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val) | ||
| 1378 | #define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) | ||
| 1379 | #define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val) | ||
| 1380 | #define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) | ||
| 1381 | #define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val) | ||
| 1382 | #define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) | ||
| 1383 | #define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val) | ||
| 1384 | #define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) | ||
| 1385 | #define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val) | ||
| 1386 | #define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) | ||
| 1387 | #define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val) | ||
| 1388 | #define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) | ||
| 1389 | #define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val) | ||
| 1390 | #define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) | ||
| 1391 | #define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val) | ||
| 1392 | #define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) | ||
| 1393 | #define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val) | ||
| 1394 | #define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) | ||
| 1395 | #define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val) | ||
| 1396 | #define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION) | ||
| 1397 | #define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val) | ||
| 1398 | #define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) | ||
| 1399 | #define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val) | ||
| 1400 | #define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) | ||
| 1401 | #define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val) | ||
| 1402 | #define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) | ||
| 1403 | #define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val) | ||
| 1404 | #define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) | ||
| 1405 | #define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val) | ||
| 1406 | #define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) | ||
| 1407 | #define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val) | ||
| 1408 | #define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) | ||
| 1409 | #define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val) | ||
| 1410 | #define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) | ||
| 1411 | #define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val) | ||
| 1412 | #define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2) | ||
| 1413 | #define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val) | ||
| 1414 | #define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) | ||
| 1415 | #define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val) | ||
| 1416 | #define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) | ||
| 1417 | #define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val) | ||
| 1418 | #define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) | ||
| 1419 | #define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val) | ||
| 1420 | #define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) | ||
| 1421 | #define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val) | ||
| 1422 | #define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) | ||
| 1423 | #define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val) | ||
| 1424 | #define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) | ||
| 1425 | #define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val) | ||
| 1426 | #define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) | ||
| 1427 | #define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val) | ||
| 1428 | #define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) | ||
| 1429 | #define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val) | ||
| 1430 | #define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) | ||
| 1431 | #define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val) | ||
| 1432 | #define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) | ||
| 1433 | #define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val) | ||
| 1434 | #define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) | ||
| 1435 | #define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val) | ||
| 1436 | #define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) | ||
| 1437 | #define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val) | ||
| 1438 | #define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) | ||
| 1439 | #define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val) | ||
| 1440 | #define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) | ||
| 1441 | #define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val) | ||
| 1442 | #define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) | ||
| 1443 | #define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val) | ||
| 1444 | #define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) | ||
| 1445 | #define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val) | ||
| 1446 | #define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) | ||
| 1447 | #define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val) | ||
| 1448 | #define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) | ||
| 1449 | #define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val) | ||
| 1450 | #define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) | ||
| 1451 | #define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val) | ||
| 1452 | #define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) | ||
| 1453 | #define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val) | ||
| 1454 | #define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) | ||
| 1455 | #define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val) | ||
| 1456 | #define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) | ||
| 1457 | #define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val) | ||
| 1458 | #define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) | ||
| 1459 | #define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val) | ||
| 1460 | #define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) | ||
| 1461 | #define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val) | ||
| 1462 | #define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) | ||
| 1463 | #define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val) | ||
| 1464 | #define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) | ||
| 1465 | #define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val) | ||
| 1466 | #define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) | ||
| 1467 | #define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val) | ||
| 1468 | #define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) | ||
| 1469 | #define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val) | ||
| 1470 | #define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) | ||
| 1471 | #define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val) | ||
| 1472 | #define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) | ||
| 1473 | #define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val) | ||
| 1474 | #define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) | ||
| 1475 | #define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val) | ||
| 1476 | #define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) | ||
| 1477 | #define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val) | ||
| 1478 | #define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) | ||
| 1479 | #define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val) | ||
| 1480 | #define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) | ||
| 1481 | #define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val) | ||
| 1482 | #define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) | ||
| 1483 | #define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val) | ||
| 1484 | #define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) | ||
| 1485 | #define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val) | ||
| 1486 | #define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) | ||
| 1487 | #define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val) | ||
| 1488 | #define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) | ||
| 1489 | #define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val) | ||
| 1490 | #define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) | ||
| 1491 | #define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val) | ||
| 1492 | #define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) | ||
| 1493 | #define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val) | ||
| 1494 | #define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) | ||
| 1495 | #define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val) | ||
| 1496 | #define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) | ||
| 1497 | #define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val) | ||
| 1498 | #define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) | ||
| 1499 | #define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val) | ||
| 1500 | #define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) | ||
| 1501 | #define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val) | ||
| 1502 | #define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) | ||
| 1503 | #define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val) | ||
| 1504 | #define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) | ||
| 1505 | #define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val) | ||
| 1506 | #define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) | ||
| 1507 | #define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val) | ||
| 1508 | #define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) | ||
| 1509 | #define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val) | ||
| 1510 | #define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) | ||
| 1511 | #define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val) | ||
| 1512 | #define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) | ||
| 1513 | #define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val) | ||
| 1514 | #define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) | ||
| 1515 | #define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val) | ||
| 1516 | #define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) | ||
| 1517 | #define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val) | ||
| 1518 | #define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) | ||
| 1519 | #define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val) | ||
| 1520 | #define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) | ||
| 1521 | #define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val) | ||
| 1522 | #define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) | ||
| 1523 | #define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val) | ||
| 1524 | #define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) | ||
| 1525 | #define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val) | ||
| 1526 | #define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) | ||
| 1527 | #define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val) | ||
| 1528 | #define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) | ||
| 1529 | #define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val) | ||
| 1530 | #define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) | ||
| 1531 | #define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val) | ||
| 1532 | #define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) | ||
| 1533 | #define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val) | ||
| 1534 | #define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) | ||
| 1535 | #define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val) | ||
| 1536 | #define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) | ||
| 1537 | #define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val) | ||
| 1538 | #define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) | ||
| 1539 | #define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val) | ||
| 1540 | #define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) | ||
| 1541 | #define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val) | ||
| 1542 | #define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) | ||
| 1543 | #define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val) | ||
| 1544 | #define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) | ||
| 1545 | #define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val) | ||
| 1546 | #define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) | ||
| 1547 | #define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val) | ||
| 1548 | #define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) | ||
| 1549 | #define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val) | ||
| 1550 | #define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) | ||
| 1551 | #define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val) | ||
| 1552 | #define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) | ||
| 1553 | #define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val) | ||
| 1554 | #define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) | ||
| 1555 | #define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val) | ||
| 1556 | #define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) | ||
| 1557 | #define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val) | ||
| 1558 | #define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) | ||
| 1559 | #define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val) | ||
| 1560 | #define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) | ||
| 1561 | #define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val) | ||
| 1562 | #define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) | ||
| 1563 | #define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val) | ||
| 1564 | #define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) | ||
| 1565 | #define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val) | ||
| 1566 | #define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) | ||
| 1567 | #define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val) | ||
| 1568 | #define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) | ||
| 1569 | #define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val) | ||
| 1570 | #define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) | ||
| 1571 | #define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val) | ||
| 1572 | #define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) | ||
| 1573 | #define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val) | ||
| 1574 | #define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) | ||
| 1575 | #define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val) | ||
| 1576 | #define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) | ||
| 1577 | #define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val) | ||
| 1578 | #define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) | ||
| 1579 | #define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val) | ||
| 1580 | #define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) | ||
| 1581 | #define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val) | ||
| 1582 | #define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) | ||
| 1583 | #define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val) | ||
| 1584 | #define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) | ||
| 1585 | #define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val) | ||
| 1586 | #define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) | ||
| 1587 | #define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val) | ||
| 1588 | #define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) | ||
| 1589 | #define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val) | ||
| 1590 | #define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) | ||
| 1591 | #define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val) | ||
| 1592 | #define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) | ||
| 1593 | #define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val) | ||
| 1594 | #define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) | ||
| 1595 | #define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val) | ||
| 1596 | #define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) | ||
| 1597 | #define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val) | ||
| 1598 | #define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) | ||
| 1599 | #define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val) | ||
| 1600 | #define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) | ||
| 1601 | #define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val) | ||
| 1602 | #define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) | ||
| 1603 | #define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val) | ||
| 1604 | #define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) | ||
| 1605 | #define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val) | ||
| 1606 | #define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) | ||
| 1607 | #define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val) | ||
| 1608 | #define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) | ||
| 1609 | #define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val) | ||
| 1610 | #define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) | ||
| 1611 | #define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val) | ||
| 1612 | #define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) | ||
| 1613 | #define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val) | ||
| 1614 | #define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) | ||
| 1615 | #define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val) | ||
| 1616 | #define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) | ||
| 1617 | #define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val) | ||
| 1618 | #define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) | ||
| 1619 | #define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val) | ||
| 1620 | #define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) | ||
| 1621 | #define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val) | ||
| 1622 | #define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) | ||
| 1623 | #define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val) | ||
| 1624 | #define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) | ||
| 1625 | #define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val) | ||
| 1626 | #define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) | ||
| 1627 | #define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val) | ||
| 1628 | #define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) | ||
| 1629 | #define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val) | ||
| 1630 | #define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) | ||
| 1631 | #define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val) | ||
| 1632 | #define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) | ||
| 1633 | #define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val) | ||
| 1634 | #define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) | ||
| 1635 | #define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val) | ||
| 1636 | #define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) | ||
| 1637 | #define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val) | ||
| 1638 | #define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) | ||
| 1639 | #define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val) | ||
| 1640 | #define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) | ||
| 1641 | #define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val) | ||
| 1642 | #define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) | ||
| 1643 | #define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val) | ||
| 1644 | #define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) | ||
| 1645 | #define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val) | ||
| 1646 | #define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) | ||
| 1647 | #define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val) | ||
| 1648 | #define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) | ||
| 1649 | #define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val) | ||
| 1650 | #define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) | ||
| 1651 | #define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val) | ||
| 1652 | #define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) | ||
| 1653 | #define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val) | ||
| 1654 | #define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) | ||
| 1655 | #define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val) | ||
| 1656 | #define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) | ||
| 1657 | #define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val) | ||
| 1658 | #define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) | ||
| 1659 | #define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val) | ||
| 1660 | #define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) | ||
| 1661 | #define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val) | ||
| 1662 | #define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) | ||
| 1663 | #define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val) | ||
| 1664 | #define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) | ||
| 1665 | #define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val) | ||
| 1666 | #define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) | ||
| 1667 | #define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val) | ||
| 1668 | #define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) | ||
| 1669 | #define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val) | ||
| 1670 | #define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) | ||
| 1671 | #define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val) | ||
| 1672 | #define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) | ||
| 1673 | #define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val) | ||
| 1674 | #define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) | ||
| 1675 | #define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val) | ||
| 1676 | #define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) | ||
| 1677 | #define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val) | ||
| 1678 | #define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) | ||
| 1679 | #define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val) | ||
| 1680 | #define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) | ||
| 1681 | #define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val) | ||
| 1682 | #define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) | ||
| 1683 | #define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val) | ||
| 1684 | #define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) | ||
| 1685 | #define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val) | ||
| 1686 | #define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) | ||
| 1687 | #define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val) | ||
| 1688 | #define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) | ||
| 1689 | #define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val) | ||
| 1690 | #define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) | ||
| 1691 | #define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val) | ||
| 1692 | #define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) | ||
| 1693 | #define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val) | ||
| 1694 | #define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) | ||
| 1695 | #define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val) | ||
| 1696 | #define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) | ||
| 1697 | #define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val) | ||
| 1698 | #define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) | ||
| 1699 | #define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val) | ||
| 1700 | #define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) | ||
| 1701 | #define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val) | ||
| 1702 | #define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) | ||
| 1703 | #define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val) | ||
| 1704 | #define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) | ||
| 1705 | #define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val) | ||
| 1706 | #define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) | ||
| 1707 | #define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val) | ||
| 1708 | #define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) | ||
| 1709 | #define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val) | ||
| 1710 | #define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) | ||
| 1711 | #define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val) | ||
| 1712 | #define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) | ||
| 1713 | #define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val) | ||
| 1714 | #define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) | ||
| 1715 | #define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val) | ||
| 1716 | #define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) | ||
| 1717 | #define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val) | ||
| 1718 | #define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) | ||
| 1719 | #define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val) | ||
| 1720 | #define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) | ||
| 1721 | #define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val) | ||
| 1722 | #define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) | ||
| 1723 | #define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val) | ||
| 1724 | #define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) | ||
| 1725 | #define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val) | ||
| 1726 | #define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) | ||
| 1727 | #define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val) | ||
| 1728 | #define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) | ||
| 1729 | #define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val) | ||
| 1730 | #define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) | ||
| 1731 | #define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val) | ||
| 1732 | #define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) | ||
| 1733 | #define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val) | ||
| 1734 | #define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) | ||
| 1735 | #define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val) | ||
| 1736 | #define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) | ||
| 1737 | #define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val) | ||
| 1738 | #define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) | ||
| 1739 | #define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val) | ||
| 1740 | #define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) | ||
| 1741 | #define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val) | ||
| 1742 | #define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) | ||
| 1743 | #define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val) | ||
| 1744 | #define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) | ||
| 1745 | #define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val) | ||
| 1746 | #define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) | ||
| 1747 | #define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val) | ||
| 1748 | #define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) | ||
| 1749 | #define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val) | ||
| 1750 | #define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) | ||
| 1751 | #define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val) | ||
| 1752 | #define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) | ||
| 1753 | #define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val) | ||
| 1754 | #define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) | ||
| 1755 | #define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val) | ||
| 1756 | #define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) | ||
| 1757 | #define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val) | ||
| 1758 | #define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) | ||
| 1759 | #define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val) | ||
| 1760 | #define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) | ||
| 1761 | #define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val) | ||
| 1762 | #define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) | ||
| 1763 | #define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val) | ||
| 1764 | #define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) | ||
| 1765 | #define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val) | ||
| 1766 | #define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) | ||
| 1767 | #define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val) | ||
| 1768 | #define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) | ||
| 1769 | #define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val) | ||
| 1770 | #define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) | ||
| 1771 | #define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val) | ||
| 1772 | #define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) | ||
| 1773 | #define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val) | ||
| 1774 | #define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) | ||
| 1775 | #define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val) | ||
| 1776 | #define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) | ||
| 1777 | #define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val) | ||
| 1778 | #define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) | ||
| 1779 | #define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val) | ||
| 1780 | #define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) | ||
| 1781 | #define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val) | ||
| 1782 | #define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) | ||
| 1783 | #define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val) | ||
| 1784 | #define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) | ||
| 1785 | #define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val) | ||
| 1786 | #define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) | ||
| 1787 | #define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val) | ||
| 1788 | #define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) | ||
| 1789 | #define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val) | ||
| 1790 | #define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) | ||
| 1791 | #define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val) | ||
| 1792 | #define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) | ||
| 1793 | #define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val) | ||
| 1794 | #define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) | ||
| 1795 | #define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val) | ||
| 1796 | #define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) | ||
| 1797 | #define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val) | ||
| 1798 | #define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) | ||
| 1799 | #define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val) | ||
| 1800 | #define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) | ||
| 1801 | #define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val) | ||
| 1802 | #define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) | ||
| 1803 | #define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val) | ||
| 1804 | #define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) | ||
| 1805 | #define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val) | ||
| 1806 | #define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) | ||
| 1807 | #define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val) | ||
| 1808 | #define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) | ||
| 1809 | #define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val) | ||
| 1810 | #define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) | ||
| 1811 | #define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val) | ||
| 1812 | #define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) | ||
| 1813 | #define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val) | ||
| 1814 | #define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) | ||
| 1815 | #define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val) | ||
| 1816 | #define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) | ||
| 1817 | #define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val) | ||
| 1818 | #define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) | ||
| 1819 | #define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val) | ||
| 1820 | #define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) | ||
| 1821 | #define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val) | ||
| 1822 | #define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) | ||
| 1823 | #define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val) | ||
| 1824 | #define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) | ||
| 1825 | #define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val) | ||
| 1826 | #define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) | ||
| 1827 | #define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val) | ||
| 1828 | #define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) | ||
| 1829 | #define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val) | ||
| 1830 | #define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) | ||
| 1831 | #define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val) | ||
| 1832 | #define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) | ||
| 1833 | #define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val) | ||
| 1834 | #define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) | ||
| 1835 | #define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val) | ||
| 1836 | #define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) | ||
| 1837 | #define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val) | ||
| 1838 | #define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) | ||
| 1839 | #define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val) | ||
| 1840 | #define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) | ||
| 1841 | #define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val) | ||
| 1842 | #define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) | ||
| 1843 | #define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val) | ||
| 1844 | #define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) | ||
| 1845 | #define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val) | ||
| 1846 | #define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) | ||
| 1847 | #define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val) | ||
| 1848 | #define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) | ||
| 1849 | #define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val) | ||
| 1850 | #define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) | ||
| 1851 | #define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val) | ||
| 1852 | #define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) | ||
| 1853 | #define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val) | ||
| 1854 | #define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) | ||
| 1855 | #define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val) | ||
| 1856 | #define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) | ||
| 1857 | #define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val) | ||
| 1858 | #define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) | ||
| 1859 | #define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val) | ||
| 1860 | #define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) | ||
| 1861 | #define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val) | ||
| 1862 | #define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) | ||
| 1863 | #define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val) | ||
| 1864 | #define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) | ||
| 1865 | #define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val) | ||
| 1866 | #define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) | ||
| 1867 | #define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val) | ||
| 1868 | #define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) | ||
| 1869 | #define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val) | ||
| 1870 | #define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) | ||
| 1871 | #define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val) | ||
| 1872 | #define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) | ||
| 1873 | #define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val) | ||
| 1874 | #define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) | ||
| 1875 | #define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val) | ||
| 1876 | #define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) | ||
| 1877 | #define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val) | ||
| 1878 | #define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) | ||
| 1879 | #define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val) | ||
| 1880 | #define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) | ||
| 1881 | #define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val) | ||
| 1882 | #define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) | ||
| 1883 | #define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val) | ||
| 1884 | #define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) | ||
| 1885 | #define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val) | ||
| 1886 | #define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) | ||
| 1887 | #define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val) | ||
| 1888 | #define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) | ||
| 1889 | #define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val) | ||
| 1890 | #define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) | ||
| 1891 | #define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val) | ||
| 1892 | #define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) | ||
| 1893 | #define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val) | ||
| 1894 | #define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) | ||
| 1895 | #define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val) | ||
| 1896 | #define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) | ||
| 1897 | #define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val) | ||
| 1898 | #define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) | ||
| 1899 | #define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val) | ||
| 1900 | #define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) | ||
| 1901 | #define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val) | ||
| 1902 | #define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) | ||
| 1903 | #define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val) | ||
| 1904 | #define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) | ||
| 1905 | #define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val) | ||
| 1906 | #define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) | ||
| 1907 | #define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val) | ||
| 1908 | #define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) | ||
| 1909 | #define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val) | ||
| 1910 | #define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) | ||
| 1911 | #define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val) | ||
| 1912 | #define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) | ||
| 1913 | #define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val) | ||
| 1914 | #define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) | ||
| 1915 | #define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val) | ||
| 1916 | #define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) | ||
| 1917 | #define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val) | ||
| 1918 | #define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) | ||
| 1919 | #define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val) | ||
| 1920 | #define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) | ||
| 1921 | #define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val) | ||
| 1922 | #define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) | ||
| 1923 | #define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val) | ||
| 1924 | #define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) | ||
| 1925 | #define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val) | ||
| 1926 | #define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) | ||
| 1927 | #define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val) | ||
| 1928 | #define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) | ||
| 1929 | #define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val) | ||
| 1930 | #define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) | ||
| 1931 | #define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val) | ||
| 1932 | #define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) | ||
| 1933 | #define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val) | ||
| 1934 | #define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) | ||
| 1935 | #define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val) | ||
| 1936 | #define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) | ||
| 1937 | #define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val) | ||
| 1938 | #define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) | ||
| 1939 | #define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val) | ||
| 1940 | #define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) | ||
| 1941 | #define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val) | ||
| 1942 | #define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) | ||
| 1943 | #define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val) | ||
| 1944 | #define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) | ||
| 1945 | #define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val) | ||
| 1946 | #define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) | ||
| 1947 | #define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val) | ||
| 1948 | #define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) | ||
| 1949 | #define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val) | ||
| 1950 | #define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) | ||
| 1951 | #define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val) | ||
| 1952 | #define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) | ||
| 1953 | #define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val) | ||
| 1954 | #define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) | ||
| 1955 | #define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val) | ||
| 1956 | #define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) | ||
| 1957 | #define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val) | ||
| 1958 | #define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) | ||
| 1959 | #define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val) | ||
| 1960 | #define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) | ||
| 1961 | #define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val) | ||
| 1962 | #define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) | ||
| 1963 | #define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val) | ||
| 1964 | #define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) | ||
| 1965 | #define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val) | ||
| 1966 | #define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) | ||
| 1967 | #define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val) | ||
| 1968 | #define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) | ||
| 1969 | #define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val) | ||
| 1970 | #define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) | ||
| 1971 | #define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val) | ||
| 1972 | #define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) | ||
| 1973 | #define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val) | ||
| 1974 | #define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) | ||
| 1975 | #define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val) | ||
| 1976 | #define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) | ||
| 1977 | #define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val) | ||
| 1978 | #define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) | ||
| 1979 | #define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val) | ||
| 1980 | #define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) | ||
| 1981 | #define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val) | ||
| 1982 | #define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) | ||
| 1983 | #define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val) | ||
| 1984 | #define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) | ||
| 1985 | #define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val) | ||
| 1986 | #define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) | ||
| 1987 | #define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val) | ||
| 1988 | #define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) | ||
| 1989 | #define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val) | ||
| 1990 | #define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) | ||
| 1991 | #define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val) | ||
| 1992 | #define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) | ||
| 1993 | #define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val) | ||
| 1994 | #define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) | ||
| 1995 | #define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val) | ||
| 1996 | #define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) | ||
| 1997 | #define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val) | ||
| 1998 | #define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) | ||
| 1999 | #define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val) | ||
| 2000 | #define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) | ||
| 2001 | #define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val) | ||
| 2002 | #define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) | ||
| 2003 | #define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val) | ||
| 2004 | #define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) | ||
| 2005 | #define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val) | ||
| 2006 | #define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) | ||
| 2007 | #define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val) | ||
| 2008 | #define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) | ||
| 2009 | #define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val) | ||
| 2010 | #define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) | ||
| 2011 | #define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val) | ||
| 2012 | #define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) | ||
| 2013 | #define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val) | ||
| 2014 | #define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) | ||
| 2015 | #define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val) | ||
| 2016 | #define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) | ||
| 2017 | #define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val) | ||
| 2018 | #define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) | ||
| 2019 | #define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val) | ||
| 2020 | #define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) | ||
| 2021 | #define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val) | ||
| 2022 | #define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) | ||
| 2023 | #define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val) | ||
| 2024 | #define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) | ||
| 2025 | #define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val) | ||
| 2026 | #define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) | ||
| 2027 | #define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val) | ||
| 2028 | #define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) | ||
| 2029 | #define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val) | ||
| 2030 | #define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) | ||
| 2031 | #define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val) | ||
| 2032 | #define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) | ||
| 2033 | #define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val) | ||
| 2034 | #define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) | ||
| 2035 | #define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val) | ||
| 2036 | #define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) | ||
| 2037 | #define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val) | ||
| 2038 | #define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) | ||
| 2039 | #define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val) | ||
| 2040 | #define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) | ||
| 2041 | #define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val) | ||
| 2042 | #define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) | ||
| 2043 | #define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val) | ||
| 2044 | #define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) | ||
| 2045 | #define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val) | ||
| 2046 | #define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) | ||
| 2047 | #define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val) | ||
| 2048 | #define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) | ||
| 2049 | #define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val) | ||
| 2050 | #define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) | ||
| 2051 | #define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val) | ||
| 2052 | #define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) | ||
| 2053 | #define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) | ||
| 2054 | |||
| 2055 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 2056 | #include <asm/irq.h> | ||
| 2057 | |||
| 2058 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 2059 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 2060 | { | ||
| 2061 | unsigned long flags, iwr0, iwr1; | ||
| 2062 | |||
| 2063 | if (val == bfin_read_PLL_CTL()) | ||
| 2064 | return; | ||
| 2065 | |||
| 2066 | local_irq_save_hw(flags); | ||
| 2067 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 2068 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 2069 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 2070 | /* Only allow PPL Wakeup) */ | ||
| 2071 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 2072 | bfin_write32(SIC_IWR1, 0); | ||
| 2073 | |||
| 2074 | bfin_write16(PLL_CTL, val); | ||
| 2075 | SSYNC(); | ||
| 2076 | asm("IDLE;"); | ||
| 2077 | |||
| 2078 | bfin_write32(SIC_IWR0, iwr0); | ||
| 2079 | bfin_write32(SIC_IWR1, iwr1); | ||
| 2080 | local_irq_restore_hw(flags); | ||
| 2081 | } | ||
| 2082 | |||
| 2083 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 2084 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 2085 | { | ||
| 2086 | unsigned long flags, iwr0, iwr1; | ||
| 2087 | |||
| 2088 | if (val == bfin_read_VR_CTL()) | ||
| 2089 | return; | ||
| 2090 | |||
| 2091 | local_irq_save_hw(flags); | ||
| 2092 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 2093 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 2094 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 2095 | /* Only allow PPL Wakeup) */ | ||
| 2096 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 2097 | bfin_write32(SIC_IWR1, 0); | ||
| 2098 | |||
| 2099 | bfin_write16(VR_CTL, val); | ||
| 2100 | SSYNC(); | ||
| 2101 | asm("IDLE;"); | ||
| 2102 | |||
| 2103 | bfin_write32(SIC_IWR0, iwr0); | ||
| 2104 | bfin_write32(SIC_IWR1, iwr1); | ||
| 2105 | local_irq_restore_hw(flags); | ||
| 2106 | } | ||
| 2107 | |||
| 2108 | #endif | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h new file mode 100644 index 000000000000..198c4bbc8e5d --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h | |||
| @@ -0,0 +1,240 @@ | |||
| 1 | /* DO NOT EDIT THIS FILE | ||
| 2 | * Automatically generated by generate-cdef-headers.xsl | ||
| 3 | * DO NOT EDIT THIS FILE | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef _CDEF_BF539_H | ||
| 7 | #define _CDEF_BF539_H | ||
| 8 | |||
| 9 | /* Include MMRs Common to BF538 */ | ||
| 10 | #include "cdefBF538.h" | ||
| 11 | |||
| 12 | |||
| 13 | #define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG) | ||
| 14 | #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) | ||
| 15 | #define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0) | ||
| 16 | #define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val) | ||
| 17 | #define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0) | ||
| 18 | #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val) | ||
| 19 | #define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1) | ||
| 20 | #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val) | ||
| 21 | #define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0) | ||
| 22 | #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val) | ||
| 23 | #define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1) | ||
| 24 | #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val) | ||
| 25 | #define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0) | ||
| 26 | #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val) | ||
| 27 | #define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1) | ||
| 28 | #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val) | ||
| 29 | #define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION) | ||
| 30 | #define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val) | ||
| 31 | #define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION) | ||
| 32 | #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val) | ||
| 33 | #define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY) | ||
| 34 | #define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val) | ||
| 35 | #define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY) | ||
| 36 | #define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val) | ||
| 37 | #define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR) | ||
| 38 | #define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val) | ||
| 39 | #define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR) | ||
| 40 | #define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val) | ||
| 41 | #define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR) | ||
| 42 | #define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val) | ||
| 43 | #define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0) | ||
| 44 | #define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val) | ||
| 45 | #define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1) | ||
| 46 | #define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val) | ||
| 47 | #define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2) | ||
| 48 | #define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val) | ||
| 49 | #define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3) | ||
| 50 | #define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val) | ||
| 51 | #define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4) | ||
| 52 | #define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val) | ||
| 53 | #define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5) | ||
| 54 | #define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val) | ||
| 55 | #define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6) | ||
| 56 | #define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val) | ||
| 57 | #define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7) | ||
| 58 | #define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val) | ||
| 59 | #define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8) | ||
| 60 | #define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val) | ||
| 61 | #define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9) | ||
| 62 | #define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val) | ||
| 63 | #define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10) | ||
| 64 | #define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val) | ||
| 65 | #define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11) | ||
| 66 | #define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val) | ||
| 67 | #define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12) | ||
| 68 | #define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val) | ||
| 69 | #define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13) | ||
| 70 | #define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val) | ||
| 71 | #define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14) | ||
| 72 | #define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val) | ||
| 73 | #define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0) | ||
| 74 | #define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val) | ||
| 75 | #define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1) | ||
| 76 | #define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val) | ||
| 77 | #define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2) | ||
| 78 | #define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val) | ||
| 79 | #define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3) | ||
| 80 | #define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val) | ||
| 81 | #define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4) | ||
| 82 | #define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val) | ||
| 83 | #define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5) | ||
| 84 | #define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val) | ||
| 85 | #define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6) | ||
| 86 | #define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val) | ||
| 87 | #define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7) | ||
| 88 | #define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val) | ||
| 89 | #define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG) | ||
| 90 | #define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val) | ||
| 91 | #define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR) | ||
| 92 | #define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val) | ||
| 93 | #define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT) | ||
| 94 | #define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val) | ||
| 95 | #define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR) | ||
| 96 | #define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val) | ||
| 97 | #define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT) | ||
| 98 | #define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val) | ||
| 99 | #define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG) | ||
| 100 | #define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val) | ||
| 101 | #define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR) | ||
| 102 | #define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val) | ||
| 103 | #define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT) | ||
| 104 | #define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val) | ||
| 105 | #define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR) | ||
| 106 | #define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val) | ||
| 107 | #define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT) | ||
| 108 | #define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val) | ||
| 109 | #define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG) | ||
| 110 | #define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val) | ||
| 111 | #define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR) | ||
| 112 | #define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val) | ||
| 113 | #define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT) | ||
| 114 | #define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val) | ||
| 115 | #define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR) | ||
| 116 | #define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val) | ||
| 117 | #define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT) | ||
| 118 | #define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val) | ||
| 119 | #define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG) | ||
| 120 | #define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val) | ||
| 121 | #define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR) | ||
| 122 | #define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val) | ||
| 123 | #define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT) | ||
| 124 | #define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val) | ||
| 125 | #define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR) | ||
| 126 | #define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val) | ||
| 127 | #define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT) | ||
| 128 | #define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val) | ||
| 129 | #define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG) | ||
| 130 | #define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val) | ||
| 131 | #define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR) | ||
| 132 | #define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val) | ||
| 133 | #define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT) | ||
| 134 | #define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val) | ||
| 135 | #define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR) | ||
| 136 | #define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val) | ||
| 137 | #define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT) | ||
| 138 | #define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val) | ||
| 139 | #define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG) | ||
| 140 | #define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val) | ||
| 141 | #define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR) | ||
| 142 | #define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val) | ||
| 143 | #define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT) | ||
| 144 | #define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val) | ||
| 145 | #define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR) | ||
| 146 | #define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val) | ||
| 147 | #define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT) | ||
| 148 | #define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val) | ||
| 149 | #define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG) | ||
| 150 | #define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val) | ||
| 151 | #define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR) | ||
| 152 | #define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val) | ||
| 153 | #define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT) | ||
| 154 | #define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val) | ||
| 155 | #define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR) | ||
| 156 | #define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val) | ||
| 157 | #define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT) | ||
| 158 | #define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val) | ||
| 159 | #define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG) | ||
| 160 | #define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val) | ||
| 161 | #define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR) | ||
| 162 | #define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val) | ||
| 163 | #define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT) | ||
| 164 | #define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val) | ||
| 165 | #define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR) | ||
| 166 | #define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val) | ||
| 167 | #define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT) | ||
| 168 | #define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val) | ||
| 169 | #define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL) | ||
| 170 | #define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val) | ||
| 171 | #define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR) | ||
| 172 | #define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val) | ||
| 173 | #define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR) | ||
| 174 | #define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val) | ||
| 175 | #define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR) | ||
| 176 | #define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val) | ||
| 177 | #define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR) | ||
| 178 | #define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val) | ||
| 179 | #define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL) | ||
| 180 | #define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val) | ||
| 181 | #define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR) | ||
| 182 | #define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val) | ||
| 183 | #define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR) | ||
| 184 | #define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val) | ||
| 185 | #define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR) | ||
| 186 | #define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val) | ||
| 187 | #define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR) | ||
| 188 | #define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val) | ||
| 189 | #define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR) | ||
| 190 | #define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val) | ||
| 191 | #define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR) | ||
| 192 | #define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val) | ||
| 193 | #define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0) | ||
| 194 | #define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val) | ||
| 195 | #define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0) | ||
| 196 | #define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val) | ||
| 197 | #define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1) | ||
| 198 | #define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val) | ||
| 199 | #define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1) | ||
| 200 | #define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val) | ||
| 201 | #define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0) | ||
| 202 | #define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val) | ||
| 203 | #define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1) | ||
| 204 | #define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val) | ||
| 205 | #define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0) | ||
| 206 | #define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val) | ||
| 207 | #define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1) | ||
| 208 | #define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val) | ||
| 209 | #define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2) | ||
| 210 | #define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val) | ||
| 211 | #define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3) | ||
| 212 | #define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val) | ||
| 213 | #define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4) | ||
| 214 | #define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val) | ||
| 215 | #define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5) | ||
| 216 | #define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val) | ||
| 217 | #define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6) | ||
| 218 | #define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val) | ||
| 219 | #define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7) | ||
| 220 | #define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val) | ||
| 221 | #define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8) | ||
| 222 | #define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val) | ||
| 223 | #define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9) | ||
| 224 | #define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val) | ||
| 225 | #define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10) | ||
| 226 | #define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val) | ||
| 227 | #define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11) | ||
| 228 | #define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val) | ||
| 229 | #define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12) | ||
| 230 | #define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val) | ||
| 231 | #define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13) | ||
| 232 | #define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val) | ||
| 233 | #define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14) | ||
| 234 | #define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val) | ||
| 235 | #define bfin_read_MXVR_PLL_CTL_1() bfin_read32(MXVR_PLL_CTL_1) | ||
| 236 | #define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val) | ||
| 237 | #define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT) | ||
| 238 | #define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val) | ||
| 239 | |||
| 240 | #endif /* _CDEF_BF539_H */ | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h new file mode 100644 index 000000000000..6adbfcc65a35 --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h | |||
| @@ -0,0 +1,4243 @@ | |||
| 1 | /************************************************************************ | ||
| 2 | * | ||
| 3 | * This file is subject to the terms and conditions of the GNU Public | ||
| 4 | * License. See the file "COPYING" in the main directory of this archive | ||
| 5 | * for more details. | ||
| 6 | * | ||
| 7 | * Non-GPL License also available as part of VisualDSP++ | ||
| 8 | * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html | ||
| 9 | * | ||
| 10 | * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved | ||
| 11 | * | ||
| 12 | * This file under source code control, please send bugs or changes to: | ||
| 13 | * dsptools.support@analog.com | ||
| 14 | * | ||
| 15 | ************************************************************************/ | ||
| 16 | /* | ||
| 17 | * File: include/asm-blackfin/mach-bf538/defBF539.h | ||
| 18 | * Based on: | ||
| 19 | * Author: | ||
| 20 | * | ||
| 21 | * Created: | ||
| 22 | * Description: | ||
| 23 | * | ||
| 24 | * Rev: | ||
| 25 | * | ||
| 26 | * Modified: | ||
| 27 | * | ||
| 28 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 29 | * | ||
| 30 | * This program is free software; you can redistribute it and/or modify | ||
| 31 | * it under the terms of the GNU General Public License as published by | ||
| 32 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 33 | * any later version. | ||
| 34 | * | ||
| 35 | * This program is distributed in the hope that it will be useful, | ||
| 36 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 37 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 38 | * GNU General Public License for more details. | ||
| 39 | * | ||
| 40 | * You should have received a copy of the GNU General Public License | ||
| 41 | * along with this program; see the file COPYING. | ||
| 42 | * If not, write to the Free Software Foundation, | ||
| 43 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 44 | */ | ||
| 45 | /* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF538/9 */ | ||
| 46 | |||
| 47 | #ifndef _DEF_BF539_H | ||
| 48 | #define _DEF_BF539_H | ||
| 49 | |||
| 50 | /* include all Core registers and bit definitions */ | ||
| 51 | #include <asm/def_LPBlackfin.h> | ||
| 52 | |||
| 53 | |||
| 54 | /*********************************************************************************** */ | ||
| 55 | /* System MMR Register Map */ | ||
| 56 | /*********************************************************************************** */ | ||
| 57 | /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */ | ||
| 58 | #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ | ||
| 59 | #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ | ||
| 60 | #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ | ||
| 61 | #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ | ||
| 62 | #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ | ||
| 63 | #define CHIPID 0xFFC00014 /* Chip ID Register */ | ||
| 64 | |||
| 65 | /* CHIPID Masks */ | ||
| 66 | #define CHIPID_VERSION 0xF0000000 | ||
| 67 | #define CHIPID_FAMILY 0x0FFFF000 | ||
| 68 | #define CHIPID_MANUFACTURE 0x00000FFE | ||
| 69 | |||
| 70 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ | ||
| 71 | #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ | ||
| 72 | #define SYSCR 0xFFC00104 /* System Configuration registe */ | ||
| 73 | #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ | ||
| 74 | #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ | ||
| 75 | #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ | ||
| 76 | #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ | ||
| 77 | #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ | ||
| 78 | #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ | ||
| 79 | #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ | ||
| 80 | #define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ | ||
| 81 | #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ | ||
| 82 | #define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ | ||
| 83 | #define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ | ||
| 84 | #define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ | ||
| 85 | #define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ | ||
| 86 | |||
| 87 | |||
| 88 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ | ||
| 89 | #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ | ||
| 90 | #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ | ||
| 91 | #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ | ||
| 92 | |||
| 93 | |||
| 94 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ | ||
| 95 | #define RTC_STAT 0xFFC00300 /* RTC Status Register */ | ||
| 96 | #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ | ||
| 97 | #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ | ||
| 98 | #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ | ||
| 99 | #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ | ||
| 100 | #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ | ||
| 101 | #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ | ||
| 102 | |||
| 103 | |||
| 104 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ | ||
| 105 | #define UART0_THR 0xFFC00400 /* Transmit Holding register */ | ||
| 106 | #define UART0_RBR 0xFFC00400 /* Receive Buffer register */ | ||
| 107 | #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ | ||
| 108 | #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ | ||
| 109 | #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ | ||
| 110 | #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ | ||
| 111 | #define UART0_LCR 0xFFC0040C /* Line Control Register */ | ||
| 112 | #define UART0_MCR 0xFFC00410 /* Modem Control Register */ | ||
| 113 | #define UART0_LSR 0xFFC00414 /* Line Status Register */ | ||
| 114 | #define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ | ||
| 115 | #define UART0_GCTL 0xFFC00424 /* Global Control Register */ | ||
| 116 | |||
| 117 | |||
| 118 | /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ | ||
| 119 | |||
| 120 | #define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ | ||
| 121 | #define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ | ||
| 122 | #define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ | ||
| 123 | #define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ | ||
| 124 | #define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ | ||
| 125 | #define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ | ||
| 126 | #define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ | ||
| 127 | #define SPI0_REGBASE SPI0_CTL | ||
| 128 | |||
| 129 | |||
| 130 | /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ | ||
| 131 | #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ | ||
| 132 | #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ | ||
| 133 | #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ | ||
| 134 | #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ | ||
| 135 | |||
| 136 | #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ | ||
| 137 | #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ | ||
| 138 | #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ | ||
| 139 | #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ | ||
| 140 | |||
| 141 | #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ | ||
| 142 | #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ | ||
| 143 | #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ | ||
| 144 | #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ | ||
| 145 | |||
| 146 | #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ | ||
| 147 | #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ | ||
| 148 | #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ | ||
| 149 | |||
| 150 | |||
| 151 | /* Programmable Flags (0xFFC00700 - 0xFFC007FF) */ | ||
| 152 | #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ | ||
| 153 | #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ | ||
| 154 | #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ | ||
| 155 | #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ | ||
| 156 | #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ | ||
| 157 | #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ | ||
| 158 | #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ | ||
| 159 | #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ | ||
| 160 | #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ | ||
| 161 | #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ | ||
| 162 | #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ | ||
| 163 | #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ | ||
| 164 | #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ | ||
| 165 | #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ | ||
| 166 | #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ | ||
| 167 | #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ | ||
| 168 | #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ | ||
| 169 | |||
| 170 | |||
| 171 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ | ||
| 172 | #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 173 | #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 174 | #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ | ||
| 175 | #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ | ||
| 176 | #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ | ||
| 177 | #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ | ||
| 178 | #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 179 | #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 180 | #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ | ||
| 181 | #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ | ||
| 182 | #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ | ||
| 183 | #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ | ||
| 184 | #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ | ||
| 185 | #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ | ||
| 186 | #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ | ||
| 187 | #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ | ||
| 188 | #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ | ||
| 189 | #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ | ||
| 190 | #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ | ||
| 191 | #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ | ||
| 192 | #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ | ||
| 193 | #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ | ||
| 194 | |||
| 195 | |||
| 196 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ | ||
| 197 | #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 198 | #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 199 | #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ | ||
| 200 | #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ | ||
| 201 | #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ | ||
| 202 | #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ | ||
| 203 | #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ | ||
| 204 | #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ | ||
| 205 | #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ | ||
| 206 | #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ | ||
| 207 | #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ | ||
| 208 | #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ | ||
| 209 | #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ | ||
| 210 | #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ | ||
| 211 | #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ | ||
| 212 | #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ | ||
| 213 | #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ | ||
| 214 | #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ | ||
| 215 | #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ | ||
| 216 | #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ | ||
| 217 | #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ | ||
| 218 | #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ | ||
| 219 | |||
| 220 | |||
| 221 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ | ||
| 222 | /* Asynchronous Memory Controller */ | ||
| 223 | #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ | ||
| 224 | #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ | ||
| 225 | #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ | ||
| 226 | |||
| 227 | /* SDRAM Controller */ | ||
| 228 | #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ | ||
| 229 | #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ | ||
| 230 | #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ | ||
| 231 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | ||
| 232 | |||
| 233 | |||
| 234 | |||
| 235 | /* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ | ||
| 236 | |||
| 237 | #define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ | ||
| 238 | #define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */ | ||
| 239 | |||
| 240 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
| 241 | #define DMA0_TCPER DMAC0_TC_PER | ||
| 242 | #define DMA0_TCCNT DMAC0_TC_CNT | ||
| 243 | |||
| 244 | |||
| 245 | /* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */ | ||
| 246 | |||
| 247 | #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ | ||
| 248 | #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ | ||
| 249 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | ||
| 250 | #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ | ||
| 251 | #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ | ||
| 252 | #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ | ||
| 253 | #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ | ||
| 254 | #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ | ||
| 255 | #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ | ||
| 256 | #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ | ||
| 257 | #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ | ||
| 258 | #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ | ||
| 259 | #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ | ||
| 260 | |||
| 261 | #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ | ||
| 262 | #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ | ||
| 263 | #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ | ||
| 264 | #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ | ||
| 265 | #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ | ||
| 266 | #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ | ||
| 267 | #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ | ||
| 268 | #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ | ||
| 269 | #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ | ||
| 270 | #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ | ||
| 271 | #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ | ||
| 272 | #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ | ||
| 273 | #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ | ||
| 274 | |||
| 275 | #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ | ||
| 276 | #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ | ||
| 277 | #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ | ||
| 278 | #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ | ||
| 279 | #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ | ||
| 280 | #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ | ||
| 281 | #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ | ||
| 282 | #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ | ||
| 283 | #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ | ||
| 284 | #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ | ||
| 285 | #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ | ||
| 286 | #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ | ||
| 287 | #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ | ||
| 288 | |||
| 289 | #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ | ||
| 290 | #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ | ||
| 291 | #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ | ||
| 292 | #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ | ||
| 293 | #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ | ||
| 294 | #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ | ||
| 295 | #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ | ||
| 296 | #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ | ||
| 297 | #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ | ||
| 298 | #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ | ||
| 299 | #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ | ||
| 300 | #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ | ||
| 301 | #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ | ||
| 302 | |||
| 303 | #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ | ||
| 304 | #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ | ||
| 305 | #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ | ||
| 306 | #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ | ||
| 307 | #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ | ||
| 308 | #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ | ||
| 309 | #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ | ||
| 310 | #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ | ||
| 311 | #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ | ||
| 312 | #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ | ||
| 313 | #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ | ||
| 314 | #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ | ||
| 315 | #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ | ||
| 316 | |||
| 317 | #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ | ||
| 318 | #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ | ||
| 319 | #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ | ||
| 320 | #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ | ||
| 321 | #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ | ||
| 322 | #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ | ||
| 323 | #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ | ||
| 324 | #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ | ||
| 325 | #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ | ||
| 326 | #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ | ||
| 327 | #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ | ||
| 328 | #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ | ||
| 329 | #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ | ||
| 330 | |||
| 331 | #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ | ||
| 332 | #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ | ||
| 333 | #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ | ||
| 334 | #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ | ||
| 335 | #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ | ||
| 336 | #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ | ||
| 337 | #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ | ||
| 338 | #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ | ||
| 339 | #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ | ||
| 340 | #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ | ||
| 341 | #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ | ||
| 342 | #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ | ||
| 343 | #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ | ||
| 344 | |||
| 345 | #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ | ||
| 346 | #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ | ||
| 347 | #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ | ||
| 348 | #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ | ||
| 349 | #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ | ||
| 350 | #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ | ||
| 351 | #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ | ||
| 352 | #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ | ||
| 353 | #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ | ||
| 354 | #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ | ||
| 355 | #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ | ||
| 356 | #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ | ||
| 357 | #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ | ||
| 358 | |||
| 359 | #define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */ | ||
| 360 | #define MDMA0_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */ | ||
| 361 | #define MDMA0_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */ | ||
| 362 | #define MDMA0_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */ | ||
| 363 | #define MDMA0_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */ | ||
| 364 | #define MDMA0_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */ | ||
| 365 | #define MDMA0_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */ | ||
| 366 | #define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ | ||
| 367 | #define MDMA0_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */ | ||
| 368 | #define MDMA0_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */ | ||
| 369 | #define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */ | ||
| 370 | #define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */ | ||
| 371 | #define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */ | ||
| 372 | |||
| 373 | #define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */ | ||
| 374 | #define MDMA0_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */ | ||
| 375 | #define MDMA0_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */ | ||
| 376 | #define MDMA0_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */ | ||
| 377 | #define MDMA0_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */ | ||
| 378 | #define MDMA0_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */ | ||
| 379 | #define MDMA0_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */ | ||
| 380 | #define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ | ||
| 381 | #define MDMA0_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */ | ||
| 382 | #define MDMA0_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */ | ||
| 383 | #define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */ | ||
| 384 | #define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */ | ||
| 385 | #define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */ | ||
| 386 | |||
| 387 | #define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */ | ||
| 388 | #define MDMA0_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */ | ||
| 389 | #define MDMA0_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */ | ||
| 390 | #define MDMA0_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */ | ||
| 391 | #define MDMA0_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */ | ||
| 392 | #define MDMA0_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */ | ||
| 393 | #define MDMA0_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */ | ||
| 394 | #define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ | ||
| 395 | #define MDMA0_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */ | ||
| 396 | #define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */ | ||
| 397 | #define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */ | ||
| 398 | #define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */ | ||
| 399 | #define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */ | ||
| 400 | |||
| 401 | #define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */ | ||
| 402 | #define MDMA0_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */ | ||
| 403 | #define MDMA0_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */ | ||
| 404 | #define MDMA0_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */ | ||
| 405 | #define MDMA0_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */ | ||
| 406 | #define MDMA0_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */ | ||
| 407 | #define MDMA0_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */ | ||
| 408 | #define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ | ||
| 409 | #define MDMA0_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */ | ||
| 410 | #define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */ | ||
| 411 | #define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */ | ||
| 412 | #define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ | ||
| 413 | #define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ | ||
| 414 | |||
| 415 | |||
| 416 | /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ | ||
| 417 | #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ | ||
| 418 | #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ | ||
| 419 | #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ | ||
| 420 | #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ | ||
| 421 | #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ | ||
| 422 | |||
| 423 | |||
| 424 | /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ | ||
| 425 | #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ | ||
| 426 | #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ | ||
| 427 | #define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ | ||
| 428 | #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ | ||
| 429 | #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ | ||
| 430 | #define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */ | ||
| 431 | #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ | ||
| 432 | #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ | ||
| 433 | #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ | ||
| 434 | #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ | ||
| 435 | #define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */ | ||
| 436 | #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ | ||
| 437 | #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ | ||
| 438 | #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ | ||
| 439 | #define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ | ||
| 440 | #define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ | ||
| 441 | |||
| 442 | #define TWI0_REGBASE TWI0_CLKDIV | ||
| 443 | |||
| 444 | /* the following are for backwards compatibility */ | ||
| 445 | #define TWI0_PRESCALE TWI0_CONTROL | ||
| 446 | #define TWI0_INT_SRC TWI0_INT_STAT | ||
| 447 | #define TWI0_INT_ENABLE TWI0_INT_MASK | ||
| 448 | |||
| 449 | |||
| 450 | /* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ | ||
| 451 | |||
| 452 | /* GPIO Port C Register Names */ | ||
| 453 | #define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */ | ||
| 454 | #define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */ | ||
| 455 | #define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */ | ||
| 456 | #define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */ | ||
| 457 | #define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */ | ||
| 458 | #define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ | ||
| 459 | #define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ | ||
| 460 | |||
| 461 | /* GPIO Port D Register Names */ | ||
| 462 | #define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */ | ||
| 463 | #define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */ | ||
| 464 | #define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */ | ||
| 465 | #define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */ | ||
| 466 | #define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */ | ||
| 467 | #define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ | ||
| 468 | #define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ | ||
| 469 | |||
| 470 | /* GPIO Port E Register Names */ | ||
| 471 | #define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */ | ||
| 472 | #define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */ | ||
| 473 | #define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */ | ||
| 474 | #define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */ | ||
| 475 | #define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */ | ||
| 476 | #define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ | ||
| 477 | #define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ | ||
| 478 | |||
| 479 | /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ | ||
| 480 | |||
| 481 | #define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ | ||
| 482 | #define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */ | ||
| 483 | |||
| 484 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
| 485 | #define DMA1_TCPER DMAC1_TC_PER | ||
| 486 | #define DMA1_TCCNT DMAC1_TC_CNT | ||
| 487 | |||
| 488 | |||
| 489 | /* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */ | ||
| 490 | #define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */ | ||
| 491 | #define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */ | ||
| 492 | #define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */ | ||
| 493 | #define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */ | ||
| 494 | #define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */ | ||
| 495 | #define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */ | ||
| 496 | #define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */ | ||
| 497 | #define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ | ||
| 498 | #define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ | ||
| 499 | #define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ | ||
| 500 | #define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */ | ||
| 501 | #define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ | ||
| 502 | #define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ | ||
| 503 | |||
| 504 | #define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */ | ||
| 505 | #define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */ | ||
| 506 | #define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */ | ||
| 507 | #define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */ | ||
| 508 | #define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */ | ||
| 509 | #define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */ | ||
| 510 | #define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */ | ||
| 511 | #define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ | ||
| 512 | #define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ | ||
| 513 | #define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */ | ||
| 514 | #define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */ | ||
| 515 | #define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ | ||
| 516 | #define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ | ||
| 517 | |||
| 518 | #define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */ | ||
| 519 | #define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */ | ||
| 520 | #define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */ | ||
| 521 | #define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */ | ||
| 522 | #define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */ | ||
| 523 | #define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */ | ||
| 524 | #define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */ | ||
| 525 | #define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ | ||
| 526 | #define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ | ||
| 527 | #define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ | ||
| 528 | #define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */ | ||
| 529 | #define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ | ||
| 530 | #define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ | ||
| 531 | |||
| 532 | #define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */ | ||
| 533 | #define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */ | ||
| 534 | #define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */ | ||
| 535 | #define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */ | ||
| 536 | #define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */ | ||
| 537 | #define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */ | ||
| 538 | #define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */ | ||
| 539 | #define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ | ||
| 540 | #define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ | ||
| 541 | #define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */ | ||
| 542 | #define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */ | ||
| 543 | #define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ | ||
| 544 | #define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ | ||
| 545 | |||
| 546 | #define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */ | ||
| 547 | #define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */ | ||
| 548 | #define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */ | ||
| 549 | #define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */ | ||
| 550 | #define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */ | ||
| 551 | #define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */ | ||
| 552 | #define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */ | ||
| 553 | #define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ | ||
| 554 | #define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ | ||
| 555 | #define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ | ||
| 556 | #define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */ | ||
| 557 | #define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ | ||
| 558 | #define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ | ||
| 559 | |||
| 560 | #define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */ | ||
| 561 | #define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */ | ||
| 562 | #define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */ | ||
| 563 | #define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */ | ||
| 564 | #define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */ | ||
| 565 | #define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */ | ||
| 566 | #define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */ | ||
| 567 | #define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ | ||
| 568 | #define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ | ||
| 569 | #define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */ | ||
| 570 | #define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */ | ||
| 571 | #define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ | ||
| 572 | #define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ | ||
| 573 | |||
| 574 | #define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */ | ||
| 575 | #define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */ | ||
| 576 | #define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */ | ||
| 577 | #define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */ | ||
| 578 | #define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */ | ||
| 579 | #define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */ | ||
| 580 | #define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */ | ||
| 581 | #define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ | ||
| 582 | #define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ | ||
| 583 | #define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ | ||
| 584 | #define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */ | ||
| 585 | #define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ | ||
| 586 | #define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ | ||
| 587 | |||
| 588 | #define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */ | ||
| 589 | #define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */ | ||
| 590 | #define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */ | ||
| 591 | #define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */ | ||
| 592 | #define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */ | ||
| 593 | #define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */ | ||
| 594 | #define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */ | ||
| 595 | #define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ | ||
| 596 | #define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ | ||
| 597 | #define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ | ||
| 598 | #define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */ | ||
| 599 | #define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ | ||
| 600 | #define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ | ||
| 601 | |||
| 602 | #define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */ | ||
| 603 | #define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */ | ||
| 604 | #define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */ | ||
| 605 | #define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */ | ||
| 606 | #define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */ | ||
| 607 | #define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */ | ||
| 608 | #define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */ | ||
| 609 | #define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ | ||
| 610 | #define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ | ||
| 611 | #define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */ | ||
| 612 | #define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */ | ||
| 613 | #define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ | ||
| 614 | #define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ | ||
| 615 | |||
| 616 | #define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */ | ||
| 617 | #define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */ | ||
| 618 | #define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */ | ||
| 619 | #define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */ | ||
| 620 | #define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */ | ||
| 621 | #define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */ | ||
| 622 | #define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */ | ||
| 623 | #define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ | ||
| 624 | #define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ | ||
| 625 | #define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ | ||
| 626 | #define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */ | ||
| 627 | #define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ | ||
| 628 | #define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ | ||
| 629 | |||
| 630 | #define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */ | ||
| 631 | #define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */ | ||
| 632 | #define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */ | ||
| 633 | #define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */ | ||
| 634 | #define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */ | ||
| 635 | #define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */ | ||
| 636 | #define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */ | ||
| 637 | #define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ | ||
| 638 | #define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ | ||
| 639 | #define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */ | ||
| 640 | #define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */ | ||
| 641 | #define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ | ||
| 642 | #define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ | ||
| 643 | |||
| 644 | #define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */ | ||
| 645 | #define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */ | ||
| 646 | #define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */ | ||
| 647 | #define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */ | ||
| 648 | #define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */ | ||
| 649 | #define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */ | ||
| 650 | #define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */ | ||
| 651 | #define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ | ||
| 652 | #define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ | ||
| 653 | #define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */ | ||
| 654 | #define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */ | ||
| 655 | #define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ | ||
| 656 | #define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ | ||
| 657 | |||
| 658 | #define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */ | ||
| 659 | #define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */ | ||
| 660 | #define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */ | ||
| 661 | #define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */ | ||
| 662 | #define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */ | ||
| 663 | #define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */ | ||
| 664 | #define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */ | ||
| 665 | #define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ | ||
| 666 | #define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ | ||
| 667 | #define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ | ||
| 668 | #define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */ | ||
| 669 | #define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ | ||
| 670 | #define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ | ||
| 671 | |||
| 672 | #define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */ | ||
| 673 | #define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */ | ||
| 674 | #define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */ | ||
| 675 | #define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */ | ||
| 676 | #define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */ | ||
| 677 | #define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */ | ||
| 678 | #define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */ | ||
| 679 | #define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ | ||
| 680 | #define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ | ||
| 681 | #define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */ | ||
| 682 | #define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */ | ||
| 683 | #define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ | ||
| 684 | #define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ | ||
| 685 | |||
| 686 | #define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */ | ||
| 687 | #define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */ | ||
| 688 | #define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */ | ||
| 689 | #define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */ | ||
| 690 | #define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */ | ||
| 691 | #define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */ | ||
| 692 | #define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */ | ||
| 693 | #define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ | ||
| 694 | #define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ | ||
| 695 | #define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */ | ||
| 696 | #define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */ | ||
| 697 | #define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ | ||
| 698 | #define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ | ||
| 699 | |||
| 700 | #define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */ | ||
| 701 | #define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */ | ||
| 702 | #define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */ | ||
| 703 | #define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */ | ||
| 704 | #define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */ | ||
| 705 | #define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */ | ||
| 706 | #define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */ | ||
| 707 | #define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ | ||
| 708 | #define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ | ||
| 709 | #define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */ | ||
| 710 | #define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */ | ||
| 711 | #define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ | ||
| 712 | #define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ | ||
| 713 | |||
| 714 | |||
| 715 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ | ||
| 716 | #define UART1_THR 0xFFC02000 /* Transmit Holding register */ | ||
| 717 | #define UART1_RBR 0xFFC02000 /* Receive Buffer register */ | ||
| 718 | #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ | ||
| 719 | #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ | ||
| 720 | #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ | ||
| 721 | #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ | ||
| 722 | #define UART1_LCR 0xFFC0200C /* Line Control Register */ | ||
| 723 | #define UART1_MCR 0xFFC02010 /* Modem Control Register */ | ||
| 724 | #define UART1_LSR 0xFFC02014 /* Line Status Register */ | ||
| 725 | #define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ | ||
| 726 | #define UART1_GCTL 0xFFC02024 /* Global Control Register */ | ||
| 727 | |||
| 728 | |||
| 729 | /* UART2 Controller (0xFFC02100 - 0xFFC021FF) */ | ||
| 730 | #define UART2_THR 0xFFC02100 /* Transmit Holding register */ | ||
| 731 | #define UART2_RBR 0xFFC02100 /* Receive Buffer register */ | ||
| 732 | #define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */ | ||
| 733 | #define UART2_IER 0xFFC02104 /* Interrupt Enable Register */ | ||
| 734 | #define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */ | ||
| 735 | #define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */ | ||
| 736 | #define UART2_LCR 0xFFC0210C /* Line Control Register */ | ||
| 737 | #define UART2_MCR 0xFFC02110 /* Modem Control Register */ | ||
| 738 | #define UART2_LSR 0xFFC02114 /* Line Status Register */ | ||
| 739 | #define UART2_SCR 0xFFC0211C /* SCR Scratch Register */ | ||
| 740 | #define UART2_GCTL 0xFFC02124 /* Global Control Register */ | ||
| 741 | |||
| 742 | |||
| 743 | /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ | ||
| 744 | #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ | ||
| 745 | #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ | ||
| 746 | #define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ | ||
| 747 | #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ | ||
| 748 | #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ | ||
| 749 | #define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */ | ||
| 750 | #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ | ||
| 751 | #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ | ||
| 752 | #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ | ||
| 753 | #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ | ||
| 754 | #define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */ | ||
| 755 | #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ | ||
| 756 | #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ | ||
| 757 | #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ | ||
| 758 | #define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ | ||
| 759 | #define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ | ||
| 760 | #define TWI1_REGBASE TWI1_CLKDIV | ||
| 761 | |||
| 762 | |||
| 763 | /* the following are for backwards compatibility */ | ||
| 764 | #define TWI1_PRESCALE TWI1_CONTROL | ||
| 765 | #define TWI1_INT_SRC TWI1_INT_STAT | ||
| 766 | #define TWI1_INT_ENABLE TWI1_INT_MASK | ||
| 767 | |||
| 768 | |||
| 769 | /* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */ | ||
| 770 | #define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ | ||
| 771 | #define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */ | ||
| 772 | #define SPI1_STAT 0xFFC02308 /* SPI1 Status register */ | ||
| 773 | #define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ | ||
| 774 | #define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ | ||
| 775 | #define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */ | ||
| 776 | #define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */ | ||
| 777 | #define SPI1_REGBASE SPI1_CTL | ||
| 778 | |||
| 779 | /* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */ | ||
| 780 | #define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ | ||
| 781 | #define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */ | ||
| 782 | #define SPI2_STAT 0xFFC02408 /* SPI2 Status register */ | ||
| 783 | #define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ | ||
| 784 | #define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ | ||
| 785 | #define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */ | ||
| 786 | #define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */ | ||
| 787 | #define SPI2_REGBASE SPI2_CTL | ||
| 788 | |||
| 789 | /* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */ | ||
| 790 | #define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ | ||
| 791 | #define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ | ||
| 792 | #define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */ | ||
| 793 | #define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */ | ||
| 794 | #define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */ | ||
| 795 | #define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */ | ||
| 796 | #define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */ | ||
| 797 | #define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */ | ||
| 798 | #define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ | ||
| 799 | #define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */ | ||
| 800 | #define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ | ||
| 801 | #define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ | ||
| 802 | #define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */ | ||
| 803 | #define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */ | ||
| 804 | #define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */ | ||
| 805 | #define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */ | ||
| 806 | #define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */ | ||
| 807 | #define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */ | ||
| 808 | #define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ | ||
| 809 | #define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */ | ||
| 810 | #define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */ | ||
| 811 | #define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */ | ||
| 812 | |||
| 813 | |||
| 814 | /* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */ | ||
| 815 | #define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ | ||
| 816 | #define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ | ||
| 817 | #define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */ | ||
| 818 | #define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */ | ||
| 819 | #define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */ | ||
| 820 | #define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */ | ||
| 821 | #define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */ | ||
| 822 | #define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */ | ||
| 823 | #define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ | ||
| 824 | #define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */ | ||
| 825 | #define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ | ||
| 826 | #define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ | ||
| 827 | #define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */ | ||
| 828 | #define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */ | ||
| 829 | #define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */ | ||
| 830 | #define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */ | ||
| 831 | #define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */ | ||
| 832 | #define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */ | ||
| 833 | #define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ | ||
| 834 | #define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */ | ||
| 835 | #define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */ | ||
| 836 | #define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */ | ||
| 837 | |||
| 838 | |||
| 839 | /* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */ | ||
| 840 | |||
| 841 | #define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */ | ||
| 842 | #define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */ | ||
| 843 | |||
| 844 | #define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */ | ||
| 845 | #define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */ | ||
| 846 | |||
| 847 | #define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */ | ||
| 848 | #define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */ | ||
| 849 | |||
| 850 | #define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */ | ||
| 851 | #define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */ | ||
| 852 | |||
| 853 | #define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */ | ||
| 854 | #define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */ | ||
| 855 | |||
| 856 | #define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */ | ||
| 857 | #define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */ | ||
| 858 | |||
| 859 | #define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */ | ||
| 860 | #define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */ | ||
| 861 | #define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */ | ||
| 862 | |||
| 863 | #define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */ | ||
| 864 | #define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */ | ||
| 865 | #define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */ | ||
| 866 | #define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */ | ||
| 867 | #define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */ | ||
| 868 | #define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */ | ||
| 869 | #define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */ | ||
| 870 | #define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */ | ||
| 871 | #define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */ | ||
| 872 | #define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */ | ||
| 873 | #define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */ | ||
| 874 | #define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */ | ||
| 875 | #define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */ | ||
| 876 | #define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */ | ||
| 877 | #define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */ | ||
| 878 | |||
| 879 | #define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ | ||
| 880 | #define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */ | ||
| 881 | #define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ | ||
| 882 | #define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ | ||
| 883 | #define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ | ||
| 884 | #define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */ | ||
| 885 | #define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ | ||
| 886 | #define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ | ||
| 887 | |||
| 888 | #define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */ | ||
| 889 | #define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */ | ||
| 890 | #define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */ | ||
| 891 | #define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */ | ||
| 892 | #define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */ | ||
| 893 | |||
| 894 | #define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */ | ||
| 895 | #define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */ | ||
| 896 | #define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */ | ||
| 897 | #define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */ | ||
| 898 | #define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */ | ||
| 899 | |||
| 900 | #define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */ | ||
| 901 | #define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */ | ||
| 902 | #define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */ | ||
| 903 | #define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */ | ||
| 904 | #define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */ | ||
| 905 | |||
| 906 | #define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */ | ||
| 907 | #define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */ | ||
| 908 | #define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */ | ||
| 909 | #define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */ | ||
| 910 | #define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */ | ||
| 911 | |||
| 912 | #define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */ | ||
| 913 | #define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */ | ||
| 914 | #define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */ | ||
| 915 | #define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */ | ||
| 916 | #define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */ | ||
| 917 | |||
| 918 | #define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */ | ||
| 919 | #define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */ | ||
| 920 | #define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */ | ||
| 921 | #define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */ | ||
| 922 | #define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */ | ||
| 923 | |||
| 924 | #define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */ | ||
| 925 | #define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */ | ||
| 926 | #define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */ | ||
| 927 | #define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */ | ||
| 928 | #define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */ | ||
| 929 | |||
| 930 | #define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */ | ||
| 931 | #define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */ | ||
| 932 | #define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */ | ||
| 933 | #define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */ | ||
| 934 | #define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */ | ||
| 935 | |||
| 936 | #define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */ | ||
| 937 | #define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */ | ||
| 938 | #define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */ | ||
| 939 | #define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */ | ||
| 940 | #define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */ | ||
| 941 | |||
| 942 | #define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */ | ||
| 943 | #define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */ | ||
| 944 | #define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */ | ||
| 945 | #define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */ | ||
| 946 | #define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */ | ||
| 947 | |||
| 948 | #define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */ | ||
| 949 | #define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */ | ||
| 950 | |||
| 951 | #define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */ | ||
| 952 | #define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */ | ||
| 953 | #define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */ | ||
| 954 | #define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */ | ||
| 955 | |||
| 956 | #define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */ | ||
| 957 | #define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */ | ||
| 958 | |||
| 959 | #define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */ | ||
| 960 | #define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */ | ||
| 961 | #define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */ | ||
| 962 | #define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */ | ||
| 963 | #define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */ | ||
| 964 | #define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */ | ||
| 965 | #define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */ | ||
| 966 | #define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */ | ||
| 967 | #define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */ | ||
| 968 | #define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */ | ||
| 969 | #define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */ | ||
| 970 | #define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */ | ||
| 971 | #define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */ | ||
| 972 | #define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */ | ||
| 973 | #define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */ | ||
| 974 | |||
| 975 | #define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */ | ||
| 976 | #define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */ | ||
| 977 | #define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */ | ||
| 978 | |||
| 979 | |||
| 980 | /* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ | ||
| 981 | /* For Mailboxes 0-15 */ | ||
| 982 | #define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ | ||
| 983 | #define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ | ||
| 984 | #define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ | ||
| 985 | #define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ | ||
| 986 | #define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ | ||
| 987 | #define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ | ||
| 988 | #define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ | ||
| 989 | #define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ | ||
| 990 | #define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ | ||
| 991 | #define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ | ||
| 992 | #define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ | ||
| 993 | #define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ | ||
| 994 | #define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ | ||
| 995 | |||
| 996 | /* For Mailboxes 16-31 */ | ||
| 997 | #define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ | ||
| 998 | #define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ | ||
| 999 | #define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ | ||
| 1000 | #define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ | ||
| 1001 | #define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ | ||
| 1002 | #define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ | ||
| 1003 | #define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ | ||
| 1004 | #define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ | ||
| 1005 | #define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ | ||
| 1006 | #define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ | ||
| 1007 | #define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ | ||
| 1008 | #define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ | ||
| 1009 | #define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ | ||
| 1010 | |||
| 1011 | #define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ | ||
| 1012 | #define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ | ||
| 1013 | |||
| 1014 | #define CAN_DEBUG 0xFFC02A88 /* Debug Register */ | ||
| 1015 | /* the following is for backwards compatibility */ | ||
| 1016 | #define CAN_CNF CAN_DEBUG | ||
| 1017 | |||
| 1018 | #define CAN_STATUS 0xFFC02A8C /* Global Status Register */ | ||
| 1019 | #define CAN_CEC 0xFFC02A90 /* Error Counter Register */ | ||
| 1020 | #define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ | ||
| 1021 | #define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ | ||
| 1022 | #define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ | ||
| 1023 | #define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ | ||
| 1024 | #define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ | ||
| 1025 | #define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ | ||
| 1026 | #define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ | ||
| 1027 | #define CAN_ESR 0xFFC02AB4 /* Error Status Register */ | ||
| 1028 | #define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ | ||
| 1029 | #define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */ | ||
| 1030 | #define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ | ||
| 1031 | |||
| 1032 | /* Mailbox Acceptance Masks */ | ||
| 1033 | #define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ | ||
| 1034 | #define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ | ||
| 1035 | #define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ | ||
| 1036 | #define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ | ||
| 1037 | #define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ | ||
| 1038 | #define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ | ||
| 1039 | #define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ | ||
| 1040 | #define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ | ||
| 1041 | #define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ | ||
| 1042 | #define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ | ||
| 1043 | #define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ | ||
| 1044 | #define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ | ||
| 1045 | #define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ | ||
| 1046 | #define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ | ||
| 1047 | #define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ | ||
| 1048 | #define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ | ||
| 1049 | #define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ | ||
| 1050 | #define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ | ||
| 1051 | #define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ | ||
| 1052 | #define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ | ||
| 1053 | #define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ | ||
| 1054 | #define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ | ||
| 1055 | #define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ | ||
| 1056 | #define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ | ||
| 1057 | #define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ | ||
| 1058 | #define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ | ||
| 1059 | #define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ | ||
| 1060 | #define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ | ||
| 1061 | #define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ | ||
| 1062 | #define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ | ||
| 1063 | #define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ | ||
| 1064 | #define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ | ||
| 1065 | |||
| 1066 | #define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ | ||
| 1067 | #define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ | ||
| 1068 | #define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ | ||
| 1069 | #define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ | ||
| 1070 | #define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ | ||
| 1071 | #define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ | ||
| 1072 | #define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ | ||
| 1073 | #define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ | ||
| 1074 | #define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ | ||
| 1075 | #define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ | ||
| 1076 | #define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ | ||
| 1077 | #define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ | ||
| 1078 | #define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ | ||
| 1079 | #define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ | ||
| 1080 | #define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ | ||
| 1081 | #define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ | ||
| 1082 | #define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ | ||
| 1083 | #define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ | ||
| 1084 | #define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ | ||
| 1085 | #define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ | ||
| 1086 | #define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ | ||
| 1087 | #define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ | ||
| 1088 | #define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ | ||
| 1089 | #define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ | ||
| 1090 | #define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ | ||
| 1091 | #define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ | ||
| 1092 | #define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ | ||
| 1093 | #define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ | ||
| 1094 | #define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ | ||
| 1095 | #define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ | ||
| 1096 | #define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ | ||
| 1097 | #define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ | ||
| 1098 | |||
| 1099 | /* CAN Acceptance Mask Macros */ | ||
| 1100 | #define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) | ||
| 1101 | #define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) | ||
| 1102 | |||
| 1103 | /* Mailbox Registers */ | ||
| 1104 | #define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ | ||
| 1105 | #define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ | ||
| 1106 | #define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ | ||
| 1107 | #define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ | ||
| 1108 | #define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ | ||
| 1109 | #define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ | ||
| 1110 | #define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ | ||
| 1111 | #define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ | ||
| 1112 | |||
| 1113 | #define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ | ||
| 1114 | #define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ | ||
| 1115 | #define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ | ||
| 1116 | #define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ | ||
| 1117 | #define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ | ||
| 1118 | #define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ | ||
| 1119 | #define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ | ||
| 1120 | #define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ | ||
| 1121 | |||
| 1122 | #define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ | ||
| 1123 | #define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ | ||
| 1124 | #define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ | ||
| 1125 | #define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ | ||
| 1126 | #define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ | ||
| 1127 | #define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ | ||
| 1128 | #define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ | ||
| 1129 | #define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ | ||
| 1130 | |||
| 1131 | #define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ | ||
| 1132 | #define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ | ||
| 1133 | #define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ | ||
| 1134 | #define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ | ||
| 1135 | #define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ | ||
| 1136 | #define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ | ||
| 1137 | #define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ | ||
| 1138 | #define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ | ||
| 1139 | |||
| 1140 | #define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ | ||
| 1141 | #define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ | ||
| 1142 | #define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ | ||
| 1143 | #define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ | ||
| 1144 | #define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ | ||
| 1145 | #define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ | ||
| 1146 | #define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ | ||
| 1147 | #define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ | ||
| 1148 | |||
| 1149 | #define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ | ||
| 1150 | #define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ | ||
| 1151 | #define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ | ||
| 1152 | #define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ | ||
| 1153 | #define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ | ||
| 1154 | #define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ | ||
| 1155 | #define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ | ||
| 1156 | #define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ | ||
| 1157 | |||
| 1158 | #define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ | ||
| 1159 | #define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ | ||
| 1160 | #define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ | ||
| 1161 | #define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ | ||
| 1162 | #define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ | ||
| 1163 | #define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ | ||
| 1164 | #define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ | ||
| 1165 | #define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ | ||
| 1166 | |||
| 1167 | #define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ | ||
| 1168 | #define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ | ||
| 1169 | #define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ | ||
| 1170 | #define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ | ||
| 1171 | #define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ | ||
| 1172 | #define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ | ||
| 1173 | #define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ | ||
| 1174 | #define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ | ||
| 1175 | |||
| 1176 | #define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ | ||
| 1177 | #define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ | ||
| 1178 | #define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ | ||
| 1179 | #define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ | ||
| 1180 | #define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ | ||
| 1181 | #define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ | ||
| 1182 | #define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ | ||
| 1183 | #define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ | ||
| 1184 | |||
| 1185 | #define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ | ||
| 1186 | #define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ | ||
| 1187 | #define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ | ||
| 1188 | #define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ | ||
| 1189 | #define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ | ||
| 1190 | #define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ | ||
| 1191 | #define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ | ||
| 1192 | #define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ | ||
| 1193 | |||
| 1194 | #define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ | ||
| 1195 | #define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ | ||
| 1196 | #define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ | ||
| 1197 | #define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ | ||
| 1198 | #define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ | ||
| 1199 | #define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ | ||
| 1200 | #define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ | ||
| 1201 | #define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ | ||
| 1202 | |||
| 1203 | #define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ | ||
| 1204 | #define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ | ||
| 1205 | #define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ | ||
| 1206 | #define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ | ||
| 1207 | #define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ | ||
| 1208 | #define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ | ||
| 1209 | #define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ | ||
| 1210 | #define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ | ||
| 1211 | |||
| 1212 | #define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ | ||
| 1213 | #define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ | ||
| 1214 | #define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ | ||
| 1215 | #define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ | ||
| 1216 | #define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ | ||
| 1217 | #define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ | ||
| 1218 | #define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ | ||
| 1219 | #define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ | ||
| 1220 | |||
| 1221 | #define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ | ||
| 1222 | #define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ | ||
| 1223 | #define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ | ||
| 1224 | #define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ | ||
| 1225 | #define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ | ||
| 1226 | #define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ | ||
| 1227 | #define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ | ||
| 1228 | #define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ | ||
| 1229 | |||
| 1230 | #define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ | ||
| 1231 | #define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ | ||
| 1232 | #define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ | ||
| 1233 | #define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ | ||
| 1234 | #define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ | ||
| 1235 | #define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ | ||
| 1236 | #define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ | ||
| 1237 | #define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ | ||
| 1238 | |||
| 1239 | #define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ | ||
| 1240 | #define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ | ||
| 1241 | #define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ | ||
| 1242 | #define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ | ||
| 1243 | #define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ | ||
| 1244 | #define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ | ||
| 1245 | #define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ | ||
| 1246 | #define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ | ||
| 1247 | |||
| 1248 | #define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ | ||
| 1249 | #define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ | ||
| 1250 | #define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ | ||
| 1251 | #define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ | ||
| 1252 | #define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ | ||
| 1253 | #define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ | ||
| 1254 | #define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ | ||
| 1255 | #define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ | ||
| 1256 | |||
| 1257 | #define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ | ||
| 1258 | #define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ | ||
| 1259 | #define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ | ||
| 1260 | #define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ | ||
| 1261 | #define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ | ||
| 1262 | #define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ | ||
| 1263 | #define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ | ||
| 1264 | #define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ | ||
| 1265 | |||
| 1266 | #define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ | ||
| 1267 | #define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ | ||
| 1268 | #define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ | ||
| 1269 | #define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ | ||
| 1270 | #define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ | ||
| 1271 | #define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ | ||
| 1272 | #define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ | ||
| 1273 | #define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ | ||
| 1274 | |||
| 1275 | #define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ | ||
| 1276 | #define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ | ||
| 1277 | #define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ | ||
| 1278 | #define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ | ||
| 1279 | #define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ | ||
| 1280 | #define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ | ||
| 1281 | #define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ | ||
| 1282 | #define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ | ||
| 1283 | |||
| 1284 | #define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ | ||
| 1285 | #define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ | ||
| 1286 | #define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ | ||
| 1287 | #define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ | ||
| 1288 | #define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ | ||
| 1289 | #define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ | ||
| 1290 | #define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ | ||
| 1291 | #define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ | ||
| 1292 | |||
| 1293 | #define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ | ||
| 1294 | #define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ | ||
| 1295 | #define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ | ||
| 1296 | #define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ | ||
| 1297 | #define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ | ||
| 1298 | #define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ | ||
| 1299 | #define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ | ||
| 1300 | #define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ | ||
| 1301 | |||
| 1302 | #define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ | ||
| 1303 | #define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ | ||
| 1304 | #define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ | ||
| 1305 | #define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ | ||
| 1306 | #define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ | ||
| 1307 | #define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ | ||
| 1308 | #define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ | ||
| 1309 | #define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ | ||
| 1310 | |||
| 1311 | #define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ | ||
| 1312 | #define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ | ||
| 1313 | #define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ | ||
| 1314 | #define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ | ||
| 1315 | #define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ | ||
| 1316 | #define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ | ||
| 1317 | #define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ | ||
| 1318 | #define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ | ||
| 1319 | |||
| 1320 | #define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ | ||
| 1321 | #define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ | ||
| 1322 | #define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ | ||
| 1323 | #define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ | ||
| 1324 | #define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ | ||
| 1325 | #define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ | ||
| 1326 | #define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ | ||
| 1327 | #define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ | ||
| 1328 | |||
| 1329 | #define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ | ||
| 1330 | #define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ | ||
| 1331 | #define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ | ||
| 1332 | #define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ | ||
| 1333 | #define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ | ||
| 1334 | #define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ | ||
| 1335 | #define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ | ||
| 1336 | #define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ | ||
| 1337 | |||
| 1338 | #define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ | ||
| 1339 | #define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ | ||
| 1340 | #define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ | ||
| 1341 | #define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ | ||
| 1342 | #define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ | ||
| 1343 | #define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ | ||
| 1344 | #define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ | ||
| 1345 | #define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ | ||
| 1346 | |||
| 1347 | #define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ | ||
| 1348 | #define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ | ||
| 1349 | #define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ | ||
| 1350 | #define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ | ||
| 1351 | #define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ | ||
| 1352 | #define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ | ||
| 1353 | #define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ | ||
| 1354 | #define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ | ||
| 1355 | |||
| 1356 | #define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ | ||
| 1357 | #define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ | ||
| 1358 | #define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ | ||
| 1359 | #define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ | ||
| 1360 | #define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ | ||
| 1361 | #define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ | ||
| 1362 | #define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ | ||
| 1363 | #define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ | ||
| 1364 | |||
| 1365 | #define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ | ||
| 1366 | #define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ | ||
| 1367 | #define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ | ||
| 1368 | #define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ | ||
| 1369 | #define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ | ||
| 1370 | #define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ | ||
| 1371 | #define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ | ||
| 1372 | #define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ | ||
| 1373 | |||
| 1374 | #define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ | ||
| 1375 | #define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ | ||
| 1376 | #define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ | ||
| 1377 | #define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ | ||
| 1378 | #define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ | ||
| 1379 | #define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ | ||
| 1380 | #define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ | ||
| 1381 | #define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ | ||
| 1382 | |||
| 1383 | #define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ | ||
| 1384 | #define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ | ||
| 1385 | #define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ | ||
| 1386 | #define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ | ||
| 1387 | #define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ | ||
| 1388 | #define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ | ||
| 1389 | #define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ | ||
| 1390 | #define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ | ||
| 1391 | |||
| 1392 | /* CAN Mailbox Area Macros */ | ||
| 1393 | #define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) | ||
| 1394 | #define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) | ||
| 1395 | #define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) | ||
| 1396 | #define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) | ||
| 1397 | #define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) | ||
| 1398 | #define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) | ||
| 1399 | #define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) | ||
| 1400 | #define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) | ||
| 1401 | |||
| 1402 | |||
| 1403 | /*********************************************************************************** */ | ||
| 1404 | /* System MMR Register Bits and Macros */ | ||
| 1405 | /******************************************************************************* */ | ||
| 1406 | |||
| 1407 | /* ********************* PLL AND RESET MASKS ************************ */ | ||
| 1408 | /* PLL_CTL Masks */ | ||
| 1409 | #define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */ | ||
| 1410 | #define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */ | ||
| 1411 | #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ | ||
| 1412 | #define PLL_OFF 0x0002 /* Shut off PLL clocks */ | ||
| 1413 | |||
| 1414 | #define STOPCK 0x0008 /* Core Clock Off */ | ||
| 1415 | #define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */ | ||
| 1416 | #define IN_DELAY 0x0014 /* EBIU Input Delay Select */ | ||
| 1417 | #define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */ | ||
| 1418 | #define BYPASS 0x0100 /* Bypass the PLL */ | ||
| 1419 | #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ | ||
| 1420 | |||
| 1421 | /* PLL_CTL Macros */ | ||
| 1422 | #ifdef _MISRA_RULES | ||
| 1423 | #define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ | ||
| 1424 | #define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6) | ||
| 1425 | #define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2)) | ||
| 1426 | #else | ||
| 1427 | #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ | ||
| 1428 | #define SET_OUT_DELAY(x) (((x)&0x03) << 0x6) | ||
| 1429 | #define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2)) | ||
| 1430 | #endif /* _MISRA_RULES */ | ||
| 1431 | |||
| 1432 | /* PLL_DIV Masks */ | ||
| 1433 | #define SSEL 0x000F /* System Select */ | ||
| 1434 | #define CSEL 0x0030 /* Core Select */ | ||
| 1435 | #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ | ||
| 1436 | #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ | ||
| 1437 | #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ | ||
| 1438 | #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ | ||
| 1439 | |||
| 1440 | #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ | ||
| 1441 | |||
| 1442 | /* PLL_DIV Macros */ | ||
| 1443 | #ifdef _MISRA_RULES | ||
| 1444 | #define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | ||
| 1445 | #else | ||
| 1446 | #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ | ||
| 1447 | #endif /* _MISRA_RULES */ | ||
| 1448 | |||
| 1449 | /* PLL_STAT Masks */ | ||
| 1450 | #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ | ||
| 1451 | #define FULL_ON 0x0002 /* Processor In Full On Mode */ | ||
| 1452 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | ||
| 1453 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | ||
| 1454 | |||
| 1455 | /* VR_CTL Masks */ | ||
| 1456 | #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ | ||
| 1457 | #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ | ||
| 1458 | #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ | ||
| 1459 | #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ | ||
| 1460 | #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ | ||
| 1461 | |||
| 1462 | #define GAIN 0x000C /* Voltage Level Gain */ | ||
| 1463 | #define GAIN_5 0x0000 /* GAIN = 5 */ | ||
| 1464 | #define GAIN_10 0x0004 /* GAIN = 10 */ | ||
| 1465 | #define GAIN_20 0x0008 /* GAIN = 20 */ | ||
| 1466 | #define GAIN_50 0x000C /* GAIN = 50 */ | ||
| 1467 | |||
| 1468 | #define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */ | ||
| 1469 | #define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */ | ||
| 1470 | #define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */ | ||
| 1471 | #define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */ | ||
| 1472 | #define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */ | ||
| 1473 | #define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */ | ||
| 1474 | #define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */ | ||
| 1475 | #define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */ | ||
| 1476 | |||
| 1477 | #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ | ||
| 1478 | #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ | ||
| 1479 | #define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ | ||
| 1480 | #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ | ||
| 1481 | |||
| 1482 | /* SWRST Mask */ | ||
| 1483 | #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ | ||
| 1484 | #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ | ||
| 1485 | #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ | ||
| 1486 | #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ | ||
| 1487 | #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ | ||
| 1488 | |||
| 1489 | /* SYSCR Masks */ | ||
| 1490 | #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ | ||
| 1491 | #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ | ||
| 1492 | |||
| 1493 | |||
| 1494 | /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ | ||
| 1495 | |||
| 1496 | /* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */ | ||
| 1497 | #define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */ | ||
| 1498 | #define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */ | ||
| 1499 | #define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */ | ||
| 1500 | #define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */ | ||
| 1501 | #define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */ | ||
| 1502 | #define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */ | ||
| 1503 | #define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */ | ||
| 1504 | #define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */ | ||
| 1505 | #define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */ | ||
| 1506 | #define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */ | ||
| 1507 | #define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */ | ||
| 1508 | #define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */ | ||
| 1509 | #define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */ | ||
| 1510 | #define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */ | ||
| 1511 | #define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */ | ||
| 1512 | #define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */ | ||
| 1513 | #define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */ | ||
| 1514 | #define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */ | ||
| 1515 | #define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */ | ||
| 1516 | #define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */ | ||
| 1517 | #define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */ | ||
| 1518 | #define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */ | ||
| 1519 | #define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */ | ||
| 1520 | #define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */ | ||
| 1521 | #define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */ | ||
| 1522 | #define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */ | ||
| 1523 | #define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */ | ||
| 1524 | #define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */ | ||
| 1525 | #define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */ | ||
| 1526 | #define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */ | ||
| 1527 | #define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */ | ||
| 1528 | #define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */ | ||
| 1529 | |||
| 1530 | /* the following are for backwards compatibility */ | ||
| 1531 | #define DMA0_ERR_IRQ DMAC0_ERR_IRQ | ||
| 1532 | #define DMA1_ERR_IRQ DMAC1_ERR_IRQ | ||
| 1533 | |||
| 1534 | |||
| 1535 | /* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */ | ||
| 1536 | #define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */ | ||
| 1537 | #define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */ | ||
| 1538 | #define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */ | ||
| 1539 | #define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */ | ||
| 1540 | #define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */ | ||
| 1541 | #define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */ | ||
| 1542 | #define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */ | ||
| 1543 | #define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */ | ||
| 1544 | #define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */ | ||
| 1545 | #define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */ | ||
| 1546 | #define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */ | ||
| 1547 | #define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */ | ||
| 1548 | #define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */ | ||
| 1549 | #define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */ | ||
| 1550 | #define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */ | ||
| 1551 | #define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */ | ||
| 1552 | #define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */ | ||
| 1553 | #define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */ | ||
| 1554 | #define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */ | ||
| 1555 | #define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */ | ||
| 1556 | #define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */ | ||
| 1557 | #define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */ | ||
| 1558 | |||
| 1559 | /* the following are for backwards compatibility */ | ||
| 1560 | #define MDMA0_IRQ MDMA1_0_IRQ | ||
| 1561 | #define MDMA1_IRQ MDMA1_1_IRQ | ||
| 1562 | |||
| 1563 | #ifdef _MISRA_RULES | ||
| 1564 | #define _MF15 0xFu | ||
| 1565 | #define _MF7 7u | ||
| 1566 | #else | ||
| 1567 | #define _MF15 0xF | ||
| 1568 | #define _MF7 7 | ||
| 1569 | #endif /* _MISRA_RULES */ | ||
| 1570 | |||
| 1571 | /* SIC_IMASKx Masks */ | ||
| 1572 | #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ | ||
| 1573 | #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ | ||
| 1574 | #ifdef _MISRA_RULES | ||
| 1575 | #define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */ | ||
| 1576 | #define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */ | ||
| 1577 | #else | ||
| 1578 | #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ | ||
| 1579 | #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ | ||
| 1580 | #endif /* _MISRA_RULES */ | ||
| 1581 | |||
| 1582 | /* SIC_IWRx Masks */ | ||
| 1583 | #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ | ||
| 1584 | #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ | ||
| 1585 | #ifdef _MISRA_RULES | ||
| 1586 | #define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */ | ||
| 1587 | #define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */ | ||
| 1588 | #else | ||
| 1589 | #define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ | ||
| 1590 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ | ||
| 1591 | #endif /* _MISRA_RULES */ | ||
| 1592 | |||
| 1593 | |||
| 1594 | /* ********* WATCHDOG TIMER MASKS ******************** */ | ||
| 1595 | /* Watchdog Timer WDOG_CTL Register Masks */ | ||
| 1596 | #ifdef _MISRA_RULES | ||
| 1597 | #define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */ | ||
| 1598 | #else | ||
| 1599 | #define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ | ||
| 1600 | #endif /* _MISRA_RULES */ | ||
| 1601 | #define WDEV_RESET 0x0000 /* generate reset event on roll over */ | ||
| 1602 | #define WDEV_NMI 0x0002 /* generate NMI event on roll over */ | ||
| 1603 | #define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ | ||
| 1604 | #define WDEV_NONE 0x0006 /* no event on roll over */ | ||
| 1605 | #define WDEN 0x0FF0 /* enable watchdog */ | ||
| 1606 | #define WDDIS 0x0AD0 /* disable watchdog */ | ||
| 1607 | #define WDRO 0x8000 /* watchdog rolled over latch */ | ||
| 1608 | |||
| 1609 | /* deprecated WDOG_CTL Register Masks for legacy code */ | ||
| 1610 | #define ICTL WDEV | ||
| 1611 | #define ENABLE_RESET WDEV_RESET | ||
| 1612 | #define WDOG_RESET WDEV_RESET | ||
| 1613 | #define ENABLE_NMI WDEV_NMI | ||
| 1614 | #define WDOG_NMI WDEV_NMI | ||
| 1615 | #define ENABLE_GPI WDEV_GPI | ||
| 1616 | #define WDOG_GPI WDEV_GPI | ||
| 1617 | #define DISABLE_EVT WDEV_NONE | ||
| 1618 | #define WDOG_NONE WDEV_NONE | ||
| 1619 | |||
| 1620 | #define TMR_EN WDEN | ||
| 1621 | #define WDOG_DISABLE WDDIS | ||
| 1622 | #define TRO WDRO | ||
| 1623 | |||
| 1624 | #define ICTL_P0 0x01 | ||
| 1625 | #define ICTL_P1 0x02 | ||
| 1626 | #define TRO_P 0x0F | ||
| 1627 | |||
| 1628 | |||
| 1629 | /* *************** REAL TIME CLOCK MASKS **************************/ | ||
| 1630 | /* RTC_STAT and RTC_ALARM register */ | ||
| 1631 | #define RTSEC 0x0000003F /* Real-Time Clock Seconds */ | ||
| 1632 | #define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ | ||
| 1633 | #define RTHR 0x0001F000 /* Real-Time Clock Hours */ | ||
| 1634 | #define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ | ||
| 1635 | |||
| 1636 | /* RTC_ICTL register */ | ||
| 1637 | #define SWIE 0x0001 /* Stopwatch Interrupt Enable */ | ||
| 1638 | #define AIE 0x0002 /* Alarm Interrupt Enable */ | ||
| 1639 | #define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ | ||
| 1640 | #define MIE 0x0008 /* Minutes Interrupt Enable */ | ||
| 1641 | #define HIE 0x0010 /* Hours Interrupt Enable */ | ||
| 1642 | #define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ | ||
| 1643 | #define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ | ||
| 1644 | #define WCIE 0x8000 /* Write Complete Interrupt Enable */ | ||
| 1645 | |||
| 1646 | /* RTC_ISTAT register */ | ||
| 1647 | #define SWEF 0x0001 /* Stopwatch Event Flag */ | ||
| 1648 | #define AEF 0x0002 /* Alarm Event Flag */ | ||
| 1649 | #define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ | ||
| 1650 | #define MEF 0x0008 /* Minutes Event Flag */ | ||
| 1651 | #define HEF 0x0010 /* Hours Event Flag */ | ||
| 1652 | #define DEF 0x0020 /* 24 Hours (Days) Event Flag */ | ||
| 1653 | #define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ | ||
| 1654 | #define WPS 0x4000 /* Write Pending Status (RO) */ | ||
| 1655 | #define WCOM 0x8000 /* Write Complete */ | ||
| 1656 | |||
| 1657 | /* RTC_FAST Mask (RTC_PREN Mask) */ | ||
| 1658 | #define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ | ||
| 1659 | #define PREN 0x00000001 | ||
| 1660 | /* ** Must be set after power-up for proper operation of RTC */ | ||
| 1661 | |||
| 1662 | /* Deprecated RTC_STAT and RTC_ALARM Masks */ | ||
| 1663 | #define RTC_SEC RTSEC /* Real-Time Clock Seconds */ | ||
| 1664 | #define RTC_MIN RTMIN /* Real-Time Clock Minutes */ | ||
| 1665 | #define RTC_HR RTHR /* Real-Time Clock Hours */ | ||
| 1666 | #define RTC_DAY RTDAY /* Real-Time Clock Days */ | ||
| 1667 | |||
| 1668 | /* Deprecated RTC_ICTL/RTC_ISTAT Masks */ | ||
| 1669 | #define STOPWATCH SWIE /* Stopwatch Interrupt Enable */ | ||
| 1670 | #define ALARM AIE /* Alarm Interrupt Enable */ | ||
| 1671 | #define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */ | ||
| 1672 | #define MINUTE MIE /* Minutes Interrupt Enable */ | ||
| 1673 | #define HOUR HIE /* Hours Interrupt Enable */ | ||
| 1674 | #define DAY DIE /* 24 Hours (Days) Interrupt Enable */ | ||
| 1675 | #define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ | ||
| 1676 | #define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */ | ||
| 1677 | |||
| 1678 | |||
| 1679 | /* ***************************** UART CONTROLLER MASKS ********************** */ | ||
| 1680 | /* UARTx_LCR Register */ | ||
| 1681 | #ifdef _MISRA_RULES | ||
| 1682 | #define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */ | ||
| 1683 | #else | ||
| 1684 | #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ | ||
| 1685 | #endif /* _MISRA_RULES */ | ||
| 1686 | #define STB 0x04 /* Stop Bits */ | ||
| 1687 | #define PEN 0x08 /* Parity Enable */ | ||
| 1688 | #define EPS 0x10 /* Even Parity Select */ | ||
| 1689 | #define STP 0x20 /* Stick Parity */ | ||
| 1690 | #define SB 0x40 /* Set Break */ | ||
| 1691 | #define DLAB 0x80 /* Divisor Latch Access */ | ||
| 1692 | |||
| 1693 | #define DLAB_P 0x07 | ||
| 1694 | #define SB_P 0x06 | ||
| 1695 | #define STP_P 0x05 | ||
| 1696 | #define EPS_P 0x04 | ||
| 1697 | #define PEN_P 0x03 | ||
| 1698 | #define STB_P 0x02 | ||
| 1699 | #define WLS_P1 0x01 | ||
| 1700 | #define WLS_P0 0x00 | ||
| 1701 | |||
| 1702 | /* UARTx_MCR Register */ | ||
| 1703 | #define LOOP_ENA 0x10 /* Loopback Mode Enable */ | ||
| 1704 | #define LOOP_ENA_P 0x04 | ||
| 1705 | /* Deprecated UARTx_MCR Mask */ | ||
| 1706 | |||
| 1707 | /* UARTx_LSR Register */ | ||
| 1708 | #define DR 0x01 /* Data Ready */ | ||
| 1709 | #define OE 0x02 /* Overrun Error */ | ||
| 1710 | #define PE 0x04 /* Parity Error */ | ||
| 1711 | #define FE 0x08 /* Framing Error */ | ||
| 1712 | #define BI 0x10 /* Break Interrupt */ | ||
| 1713 | #define THRE 0x20 /* THR Empty */ | ||
| 1714 | #define TEMT 0x40 /* TSR and UART_THR Empty */ | ||
| 1715 | |||
| 1716 | #define TEMP_P 0x06 | ||
| 1717 | #define THRE_P 0x05 | ||
| 1718 | #define BI_P 0x04 | ||
| 1719 | #define FE_P 0x03 | ||
| 1720 | #define PE_P 0x02 | ||
| 1721 | #define OE_P 0x01 | ||
| 1722 | #define DR_P 0x00 | ||
| 1723 | |||
| 1724 | /* UARTx_IER Register */ | ||
| 1725 | #define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ | ||
| 1726 | #define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ | ||
| 1727 | #define ELSI 0x04 /* Enable RX Status Interrupt */ | ||
| 1728 | |||
| 1729 | #define ELSI_P 0x02 | ||
| 1730 | #define ETBEI_P 0x01 | ||
| 1731 | #define ERBFI_P 0x00 | ||
| 1732 | |||
| 1733 | /* UARTx_IIR Register */ | ||
| 1734 | #define NINT 0x01 | ||
| 1735 | #define STATUS_P1 0x02 | ||
| 1736 | #define STATUS_P0 0x01 | ||
| 1737 | #define NINT_P 0x00 | ||
| 1738 | |||
| 1739 | /* UARTx_GCTL Register */ | ||
| 1740 | #define UCEN 0x01 /* Enable UARTx Clocks */ | ||
| 1741 | #define IREN 0x02 /* Enable IrDA Mode */ | ||
| 1742 | #define TPOLC 0x04 /* IrDA TX Polarity Change */ | ||
| 1743 | #define RPOLC 0x08 /* IrDA RX Polarity Change */ | ||
| 1744 | #define FPE 0x10 /* Force Parity Error On Transmit */ | ||
| 1745 | #define FFE 0x20 /* Force Framing Error On Transmit */ | ||
| 1746 | |||
| 1747 | #define FFE_P 0x05 | ||
| 1748 | #define FPE_P 0x04 | ||
| 1749 | #define RPOLC_P 0x03 | ||
| 1750 | #define TPOLC_P 0x02 | ||
| 1751 | #define IREN_P 0x01 | ||
| 1752 | #define UCEN_P 0x00 | ||
| 1753 | |||
| 1754 | |||
| 1755 | /* ********** SERIAL PORT MASKS ********************** */ | ||
| 1756 | /* SPORTx_TCR1 Masks */ | ||
| 1757 | #define TSPEN 0x0001 /* TX enable */ | ||
| 1758 | #define ITCLK 0x0002 /* Internal TX Clock Select */ | ||
| 1759 | #define TDTYPE 0x000C /* TX Data Formatting Select */ | ||
| 1760 | #define DTYPE_NORM 0x0000 /* Data Format Normal */ | ||
| 1761 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 1762 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 1763 | #define TLSBIT 0x0010 /* TX Bit Order */ | ||
| 1764 | #define ITFS 0x0200 /* Internal TX Frame Sync Select */ | ||
| 1765 | #define TFSR 0x0400 /* TX Frame Sync Required Select */ | ||
| 1766 | #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ | ||
| 1767 | #define LTFS 0x1000 /* Low TX Frame Sync Select */ | ||
| 1768 | #define LATFS 0x2000 /* Late TX Frame Sync Select */ | ||
| 1769 | #define TCKFE 0x4000 /* TX Clock Falling Edge Select */ | ||
| 1770 | /* SPORTx_RCR1 Deprecated Masks */ | ||
| 1771 | #define TULAW DTYPE_ULAW /* Compand Using u-Law */ | ||
| 1772 | #define TALAW DTYPE_ALAW /* Compand Using A-Law */ | ||
| 1773 | |||
| 1774 | /* SPORTx_TCR2 Masks */ | ||
| 1775 | #ifdef _MISRA_RULES | ||
| 1776 | #define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */ | ||
| 1777 | #else | ||
| 1778 | #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ | ||
| 1779 | #endif /* _MISRA_RULES */ | ||
| 1780 | #define TXSE 0x0100 /*TX Secondary Enable */ | ||
| 1781 | #define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ | ||
| 1782 | #define TRFST 0x0400 /*TX Right-First Data Order */ | ||
| 1783 | |||
| 1784 | /* SPORTx_RCR1 Masks */ | ||
| 1785 | #define RSPEN 0x0001 /* RX enable */ | ||
| 1786 | #define IRCLK 0x0002 /* Internal RX Clock Select */ | ||
| 1787 | #define RDTYPE 0x000C /* RX Data Formatting Select */ | ||
| 1788 | #define DTYPE_NORM 0x0000 /* no companding */ | ||
| 1789 | #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ | ||
| 1790 | #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ | ||
| 1791 | #define RLSBIT 0x0010 /* RX Bit Order */ | ||
| 1792 | #define IRFS 0x0200 /* Internal RX Frame Sync Select */ | ||
| 1793 | #define RFSR 0x0400 /* RX Frame Sync Required Select */ | ||
| 1794 | #define LRFS 0x1000 /* Low RX Frame Sync Select */ | ||
| 1795 | #define LARFS 0x2000 /* Late RX Frame Sync Select */ | ||
| 1796 | #define RCKFE 0x4000 /* RX Clock Falling Edge Select */ | ||
| 1797 | /* SPORTx_RCR1 Deprecated Masks */ | ||
| 1798 | #define RULAW DTYPE_ULAW /* Compand Using u-Law */ | ||
| 1799 | #define RALAW DTYPE_ALAW /* Compand Using A-Law */ | ||
| 1800 | |||
| 1801 | /* SPORTx_RCR2 Masks */ | ||
| 1802 | #ifdef _MISRA_RULES | ||
| 1803 | #define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */ | ||
| 1804 | #else | ||
| 1805 | #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ | ||
| 1806 | #endif /* _MISRA_RULES */ | ||
| 1807 | #define RXSE 0x0100 /*RX Secondary Enable */ | ||
| 1808 | #define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ | ||
| 1809 | #define RRFST 0x0400 /*Right-First Data Order */ | ||
| 1810 | |||
| 1811 | /*SPORTx_STAT Masks */ | ||
| 1812 | #define RXNE 0x0001 /*RX FIFO Not Empty Status */ | ||
| 1813 | #define RUVF 0x0002 /*RX Underflow Status */ | ||
| 1814 | #define ROVF 0x0004 /*RX Overflow Status */ | ||
| 1815 | #define TXF 0x0008 /*TX FIFO Full Status */ | ||
| 1816 | #define TUVF 0x0010 /*TX Underflow Status */ | ||
| 1817 | #define TOVF 0x0020 /*TX Overflow Status */ | ||
| 1818 | #define TXHRE 0x0040 /*TX Hold Register Empty */ | ||
| 1819 | |||
| 1820 | /*SPORTx_MCMC1 Masks */ | ||
| 1821 | #define WOFF 0x000003FF /*Multichannel Window Offset Field */ | ||
| 1822 | /* SPORTx_MCMC1 Macros */ | ||
| 1823 | #ifdef _MISRA_RULES | ||
| 1824 | #define SET_WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */ | ||
| 1825 | /* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */ | ||
| 1826 | #define SET_WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */ | ||
| 1827 | #else | ||
| 1828 | #define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ | ||
| 1829 | /* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */ | ||
| 1830 | #define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ | ||
| 1831 | #endif /* _MISRA_RULES */ | ||
| 1832 | |||
| 1833 | |||
| 1834 | /*SPORTx_MCMC2 Masks */ | ||
| 1835 | #define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */ | ||
| 1836 | #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ | ||
| 1837 | #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ | ||
| 1838 | #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ | ||
| 1839 | #define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */ | ||
| 1840 | #define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */ | ||
| 1841 | #define MCMEN 0x0010 /*Multichannel Frame Mode Enable */ | ||
| 1842 | #define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */ | ||
| 1843 | #define MFD 0xF000 /*Multichannel Frame Delay */ | ||
| 1844 | #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ | ||
| 1845 | #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ | ||
| 1846 | #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ | ||
| 1847 | #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ | ||
| 1848 | #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ | ||
| 1849 | #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ | ||
| 1850 | #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ | ||
| 1851 | #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ | ||
| 1852 | #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ | ||
| 1853 | #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ | ||
| 1854 | #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ | ||
| 1855 | #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ | ||
| 1856 | #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ | ||
| 1857 | #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ | ||
| 1858 | #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ | ||
| 1859 | #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ | ||
| 1860 | |||
| 1861 | |||
| 1862 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ | ||
| 1863 | /* PPI_CONTROL Masks */ | ||
| 1864 | #define PORT_EN 0x0001 /* PPI Port Enable */ | ||
| 1865 | #define PORT_DIR 0x0002 /* PPI Port Direction */ | ||
| 1866 | #define XFR_TYPE 0x000C /* PPI Transfer Type */ | ||
| 1867 | #define PORT_CFG 0x0030 /* PPI Port Configuration */ | ||
| 1868 | #define FLD_SEL 0x0040 /* PPI Active Field Select */ | ||
| 1869 | #define PACK_EN 0x0080 /* PPI Packing Mode */ | ||
| 1870 | /* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */ | ||
| 1871 | #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ | ||
| 1872 | #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ | ||
| 1873 | #define DLENGTH 0x3800 /* PPI Data Length */ | ||
| 1874 | #define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ | ||
| 1875 | #define DLEN_10 0x0800 /* Data Length = 10 Bits */ | ||
| 1876 | #define DLEN_11 0x1000 /* Data Length = 11 Bits */ | ||
| 1877 | #define DLEN_12 0x1800 /* Data Length = 12 Bits */ | ||
| 1878 | #define DLEN_13 0x2000 /* Data Length = 13 Bits */ | ||
| 1879 | #define DLEN_14 0x2800 /* Data Length = 14 Bits */ | ||
| 1880 | #define DLEN_15 0x3000 /* Data Length = 15 Bits */ | ||
| 1881 | #define DLEN_16 0x3800 /* Data Length = 16 Bits */ | ||
| 1882 | #ifdef _MISRA_RULES | ||
| 1883 | #define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */ | ||
| 1884 | #else | ||
| 1885 | #define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ | ||
| 1886 | #endif /* _MISRA_RULES */ | ||
| 1887 | #define POL 0xC000 /* PPI Signal Polarities */ | ||
| 1888 | #define POLC 0x4000 /* PPI Clock Polarity */ | ||
| 1889 | #define POLS 0x8000 /* PPI Frame Sync Polarity */ | ||
| 1890 | |||
| 1891 | |||
| 1892 | /* PPI_STATUS Masks */ | ||
| 1893 | #define FLD 0x0400 /* Field Indicator */ | ||
| 1894 | #define FT_ERR 0x0800 /* Frame Track Error */ | ||
| 1895 | #define OVR 0x1000 /* FIFO Overflow Error */ | ||
| 1896 | #define UNDR 0x2000 /* FIFO Underrun Error */ | ||
| 1897 | #define ERR_DET 0x4000 /* Error Detected Indicator */ | ||
| 1898 | #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ | ||
| 1899 | |||
| 1900 | |||
| 1901 | /* ********** DMA CONTROLLER MASKS ***********************/ | ||
| 1902 | /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ | ||
| 1903 | #define DMAEN 0x0001 /* Channel Enable */ | ||
| 1904 | #define WNR 0x0002 /* Channel Direction (W/R*) */ | ||
| 1905 | #define WDSIZE_8 0x0000 /* Word Size 8 bits */ | ||
| 1906 | #define WDSIZE_16 0x0004 /* Word Size 16 bits */ | ||
| 1907 | #define WDSIZE_32 0x0008 /* Word Size 32 bits */ | ||
| 1908 | #define DMA2D 0x0010 /* 2D/1D* Mode */ | ||
| 1909 | #define RESTART 0x0020 /* Restart */ | ||
| 1910 | #define DI_SEL 0x0040 /* Data Interrupt Select */ | ||
| 1911 | #define DI_EN 0x0080 /* Data Interrupt Enable */ | ||
| 1912 | #define NDSIZE 0x0900 /* Next Descriptor Size */ | ||
| 1913 | #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ | ||
| 1914 | #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ | ||
| 1915 | #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ | ||
| 1916 | #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ | ||
| 1917 | #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ | ||
| 1918 | #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ | ||
| 1919 | #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ | ||
| 1920 | #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ | ||
| 1921 | #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ | ||
| 1922 | #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ | ||
| 1923 | |||
| 1924 | #define DMAFLOW 0x7000 /* Flow Control */ | ||
| 1925 | #define DMAFLOW_STOP 0x0000 /* Stop Mode */ | ||
| 1926 | #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ | ||
| 1927 | #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ | ||
| 1928 | #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ | ||
| 1929 | #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ | ||
| 1930 | |||
| 1931 | #define DMAEN_P 0x0 /* Channel Enable */ | ||
| 1932 | #define WNR_P 0x1 /* Channel Direction (W/R*) */ | ||
| 1933 | #define DMA2D_P 0x4 /* 2D/1D* Mode */ | ||
| 1934 | #define RESTART_P 0x5 /* Restart */ | ||
| 1935 | #define DI_SEL_P 0x6 /* Data Interrupt Select */ | ||
| 1936 | #define DI_EN_P 0x7 /* Data Interrupt Enable */ | ||
| 1937 | |||
| 1938 | /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ | ||
| 1939 | #define DMA_DONE 0x0001 /* DMA Done Indicator */ | ||
| 1940 | #define DMA_ERR 0x0002 /* DMA Error Indicator */ | ||
| 1941 | #define DFETCH 0x0004 /* Descriptor Fetch Indicator */ | ||
| 1942 | #define DMA_RUN 0x0008 /* DMA Running Indicator */ | ||
| 1943 | |||
| 1944 | #define DMA_DONE_P 0x0 /* DMA Done Indicator */ | ||
| 1945 | #define DMA_ERR_P 0x1 /* DMA Error Indicator */ | ||
| 1946 | #define DFETCH_P 0x2 /* Descriptor Fetch Indicator */ | ||
| 1947 | #define DMA_RUN_P 0x3 /* DMA Running Indicator */ | ||
| 1948 | |||
| 1949 | /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ | ||
| 1950 | |||
| 1951 | #define CTYPE 0x0040 /* DMA Channel Type Indicator */ | ||
| 1952 | #define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */ | ||
| 1953 | #define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */ | ||
| 1954 | #define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */ | ||
| 1955 | #define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */ | ||
| 1956 | #define PCAPWR 0x0400 /* DMA Write Operation Indicator */ | ||
| 1957 | #define PCAPRD 0x0800 /* DMA Read Operation Indicator */ | ||
| 1958 | #define PMAP 0xF000 /* DMA Peripheral Map Field */ | ||
| 1959 | |||
| 1960 | /* PMAP Encodings For DMA Controller 0 */ | ||
| 1961 | #define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ | ||
| 1962 | #define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ | ||
| 1963 | #define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ | ||
| 1964 | #define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ | ||
| 1965 | #define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ | ||
| 1966 | #define PMAP_SPI0 0x5000 /* PMAP SPI DMA */ | ||
| 1967 | #define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */ | ||
| 1968 | #define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */ | ||
| 1969 | |||
| 1970 | /* PMAP Encodings For DMA Controller 1 */ | ||
| 1971 | #define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */ | ||
| 1972 | #define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */ | ||
| 1973 | #define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */ | ||
| 1974 | #define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */ | ||
| 1975 | #define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */ | ||
| 1976 | #define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */ | ||
| 1977 | #define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */ | ||
| 1978 | #define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */ | ||
| 1979 | #define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */ | ||
| 1980 | #define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */ | ||
| 1981 | |||
| 1982 | |||
| 1983 | /* ************* GENERAL PURPOSE TIMER MASKS ******************** */ | ||
| 1984 | /* PWM Timer bit definitions */ | ||
| 1985 | /* TIMER_ENABLE Register */ | ||
| 1986 | #define TIMEN0 0x0001 /* Enable Timer 0 */ | ||
| 1987 | #define TIMEN1 0x0002 /* Enable Timer 1 */ | ||
| 1988 | #define TIMEN2 0x0004 /* Enable Timer 2 */ | ||
| 1989 | |||
| 1990 | #define TIMEN0_P 0x00 | ||
| 1991 | #define TIMEN1_P 0x01 | ||
| 1992 | #define TIMEN2_P 0x02 | ||
| 1993 | |||
| 1994 | /* TIMER_DISABLE Register */ | ||
| 1995 | #define TIMDIS0 0x0001 /* Disable Timer 0 */ | ||
| 1996 | #define TIMDIS1 0x0002 /* Disable Timer 1 */ | ||
| 1997 | #define TIMDIS2 0x0004 /* Disable Timer 2 */ | ||
| 1998 | |||
| 1999 | #define TIMDIS0_P 0x00 | ||
| 2000 | #define TIMDIS1_P 0x01 | ||
| 2001 | #define TIMDIS2_P 0x02 | ||
| 2002 | |||
| 2003 | /* TIMER_STATUS Register */ | ||
| 2004 | #define TIMIL0 0x0001 /* Timer 0 Interrupt */ | ||
| 2005 | #define TIMIL1 0x0002 /* Timer 1 Interrupt */ | ||
| 2006 | #define TIMIL2 0x0004 /* Timer 2 Interrupt */ | ||
| 2007 | #define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ | ||
| 2008 | #define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ | ||
| 2009 | #define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ | ||
| 2010 | #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ | ||
| 2011 | #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ | ||
| 2012 | #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ | ||
| 2013 | |||
| 2014 | #define TIMIL0_P 0x00 | ||
| 2015 | #define TIMIL1_P 0x01 | ||
| 2016 | #define TIMIL2_P 0x02 | ||
| 2017 | #define TOVF_ERR0_P 0x04 | ||
| 2018 | #define TOVF_ERR1_P 0x05 | ||
| 2019 | #define TOVF_ERR2_P 0x06 | ||
| 2020 | #define TRUN0_P 0x0C | ||
| 2021 | #define TRUN1_P 0x0D | ||
| 2022 | #define TRUN2_P 0x0E | ||
| 2023 | |||
| 2024 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ | ||
| 2025 | #define TOVL_ERR0 TOVF_ERR0 | ||
| 2026 | #define TOVL_ERR1 TOVF_ERR1 | ||
| 2027 | #define TOVL_ERR2 TOVF_ERR2 | ||
| 2028 | #define TOVL_ERR0_P TOVF_ERR0_P | ||
| 2029 | #define TOVL_ERR1_P TOVF_ERR1_P | ||
| 2030 | #define TOVL_ERR2_P TOVF_ERR2_P | ||
| 2031 | |||
| 2032 | /* TIMERx_CONFIG Registers */ | ||
| 2033 | #define PWM_OUT 0x0001 | ||
| 2034 | #define WDTH_CAP 0x0002 | ||
| 2035 | #define EXT_CLK 0x0003 | ||
| 2036 | #define PULSE_HI 0x0004 | ||
| 2037 | #define PERIOD_CNT 0x0008 | ||
| 2038 | #define IRQ_ENA 0x0010 | ||
| 2039 | #define TIN_SEL 0x0020 | ||
| 2040 | #define OUT_DIS 0x0040 | ||
| 2041 | #define CLK_SEL 0x0080 | ||
| 2042 | #define TOGGLE_HI 0x0100 | ||
| 2043 | #define EMU_RUN 0x0200 | ||
| 2044 | #ifdef _MISRA_RULES | ||
| 2045 | #define ERR_TYP(x) (((x) & 0x03u) << 14) | ||
| 2046 | #else | ||
| 2047 | #define ERR_TYP(x) (((x) & 0x03) << 14) | ||
| 2048 | #endif /* _MISRA_RULES */ | ||
| 2049 | |||
| 2050 | #define TMODE_P0 0x00 | ||
| 2051 | #define TMODE_P1 0x01 | ||
| 2052 | #define PULSE_HI_P 0x02 | ||
| 2053 | #define PERIOD_CNT_P 0x03 | ||
| 2054 | #define IRQ_ENA_P 0x04 | ||
| 2055 | #define TIN_SEL_P 0x05 | ||
| 2056 | #define OUT_DIS_P 0x06 | ||
| 2057 | #define CLK_SEL_P 0x07 | ||
| 2058 | #define TOGGLE_HI_P 0x08 | ||
| 2059 | #define EMU_RUN_P 0x09 | ||
| 2060 | #define ERR_TYP_P0 0x0E | ||
| 2061 | #define ERR_TYP_P1 0x0F | ||
| 2062 | |||
| 2063 | |||
| 2064 | /*/ ****************** GENERAL-PURPOSE I/O ********************* */ | ||
| 2065 | /* Flag I/O (FIO_) Masks */ | ||
| 2066 | #define PF0 0x0001 | ||
| 2067 | #define PF1 0x0002 | ||
| 2068 | #define PF2 0x0004 | ||
| 2069 | #define PF3 0x0008 | ||
| 2070 | #define PF4 0x0010 | ||
| 2071 | #define PF5 0x0020 | ||
| 2072 | #define PF6 0x0040 | ||
| 2073 | #define PF7 0x0080 | ||
| 2074 | #define PF8 0x0100 | ||
| 2075 | #define PF9 0x0200 | ||
| 2076 | #define PF10 0x0400 | ||
| 2077 | #define PF11 0x0800 | ||
| 2078 | #define PF12 0x1000 | ||
| 2079 | #define PF13 0x2000 | ||
| 2080 | #define PF14 0x4000 | ||
| 2081 | #define PF15 0x8000 | ||
| 2082 | |||
| 2083 | /* PORT F BIT POSITIONS */ | ||
| 2084 | #define PF0_P 0x0 | ||
| 2085 | #define PF1_P 0x1 | ||
| 2086 | #define PF2_P 0x2 | ||
| 2087 | #define PF3_P 0x3 | ||
| 2088 | #define PF4_P 0x4 | ||
| 2089 | #define PF5_P 0x5 | ||
| 2090 | #define PF6_P 0x6 | ||
| 2091 | #define PF7_P 0x7 | ||
| 2092 | #define PF8_P 0x8 | ||
| 2093 | #define PF9_P 0x9 | ||
| 2094 | #define PF10_P 0xA | ||
| 2095 | #define PF11_P 0xB | ||
| 2096 | #define PF12_P 0xC | ||
| 2097 | #define PF13_P 0xD | ||
| 2098 | #define PF14_P 0xE | ||
| 2099 | #define PF15_P 0xF | ||
| 2100 | |||
| 2101 | |||
| 2102 | /******************* GPIO MASKS *********************/ | ||
| 2103 | /* Port C Masks */ | ||
| 2104 | #define PC0 0x0001 | ||
| 2105 | #define PC1 0x0002 | ||
| 2106 | #define PC4 0x0010 | ||
| 2107 | #define PC5 0x0020 | ||
| 2108 | #define PC6 0x0040 | ||
| 2109 | #define PC7 0x0080 | ||
| 2110 | #define PC8 0x0100 | ||
| 2111 | #define PC9 0x0200 | ||
| 2112 | /* Port C Bit Positions */ | ||
| 2113 | #define PC0_P 0x0 | ||
| 2114 | #define PC1_P 0x1 | ||
| 2115 | #define PC4_P 0x4 | ||
| 2116 | #define PC5_P 0x5 | ||
| 2117 | #define PC6_P 0x6 | ||
| 2118 | #define PC7_P 0x7 | ||
| 2119 | #define PC8_P 0x8 | ||
| 2120 | #define PC9_P 0x9 | ||
| 2121 | |||
| 2122 | /* Port D */ | ||
| 2123 | #define PD0 0x0001 | ||
| 2124 | #define PD1 0x0002 | ||
| 2125 | #define PD2 0x0004 | ||
| 2126 | #define PD3 0x0008 | ||
| 2127 | #define PD4 0x0010 | ||
| 2128 | #define PD5 0x0020 | ||
| 2129 | #define PD6 0x0040 | ||
| 2130 | #define PD7 0x0080 | ||
| 2131 | #define PD8 0x0100 | ||
| 2132 | #define PD9 0x0200 | ||
| 2133 | #define PD10 0x0400 | ||
| 2134 | #define PD11 0x0800 | ||
| 2135 | #define PD12 0x1000 | ||
| 2136 | #define PD13 0x2000 | ||
| 2137 | #define PD14 0x4000 | ||
| 2138 | #define PD15 0x8000 | ||
| 2139 | /* Port D Bit Positions */ | ||
| 2140 | #define PD0_P 0x0 | ||
| 2141 | #define PD1_P 0x1 | ||
| 2142 | #define PD2_P 0x2 | ||
| 2143 | #define PD3_P 0x3 | ||
| 2144 | #define PD4_P 0x4 | ||
| 2145 | #define PD5_P 0x5 | ||
| 2146 | #define PD6_P 0x6 | ||
| 2147 | #define PD7_P 0x7 | ||
| 2148 | #define PD8_P 0x8 | ||
| 2149 | #define PD9_P 0x9 | ||
| 2150 | #define PD10_P 0xA | ||
| 2151 | #define PD11_P 0xB | ||
| 2152 | #define PD12_P 0xC | ||
| 2153 | #define PD13_P 0xD | ||
| 2154 | #define PD14_P 0xE | ||
| 2155 | #define PD15_P 0xF | ||
| 2156 | |||
| 2157 | /* Port E */ | ||
| 2158 | #define PE0 0x0001 | ||
| 2159 | #define PE1 0x0002 | ||
| 2160 | #define PE2 0x0004 | ||
| 2161 | #define PE3 0x0008 | ||
| 2162 | #define PE4 0x0010 | ||
| 2163 | #define PE5 0x0020 | ||
| 2164 | #define PE6 0x0040 | ||
| 2165 | #define PE7 0x0080 | ||
| 2166 | #define PE8 0x0100 | ||
| 2167 | #define PE9 0x0200 | ||
| 2168 | #define PE10 0x0400 | ||
| 2169 | #define PE11 0x0800 | ||
| 2170 | #define PE12 0x1000 | ||
| 2171 | #define PE13 0x2000 | ||
| 2172 | #define PE14 0x4000 | ||
| 2173 | #define PE15 0x8000 | ||
| 2174 | /* Port E Bit Positions */ | ||
| 2175 | #define PE0_P 0x0 | ||
| 2176 | #define PE1_P 0x1 | ||
| 2177 | #define PE2_P 0x2 | ||
| 2178 | #define PE3_P 0x3 | ||
| 2179 | #define PE4_P 0x4 | ||
| 2180 | #define PE5_P 0x5 | ||
| 2181 | #define PE6_P 0x6 | ||
| 2182 | #define PE7_P 0x7 | ||
| 2183 | #define PE8_P 0x8 | ||
| 2184 | #define PE9_P 0x9 | ||
| 2185 | #define PE10_P 0xA | ||
| 2186 | #define PE11_P 0xB | ||
| 2187 | #define PE12_P 0xC | ||
| 2188 | #define PE13_P 0xD | ||
| 2189 | #define PE14_P 0xE | ||
| 2190 | #define PE15_P 0xF | ||
| 2191 | |||
| 2192 | |||
| 2193 | /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ | ||
| 2194 | /* SPIx_CTL Masks */ | ||
| 2195 | #define TIMOD 0x0003 /* Transfer Initiate Mode */ | ||
| 2196 | #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ | ||
| 2197 | #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ | ||
| 2198 | #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ | ||
| 2199 | #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ | ||
| 2200 | #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ | ||
| 2201 | #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ | ||
| 2202 | #define PSSE 0x0010 /* Slave-Select Input Enable */ | ||
| 2203 | #define EMISO 0x0020 /* Enable MISO As Output */ | ||
| 2204 | #define SIZE 0x0100 /* Size of Words (16/8* Bits) */ | ||
| 2205 | #define LSBF 0x0200 /* LSB First */ | ||
| 2206 | #define CPHA 0x0400 /* Clock Phase */ | ||
| 2207 | #define CPOL 0x0800 /* Clock Polarity */ | ||
| 2208 | #define MSTR 0x1000 /* Master/Slave* */ | ||
| 2209 | #define WOM 0x2000 /* Write Open Drain Master */ | ||
| 2210 | #define SPE 0x4000 /* SPI Enable */ | ||
| 2211 | |||
| 2212 | /* SPIx_FLG Masks */ | ||
| 2213 | #define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 2214 | #define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 2215 | #define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 2216 | #define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 2217 | #define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 2218 | #define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 2219 | #define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 2220 | |||
| 2221 | #define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 2222 | #define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 2223 | #define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 2224 | #define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 2225 | #define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 2226 | #define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 2227 | #define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 2228 | |||
| 2229 | /* SPIx_FLG Bit Positions */ | ||
| 2230 | #define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 2231 | #define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 2232 | #define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 2233 | #define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 2234 | #define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 2235 | #define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 2236 | #define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 2237 | #define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ | ||
| 2238 | #define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ | ||
| 2239 | #define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ | ||
| 2240 | #define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ | ||
| 2241 | #define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ | ||
| 2242 | #define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ | ||
| 2243 | #define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ | ||
| 2244 | |||
| 2245 | /* SPIx_STAT Masks */ | ||
| 2246 | #define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */ | ||
| 2247 | #define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */ | ||
| 2248 | #define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ | ||
| 2249 | #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
| 2250 | #define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */ | ||
| 2251 | #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ | ||
| 2252 | #define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */ | ||
| 2253 | |||
| 2254 | /* SPIx_FLG Masks */ | ||
| 2255 | #define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */ | ||
| 2256 | #define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */ | ||
| 2257 | #define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */ | ||
| 2258 | #define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */ | ||
| 2259 | #define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */ | ||
| 2260 | #define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */ | ||
| 2261 | #define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */ | ||
| 2262 | |||
| 2263 | |||
| 2264 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ | ||
| 2265 | /* EBIU_AMGCTL Masks */ | ||
| 2266 | #define AMCKEN 0x0001 /* Enable CLKOUT */ | ||
| 2267 | #define AMBEN_NONE 0x0000 /* All Banks Disabled */ | ||
| 2268 | #define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ | ||
| 2269 | #define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ | ||
| 2270 | #define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ | ||
| 2271 | #define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ | ||
| 2272 | #define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */ | ||
| 2273 | |||
| 2274 | /* EBIU_AMGCTL Bit Positions */ | ||
| 2275 | #define AMCKEN_P 0x0000 /* Enable CLKOUT */ | ||
| 2276 | #define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ | ||
| 2277 | #define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ | ||
| 2278 | #define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ | ||
| 2279 | |||
| 2280 | /* EBIU_AMBCTL0 Masks */ | ||
| 2281 | #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ | ||
| 2282 | #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ | ||
| 2283 | #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ | ||
| 2284 | #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ | ||
| 2285 | #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ | ||
| 2286 | #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ | ||
| 2287 | #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ | ||
| 2288 | #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ | ||
| 2289 | #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ | ||
| 2290 | #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ | ||
| 2291 | #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ | ||
| 2292 | #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ | ||
| 2293 | #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ | ||
| 2294 | #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ | ||
| 2295 | #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ | ||
| 2296 | #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ | ||
| 2297 | #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ | ||
| 2298 | #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ | ||
| 2299 | #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ | ||
| 2300 | #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ | ||
| 2301 | #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ | ||
| 2302 | #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ | ||
| 2303 | #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ | ||
| 2304 | #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ | ||
| 2305 | #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ | ||
| 2306 | #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ | ||
| 2307 | #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ | ||
| 2308 | #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ | ||
| 2309 | #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ | ||
| 2310 | #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ | ||
| 2311 | #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ | ||
| 2312 | #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ | ||
| 2313 | #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ | ||
| 2314 | #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ | ||
| 2315 | #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ | ||
| 2316 | #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ | ||
| 2317 | #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ | ||
| 2318 | #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ | ||
| 2319 | #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ | ||
| 2320 | #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ | ||
| 2321 | #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ | ||
| 2322 | #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ | ||
| 2323 | #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ | ||
| 2324 | #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ | ||
| 2325 | #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ | ||
| 2326 | #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ | ||
| 2327 | #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ | ||
| 2328 | #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ | ||
| 2329 | #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ | ||
| 2330 | #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ | ||
| 2331 | #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | ||
| 2332 | #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | ||
| 2333 | #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | ||
| 2334 | #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | ||
| 2335 | #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | ||
| 2336 | #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | ||
| 2337 | #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | ||
| 2338 | #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | ||
| 2339 | #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ | ||
| 2340 | #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ | ||
| 2341 | #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ | ||
| 2342 | #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ | ||
| 2343 | #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ | ||
| 2344 | #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ | ||
| 2345 | #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ | ||
| 2346 | #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ | ||
| 2347 | #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ | ||
| 2348 | #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ | ||
| 2349 | #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ | ||
| 2350 | #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ | ||
| 2351 | #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ | ||
| 2352 | #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ | ||
| 2353 | #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ | ||
| 2354 | #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ | ||
| 2355 | #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ | ||
| 2356 | #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ | ||
| 2357 | #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ | ||
| 2358 | #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ | ||
| 2359 | #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ | ||
| 2360 | #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ | ||
| 2361 | #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ | ||
| 2362 | #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ | ||
| 2363 | #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ | ||
| 2364 | #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ | ||
| 2365 | #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ | ||
| 2366 | #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ | ||
| 2367 | #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ | ||
| 2368 | #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ | ||
| 2369 | |||
| 2370 | /* EBIU_AMBCTL1 Masks */ | ||
| 2371 | #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ | ||
| 2372 | #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ | ||
| 2373 | #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ | ||
| 2374 | #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ | ||
| 2375 | #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ | ||
| 2376 | #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ | ||
| 2377 | #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | ||
| 2378 | #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | ||
| 2379 | #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | ||
| 2380 | #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | ||
| 2381 | #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | ||
| 2382 | #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | ||
| 2383 | #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | ||
| 2384 | #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | ||
| 2385 | #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ | ||
| 2386 | #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ | ||
| 2387 | #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ | ||
| 2388 | #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ | ||
| 2389 | #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ | ||
| 2390 | #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ | ||
| 2391 | #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ | ||
| 2392 | #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ | ||
| 2393 | #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ | ||
| 2394 | #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ | ||
| 2395 | #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ | ||
| 2396 | #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ | ||
| 2397 | #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ | ||
| 2398 | #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ | ||
| 2399 | #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ | ||
| 2400 | #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ | ||
| 2401 | #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ | ||
| 2402 | #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ | ||
| 2403 | #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ | ||
| 2404 | #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ | ||
| 2405 | #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ | ||
| 2406 | #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ | ||
| 2407 | #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ | ||
| 2408 | #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ | ||
| 2409 | #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ | ||
| 2410 | #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ | ||
| 2411 | #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ | ||
| 2412 | #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ | ||
| 2413 | #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ | ||
| 2414 | #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ | ||
| 2415 | #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ | ||
| 2416 | #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ | ||
| 2417 | #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ | ||
| 2418 | #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ | ||
| 2419 | #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ | ||
| 2420 | #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ | ||
| 2421 | #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ | ||
| 2422 | #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ | ||
| 2423 | #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ | ||
| 2424 | #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ | ||
| 2425 | #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ | ||
| 2426 | #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ | ||
| 2427 | #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ | ||
| 2428 | #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ | ||
| 2429 | #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ | ||
| 2430 | #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ | ||
| 2431 | #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ | ||
| 2432 | #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ | ||
| 2433 | #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ | ||
| 2434 | #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ | ||
| 2435 | #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ | ||
| 2436 | #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ | ||
| 2437 | #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ | ||
| 2438 | #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ | ||
| 2439 | #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ | ||
| 2440 | #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ | ||
| 2441 | #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ | ||
| 2442 | #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ | ||
| 2443 | #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ | ||
| 2444 | #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ | ||
| 2445 | #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ | ||
| 2446 | #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ | ||
| 2447 | #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ | ||
| 2448 | #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ | ||
| 2449 | #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ | ||
| 2450 | #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ | ||
| 2451 | #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ | ||
| 2452 | #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ | ||
| 2453 | #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ | ||
| 2454 | #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ | ||
| 2455 | #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ | ||
| 2456 | #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ | ||
| 2457 | #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ | ||
| 2458 | #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ | ||
| 2459 | |||
| 2460 | /* ********************** SDRAM CONTROLLER MASKS *************************** */ | ||
| 2461 | /* EBIU_SDGCTL Masks */ | ||
| 2462 | #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ | ||
| 2463 | #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ | ||
| 2464 | #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ | ||
| 2465 | #define PFE 0x00000010 /* Enable SDRAM prefetch */ | ||
| 2466 | #define PFP 0x00000020 /* Prefetch has priority over AMC requests */ | ||
| 2467 | #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ | ||
| 2468 | #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ | ||
| 2469 | #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ | ||
| 2470 | #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ | ||
| 2471 | #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ | ||
| 2472 | #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ | ||
| 2473 | #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ | ||
| 2474 | #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ | ||
| 2475 | #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ | ||
| 2476 | #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ | ||
| 2477 | #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ | ||
| 2478 | #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ | ||
| 2479 | #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ | ||
| 2480 | #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ | ||
| 2481 | #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ | ||
| 2482 | #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ | ||
| 2483 | #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ | ||
| 2484 | #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ | ||
| 2485 | #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ | ||
| 2486 | #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ | ||
| 2487 | #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ | ||
| 2488 | #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ | ||
| 2489 | #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ | ||
| 2490 | #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ | ||
| 2491 | #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ | ||
| 2492 | #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ | ||
| 2493 | #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ | ||
| 2494 | #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ | ||
| 2495 | #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ | ||
| 2496 | #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ | ||
| 2497 | #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ | ||
| 2498 | #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ | ||
| 2499 | #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ | ||
| 2500 | #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ | ||
| 2501 | #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ | ||
| 2502 | #define PUPSD 0x00200000 /*Power-up start delay */ | ||
| 2503 | #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ | ||
| 2504 | #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ | ||
| 2505 | #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ | ||
| 2506 | #define EBUFE 0x02000000 /* Enable external buffering timing */ | ||
| 2507 | #define FBBRW 0x04000000 /* Fast back-to-back read write enable */ | ||
| 2508 | #define EMREN 0x10000000 /* Extended mode register enable */ | ||
| 2509 | #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ | ||
| 2510 | #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ | ||
| 2511 | |||
| 2512 | /* EBIU_SDBCTL Masks */ | ||
| 2513 | #define EBE 0x00000001 /* Enable SDRAM external bank */ | ||
| 2514 | #define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ | ||
| 2515 | #define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ | ||
| 2516 | #define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ | ||
| 2517 | #define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ | ||
| 2518 | #define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */ | ||
| 2519 | #define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */ | ||
| 2520 | #define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ | ||
| 2521 | #define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ | ||
| 2522 | #define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ | ||
| 2523 | #define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ | ||
| 2524 | |||
| 2525 | /* EBIU_SDSTAT Masks */ | ||
| 2526 | #define SDCI 0x00000001 /* SDRAM controller is idle */ | ||
| 2527 | #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ | ||
| 2528 | #define SDPUA 0x00000004 /* SDRAM power up active */ | ||
| 2529 | #define SDRS 0x00000008 /* SDRAM is in reset state */ | ||
| 2530 | #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ | ||
| 2531 | #define BGSTAT 0x00000020 /* Bus granted */ | ||
| 2532 | |||
| 2533 | |||
| 2534 | /* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/ | ||
| 2535 | /* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ | ||
| 2536 | #ifdef _MISRA_RULES | ||
| 2537 | #define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */ | ||
| 2538 | #define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */ | ||
| 2539 | #else | ||
| 2540 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ | ||
| 2541 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ | ||
| 2542 | #endif /* _MISRA_RULES */ | ||
| 2543 | |||
| 2544 | /* TWIx_PRESCALE Masks */ | ||
| 2545 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ | ||
| 2546 | #define TWI_ENA 0x0080 /* TWI Enable */ | ||
| 2547 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ | ||
| 2548 | |||
| 2549 | /* TWIx_SLAVE_CTRL Masks */ | ||
| 2550 | #define SEN 0x0001 /* Slave Enable */ | ||
| 2551 | #define SADD_LEN 0x0002 /* Slave Address Length */ | ||
| 2552 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ | ||
| 2553 | #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ | ||
| 2554 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ | ||
| 2555 | |||
| 2556 | /* TWIx_SLAVE_STAT Masks */ | ||
| 2557 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ | ||
| 2558 | #define GCALL 0x0002 /* General Call Indicator */ | ||
| 2559 | |||
| 2560 | /* TWIx_MASTER_CTRL Masks */ | ||
| 2561 | #define MEN 0x0001 /* Master Mode Enable */ | ||
| 2562 | #define MADD_LEN 0x0002 /* Master Address Length */ | ||
| 2563 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ | ||
| 2564 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ | ||
| 2565 | #define STOP 0x0010 /* Issue Stop Condition */ | ||
| 2566 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ | ||
| 2567 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ | ||
| 2568 | #define SDAOVR 0x4000 /* Serial Data Override */ | ||
| 2569 | #define SCLOVR 0x8000 /* Serial Clock Override */ | ||
| 2570 | |||
| 2571 | /* TWIx_MASTER_STAT Masks */ | ||
| 2572 | #define MPROG 0x0001 /* Master Transfer In Progress */ | ||
| 2573 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ | ||
| 2574 | #define ANAK 0x0004 /* Address Not Acknowledged */ | ||
| 2575 | #define DNAK 0x0008 /* Data Not Acknowledged */ | ||
| 2576 | #define BUFRDERR 0x0010 /* Buffer Read Error */ | ||
| 2577 | #define BUFWRERR 0x0020 /* Buffer Write Error */ | ||
| 2578 | #define SDASEN 0x0040 /* Serial Data Sense */ | ||
| 2579 | #define SCLSEN 0x0080 /* Serial Clock Sense */ | ||
| 2580 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ | ||
| 2581 | |||
| 2582 | /* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */ | ||
| 2583 | #define SINIT 0x0001 /* Slave Transfer Initiated */ | ||
| 2584 | #define SCOMP 0x0002 /* Slave Transfer Complete */ | ||
| 2585 | #define SERR 0x0004 /* Slave Transfer Error */ | ||
| 2586 | #define SOVF 0x0008 /* Slave Overflow */ | ||
| 2587 | #define MCOMP 0x0010 /* Master Transfer Complete */ | ||
| 2588 | #define MERR 0x0020 /* Master Transfer Error */ | ||
| 2589 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ | ||
| 2590 | #define RCVSERV 0x0080 /* Receive FIFO Service */ | ||
| 2591 | |||
| 2592 | /* TWIx_FIFO_CTRL Masks */ | ||
| 2593 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ | ||
| 2594 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ | ||
| 2595 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ | ||
| 2596 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ | ||
| 2597 | |||
| 2598 | /* TWIx_FIFO_STAT Masks */ | ||
| 2599 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ | ||
| 2600 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ | ||
| 2601 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ | ||
| 2602 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ | ||
| 2603 | |||
| 2604 | #define RCVSTAT 0x000C /* Receive FIFO Status */ | ||
| 2605 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ | ||
| 2606 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ | ||
| 2607 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ | ||
| 2608 | |||
| 2609 | |||
| 2610 | /********************************* MXVR MASKS ****************************************/ | ||
| 2611 | |||
| 2612 | /* MXVR_CONFIG Masks */ | ||
| 2613 | |||
| 2614 | #define MXVREN 0x00000001lu | ||
| 2615 | #define MMSM 0x00000002lu | ||
| 2616 | #define ACTIVE 0x00000004lu | ||
| 2617 | #define SDELAY 0x00000008lu | ||
| 2618 | #define NCMRXEN 0x00000010lu | ||
| 2619 | #define RWRRXEN 0x00000020lu | ||
| 2620 | #define MTXEN 0x00000040lu | ||
| 2621 | #define MTXON 0x00000080lu /*legacy*/ | ||
| 2622 | #define MTXONB 0x00000080lu | ||
| 2623 | #define EPARITY 0x00000100lu | ||
| 2624 | #define MSB 0x00001E00lu | ||
| 2625 | #define APRXEN 0x00002000lu | ||
| 2626 | #define WAKEUP 0x00004000lu | ||
| 2627 | #define LMECH 0x00008000lu | ||
| 2628 | |||
| 2629 | #ifdef _MISRA_RULES | ||
| 2630 | #define SET_MSB(x) (((x)&0xFu) << 0x9) | ||
| 2631 | #else | ||
| 2632 | #define SET_MSB(x) (((x)&0xF) << 0x9) | ||
| 2633 | #endif /* _MISRA_RULES */ | ||
| 2634 | |||
| 2635 | |||
| 2636 | /* MXVR_PLL_CTL_0 Masks */ | ||
| 2637 | |||
| 2638 | #define MXTALCEN 0x00000001lu | ||
| 2639 | #define MXTALFEN 0x00000002lu | ||
| 2640 | #define MPLLMS 0x00000008lu | ||
| 2641 | #define MXTALMUL 0x00000030lu | ||
| 2642 | #define MPLLEN 0x00000040lu | ||
| 2643 | #define MPLLEN0 0x00000040lu /* legacy */ | ||
| 2644 | #define MPLLEN1 0x00000080lu /* legacy */ | ||
| 2645 | #define MMCLKEN 0x00000100lu | ||
| 2646 | #define MMCLKMUL 0x00001E00lu | ||
| 2647 | #define MPLLRSTB 0x00002000lu | ||
| 2648 | #define MPLLRSTB0 0x00002000lu /* legacy */ | ||
| 2649 | #define MPLLRSTB1 0x00004000lu /* legacy */ | ||
| 2650 | #define MBCLKEN 0x00010000lu | ||
| 2651 | #define MBCLKDIV 0x001E0000lu | ||
| 2652 | #define MPLLCDR 0x00200000lu | ||
| 2653 | #define MPLLCDR0 0x00200000lu /* legacy */ | ||
| 2654 | #define MPLLCDR1 0x00400000lu /* legacy */ | ||
| 2655 | #define INVRX 0x00800000lu | ||
| 2656 | #define MFSEN 0x01000000lu | ||
| 2657 | #define MFSDIV 0x1E000000lu | ||
| 2658 | #define MFSSEL 0x60000000lu | ||
| 2659 | #define MFSSYNC 0x80000000lu | ||
| 2660 | |||
| 2661 | #define MXTALMUL_256FS 0x00000000lu /* legacy */ | ||
| 2662 | #define MXTALMUL_384FS 0x00000010lu /* legacy */ | ||
| 2663 | #define MXTALMUL_512FS 0x00000020lu /* legacy */ | ||
| 2664 | #define MXTALMUL_1024FS 0x00000030lu | ||
| 2665 | |||
| 2666 | #define MMCLKMUL_1024FS 0x00000000lu | ||
| 2667 | #define MMCLKMUL_512FS 0x00000200lu | ||
| 2668 | #define MMCLKMUL_256FS 0x00000400lu | ||
| 2669 | #define MMCLKMUL_128FS 0x00000600lu | ||
| 2670 | #define MMCLKMUL_64FS 0x00000800lu | ||
| 2671 | #define MMCLKMUL_32FS 0x00000A00lu | ||
| 2672 | #define MMCLKMUL_16FS 0x00000C00lu | ||
| 2673 | #define MMCLKMUL_8FS 0x00000E00lu | ||
| 2674 | #define MMCLKMUL_4FS 0x00001000lu | ||
| 2675 | #define MMCLKMUL_2FS 0x00001200lu | ||
| 2676 | #define MMCLKMUL_1FS 0x00001400lu | ||
| 2677 | #define MMCLKMUL_1536FS 0x00001A00lu | ||
| 2678 | #define MMCLKMUL_768FS 0x00001C00lu | ||
| 2679 | #define MMCLKMUL_384FS 0x00001E00lu | ||
| 2680 | |||
| 2681 | #define MBCLKDIV_DIV2 0x00020000lu | ||
| 2682 | #define MBCLKDIV_DIV4 0x00040000lu | ||
| 2683 | #define MBCLKDIV_DIV8 0x00060000lu | ||
| 2684 | #define MBCLKDIV_DIV16 0x00080000lu | ||
| 2685 | #define MBCLKDIV_DIV32 0x000A0000lu | ||
| 2686 | #define MBCLKDIV_DIV64 0x000C0000lu | ||
| 2687 | #define MBCLKDIV_DIV128 0x000E0000lu | ||
| 2688 | #define MBCLKDIV_DIV256 0x00100000lu | ||
| 2689 | #define MBCLKDIV_DIV512 0x00120000lu | ||
| 2690 | #define MBCLKDIV_DIV1024 0x00140000lu | ||
| 2691 | |||
| 2692 | #define MFSDIV_DIV2 0x02000000lu | ||
| 2693 | #define MFSDIV_DIV4 0x04000000lu | ||
| 2694 | #define MFSDIV_DIV8 0x06000000lu | ||
| 2695 | #define MFSDIV_DIV16 0x08000000lu | ||
| 2696 | #define MFSDIV_DIV32 0x0A000000lu | ||
| 2697 | #define MFSDIV_DIV64 0x0C000000lu | ||
| 2698 | #define MFSDIV_DIV128 0x0E000000lu | ||
| 2699 | #define MFSDIV_DIV256 0x10000000lu | ||
| 2700 | #define MFSDIV_DIV512 0x12000000lu | ||
| 2701 | #define MFSDIV_DIV1024 0x14000000lu | ||
| 2702 | |||
| 2703 | #define MFSSEL_CLOCK 0x00000000lu | ||
| 2704 | #define MFSSEL_PULSE_HI 0x20000000lu | ||
| 2705 | #define MFSSEL_PULSE_LO 0x40000000lu | ||
| 2706 | |||
| 2707 | |||
| 2708 | /* MXVR_PLL_CTL_1 Masks */ | ||
| 2709 | |||
| 2710 | #define MSTO 0x00000001lu | ||
| 2711 | #define MSTO0 0x00000001lu /* legacy */ | ||
| 2712 | #define MHOGGD 0x00000004lu | ||
| 2713 | #define MHOGGD0 0x00000004lu /* legacy */ | ||
| 2714 | #define MHOGGD1 0x00000008lu /* legacy */ | ||
| 2715 | #define MSHAPEREN 0x00000010lu | ||
| 2716 | #define MSHAPEREN0 0x00000010lu /* legacy */ | ||
| 2717 | #define MSHAPEREN1 0x00000020lu /* legacy */ | ||
| 2718 | #define MPLLCNTEN 0x00008000lu | ||
| 2719 | #define MPLLCNT 0xFFFF0000lu | ||
| 2720 | |||
| 2721 | #ifdef _MISRA_RULES | ||
| 2722 | #define SET_MPLLCNT(x) (((x)&0xFFFFu) << 0x10) | ||
| 2723 | #else | ||
| 2724 | #define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10) | ||
| 2725 | #endif /* _MISRA_RULES */ | ||
| 2726 | |||
| 2727 | |||
| 2728 | /* MXVR_PLL_CTL_2 Masks */ | ||
| 2729 | |||
| 2730 | #define MSHAPERSEL 0x00000007lu | ||
| 2731 | #define MCPSEL 0x000000E0lu | ||
| 2732 | |||
| 2733 | /* MXVR_INT_STAT_0 Masks */ | ||
| 2734 | |||
| 2735 | #define NI2A 0x00000001lu | ||
| 2736 | #define NA2I 0x00000002lu | ||
| 2737 | #define SBU2L 0x00000004lu | ||
| 2738 | #define SBL2U 0x00000008lu | ||
| 2739 | #define PRU 0x00000010lu | ||
| 2740 | #define MPRU 0x00000020lu | ||
| 2741 | #define DRU 0x00000040lu | ||
| 2742 | #define MDRU 0x00000080lu | ||
| 2743 | #define SBU 0x00000100lu | ||
| 2744 | #define ATU 0x00000200lu | ||
| 2745 | #define FCZ0 0x00000400lu | ||
| 2746 | #define FCZ1 0x00000800lu | ||
| 2747 | #define PERR 0x00001000lu | ||
| 2748 | #define MH2L 0x00002000lu | ||
| 2749 | #define ML2H 0x00004000lu | ||
| 2750 | #define WUP 0x00008000lu | ||
| 2751 | #define FU2L 0x00010000lu | ||
| 2752 | #define FL2U 0x00020000lu | ||
| 2753 | #define BU2L 0x00040000lu | ||
| 2754 | #define BL2U 0x00080000lu | ||
| 2755 | #define PCZ 0x00400000lu | ||
| 2756 | #define FERR 0x00800000lu | ||
| 2757 | #define CMR 0x01000000lu | ||
| 2758 | #define CMROF 0x02000000lu | ||
| 2759 | #define CMTS 0x04000000lu | ||
| 2760 | #define CMTC 0x08000000lu | ||
| 2761 | #define RWRC 0x10000000lu | ||
| 2762 | #define BCZ 0x20000000lu | ||
| 2763 | #define BMERR 0x40000000lu | ||
| 2764 | #define DERR 0x80000000lu | ||
| 2765 | |||
| 2766 | |||
| 2767 | /* MXVR_INT_EN_0 Masks */ | ||
| 2768 | |||
| 2769 | #define NI2AEN NI2A | ||
| 2770 | #define NA2IEN NA2I | ||
| 2771 | #define SBU2LEN SBU2L | ||
| 2772 | #define SBL2UEN SBL2U | ||
| 2773 | #define PRUEN PRU | ||
| 2774 | #define MPRUEN MPRU | ||
| 2775 | #define DRUEN DRU | ||
| 2776 | #define MDRUEN MDRU | ||
| 2777 | #define SBUEN SBU | ||
| 2778 | #define ATUEN ATU | ||
| 2779 | #define FCZ0EN FCZ0 | ||
| 2780 | #define FCZ1EN FCZ1 | ||
| 2781 | #define PERREN PERR | ||
| 2782 | #define MH2LEN MH2L | ||
| 2783 | #define ML2HEN ML2H | ||
| 2784 | #define WUPEN WUP | ||
| 2785 | #define FU2LEN FU2L | ||
| 2786 | #define FL2UEN FL2U | ||
| 2787 | #define BU2LEN BU2L | ||
| 2788 | #define BL2UEN BL2U | ||
| 2789 | #define PCZEN PCZ | ||
| 2790 | #define FERREN FERR | ||
| 2791 | #define CMREN CMR | ||
| 2792 | #define CMROFEN CMROF | ||
| 2793 | #define CMTSEN CMTS | ||
| 2794 | #define CMTCEN CMTC | ||
| 2795 | #define RWRCEN RWRC | ||
| 2796 | #define BCZEN BCZ | ||
| 2797 | #define BMERREN BMERR | ||
| 2798 | #define DERREN DERR | ||
| 2799 | |||
| 2800 | |||
| 2801 | /* MXVR_INT_STAT_1 Masks */ | ||
| 2802 | |||
| 2803 | #define APR 0x00000004lu | ||
| 2804 | #define APROF 0x00000008lu | ||
| 2805 | #define APTS 0x00000040lu | ||
| 2806 | #define APTC 0x00000080lu | ||
| 2807 | #define APRCE 0x00000400lu | ||
| 2808 | #define APRPE 0x00000800lu | ||
| 2809 | |||
| 2810 | #define HDONE0 0x00000001lu | ||
| 2811 | #define DONE0 0x00000002lu | ||
| 2812 | #define HDONE1 0x00000010lu | ||
| 2813 | #define DONE1 0x00000020lu | ||
| 2814 | #define HDONE2 0x00000100lu | ||
| 2815 | #define DONE2 0x00000200lu | ||
| 2816 | #define HDONE3 0x00001000lu | ||
| 2817 | #define DONE3 0x00002000lu | ||
| 2818 | #define HDONE4 0x00010000lu | ||
| 2819 | #define DONE4 0x00020000lu | ||
| 2820 | #define HDONE5 0x00100000lu | ||
| 2821 | #define DONE5 0x00200000lu | ||
| 2822 | #define HDONE6 0x01000000lu | ||
| 2823 | #define DONE6 0x02000000lu | ||
| 2824 | #define HDONE7 0x10000000lu | ||
| 2825 | #define DONE7 0x20000000lu | ||
| 2826 | |||
| 2827 | #define DONEX(x) (0x00000002 << (4 * (x))) | ||
| 2828 | #define HDONEX(x) (0x00000001 << (4 * (x))) | ||
| 2829 | |||
| 2830 | |||
| 2831 | /* MXVR_INT_EN_1 Masks */ | ||
| 2832 | |||
| 2833 | #define APREN APR | ||
| 2834 | #define APROFEN APROF | ||
| 2835 | #define APTSEN APTS | ||
| 2836 | #define APTCEN APTC | ||
| 2837 | #define APRCEEN APRCE | ||
| 2838 | #define APRPEEN APRPE | ||
| 2839 | |||
| 2840 | #define HDONEEN0 HDONE0 | ||
| 2841 | #define DONEEN0 DONE0 | ||
| 2842 | #define HDONEEN1 HDONE1 | ||
| 2843 | #define DONEEN1 DONE1 | ||
| 2844 | #define HDONEEN2 HDONE2 | ||
| 2845 | #define DONEEN2 DONE2 | ||
| 2846 | #define HDONEEN3 HDONE3 | ||
| 2847 | #define DONEEN3 DONE3 | ||
| 2848 | #define HDONEEN4 HDONE4 | ||
| 2849 | #define DONEEN4 DONE4 | ||
| 2850 | #define HDONEEN5 HDONE5 | ||
| 2851 | #define DONEEN5 DONE5 | ||
| 2852 | #define HDONEEN6 HDONE6 | ||
| 2853 | #define DONEEN6 DONE6 | ||
| 2854 | #define HDONEEN7 HDONE7 | ||
| 2855 | #define DONEEN7 DONE7 | ||
| 2856 | |||
| 2857 | #define DONEENX(x) (0x00000002 << (4 * (x))) | ||
| 2858 | #define HDONEENX(x) (0x00000001 << (4 * (x))) | ||
| 2859 | |||
| 2860 | |||
| 2861 | /* MXVR_STATE_0 Masks */ | ||
| 2862 | |||
| 2863 | #define NACT 0x00000001lu | ||
| 2864 | #define SBLOCK 0x00000002lu | ||
| 2865 | #define PFDLOCK 0x00000004lu | ||
| 2866 | #define PFDLOCK0 0x00000004lu /* legacy */ | ||
| 2867 | #define PDD 0x00000008lu | ||
| 2868 | #define PDD0 0x00000008lu /* legacy */ | ||
| 2869 | #define PVCO 0x00000010lu | ||
| 2870 | #define PVCO0 0x00000010lu /* legacy */ | ||
| 2871 | #define PFDLOCK1 0x00000020lu /* legacy */ | ||
| 2872 | #define PDD1 0x00000040lu /* legacy */ | ||
| 2873 | #define PVCO1 0x00000080lu /* legacy */ | ||
| 2874 | #define APBSY 0x00000100lu | ||
| 2875 | #define APARB 0x00000200lu | ||
| 2876 | #define APTX 0x00000400lu | ||
| 2877 | #define APRX 0x00000800lu | ||
| 2878 | #define CMBSY 0x00001000lu | ||
| 2879 | #define CMARB 0x00002000lu | ||
| 2880 | #define CMTX 0x00004000lu | ||
| 2881 | #define CMRX 0x00008000lu | ||
| 2882 | #define MRXONB 0x00010000lu | ||
| 2883 | #define RGSIP 0x00020000lu | ||
| 2884 | #define DALIP 0x00040000lu | ||
| 2885 | #define ALIP 0x00080000lu | ||
| 2886 | #define RRDIP 0x00100000lu | ||
| 2887 | #define RWRIP 0x00200000lu | ||
| 2888 | #define FLOCK 0x00400000lu | ||
| 2889 | #define BLOCK 0x00800000lu | ||
| 2890 | #define RSB 0x0F000000lu | ||
| 2891 | #define DERRNUM 0xF0000000lu | ||
| 2892 | |||
| 2893 | |||
| 2894 | /* MXVR_STATE_1 Masks */ | ||
| 2895 | |||
| 2896 | #define STXNUMB 0x0000000Flu | ||
| 2897 | #define SRXNUMB 0x000000F0lu | ||
| 2898 | #define APCONT 0x00000100lu | ||
| 2899 | #define DMAACTIVEX 0x00FF0000lu | ||
| 2900 | #define DMAACTIVE0 0x00010000lu | ||
| 2901 | #define DMAACTIVE1 0x00020000lu | ||
| 2902 | #define DMAACTIVE2 0x00040000lu | ||
| 2903 | #define DMAACTIVE3 0x00080000lu | ||
| 2904 | #define DMAACTIVE4 0x00100000lu | ||
| 2905 | #define DMAACTIVE5 0x00200000lu | ||
| 2906 | #define DMAACTIVE6 0x00400000lu | ||
| 2907 | #define DMAACTIVE7 0x00800000lu | ||
| 2908 | #define DMAPMENX 0xFF000000lu | ||
| 2909 | #define DMAPMEN0 0x01000000lu | ||
| 2910 | #define DMAPMEN1 0x02000000lu | ||
| 2911 | #define DMAPMEN2 0x04000000lu | ||
| 2912 | #define DMAPMEN3 0x08000000lu | ||
| 2913 | #define DMAPMEN4 0x10000000lu | ||
| 2914 | #define DMAPMEN5 0x20000000lu | ||
| 2915 | #define DMAPMEN6 0x40000000lu | ||
| 2916 | #define DMAPMEN7 0x80000000lu | ||
| 2917 | |||
| 2918 | |||
| 2919 | /* MXVR_POSITION Masks */ | ||
| 2920 | |||
| 2921 | #define PVALID 0x8000 | ||
| 2922 | #define POSITION 0x003F | ||
| 2923 | |||
| 2924 | |||
| 2925 | /* MXVR_MAX_POSITION Masks */ | ||
| 2926 | |||
| 2927 | #define MPVALID 0x8000 | ||
| 2928 | #define MPOSITION 0x003F | ||
| 2929 | |||
| 2930 | |||
| 2931 | /* MXVR_DELAY Masks */ | ||
| 2932 | |||
| 2933 | #define DVALID 0x8000 | ||
| 2934 | #define DELAY 0x003F | ||
| 2935 | |||
| 2936 | |||
| 2937 | /* MXVR_MAX_DELAY Masks */ | ||
| 2938 | |||
| 2939 | #define MDVALID 0x8000 | ||
| 2940 | #define MDELAY 0x003F | ||
| 2941 | |||
| 2942 | |||
| 2943 | /* MXVR_LADDR Masks */ | ||
| 2944 | |||
| 2945 | #define LVALID 0x80000000lu | ||
| 2946 | #define LADDR 0x0000FFFFlu | ||
| 2947 | |||
| 2948 | |||
| 2949 | /* MXVR_GADDR Masks */ | ||
| 2950 | |||
| 2951 | #define GVALID 0x8000 | ||
| 2952 | #define GADDRL 0x00FF | ||
| 2953 | |||
| 2954 | |||
| 2955 | /* MXVR_AADDR Masks */ | ||
| 2956 | |||
| 2957 | #define AVALID 0x80000000lu | ||
| 2958 | #define AADDR 0x0000FFFFlu | ||
| 2959 | |||
| 2960 | |||
| 2961 | /* MXVR_ALLOC_0 Masks */ | ||
| 2962 | |||
| 2963 | #define CIU0 0x00000080lu | ||
| 2964 | #define CIU1 0x00008000lu | ||
| 2965 | #define CIU2 0x00800000lu | ||
| 2966 | #define CIU3 0x80000000lu | ||
| 2967 | |||
| 2968 | #define CL0 0x0000007Flu | ||
| 2969 | #define CL1 0x00007F00lu | ||
| 2970 | #define CL2 0x007F0000lu | ||
| 2971 | #define CL3 0x7F000000lu | ||
| 2972 | |||
| 2973 | |||
| 2974 | /* MXVR_ALLOC_1 Masks */ | ||
| 2975 | |||
| 2976 | #define CIU4 0x00000080lu | ||
| 2977 | #define CIU5 0x00008000lu | ||
| 2978 | #define CIU6 0x00800000lu | ||
| 2979 | #define CIU7 0x80000000lu | ||
| 2980 | |||
| 2981 | #define CL4 0x0000007Flu | ||
| 2982 | #define CL5 0x00007F00lu | ||
| 2983 | #define CL6 0x007F0000lu | ||
| 2984 | #define CL7 0x7F000000lu | ||
| 2985 | |||
| 2986 | |||
| 2987 | /* MXVR_ALLOC_2 Masks */ | ||
| 2988 | |||
| 2989 | #define CIU8 0x00000080lu | ||
| 2990 | #define CIU9 0x00008000lu | ||
| 2991 | #define CIU10 0x00800000lu | ||
| 2992 | #define CIU11 0x80000000lu | ||
| 2993 | |||
| 2994 | #define CL8 0x0000007Flu | ||
| 2995 | #define CL9 0x00007F00lu | ||
| 2996 | #define CL10 0x007F0000lu | ||
| 2997 | #define CL11 0x7F000000lu | ||
| 2998 | |||
| 2999 | |||
| 3000 | /* MXVR_ALLOC_3 Masks */ | ||
| 3001 | |||
| 3002 | #define CIU12 0x00000080lu | ||
| 3003 | #define CIU13 0x00008000lu | ||
| 3004 | #define CIU14 0x00800000lu | ||
| 3005 | #define CIU15 0x80000000lu | ||
| 3006 | |||
| 3007 | #define CL12 0x0000007Flu | ||
| 3008 | #define CL13 0x00007F00lu | ||
| 3009 | #define CL14 0x007F0000lu | ||
| 3010 | #define CL15 0x7F000000lu | ||
| 3011 | |||
| 3012 | |||
| 3013 | /* MXVR_ALLOC_4 Masks */ | ||
| 3014 | |||
| 3015 | #define CIU16 0x00000080lu | ||
| 3016 | #define CIU17 0x00008000lu | ||
| 3017 | #define CIU18 0x00800000lu | ||
| 3018 | #define CIU19 0x80000000lu | ||
| 3019 | |||
| 3020 | #define CL16 0x0000007Flu | ||
| 3021 | #define CL17 0x00007F00lu | ||
| 3022 | #define CL18 0x007F0000lu | ||
| 3023 | #define CL19 0x7F000000lu | ||
| 3024 | |||
| 3025 | |||
| 3026 | /* MXVR_ALLOC_5 Masks */ | ||
| 3027 | |||
| 3028 | #define CIU20 0x00000080lu | ||
| 3029 | #define CIU21 0x00008000lu | ||
| 3030 | #define CIU22 0x00800000lu | ||
| 3031 | #define CIU23 0x80000000lu | ||
| 3032 | |||
| 3033 | #define CL20 0x0000007Flu | ||
| 3034 | #define CL21 0x00007F00lu | ||
| 3035 | #define CL22 0x007F0000lu | ||
| 3036 | #define CL23 0x7F000000lu | ||
| 3037 | |||
| 3038 | |||
| 3039 | /* MXVR_ALLOC_6 Masks */ | ||
| 3040 | |||
| 3041 | #define CIU24 0x00000080lu | ||
| 3042 | #define CIU25 0x00008000lu | ||
| 3043 | #define CIU26 0x00800000lu | ||
| 3044 | #define CIU27 0x80000000lu | ||
| 3045 | |||
| 3046 | #define CL24 0x0000007Flu | ||
| 3047 | #define CL25 0x00007F00lu | ||
| 3048 | #define CL26 0x007F0000lu | ||
| 3049 | #define CL27 0x7F000000lu | ||
| 3050 | |||
| 3051 | |||
| 3052 | /* MXVR_ALLOC_7 Masks */ | ||
| 3053 | |||
| 3054 | #define CIU28 0x00000080lu | ||
| 3055 | #define CIU29 0x00008000lu | ||
| 3056 | #define CIU30 0x00800000lu | ||
| 3057 | #define CIU31 0x80000000lu | ||
| 3058 | |||
| 3059 | #define CL28 0x0000007Flu | ||
| 3060 | #define CL29 0x00007F00lu | ||
| 3061 | #define CL30 0x007F0000lu | ||
| 3062 | #define CL31 0x7F000000lu | ||
| 3063 | |||
| 3064 | |||
| 3065 | /* MXVR_ALLOC_8 Masks */ | ||
| 3066 | |||
| 3067 | #define CIU32 0x00000080lu | ||
| 3068 | #define CIU33 0x00008000lu | ||
| 3069 | #define CIU34 0x00800000lu | ||
| 3070 | #define CIU35 0x80000000lu | ||
| 3071 | |||
| 3072 | #define CL32 0x0000007Flu | ||
| 3073 | #define CL33 0x00007F00lu | ||
| 3074 | #define CL34 0x007F0000lu | ||
| 3075 | #define CL35 0x7F000000lu | ||
| 3076 | |||
| 3077 | |||
| 3078 | /* MXVR_ALLOC_9 Masks */ | ||
| 3079 | |||
| 3080 | #define CIU36 0x00000080lu | ||
| 3081 | #define CIU37 0x00008000lu | ||
| 3082 | #define CIU38 0x00800000lu | ||
| 3083 | #define CIU39 0x80000000lu | ||
| 3084 | |||
| 3085 | #define CL36 0x0000007Flu | ||
| 3086 | #define CL37 0x00007F00lu | ||
| 3087 | #define CL38 0x007F0000lu | ||
| 3088 | #define CL39 0x7F000000lu | ||
| 3089 | |||
| 3090 | |||
| 3091 | /* MXVR_ALLOC_10 Masks */ | ||
| 3092 | |||
| 3093 | #define CIU40 0x00000080lu | ||
| 3094 | #define CIU41 0x00008000lu | ||
| 3095 | #define CIU42 0x00800000lu | ||
| 3096 | #define CIU43 0x80000000lu | ||
| 3097 | |||
| 3098 | #define CL40 0x0000007Flu | ||
| 3099 | #define CL41 0x00007F00lu | ||
| 3100 | #define CL42 0x007F0000lu | ||
| 3101 | #define CL43 0x7F000000lu | ||
| 3102 | |||
| 3103 | |||
| 3104 | /* MXVR_ALLOC_11 Masks */ | ||
| 3105 | |||
| 3106 | #define CIU44 0x00000080lu | ||
| 3107 | #define CIU45 0x00008000lu | ||
| 3108 | #define CIU46 0x00800000lu | ||
| 3109 | #define CIU47 0x80000000lu | ||
| 3110 | |||
| 3111 | #define CL44 0x0000007Flu | ||
| 3112 | #define CL45 0x00007F00lu | ||
| 3113 | #define CL46 0x007F0000lu | ||
| 3114 | #define CL47 0x7F000000lu | ||
| 3115 | |||
| 3116 | |||
| 3117 | /* MXVR_ALLOC_12 Masks */ | ||
| 3118 | |||
| 3119 | #define CIU48 0x00000080lu | ||
| 3120 | #define CIU49 0x00008000lu | ||
| 3121 | #define CIU50 0x00800000lu | ||
| 3122 | #define CIU51 0x80000000lu | ||
| 3123 | |||
| 3124 | #define CL48 0x0000007Flu | ||
| 3125 | #define CL49 0x00007F00lu | ||
| 3126 | #define CL50 0x007F0000lu | ||
| 3127 | #define CL51 0x7F000000lu | ||
| 3128 | |||
| 3129 | |||
| 3130 | /* MXVR_ALLOC_13 Masks */ | ||
| 3131 | |||
| 3132 | #define CIU52 0x00000080lu | ||
| 3133 | #define CIU53 0x00008000lu | ||
| 3134 | #define CIU54 0x00800000lu | ||
| 3135 | #define CIU55 0x80000000lu | ||
| 3136 | |||
| 3137 | #define CL52 0x0000007Flu | ||
| 3138 | #define CL53 0x00007F00lu | ||
| 3139 | #define CL54 0x007F0000lu | ||
| 3140 | #define CL55 0x7F000000lu | ||
| 3141 | |||
| 3142 | |||
| 3143 | /* MXVR_ALLOC_14 Masks */ | ||
| 3144 | |||
| 3145 | #define CIU56 0x00000080lu | ||
| 3146 | #define CIU57 0x00008000lu | ||
| 3147 | #define CIU58 0x00800000lu | ||
| 3148 | #define CIU59 0x80000000lu | ||
| 3149 | |||
| 3150 | #define CL56 0x0000007Flu | ||
| 3151 | #define CL57 0x00007F00lu | ||
| 3152 | #define CL58 0x007F0000lu | ||
| 3153 | #define CL59 0x7F000000lu | ||
| 3154 | |||
| 3155 | |||
| 3156 | /* MXVR_SYNC_LCHAN_0 Masks */ | ||
| 3157 | |||
| 3158 | #define LCHANPC0 0x0000000Flu | ||
| 3159 | #define LCHANPC1 0x000000F0lu | ||
| 3160 | #define LCHANPC2 0x00000F00lu | ||
| 3161 | #define LCHANPC3 0x0000F000lu | ||
| 3162 | #define LCHANPC4 0x000F0000lu | ||
| 3163 | #define LCHANPC5 0x00F00000lu | ||
| 3164 | #define LCHANPC6 0x0F000000lu | ||
| 3165 | #define LCHANPC7 0xF0000000lu | ||
| 3166 | |||
| 3167 | |||
| 3168 | /* MXVR_SYNC_LCHAN_1 Masks */ | ||
| 3169 | |||
| 3170 | #define LCHANPC8 0x0000000Flu | ||
| 3171 | #define LCHANPC9 0x000000F0lu | ||
| 3172 | #define LCHANPC10 0x00000F00lu | ||
| 3173 | #define LCHANPC11 0x0000F000lu | ||
| 3174 | #define LCHANPC12 0x000F0000lu | ||
| 3175 | #define LCHANPC13 0x00F00000lu | ||
| 3176 | #define LCHANPC14 0x0F000000lu | ||
| 3177 | #define LCHANPC15 0xF0000000lu | ||
| 3178 | |||
| 3179 | |||
| 3180 | /* MXVR_SYNC_LCHAN_2 Masks */ | ||
| 3181 | |||
| 3182 | #define LCHANPC16 0x0000000Flu | ||
| 3183 | #define LCHANPC17 0x000000F0lu | ||
| 3184 | #define LCHANPC18 0x00000F00lu | ||
| 3185 | #define LCHANPC19 0x0000F000lu | ||
| 3186 | #define LCHANPC20 0x000F0000lu | ||
| 3187 | #define LCHANPC21 0x00F00000lu | ||
| 3188 | #define LCHANPC22 0x0F000000lu | ||
| 3189 | #define LCHANPC23 0xF0000000lu | ||
| 3190 | |||
| 3191 | |||
| 3192 | /* MXVR_SYNC_LCHAN_3 Masks */ | ||
| 3193 | |||
| 3194 | #define LCHANPC24 0x0000000Flu | ||
| 3195 | #define LCHANPC25 0x000000F0lu | ||
| 3196 | #define LCHANPC26 0x00000F00lu | ||
| 3197 | #define LCHANPC27 0x0000F000lu | ||
| 3198 | #define LCHANPC28 0x000F0000lu | ||
| 3199 | #define LCHANPC29 0x00F00000lu | ||
| 3200 | #define LCHANPC30 0x0F000000lu | ||
| 3201 | #define LCHANPC31 0xF0000000lu | ||
| 3202 | |||
| 3203 | |||
| 3204 | /* MXVR_SYNC_LCHAN_4 Masks */ | ||
| 3205 | |||
| 3206 | #define LCHANPC32 0x0000000Flu | ||
| 3207 | #define LCHANPC33 0x000000F0lu | ||
| 3208 | #define LCHANPC34 0x00000F00lu | ||
| 3209 | #define LCHANPC35 0x0000F000lu | ||
| 3210 | #define LCHANPC36 0x000F0000lu | ||
| 3211 | #define LCHANPC37 0x00F00000lu | ||
| 3212 | #define LCHANPC38 0x0F000000lu | ||
| 3213 | #define LCHANPC39 0xF0000000lu | ||
| 3214 | |||
| 3215 | |||
| 3216 | /* MXVR_SYNC_LCHAN_5 Masks */ | ||
| 3217 | |||
| 3218 | #define LCHANPC40 0x0000000Flu | ||
| 3219 | #define LCHANPC41 0x000000F0lu | ||
| 3220 | #define LCHANPC42 0x00000F00lu | ||
| 3221 | #define LCHANPC43 0x0000F000lu | ||
| 3222 | #define LCHANPC44 0x000F0000lu | ||
| 3223 | #define LCHANPC45 0x00F00000lu | ||
| 3224 | #define LCHANPC46 0x0F000000lu | ||
| 3225 | #define LCHANPC47 0xF0000000lu | ||
| 3226 | |||
| 3227 | |||
| 3228 | /* MXVR_SYNC_LCHAN_6 Masks */ | ||
| 3229 | |||
| 3230 | #define LCHANPC48 0x0000000Flu | ||
| 3231 | #define LCHANPC49 0x000000F0lu | ||
| 3232 | #define LCHANPC50 0x00000F00lu | ||
| 3233 | #define LCHANPC51 0x0000F000lu | ||
| 3234 | #define LCHANPC52 0x000F0000lu | ||
| 3235 | #define LCHANPC53 0x00F00000lu | ||
| 3236 | #define LCHANPC54 0x0F000000lu | ||
| 3237 | #define LCHANPC55 0xF0000000lu | ||
| 3238 | |||
| 3239 | |||
| 3240 | /* MXVR_SYNC_LCHAN_7 Masks */ | ||
| 3241 | |||
| 3242 | #define LCHANPC56 0x0000000Flu | ||
| 3243 | #define LCHANPC57 0x000000F0lu | ||
| 3244 | #define LCHANPC58 0x00000F00lu | ||
| 3245 | #define LCHANPC59 0x0000F000lu | ||
| 3246 | |||
| 3247 | |||
| 3248 | /* MXVR_DMAx_CONFIG Masks */ | ||
| 3249 | |||
| 3250 | #define MDMAEN 0x00000001lu | ||
| 3251 | #define DD 0x00000002lu | ||
| 3252 | #define LCHAN 0x000003C0lu | ||
| 3253 | #define BITSWAPEN 0x00000400lu | ||
| 3254 | #define BYSWAPEN 0x00000800lu | ||
| 3255 | #define MFLOW 0x00007000lu | ||
| 3256 | #define FIXEDPM 0x00080000lu | ||
| 3257 | #define STARTPAT 0x00300000lu | ||
| 3258 | #define STOPPAT 0x00C00000lu | ||
| 3259 | #define COUNTPOS 0x1C000000lu | ||
| 3260 | |||
| 3261 | #define DD_TX 0x00000000lu | ||
| 3262 | #define DD_RX 0x00000002lu | ||
| 3263 | |||
| 3264 | #define LCHAN_0 0x00000000lu | ||
| 3265 | #define LCHAN_1 0x00000040lu | ||
| 3266 | #define LCHAN_2 0x00000080lu | ||
| 3267 | #define LCHAN_3 0x000000C0lu | ||
| 3268 | #define LCHAN_4 0x00000100lu | ||
| 3269 | #define LCHAN_5 0x00000140lu | ||
| 3270 | #define LCHAN_6 0x00000180lu | ||
| 3271 | #define LCHAN_7 0x000001C0lu | ||
| 3272 | |||
| 3273 | #define MFLOW_STOP 0x00000000lu | ||
| 3274 | #define MFLOW_AUTO 0x00001000lu | ||
| 3275 | #define MFLOW_PVC 0x00002000lu | ||
| 3276 | #define MFLOW_PSS 0x00003000lu | ||
| 3277 | #define MFLOW_PFC 0x00004000lu | ||
| 3278 | |||
| 3279 | #define STARTPAT_0 0x00000000lu | ||
| 3280 | #define STARTPAT_1 0x00100000lu | ||
| 3281 | |||
| 3282 | #define STOPPAT_0 0x00000000lu | ||
| 3283 | #define STOPPAT_1 0x00400000lu | ||
| 3284 | |||
| 3285 | #define COUNTPOS_0 0x00000000lu | ||
| 3286 | #define COUNTPOS_1 0x04000000lu | ||
| 3287 | #define COUNTPOS_2 0x08000000lu | ||
| 3288 | #define COUNTPOS_3 0x0C000000lu | ||
| 3289 | #define COUNTPOS_4 0x10000000lu | ||
| 3290 | #define COUNTPOS_5 0x14000000lu | ||
| 3291 | #define COUNTPOS_6 0x18000000lu | ||
| 3292 | #define COUNTPOS_7 0x1C000000lu | ||
| 3293 | |||
| 3294 | |||
| 3295 | /* MXVR_AP_CTL Masks */ | ||
| 3296 | |||
| 3297 | #define STARTAP 0x00000001lu | ||
| 3298 | #define CANCELAP 0x00000002lu | ||
| 3299 | #define RESETAP 0x00000004lu | ||
| 3300 | #define APRBE0 0x00004000lu | ||
| 3301 | #define APRBE1 0x00008000lu | ||
| 3302 | #define APRBEX 0x0000C000lu | ||
| 3303 | |||
| 3304 | |||
| 3305 | /* MXVR_CM_CTL Masks */ | ||
| 3306 | |||
| 3307 | #define STARTCM 0x00000001lu | ||
| 3308 | #define CANCELCM 0x00000002lu | ||
| 3309 | #define CMRBEX 0xFFFF0000lu | ||
| 3310 | #define CMRBE0 0x00010000lu | ||
| 3311 | #define CMRBE1 0x00020000lu | ||
| 3312 | #define CMRBE2 0x00040000lu | ||
| 3313 | #define CMRBE3 0x00080000lu | ||
| 3314 | #define CMRBE4 0x00100000lu | ||
| 3315 | #define CMRBE5 0x00200000lu | ||
| 3316 | #define CMRBE6 0x00400000lu | ||
| 3317 | #define CMRBE7 0x00800000lu | ||
| 3318 | #define CMRBE8 0x01000000lu | ||
| 3319 | #define CMRBE9 0x02000000lu | ||
| 3320 | #define CMRBE10 0x04000000lu | ||
| 3321 | #define CMRBE11 0x08000000lu | ||
| 3322 | #define CMRBE12 0x10000000lu | ||
| 3323 | #define CMRBE13 0x20000000lu | ||
| 3324 | #define CMRBE14 0x40000000lu | ||
| 3325 | #define CMRBE15 0x80000000lu | ||
| 3326 | |||
| 3327 | |||
| 3328 | /* MXVR_PAT_DATA_x Masks */ | ||
| 3329 | |||
| 3330 | #define MATCH_DATA_0 0x000000FFlu | ||
| 3331 | #define MATCH_DATA_1 0x0000FF00lu | ||
| 3332 | #define MATCH_DATA_2 0x00FF0000lu | ||
| 3333 | #define MATCH_DATA_3 0xFF000000lu | ||
| 3334 | |||
| 3335 | |||
| 3336 | |||
| 3337 | /* MXVR_PAT_EN_x Masks */ | ||
| 3338 | |||
| 3339 | #define MATCH_EN_0_0 0x00000001lu | ||
| 3340 | #define MATCH_EN_0_1 0x00000002lu | ||
| 3341 | #define MATCH_EN_0_2 0x00000004lu | ||
| 3342 | #define MATCH_EN_0_3 0x00000008lu | ||
| 3343 | #define MATCH_EN_0_4 0x00000010lu | ||
| 3344 | #define MATCH_EN_0_5 0x00000020lu | ||
| 3345 | #define MATCH_EN_0_6 0x00000040lu | ||
| 3346 | #define MATCH_EN_0_7 0x00000080lu | ||
| 3347 | |||
| 3348 | #define MATCH_EN_1_0 0x00000100lu | ||
| 3349 | #define MATCH_EN_1_1 0x00000200lu | ||
| 3350 | #define MATCH_EN_1_2 0x00000400lu | ||
| 3351 | #define MATCH_EN_1_3 0x00000800lu | ||
| 3352 | #define MATCH_EN_1_4 0x00001000lu | ||
| 3353 | #define MATCH_EN_1_5 0x00002000lu | ||
| 3354 | #define MATCH_EN_1_6 0x00004000lu | ||
| 3355 | #define MATCH_EN_1_7 0x00008000lu | ||
| 3356 | |||
| 3357 | #define MATCH_EN_2_0 0x00010000lu | ||
| 3358 | #define MATCH_EN_2_1 0x00020000lu | ||
| 3359 | #define MATCH_EN_2_2 0x00040000lu | ||
| 3360 | #define MATCH_EN_2_3 0x00080000lu | ||
| 3361 | #define MATCH_EN_2_4 0x00100000lu | ||
| 3362 | #define MATCH_EN_2_5 0x00200000lu | ||
| 3363 | #define MATCH_EN_2_6 0x00400000lu | ||
| 3364 | #define MATCH_EN_2_7 0x00800000lu | ||
| 3365 | |||
| 3366 | #define MATCH_EN_3_0 0x01000000lu | ||
| 3367 | #define MATCH_EN_3_1 0x02000000lu | ||
| 3368 | #define MATCH_EN_3_2 0x04000000lu | ||
| 3369 | #define MATCH_EN_3_3 0x08000000lu | ||
| 3370 | #define MATCH_EN_3_4 0x10000000lu | ||
| 3371 | #define MATCH_EN_3_5 0x20000000lu | ||
| 3372 | #define MATCH_EN_3_6 0x40000000lu | ||
| 3373 | #define MATCH_EN_3_7 0x80000000lu | ||
| 3374 | |||
| 3375 | |||
| 3376 | /* MXVR_ROUTING_0 Masks */ | ||
| 3377 | |||
| 3378 | #define MUTE_CH0 0x00000080lu | ||
| 3379 | #define MUTE_CH1 0x00008000lu | ||
| 3380 | #define MUTE_CH2 0x00800000lu | ||
| 3381 | #define MUTE_CH3 0x80000000lu | ||
| 3382 | |||
| 3383 | #define TX_CH0 0x0000007Flu | ||
| 3384 | #define TX_CH1 0x00007F00lu | ||
| 3385 | #define TX_CH2 0x007F0000lu | ||
| 3386 | #define TX_CH3 0x7F000000lu | ||
| 3387 | |||
| 3388 | |||
| 3389 | /* MXVR_ROUTING_1 Masks */ | ||
| 3390 | |||
| 3391 | #define MUTE_CH4 0x00000080lu | ||
| 3392 | #define MUTE_CH5 0x00008000lu | ||
| 3393 | #define MUTE_CH6 0x00800000lu | ||
| 3394 | #define MUTE_CH7 0x80000000lu | ||
| 3395 | |||
| 3396 | #define TX_CH4 0x0000007Flu | ||
| 3397 | #define TX_CH5 0x00007F00lu | ||
| 3398 | #define TX_CH6 0x007F0000lu | ||
| 3399 | #define TX_CH7 0x7F000000lu | ||
| 3400 | |||
| 3401 | |||
| 3402 | /* MXVR_ROUTING_2 Masks */ | ||
| 3403 | |||
| 3404 | #define MUTE_CH8 0x00000080lu | ||
| 3405 | #define MUTE_CH9 0x00008000lu | ||
| 3406 | #define MUTE_CH10 0x00800000lu | ||
| 3407 | #define MUTE_CH11 0x80000000lu | ||
| 3408 | |||
| 3409 | #define TX_CH8 0x0000007Flu | ||
| 3410 | #define TX_CH9 0x00007F00lu | ||
| 3411 | #define TX_CH10 0x007F0000lu | ||
| 3412 | #define TX_CH11 0x7F000000lu | ||
| 3413 | |||
| 3414 | /* MXVR_ROUTING_3 Masks */ | ||
| 3415 | |||
| 3416 | #define MUTE_CH12 0x00000080lu | ||
| 3417 | #define MUTE_CH13 0x00008000lu | ||
| 3418 | #define MUTE_CH14 0x00800000lu | ||
| 3419 | #define MUTE_CH15 0x80000000lu | ||
| 3420 | |||
| 3421 | #define TX_CH12 0x0000007Flu | ||
| 3422 | #define TX_CH13 0x00007F00lu | ||
| 3423 | #define TX_CH14 0x007F0000lu | ||
| 3424 | #define TX_CH15 0x7F000000lu | ||
| 3425 | |||
| 3426 | |||
| 3427 | /* MXVR_ROUTING_4 Masks */ | ||
| 3428 | |||
| 3429 | #define MUTE_CH16 0x00000080lu | ||
| 3430 | #define MUTE_CH17 0x00008000lu | ||
| 3431 | #define MUTE_CH18 0x00800000lu | ||
| 3432 | #define MUTE_CH19 0x80000000lu | ||
| 3433 | |||
| 3434 | #define TX_CH16 0x0000007Flu | ||
| 3435 | #define TX_CH17 0x00007F00lu | ||
| 3436 | #define TX_CH18 0x007F0000lu | ||
| 3437 | #define TX_CH19 0x7F000000lu | ||
| 3438 | |||
| 3439 | |||
| 3440 | /* MXVR_ROUTING_5 Masks */ | ||
| 3441 | |||
| 3442 | #define MUTE_CH20 0x00000080lu | ||
| 3443 | #define MUTE_CH21 0x00008000lu | ||
| 3444 | #define MUTE_CH22 0x00800000lu | ||
| 3445 | #define MUTE_CH23 0x80000000lu | ||
| 3446 | |||
| 3447 | #define TX_CH20 0x0000007Flu | ||
| 3448 | #define TX_CH21 0x00007F00lu | ||
| 3449 | #define TX_CH22 0x007F0000lu | ||
| 3450 | #define TX_CH23 0x7F000000lu | ||
| 3451 | |||
| 3452 | |||
| 3453 | /* MXVR_ROUTING_6 Masks */ | ||
| 3454 | |||
| 3455 | #define MUTE_CH24 0x00000080lu | ||
| 3456 | #define MUTE_CH25 0x00008000lu | ||
| 3457 | #define MUTE_CH26 0x00800000lu | ||
| 3458 | #define MUTE_CH27 0x80000000lu | ||
| 3459 | |||
| 3460 | #define TX_CH24 0x0000007Flu | ||
| 3461 | #define TX_CH25 0x00007F00lu | ||
| 3462 | #define TX_CH26 0x007F0000lu | ||
| 3463 | #define TX_CH27 0x7F000000lu | ||
| 3464 | |||
| 3465 | |||
| 3466 | /* MXVR_ROUTING_7 Masks */ | ||
| 3467 | |||
| 3468 | #define MUTE_CH28 0x00000080lu | ||
| 3469 | #define MUTE_CH29 0x00008000lu | ||
| 3470 | #define MUTE_CH30 0x00800000lu | ||
| 3471 | #define MUTE_CH31 0x80000000lu | ||
| 3472 | |||
| 3473 | #define TX_CH28 0x0000007Flu | ||
| 3474 | #define TX_CH29 0x00007F00lu | ||
| 3475 | #define TX_CH30 0x007F0000lu | ||
| 3476 | #define TX_CH31 0x7F000000lu | ||
| 3477 | |||
| 3478 | |||
| 3479 | /* MXVR_ROUTING_8 Masks */ | ||
| 3480 | |||
| 3481 | #define MUTE_CH32 0x00000080lu | ||
| 3482 | #define MUTE_CH33 0x00008000lu | ||
| 3483 | #define MUTE_CH34 0x00800000lu | ||
| 3484 | #define MUTE_CH35 0x80000000lu | ||
| 3485 | |||
| 3486 | #define TX_CH32 0x0000007Flu | ||
| 3487 | #define TX_CH33 0x00007F00lu | ||
| 3488 | #define TX_CH34 0x007F0000lu | ||
| 3489 | #define TX_CH35 0x7F000000lu | ||
| 3490 | |||
| 3491 | |||
| 3492 | /* MXVR_ROUTING_9 Masks */ | ||
| 3493 | |||
| 3494 | #define MUTE_CH36 0x00000080lu | ||
| 3495 | #define MUTE_CH37 0x00008000lu | ||
| 3496 | #define MUTE_CH38 0x00800000lu | ||
| 3497 | #define MUTE_CH39 0x80000000lu | ||
| 3498 | |||
| 3499 | #define TX_CH36 0x0000007Flu | ||
| 3500 | #define TX_CH37 0x00007F00lu | ||
| 3501 | #define TX_CH38 0x007F0000lu | ||
| 3502 | #define TX_CH39 0x7F000000lu | ||
| 3503 | |||
| 3504 | |||
| 3505 | /* MXVR_ROUTING_10 Masks */ | ||
| 3506 | |||
| 3507 | #define MUTE_CH40 0x00000080lu | ||
| 3508 | #define MUTE_CH41 0x00008000lu | ||
| 3509 | #define MUTE_CH42 0x00800000lu | ||
| 3510 | #define MUTE_CH43 0x80000000lu | ||
| 3511 | |||
| 3512 | #define TX_CH40 0x0000007Flu | ||
| 3513 | #define TX_CH41 0x00007F00lu | ||
| 3514 | #define TX_CH42 0x007F0000lu | ||
| 3515 | #define TX_CH43 0x7F000000lu | ||
| 3516 | |||
| 3517 | |||
| 3518 | /* MXVR_ROUTING_11 Masks */ | ||
| 3519 | |||
| 3520 | #define MUTE_CH44 0x00000080lu | ||
| 3521 | #define MUTE_CH45 0x00008000lu | ||
| 3522 | #define MUTE_CH46 0x00800000lu | ||
| 3523 | #define MUTE_CH47 0x80000000lu | ||
| 3524 | |||
| 3525 | #define TX_CH44 0x0000007Flu | ||
| 3526 | #define TX_CH45 0x00007F00lu | ||
| 3527 | #define TX_CH46 0x007F0000lu | ||
| 3528 | #define TX_CH47 0x7F000000lu | ||
| 3529 | |||
| 3530 | |||
| 3531 | /* MXVR_ROUTING_12 Masks */ | ||
| 3532 | |||
| 3533 | #define MUTE_CH48 0x00000080lu | ||
| 3534 | #define MUTE_CH49 0x00008000lu | ||
| 3535 | #define MUTE_CH50 0x00800000lu | ||
| 3536 | #define MUTE_CH51 0x80000000lu | ||
| 3537 | |||
| 3538 | #define TX_CH48 0x0000007Flu | ||
| 3539 | #define TX_CH49 0x00007F00lu | ||
| 3540 | #define TX_CH50 0x007F0000lu | ||
| 3541 | #define TX_CH51 0x7F000000lu | ||
| 3542 | |||
| 3543 | |||
| 3544 | /* MXVR_ROUTING_13 Masks */ | ||
| 3545 | |||
| 3546 | #define MUTE_CH52 0x00000080lu | ||
| 3547 | #define MUTE_CH53 0x00008000lu | ||
| 3548 | #define MUTE_CH54 0x00800000lu | ||
| 3549 | #define MUTE_CH55 0x80000000lu | ||
| 3550 | |||
| 3551 | #define TX_CH52 0x0000007Flu | ||
| 3552 | #define TX_CH53 0x00007F00lu | ||
| 3553 | #define TX_CH54 0x007F0000lu | ||
| 3554 | #define TX_CH55 0x7F000000lu | ||
| 3555 | |||
| 3556 | |||
| 3557 | /* MXVR_ROUTING_14 Masks */ | ||
| 3558 | |||
| 3559 | #define MUTE_CH56 0x00000080lu | ||
| 3560 | #define MUTE_CH57 0x00008000lu | ||
| 3561 | #define MUTE_CH58 0x00800000lu | ||
| 3562 | #define MUTE_CH59 0x80000000lu | ||
| 3563 | |||
| 3564 | #define TX_CH56 0x0000007Flu | ||
| 3565 | #define TX_CH57 0x00007F00lu | ||
| 3566 | #define TX_CH58 0x007F0000lu | ||
| 3567 | #define TX_CH59 0x7F000000lu | ||
| 3568 | |||
| 3569 | |||
| 3570 | /* Control Message Receive Buffer (CMRB) Address Offsets */ | ||
| 3571 | |||
| 3572 | #define CMRB_STRIDE 0x00000016lu | ||
| 3573 | |||
| 3574 | #define CMRB_DST_OFFSET 0x00000000lu | ||
| 3575 | #define CMRB_SRC_OFFSET 0x00000002lu | ||
| 3576 | #define CMRB_DATA_OFFSET 0x00000005lu | ||
| 3577 | |||
| 3578 | |||
| 3579 | /* Control Message Transmit Buffer (CMTB) Address Offsets */ | ||
| 3580 | |||
| 3581 | #define CMTB_PRIO_OFFSET 0x00000000lu | ||
| 3582 | #define CMTB_DST_OFFSET 0x00000002lu | ||
| 3583 | #define CMTB_SRC_OFFSET 0x00000004lu | ||
| 3584 | #define CMTB_TYPE_OFFSET 0x00000006lu | ||
| 3585 | #define CMTB_DATA_OFFSET 0x00000007lu | ||
| 3586 | |||
| 3587 | #define CMTB_ANSWER_OFFSET 0x0000000Alu | ||
| 3588 | |||
| 3589 | #define CMTB_STAT_N_OFFSET 0x00000018lu | ||
| 3590 | #define CMTB_STAT_A_OFFSET 0x00000016lu | ||
| 3591 | #define CMTB_STAT_D_OFFSET 0x0000000Elu | ||
| 3592 | #define CMTB_STAT_R_OFFSET 0x00000014lu | ||
| 3593 | #define CMTB_STAT_W_OFFSET 0x00000014lu | ||
| 3594 | #define CMTB_STAT_G_OFFSET 0x00000014lu | ||
| 3595 | |||
| 3596 | |||
| 3597 | /* Asynchronous Packet Receive Buffer (APRB) Address Offsets */ | ||
| 3598 | |||
| 3599 | #define APRB_STRIDE 0x00000400lu | ||
| 3600 | |||
| 3601 | #define APRB_DST_OFFSET 0x00000000lu | ||
| 3602 | #define APRB_LEN_OFFSET 0x00000002lu | ||
| 3603 | #define APRB_SRC_OFFSET 0x00000004lu | ||
| 3604 | #define APRB_DATA_OFFSET 0x00000006lu | ||
| 3605 | |||
| 3606 | |||
| 3607 | /* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */ | ||
| 3608 | |||
| 3609 | #define APTB_PRIO_OFFSET 0x00000000lu | ||
| 3610 | #define APTB_DST_OFFSET 0x00000002lu | ||
| 3611 | #define APTB_LEN_OFFSET 0x00000004lu | ||
| 3612 | #define APTB_SRC_OFFSET 0x00000006lu | ||
| 3613 | #define APTB_DATA_OFFSET 0x00000008lu | ||
| 3614 | |||
| 3615 | |||
| 3616 | /* Remote Read Buffer (RRDB) Address Offsets */ | ||
| 3617 | |||
| 3618 | #define RRDB_WADDR_OFFSET 0x00000100lu | ||
| 3619 | #define RRDB_WLEN_OFFSET 0x00000101lu | ||
| 3620 | |||
| 3621 | |||
| 3622 | |||
| 3623 | /* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ | ||
| 3624 | /* CAN_CONTROL Masks */ | ||
| 3625 | #define SRS 0x0001 /* Software Reset */ | ||
| 3626 | #define DNM 0x0002 /* Device Net Mode */ | ||
| 3627 | #define ABO 0x0004 /* Auto-Bus On Enable */ | ||
| 3628 | #define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ | ||
| 3629 | #define SMR 0x0020 /* Sleep Mode Request */ | ||
| 3630 | #define CSR 0x0040 /* CAN Suspend Mode Request */ | ||
| 3631 | #define CCR 0x0080 /* CAN Configuration Mode Request */ | ||
| 3632 | |||
| 3633 | /* CAN_STATUS Masks */ | ||
| 3634 | #define WT 0x0001 /* TX Warning Flag */ | ||
| 3635 | #define WR 0x0002 /* RX Warning Flag */ | ||
| 3636 | #define EP 0x0004 /* Error Passive Mode */ | ||
| 3637 | #define EBO 0x0008 /* Error Bus Off Mode */ | ||
| 3638 | #define CSA 0x0040 /* Suspend Mode Acknowledge */ | ||
| 3639 | #define CCA 0x0080 /* Configuration Mode Acknowledge */ | ||
| 3640 | #define MBPTR 0x1F00 /* Mailbox Pointer */ | ||
| 3641 | #define TRM 0x4000 /* Transmit Mode */ | ||
| 3642 | #define REC 0x8000 /* Receive Mode */ | ||
| 3643 | |||
| 3644 | /* CAN_CLOCK Masks */ | ||
| 3645 | #define BRP 0x03FF /* Bit-Rate Pre-Scaler */ | ||
| 3646 | |||
| 3647 | /* CAN_TIMING Masks */ | ||
| 3648 | #define TSEG1 0x000F /* Time Segment 1 */ | ||
| 3649 | #define TSEG2 0x0070 /* Time Segment 2 */ | ||
| 3650 | #define SAM 0x0080 /* Sampling */ | ||
| 3651 | #define SJW 0x0300 /* Synchronization Jump Width */ | ||
| 3652 | |||
| 3653 | /* CAN_DEBUG Masks */ | ||
| 3654 | #define DEC 0x0001 /* Disable CAN Error Counters */ | ||
| 3655 | #define DRI 0x0002 /* Disable CAN RX Input */ | ||
| 3656 | #define DTO 0x0004 /* Disable CAN TX Output */ | ||
| 3657 | #define DIL 0x0008 /* Disable CAN Internal Loop */ | ||
| 3658 | #define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ | ||
| 3659 | #define MRB 0x0020 /* Mode Read Back Enable */ | ||
| 3660 | #define CDE 0x8000 /* CAN Debug Enable */ | ||
| 3661 | |||
| 3662 | /* CAN_CEC Masks */ | ||
| 3663 | #define RXECNT 0x00FF /* Receive Error Counter */ | ||
| 3664 | #define TXECNT 0xFF00 /* Transmit Error Counter */ | ||
| 3665 | |||
| 3666 | /* CAN_INTR Masks */ | ||
| 3667 | #define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ | ||
| 3668 | #define MBRIF MBRIRQ /* legacy */ | ||
| 3669 | #define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ | ||
| 3670 | #define MBTIF MBTIRQ /* legacy */ | ||
| 3671 | #define GIRQ 0x0004 /* Global Interrupt */ | ||
| 3672 | #define SMACK 0x0008 /* Sleep Mode Acknowledge */ | ||
| 3673 | #define CANTX 0x0040 /* CAN TX Bus Value */ | ||
| 3674 | #define CANRX 0x0080 /* CAN RX Bus Value */ | ||
| 3675 | |||
| 3676 | /* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ | ||
| 3677 | #define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ | ||
| 3678 | #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ | ||
| 3679 | #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ | ||
| 3680 | #define BASEID 0x1FFC /* Base Identifier */ | ||
| 3681 | #define IDE 0x2000 /* Identifier Extension */ | ||
| 3682 | #define RTR 0x4000 /* Remote Frame Transmission Request */ | ||
| 3683 | #define AME 0x8000 /* Acceptance Mask Enable */ | ||
| 3684 | |||
| 3685 | /* CAN_MBxx_TIMESTAMP Masks */ | ||
| 3686 | #define TSV 0xFFFF /* Timestamp */ | ||
| 3687 | |||
| 3688 | /* CAN_MBxx_LENGTH Masks */ | ||
| 3689 | #define DLC 0x000F /* Data Length Code */ | ||
| 3690 | |||
| 3691 | /* CAN_AMxxH and CAN_AMxxL Masks */ | ||
| 3692 | #define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ | ||
| 3693 | #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ | ||
| 3694 | #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ | ||
| 3695 | #define BASEID 0x1FFC /* Base Identifier */ | ||
| 3696 | #define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ | ||
| 3697 | #define FMD 0x4000 /* Full Mask Data Field Enable */ | ||
| 3698 | #define FDF 0x8000 /* Filter On Data Field Enable */ | ||
| 3699 | |||
| 3700 | /* CAN_MC1 Masks */ | ||
| 3701 | #define MC0 0x0001 /* Enable Mailbox 0 */ | ||
| 3702 | #define MC1 0x0002 /* Enable Mailbox 1 */ | ||
| 3703 | #define MC2 0x0004 /* Enable Mailbox 2 */ | ||
| 3704 | #define MC3 0x0008 /* Enable Mailbox 3 */ | ||
| 3705 | #define MC4 0x0010 /* Enable Mailbox 4 */ | ||
| 3706 | #define MC5 0x0020 /* Enable Mailbox 5 */ | ||
| 3707 | #define MC6 0x0040 /* Enable Mailbox 6 */ | ||
| 3708 | #define MC7 0x0080 /* Enable Mailbox 7 */ | ||
| 3709 | #define MC8 0x0100 /* Enable Mailbox 8 */ | ||
| 3710 | #define MC9 0x0200 /* Enable Mailbox 9 */ | ||
| 3711 | #define MC10 0x0400 /* Enable Mailbox 10 */ | ||
| 3712 | #define MC11 0x0800 /* Enable Mailbox 11 */ | ||
| 3713 | #define MC12 0x1000 /* Enable Mailbox 12 */ | ||
| 3714 | #define MC13 0x2000 /* Enable Mailbox 13 */ | ||
| 3715 | #define MC14 0x4000 /* Enable Mailbox 14 */ | ||
| 3716 | #define MC15 0x8000 /* Enable Mailbox 15 */ | ||
| 3717 | |||
| 3718 | /* CAN_MC2 Masks */ | ||
| 3719 | #define MC16 0x0001 /* Enable Mailbox 16 */ | ||
| 3720 | #define MC17 0x0002 /* Enable Mailbox 17 */ | ||
| 3721 | #define MC18 0x0004 /* Enable Mailbox 18 */ | ||
| 3722 | #define MC19 0x0008 /* Enable Mailbox 19 */ | ||
| 3723 | #define MC20 0x0010 /* Enable Mailbox 20 */ | ||
| 3724 | #define MC21 0x0020 /* Enable Mailbox 21 */ | ||
| 3725 | #define MC22 0x0040 /* Enable Mailbox 22 */ | ||
| 3726 | #define MC23 0x0080 /* Enable Mailbox 23 */ | ||
| 3727 | #define MC24 0x0100 /* Enable Mailbox 24 */ | ||
| 3728 | #define MC25 0x0200 /* Enable Mailbox 25 */ | ||
| 3729 | #define MC26 0x0400 /* Enable Mailbox 26 */ | ||
| 3730 | #define MC27 0x0800 /* Enable Mailbox 27 */ | ||
| 3731 | #define MC28 0x1000 /* Enable Mailbox 28 */ | ||
| 3732 | #define MC29 0x2000 /* Enable Mailbox 29 */ | ||
| 3733 | #define MC30 0x4000 /* Enable Mailbox 30 */ | ||
| 3734 | #define MC31 0x8000 /* Enable Mailbox 31 */ | ||
| 3735 | |||
| 3736 | /* CAN_MD1 Masks */ | ||
| 3737 | #define MD0 0x0001 /* Enable Mailbox 0 For Receive */ | ||
| 3738 | #define MD1 0x0002 /* Enable Mailbox 1 For Receive */ | ||
| 3739 | #define MD2 0x0004 /* Enable Mailbox 2 For Receive */ | ||
| 3740 | #define MD3 0x0008 /* Enable Mailbox 3 For Receive */ | ||
| 3741 | #define MD4 0x0010 /* Enable Mailbox 4 For Receive */ | ||
| 3742 | #define MD5 0x0020 /* Enable Mailbox 5 For Receive */ | ||
| 3743 | #define MD6 0x0040 /* Enable Mailbox 6 For Receive */ | ||
| 3744 | #define MD7 0x0080 /* Enable Mailbox 7 For Receive */ | ||
| 3745 | #define MD8 0x0100 /* Enable Mailbox 8 For Receive */ | ||
| 3746 | #define MD9 0x0200 /* Enable Mailbox 9 For Receive */ | ||
| 3747 | #define MD10 0x0400 /* Enable Mailbox 10 For Receive */ | ||
| 3748 | #define MD11 0x0800 /* Enable Mailbox 11 For Receive */ | ||
| 3749 | #define MD12 0x1000 /* Enable Mailbox 12 For Receive */ | ||
| 3750 | #define MD13 0x2000 /* Enable Mailbox 13 For Receive */ | ||
| 3751 | #define MD14 0x4000 /* Enable Mailbox 14 For Receive */ | ||
| 3752 | #define MD15 0x8000 /* Enable Mailbox 15 For Receive */ | ||
| 3753 | |||
| 3754 | /* CAN_MD2 Masks */ | ||
| 3755 | #define MD16 0x0001 /* Enable Mailbox 16 For Receive */ | ||
| 3756 | #define MD17 0x0002 /* Enable Mailbox 17 For Receive */ | ||
| 3757 | #define MD18 0x0004 /* Enable Mailbox 18 For Receive */ | ||
| 3758 | #define MD19 0x0008 /* Enable Mailbox 19 For Receive */ | ||
| 3759 | #define MD20 0x0010 /* Enable Mailbox 20 For Receive */ | ||
| 3760 | #define MD21 0x0020 /* Enable Mailbox 21 For Receive */ | ||
| 3761 | #define MD22 0x0040 /* Enable Mailbox 22 For Receive */ | ||
| 3762 | #define MD23 0x0080 /* Enable Mailbox 23 For Receive */ | ||
| 3763 | #define MD24 0x0100 /* Enable Mailbox 24 For Receive */ | ||
| 3764 | #define MD25 0x0200 /* Enable Mailbox 25 For Receive */ | ||
| 3765 | #define MD26 0x0400 /* Enable Mailbox 26 For Receive */ | ||
| 3766 | #define MD27 0x0800 /* Enable Mailbox 27 For Receive */ | ||
| 3767 | #define MD28 0x1000 /* Enable Mailbox 28 For Receive */ | ||
| 3768 | #define MD29 0x2000 /* Enable Mailbox 29 For Receive */ | ||
| 3769 | #define MD30 0x4000 /* Enable Mailbox 30 For Receive */ | ||
| 3770 | #define MD31 0x8000 /* Enable Mailbox 31 For Receive */ | ||
| 3771 | |||
| 3772 | /* CAN_RMP1 Masks */ | ||
| 3773 | #define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ | ||
| 3774 | #define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ | ||
| 3775 | #define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ | ||
| 3776 | #define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ | ||
| 3777 | #define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ | ||
| 3778 | #define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ | ||
| 3779 | #define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ | ||
| 3780 | #define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ | ||
| 3781 | #define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ | ||
| 3782 | #define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ | ||
| 3783 | #define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ | ||
| 3784 | #define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ | ||
| 3785 | #define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ | ||
| 3786 | #define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ | ||
| 3787 | #define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ | ||
| 3788 | #define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ | ||
| 3789 | |||
| 3790 | /* CAN_RMP2 Masks */ | ||
| 3791 | #define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ | ||
| 3792 | #define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ | ||
| 3793 | #define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ | ||
| 3794 | #define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ | ||
| 3795 | #define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ | ||
| 3796 | #define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ | ||
| 3797 | #define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ | ||
| 3798 | #define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ | ||
| 3799 | #define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ | ||
| 3800 | #define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ | ||
| 3801 | #define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ | ||
| 3802 | #define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ | ||
| 3803 | #define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ | ||
| 3804 | #define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ | ||
| 3805 | #define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ | ||
| 3806 | #define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ | ||
| 3807 | |||
| 3808 | /* CAN_RML1 Masks */ | ||
| 3809 | #define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ | ||
| 3810 | #define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ | ||
| 3811 | #define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ | ||
| 3812 | #define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ | ||
| 3813 | #define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ | ||
| 3814 | #define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ | ||
| 3815 | #define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ | ||
| 3816 | #define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ | ||
| 3817 | #define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ | ||
| 3818 | #define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ | ||
| 3819 | #define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ | ||
| 3820 | #define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ | ||
| 3821 | #define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ | ||
| 3822 | #define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ | ||
| 3823 | #define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ | ||
| 3824 | #define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ | ||
| 3825 | |||
| 3826 | /* CAN_RML2 Masks */ | ||
| 3827 | #define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ | ||
| 3828 | #define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ | ||
| 3829 | #define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ | ||
| 3830 | #define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ | ||
| 3831 | #define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ | ||
| 3832 | #define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ | ||
| 3833 | #define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ | ||
| 3834 | #define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ | ||
| 3835 | #define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ | ||
| 3836 | #define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ | ||
| 3837 | #define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ | ||
| 3838 | #define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ | ||
| 3839 | #define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ | ||
| 3840 | #define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ | ||
| 3841 | #define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ | ||
| 3842 | #define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ | ||
| 3843 | |||
| 3844 | /* CAN_OPSS1 Masks */ | ||
| 3845 | #define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ | ||
| 3846 | #define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ | ||
| 3847 | #define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ | ||
| 3848 | #define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ | ||
| 3849 | #define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ | ||
| 3850 | #define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ | ||
| 3851 | #define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ | ||
| 3852 | #define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ | ||
| 3853 | #define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ | ||
| 3854 | #define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ | ||
| 3855 | #define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ | ||
| 3856 | #define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ | ||
| 3857 | #define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ | ||
| 3858 | #define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ | ||
| 3859 | #define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ | ||
| 3860 | #define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ | ||
| 3861 | |||
| 3862 | /* CAN_OPSS2 Masks */ | ||
| 3863 | #define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ | ||
| 3864 | #define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ | ||
| 3865 | #define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ | ||
| 3866 | #define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ | ||
| 3867 | #define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ | ||
| 3868 | #define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ | ||
| 3869 | #define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ | ||
| 3870 | #define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ | ||
| 3871 | #define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ | ||
| 3872 | #define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ | ||
| 3873 | #define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ | ||
| 3874 | #define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ | ||
| 3875 | #define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ | ||
| 3876 | #define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ | ||
| 3877 | #define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ | ||
| 3878 | #define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ | ||
| 3879 | |||
| 3880 | /* CAN_TRR1 Masks */ | ||
| 3881 | #define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ | ||
| 3882 | #define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ | ||
| 3883 | #define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ | ||
| 3884 | #define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ | ||
| 3885 | #define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ | ||
| 3886 | #define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ | ||
| 3887 | #define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ | ||
| 3888 | #define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ | ||
| 3889 | #define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ | ||
| 3890 | #define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ | ||
| 3891 | #define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ | ||
| 3892 | #define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ | ||
| 3893 | #define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ | ||
| 3894 | #define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ | ||
| 3895 | #define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ | ||
| 3896 | #define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ | ||
| 3897 | |||
| 3898 | /* CAN_TRR2 Masks */ | ||
| 3899 | #define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ | ||
| 3900 | #define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ | ||
| 3901 | #define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ | ||
| 3902 | #define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ | ||
| 3903 | #define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ | ||
| 3904 | #define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ | ||
| 3905 | #define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ | ||
| 3906 | #define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ | ||
| 3907 | #define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ | ||
| 3908 | #define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ | ||
| 3909 | #define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ | ||
| 3910 | #define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ | ||
| 3911 | #define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ | ||
| 3912 | #define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ | ||
| 3913 | #define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ | ||
| 3914 | #define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ | ||
| 3915 | |||
| 3916 | /* CAN_TRS1 Masks */ | ||
| 3917 | #define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ | ||
| 3918 | #define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ | ||
| 3919 | #define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ | ||
| 3920 | #define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ | ||
| 3921 | #define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ | ||
| 3922 | #define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ | ||
| 3923 | #define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ | ||
| 3924 | #define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ | ||
| 3925 | #define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ | ||
| 3926 | #define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ | ||
| 3927 | #define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ | ||
| 3928 | #define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ | ||
| 3929 | #define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ | ||
| 3930 | #define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ | ||
| 3931 | #define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ | ||
| 3932 | #define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ | ||
| 3933 | |||
| 3934 | /* CAN_TRS2 Masks */ | ||
| 3935 | #define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ | ||
| 3936 | #define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ | ||
| 3937 | #define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ | ||
| 3938 | #define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ | ||
| 3939 | #define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ | ||
| 3940 | #define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ | ||
| 3941 | #define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ | ||
| 3942 | #define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ | ||
| 3943 | #define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ | ||
| 3944 | #define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ | ||
| 3945 | #define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ | ||
| 3946 | #define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ | ||
| 3947 | #define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ | ||
| 3948 | #define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ | ||
| 3949 | #define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ | ||
| 3950 | #define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ | ||
| 3951 | |||
| 3952 | /* CAN_AA1 Masks */ | ||
| 3953 | #define AA0 0x0001 /* Aborted Message In Mailbox 0 */ | ||
| 3954 | #define AA1 0x0002 /* Aborted Message In Mailbox 1 */ | ||
| 3955 | #define AA2 0x0004 /* Aborted Message In Mailbox 2 */ | ||
| 3956 | #define AA3 0x0008 /* Aborted Message In Mailbox 3 */ | ||
| 3957 | #define AA4 0x0010 /* Aborted Message In Mailbox 4 */ | ||
| 3958 | #define AA5 0x0020 /* Aborted Message In Mailbox 5 */ | ||
| 3959 | #define AA6 0x0040 /* Aborted Message In Mailbox 6 */ | ||
| 3960 | #define AA7 0x0080 /* Aborted Message In Mailbox 7 */ | ||
| 3961 | #define AA8 0x0100 /* Aborted Message In Mailbox 8 */ | ||
| 3962 | #define AA9 0x0200 /* Aborted Message In Mailbox 9 */ | ||
| 3963 | #define AA10 0x0400 /* Aborted Message In Mailbox 10 */ | ||
| 3964 | #define AA11 0x0800 /* Aborted Message In Mailbox 11 */ | ||
| 3965 | #define AA12 0x1000 /* Aborted Message In Mailbox 12 */ | ||
| 3966 | #define AA13 0x2000 /* Aborted Message In Mailbox 13 */ | ||
| 3967 | #define AA14 0x4000 /* Aborted Message In Mailbox 14 */ | ||
| 3968 | #define AA15 0x8000 /* Aborted Message In Mailbox 15 */ | ||
| 3969 | |||
| 3970 | /* CAN_AA2 Masks */ | ||
| 3971 | #define AA16 0x0001 /* Aborted Message In Mailbox 16 */ | ||
| 3972 | #define AA17 0x0002 /* Aborted Message In Mailbox 17 */ | ||
| 3973 | #define AA18 0x0004 /* Aborted Message In Mailbox 18 */ | ||
| 3974 | #define AA19 0x0008 /* Aborted Message In Mailbox 19 */ | ||
| 3975 | #define AA20 0x0010 /* Aborted Message In Mailbox 20 */ | ||
| 3976 | #define AA21 0x0020 /* Aborted Message In Mailbox 21 */ | ||
| 3977 | #define AA22 0x0040 /* Aborted Message In Mailbox 22 */ | ||
| 3978 | #define AA23 0x0080 /* Aborted Message In Mailbox 23 */ | ||
| 3979 | #define AA24 0x0100 /* Aborted Message In Mailbox 24 */ | ||
| 3980 | #define AA25 0x0200 /* Aborted Message In Mailbox 25 */ | ||
| 3981 | #define AA26 0x0400 /* Aborted Message In Mailbox 26 */ | ||
| 3982 | #define AA27 0x0800 /* Aborted Message In Mailbox 27 */ | ||
| 3983 | #define AA28 0x1000 /* Aborted Message In Mailbox 28 */ | ||
| 3984 | #define AA29 0x2000 /* Aborted Message In Mailbox 29 */ | ||
| 3985 | #define AA30 0x4000 /* Aborted Message In Mailbox 30 */ | ||
| 3986 | #define AA31 0x8000 /* Aborted Message In Mailbox 31 */ | ||
| 3987 | |||
| 3988 | /* CAN_TA1 Masks */ | ||
| 3989 | #define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ | ||
| 3990 | #define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ | ||
| 3991 | #define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ | ||
| 3992 | #define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ | ||
| 3993 | #define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ | ||
| 3994 | #define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ | ||
| 3995 | #define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ | ||
| 3996 | #define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ | ||
| 3997 | #define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ | ||
| 3998 | #define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ | ||
| 3999 | #define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ | ||
| 4000 | #define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ | ||
| 4001 | #define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ | ||
| 4002 | #define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ | ||
| 4003 | #define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ | ||
| 4004 | #define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ | ||
| 4005 | |||
| 4006 | /* CAN_TA2 Masks */ | ||
| 4007 | #define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ | ||
| 4008 | #define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ | ||
| 4009 | #define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ | ||
| 4010 | #define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ | ||
| 4011 | #define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ | ||
| 4012 | #define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ | ||
| 4013 | #define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ | ||
| 4014 | #define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ | ||
| 4015 | #define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ | ||
| 4016 | #define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ | ||
| 4017 | #define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ | ||
| 4018 | #define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ | ||
| 4019 | #define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ | ||
| 4020 | #define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ | ||
| 4021 | #define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ | ||
| 4022 | #define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ | ||
| 4023 | |||
| 4024 | /* CAN_MBTD Masks */ | ||
| 4025 | #define TDPTR 0x001F /* Mailbox To Temporarily Disable */ | ||
| 4026 | #define TDA 0x0040 /* Temporary Disable Acknowledge */ | ||
| 4027 | #define TDR 0x0080 /* Temporary Disable Request */ | ||
| 4028 | |||
| 4029 | /* CAN_RFH1 Masks */ | ||
| 4030 | #define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ | ||
| 4031 | #define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ | ||
| 4032 | #define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ | ||
| 4033 | #define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ | ||
| 4034 | #define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ | ||
| 4035 | #define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ | ||
| 4036 | #define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ | ||
| 4037 | #define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ | ||
| 4038 | #define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ | ||
| 4039 | #define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ | ||
| 4040 | #define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ | ||
| 4041 | #define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ | ||
| 4042 | #define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ | ||
| 4043 | #define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ | ||
| 4044 | #define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ | ||
| 4045 | #define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ | ||
| 4046 | |||
| 4047 | /* CAN_RFH2 Masks */ | ||
| 4048 | #define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ | ||
| 4049 | #define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ | ||
| 4050 | #define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ | ||
| 4051 | #define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ | ||
| 4052 | #define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ | ||
| 4053 | #define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ | ||
| 4054 | #define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ | ||
| 4055 | #define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ | ||
| 4056 | #define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ | ||
| 4057 | #define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ | ||
| 4058 | #define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ | ||
| 4059 | #define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ | ||
| 4060 | #define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ | ||
| 4061 | #define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ | ||
| 4062 | #define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ | ||
| 4063 | #define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ | ||
| 4064 | |||
| 4065 | /* CAN_MBTIF1 Masks */ | ||
| 4066 | #define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ | ||
| 4067 | #define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ | ||
| 4068 | #define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ | ||
| 4069 | #define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ | ||
| 4070 | #define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ | ||
| 4071 | #define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ | ||
| 4072 | #define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ | ||
| 4073 | #define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ | ||
| 4074 | #define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ | ||
| 4075 | #define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ | ||
| 4076 | #define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ | ||
| 4077 | #define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ | ||
| 4078 | #define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ | ||
| 4079 | #define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ | ||
| 4080 | #define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ | ||
| 4081 | #define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ | ||
| 4082 | |||
| 4083 | /* CAN_MBTIF2 Masks */ | ||
| 4084 | #define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ | ||
| 4085 | #define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ | ||
| 4086 | #define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ | ||
| 4087 | #define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ | ||
| 4088 | #define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ | ||
| 4089 | #define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ | ||
| 4090 | #define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ | ||
| 4091 | #define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ | ||
| 4092 | #define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ | ||
| 4093 | #define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ | ||
| 4094 | #define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ | ||
| 4095 | #define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ | ||
| 4096 | #define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ | ||
| 4097 | #define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ | ||
| 4098 | #define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ | ||
| 4099 | #define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ | ||
| 4100 | |||
| 4101 | /* CAN_MBRIF1 Masks */ | ||
| 4102 | #define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ | ||
| 4103 | #define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ | ||
| 4104 | #define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ | ||
| 4105 | #define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ | ||
| 4106 | #define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ | ||
| 4107 | #define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ | ||
| 4108 | #define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ | ||
| 4109 | #define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ | ||
| 4110 | #define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ | ||
| 4111 | #define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ | ||
| 4112 | #define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ | ||
| 4113 | #define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ | ||
| 4114 | #define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ | ||
| 4115 | #define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ | ||
| 4116 | #define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ | ||
| 4117 | #define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ | ||
| 4118 | |||
| 4119 | /* CAN_MBRIF2 Masks */ | ||
| 4120 | #define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ | ||
| 4121 | #define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ | ||
| 4122 | #define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ | ||
| 4123 | #define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ | ||
| 4124 | #define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ | ||
| 4125 | #define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ | ||
| 4126 | #define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ | ||
| 4127 | #define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ | ||
| 4128 | #define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ | ||
| 4129 | #define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ | ||
| 4130 | #define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ | ||
| 4131 | #define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ | ||
| 4132 | #define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ | ||
| 4133 | #define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ | ||
| 4134 | #define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ | ||
| 4135 | #define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ | ||
| 4136 | |||
| 4137 | /* CAN_MBIM1 Masks */ | ||
| 4138 | #define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ | ||
| 4139 | #define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ | ||
| 4140 | #define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ | ||
| 4141 | #define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ | ||
| 4142 | #define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ | ||
| 4143 | #define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ | ||
| 4144 | #define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ | ||
| 4145 | #define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ | ||
| 4146 | #define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ | ||
| 4147 | #define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ | ||
| 4148 | #define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ | ||
| 4149 | #define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ | ||
| 4150 | #define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ | ||
| 4151 | #define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ | ||
| 4152 | #define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ | ||
| 4153 | #define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ | ||
| 4154 | |||
| 4155 | /* CAN_MBIM2 Masks */ | ||
| 4156 | #define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ | ||
| 4157 | #define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ | ||
| 4158 | #define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ | ||
| 4159 | #define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ | ||
| 4160 | #define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ | ||
| 4161 | #define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ | ||
| 4162 | #define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ | ||
| 4163 | #define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ | ||
| 4164 | #define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ | ||
| 4165 | #define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ | ||
| 4166 | #define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ | ||
| 4167 | #define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ | ||
| 4168 | #define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ | ||
| 4169 | #define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ | ||
| 4170 | #define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ | ||
| 4171 | #define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ | ||
| 4172 | |||
| 4173 | /* CAN_GIM Masks */ | ||
| 4174 | #define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ | ||
| 4175 | #define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ | ||
| 4176 | #define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ | ||
| 4177 | #define BOIM 0x0008 /* Enable Bus Off Interrupt */ | ||
| 4178 | #define WUIM 0x0010 /* Enable Wake-Up Interrupt */ | ||
| 4179 | #define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ | ||
| 4180 | #define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ | ||
| 4181 | #define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ | ||
| 4182 | #define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ | ||
| 4183 | #define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ | ||
| 4184 | #define ADIM 0x0400 /* Enable Access Denied Interrupt */ | ||
| 4185 | |||
| 4186 | /* CAN_GIS Masks */ | ||
| 4187 | #define EWTIS 0x0001 /* TX Error Count IRQ Status */ | ||
| 4188 | #define EWRIS 0x0002 /* RX Error Count IRQ Status */ | ||
| 4189 | #define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ | ||
| 4190 | #define BOIS 0x0008 /* Bus Off IRQ Status */ | ||
| 4191 | #define WUIS 0x0010 /* Wake-Up IRQ Status */ | ||
| 4192 | #define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ | ||
| 4193 | #define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ | ||
| 4194 | #define RMLIS 0x0080 /* RX Message Lost IRQ Status */ | ||
| 4195 | #define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ | ||
| 4196 | #define EXTIS 0x0200 /* External Trigger Output IRQ Status */ | ||
| 4197 | #define ADIS 0x0400 /* Access Denied IRQ Status */ | ||
| 4198 | |||
| 4199 | /* CAN_GIF Masks */ | ||
| 4200 | #define EWTIF 0x0001 /* TX Error Count IRQ Flag */ | ||
| 4201 | #define EWRIF 0x0002 /* RX Error Count IRQ Flag */ | ||
| 4202 | #define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ | ||
| 4203 | #define BOIF 0x0008 /* Bus Off IRQ Flag */ | ||
| 4204 | #define WUIF 0x0010 /* Wake-Up IRQ Flag */ | ||
| 4205 | #define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ | ||
| 4206 | #define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ | ||
| 4207 | #define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ | ||
| 4208 | #define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ | ||
| 4209 | #define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ | ||
| 4210 | #define ADIF 0x0400 /* Access Denied IRQ Flag */ | ||
| 4211 | |||
| 4212 | /* CAN_UCCNF Masks */ | ||
| 4213 | #define UCCNF 0x000F /* Universal Counter Mode */ | ||
| 4214 | #define UC_STAMP 0x0001 /* Timestamp Mode */ | ||
| 4215 | #define UC_WDOG 0x0002 /* Watchdog Mode */ | ||
| 4216 | #define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ | ||
| 4217 | #define UC_ERROR 0x0006 /* CAN Error Frame Count */ | ||
| 4218 | #define UC_OVER 0x0007 /* CAN Overload Frame Count */ | ||
| 4219 | #define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ | ||
| 4220 | #define UC_AA 0x0009 /* TX Abort Count */ | ||
| 4221 | #define UC_TA 0x000A /* TX Successful Count */ | ||
| 4222 | #define UC_REJECT 0x000B /* RX Message Rejected Count */ | ||
| 4223 | #define UC_RML 0x000C /* RX Message Lost Count */ | ||
| 4224 | #define UC_RX 0x000D /* Total Successful RX Messages Count */ | ||
| 4225 | #define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ | ||
| 4226 | #define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ | ||
| 4227 | #define UCRC 0x0020 /* Universal Counter Reload/Clear */ | ||
| 4228 | #define UCCT 0x0040 /* Universal Counter CAN Trigger */ | ||
| 4229 | #define UCE 0x0080 /* Universal Counter Enable */ | ||
| 4230 | |||
| 4231 | /* CAN_ESR Masks */ | ||
| 4232 | #define ACKE 0x0004 /* Acknowledge Error */ | ||
| 4233 | #define SER 0x0008 /* Stuff Error */ | ||
| 4234 | #define CRCE 0x0010 /* CRC Error */ | ||
| 4235 | #define SA0 0x0020 /* Stuck At Dominant Error */ | ||
| 4236 | #define BEF 0x0040 /* Bit Error Flag */ | ||
| 4237 | #define FER 0x0080 /* Form Error Flag */ | ||
| 4238 | |||
| 4239 | /* CAN_EWR Masks */ | ||
| 4240 | #define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ | ||
| 4241 | #define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ | ||
| 4242 | |||
| 4243 | #endif /* _DEF_BF539_H */ | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/dma.h b/arch/blackfin/mach-bf538/include/mach/dma.h new file mode 100644 index 000000000000..eb05cacbf4d3 --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/dma.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* mach/dma.h - arch-specific DMA defines | ||
| 2 | * | ||
| 3 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 4 | * | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _MACH_DMA_H_ | ||
| 9 | #define _MACH_DMA_H_ | ||
| 10 | |||
| 11 | #define CH_PPI 0 | ||
| 12 | #define CH_SPORT0_RX 1 | ||
| 13 | #define CH_SPORT0_TX 2 | ||
| 14 | #define CH_SPORT1_RX 3 | ||
| 15 | #define CH_SPORT1_TX 4 | ||
| 16 | #define CH_SPI0 5 | ||
| 17 | #define CH_UART0_RX 6 | ||
| 18 | #define CH_UART0_TX 7 | ||
| 19 | #define CH_SPORT2_RX 8 | ||
| 20 | #define CH_SPORT2_TX 9 | ||
| 21 | #define CH_SPORT3_RX 10 | ||
| 22 | #define CH_SPORT3_TX 11 | ||
| 23 | #define CH_SPI1 14 | ||
| 24 | #define CH_SPI2 15 | ||
| 25 | #define CH_UART1_RX 16 | ||
| 26 | #define CH_UART1_TX 17 | ||
| 27 | #define CH_UART2_RX 18 | ||
| 28 | #define CH_UART2_TX 19 | ||
| 29 | |||
| 30 | #define CH_MEM_STREAM0_DEST 20 | ||
| 31 | #define CH_MEM_STREAM0_SRC 21 | ||
| 32 | #define CH_MEM_STREAM1_DEST 22 | ||
| 33 | #define CH_MEM_STREAM1_SRC 23 | ||
| 34 | #define CH_MEM_STREAM2_DEST 24 | ||
| 35 | #define CH_MEM_STREAM2_SRC 25 | ||
| 36 | #define CH_MEM_STREAM3_DEST 26 | ||
| 37 | #define CH_MEM_STREAM3_SRC 27 | ||
| 38 | |||
| 39 | #define MAX_DMA_CHANNELS 28 | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h new file mode 100644 index 000000000000..30f4f723f7cc --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/gpio.h | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf538/include/mach/gpio.h | ||
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 4 | * | ||
| 5 | * Copyright (C) 2008 Analog Devices Inc. | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | #ifndef _MACH_GPIO_H_ | ||
| 11 | #define _MACH_GPIO_H_ | ||
| 12 | |||
| 13 | /* FIXME: | ||
| 14 | * For now only support PORTF GPIOs. | ||
| 15 | * PORT C,D and E are for peripheral usage only | ||
| 16 | */ | ||
| 17 | #define MAX_BLACKFIN_GPIOS 16 | ||
| 18 | |||
| 19 | #define GPIO_PF0 0 /* PF */ | ||
| 20 | #define GPIO_PF1 1 | ||
| 21 | #define GPIO_PF2 2 | ||
| 22 | #define GPIO_PF3 3 | ||
| 23 | #define GPIO_PF4 4 | ||
| 24 | #define GPIO_PF5 5 | ||
| 25 | #define GPIO_PF6 6 | ||
| 26 | #define GPIO_PF7 7 | ||
| 27 | #define GPIO_PF8 8 | ||
| 28 | #define GPIO_PF9 9 | ||
| 29 | #define GPIO_PF10 10 | ||
| 30 | #define GPIO_PF11 11 | ||
| 31 | #define GPIO_PF12 12 | ||
| 32 | #define GPIO_PF13 13 | ||
| 33 | #define GPIO_PF14 14 | ||
| 34 | #define GPIO_PF15 15 | ||
| 35 | #define GPIO_PC0 16 /* PC */ | ||
| 36 | #define GPIO_PC1 17 | ||
| 37 | #define GPIO_PC4 20 | ||
| 38 | #define GPIO_PC5 21 | ||
| 39 | #define GPIO_PC6 22 | ||
| 40 | #define GPIO_PC7 23 | ||
| 41 | #define GPIO_PC8 24 | ||
| 42 | #define GPIO_PC9 25 | ||
| 43 | #define GPIO_PD0 32 /* PD */ | ||
| 44 | #define GPIO_PD1 33 | ||
| 45 | #define GPIO_PD2 34 | ||
| 46 | #define GPIO_PD3 35 | ||
| 47 | #define GPIO_PD4 36 | ||
| 48 | #define GPIO_PD5 37 | ||
| 49 | #define GPIO_PD6 38 | ||
| 50 | #define GPIO_PD7 39 | ||
| 51 | #define GPIO_PD8 40 | ||
| 52 | #define GPIO_PD9 41 | ||
| 53 | #define GPIO_PD10 42 | ||
| 54 | #define GPIO_PD11 43 | ||
| 55 | #define GPIO_PD12 44 | ||
| 56 | #define GPIO_PD13 45 | ||
| 57 | #define GPIO_PE0 48 /* PE */ | ||
| 58 | #define GPIO_PE1 49 | ||
| 59 | #define GPIO_PE2 50 | ||
| 60 | #define GPIO_PE3 51 | ||
| 61 | #define GPIO_PE4 52 | ||
| 62 | #define GPIO_PE5 53 | ||
| 63 | #define GPIO_PE6 54 | ||
| 64 | #define GPIO_PE7 55 | ||
| 65 | #define GPIO_PE8 56 | ||
| 66 | #define GPIO_PE9 57 | ||
| 67 | #define GPIO_PE10 58 | ||
| 68 | #define GPIO_PE11 59 | ||
| 69 | #define GPIO_PE12 60 | ||
| 70 | #define GPIO_PE13 61 | ||
| 71 | #define GPIO_PE14 62 | ||
| 72 | #define GPIO_PE15 63 | ||
| 73 | |||
| 74 | #define PORT_F GPIO_PF0 | ||
| 75 | #define PORT_C GPIO_PC0 | ||
| 76 | #define PORT_D GPIO_PD0 | ||
| 77 | #define PORT_E GPIO_PE0 | ||
| 78 | |||
| 79 | #endif /* _MACH_GPIO_H_ */ | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h new file mode 100644 index 000000000000..fdc87fe2c174 --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/irq.h | |||
| @@ -0,0 +1,211 @@ | |||
| 1 | /* | ||
| 2 | * file: include/asm-blackfin/mach-bf538/irq.h | ||
| 3 | * based on: include/asm-blackfin/mach-bf537/irq.h | ||
| 4 | * author: Michael Hennerich (michael.hennerich@analog.com) | ||
| 5 | * | ||
| 6 | * created: | ||
| 7 | * description: | ||
| 8 | * system mmr register map | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * this program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the gnu general public license as published by | ||
| 18 | * the free software foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * this program is distributed in the hope that it will be useful, | ||
| 22 | * but without any warranty; without even the implied warranty of | ||
| 23 | * merchantability or fitness for a particular purpose. see the | ||
| 24 | * gnu general public license for more details. | ||
| 25 | * | ||
| 26 | * you should have received a copy of the gnu general public license | ||
| 27 | * along with this program; see the file copying. | ||
| 28 | * if not, write to the free software foundation, | ||
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #ifndef _BF538_IRQ_H_ | ||
| 33 | #define _BF538_IRQ_H_ | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Interrupt source definitions | ||
| 37 | Event Source Core Event Name | ||
| 38 | Core Emulation ** | ||
| 39 | Events (highest priority) EMU 0 | ||
| 40 | Reset RST 1 | ||
| 41 | NMI NMI 2 | ||
| 42 | Exception EVX 3 | ||
| 43 | Reserved -- 4 | ||
| 44 | Hardware Error IVHW 5 | ||
| 45 | Core Timer IVTMR 6 * | ||
| 46 | |||
| 47 | ..... | ||
| 48 | |||
| 49 | Software Interrupt 1 IVG14 31 | ||
| 50 | Software Interrupt 2 -- | ||
| 51 | (lowest priority) IVG15 32 * | ||
| 52 | */ | ||
| 53 | |||
| 54 | #define NR_PERI_INTS (2 * 32) | ||
| 55 | |||
| 56 | /* The ABSTRACT IRQ definitions */ | ||
| 57 | /** the first seven of the following are fixed, the rest you change if you need to **/ | ||
| 58 | #define IRQ_EMU 0 /* Emulation */ | ||
| 59 | #define IRQ_RST 1 /* reset */ | ||
| 60 | #define IRQ_NMI 2 /* Non Maskable */ | ||
| 61 | #define IRQ_EVX 3 /* Exception */ | ||
| 62 | #define IRQ_UNUSED 4 /* - unused interrupt */ | ||
| 63 | #define IRQ_HWERR 5 /* Hardware Error */ | ||
| 64 | #define IRQ_CORETMR 6 /* Core timer */ | ||
| 65 | |||
| 66 | #define BFIN_IRQ(x) ((x) + 7) | ||
| 67 | |||
| 68 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ | ||
| 69 | #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ | ||
| 70 | #define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */ | ||
| 71 | #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */ | ||
| 72 | #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */ | ||
| 73 | #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */ | ||
| 74 | #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */ | ||
| 75 | #define IRQ_RTC BFIN_IRQ(7) /* RTC */ | ||
| 76 | #define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */ | ||
| 77 | #define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */ | ||
| 78 | #define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */ | ||
| 79 | #define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */ | ||
| 80 | #define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */ | ||
| 81 | #define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */ | ||
| 82 | #define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */ | ||
| 83 | #define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */ | ||
| 84 | #define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */ | ||
| 85 | #define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */ | ||
| 86 | #define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */ | ||
| 87 | #define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */ | ||
| 88 | #define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */ | ||
| 89 | #define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */ | ||
| 90 | #define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */ | ||
| 91 | #define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */ | ||
| 92 | #define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */ | ||
| 93 | #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */ | ||
| 94 | #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */ | ||
| 95 | #define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */ | ||
| 96 | #define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */ | ||
| 97 | #define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */ | ||
| 98 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */ | ||
| 99 | #define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */ | ||
| 100 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */ | ||
| 101 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */ | ||
| 102 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */ | ||
| 103 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */ | ||
| 104 | #define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */ | ||
| 105 | #define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */ | ||
| 106 | #define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */ | ||
| 107 | #define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */ | ||
| 108 | #define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */ | ||
| 109 | #define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */ | ||
| 110 | #define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */ | ||
| 111 | #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */ | ||
| 112 | #define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */ | ||
| 113 | #define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */ | ||
| 114 | #define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */ | ||
| 115 | #define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */ | ||
| 116 | |||
| 117 | #define SYS_IRQS BFIN_IRQ(63) /* 70 */ | ||
| 118 | |||
| 119 | #define IRQ_PF0 71 | ||
| 120 | #define IRQ_PF1 72 | ||
| 121 | #define IRQ_PF2 73 | ||
| 122 | #define IRQ_PF3 74 | ||
| 123 | #define IRQ_PF4 75 | ||
| 124 | #define IRQ_PF5 76 | ||
| 125 | #define IRQ_PF6 77 | ||
| 126 | #define IRQ_PF7 78 | ||
| 127 | #define IRQ_PF8 79 | ||
| 128 | #define IRQ_PF9 80 | ||
| 129 | #define IRQ_PF10 81 | ||
| 130 | #define IRQ_PF11 82 | ||
| 131 | #define IRQ_PF12 83 | ||
| 132 | #define IRQ_PF13 84 | ||
| 133 | #define IRQ_PF14 85 | ||
| 134 | #define IRQ_PF15 86 | ||
| 135 | |||
| 136 | #define GPIO_IRQ_BASE IRQ_PF0 | ||
| 137 | |||
| 138 | #define NR_IRQS (IRQ_PF15+1) | ||
| 139 | |||
| 140 | #define IVG7 7 | ||
| 141 | #define IVG8 8 | ||
| 142 | #define IVG9 9 | ||
| 143 | #define IVG10 10 | ||
| 144 | #define IVG11 11 | ||
| 145 | #define IVG12 12 | ||
| 146 | #define IVG13 13 | ||
| 147 | #define IVG14 14 | ||
| 148 | #define IVG15 15 | ||
| 149 | |||
| 150 | /* IAR0 BIT FIELDS */ | ||
| 151 | #define IRQ_PLL_WAKEUP_POS 0 | ||
| 152 | #define IRQ_DMA0_ERROR_POS 4 | ||
| 153 | #define IRQ_PPI_ERROR_POS 8 | ||
| 154 | #define IRQ_SPORT0_ERROR_POS 12 | ||
| 155 | #define IRQ_SPORT1_ERROR_POS 16 | ||
| 156 | #define IRQ_SPI0_ERROR_POS 20 | ||
| 157 | #define IRQ_UART0_ERROR_POS 24 | ||
| 158 | #define IRQ_RTC_POS 28 | ||
| 159 | |||
| 160 | /* IAR1 BIT FIELDS */ | ||
| 161 | #define IRQ_PPI_POS 0 | ||
| 162 | #define IRQ_SPORT0_RX_POS 4 | ||
| 163 | #define IRQ_SPORT0_TX_POS 8 | ||
| 164 | #define IRQ_SPORT1_RX_POS 12 | ||
| 165 | #define IRQ_SPORT1_TX_POS 16 | ||
| 166 | #define IRQ_SPI0_POS 20 | ||
| 167 | #define IRQ_UART0_RX_POS 24 | ||
| 168 | #define IRQ_UART0_TX_POS 28 | ||
| 169 | |||
| 170 | /* IAR2 BIT FIELDS */ | ||
| 171 | #define IRQ_TIMER0_POS 0 | ||
| 172 | #define IRQ_TIMER1_POS 4 | ||
| 173 | #define IRQ_TIMER2_POS 8 | ||
| 174 | #define IRQ_PORTF_INTA_POS 12 | ||
| 175 | #define IRQ_PORTF_INTB_POS 16 | ||
| 176 | #define IRQ_MEM0_DMA0_POS 20 | ||
| 177 | #define IRQ_MEM0_DMA1_POS 24 | ||
| 178 | #define IRQ_WATCH_POS 28 | ||
| 179 | |||
| 180 | /* IAR3 BIT FIELDS */ | ||
| 181 | #define IRQ_DMA1_ERROR_POS 0 | ||
| 182 | #define IRQ_SPORT2_ERROR_POS 4 | ||
| 183 | #define IRQ_SPORT3_ERROR_POS 8 | ||
| 184 | #define IRQ_SPI1_ERROR_POS 16 | ||
| 185 | #define IRQ_SPI2_ERROR_POS 20 | ||
| 186 | #define IRQ_UART1_ERROR_POS 24 | ||
| 187 | #define IRQ_UART2_ERROR_POS 28 | ||
| 188 | |||
| 189 | /* IAR4 BIT FIELDS */ | ||
| 190 | #define IRQ_CAN_ERROR_POS 0 | ||
| 191 | #define IRQ_SPORT2_RX_POS 4 | ||
| 192 | #define IRQ_SPORT2_TX_POS 8 | ||
| 193 | #define IRQ_SPORT3_RX_POS 12 | ||
| 194 | #define IRQ_SPORT3_TX_POS 16 | ||
| 195 | #define IRQ_SPI1_POS 28 | ||
| 196 | |||
| 197 | /* IAR5 BIT FIELDS */ | ||
| 198 | #define IRQ_SPI2_POS 0 | ||
| 199 | #define IRQ_UART1_RX_POS 4 | ||
| 200 | #define IRQ_UART1_TX_POS 8 | ||
| 201 | #define IRQ_UART2_RX_POS 12 | ||
| 202 | #define IRQ_UART2_TX_POS 16 | ||
| 203 | #define IRQ_TWI0_POS 20 | ||
| 204 | #define IRQ_TWI1_POS 24 | ||
| 205 | #define IRQ_CAN_RX_POS 28 | ||
| 206 | |||
| 207 | /* IAR6 BIT FIELDS */ | ||
| 208 | #define IRQ_CAN_TX_POS 0 | ||
| 209 | #define IRQ_MEM1_DMA0_POS 4 | ||
| 210 | #define IRQ_MEM1_DMA1_POS 8 | ||
| 211 | #endif /* _BF538_IRQ_H_ */ | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h new file mode 100644 index 000000000000..76811966690e --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/mem_map.h | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf538/mem_map.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _MEM_MAP_538_H_ | ||
| 32 | #define _MEM_MAP_538_H_ | ||
| 33 | |||
| 34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | ||
| 35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | ||
| 36 | |||
| 37 | /* Async Memory Banks */ | ||
| 38 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | ||
| 39 | #define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ | ||
| 40 | #define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ | ||
| 41 | #define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ | ||
| 42 | #define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ | ||
| 43 | #define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ | ||
| 44 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ | ||
| 45 | #define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ | ||
| 46 | |||
| 47 | /* Boot ROM Memory */ | ||
| 48 | |||
| 49 | #define BOOT_ROM_START 0xEF000000 | ||
| 50 | #define BOOT_ROM_LENGTH 0x400 | ||
| 51 | |||
| 52 | /* Level 1 Memory */ | ||
| 53 | |||
| 54 | #ifdef CONFIG_BFIN_ICACHE | ||
| 55 | #define BFIN_ICACHESIZE (16*1024) | ||
| 56 | #else | ||
| 57 | #define BFIN_ICACHESIZE (0*1024) | ||
| 58 | #endif | ||
| 59 | |||
| 60 | /* Memory Map for ADSP-BF538/9 processors */ | ||
| 61 | |||
| 62 | #define L1_CODE_START 0xFFA00000 | ||
| 63 | #define L1_DATA_A_START 0xFF800000 | ||
| 64 | #define L1_DATA_B_START 0xFF900000 | ||
| 65 | |||
| 66 | #ifdef CONFIG_BFIN_ICACHE | ||
| 67 | #define L1_CODE_LENGTH (0x14000 - 0x4000) | ||
| 68 | #else | ||
| 69 | #define L1_CODE_LENGTH 0x14000 | ||
| 70 | #endif | ||
| 71 | |||
| 72 | #ifdef CONFIG_BFIN_DCACHE | ||
| 73 | |||
| 74 | #ifdef CONFIG_BFIN_DCACHE_BANKA | ||
| 75 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) | ||
| 76 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | ||
| 77 | #define L1_DATA_B_LENGTH 0x8000 | ||
| 78 | #define BFIN_DCACHESIZE (16*1024) | ||
| 79 | #define BFIN_DSUPBANKS 1 | ||
| 80 | #else | ||
| 81 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) | ||
| 82 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) | ||
| 83 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) | ||
| 84 | #define BFIN_DCACHESIZE (32*1024) | ||
| 85 | #define BFIN_DSUPBANKS 2 | ||
| 86 | #endif | ||
| 87 | |||
| 88 | #else | ||
| 89 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) | ||
| 90 | #define L1_DATA_A_LENGTH 0x8000 | ||
| 91 | #define L1_DATA_B_LENGTH 0x8000 | ||
| 92 | #define BFIN_DCACHESIZE (0*1024) | ||
| 93 | #define BFIN_DSUPBANKS 0 | ||
| 94 | #endif /*CONFIG_BFIN_DCACHE*/ | ||
| 95 | |||
| 96 | |||
| 97 | /* Level 2 Memory - none */ | ||
| 98 | |||
| 99 | #define L2_START 0 | ||
| 100 | #define L2_LENGTH 0 | ||
| 101 | |||
| 102 | /* Scratch Pad Memory */ | ||
| 103 | |||
| 104 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 105 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 106 | |||
| 107 | #define GET_PDA_SAFE(preg) \ | ||
| 108 | preg.l = _cpu_pda; \ | ||
| 109 | preg.h = _cpu_pda; | ||
| 110 | |||
| 111 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 112 | |||
| 113 | #endif /* _MEM_MAP_538_H_ */ | ||
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h new file mode 100644 index 000000000000..1e031b588b47 --- /dev/null +++ b/arch/blackfin/mach-bf538/include/mach/portmux.h | |||
| @@ -0,0 +1,106 @@ | |||
| 1 | #ifndef _MACH_PORTMUX_H_ | ||
| 2 | #define _MACH_PORTMUX_H_ | ||
| 3 | |||
| 4 | #define MAX_RESOURCES MAX_BLACKFIN_GPIOS | ||
| 5 | |||
| 6 | #define P_TMR2 (P_DONTCARE) | ||
| 7 | #define P_TMR1 (P_DONTCARE) | ||
| 8 | #define P_TMR0 (P_DONTCARE) | ||
| 9 | #define P_TMRCLK (P_DONTCARE) | ||
| 10 | #define P_PPI0_CLK (P_DONTCARE) | ||
| 11 | #define P_PPI0_FS1 (P_DONTCARE) | ||
| 12 | #define P_PPI0_FS2 (P_DONTCARE) | ||
| 13 | |||
| 14 | #define P_TWI0_SCL (P_DONTCARE) | ||
| 15 | #define P_TWI0_SDA (P_DONTCARE) | ||
| 16 | #define P_TWI1_SCL (P_DONTCARE) | ||
| 17 | #define P_TWI1_SDA (P_DONTCARE) | ||
| 18 | |||
| 19 | #define P_SPORT1_TSCLK (P_DONTCARE) | ||
| 20 | #define P_SPORT1_RSCLK (P_DONTCARE) | ||
| 21 | #define P_SPORT0_TSCLK (P_DONTCARE) | ||
| 22 | #define P_SPORT0_RSCLK (P_DONTCARE) | ||
| 23 | #define P_SPORT1_DRSEC (P_DONTCARE) | ||
| 24 | #define P_SPORT1_RFS (P_DONTCARE) | ||
| 25 | #define P_SPORT1_DTPRI (P_DONTCARE) | ||
| 26 | #define P_SPORT1_DTSEC (P_DONTCARE) | ||
| 27 | #define P_SPORT1_TFS (P_DONTCARE) | ||
| 28 | #define P_SPORT1_DRPRI (P_DONTCARE) | ||
| 29 | #define P_SPORT0_DRSEC (P_DONTCARE) | ||
| 30 | #define P_SPORT0_RFS (P_DONTCARE) | ||
| 31 | #define P_SPORT0_DTPRI (P_DONTCARE) | ||
| 32 | #define P_SPORT0_DTSEC (P_DONTCARE) | ||
| 33 | #define P_SPORT0_TFS (P_DONTCARE) | ||
| 34 | #define P_SPORT0_DRPRI (P_DONTCARE) | ||
| 35 | |||
| 36 | #define P_UART0_RX (P_DONTCARE) | ||
| 37 | #define P_UART0_TX (P_DONTCARE) | ||
| 38 | |||
| 39 | #define P_SPI0_MOSI (P_DONTCARE) | ||
| 40 | #define P_SPI0_MISO (P_DONTCARE) | ||
| 41 | #define P_SPI0_SCK (P_DONTCARE) | ||
| 42 | |||
| 43 | #define P_PPI0_D0 (P_DONTCARE) | ||
| 44 | #define P_PPI0_D1 (P_DONTCARE) | ||
| 45 | #define P_PPI0_D2 (P_DONTCARE) | ||
| 46 | #define P_PPI0_D3 (P_DONTCARE) | ||
| 47 | |||
| 48 | #define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0)) | ||
| 49 | #define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1)) | ||
| 50 | |||
| 51 | #define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0)) | ||
| 52 | #define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1)) | ||
| 53 | #define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2)) | ||
| 54 | #define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3)) | ||
| 55 | #define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4)) | ||
| 56 | #define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5)) | ||
| 57 | #define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6)) | ||
| 58 | #define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7)) | ||
| 59 | #define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8)) | ||
| 60 | #define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9)) | ||
| 61 | #define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10)) | ||
| 62 | #define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11)) | ||
| 63 | #define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12)) | ||
| 64 | #define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13)) | ||
| 65 | |||
| 66 | #define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0)) | ||
| 67 | #define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1)) | ||
| 68 | #define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2)) | ||
| 69 | #define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3)) | ||
| 70 | #define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4)) | ||
| 71 | #define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5)) | ||
| 72 | #define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6)) | ||
| 73 | #define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7)) | ||
| 74 | #define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8)) | ||
| 75 | #define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9)) | ||
| 76 | #define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10)) | ||
| 77 | #define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11)) | ||
| 78 | #define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12)) | ||
| 79 | #define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13)) | ||
| 80 | #define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14)) | ||
| 81 | #define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15)) | ||
| 82 | |||
| 83 | #define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) | ||
| 84 | #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) | ||
| 85 | #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) | ||
| 86 | #define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) | ||
| 87 | #define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) | ||
| 88 | #define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) | ||
| 89 | #define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) | ||
| 90 | #define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) | ||
| 91 | #define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) | ||
| 92 | |||
| 93 | #define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) | ||
| 94 | #define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) | ||
| 95 | #define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) | ||
| 96 | #define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) | ||
| 97 | #define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) | ||
| 98 | #define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) | ||
| 99 | #define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) | ||
| 100 | #define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) | ||
| 101 | #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) | ||
| 102 | #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) | ||
| 103 | #define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) | ||
| 104 | #define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) | ||
| 105 | |||
| 106 | #endif /* _MACH_PORTMUX_H_ */ | ||
diff --git a/arch/blackfin/mach-bf538/ints-priority.c b/arch/blackfin/mach-bf538/ints-priority.c new file mode 100644 index 000000000000..70d17e550e05 --- /dev/null +++ b/arch/blackfin/mach-bf538/ints-priority.c | |||
| @@ -0,0 +1,94 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf538/ints-priority.c | ||
| 3 | * Based on: arch/blackfin/mach-bf533/ints-priority.c | ||
| 4 | * Author: Michael Hennerich | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: Set up the interrupt priorities | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2008 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/module.h> | ||
| 31 | #include <linux/irq.h> | ||
| 32 | #include <asm/blackfin.h> | ||
| 33 | |||
| 34 | void __init program_IAR(void) | ||
| 35 | { | ||
| 36 | |||
| 37 | /* Program the IAR0 Register with the configured priority */ | ||
| 38 | bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | | ||
| 39 | ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) | | ||
| 40 | ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) | | ||
| 41 | ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | | ||
| 42 | ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) | | ||
| 43 | ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) | | ||
| 44 | ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) | | ||
| 45 | ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS)); | ||
| 46 | |||
| 47 | bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) | | ||
| 48 | ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) | | ||
| 49 | ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) | | ||
| 50 | ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) | | ||
| 51 | ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) | | ||
| 52 | ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) | | ||
| 53 | ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) | | ||
| 54 | ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS)); | ||
| 55 | |||
| 56 | bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | | ||
| 57 | ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) | | ||
| 58 | ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) | | ||
| 59 | ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) | | ||
| 60 | ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) | | ||
| 61 | ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) | | ||
| 62 | ((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) | | ||
| 63 | ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS)); | ||
| 64 | |||
| 65 | bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | | ||
| 66 | ((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) | | ||
| 67 | ((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) | | ||
| 68 | ((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) | | ||
| 69 | ((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) | | ||
| 70 | ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) | | ||
| 71 | ((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS)); | ||
| 72 | |||
| 73 | bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) | | ||
| 74 | ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) | | ||
| 75 | ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) | | ||
| 76 | ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) | | ||
| 77 | ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) | | ||
| 78 | ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS)); | ||
| 79 | |||
| 80 | bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) | | ||
| 81 | ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) | | ||
| 82 | ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) | | ||
| 83 | ((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) | | ||
| 84 | ((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) | | ||
| 85 | ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) | | ||
| 86 | ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) | | ||
| 87 | ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS)); | ||
| 88 | |||
| 89 | bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) | | ||
| 90 | ((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) | | ||
| 91 | ((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS)); | ||
| 92 | |||
| 93 | SSYNC(); | ||
| 94 | } | ||
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig index 1bfcd8f646ab..dcf657159051 100644 --- a/arch/blackfin/mach-bf548/Kconfig +++ b/arch/blackfin/mach-bf548/Kconfig | |||
| @@ -250,7 +250,7 @@ config IRQ_OTPSEC | |||
| 250 | default 11 | 250 | default 11 |
| 251 | config IRQ_TIMER0 | 251 | config IRQ_TIMER0 |
| 252 | int "IRQ_TIMER0" | 252 | int "IRQ_TIMER0" |
| 253 | default 11 | 253 | default 8 |
| 254 | config IRQ_TIMER1 | 254 | config IRQ_TIMER1 |
| 255 | int "IRQ_TIMER1" | 255 | int "IRQ_TIMER1" |
| 256 | default 11 | 256 | default 11 |
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile index 68e5478e95a9..56994b675f9c 100644 --- a/arch/blackfin/mach-bf548/Makefile +++ b/arch/blackfin/mach-bf548/Makefile | |||
| @@ -2,6 +2,4 @@ | |||
| 2 | # arch/blackfin/mach-bf537/Makefile | 2 | # arch/blackfin/mach-bf537/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | extra-y := head.o | ||
| 6 | |||
| 7 | obj-y := ints-priority.o dma.o | 5 | obj-y := ints-priority.o dma.o |
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index 24192aaa9275..f53ad682530b 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <linux/platform_device.h> | 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/mtd/mtd.h> | 33 | #include <linux/mtd/mtd.h> |
| 34 | #include <linux/mtd/partitions.h> | 34 | #include <linux/mtd/partitions.h> |
| 35 | #include <linux/mtd/physmap.h> | ||
| 35 | #include <linux/spi/spi.h> | 36 | #include <linux/spi/spi.h> |
| 36 | #include <linux/spi/flash.h> | 37 | #include <linux/spi/flash.h> |
| 37 | #include <linux/irq.h> | 38 | #include <linux/irq.h> |
| @@ -42,6 +43,7 @@ | |||
| 42 | #include <asm/gpio.h> | 43 | #include <asm/gpio.h> |
| 43 | #include <asm/nand.h> | 44 | #include <asm/nand.h> |
| 44 | #include <asm/portmux.h> | 45 | #include <asm/portmux.h> |
| 46 | #include <asm/bfin_sdh.h> | ||
| 45 | #include <mach/bf54x_keys.h> | 47 | #include <mach/bf54x_keys.h> |
| 46 | #include <asm/dpmc.h> | 48 | #include <asm/dpmc.h> |
| 47 | #include <linux/input.h> | 49 | #include <linux/input.h> |
| @@ -186,44 +188,107 @@ static struct platform_device bfin_uart_device = { | |||
| 186 | #endif | 188 | #endif |
| 187 | 189 | ||
| 188 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 190 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 189 | static struct resource bfin_sir_resources[] = { | ||
| 190 | #ifdef CONFIG_BFIN_SIR0 | 191 | #ifdef CONFIG_BFIN_SIR0 |
| 192 | static struct resource bfin_sir0_resources[] = { | ||
| 191 | { | 193 | { |
| 192 | .start = 0xFFC00400, | 194 | .start = 0xFFC00400, |
| 193 | .end = 0xFFC004FF, | 195 | .end = 0xFFC004FF, |
| 194 | .flags = IORESOURCE_MEM, | 196 | .flags = IORESOURCE_MEM, |
| 195 | }, | 197 | }, |
| 198 | { | ||
| 199 | .start = IRQ_UART0_RX, | ||
| 200 | .end = IRQ_UART0_RX+1, | ||
| 201 | .flags = IORESOURCE_IRQ, | ||
| 202 | }, | ||
| 203 | { | ||
| 204 | .start = CH_UART0_RX, | ||
| 205 | .end = CH_UART0_RX+1, | ||
| 206 | .flags = IORESOURCE_DMA, | ||
| 207 | }, | ||
| 208 | }; | ||
| 209 | static struct platform_device bfin_sir0_device = { | ||
| 210 | .name = "bfin_sir", | ||
| 211 | .id = 0, | ||
| 212 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 213 | .resource = bfin_sir0_resources, | ||
| 214 | }; | ||
| 196 | #endif | 215 | #endif |
| 197 | #ifdef CONFIG_BFIN_SIR1 | 216 | #ifdef CONFIG_BFIN_SIR1 |
| 217 | static struct resource bfin_sir1_resources[] = { | ||
| 198 | { | 218 | { |
| 199 | .start = 0xFFC02000, | 219 | .start = 0xFFC02000, |
| 200 | .end = 0xFFC020FF, | 220 | .end = 0xFFC020FF, |
| 201 | .flags = IORESOURCE_MEM, | 221 | .flags = IORESOURCE_MEM, |
| 202 | }, | 222 | }, |
| 223 | { | ||
| 224 | .start = IRQ_UART1_RX, | ||
| 225 | .end = IRQ_UART1_RX+1, | ||
| 226 | .flags = IORESOURCE_IRQ, | ||
| 227 | }, | ||
| 228 | { | ||
| 229 | .start = CH_UART1_RX, | ||
| 230 | .end = CH_UART1_RX+1, | ||
| 231 | .flags = IORESOURCE_DMA, | ||
| 232 | }, | ||
| 233 | }; | ||
| 234 | static struct platform_device bfin_sir1_device = { | ||
| 235 | .name = "bfin_sir", | ||
| 236 | .id = 1, | ||
| 237 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | ||
| 238 | .resource = bfin_sir1_resources, | ||
| 239 | }; | ||
| 203 | #endif | 240 | #endif |
| 204 | #ifdef CONFIG_BFIN_SIR2 | 241 | #ifdef CONFIG_BFIN_SIR2 |
| 242 | static struct resource bfin_sir2_resources[] = { | ||
| 205 | { | 243 | { |
| 206 | .start = 0xFFC02100, | 244 | .start = 0xFFC02100, |
| 207 | .end = 0xFFC021FF, | 245 | .end = 0xFFC021FF, |
| 208 | .flags = IORESOURCE_MEM, | 246 | .flags = IORESOURCE_MEM, |
| 209 | }, | 247 | }, |
| 248 | { | ||
| 249 | .start = IRQ_UART2_RX, | ||
| 250 | .end = IRQ_UART2_RX+1, | ||
| 251 | .flags = IORESOURCE_IRQ, | ||
| 252 | }, | ||
| 253 | { | ||
| 254 | .start = CH_UART2_RX, | ||
| 255 | .end = CH_UART2_RX+1, | ||
| 256 | .flags = IORESOURCE_DMA, | ||
| 257 | }, | ||
| 258 | }; | ||
| 259 | static struct platform_device bfin_sir2_device = { | ||
| 260 | .name = "bfin_sir", | ||
| 261 | .id = 2, | ||
| 262 | .num_resources = ARRAY_SIZE(bfin_sir2_resources), | ||
| 263 | .resource = bfin_sir2_resources, | ||
| 264 | }; | ||
| 210 | #endif | 265 | #endif |
| 211 | #ifdef CONFIG_BFIN_SIR3 | 266 | #ifdef CONFIG_BFIN_SIR3 |
| 267 | static struct resource bfin_sir3_resources[] = { | ||
| 212 | { | 268 | { |
| 213 | .start = 0xFFC03100, | 269 | .start = 0xFFC03100, |
| 214 | .end = 0xFFC031FF, | 270 | .end = 0xFFC031FF, |
| 215 | .flags = IORESOURCE_MEM, | 271 | .flags = IORESOURCE_MEM, |
| 216 | }, | 272 | }, |
| 217 | #endif | 273 | { |
| 274 | .start = IRQ_UART3_RX, | ||
| 275 | .end = IRQ_UART3_RX+1, | ||
| 276 | .flags = IORESOURCE_IRQ, | ||
| 277 | }, | ||
| 278 | { | ||
| 279 | .start = CH_UART3_RX, | ||
| 280 | .end = CH_UART3_RX+1, | ||
| 281 | .flags = IORESOURCE_DMA, | ||
| 282 | }, | ||
| 218 | }; | 283 | }; |
| 219 | 284 | static struct platform_device bfin_sir3_device = { | |
| 220 | static struct platform_device bfin_sir_device = { | ||
| 221 | .name = "bfin_sir", | 285 | .name = "bfin_sir", |
| 222 | .id = 0, | 286 | .id = 3, |
| 223 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 287 | .num_resources = ARRAY_SIZE(bfin_sir3_resources), |
| 224 | .resource = bfin_sir_resources, | 288 | .resource = bfin_sir3_resources, |
| 225 | }; | 289 | }; |
| 226 | #endif | 290 | #endif |
| 291 | #endif | ||
| 227 | 292 | ||
| 228 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | 293 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
| 229 | static struct resource smsc911x_resources[] = { | 294 | static struct resource smsc911x_resources[] = { |
| @@ -271,8 +336,8 @@ static struct musb_hdrc_config musb_config = { | |||
| 271 | .dyn_fifo = 0, | 336 | .dyn_fifo = 0, |
| 272 | .soft_con = 1, | 337 | .soft_con = 1, |
| 273 | .dma = 1, | 338 | .dma = 1, |
| 274 | .num_eps = 7, | 339 | .num_eps = 8, |
| 275 | .dma_channels = 7, | 340 | .dma_channels = 8, |
| 276 | .gpio_vrsel = GPIO_PH6, | 341 | .gpio_vrsel = GPIO_PH6, |
| 277 | }; | 342 | }; |
| 278 | 343 | ||
| @@ -302,6 +367,19 @@ static struct platform_device musb_device = { | |||
| 302 | }; | 367 | }; |
| 303 | #endif | 368 | #endif |
| 304 | 369 | ||
| 370 | static struct resource bfin_gpios_resources = { | ||
| 371 | .start = 0, | ||
| 372 | .end = MAX_BLACKFIN_GPIOS - 1, | ||
| 373 | .flags = IORESOURCE_IRQ, | ||
| 374 | }; | ||
| 375 | |||
| 376 | static struct platform_device bfin_gpios_device = { | ||
| 377 | .name = "simple-gpio", | ||
| 378 | .id = -1, | ||
| 379 | .num_resources = 1, | ||
| 380 | .resource = &bfin_gpios_resources, | ||
| 381 | }; | ||
| 382 | |||
| 305 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) | 383 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) |
| 306 | static struct resource bfin_atapi_resources[] = { | 384 | static struct resource bfin_atapi_resources[] = { |
| 307 | { | 385 | { |
| @@ -372,9 +450,58 @@ static struct platform_device bf5xx_nand_device = { | |||
| 372 | #endif | 450 | #endif |
| 373 | 451 | ||
| 374 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) | 452 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) |
| 453 | static struct bfin_sd_host bfin_sdh_data = { | ||
| 454 | .dma_chan = CH_SDH, | ||
| 455 | .irq_int0 = IRQ_SDH_MASK0, | ||
| 456 | .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, | ||
| 457 | }; | ||
| 458 | |||
| 375 | static struct platform_device bf54x_sdh_device = { | 459 | static struct platform_device bf54x_sdh_device = { |
| 376 | .name = "bfin-sdh", | 460 | .name = "bfin-sdh", |
| 377 | .id = 0, | 461 | .id = 0, |
| 462 | .dev = { | ||
| 463 | .platform_data = &bfin_sdh_data, | ||
| 464 | }, | ||
| 465 | }; | ||
| 466 | #endif | ||
| 467 | |||
| 468 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
| 469 | static struct mtd_partition para_partitions[] = { | ||
| 470 | { | ||
| 471 | .name = "bootloader(nor)", | ||
| 472 | .size = 0x40000, | ||
| 473 | .offset = 0, | ||
| 474 | }, { | ||
| 475 | .name = "linux kernel(nor)", | ||
| 476 | .size = 0x400000, | ||
| 477 | .offset = MTDPART_OFS_APPEND, | ||
| 478 | }, { | ||
| 479 | .name = "file system(nor)", | ||
| 480 | .size = MTDPART_SIZ_FULL, | ||
| 481 | .offset = MTDPART_OFS_APPEND, | ||
| 482 | } | ||
| 483 | }; | ||
| 484 | |||
| 485 | static struct physmap_flash_data para_flash_data = { | ||
| 486 | .width = 2, | ||
| 487 | .parts = para_partitions, | ||
| 488 | .nr_parts = ARRAY_SIZE(para_partitions), | ||
| 489 | }; | ||
| 490 | |||
| 491 | static struct resource para_flash_resource = { | ||
| 492 | .start = 0x20000000, | ||
| 493 | .end = 0x207fffff, | ||
| 494 | .flags = IORESOURCE_MEM, | ||
| 495 | }; | ||
| 496 | |||
| 497 | static struct platform_device para_flash_device = { | ||
| 498 | .name = "physmap-flash", | ||
| 499 | .id = 0, | ||
| 500 | .dev = { | ||
| 501 | .platform_data = ¶_flash_data, | ||
| 502 | }, | ||
| 503 | .num_resources = 1, | ||
| 504 | .resource = ¶_flash_resource, | ||
| 378 | }; | 505 | }; |
| 379 | #endif | 506 | #endif |
| 380 | 507 | ||
| @@ -642,7 +769,18 @@ static struct platform_device *cm_bf548_devices[] __initdata = { | |||
| 642 | #endif | 769 | #endif |
| 643 | 770 | ||
| 644 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 771 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 645 | &bfin_sir_device, | 772 | #ifdef CONFIG_BFIN_SIR0 |
| 773 | &bfin_sir0_device, | ||
| 774 | #endif | ||
| 775 | #ifdef CONFIG_BFIN_SIR1 | ||
| 776 | &bfin_sir1_device, | ||
| 777 | #endif | ||
| 778 | #ifdef CONFIG_BFIN_SIR2 | ||
| 779 | &bfin_sir2_device, | ||
| 780 | #endif | ||
| 781 | #ifdef CONFIG_BFIN_SIR3 | ||
| 782 | &bfin_sir3_device, | ||
| 783 | #endif | ||
| 646 | #endif | 784 | #endif |
| 647 | 785 | ||
| 648 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) | 786 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) |
| @@ -679,7 +817,7 @@ static struct platform_device *cm_bf548_devices[] __initdata = { | |||
| 679 | #endif | 817 | #endif |
| 680 | 818 | ||
| 681 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | 819 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
| 682 | /* &i2c_bfin_twi0_device, */ | 820 | &i2c_bfin_twi0_device, |
| 683 | #if !defined(CONFIG_BF542) | 821 | #if !defined(CONFIG_BF542) |
| 684 | &i2c_bfin_twi1_device, | 822 | &i2c_bfin_twi1_device, |
| 685 | #endif | 823 | #endif |
| @@ -688,6 +826,12 @@ static struct platform_device *cm_bf548_devices[] __initdata = { | |||
| 688 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | 826 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
| 689 | &bfin_device_gpiokeys, | 827 | &bfin_device_gpiokeys, |
| 690 | #endif | 828 | #endif |
| 829 | |||
| 830 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
| 831 | ¶_flash_device, | ||
| 832 | #endif | ||
| 833 | |||
| 834 | &bfin_gpios_device, | ||
| 691 | }; | 835 | }; |
| 692 | 836 | ||
| 693 | static int __init cm_bf548_init(void) | 837 | static int __init cm_bf548_init(void) |
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 5288187a3ace..309c16014cae 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | #include <asm/nand.h> | 45 | #include <asm/nand.h> |
| 46 | #include <asm/dpmc.h> | 46 | #include <asm/dpmc.h> |
| 47 | #include <asm/portmux.h> | 47 | #include <asm/portmux.h> |
| 48 | #include <asm/bfin_sdh.h> | ||
| 48 | #include <mach/bf54x_keys.h> | 49 | #include <mach/bf54x_keys.h> |
| 49 | #include <linux/input.h> | 50 | #include <linux/input.h> |
| 50 | #include <linux/spi/ad7877.h> | 51 | #include <linux/spi/ad7877.h> |
| @@ -52,16 +53,16 @@ | |||
| 52 | /* | 53 | /* |
| 53 | * Name the Board for the /proc/cpuinfo | 54 | * Name the Board for the /proc/cpuinfo |
| 54 | */ | 55 | */ |
| 55 | const char bfin_board_name[] = "ADSP-BF548-EZKIT"; | 56 | const char bfin_board_name[] = "ADI BF548-EZKIT"; |
| 56 | 57 | ||
| 57 | /* | 58 | /* |
| 58 | * Driver needs to know address, irq and flag pin. | 59 | * Driver needs to know address, irq and flag pin. |
| 59 | */ | 60 | */ |
| 60 | 61 | ||
| 61 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | 62 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
| 62 | static struct resource bfin_isp1761_resources[] = { | 63 | #include <linux/usb/isp1760.h> |
| 64 | static struct resource bfin_isp1760_resources[] = { | ||
| 63 | [0] = { | 65 | [0] = { |
| 64 | .name = "isp1761-regs", | ||
| 65 | .start = 0x2C0C0000, | 66 | .start = 0x2C0C0000, |
| 66 | .end = 0x2C0C0000 + 0xfffff, | 67 | .end = 0x2C0C0000 + 0xfffff, |
| 67 | .flags = IORESOURCE_MEM, | 68 | .flags = IORESOURCE_MEM, |
| @@ -73,32 +74,25 @@ static struct resource bfin_isp1761_resources[] = { | |||
| 73 | }, | 74 | }, |
| 74 | }; | 75 | }; |
| 75 | 76 | ||
| 76 | static struct platform_device bfin_isp1761_device = { | 77 | static struct isp1760_platform_data isp1760_priv = { |
| 77 | .name = "isp1761", | 78 | .is_isp1761 = 0, |
| 78 | .id = 0, | 79 | .port1_disable = 0, |
| 79 | .num_resources = ARRAY_SIZE(bfin_isp1761_resources), | 80 | .bus_width_16 = 1, |
| 80 | .resource = bfin_isp1761_resources, | 81 | .port1_otg = 0, |
| 82 | .analog_oc = 0, | ||
| 83 | .dack_polarity_high = 0, | ||
| 84 | .dreq_polarity_high = 0, | ||
| 81 | }; | 85 | }; |
| 82 | 86 | ||
| 83 | static struct platform_device *bfin_isp1761_devices[] = { | 87 | static struct platform_device bfin_isp1760_device = { |
| 84 | &bfin_isp1761_device, | 88 | .name = "isp1760-hcd", |
| 89 | .id = 0, | ||
| 90 | .dev = { | ||
| 91 | .platform_data = &isp1760_priv, | ||
| 92 | }, | ||
| 93 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | ||
| 94 | .resource = bfin_isp1760_resources, | ||
| 85 | }; | 95 | }; |
| 86 | |||
| 87 | int __init bfin_isp1761_init(void) | ||
| 88 | { | ||
| 89 | unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); | ||
| 90 | |||
| 91 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 92 | set_irq_type(bfin_isp1761_resources[1].start, IRQF_TRIGGER_FALLING); | ||
| 93 | |||
| 94 | return platform_add_devices(bfin_isp1761_devices, num_devices); | ||
| 95 | } | ||
| 96 | |||
| 97 | void __exit bfin_isp1761_exit(void) | ||
| 98 | { | ||
| 99 | platform_device_unregister(&bfin_isp1761_device); | ||
| 100 | } | ||
| 101 | arch_initcall(bfin_isp1761_init); | ||
| 102 | #endif | 96 | #endif |
| 103 | 97 | ||
| 104 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) | 98 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) |
| @@ -262,44 +256,107 @@ static struct platform_device bfin_uart_device = { | |||
| 262 | #endif | 256 | #endif |
| 263 | 257 | ||
| 264 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 258 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 265 | static struct resource bfin_sir_resources[] = { | ||
| 266 | #ifdef CONFIG_BFIN_SIR0 | 259 | #ifdef CONFIG_BFIN_SIR0 |
| 260 | static struct resource bfin_sir0_resources[] = { | ||
| 267 | { | 261 | { |
| 268 | .start = 0xFFC00400, | 262 | .start = 0xFFC00400, |
| 269 | .end = 0xFFC004FF, | 263 | .end = 0xFFC004FF, |
| 270 | .flags = IORESOURCE_MEM, | 264 | .flags = IORESOURCE_MEM, |
| 271 | }, | 265 | }, |
| 266 | { | ||
| 267 | .start = IRQ_UART0_RX, | ||
| 268 | .end = IRQ_UART0_RX+1, | ||
| 269 | .flags = IORESOURCE_IRQ, | ||
| 270 | }, | ||
| 271 | { | ||
| 272 | .start = CH_UART0_RX, | ||
| 273 | .end = CH_UART0_RX+1, | ||
| 274 | .flags = IORESOURCE_DMA, | ||
| 275 | }, | ||
| 276 | }; | ||
| 277 | static struct platform_device bfin_sir0_device = { | ||
| 278 | .name = "bfin_sir", | ||
| 279 | .id = 0, | ||
| 280 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 281 | .resource = bfin_sir0_resources, | ||
| 282 | }; | ||
| 272 | #endif | 283 | #endif |
| 273 | #ifdef CONFIG_BFIN_SIR1 | 284 | #ifdef CONFIG_BFIN_SIR1 |
| 285 | static struct resource bfin_sir1_resources[] = { | ||
| 274 | { | 286 | { |
| 275 | .start = 0xFFC02000, | 287 | .start = 0xFFC02000, |
| 276 | .end = 0xFFC020FF, | 288 | .end = 0xFFC020FF, |
| 277 | .flags = IORESOURCE_MEM, | 289 | .flags = IORESOURCE_MEM, |
| 278 | }, | 290 | }, |
| 291 | { | ||
| 292 | .start = IRQ_UART1_RX, | ||
| 293 | .end = IRQ_UART1_RX+1, | ||
| 294 | .flags = IORESOURCE_IRQ, | ||
| 295 | }, | ||
| 296 | { | ||
| 297 | .start = CH_UART1_RX, | ||
| 298 | .end = CH_UART1_RX+1, | ||
| 299 | .flags = IORESOURCE_DMA, | ||
| 300 | }, | ||
| 301 | }; | ||
| 302 | static struct platform_device bfin_sir1_device = { | ||
| 303 | .name = "bfin_sir", | ||
| 304 | .id = 1, | ||
| 305 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | ||
| 306 | .resource = bfin_sir1_resources, | ||
| 307 | }; | ||
| 279 | #endif | 308 | #endif |
| 280 | #ifdef CONFIG_BFIN_SIR2 | 309 | #ifdef CONFIG_BFIN_SIR2 |
| 310 | static struct resource bfin_sir2_resources[] = { | ||
| 281 | { | 311 | { |
| 282 | .start = 0xFFC02100, | 312 | .start = 0xFFC02100, |
| 283 | .end = 0xFFC021FF, | 313 | .end = 0xFFC021FF, |
| 284 | .flags = IORESOURCE_MEM, | 314 | .flags = IORESOURCE_MEM, |
| 285 | }, | 315 | }, |
| 316 | { | ||
| 317 | .start = IRQ_UART2_RX, | ||
| 318 | .end = IRQ_UART2_RX+1, | ||
| 319 | .flags = IORESOURCE_IRQ, | ||
| 320 | }, | ||
| 321 | { | ||
| 322 | .start = CH_UART2_RX, | ||
| 323 | .end = CH_UART2_RX+1, | ||
| 324 | .flags = IORESOURCE_DMA, | ||
| 325 | }, | ||
| 326 | }; | ||
| 327 | static struct platform_device bfin_sir2_device = { | ||
| 328 | .name = "bfin_sir", | ||
| 329 | .id = 2, | ||
| 330 | .num_resources = ARRAY_SIZE(bfin_sir2_resources), | ||
| 331 | .resource = bfin_sir2_resources, | ||
| 332 | }; | ||
| 286 | #endif | 333 | #endif |
| 287 | #ifdef CONFIG_BFIN_SIR3 | 334 | #ifdef CONFIG_BFIN_SIR3 |
| 335 | static struct resource bfin_sir3_resources[] = { | ||
| 288 | { | 336 | { |
| 289 | .start = 0xFFC03100, | 337 | .start = 0xFFC03100, |
| 290 | .end = 0xFFC031FF, | 338 | .end = 0xFFC031FF, |
| 291 | .flags = IORESOURCE_MEM, | 339 | .flags = IORESOURCE_MEM, |
| 292 | }, | 340 | }, |
| 293 | #endif | 341 | { |
| 342 | .start = IRQ_UART3_RX, | ||
| 343 | .end = IRQ_UART3_RX+1, | ||
| 344 | .flags = IORESOURCE_IRQ, | ||
| 345 | }, | ||
| 346 | { | ||
| 347 | .start = CH_UART3_RX, | ||
| 348 | .end = CH_UART3_RX+1, | ||
| 349 | .flags = IORESOURCE_DMA, | ||
| 350 | }, | ||
| 294 | }; | 351 | }; |
| 295 | 352 | static struct platform_device bfin_sir3_device = { | |
| 296 | static struct platform_device bfin_sir_device = { | ||
| 297 | .name = "bfin_sir", | 353 | .name = "bfin_sir", |
| 298 | .id = 0, | 354 | .id = 3, |
| 299 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 355 | .num_resources = ARRAY_SIZE(bfin_sir3_resources), |
| 300 | .resource = bfin_sir_resources, | 356 | .resource = bfin_sir3_resources, |
| 301 | }; | 357 | }; |
| 302 | #endif | 358 | #endif |
| 359 | #endif | ||
| 303 | 360 | ||
| 304 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | 361 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
| 305 | static struct resource smsc911x_resources[] = { | 362 | static struct resource smsc911x_resources[] = { |
| @@ -347,8 +404,8 @@ static struct musb_hdrc_config musb_config = { | |||
| 347 | .dyn_fifo = 0, | 404 | .dyn_fifo = 0, |
| 348 | .soft_con = 1, | 405 | .soft_con = 1, |
| 349 | .dma = 1, | 406 | .dma = 1, |
| 350 | .num_eps = 7, | 407 | .num_eps = 8, |
| 351 | .dma_channels = 7, | 408 | .dma_channels = 8, |
| 352 | .gpio_vrsel = GPIO_PE7, | 409 | .gpio_vrsel = GPIO_PE7, |
| 353 | }; | 410 | }; |
| 354 | 411 | ||
| @@ -448,9 +505,19 @@ static struct platform_device bf5xx_nand_device = { | |||
| 448 | #endif | 505 | #endif |
| 449 | 506 | ||
| 450 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) | 507 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) |
| 508 | |||
| 509 | static struct bfin_sd_host bfin_sdh_data = { | ||
| 510 | .dma_chan = CH_SDH, | ||
| 511 | .irq_int0 = IRQ_SDH_MASK0, | ||
| 512 | .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, | ||
| 513 | }; | ||
| 514 | |||
| 451 | static struct platform_device bf54x_sdh_device = { | 515 | static struct platform_device bf54x_sdh_device = { |
| 452 | .name = "bfin-sdh", | 516 | .name = "bfin-sdh", |
| 453 | .id = 0, | 517 | .id = 0, |
| 518 | .dev = { | ||
| 519 | .platform_data = &bfin_sdh_data, | ||
| 520 | }, | ||
| 454 | }; | 521 | }; |
| 455 | #endif | 522 | #endif |
| 456 | 523 | ||
| @@ -589,7 +656,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 589 | { | 656 | { |
| 590 | .modalias = "ad7877", | 657 | .modalias = "ad7877", |
| 591 | .platform_data = &bfin_ad7877_ts_info, | 658 | .platform_data = &bfin_ad7877_ts_info, |
| 592 | .irq = IRQ_PJ11, /* newer boards (Rev 1.4+) use IRQ_PB4 */ | 659 | .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ |
| 593 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | 660 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ |
| 594 | .bus_num = 0, | 661 | .bus_num = 0, |
| 595 | .chip_select = 2, | 662 | .chip_select = 2, |
| @@ -812,7 +879,18 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
| 812 | #endif | 879 | #endif |
| 813 | 880 | ||
| 814 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 881 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 815 | &bfin_sir_device, | 882 | #ifdef CONFIG_BFIN_SIR0 |
| 883 | &bfin_sir0_device, | ||
| 884 | #endif | ||
| 885 | #ifdef CONFIG_BFIN_SIR1 | ||
| 886 | &bfin_sir1_device, | ||
| 887 | #endif | ||
| 888 | #ifdef CONFIG_BFIN_SIR2 | ||
| 889 | &bfin_sir2_device, | ||
| 890 | #endif | ||
| 891 | #ifdef CONFIG_BFIN_SIR3 | ||
| 892 | &bfin_sir3_device, | ||
| 893 | #endif | ||
| 816 | #endif | 894 | #endif |
| 817 | 895 | ||
| 818 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) | 896 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) |
| @@ -827,6 +905,10 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
| 827 | &musb_device, | 905 | &musb_device, |
| 828 | #endif | 906 | #endif |
| 829 | 907 | ||
| 908 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | ||
| 909 | &bfin_isp1760_device, | ||
| 910 | #endif | ||
| 911 | |||
| 830 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) | 912 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) |
| 831 | &bfin_atapi_device, | 913 | &bfin_atapi_device, |
| 832 | #endif | 914 | #endif |
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c index 74730eb8ae1b..535980652bf6 100644 --- a/arch/blackfin/mach-bf548/dma.c +++ b/arch/blackfin/mach-bf548/dma.c | |||
| @@ -32,7 +32,7 @@ | |||
| 32 | #include <asm/blackfin.h> | 32 | #include <asm/blackfin.h> |
| 33 | #include <asm/dma.h> | 33 | #include <asm/dma.h> |
| 34 | 34 | ||
| 35 | struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { | 35 | struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { |
| 36 | (struct dma_register *) DMA0_NEXT_DESC_PTR, | 36 | (struct dma_register *) DMA0_NEXT_DESC_PTR, |
| 37 | (struct dma_register *) DMA1_NEXT_DESC_PTR, | 37 | (struct dma_register *) DMA1_NEXT_DESC_PTR, |
| 38 | (struct dma_register *) DMA2_NEXT_DESC_PTR, | 38 | (struct dma_register *) DMA2_NEXT_DESC_PTR, |
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S deleted file mode 100644 index 93b361dff27b..000000000000 --- a/arch/blackfin/mach-bf548/head.S +++ /dev/null | |||
| @@ -1,158 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf548/head.S | ||
| 3 | * Based on: arch/blackfin/mach-bf537/head.S | ||
| 4 | * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne | ||
| 5 | * | ||
| 6 | * Created: 1998 | ||
| 7 | * Description: Startup code for Blackfin BF548 | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2007 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/linkage.h> | ||
| 31 | #include <linux/init.h> | ||
| 32 | #include <asm/blackfin.h> | ||
| 33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 34 | #include <asm/clocks.h> | ||
| 35 | #include <mach/mem_init.h> | ||
| 36 | #endif | ||
| 37 | |||
| 38 | .section .l1.text | ||
| 39 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 40 | ENTRY(_start_dma_code) | ||
| 41 | |||
| 42 | /* Enable PHY CLK buffer output */ | ||
| 43 | p0.h = hi(VR_CTL); | ||
| 44 | p0.l = lo(VR_CTL); | ||
| 45 | r0.l = w[p0]; | ||
| 46 | bitset(r0, 14); | ||
| 47 | w[p0] = r0.l; | ||
| 48 | ssync; | ||
| 49 | |||
| 50 | p0.h = hi(SIC_IWR0); | ||
| 51 | p0.l = lo(SIC_IWR0); | ||
| 52 | r0.l = 0x1; | ||
| 53 | r0.h = 0x0; | ||
| 54 | [p0] = r0; | ||
| 55 | SSYNC; | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Set PLL_CTL | ||
| 59 | * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors | ||
| 60 | * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK | ||
| 61 | * - [7] = output delay (add 200ps of delay to mem signals) | ||
| 62 | * - [6] = input delay (add 200ps of input delay to mem signals) | ||
| 63 | * - [5] = PDWN : 1=All Clocks off | ||
| 64 | * - [3] = STOPCK : 1=Core Clock off | ||
| 65 | * - [1] = PLL_OFF : 1=Disable Power to PLL | ||
| 66 | * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL | ||
| 67 | * all other bits set to zero | ||
| 68 | */ | ||
| 69 | |||
| 70 | p0.h = hi(PLL_LOCKCNT); | ||
| 71 | p0.l = lo(PLL_LOCKCNT); | ||
| 72 | r0 = 0x300(Z); | ||
| 73 | w[p0] = r0.l; | ||
| 74 | ssync; | ||
| 75 | |||
| 76 | /* enable self refresh via SRREQ */ | ||
| 77 | P2.H = hi(EBIU_RSTCTL); | ||
| 78 | P2.L = lo(EBIU_RSTCTL); | ||
| 79 | R0 = [P2]; | ||
| 80 | BITSET (R0, 3); | ||
| 81 | [P2] = R0; | ||
| 82 | SSYNC; | ||
| 83 | |||
| 84 | /* wait for SRACK bit to be set */ | ||
| 85 | .LSRR_MODE: | ||
| 86 | R0 = [P2]; | ||
| 87 | CC = BITTST(R0, 4); | ||
| 88 | if !CC JUMP .LSRR_MODE; | ||
| 89 | |||
| 90 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ | ||
| 91 | r0 = r0 << 9; /* Shift it over, */ | ||
| 92 | r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ | ||
| 93 | r0 = r1 | r0; | ||
| 94 | r1 = PLL_BYPASS; /* Bypass the PLL? */ | ||
| 95 | r1 = r1 << 8; /* Shift it over */ | ||
| 96 | r0 = r1 | r0; /* add them all together */ | ||
| 97 | #ifdef ANOMALY_05000265 | ||
| 98 | BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */ | ||
| 99 | #endif | ||
| 100 | |||
| 101 | p0.h = hi(PLL_CTL); | ||
| 102 | p0.l = lo(PLL_CTL); /* Load the address */ | ||
| 103 | cli r2; /* Disable interrupts */ | ||
| 104 | ssync; | ||
| 105 | w[p0] = r0.l; /* Set the value */ | ||
| 106 | idle; /* Wait for the PLL to stablize */ | ||
| 107 | sti r2; /* Enable interrupts */ | ||
| 108 | |||
| 109 | .Lcheck_again: | ||
| 110 | p0.h = hi(PLL_STAT); | ||
| 111 | p0.l = lo(PLL_STAT); | ||
| 112 | R0 = W[P0](Z); | ||
| 113 | CC = BITTST(R0,5); | ||
| 114 | if ! CC jump .Lcheck_again; | ||
| 115 | |||
| 116 | /* Configure SCLK & CCLK Dividers */ | ||
| 117 | r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | ||
| 118 | p0.h = hi(PLL_DIV); | ||
| 119 | p0.l = lo(PLL_DIV); | ||
| 120 | w[p0] = r0.l; | ||
| 121 | ssync; | ||
| 122 | |||
| 123 | /* disable self refresh by clearing SRREQ */ | ||
| 124 | P2.H = hi(EBIU_RSTCTL); | ||
| 125 | P2.L = lo(EBIU_RSTCTL); | ||
| 126 | R0 = [P2]; | ||
| 127 | CC = BITTST(R0, 0); | ||
| 128 | if CC jump .Lskipddrrst; | ||
| 129 | BITSET (R0, 0); | ||
| 130 | .Lskipddrrst: | ||
| 131 | BITCLR (R0, 3); | ||
| 132 | [P2] = R0; | ||
| 133 | SSYNC; | ||
| 134 | |||
| 135 | p0.l = lo(EBIU_DDRCTL0); | ||
| 136 | p0.h = hi(EBIU_DDRCTL0); | ||
| 137 | r0.l = lo(mem_DDRCTL0); | ||
| 138 | r0.h = hi(mem_DDRCTL0); | ||
| 139 | [p0] = r0; | ||
| 140 | ssync; | ||
| 141 | |||
| 142 | p0.l = lo(EBIU_DDRCTL1); | ||
| 143 | p0.h = hi(EBIU_DDRCTL1); | ||
| 144 | r0.l = lo(mem_DDRCTL1); | ||
| 145 | r0.h = hi(mem_DDRCTL1); | ||
| 146 | [p0] = r0; | ||
| 147 | ssync; | ||
| 148 | |||
| 149 | p0.l = lo(EBIU_DDRCTL2); | ||
| 150 | p0.h = hi(EBIU_DDRCTL2); | ||
| 151 | r0.l = lo(mem_DDRCTL2); | ||
| 152 | r0.h = hi(mem_DDRCTL2); | ||
| 153 | [p0] = r0; | ||
| 154 | ssync; | ||
| 155 | |||
| 156 | RTS; | ||
| 157 | ENDPROC(_start_dma_code) | ||
| 158 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | ||
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 816b09278f62..3b5430999f4f 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h | |||
| @@ -157,6 +157,8 @@ | |||
| 157 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) | 157 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) |
| 158 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | 158 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
| 159 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) | 159 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) |
| 160 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | ||
| 161 | #define ANOMALY_05000443 (1) | ||
| 160 | 162 | ||
| 161 | /* Anomalies that don't exist on this proc */ | 163 | /* Anomalies that don't exist on this proc */ |
| 162 | #define ANOMALY_05000125 (0) | 164 | #define ANOMALY_05000125 (0) |
| @@ -173,5 +175,8 @@ | |||
| 173 | #define ANOMALY_05000311 (0) | 175 | #define ANOMALY_05000311 (0) |
| 174 | #define ANOMALY_05000323 (0) | 176 | #define ANOMALY_05000323 (0) |
| 175 | #define ANOMALY_05000363 (0) | 177 | #define ANOMALY_05000363 (0) |
| 178 | #define ANOMALY_05000412 (0) | ||
| 179 | #define ANOMALY_05000432 (0) | ||
| 180 | #define ANOMALY_05000435 (0) | ||
| 176 | 181 | ||
| 177 | #endif | 182 | #endif |
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h index 49f9b403d458..f0e569984810 100644 --- a/arch/blackfin/mach-bf548/include/mach/bf548.h +++ b/arch/blackfin/mach-bf548/include/mach/bf548.h | |||
| @@ -122,7 +122,7 @@ | |||
| 122 | #endif | 122 | #endif |
| 123 | 123 | ||
| 124 | #ifndef CPU | 124 | #ifndef CPU |
| 125 | #error Unknown CPU type - This kernel doesn't seem to be configured properly | 125 | #error "Unknown CPU type - This kernel doesn't seem to be configured properly" |
| 126 | #endif | 126 | #endif |
| 127 | 127 | ||
| 128 | #endif /* __MACH_BF48_H__ */ | 128 | #endif /* __MACH_BF48_H__ */ |
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h b/arch/blackfin/mach-bf548/include/mach/bfin_sir.h deleted file mode 100644 index c41f9cf00268..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/bfin_sir.h +++ /dev/null | |||
| @@ -1,166 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Blackfin Infra-red Driver | ||
| 3 | * | ||
| 4 | * Copyright 2006-2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Enter bugs at http://blackfin.uclinux.org/ | ||
| 7 | * | ||
| 8 | * Licensed under the GPL-2 or later. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/serial.h> | ||
| 13 | #include <asm/dma.h> | ||
| 14 | #include <asm/portmux.h> | ||
| 15 | |||
| 16 | #define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) | ||
| 17 | #define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) | ||
| 18 | #define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET) | ||
| 19 | #define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) | ||
| 20 | #define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) | ||
| 21 | #define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR) | ||
| 22 | #define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) | ||
| 23 | |||
| 24 | #define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) | ||
| 25 | #define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) | ||
| 26 | #define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v) | ||
| 27 | #define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v) | ||
| 28 | #define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) | ||
| 29 | #define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v) | ||
| 30 | #define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) | ||
| 31 | #define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1) | ||
| 32 | #define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) | ||
| 33 | |||
| 34 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 35 | struct dma_rx_buf { | ||
| 36 | char *buf; | ||
| 37 | int head; | ||
| 38 | int tail; | ||
| 39 | }; | ||
| 40 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 41 | |||
| 42 | struct bfin_sir_port { | ||
| 43 | unsigned char __iomem *membase; | ||
| 44 | unsigned int irq; | ||
| 45 | unsigned int lsr; | ||
| 46 | unsigned long clk; | ||
| 47 | struct net_device *dev; | ||
| 48 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 49 | int tx_done; | ||
| 50 | struct dma_rx_buf rx_dma_buf; | ||
| 51 | struct timer_list rx_dma_timer; | ||
| 52 | int rx_dma_nrows; | ||
| 53 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 54 | unsigned int tx_dma_channel; | ||
| 55 | unsigned int rx_dma_channel; | ||
| 56 | }; | ||
| 57 | |||
| 58 | struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; | ||
| 59 | |||
| 60 | struct bfin_sir_port_res { | ||
| 61 | unsigned long base_addr; | ||
| 62 | int irq; | ||
| 63 | unsigned int rx_dma_channel; | ||
| 64 | unsigned int tx_dma_channel; | ||
| 65 | }; | ||
| 66 | |||
| 67 | struct bfin_sir_port_res bfin_sir_port_resource[] = { | ||
| 68 | #ifdef CONFIG_BFIN_SIR0 | ||
| 69 | { | ||
| 70 | 0xFFC00400, | ||
| 71 | IRQ_UART0_RX, | ||
| 72 | CH_UART0_RX, | ||
| 73 | CH_UART0_TX, | ||
| 74 | }, | ||
| 75 | #endif | ||
| 76 | #ifdef CONFIG_BFIN_SIR1 | ||
| 77 | { | ||
| 78 | 0xFFC02000, | ||
| 79 | IRQ_UART1_RX, | ||
| 80 | CH_UART1_RX, | ||
| 81 | CH_UART1_TX, | ||
| 82 | }, | ||
| 83 | #endif | ||
| 84 | #ifdef CONFIG_BFIN_SIR2 | ||
| 85 | { | ||
| 86 | 0xFFC02100, | ||
| 87 | IRQ_UART2_RX, | ||
| 88 | CH_UART2_RX, | ||
| 89 | CH_UART2_TX, | ||
| 90 | }, | ||
| 91 | #endif | ||
| 92 | #ifdef CONFIG_BFIN_SIR3 | ||
| 93 | { | ||
| 94 | 0xFFC03100, | ||
| 95 | IRQ_UART3_RX, | ||
| 96 | CH_UART3_RX, | ||
| 97 | CH_UART3_TX, | ||
| 98 | }, | ||
| 99 | #endif | ||
| 100 | }; | ||
| 101 | |||
| 102 | int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); | ||
| 103 | |||
| 104 | struct bfin_sir_self { | ||
| 105 | struct bfin_sir_port *sir_port; | ||
| 106 | spinlock_t lock; | ||
| 107 | unsigned int open; | ||
| 108 | int speed; | ||
| 109 | int newspeed; | ||
| 110 | |||
| 111 | struct sk_buff *txskb; | ||
| 112 | struct sk_buff *rxskb; | ||
| 113 | struct net_device_stats stats; | ||
| 114 | struct device *dev; | ||
| 115 | struct irlap_cb *irlap; | ||
| 116 | struct qos_info qos; | ||
| 117 | |||
| 118 | iobuff_t tx_buff; | ||
| 119 | iobuff_t rx_buff; | ||
| 120 | |||
| 121 | struct work_struct work; | ||
| 122 | int mtt; | ||
| 123 | }; | ||
| 124 | |||
| 125 | #define DRIVER_NAME "bfin_sir" | ||
| 126 | |||
| 127 | static int bfin_sir_hw_init(void) | ||
| 128 | { | ||
| 129 | int ret = -ENODEV; | ||
| 130 | #ifdef CONFIG_BFIN_SIR0 | ||
| 131 | ret = peripheral_request(P_UART0_TX, DRIVER_NAME); | ||
| 132 | if (ret) | ||
| 133 | return ret; | ||
| 134 | ret = peripheral_request(P_UART0_RX, DRIVER_NAME); | ||
| 135 | if (ret) | ||
| 136 | return ret; | ||
| 137 | #endif | ||
| 138 | |||
| 139 | #ifdef CONFIG_BFIN_SIR1 | ||
| 140 | ret = peripheral_request(P_UART1_TX, DRIVER_NAME); | ||
| 141 | if (ret) | ||
| 142 | return ret; | ||
| 143 | ret = peripheral_request(P_UART1_RX, DRIVER_NAME); | ||
| 144 | if (ret) | ||
| 145 | return ret; | ||
| 146 | #endif | ||
| 147 | |||
| 148 | #ifdef CONFIG_BFIN_SIR2 | ||
| 149 | ret = peripheral_request(P_UART2_TX, DRIVER_NAME); | ||
| 150 | if (ret) | ||
| 151 | return ret; | ||
| 152 | ret = peripheral_request(P_UART2_RX, DRIVER_NAME); | ||
| 153 | if (ret) | ||
| 154 | return ret; | ||
| 155 | #endif | ||
| 156 | |||
| 157 | #ifdef CONFIG_BFIN_SIR3 | ||
| 158 | ret = peripheral_request(P_UART3_TX, DRIVER_NAME); | ||
| 159 | if (ret) | ||
| 160 | return ret; | ||
| 161 | ret = peripheral_request(P_UART3_RX, DRIVER_NAME); | ||
| 162 | if (ret) | ||
| 163 | return ret; | ||
| 164 | #endif | ||
| 165 | return ret; | ||
| 166 | } | ||
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h index d6ee74ac0460..0c0e3e2c3c21 100644 --- a/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h | |||
| @@ -111,7 +111,7 @@ | |||
| 111 | 111 | ||
| 112 | /* UART 0*/ | 112 | /* UART 0*/ |
| 113 | 113 | ||
| 114 | /* DMA Channnel */ | 114 | /* DMA Channel */ |
| 115 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() | 115 | #define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() |
| 116 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) | 116 | #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) |
| 117 | #define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() | 117 | #define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() |
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index 57ac8cb9b1f6..6e636c418cb0 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h | |||
| @@ -34,7 +34,6 @@ | |||
| 34 | #include <asm/blackfin.h> | 34 | #include <asm/blackfin.h> |
| 35 | 35 | ||
| 36 | #include "defBF54x_base.h" | 36 | #include "defBF54x_base.h" |
| 37 | #include <asm/system.h> | ||
| 38 | 37 | ||
| 39 | /* ************************************************************** */ | 38 | /* ************************************************************** */ |
| 40 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ | 39 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ |
| @@ -43,63 +42,9 @@ | |||
| 43 | /* PLL Registers */ | 42 | /* PLL Registers */ |
| 44 | 43 | ||
| 45 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | 44 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 46 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 47 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 48 | { | ||
| 49 | unsigned long flags, iwr0, iwr1, iwr2; | ||
| 50 | |||
| 51 | if (val == bfin_read_PLL_CTL()) | ||
| 52 | return; | ||
| 53 | |||
| 54 | local_irq_save(flags); | ||
| 55 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 56 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 57 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 58 | iwr2 = bfin_read32(SIC_IWR2); | ||
| 59 | /* Only allow PPL Wakeup) */ | ||
| 60 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 61 | bfin_write32(SIC_IWR1, 0); | ||
| 62 | bfin_write32(SIC_IWR2, 0); | ||
| 63 | |||
| 64 | bfin_write16(PLL_CTL, val); | ||
| 65 | SSYNC(); | ||
| 66 | asm("IDLE;"); | ||
| 67 | |||
| 68 | bfin_write32(SIC_IWR0, iwr0); | ||
| 69 | bfin_write32(SIC_IWR1, iwr1); | ||
| 70 | bfin_write32(SIC_IWR2, iwr2); | ||
| 71 | local_irq_restore(flags); | ||
| 72 | } | ||
| 73 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | 45 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 74 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | 46 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) |
| 75 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | 47 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| 76 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 77 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 78 | { | ||
| 79 | unsigned long flags, iwr0, iwr1, iwr2; | ||
| 80 | |||
| 81 | if (val == bfin_read_VR_CTL()) | ||
| 82 | return; | ||
| 83 | |||
| 84 | local_irq_save(flags); | ||
| 85 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 86 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 87 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 88 | iwr2 = bfin_read32(SIC_IWR2); | ||
| 89 | /* Only allow PPL Wakeup) */ | ||
| 90 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 91 | bfin_write32(SIC_IWR1, 0); | ||
| 92 | bfin_write32(SIC_IWR2, 0); | ||
| 93 | |||
| 94 | bfin_write16(VR_CTL, val); | ||
| 95 | SSYNC(); | ||
| 96 | asm("IDLE;"); | ||
| 97 | |||
| 98 | bfin_write32(SIC_IWR0, iwr0); | ||
| 99 | bfin_write32(SIC_IWR1, iwr1); | ||
| 100 | bfin_write32(SIC_IWR2, iwr2); | ||
| 101 | local_irq_restore(flags); | ||
| 102 | } | ||
| 103 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | 48 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 104 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | 49 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) |
| 105 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | 50 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| @@ -2746,5 +2691,64 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 2746 | #define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST | 2691 | #define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST |
| 2747 | #define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST | 2692 | #define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST |
| 2748 | 2693 | ||
| 2694 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 2695 | #include <asm/irq.h> | ||
| 2696 | |||
| 2697 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 2698 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 2699 | { | ||
| 2700 | unsigned long flags, iwr0, iwr1, iwr2; | ||
| 2701 | |||
| 2702 | if (val == bfin_read_PLL_CTL()) | ||
| 2703 | return; | ||
| 2704 | |||
| 2705 | local_irq_save_hw(flags); | ||
| 2706 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 2707 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 2708 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 2709 | iwr2 = bfin_read32(SIC_IWR2); | ||
| 2710 | /* Only allow PPL Wakeup) */ | ||
| 2711 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 2712 | bfin_write32(SIC_IWR1, 0); | ||
| 2713 | bfin_write32(SIC_IWR2, 0); | ||
| 2714 | |||
| 2715 | bfin_write16(PLL_CTL, val); | ||
| 2716 | SSYNC(); | ||
| 2717 | asm("IDLE;"); | ||
| 2718 | |||
| 2719 | bfin_write32(SIC_IWR0, iwr0); | ||
| 2720 | bfin_write32(SIC_IWR1, iwr1); | ||
| 2721 | bfin_write32(SIC_IWR2, iwr2); | ||
| 2722 | local_irq_restore_hw(flags); | ||
| 2723 | } | ||
| 2724 | |||
| 2725 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 2726 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 2727 | { | ||
| 2728 | unsigned long flags, iwr0, iwr1, iwr2; | ||
| 2729 | |||
| 2730 | if (val == bfin_read_VR_CTL()) | ||
| 2731 | return; | ||
| 2732 | |||
| 2733 | local_irq_save_hw(flags); | ||
| 2734 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 2735 | iwr0 = bfin_read32(SIC_IWR0); | ||
| 2736 | iwr1 = bfin_read32(SIC_IWR1); | ||
| 2737 | iwr2 = bfin_read32(SIC_IWR2); | ||
| 2738 | /* Only allow PPL Wakeup) */ | ||
| 2739 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| 2740 | bfin_write32(SIC_IWR1, 0); | ||
| 2741 | bfin_write32(SIC_IWR2, 0); | ||
| 2742 | |||
| 2743 | bfin_write16(VR_CTL, val); | ||
| 2744 | SSYNC(); | ||
| 2745 | asm("IDLE;"); | ||
| 2746 | |||
| 2747 | bfin_write32(SIC_IWR0, iwr0); | ||
| 2748 | bfin_write32(SIC_IWR1, iwr1); | ||
| 2749 | bfin_write32(SIC_IWR2, iwr2); | ||
| 2750 | local_irq_restore_hw(flags); | ||
| 2751 | } | ||
| 2752 | |||
| 2749 | #endif /* _CDEF_BF54X_H */ | 2753 | #endif /* _CDEF_BF54X_H */ |
| 2750 | 2754 | ||
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h index 36a2ef7e7849..a30d242c7398 100644 --- a/arch/blackfin/mach-bf548/include/mach/dma.h +++ b/arch/blackfin/mach-bf548/include/mach/dma.h | |||
| @@ -1,32 +1,8 @@ | |||
| 1 | /* | 1 | /* mach/dma.h - arch-specific DMA defines |
| 2 | * file: include/asm-blackfin/mach-bf548/dma.h | ||
| 3 | * based on: | ||
| 4 | * author: | ||
| 5 | * | 2 | * |
| 6 | * created: | 3 | * Copyright 2004-2008 Analog Devices Inc. |
| 7 | * description: | ||
| 8 | * system mmr register map | ||
| 9 | * rev: | ||
| 10 | * | 4 | * |
| 11 | * modified: | 5 | * Licensed under the GPL-2 or later. |
| 12 | * | ||
| 13 | * | ||
| 14 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * this program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the gnu general public license as published by | ||
| 18 | * the free software foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * this program is distributed in the hope that it will be useful, | ||
| 22 | * but without any warranty; without even the implied warranty of | ||
| 23 | * merchantability or fitness for a particular purpose. see the | ||
| 24 | * gnu general public license for more details. | ||
| 25 | * | ||
| 26 | * you should have received a copy of the gnu general public license | ||
| 27 | * along with this program; see the file copying. | ||
| 28 | * if not, write to the free software foundation, | ||
| 29 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 30 | */ | 6 | */ |
| 31 | 7 | ||
| 32 | #ifndef _MACH_DMA_H_ | 8 | #ifndef _MACH_DMA_H_ |
| @@ -71,6 +47,6 @@ | |||
| 71 | #define CH_MEM_STREAM3_DEST 30 | 47 | #define CH_MEM_STREAM3_DEST 30 |
| 72 | #define CH_MEM_STREAM3_SRC 31 | 48 | #define CH_MEM_STREAM3_SRC 31 |
| 73 | 49 | ||
| 74 | #define MAX_BLACKFIN_DMA_CHANNEL 32 | 50 | #define MAX_DMA_CHANNELS 32 |
| 75 | 51 | ||
| 76 | #endif | 52 | #endif |
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h index ad380d1f5872..60299a71e090 100644 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ b/arch/blackfin/mach-bf548/include/mach/irq.h | |||
| @@ -158,7 +158,7 @@ Events (highest priority) EMU 0 | |||
| 158 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ | 158 | #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ |
| 159 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ | 159 | #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ |
| 160 | 160 | ||
| 161 | #define SYS_IRQS IRQ_PINT3 | 161 | #define SYS_IRQS IRQ_PINT3 |
| 162 | 162 | ||
| 163 | #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) | 163 | #define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) |
| 164 | #define IRQ_PA0 BFIN_PA_IRQ(0) | 164 | #define IRQ_PA0 BFIN_PA_IRQ(0) |
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_init.h b/arch/blackfin/mach-bf548/include/mach/mem_init.h deleted file mode 100644 index ab0b863eee66..000000000000 --- a/arch/blackfin/mach-bf548/include/mach/mem_init.h +++ /dev/null | |||
| @@ -1,255 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf548/mem_init.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 13 | * | ||
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License as published by | ||
| 18 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 19 | * any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; see the file COPYING. | ||
| 28 | * If not, write to the Free Software Foundation, | ||
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 30 | */ | ||
| 31 | #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) | ||
| 32 | #define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) | ||
| 33 | #define DDR_CLK_HZ(x) (1000*1000*1000/x) | ||
| 34 | |||
| 35 | #if (CONFIG_MEM_MT46V32M16_6T) | ||
| 36 | #define DDR_SIZE DEVSZ_512 | ||
| 37 | #define DDR_WIDTH DEVWD_16 | ||
| 38 | #define DDR_MAX_tCK 13 | ||
| 39 | |||
| 40 | #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) | ||
| 41 | #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) | ||
| 42 | #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) | ||
| 43 | #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) | ||
| 44 | #define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) | ||
| 45 | |||
| 46 | #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) | ||
| 47 | #define DDR_tWTR DDR_TWTR(1) | ||
| 48 | #define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) | ||
| 49 | #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) | ||
| 50 | #endif | ||
| 51 | |||
| 52 | #if (CONFIG_MEM_MT46V32M16_5B) | ||
| 53 | #define DDR_SIZE DEVSZ_512 | ||
| 54 | #define DDR_WIDTH DEVWD_16 | ||
| 55 | #define DDR_MAX_tCK 13 | ||
| 56 | |||
| 57 | #define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) | ||
| 58 | #define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) | ||
| 59 | #define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) | ||
| 60 | #define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) | ||
| 61 | #define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) | ||
| 62 | |||
| 63 | #define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) | ||
| 64 | #define DDR_tWTR DDR_TWTR(2) | ||
| 65 | #define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) | ||
| 66 | #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) | ||
| 67 | #endif | ||
| 68 | |||
| 69 | #if (CONFIG_MEM_GENERIC_BOARD) | ||
| 70 | #define DDR_SIZE DEVSZ_512 | ||
| 71 | #define DDR_WIDTH DEVWD_16 | ||
| 72 | #define DDR_MAX_tCK 13 | ||
| 73 | |||
| 74 | #define DDR_tRCD DDR_TRCD(3) | ||
| 75 | #define DDR_tWTR DDR_TWTR(2) | ||
| 76 | #define DDR_tWR DDR_TWR(2) | ||
| 77 | #define DDR_tMRD DDR_TMRD(2) | ||
| 78 | #define DDR_tRP DDR_TRP(3) | ||
| 79 | #define DDR_tRAS DDR_TRAS(7) | ||
| 80 | #define DDR_tRC DDR_TRC(10) | ||
| 81 | #define DDR_tRFC DDR_TRFC(12) | ||
| 82 | #define DDR_tREFI DDR_TREFI(1288) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) | ||
| 86 | # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." | ||
| 87 | #elif(CONFIG_SCLK_HZ <= 133333333) | ||
| 88 | # define DDR_CL CL_2 | ||
| 89 | #else | ||
| 90 | # error "CONFIG_SCLK_HZ is too large (>133333333 Hz)." | ||
| 91 | #endif | ||
| 92 | |||
| 93 | |||
| 94 | #define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) | ||
| 95 | #define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ | ||
| 96 | | DDR_tMRD | DDR_tWR | DDR_tRCD) | ||
| 97 | #define mem_DDRCTL2 DDR_CL | ||
| 98 | |||
| 99 | |||
| 100 | #if defined CONFIG_CLKIN_HALF | ||
| 101 | #define CLKIN_HALF 1 | ||
| 102 | #else | ||
| 103 | #define CLKIN_HALF 0 | ||
| 104 | #endif | ||
| 105 | |||
| 106 | #if defined CONFIG_PLL_BYPASS | ||
| 107 | #define PLL_BYPASS 1 | ||
| 108 | #else | ||
| 109 | #define PLL_BYPASS 0 | ||
| 110 | #endif | ||
| 111 | |||
| 112 | /***************************************Currently Not Being Used *********************************/ | ||
| 113 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 114 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 115 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) | ||
| 116 | #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 117 | #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 118 | |||
| 119 | #if (flash_EBIU_AMBCTL_TT > 3) | ||
| 120 | #define flash_EBIU_AMBCTL0_TT B0TT_4 | ||
| 121 | #endif | ||
| 122 | #if (flash_EBIU_AMBCTL_TT == 3) | ||
| 123 | #define flash_EBIU_AMBCTL0_TT B0TT_3 | ||
| 124 | #endif | ||
| 125 | #if (flash_EBIU_AMBCTL_TT == 2) | ||
| 126 | #define flash_EBIU_AMBCTL0_TT B0TT_2 | ||
| 127 | #endif | ||
| 128 | #if (flash_EBIU_AMBCTL_TT < 2) | ||
| 129 | #define flash_EBIU_AMBCTL0_TT B0TT_1 | ||
| 130 | #endif | ||
| 131 | |||
| 132 | #if (flash_EBIU_AMBCTL_ST > 3) | ||
| 133 | #define flash_EBIU_AMBCTL0_ST B0ST_4 | ||
| 134 | #endif | ||
| 135 | #if (flash_EBIU_AMBCTL_ST == 3) | ||
| 136 | #define flash_EBIU_AMBCTL0_ST B0ST_3 | ||
| 137 | #endif | ||
| 138 | #if (flash_EBIU_AMBCTL_ST == 2) | ||
| 139 | #define flash_EBIU_AMBCTL0_ST B0ST_2 | ||
| 140 | #endif | ||
| 141 | #if (flash_EBIU_AMBCTL_ST < 2) | ||
| 142 | #define flash_EBIU_AMBCTL0_ST B0ST_1 | ||
| 143 | #endif | ||
| 144 | |||
| 145 | #if (flash_EBIU_AMBCTL_HT > 2) | ||
| 146 | #define flash_EBIU_AMBCTL0_HT B0HT_3 | ||
| 147 | #endif | ||
| 148 | #if (flash_EBIU_AMBCTL_HT == 2) | ||
| 149 | #define flash_EBIU_AMBCTL0_HT B0HT_2 | ||
| 150 | #endif | ||
| 151 | #if (flash_EBIU_AMBCTL_HT == 1) | ||
| 152 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 153 | #endif | ||
| 154 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) | ||
| 155 | #define flash_EBIU_AMBCTL0_HT B0HT_0 | ||
| 156 | #endif | ||
| 157 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) | ||
| 158 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 159 | #endif | ||
| 160 | |||
| 161 | #if (flash_EBIU_AMBCTL_WAT > 14) | ||
| 162 | #define flash_EBIU_AMBCTL0_WAT B0WAT_15 | ||
| 163 | #endif | ||
| 164 | #if (flash_EBIU_AMBCTL_WAT == 14) | ||
| 165 | #define flash_EBIU_AMBCTL0_WAT B0WAT_14 | ||
| 166 | #endif | ||
| 167 | #if (flash_EBIU_AMBCTL_WAT == 13) | ||
| 168 | #define flash_EBIU_AMBCTL0_WAT B0WAT_13 | ||
| 169 | #endif | ||
| 170 | #if (flash_EBIU_AMBCTL_WAT == 12) | ||
| 171 | #define flash_EBIU_AMBCTL0_WAT B0WAT_12 | ||
| 172 | #endif | ||
| 173 | #if (flash_EBIU_AMBCTL_WAT == 11) | ||
| 174 | #define flash_EBIU_AMBCTL0_WAT B0WAT_11 | ||
| 175 | #endif | ||
| 176 | #if (flash_EBIU_AMBCTL_WAT == 10) | ||
| 177 | #define flash_EBIU_AMBCTL0_WAT B0WAT_10 | ||
| 178 | #endif | ||
| 179 | #if (flash_EBIU_AMBCTL_WAT == 9) | ||
| 180 | #define flash_EBIU_AMBCTL0_WAT B0WAT_9 | ||
| 181 | #endif | ||
| 182 | #if (flash_EBIU_AMBCTL_WAT == 8) | ||
| 183 | #define flash_EBIU_AMBCTL0_WAT B0WAT_8 | ||
| 184 | #endif | ||
| 185 | #if (flash_EBIU_AMBCTL_WAT == 7) | ||
| 186 | #define flash_EBIU_AMBCTL0_WAT B0WAT_7 | ||
| 187 | #endif | ||
| 188 | #if (flash_EBIU_AMBCTL_WAT == 6) | ||
| 189 | #define flash_EBIU_AMBCTL0_WAT B0WAT_6 | ||
| 190 | #endif | ||
| 191 | #if (flash_EBIU_AMBCTL_WAT == 5) | ||
| 192 | #define flash_EBIU_AMBCTL0_WAT B0WAT_5 | ||
| 193 | #endif | ||
| 194 | #if (flash_EBIU_AMBCTL_WAT == 4) | ||
| 195 | #define flash_EBIU_AMBCTL0_WAT B0WAT_4 | ||
| 196 | #endif | ||
| 197 | #if (flash_EBIU_AMBCTL_WAT == 3) | ||
| 198 | #define flash_EBIU_AMBCTL0_WAT B0WAT_3 | ||
| 199 | #endif | ||
| 200 | #if (flash_EBIU_AMBCTL_WAT == 2) | ||
| 201 | #define flash_EBIU_AMBCTL0_WAT B0WAT_2 | ||
| 202 | #endif | ||
| 203 | #if (flash_EBIU_AMBCTL_WAT == 1) | ||
| 204 | #define flash_EBIU_AMBCTL0_WAT B0WAT_1 | ||
| 205 | #endif | ||
| 206 | |||
| 207 | #if (flash_EBIU_AMBCTL_RAT > 14) | ||
| 208 | #define flash_EBIU_AMBCTL0_RAT B0RAT_15 | ||
| 209 | #endif | ||
| 210 | #if (flash_EBIU_AMBCTL_RAT == 14) | ||
| 211 | #define flash_EBIU_AMBCTL0_RAT B0RAT_14 | ||
| 212 | #endif | ||
| 213 | #if (flash_EBIU_AMBCTL_RAT == 13) | ||
| 214 | #define flash_EBIU_AMBCTL0_RAT B0RAT_13 | ||
| 215 | #endif | ||
| 216 | #if (flash_EBIU_AMBCTL_RAT == 12) | ||
| 217 | #define flash_EBIU_AMBCTL0_RAT B0RAT_12 | ||
| 218 | #endif | ||
| 219 | #if (flash_EBIU_AMBCTL_RAT == 11) | ||
| 220 | #define flash_EBIU_AMBCTL0_RAT B0RAT_11 | ||
| 221 | #endif | ||
| 222 | #if (flash_EBIU_AMBCTL_RAT == 10) | ||
| 223 | #define flash_EBIU_AMBCTL0_RAT B0RAT_10 | ||
| 224 | #endif | ||
| 225 | #if (flash_EBIU_AMBCTL_RAT == 9) | ||
| 226 | #define flash_EBIU_AMBCTL0_RAT B0RAT_9 | ||
| 227 | #endif | ||
| 228 | #if (flash_EBIU_AMBCTL_RAT == 8) | ||
| 229 | #define flash_EBIU_AMBCTL0_RAT B0RAT_8 | ||
| 230 | #endif | ||
| 231 | #if (flash_EBIU_AMBCTL_RAT == 7) | ||
| 232 | #define flash_EBIU_AMBCTL0_RAT B0RAT_7 | ||
| 233 | #endif | ||
| 234 | #if (flash_EBIU_AMBCTL_RAT == 6) | ||
| 235 | #define flash_EBIU_AMBCTL0_RAT B0RAT_6 | ||
| 236 | #endif | ||
| 237 | #if (flash_EBIU_AMBCTL_RAT == 5) | ||
| 238 | #define flash_EBIU_AMBCTL0_RAT B0RAT_5 | ||
| 239 | #endif | ||
| 240 | #if (flash_EBIU_AMBCTL_RAT == 4) | ||
| 241 | #define flash_EBIU_AMBCTL0_RAT B0RAT_4 | ||
| 242 | #endif | ||
| 243 | #if (flash_EBIU_AMBCTL_RAT == 3) | ||
| 244 | #define flash_EBIU_AMBCTL0_RAT B0RAT_3 | ||
| 245 | #endif | ||
| 246 | #if (flash_EBIU_AMBCTL_RAT == 2) | ||
| 247 | #define flash_EBIU_AMBCTL0_RAT B0RAT_2 | ||
| 248 | #endif | ||
| 249 | #if (flash_EBIU_AMBCTL_RAT == 1) | ||
| 250 | #define flash_EBIU_AMBCTL0_RAT B0RAT_1 | ||
| 251 | #endif | ||
| 252 | |||
| 253 | #define flash_EBIU_AMBCTL0 \ | ||
| 254 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ | ||
| 255 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) | ||
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h index a2228428dc06..70b9c1194024 100644 --- a/arch/blackfin/mach-bf548/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h | |||
| @@ -108,4 +108,10 @@ | |||
| 108 | #define L1_SCRATCH_START 0xFFB00000 | 108 | #define L1_SCRATCH_START 0xFFB00000 |
| 109 | #define L1_SCRATCH_LENGTH 0x1000 | 109 | #define L1_SCRATCH_LENGTH 0x1000 |
| 110 | 110 | ||
| 111 | #define GET_PDA_SAFE(preg) \ | ||
| 112 | preg.l = _cpu_pda; \ | ||
| 113 | preg.h = _cpu_pda; | ||
| 114 | |||
| 115 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 116 | |||
| 111 | #endif/* _MEM_MAP_548_H_ */ | 117 | #endif/* _MEM_MAP_548_H_ */ |
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig index 3f4895450bea..638ec38ca470 100644 --- a/arch/blackfin/mach-bf561/Kconfig +++ b/arch/blackfin/mach-bf561/Kconfig | |||
| @@ -4,9 +4,9 @@ source "arch/blackfin/mach-bf561/boards/Kconfig" | |||
| 4 | 4 | ||
| 5 | menu "BF561 Specific Configuration" | 5 | menu "BF561 Specific Configuration" |
| 6 | 6 | ||
| 7 | comment "Core B Support" | 7 | if (!SMP) |
| 8 | 8 | ||
| 9 | menu "Core B Support" | 9 | comment "Core B Support" |
| 10 | 10 | ||
| 11 | config BF561_COREB | 11 | config BF561_COREB |
| 12 | bool "Enable Core B support" | 12 | bool "Enable Core B support" |
| @@ -25,7 +25,7 @@ config BF561_COREB_RESET | |||
| 25 | 0 is set, and will reset PC to 0xff600000 when | 25 | 0 is set, and will reset PC to 0xff600000 when |
| 26 | COREB_SRAM_INIT is cleared. | 26 | COREB_SRAM_INIT is cleared. |
| 27 | 27 | ||
| 28 | endmenu | 28 | endif |
| 29 | 29 | ||
| 30 | comment "Interrupt Priority Assignment" | 30 | comment "Interrupt Priority Assignment" |
| 31 | 31 | ||
| @@ -138,7 +138,7 @@ config IRQ_DMA2_11 | |||
| 138 | default 9 | 138 | default 9 |
| 139 | config IRQ_TIMER0 | 139 | config IRQ_TIMER0 |
| 140 | int "TIMER 0 Interrupt" | 140 | int "TIMER 0 Interrupt" |
| 141 | default 10 | 141 | default 8 |
| 142 | config IRQ_TIMER1 | 142 | config IRQ_TIMER1 |
| 143 | int "TIMER 1 Interrupt" | 143 | int "TIMER 1 Interrupt" |
| 144 | default 10 | 144 | default 10 |
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile index f39235a55783..59e18afe28c6 100644 --- a/arch/blackfin/mach-bf561/Makefile +++ b/arch/blackfin/mach-bf561/Makefile | |||
| @@ -2,8 +2,7 @@ | |||
| 2 | # arch/blackfin/mach-bf561/Makefile | 2 | # arch/blackfin/mach-bf561/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | extra-y := head.o | ||
| 6 | |||
| 7 | obj-y := ints-priority.o dma.o | 5 | obj-y := ints-priority.o dma.o |
| 8 | 6 | ||
| 9 | obj-$(CONFIG_BF561_COREB) += coreb.o | 7 | obj-$(CONFIG_BF561_COREB) += coreb.o |
| 8 | obj-$(CONFIG_SMP) += smp.o secondary.o atomic.o | ||
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S new file mode 100644 index 000000000000..9439bc6bd01f --- /dev/null +++ b/arch/blackfin/mach-bf561/atomic.S | |||
| @@ -0,0 +1,919 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf561/atomic.S | ||
| 3 | * Author: Philippe Gerum <rpm@xenomai.org> | ||
| 4 | * | ||
| 5 | * Copyright 2007 Analog Devices Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, see the file COPYING, or write | ||
| 19 | * to the Free Software Foundation, Inc., | ||
| 20 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/linkage.h> | ||
| 24 | #include <asm/blackfin.h> | ||
| 25 | #include <asm/cache.h> | ||
| 26 | #include <asm/asm-offsets.h> | ||
| 27 | #include <asm/rwlock.h> | ||
| 28 | #include <asm/cplb.h> | ||
| 29 | |||
| 30 | .text | ||
| 31 | |||
| 32 | .macro coreslot_loadaddr reg:req | ||
| 33 | \reg\().l = _corelock; | ||
| 34 | \reg\().h = _corelock; | ||
| 35 | .endm | ||
| 36 | |||
| 37 | /* | ||
| 38 | * r0 = address of atomic data to flush and invalidate (32bit). | ||
| 39 | * | ||
| 40 | * Clear interrupts and return the old mask. | ||
| 41 | * We assume that no atomic data can span cachelines. | ||
| 42 | * | ||
| 43 | * Clobbers: r2:0, p0 | ||
| 44 | */ | ||
| 45 | ENTRY(_get_core_lock) | ||
| 46 | r1 = -L1_CACHE_BYTES; | ||
| 47 | r1 = r0 & r1; | ||
| 48 | cli r0; | ||
| 49 | coreslot_loadaddr p0; | ||
| 50 | .Lretry_corelock: | ||
| 51 | testset (p0); | ||
| 52 | if cc jump .Ldone_corelock; | ||
| 53 | SSYNC(r2); | ||
| 54 | jump .Lretry_corelock | ||
| 55 | .Ldone_corelock: | ||
| 56 | p0 = r1; | ||
| 57 | CSYNC(r2); | ||
| 58 | flushinv[p0]; | ||
| 59 | SSYNC(r2); | ||
| 60 | rts; | ||
| 61 | ENDPROC(_get_core_lock) | ||
| 62 | |||
| 63 | /* | ||
| 64 | * r0 = address of atomic data in uncacheable memory region (32bit). | ||
| 65 | * | ||
| 66 | * Clear interrupts and return the old mask. | ||
| 67 | * | ||
| 68 | * Clobbers: r0, p0 | ||
| 69 | */ | ||
| 70 | ENTRY(_get_core_lock_noflush) | ||
| 71 | cli r0; | ||
| 72 | coreslot_loadaddr p0; | ||
| 73 | .Lretry_corelock_noflush: | ||
| 74 | testset (p0); | ||
| 75 | if cc jump .Ldone_corelock_noflush; | ||
| 76 | SSYNC(r2); | ||
| 77 | jump .Lretry_corelock_noflush | ||
| 78 | .Ldone_corelock_noflush: | ||
| 79 | rts; | ||
| 80 | ENDPROC(_get_core_lock_noflush) | ||
| 81 | |||
| 82 | /* | ||
| 83 | * r0 = interrupt mask to restore. | ||
| 84 | * r1 = address of atomic data to flush and invalidate (32bit). | ||
| 85 | * | ||
| 86 | * Interrupts are masked on entry (see _get_core_lock). | ||
| 87 | * Clobbers: r2:0, p0 | ||
| 88 | */ | ||
| 89 | ENTRY(_put_core_lock) | ||
| 90 | /* Write-through cache assumed, so no flush needed here. */ | ||
| 91 | coreslot_loadaddr p0; | ||
| 92 | r1 = 0; | ||
| 93 | [p0] = r1; | ||
| 94 | SSYNC(r2); | ||
| 95 | sti r0; | ||
| 96 | rts; | ||
| 97 | ENDPROC(_put_core_lock) | ||
| 98 | |||
| 99 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 100 | |||
| 101 | ENTRY(___raw_smp_mark_barrier_asm) | ||
| 102 | [--sp] = rets; | ||
| 103 | [--sp] = ( r7:5 ); | ||
| 104 | [--sp] = r0; | ||
| 105 | [--sp] = p1; | ||
| 106 | [--sp] = p0; | ||
| 107 | call _get_core_lock_noflush; | ||
| 108 | |||
| 109 | /* | ||
| 110 | * Calculate current core mask | ||
| 111 | */ | ||
| 112 | GET_CPUID(p1, r7); | ||
| 113 | r6 = 1; | ||
| 114 | r6 <<= r7; | ||
| 115 | |||
| 116 | /* | ||
| 117 | * Set bit of other cores in barrier mask. Don't change current core bit. | ||
| 118 | */ | ||
| 119 | p1.l = _barrier_mask; | ||
| 120 | p1.h = _barrier_mask; | ||
| 121 | r7 = [p1]; | ||
| 122 | r5 = r7 & r6; | ||
| 123 | r7 = ~r6; | ||
| 124 | cc = r5 == 0; | ||
| 125 | if cc jump 1f; | ||
| 126 | r7 = r7 | r6; | ||
| 127 | 1: | ||
| 128 | [p1] = r7; | ||
| 129 | SSYNC(r2); | ||
| 130 | |||
| 131 | call _put_core_lock; | ||
| 132 | p0 = [sp++]; | ||
| 133 | p1 = [sp++]; | ||
| 134 | r0 = [sp++]; | ||
| 135 | ( r7:5 ) = [sp++]; | ||
| 136 | rets = [sp++]; | ||
| 137 | rts; | ||
| 138 | ENDPROC(___raw_smp_mark_barrier_asm) | ||
| 139 | |||
| 140 | ENTRY(___raw_smp_check_barrier_asm) | ||
| 141 | [--sp] = rets; | ||
| 142 | [--sp] = ( r7:5 ); | ||
| 143 | [--sp] = r0; | ||
| 144 | [--sp] = p1; | ||
| 145 | [--sp] = p0; | ||
| 146 | call _get_core_lock_noflush; | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Calculate current core mask | ||
| 150 | */ | ||
| 151 | GET_CPUID(p1, r7); | ||
| 152 | r6 = 1; | ||
| 153 | r6 <<= r7; | ||
| 154 | |||
| 155 | /* | ||
| 156 | * Clear current core bit in barrier mask if it is set. | ||
| 157 | */ | ||
| 158 | p1.l = _barrier_mask; | ||
| 159 | p1.h = _barrier_mask; | ||
| 160 | r7 = [p1]; | ||
| 161 | r5 = r7 & r6; | ||
| 162 | cc = r5 == 0; | ||
| 163 | if cc jump 1f; | ||
| 164 | r6 = ~r6; | ||
| 165 | r7 = r7 & r6; | ||
| 166 | [p1] = r7; | ||
| 167 | SSYNC(r2); | ||
| 168 | |||
| 169 | call _put_core_lock; | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Invalidate the entire D-cache of current core. | ||
| 173 | */ | ||
| 174 | sp += -12; | ||
| 175 | call _resync_core_dcache | ||
| 176 | sp += 12; | ||
| 177 | jump 2f; | ||
| 178 | 1: | ||
| 179 | call _put_core_lock; | ||
| 180 | 2: | ||
| 181 | p0 = [sp++]; | ||
| 182 | p1 = [sp++]; | ||
| 183 | r0 = [sp++]; | ||
| 184 | ( r7:5 ) = [sp++]; | ||
| 185 | rets = [sp++]; | ||
| 186 | rts; | ||
| 187 | ENDPROC(___raw_smp_check_barrier_asm) | ||
| 188 | |||
| 189 | /* | ||
| 190 | * r0 = irqflags | ||
| 191 | * r1 = address of atomic data | ||
| 192 | * | ||
| 193 | * Clobbers: r2:0, p1:0 | ||
| 194 | */ | ||
| 195 | _start_lock_coherent: | ||
| 196 | |||
| 197 | [--sp] = rets; | ||
| 198 | [--sp] = ( r7:6 ); | ||
| 199 | r7 = r0; | ||
| 200 | p1 = r1; | ||
| 201 | |||
| 202 | /* | ||
| 203 | * Determine whether the atomic data was previously | ||
| 204 | * owned by another CPU (=r6). | ||
| 205 | */ | ||
| 206 | GET_CPUID(p0, r2); | ||
| 207 | r1 = 1; | ||
| 208 | r1 <<= r2; | ||
| 209 | r2 = ~r1; | ||
| 210 | |||
| 211 | r1 = [p1]; | ||
| 212 | r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */ | ||
| 213 | r6 = r1 & r2; | ||
| 214 | r1 = [p1]; | ||
| 215 | r1 <<= 4; | ||
| 216 | r1 >>= 4; | ||
| 217 | [p1] = r1; | ||
| 218 | |||
| 219 | /* | ||
| 220 | * Release the core lock now, but keep IRQs disabled while we are | ||
| 221 | * performing the remaining housekeeping chores for the current CPU. | ||
| 222 | */ | ||
| 223 | coreslot_loadaddr p0; | ||
| 224 | r1 = 0; | ||
| 225 | [p0] = r1; | ||
| 226 | |||
| 227 | /* | ||
| 228 | * If another CPU has owned the same atomic section before us, | ||
| 229 | * then our D-cached copy of the shared data protected by the | ||
| 230 | * current spin/write_lock may be obsolete. | ||
| 231 | */ | ||
| 232 | cc = r6 == 0; | ||
| 233 | if cc jump .Lcache_synced | ||
| 234 | |||
| 235 | /* | ||
| 236 | * Invalidate the entire D-cache of the current core. | ||
| 237 | */ | ||
| 238 | sp += -12; | ||
| 239 | call _resync_core_dcache | ||
| 240 | sp += 12; | ||
| 241 | |||
| 242 | .Lcache_synced: | ||
| 243 | SSYNC(r2); | ||
| 244 | sti r7; | ||
| 245 | ( r7:6 ) = [sp++]; | ||
| 246 | rets = [sp++]; | ||
| 247 | rts | ||
| 248 | |||
| 249 | /* | ||
| 250 | * r0 = irqflags | ||
| 251 | * r1 = address of atomic data | ||
| 252 | * | ||
| 253 | * Clobbers: r2:0, p1:0 | ||
| 254 | */ | ||
| 255 | _end_lock_coherent: | ||
| 256 | |||
| 257 | p1 = r1; | ||
| 258 | GET_CPUID(p0, r2); | ||
| 259 | r2 += 28; | ||
| 260 | r1 = 1; | ||
| 261 | r1 <<= r2; | ||
| 262 | r2 = [p1]; | ||
| 263 | r2 = r1 | r2; | ||
| 264 | [p1] = r2; | ||
| 265 | r1 = p1; | ||
| 266 | jump _put_core_lock; | ||
| 267 | |||
| 268 | #endif /* __ARCH_SYNC_CORE_DCACHE */ | ||
| 269 | |||
| 270 | /* | ||
| 271 | * r0 = &spinlock->lock | ||
| 272 | * | ||
| 273 | * Clobbers: r3:0, p1:0 | ||
| 274 | */ | ||
| 275 | ENTRY(___raw_spin_is_locked_asm) | ||
| 276 | p1 = r0; | ||
| 277 | [--sp] = rets; | ||
| 278 | call _get_core_lock; | ||
| 279 | r3 = [p1]; | ||
| 280 | cc = bittst( r3, 0 ); | ||
| 281 | r3 = cc; | ||
| 282 | r1 = p1; | ||
| 283 | call _put_core_lock; | ||
| 284 | rets = [sp++]; | ||
| 285 | r0 = r3; | ||
| 286 | rts; | ||
| 287 | ENDPROC(___raw_spin_is_locked_asm) | ||
| 288 | |||
| 289 | /* | ||
| 290 | * r0 = &spinlock->lock | ||
| 291 | * | ||
| 292 | * Clobbers: r3:0, p1:0 | ||
| 293 | */ | ||
| 294 | ENTRY(___raw_spin_lock_asm) | ||
| 295 | p1 = r0; | ||
| 296 | [--sp] = rets; | ||
| 297 | .Lretry_spinlock: | ||
| 298 | call _get_core_lock; | ||
| 299 | r1 = p1; | ||
| 300 | r2 = [p1]; | ||
| 301 | cc = bittst( r2, 0 ); | ||
| 302 | if cc jump .Lbusy_spinlock | ||
| 303 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 304 | r3 = p1; | ||
| 305 | bitset ( r2, 0 ); /* Raise the lock bit. */ | ||
| 306 | [p1] = r2; | ||
| 307 | call _start_lock_coherent | ||
| 308 | #else | ||
| 309 | r2 = 1; | ||
| 310 | [p1] = r2; | ||
| 311 | call _put_core_lock; | ||
| 312 | #endif | ||
| 313 | rets = [sp++]; | ||
| 314 | rts; | ||
| 315 | |||
| 316 | .Lbusy_spinlock: | ||
| 317 | /* We don't touch the atomic area if busy, so that flush | ||
| 318 | will behave like nop in _put_core_lock. */ | ||
| 319 | call _put_core_lock; | ||
| 320 | SSYNC(r2); | ||
| 321 | r0 = p1; | ||
| 322 | jump .Lretry_spinlock | ||
| 323 | ENDPROC(___raw_spin_lock_asm) | ||
| 324 | |||
| 325 | /* | ||
| 326 | * r0 = &spinlock->lock | ||
| 327 | * | ||
| 328 | * Clobbers: r3:0, p1:0 | ||
| 329 | */ | ||
| 330 | ENTRY(___raw_spin_trylock_asm) | ||
| 331 | p1 = r0; | ||
| 332 | [--sp] = rets; | ||
| 333 | call _get_core_lock; | ||
| 334 | r1 = p1; | ||
| 335 | r3 = [p1]; | ||
| 336 | cc = bittst( r3, 0 ); | ||
| 337 | if cc jump .Lfailed_trylock | ||
| 338 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 339 | bitset ( r3, 0 ); /* Raise the lock bit. */ | ||
| 340 | [p1] = r3; | ||
| 341 | call _start_lock_coherent | ||
| 342 | #else | ||
| 343 | r2 = 1; | ||
| 344 | [p1] = r2; | ||
| 345 | call _put_core_lock; | ||
| 346 | #endif | ||
| 347 | r0 = 1; | ||
| 348 | rets = [sp++]; | ||
| 349 | rts; | ||
| 350 | .Lfailed_trylock: | ||
| 351 | call _put_core_lock; | ||
| 352 | r0 = 0; | ||
| 353 | rets = [sp++]; | ||
| 354 | rts; | ||
| 355 | ENDPROC(___raw_spin_trylock_asm) | ||
| 356 | |||
| 357 | /* | ||
| 358 | * r0 = &spinlock->lock | ||
| 359 | * | ||
| 360 | * Clobbers: r2:0, p1:0 | ||
| 361 | */ | ||
| 362 | ENTRY(___raw_spin_unlock_asm) | ||
| 363 | p1 = r0; | ||
| 364 | [--sp] = rets; | ||
| 365 | call _get_core_lock; | ||
| 366 | r2 = [p1]; | ||
| 367 | bitclr ( r2, 0 ); | ||
| 368 | [p1] = r2; | ||
| 369 | r1 = p1; | ||
| 370 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 371 | call _end_lock_coherent | ||
| 372 | #else | ||
| 373 | call _put_core_lock; | ||
| 374 | #endif | ||
| 375 | rets = [sp++]; | ||
| 376 | rts; | ||
| 377 | ENDPROC(___raw_spin_unlock_asm) | ||
| 378 | |||
| 379 | /* | ||
| 380 | * r0 = &rwlock->lock | ||
| 381 | * | ||
| 382 | * Clobbers: r2:0, p1:0 | ||
| 383 | */ | ||
| 384 | ENTRY(___raw_read_lock_asm) | ||
| 385 | p1 = r0; | ||
| 386 | [--sp] = rets; | ||
| 387 | call _get_core_lock; | ||
| 388 | .Lrdlock_try: | ||
| 389 | r1 = [p1]; | ||
| 390 | r1 += -1; | ||
| 391 | [p1] = r1; | ||
| 392 | cc = r1 < 0; | ||
| 393 | if cc jump .Lrdlock_failed | ||
| 394 | r1 = p1; | ||
| 395 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 396 | call _start_lock_coherent | ||
| 397 | #else | ||
| 398 | call _put_core_lock; | ||
| 399 | #endif | ||
| 400 | rets = [sp++]; | ||
| 401 | rts; | ||
| 402 | |||
| 403 | .Lrdlock_failed: | ||
| 404 | r1 += 1; | ||
| 405 | [p1] = r1; | ||
| 406 | .Lrdlock_wait: | ||
| 407 | r1 = p1; | ||
| 408 | call _put_core_lock; | ||
| 409 | SSYNC(r2); | ||
| 410 | r0 = p1; | ||
| 411 | call _get_core_lock; | ||
| 412 | r1 = [p1]; | ||
| 413 | cc = r1 < 2; | ||
| 414 | if cc jump .Lrdlock_wait; | ||
| 415 | jump .Lrdlock_try | ||
| 416 | ENDPROC(___raw_read_lock_asm) | ||
| 417 | |||
| 418 | /* | ||
| 419 | * r0 = &rwlock->lock | ||
| 420 | * | ||
| 421 | * Clobbers: r3:0, p1:0 | ||
| 422 | */ | ||
| 423 | ENTRY(___raw_read_trylock_asm) | ||
| 424 | p1 = r0; | ||
| 425 | [--sp] = rets; | ||
| 426 | call _get_core_lock; | ||
| 427 | r1 = [p1]; | ||
| 428 | cc = r1 <= 0; | ||
| 429 | if cc jump .Lfailed_tryrdlock; | ||
| 430 | r1 += -1; | ||
| 431 | [p1] = r1; | ||
| 432 | r1 = p1; | ||
| 433 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 434 | call _start_lock_coherent | ||
| 435 | #else | ||
| 436 | call _put_core_lock; | ||
| 437 | #endif | ||
| 438 | rets = [sp++]; | ||
| 439 | r0 = 1; | ||
| 440 | rts; | ||
| 441 | .Lfailed_tryrdlock: | ||
| 442 | r1 = p1; | ||
| 443 | call _put_core_lock; | ||
| 444 | rets = [sp++]; | ||
| 445 | r0 = 0; | ||
| 446 | rts; | ||
| 447 | ENDPROC(___raw_read_trylock_asm) | ||
| 448 | |||
| 449 | /* | ||
| 450 | * r0 = &rwlock->lock | ||
| 451 | * | ||
| 452 | * Note: Processing controlled by a reader lock should not have | ||
| 453 | * any side-effect on cache issues with the other core, so we | ||
| 454 | * just release the core lock and exit (no _end_lock_coherent). | ||
| 455 | * | ||
| 456 | * Clobbers: r3:0, p1:0 | ||
| 457 | */ | ||
| 458 | ENTRY(___raw_read_unlock_asm) | ||
| 459 | p1 = r0; | ||
| 460 | [--sp] = rets; | ||
| 461 | call _get_core_lock; | ||
| 462 | r1 = [p1]; | ||
| 463 | r1 += 1; | ||
| 464 | [p1] = r1; | ||
| 465 | r1 = p1; | ||
| 466 | call _put_core_lock; | ||
| 467 | rets = [sp++]; | ||
| 468 | rts; | ||
| 469 | ENDPROC(___raw_read_unlock_asm) | ||
| 470 | |||
| 471 | /* | ||
| 472 | * r0 = &rwlock->lock | ||
| 473 | * | ||
| 474 | * Clobbers: r3:0, p1:0 | ||
| 475 | */ | ||
| 476 | ENTRY(___raw_write_lock_asm) | ||
| 477 | p1 = r0; | ||
| 478 | r3.l = lo(RW_LOCK_BIAS); | ||
| 479 | r3.h = hi(RW_LOCK_BIAS); | ||
| 480 | [--sp] = rets; | ||
| 481 | call _get_core_lock; | ||
| 482 | .Lwrlock_try: | ||
| 483 | r1 = [p1]; | ||
| 484 | r1 = r1 - r3; | ||
| 485 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 486 | r2 = r1; | ||
| 487 | r2 <<= 4; | ||
| 488 | r2 >>= 4; | ||
| 489 | cc = r2 == 0; | ||
| 490 | #else | ||
| 491 | cc = r1 == 0; | ||
| 492 | #endif | ||
| 493 | if !cc jump .Lwrlock_wait | ||
| 494 | [p1] = r1; | ||
| 495 | r1 = p1; | ||
| 496 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 497 | call _start_lock_coherent | ||
| 498 | #else | ||
| 499 | call _put_core_lock; | ||
| 500 | #endif | ||
| 501 | rets = [sp++]; | ||
| 502 | rts; | ||
| 503 | |||
| 504 | .Lwrlock_wait: | ||
| 505 | r1 = p1; | ||
| 506 | call _put_core_lock; | ||
| 507 | SSYNC(r2); | ||
| 508 | r0 = p1; | ||
| 509 | call _get_core_lock; | ||
| 510 | r1 = [p1]; | ||
| 511 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 512 | r1 <<= 4; | ||
| 513 | r1 >>= 4; | ||
| 514 | #endif | ||
| 515 | cc = r1 == r3; | ||
| 516 | if !cc jump .Lwrlock_wait; | ||
| 517 | jump .Lwrlock_try | ||
| 518 | ENDPROC(___raw_write_lock_asm) | ||
| 519 | |||
| 520 | /* | ||
| 521 | * r0 = &rwlock->lock | ||
| 522 | * | ||
| 523 | * Clobbers: r3:0, p1:0 | ||
| 524 | */ | ||
| 525 | ENTRY(___raw_write_trylock_asm) | ||
| 526 | p1 = r0; | ||
| 527 | [--sp] = rets; | ||
| 528 | call _get_core_lock; | ||
| 529 | r1 = [p1]; | ||
| 530 | r2.l = lo(RW_LOCK_BIAS); | ||
| 531 | r2.h = hi(RW_LOCK_BIAS); | ||
| 532 | cc = r1 == r2; | ||
| 533 | if !cc jump .Lfailed_trywrlock; | ||
| 534 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 535 | r1 >>= 28; | ||
| 536 | r1 <<= 28; | ||
| 537 | #else | ||
| 538 | r1 = 0; | ||
| 539 | #endif | ||
| 540 | [p1] = r1; | ||
| 541 | r1 = p1; | ||
| 542 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 543 | call _start_lock_coherent | ||
| 544 | #else | ||
| 545 | call _put_core_lock; | ||
| 546 | #endif | ||
| 547 | rets = [sp++]; | ||
| 548 | r0 = 1; | ||
| 549 | rts; | ||
| 550 | |||
| 551 | .Lfailed_trywrlock: | ||
| 552 | r1 = p1; | ||
| 553 | call _put_core_lock; | ||
| 554 | rets = [sp++]; | ||
| 555 | r0 = 0; | ||
| 556 | rts; | ||
| 557 | ENDPROC(___raw_write_trylock_asm) | ||
| 558 | |||
| 559 | /* | ||
| 560 | * r0 = &rwlock->lock | ||
| 561 | * | ||
| 562 | * Clobbers: r3:0, p1:0 | ||
| 563 | */ | ||
| 564 | ENTRY(___raw_write_unlock_asm) | ||
| 565 | p1 = r0; | ||
| 566 | r3.l = lo(RW_LOCK_BIAS); | ||
| 567 | r3.h = hi(RW_LOCK_BIAS); | ||
| 568 | [--sp] = rets; | ||
| 569 | call _get_core_lock; | ||
| 570 | r1 = [p1]; | ||
| 571 | r1 = r1 + r3; | ||
| 572 | [p1] = r1; | ||
| 573 | r1 = p1; | ||
| 574 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 575 | call _end_lock_coherent | ||
| 576 | #else | ||
| 577 | call _put_core_lock; | ||
| 578 | #endif | ||
| 579 | rets = [sp++]; | ||
| 580 | rts; | ||
| 581 | ENDPROC(___raw_write_unlock_asm) | ||
| 582 | |||
| 583 | /* | ||
| 584 | * r0 = ptr | ||
| 585 | * r1 = value | ||
| 586 | * | ||
| 587 | * Add a signed value to a 32bit word and return the new value atomically. | ||
| 588 | * Clobbers: r3:0, p1:0 | ||
| 589 | */ | ||
| 590 | ENTRY(___raw_atomic_update_asm) | ||
| 591 | p1 = r0; | ||
| 592 | r3 = r1; | ||
| 593 | [--sp] = rets; | ||
| 594 | call _get_core_lock; | ||
| 595 | r2 = [p1]; | ||
| 596 | r3 = r3 + r2; | ||
| 597 | [p1] = r3; | ||
| 598 | r1 = p1; | ||
| 599 | call _put_core_lock; | ||
| 600 | r0 = r3; | ||
| 601 | rets = [sp++]; | ||
| 602 | rts; | ||
| 603 | ENDPROC(___raw_atomic_update_asm) | ||
| 604 | |||
| 605 | /* | ||
| 606 | * r0 = ptr | ||
| 607 | * r1 = mask | ||
| 608 | * | ||
| 609 | * Clear the mask bits from a 32bit word and return the old 32bit value | ||
| 610 | * atomically. | ||
| 611 | * Clobbers: r3:0, p1:0 | ||
| 612 | */ | ||
| 613 | ENTRY(___raw_atomic_clear_asm) | ||
| 614 | p1 = r0; | ||
| 615 | r3 = ~r1; | ||
| 616 | [--sp] = rets; | ||
| 617 | call _get_core_lock; | ||
| 618 | r2 = [p1]; | ||
| 619 | r3 = r2 & r3; | ||
| 620 | [p1] = r3; | ||
| 621 | r3 = r2; | ||
| 622 | r1 = p1; | ||
| 623 | call _put_core_lock; | ||
| 624 | r0 = r3; | ||
| 625 | rets = [sp++]; | ||
| 626 | rts; | ||
| 627 | ENDPROC(___raw_atomic_clear_asm) | ||
| 628 | |||
| 629 | /* | ||
| 630 | * r0 = ptr | ||
| 631 | * r1 = mask | ||
| 632 | * | ||
| 633 | * Set the mask bits into a 32bit word and return the old 32bit value | ||
| 634 | * atomically. | ||
| 635 | * Clobbers: r3:0, p1:0 | ||
| 636 | */ | ||
| 637 | ENTRY(___raw_atomic_set_asm) | ||
| 638 | p1 = r0; | ||
| 639 | r3 = r1; | ||
| 640 | [--sp] = rets; | ||
| 641 | call _get_core_lock; | ||
| 642 | r2 = [p1]; | ||
| 643 | r3 = r2 | r3; | ||
| 644 | [p1] = r3; | ||
| 645 | r3 = r2; | ||
| 646 | r1 = p1; | ||
| 647 | call _put_core_lock; | ||
| 648 | r0 = r3; | ||
| 649 | rets = [sp++]; | ||
| 650 | rts; | ||
| 651 | ENDPROC(___raw_atomic_set_asm) | ||
| 652 | |||
| 653 | /* | ||
| 654 | * r0 = ptr | ||
| 655 | * r1 = mask | ||
| 656 | * | ||
| 657 | * XOR the mask bits with a 32bit word and return the old 32bit value | ||
| 658 | * atomically. | ||
| 659 | * Clobbers: r3:0, p1:0 | ||
| 660 | */ | ||
| 661 | ENTRY(___raw_atomic_xor_asm) | ||
| 662 | p1 = r0; | ||
| 663 | r3 = r1; | ||
| 664 | [--sp] = rets; | ||
| 665 | call _get_core_lock; | ||
| 666 | r2 = [p1]; | ||
| 667 | r3 = r2 ^ r3; | ||
| 668 | [p1] = r3; | ||
| 669 | r3 = r2; | ||
| 670 | r1 = p1; | ||
| 671 | call _put_core_lock; | ||
| 672 | r0 = r3; | ||
| 673 | rets = [sp++]; | ||
| 674 | rts; | ||
| 675 | ENDPROC(___raw_atomic_xor_asm) | ||
| 676 | |||
| 677 | /* | ||
| 678 | * r0 = ptr | ||
| 679 | * r1 = mask | ||
| 680 | * | ||
| 681 | * Perform a logical AND between the mask bits and a 32bit word, and | ||
| 682 | * return the masked value. We need this on this architecture in | ||
| 683 | * order to invalidate the local cache before testing. | ||
| 684 | * | ||
| 685 | * Clobbers: r3:0, p1:0 | ||
| 686 | */ | ||
| 687 | ENTRY(___raw_atomic_test_asm) | ||
| 688 | p1 = r0; | ||
| 689 | r3 = r1; | ||
| 690 | r1 = -L1_CACHE_BYTES; | ||
| 691 | r1 = r0 & r1; | ||
| 692 | p0 = r1; | ||
| 693 | flushinv[p0]; | ||
| 694 | SSYNC(r2); | ||
| 695 | r0 = [p1]; | ||
| 696 | r0 = r0 & r3; | ||
| 697 | rts; | ||
| 698 | ENDPROC(___raw_atomic_test_asm) | ||
| 699 | |||
| 700 | /* | ||
| 701 | * r0 = ptr | ||
| 702 | * r1 = value | ||
| 703 | * | ||
| 704 | * Swap *ptr with value and return the old 32bit value atomically. | ||
| 705 | * Clobbers: r3:0, p1:0 | ||
| 706 | */ | ||
| 707 | #define __do_xchg(src, dst) \ | ||
| 708 | p1 = r0; \ | ||
| 709 | r3 = r1; \ | ||
| 710 | [--sp] = rets; \ | ||
| 711 | call _get_core_lock; \ | ||
| 712 | r2 = src; \ | ||
| 713 | dst = r3; \ | ||
| 714 | r3 = r2; \ | ||
| 715 | r1 = p1; \ | ||
| 716 | call _put_core_lock; \ | ||
| 717 | r0 = r3; \ | ||
| 718 | rets = [sp++]; \ | ||
| 719 | rts; | ||
| 720 | |||
| 721 | ENTRY(___raw_xchg_1_asm) | ||
| 722 | __do_xchg(b[p1] (z), b[p1]) | ||
| 723 | ENDPROC(___raw_xchg_1_asm) | ||
| 724 | |||
| 725 | ENTRY(___raw_xchg_2_asm) | ||
| 726 | __do_xchg(w[p1] (z), w[p1]) | ||
| 727 | ENDPROC(___raw_xchg_2_asm) | ||
| 728 | |||
| 729 | ENTRY(___raw_xchg_4_asm) | ||
| 730 | __do_xchg([p1], [p1]) | ||
| 731 | ENDPROC(___raw_xchg_4_asm) | ||
| 732 | |||
| 733 | /* | ||
| 734 | * r0 = ptr | ||
| 735 | * r1 = new | ||
| 736 | * r2 = old | ||
| 737 | * | ||
| 738 | * Swap *ptr with new if *ptr == old and return the previous *ptr | ||
| 739 | * value atomically. | ||
| 740 | * | ||
| 741 | * Clobbers: r3:0, p1:0 | ||
| 742 | */ | ||
| 743 | #define __do_cmpxchg(src, dst) \ | ||
| 744 | [--sp] = rets; \ | ||
| 745 | [--sp] = r4; \ | ||
| 746 | p1 = r0; \ | ||
| 747 | r3 = r1; \ | ||
| 748 | r4 = r2; \ | ||
| 749 | call _get_core_lock; \ | ||
| 750 | r2 = src; \ | ||
| 751 | cc = r2 == r4; \ | ||
| 752 | if !cc jump 1f; \ | ||
| 753 | dst = r3; \ | ||
| 754 | 1: r3 = r2; \ | ||
| 755 | r1 = p1; \ | ||
| 756 | call _put_core_lock; \ | ||
| 757 | r0 = r3; \ | ||
| 758 | r4 = [sp++]; \ | ||
| 759 | rets = [sp++]; \ | ||
| 760 | rts; | ||
| 761 | |||
| 762 | ENTRY(___raw_cmpxchg_1_asm) | ||
| 763 | __do_cmpxchg(b[p1] (z), b[p1]) | ||
| 764 | ENDPROC(___raw_cmpxchg_1_asm) | ||
| 765 | |||
| 766 | ENTRY(___raw_cmpxchg_2_asm) | ||
| 767 | __do_cmpxchg(w[p1] (z), w[p1]) | ||
| 768 | ENDPROC(___raw_cmpxchg_2_asm) | ||
| 769 | |||
| 770 | ENTRY(___raw_cmpxchg_4_asm) | ||
| 771 | __do_cmpxchg([p1], [p1]) | ||
| 772 | ENDPROC(___raw_cmpxchg_4_asm) | ||
| 773 | |||
| 774 | /* | ||
| 775 | * r0 = ptr | ||
| 776 | * r1 = bitnr | ||
| 777 | * | ||
| 778 | * Set a bit in a 32bit word and return the old 32bit value atomically. | ||
| 779 | * Clobbers: r3:0, p1:0 | ||
| 780 | */ | ||
| 781 | ENTRY(___raw_bit_set_asm) | ||
| 782 | r2 = r1; | ||
| 783 | r1 = 1; | ||
| 784 | r1 <<= r2; | ||
| 785 | jump ___raw_atomic_set_asm | ||
| 786 | ENDPROC(___raw_bit_set_asm) | ||
| 787 | |||
| 788 | /* | ||
| 789 | * r0 = ptr | ||
| 790 | * r1 = bitnr | ||
| 791 | * | ||
| 792 | * Clear a bit in a 32bit word and return the old 32bit value atomically. | ||
| 793 | * Clobbers: r3:0, p1:0 | ||
| 794 | */ | ||
| 795 | ENTRY(___raw_bit_clear_asm) | ||
| 796 | r2 = r1; | ||
| 797 | r1 = 1; | ||
| 798 | r1 <<= r2; | ||
| 799 | jump ___raw_atomic_clear_asm | ||
| 800 | ENDPROC(___raw_bit_clear_asm) | ||
| 801 | |||
| 802 | /* | ||
| 803 | * r0 = ptr | ||
| 804 | * r1 = bitnr | ||
| 805 | * | ||
| 806 | * Toggle a bit in a 32bit word and return the old 32bit value atomically. | ||
| 807 | * Clobbers: r3:0, p1:0 | ||
| 808 | */ | ||
| 809 | ENTRY(___raw_bit_toggle_asm) | ||
| 810 | r2 = r1; | ||
| 811 | r1 = 1; | ||
| 812 | r1 <<= r2; | ||
| 813 | jump ___raw_atomic_xor_asm | ||
| 814 | ENDPROC(___raw_bit_toggle_asm) | ||
| 815 | |||
| 816 | /* | ||
| 817 | * r0 = ptr | ||
| 818 | * r1 = bitnr | ||
| 819 | * | ||
| 820 | * Test-and-set a bit in a 32bit word and return the old bit value atomically. | ||
| 821 | * Clobbers: r3:0, p1:0 | ||
| 822 | */ | ||
| 823 | ENTRY(___raw_bit_test_set_asm) | ||
| 824 | [--sp] = rets; | ||
| 825 | [--sp] = r1; | ||
| 826 | call ___raw_bit_set_asm | ||
| 827 | r1 = [sp++]; | ||
| 828 | r2 = 1; | ||
| 829 | r2 <<= r1; | ||
| 830 | r0 = r0 & r2; | ||
| 831 | cc = r0 == 0; | ||
| 832 | if cc jump 1f | ||
| 833 | r0 = 1; | ||
| 834 | 1: | ||
| 835 | rets = [sp++]; | ||
| 836 | rts; | ||
| 837 | ENDPROC(___raw_bit_test_set_asm) | ||
| 838 | |||
| 839 | /* | ||
| 840 | * r0 = ptr | ||
| 841 | * r1 = bitnr | ||
| 842 | * | ||
| 843 | * Test-and-clear a bit in a 32bit word and return the old bit value atomically. | ||
| 844 | * Clobbers: r3:0, p1:0 | ||
| 845 | */ | ||
| 846 | ENTRY(___raw_bit_test_clear_asm) | ||
| 847 | [--sp] = rets; | ||
| 848 | [--sp] = r1; | ||
| 849 | call ___raw_bit_clear_asm | ||
| 850 | r1 = [sp++]; | ||
| 851 | r2 = 1; | ||
| 852 | r2 <<= r1; | ||
| 853 | r0 = r0 & r2; | ||
| 854 | cc = r0 == 0; | ||
| 855 | if cc jump 1f | ||
| 856 | r0 = 1; | ||
| 857 | 1: | ||
| 858 | rets = [sp++]; | ||
| 859 | rts; | ||
| 860 | ENDPROC(___raw_bit_test_clear_asm) | ||
| 861 | |||
| 862 | /* | ||
| 863 | * r0 = ptr | ||
| 864 | * r1 = bitnr | ||
| 865 | * | ||
| 866 | * Test-and-toggle a bit in a 32bit word, | ||
| 867 | * and return the old bit value atomically. | ||
| 868 | * Clobbers: r3:0, p1:0 | ||
| 869 | */ | ||
| 870 | ENTRY(___raw_bit_test_toggle_asm) | ||
| 871 | [--sp] = rets; | ||
| 872 | [--sp] = r1; | ||
| 873 | call ___raw_bit_toggle_asm | ||
| 874 | r1 = [sp++]; | ||
| 875 | r2 = 1; | ||
| 876 | r2 <<= r1; | ||
| 877 | r0 = r0 & r2; | ||
| 878 | cc = r0 == 0; | ||
| 879 | if cc jump 1f | ||
| 880 | r0 = 1; | ||
| 881 | 1: | ||
| 882 | rets = [sp++]; | ||
| 883 | rts; | ||
| 884 | ENDPROC(___raw_bit_test_toggle_asm) | ||
| 885 | |||
| 886 | /* | ||
| 887 | * r0 = ptr | ||
| 888 | * r1 = bitnr | ||
| 889 | * | ||
| 890 | * Test a bit in a 32bit word and return its value. | ||
| 891 | * We need this on this architecture in order to invalidate | ||
| 892 | * the local cache before testing. | ||
| 893 | * | ||
| 894 | * Clobbers: r3:0, p1:0 | ||
| 895 | */ | ||
| 896 | ENTRY(___raw_bit_test_asm) | ||
| 897 | r2 = r1; | ||
| 898 | r1 = 1; | ||
| 899 | r1 <<= r2; | ||
| 900 | jump ___raw_atomic_test_asm | ||
| 901 | ENDPROC(___raw_bit_test_asm) | ||
| 902 | |||
| 903 | /* | ||
| 904 | * r0 = ptr | ||
| 905 | * | ||
| 906 | * Fetch and return an uncached 32bit value. | ||
| 907 | * | ||
| 908 | * Clobbers: r2:0, p1:0 | ||
| 909 | */ | ||
| 910 | ENTRY(___raw_uncached_fetch_asm) | ||
| 911 | p1 = r0; | ||
| 912 | r1 = -L1_CACHE_BYTES; | ||
| 913 | r1 = r0 & r1; | ||
| 914 | p0 = r1; | ||
| 915 | flushinv[p0]; | ||
| 916 | SSYNC(r2); | ||
| 917 | r0 = [p1]; | ||
| 918 | rts; | ||
| 919 | ENDPROC(___raw_uncached_fetch_asm) | ||
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index 8f40990eea2f..6880d1ebfe60 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c | |||
| @@ -230,6 +230,19 @@ static struct platform_device smc91x_device = { | |||
| 230 | }; | 230 | }; |
| 231 | #endif | 231 | #endif |
| 232 | 232 | ||
| 233 | static struct resource bfin_gpios_resources = { | ||
| 234 | .start = 0, | ||
| 235 | .end = MAX_BLACKFIN_GPIOS - 1, | ||
| 236 | .flags = IORESOURCE_IRQ, | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct platform_device bfin_gpios_device = { | ||
| 240 | .name = "simple-gpio", | ||
| 241 | .id = -1, | ||
| 242 | .num_resources = 1, | ||
| 243 | .resource = &bfin_gpios_resources, | ||
| 244 | }; | ||
| 245 | |||
| 233 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | 246 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
| 234 | static struct resource isp1362_hcd_resources[] = { | 247 | static struct resource isp1362_hcd_resources[] = { |
| 235 | { | 248 | { |
| @@ -287,23 +300,33 @@ static struct platform_device bfin_uart_device = { | |||
| 287 | #endif | 300 | #endif |
| 288 | 301 | ||
| 289 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 302 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 290 | static struct resource bfin_sir_resources[] = { | ||
| 291 | #ifdef CONFIG_BFIN_SIR0 | 303 | #ifdef CONFIG_BFIN_SIR0 |
| 304 | static struct resource bfin_sir0_resources[] = { | ||
| 292 | { | 305 | { |
| 293 | .start = 0xFFC00400, | 306 | .start = 0xFFC00400, |
| 294 | .end = 0xFFC004FF, | 307 | .end = 0xFFC004FF, |
| 295 | .flags = IORESOURCE_MEM, | 308 | .flags = IORESOURCE_MEM, |
| 296 | }, | 309 | }, |
| 297 | #endif | 310 | { |
| 311 | .start = IRQ_UART0_RX, | ||
| 312 | .end = IRQ_UART0_RX+1, | ||
| 313 | .flags = IORESOURCE_IRQ, | ||
| 314 | }, | ||
| 315 | { | ||
| 316 | .start = CH_UART0_RX, | ||
| 317 | .end = CH_UART0_RX+1, | ||
| 318 | .flags = IORESOURCE_DMA, | ||
| 319 | }, | ||
| 298 | }; | 320 | }; |
| 299 | 321 | ||
| 300 | static struct platform_device bfin_sir_device = { | 322 | static struct platform_device bfin_sir0_device = { |
| 301 | .name = "bfin_sir", | 323 | .name = "bfin_sir", |
| 302 | .id = 0, | 324 | .id = 0, |
| 303 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 325 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 304 | .resource = bfin_sir_resources, | 326 | .resource = bfin_sir0_resources, |
| 305 | }; | 327 | }; |
| 306 | #endif | 328 | #endif |
| 329 | #endif | ||
| 307 | 330 | ||
| 308 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | 331 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) |
| 309 | #define PATA_INT IRQ_PF46 | 332 | #define PATA_INT IRQ_PF46 |
| @@ -382,7 +405,9 @@ static struct platform_device *cm_bf561_devices[] __initdata = { | |||
| 382 | #endif | 405 | #endif |
| 383 | 406 | ||
| 384 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 407 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 385 | &bfin_sir_device, | 408 | #ifdef CONFIG_BFIN_SIR0 |
| 409 | &bfin_sir0_device, | ||
| 410 | #endif | ||
| 386 | #endif | 411 | #endif |
| 387 | 412 | ||
| 388 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | 413 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
| @@ -400,6 +425,8 @@ static struct platform_device *cm_bf561_devices[] __initdata = { | |||
| 400 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | 425 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) |
| 401 | &bfin_pata_device, | 426 | &bfin_pata_device, |
| 402 | #endif | 427 | #endif |
| 428 | |||
| 429 | &bfin_gpios_device, | ||
| 403 | }; | 430 | }; |
| 404 | 431 | ||
| 405 | static int __init cm_bf561_init(void) | 432 | static int __init cm_bf561_init(void) |
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 50b4cdceccfe..0e2178a1aec5 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c | |||
| @@ -43,53 +43,42 @@ | |||
| 43 | /* | 43 | /* |
| 44 | * Name the Board for the /proc/cpuinfo | 44 | * Name the Board for the /proc/cpuinfo |
| 45 | */ | 45 | */ |
| 46 | const char bfin_board_name[] = "ADDS-BF561-EZKIT"; | 46 | const char bfin_board_name[] = "ADI BF561-EZKIT"; |
| 47 | |||
| 48 | #define ISP1761_BASE 0x2C0F0000 | ||
| 49 | #define ISP1761_IRQ IRQ_PF10 | ||
| 50 | 47 | ||
| 51 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | 48 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
| 52 | static struct resource bfin_isp1761_resources[] = { | 49 | #include <linux/usb/isp1760.h> |
| 53 | { | 50 | static struct resource bfin_isp1760_resources[] = { |
| 54 | .name = "isp1761-regs", | 51 | [0] = { |
| 55 | .start = ISP1761_BASE + 0x00000000, | 52 | .start = 0x2C0F0000, |
| 56 | .end = ISP1761_BASE + 0x000fffff, | 53 | .end = 0x203C0000 + 0xfffff, |
| 57 | .flags = IORESOURCE_MEM, | 54 | .flags = IORESOURCE_MEM, |
| 58 | }, | 55 | }, |
| 59 | { | 56 | [1] = { |
| 60 | .start = ISP1761_IRQ, | 57 | .start = IRQ_PF10, |
| 61 | .end = ISP1761_IRQ, | 58 | .end = IRQ_PF10, |
| 62 | .flags = IORESOURCE_IRQ, | 59 | .flags = IORESOURCE_IRQ, |
| 63 | }, | 60 | }, |
| 64 | }; | 61 | }; |
| 65 | 62 | ||
| 66 | static struct platform_device bfin_isp1761_device = { | 63 | static struct isp1760_platform_data isp1760_priv = { |
| 67 | .name = "isp1761", | 64 | .is_isp1761 = 0, |
| 68 | .id = 0, | 65 | .port1_disable = 0, |
| 69 | .num_resources = ARRAY_SIZE(bfin_isp1761_resources), | 66 | .bus_width_16 = 1, |
| 70 | .resource = bfin_isp1761_resources, | 67 | .port1_otg = 0, |
| 68 | .analog_oc = 0, | ||
| 69 | .dack_polarity_high = 0, | ||
| 70 | .dreq_polarity_high = 0, | ||
| 71 | }; | 71 | }; |
| 72 | 72 | ||
| 73 | static struct platform_device *bfin_isp1761_devices[] = { | 73 | static struct platform_device bfin_isp1760_device = { |
| 74 | &bfin_isp1761_device, | 74 | .name = "isp1760-hcd", |
| 75 | .id = 0, | ||
| 76 | .dev = { | ||
| 77 | .platform_data = &isp1760_priv, | ||
| 78 | }, | ||
| 79 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | ||
| 80 | .resource = bfin_isp1760_resources, | ||
| 75 | }; | 81 | }; |
| 76 | |||
| 77 | int __init bfin_isp1761_init(void) | ||
| 78 | { | ||
| 79 | unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices); | ||
| 80 | |||
| 81 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 82 | set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); | ||
| 83 | |||
| 84 | return platform_add_devices(bfin_isp1761_devices, num_devices); | ||
| 85 | } | ||
| 86 | |||
| 87 | void __exit bfin_isp1761_exit(void) | ||
| 88 | { | ||
| 89 | platform_device_unregister(&bfin_isp1761_device); | ||
| 90 | } | ||
| 91 | |||
| 92 | arch_initcall(bfin_isp1761_init); | ||
| 93 | #endif | 82 | #endif |
| 94 | 83 | ||
| 95 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | 84 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
| @@ -221,23 +210,33 @@ static struct platform_device bfin_uart_device = { | |||
| 221 | #endif | 210 | #endif |
| 222 | 211 | ||
| 223 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 212 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 224 | static struct resource bfin_sir_resources[] = { | ||
| 225 | #ifdef CONFIG_BFIN_SIR0 | 213 | #ifdef CONFIG_BFIN_SIR0 |
| 214 | static struct resource bfin_sir0_resources[] = { | ||
| 226 | { | 215 | { |
| 227 | .start = 0xFFC00400, | 216 | .start = 0xFFC00400, |
| 228 | .end = 0xFFC004FF, | 217 | .end = 0xFFC004FF, |
| 229 | .flags = IORESOURCE_MEM, | 218 | .flags = IORESOURCE_MEM, |
| 230 | }, | 219 | }, |
| 231 | #endif | 220 | { |
| 221 | .start = IRQ_UART0_RX, | ||
| 222 | .end = IRQ_UART0_RX+1, | ||
| 223 | .flags = IORESOURCE_IRQ, | ||
| 224 | }, | ||
| 225 | { | ||
| 226 | .start = CH_UART0_RX, | ||
| 227 | .end = CH_UART0_RX+1, | ||
| 228 | .flags = IORESOURCE_DMA, | ||
| 229 | }, | ||
| 232 | }; | 230 | }; |
| 233 | 231 | ||
| 234 | static struct platform_device bfin_sir_device = { | 232 | static struct platform_device bfin_sir0_device = { |
| 235 | .name = "bfin_sir", | 233 | .name = "bfin_sir", |
| 236 | .id = 0, | 234 | .id = 0, |
| 237 | .num_resources = ARRAY_SIZE(bfin_sir_resources), | 235 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 238 | .resource = bfin_sir_resources, | 236 | .resource = bfin_sir0_resources, |
| 239 | }; | 237 | }; |
| 240 | #endif | 238 | #endif |
| 239 | #endif | ||
| 241 | 240 | ||
| 242 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | 241 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
| 243 | static struct mtd_partition ezkit_partitions[] = { | 242 | static struct mtd_partition ezkit_partitions[] = { |
| @@ -449,6 +448,10 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
| 449 | &net2272_bfin_device, | 448 | &net2272_bfin_device, |
| 450 | #endif | 449 | #endif |
| 451 | 450 | ||
| 451 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | ||
| 452 | &bfin_isp1760_device, | ||
| 453 | #endif | ||
| 454 | |||
| 452 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 455 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 453 | &bfin_spi0_device, | 456 | &bfin_spi0_device, |
| 454 | #endif | 457 | #endif |
| @@ -458,7 +461,9 @@ static struct platform_device *ezkit_devices[] __initdata = { | |||
| 458 | #endif | 461 | #endif |
| 459 | 462 | ||
| 460 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | 463 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
| 461 | &bfin_sir_device, | 464 | #ifdef CONFIG_BFIN_SIR0 |
| 465 | &bfin_sir0_device, | ||
| 466 | #endif | ||
| 462 | #endif | 467 | #endif |
| 463 | 468 | ||
| 464 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | 469 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c index 2faa0072d614..0ba366a0e696 100644 --- a/arch/blackfin/mach-bf561/boards/generic_board.c +++ b/arch/blackfin/mach-bf561/boards/generic_board.c | |||
| @@ -62,10 +62,45 @@ static struct platform_device smc91x_device = { | |||
| 62 | }; | 62 | }; |
| 63 | #endif | 63 | #endif |
| 64 | 64 | ||
| 65 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 66 | #ifdef CONFIG_BFIN_SIR0 | ||
| 67 | static struct resource bfin_sir0_resources[] = { | ||
| 68 | { | ||
| 69 | .start = 0xFFC00400, | ||
| 70 | .end = 0xFFC004FF, | ||
| 71 | .flags = IORESOURCE_MEM, | ||
| 72 | }, | ||
| 73 | { | ||
| 74 | .start = IRQ_UART0_RX, | ||
| 75 | .end = IRQ_UART0_RX+1, | ||
| 76 | .flags = IORESOURCE_IRQ, | ||
| 77 | }, | ||
| 78 | { | ||
| 79 | .start = CH_UART0_RX, | ||
| 80 | .end = CH_UART0_RX+1, | ||
| 81 | .flags = IORESOURCE_DMA, | ||
| 82 | }, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct platform_device bfin_sir0_device = { | ||
| 86 | .name = "bfin_sir", | ||
| 87 | .id = 0, | ||
| 88 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 89 | .resource = bfin_sir0_resources, | ||
| 90 | }; | ||
| 91 | #endif | ||
| 92 | #endif | ||
| 93 | |||
| 65 | static struct platform_device *generic_board_devices[] __initdata = { | 94 | static struct platform_device *generic_board_devices[] __initdata = { |
| 66 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 95 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
| 67 | &smc91x_device, | 96 | &smc91x_device, |
| 68 | #endif | 97 | #endif |
| 98 | |||
| 99 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 100 | #ifdef CONFIG_BFIN_SIR0 | ||
| 101 | &bfin_sir0_device, | ||
| 102 | #endif | ||
| 103 | #endif | ||
| 69 | }; | 104 | }; |
| 70 | 105 | ||
| 71 | static int __init generic_board_init(void) | 106 | static int __init generic_board_init(void) |
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c index c9174b39f98d..6f77dbe952f5 100644 --- a/arch/blackfin/mach-bf561/boards/tepla.c +++ b/arch/blackfin/mach-bf561/boards/tepla.c | |||
| @@ -44,8 +44,42 @@ static struct platform_device smc91x_device = { | |||
| 44 | .resource = smc91x_resources, | 44 | .resource = smc91x_resources, |
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 48 | #ifdef CONFIG_BFIN_SIR0 | ||
| 49 | static struct resource bfin_sir0_resources[] = { | ||
| 50 | { | ||
| 51 | .start = 0xFFC00400, | ||
| 52 | .end = 0xFFC004FF, | ||
| 53 | .flags = IORESOURCE_MEM, | ||
| 54 | }, | ||
| 55 | { | ||
| 56 | .start = IRQ_UART0_RX, | ||
| 57 | .end = IRQ_UART0_RX+1, | ||
| 58 | .flags = IORESOURCE_IRQ, | ||
| 59 | }, | ||
| 60 | { | ||
| 61 | .start = CH_UART0_RX, | ||
| 62 | .end = CH_UART0_RX+1, | ||
| 63 | .flags = IORESOURCE_DMA, | ||
| 64 | }, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct platform_device bfin_sir0_device = { | ||
| 68 | .name = "bfin_sir", | ||
| 69 | .id = 0, | ||
| 70 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 71 | .resource = bfin_sir0_resources, | ||
| 72 | }; | ||
| 73 | #endif | ||
| 74 | #endif | ||
| 75 | |||
| 47 | static struct platform_device *tepla_devices[] __initdata = { | 76 | static struct platform_device *tepla_devices[] __initdata = { |
| 48 | &smc91x_device, | 77 | &smc91x_device, |
| 78 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 79 | #ifdef CONFIG_BFIN_SIR0 | ||
| 80 | &bfin_sir0_device, | ||
| 81 | #endif | ||
| 82 | #endif | ||
| 49 | }; | 83 | }; |
| 50 | 84 | ||
| 51 | static int __init tepla_init(void) | 85 | static int __init tepla_init(void) |
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c index 24415eb82698..42b0037afe61 100644 --- a/arch/blackfin/mach-bf561/dma.c +++ b/arch/blackfin/mach-bf561/dma.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <asm/blackfin.h> | 31 | #include <asm/blackfin.h> |
| 32 | #include <asm/dma.h> | 32 | #include <asm/dma.h> |
| 33 | 33 | ||
| 34 | struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { | 34 | struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { |
| 35 | (struct dma_register *) DMA1_0_NEXT_DESC_PTR, | 35 | (struct dma_register *) DMA1_0_NEXT_DESC_PTR, |
| 36 | (struct dma_register *) DMA1_1_NEXT_DESC_PTR, | 36 | (struct dma_register *) DMA1_1_NEXT_DESC_PTR, |
| 37 | (struct dma_register *) DMA1_2_NEXT_DESC_PTR, | 37 | (struct dma_register *) DMA1_2_NEXT_DESC_PTR, |
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S deleted file mode 100644 index 31a777a9e699..000000000000 --- a/arch/blackfin/mach-bf561/head.S +++ /dev/null | |||
| @@ -1,136 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf561/head.S | ||
| 3 | * Based on: arch/blackfin/mach-bf533/head.S | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: BF561 startup file | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/linkage.h> | ||
| 31 | #include <linux/init.h> | ||
| 32 | #include <asm/blackfin.h> | ||
| 33 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 34 | #include <asm/clocks.h> | ||
| 35 | #include <mach/mem_init.h> | ||
| 36 | #endif | ||
| 37 | |||
| 38 | .section .l1.text | ||
| 39 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | ||
| 40 | ENTRY(_start_dma_code) | ||
| 41 | p0.h = hi(SICA_IWR0); | ||
| 42 | p0.l = lo(SICA_IWR0); | ||
| 43 | r0.l = 0x1; | ||
| 44 | [p0] = r0; | ||
| 45 | SSYNC; | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Set PLL_CTL | ||
| 49 | * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors | ||
| 50 | * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK | ||
| 51 | * - [7] = output delay (add 200ps of delay to mem signals) | ||
| 52 | * - [6] = input delay (add 200ps of input delay to mem signals) | ||
| 53 | * - [5] = PDWN : 1=All Clocks off | ||
| 54 | * - [3] = STOPCK : 1=Core Clock off | ||
| 55 | * - [1] = PLL_OFF : 1=Disable Power to PLL | ||
| 56 | * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL | ||
| 57 | * all other bits set to zero | ||
| 58 | */ | ||
| 59 | |||
| 60 | p0.h = hi(PLL_LOCKCNT); | ||
| 61 | p0.l = lo(PLL_LOCKCNT); | ||
| 62 | r0 = 0x300(Z); | ||
| 63 | w[p0] = r0.l; | ||
| 64 | ssync; | ||
| 65 | |||
| 66 | P2.H = hi(EBIU_SDGCTL); | ||
| 67 | P2.L = lo(EBIU_SDGCTL); | ||
| 68 | R0 = [P2]; | ||
| 69 | BITSET (R0, 24); | ||
| 70 | [P2] = R0; | ||
| 71 | SSYNC; | ||
| 72 | |||
| 73 | r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ | ||
| 74 | r0 = r0 << 9; /* Shift it over, */ | ||
| 75 | r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ | ||
| 76 | r0 = r1 | r0; | ||
| 77 | r1 = PLL_BYPASS; /* Bypass the PLL? */ | ||
| 78 | r1 = r1 << 8; /* Shift it over */ | ||
| 79 | r0 = r1 | r0; /* add them all together */ | ||
| 80 | #ifdef ANOMALY_05000265 | ||
| 81 | BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */ | ||
| 82 | #endif | ||
| 83 | |||
| 84 | p0.h = hi(PLL_CTL); | ||
| 85 | p0.l = lo(PLL_CTL); /* Load the address */ | ||
| 86 | cli r2; /* Disable interrupts */ | ||
| 87 | ssync; | ||
| 88 | w[p0] = r0.l; /* Set the value */ | ||
| 89 | idle; /* Wait for the PLL to stablize */ | ||
| 90 | sti r2; /* Enable interrupts */ | ||
| 91 | |||
| 92 | .Lcheck_again: | ||
| 93 | p0.h = hi(PLL_STAT); | ||
| 94 | p0.l = lo(PLL_STAT); | ||
| 95 | R0 = W[P0](Z); | ||
| 96 | CC = BITTST(R0,5); | ||
| 97 | if ! CC jump .Lcheck_again; | ||
| 98 | |||
| 99 | /* Configure SCLK & CCLK Dividers */ | ||
| 100 | r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | ||
| 101 | p0.h = hi(PLL_DIV); | ||
| 102 | p0.l = lo(PLL_DIV); | ||
| 103 | w[p0] = r0.l; | ||
| 104 | ssync; | ||
| 105 | |||
| 106 | p0.l = lo(EBIU_SDRRC); | ||
| 107 | p0.h = hi(EBIU_SDRRC); | ||
| 108 | r0 = mem_SDRRC; | ||
| 109 | w[p0] = r0.l; | ||
| 110 | ssync; | ||
| 111 | |||
| 112 | P2.H = hi(EBIU_SDGCTL); | ||
| 113 | P2.L = lo(EBIU_SDGCTL); | ||
| 114 | R0 = [P2]; | ||
| 115 | BITCLR (R0, 24); | ||
| 116 | p0.h = hi(EBIU_SDSTAT); | ||
| 117 | p0.l = lo(EBIU_SDSTAT); | ||
| 118 | r2.l = w[p0]; | ||
| 119 | cc = bittst(r2,3); | ||
| 120 | if !cc jump .Lskip; | ||
| 121 | NOP; | ||
| 122 | BITSET (R0, 23); | ||
| 123 | .Lskip: | ||
| 124 | [P2] = R0; | ||
| 125 | SSYNC; | ||
| 126 | |||
| 127 | R0.L = lo(mem_SDGCTL); | ||
| 128 | R0.H = hi(mem_SDGCTL); | ||
| 129 | R1 = [p2]; | ||
| 130 | R1 = R1 | R0; | ||
| 131 | [P2] = R1; | ||
| 132 | SSYNC; | ||
| 133 | |||
| 134 | RTS; | ||
| 135 | ENDPROC(_start_dma_code) | ||
| 136 | #endif /* CONFIG_BFIN_KERNEL_CLOCK */ | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 22990df04ae1..1a9e17562821 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file shoule be up to date with: |
| 10 | * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List | 10 | * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
| @@ -264,6 +264,18 @@ | |||
| 264 | #define ANOMALY_05000371 (1) | 264 | #define ANOMALY_05000371 (1) |
| 265 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 265 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
| 266 | #define ANOMALY_05000403 (1) | 266 | #define ANOMALY_05000403 (1) |
| 267 | /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ | ||
| 268 | #define ANOMALY_05000412 (1) | ||
| 269 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | ||
| 270 | #define ANOMALY_05000416 (1) | ||
| 271 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ | ||
| 272 | #define ANOMALY_05000425 (1) | ||
| 273 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | ||
| 274 | #define ANOMALY_05000426 (1) | ||
| 275 | /* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */ | ||
| 276 | #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) | ||
| 277 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | ||
| 278 | #define ANOMALY_05000443 (1) | ||
| 267 | 279 | ||
| 268 | /* Anomalies that don't exist on this proc */ | 280 | /* Anomalies that don't exist on this proc */ |
| 269 | #define ANOMALY_05000158 (0) | 281 | #define ANOMALY_05000158 (0) |
| @@ -272,5 +284,7 @@ | |||
| 272 | #define ANOMALY_05000311 (0) | 284 | #define ANOMALY_05000311 (0) |
| 273 | #define ANOMALY_05000353 (1) | 285 | #define ANOMALY_05000353 (1) |
| 274 | #define ANOMALY_05000386 (1) | 286 | #define ANOMALY_05000386 (1) |
| 287 | #define ANOMALY_05000432 (0) | ||
| 288 | #define ANOMALY_05000435 (0) | ||
| 275 | 289 | ||
| 276 | #endif | 290 | #endif |
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h index 18b1b3a223ab..9968362a2ee4 100644 --- a/arch/blackfin/mach-bf561/include/mach/bf561.h +++ b/arch/blackfin/mach-bf561/include/mach/bf561.h | |||
| @@ -215,7 +215,7 @@ | |||
| 215 | #endif | 215 | #endif |
| 216 | 216 | ||
| 217 | #ifndef CPU | 217 | #ifndef CPU |
| 218 | #error Unknown CPU type - This kernel doesn't seem to be configured properly | 218 | #error "Unknown CPU type - This kernel doesn't seem to be configured properly" |
| 219 | #endif | 219 | #endif |
| 220 | 220 | ||
| 221 | #endif /* __MACH_BF561_H__ */ | 221 | #endif /* __MACH_BF561_H__ */ |
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h b/arch/blackfin/mach-bf561/include/mach/bfin_sir.h deleted file mode 100644 index 9bb87e9e2e9b..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/bfin_sir.h +++ /dev/null | |||
| @@ -1,125 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Blackfin Infra-red Driver | ||
| 3 | * | ||
| 4 | * Copyright 2006-2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Enter bugs at http://blackfin.uclinux.org/ | ||
| 7 | * | ||
| 8 | * Licensed under the GPL-2 or later. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/serial.h> | ||
| 13 | #include <asm/dma.h> | ||
| 14 | #include <asm/portmux.h> | ||
| 15 | |||
| 16 | #define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) | ||
| 17 | #define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) | ||
| 18 | #define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER) | ||
| 19 | #define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) | ||
| 20 | #define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR) | ||
| 21 | #define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) | ||
| 22 | #define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL) | ||
| 23 | |||
| 24 | #define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v) | ||
| 25 | #define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v) | ||
| 26 | #define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v) | ||
| 27 | #define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v) | ||
| 28 | #define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v) | ||
| 29 | #define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v) | ||
| 30 | |||
| 31 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 32 | struct dma_rx_buf { | ||
| 33 | char *buf; | ||
| 34 | int head; | ||
| 35 | int tail; | ||
| 36 | }; | ||
| 37 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 38 | |||
| 39 | struct bfin_sir_port { | ||
| 40 | unsigned char __iomem *membase; | ||
| 41 | unsigned int irq; | ||
| 42 | unsigned int lsr; | ||
| 43 | unsigned long clk; | ||
| 44 | struct net_device *dev; | ||
| 45 | #ifdef CONFIG_SIR_BFIN_DMA | ||
| 46 | int tx_done; | ||
| 47 | struct dma_rx_buf rx_dma_buf; | ||
| 48 | struct timer_list rx_dma_timer; | ||
| 49 | int rx_dma_nrows; | ||
| 50 | #endif /* CONFIG_SIR_BFIN_DMA */ | ||
| 51 | unsigned int tx_dma_channel; | ||
| 52 | unsigned int rx_dma_channel; | ||
| 53 | }; | ||
| 54 | |||
| 55 | struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS]; | ||
| 56 | |||
| 57 | struct bfin_sir_port_res { | ||
| 58 | unsigned long base_addr; | ||
| 59 | int irq; | ||
| 60 | unsigned int rx_dma_channel; | ||
| 61 | unsigned int tx_dma_channel; | ||
| 62 | }; | ||
| 63 | |||
| 64 | struct bfin_sir_port_res bfin_sir_port_resource[] = { | ||
| 65 | #ifdef CONFIG_BFIN_SIR0 | ||
| 66 | { | ||
| 67 | 0xFFC00400, | ||
| 68 | IRQ_UART_RX, | ||
| 69 | CH_UART_RX, | ||
| 70 | CH_UART_TX, | ||
| 71 | }, | ||
| 72 | #endif | ||
| 73 | }; | ||
| 74 | |||
| 75 | int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource); | ||
| 76 | |||
| 77 | struct bfin_sir_self { | ||
| 78 | struct bfin_sir_port *sir_port; | ||
| 79 | spinlock_t lock; | ||
| 80 | unsigned int open; | ||
| 81 | int speed; | ||
| 82 | int newspeed; | ||
| 83 | |||
| 84 | struct sk_buff *txskb; | ||
| 85 | struct sk_buff *rxskb; | ||
| 86 | struct net_device_stats stats; | ||
| 87 | struct device *dev; | ||
| 88 | struct irlap_cb *irlap; | ||
| 89 | struct qos_info qos; | ||
| 90 | |||
| 91 | iobuff_t tx_buff; | ||
| 92 | iobuff_t rx_buff; | ||
| 93 | |||
| 94 | struct work_struct work; | ||
| 95 | int mtt; | ||
| 96 | }; | ||
| 97 | |||
| 98 | static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port) | ||
| 99 | { | ||
| 100 | unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR); | ||
| 101 | port->lsr |= (lsr & (BI|FE|PE|OE)); | ||
| 102 | return lsr | port->lsr; | ||
| 103 | } | ||
| 104 | |||
| 105 | static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port) | ||
| 106 | { | ||
| 107 | port->lsr = 0; | ||
| 108 | bfin_read16(port->membase + OFFSET_LSR); | ||
| 109 | } | ||
| 110 | |||
| 111 | #define DRIVER_NAME "bfin_sir" | ||
| 112 | |||
| 113 | static int bfin_sir_hw_init(void) | ||
| 114 | { | ||
| 115 | int ret = -ENODEV; | ||
| 116 | #ifdef CONFIG_BFIN_SIR0 | ||
| 117 | ret = peripheral_request(P_UART0_TX, DRIVER_NAME); | ||
| 118 | if (ret) | ||
| 119 | return ret; | ||
| 120 | ret = peripheral_request(P_UART0_RX, DRIVER_NAME); | ||
| 121 | if (ret) | ||
| 122 | return ret; | ||
| 123 | #endif | ||
| 124 | return ret; | ||
| 125 | } | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index 0ea8666e6764..f79f6626b7ec 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h | |||
| @@ -66,8 +66,12 @@ | |||
| 66 | 66 | ||
| 67 | #define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) | 67 | #define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) |
| 68 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) | 68 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) |
| 69 | #define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2)) | ||
| 70 | #define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val) | ||
| 69 | #define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) | 71 | #define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) |
| 70 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) | 72 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) |
| 73 | #define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2)) | ||
| 74 | #define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val) | ||
| 71 | 75 | ||
| 72 | #define BFIN_UART_NR_PORTS 1 | 76 | #define BFIN_UART_NR_PORTS 1 |
| 73 | 77 | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index c14d63402e70..95d609f11c97 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h | |||
| @@ -39,65 +39,15 @@ | |||
| 39 | /*include core specific register pointer definitions*/ | 39 | /*include core specific register pointer definitions*/ |
| 40 | #include <asm/cdef_LPBlackfin.h> | 40 | #include <asm/cdef_LPBlackfin.h> |
| 41 | 41 | ||
| 42 | #include <asm/system.h> | ||
| 43 | |||
| 44 | /*********************************************************************************** */ | 42 | /*********************************************************************************** */ |
| 45 | /* System MMR Register Map */ | 43 | /* System MMR Register Map */ |
| 46 | /*********************************************************************************** */ | 44 | /*********************************************************************************** */ |
| 47 | 45 | ||
| 48 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ | 46 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ |
| 49 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | 47 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 50 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 51 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 52 | { | ||
| 53 | unsigned long flags, iwr0, iwr1; | ||
| 54 | |||
| 55 | if (val == bfin_read_PLL_CTL()) | ||
| 56 | return; | ||
| 57 | |||
| 58 | local_irq_save(flags); | ||
| 59 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 60 | iwr0 = bfin_read32(SICA_IWR0); | ||
| 61 | iwr1 = bfin_read32(SICA_IWR1); | ||
| 62 | /* Only allow PPL Wakeup) */ | ||
| 63 | bfin_write32(SICA_IWR0, IWR_ENABLE(0)); | ||
| 64 | bfin_write32(SICA_IWR1, 0); | ||
| 65 | |||
| 66 | bfin_write16(PLL_CTL, val); | ||
| 67 | SSYNC(); | ||
| 68 | asm("IDLE;"); | ||
| 69 | |||
| 70 | bfin_write32(SICA_IWR0, iwr0); | ||
| 71 | bfin_write32(SICA_IWR1, iwr1); | ||
| 72 | local_irq_restore(flags); | ||
| 73 | } | ||
| 74 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) | 48 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 75 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) | 49 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) |
| 76 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | 50 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| 77 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 78 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 79 | { | ||
| 80 | unsigned long flags, iwr0, iwr1; | ||
| 81 | |||
| 82 | if (val == bfin_read_VR_CTL()) | ||
| 83 | return; | ||
| 84 | |||
| 85 | local_irq_save(flags); | ||
| 86 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 87 | iwr0 = bfin_read32(SICA_IWR0); | ||
| 88 | iwr1 = bfin_read32(SICA_IWR1); | ||
| 89 | /* Only allow PPL Wakeup) */ | ||
| 90 | bfin_write32(SICA_IWR0, IWR_ENABLE(0)); | ||
| 91 | bfin_write32(SICA_IWR1, 0); | ||
| 92 | |||
| 93 | bfin_write16(VR_CTL, val); | ||
| 94 | SSYNC(); | ||
| 95 | asm("IDLE;"); | ||
| 96 | |||
| 97 | bfin_write32(SICA_IWR0, iwr0); | ||
| 98 | bfin_write32(SICA_IWR1, iwr1); | ||
| 99 | local_irq_restore(flags); | ||
| 100 | } | ||
| 101 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | 51 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 102 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) | 52 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) |
| 103 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | 53 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| @@ -1576,4 +1526,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) | |||
| 1576 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() | 1526 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() |
| 1577 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) | 1527 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) |
| 1578 | 1528 | ||
| 1529 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
| 1530 | #include <asm/irq.h> | ||
| 1531 | |||
| 1532 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| 1533 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| 1534 | { | ||
| 1535 | unsigned long flags, iwr0, iwr1; | ||
| 1536 | |||
| 1537 | if (val == bfin_read_PLL_CTL()) | ||
| 1538 | return; | ||
| 1539 | |||
| 1540 | local_irq_save_hw(flags); | ||
| 1541 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 1542 | iwr0 = bfin_read32(SICA_IWR0); | ||
| 1543 | iwr1 = bfin_read32(SICA_IWR1); | ||
| 1544 | /* Only allow PPL Wakeup) */ | ||
| 1545 | bfin_write32(SICA_IWR0, IWR_ENABLE(0)); | ||
| 1546 | bfin_write32(SICA_IWR1, 0); | ||
| 1547 | |||
| 1548 | bfin_write16(PLL_CTL, val); | ||
| 1549 | SSYNC(); | ||
| 1550 | asm("IDLE;"); | ||
| 1551 | |||
| 1552 | bfin_write32(SICA_IWR0, iwr0); | ||
| 1553 | bfin_write32(SICA_IWR1, iwr1); | ||
| 1554 | local_irq_restore_hw(flags); | ||
| 1555 | } | ||
| 1556 | |||
| 1557 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| 1558 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| 1559 | { | ||
| 1560 | unsigned long flags, iwr0, iwr1; | ||
| 1561 | |||
| 1562 | if (val == bfin_read_VR_CTL()) | ||
| 1563 | return; | ||
| 1564 | |||
| 1565 | local_irq_save_hw(flags); | ||
| 1566 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| 1567 | iwr0 = bfin_read32(SICA_IWR0); | ||
| 1568 | iwr1 = bfin_read32(SICA_IWR1); | ||
| 1569 | /* Only allow PPL Wakeup) */ | ||
| 1570 | bfin_write32(SICA_IWR0, IWR_ENABLE(0)); | ||
| 1571 | bfin_write32(SICA_IWR1, 0); | ||
| 1572 | |||
| 1573 | bfin_write16(VR_CTL, val); | ||
| 1574 | SSYNC(); | ||
| 1575 | asm("IDLE;"); | ||
| 1576 | |||
| 1577 | bfin_write32(SICA_IWR0, iwr0); | ||
| 1578 | bfin_write32(SICA_IWR1, iwr1); | ||
| 1579 | local_irq_restore_hw(flags); | ||
| 1580 | } | ||
| 1581 | |||
| 1579 | #endif /* _CDEF_BF561_H */ | 1582 | #endif /* _CDEF_BF561_H */ |
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 4eca2026bb92..d7c509759659 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h | |||
| @@ -912,6 +912,9 @@ | |||
| 912 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ | 912 | #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ |
| 913 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ | 913 | #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ |
| 914 | 914 | ||
| 915 | /* SICA_SYSCR Masks */ | ||
| 916 | #define COREB_SRAM_INIT 0x0020 | ||
| 917 | |||
| 915 | /* SWRST Mask */ | 918 | /* SWRST Mask */ |
| 916 | #define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ | 919 | #define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ |
| 917 | #define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ | 920 | #define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ |
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h index 8bc46cd89a02..13647c71f1c7 100644 --- a/arch/blackfin/mach-bf561/include/mach/dma.h +++ b/arch/blackfin/mach-bf561/include/mach/dma.h | |||
| @@ -1,13 +1,17 @@ | |||
| 1 | /***************************************************************************** | 1 | /* mach/dma.h - arch-specific DMA defines |
| 2 | * | 2 | * |
| 3 | * BF-533/2/1 Specific Declarations | 3 | * Copyright 2004-2008 Analog Devices Inc. |
| 4 | * | 4 | * |
| 5 | ****************************************************************************/ | 5 | * Licensed under the GPL-2 or later. |
| 6 | */ | ||
| 6 | 7 | ||
| 7 | #ifndef _MACH_DMA_H_ | 8 | #ifndef _MACH_DMA_H_ |
| 8 | #define _MACH_DMA_H_ | 9 | #define _MACH_DMA_H_ |
| 9 | 10 | ||
| 10 | #define MAX_BLACKFIN_DMA_CHANNEL 36 | 11 | #define MAX_DMA_CHANNELS 36 |
| 12 | |||
| 13 | /* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */ | ||
| 14 | #define MAX_DMA_SUSPEND_CHANNELS 32 | ||
| 11 | 15 | ||
| 12 | #define CH_PPI0 0 | 16 | #define CH_PPI0 0 |
| 13 | #define CH_PPI (CH_PPI0) | 17 | #define CH_PPI (CH_PPI0) |
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h new file mode 100644 index 000000000000..7882f79e1ade --- /dev/null +++ b/arch/blackfin/mach-bf561/include/mach/gpio.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf561/include/mach/gpio.h | ||
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 4 | * | ||
| 5 | * Copyright (C) 2008 Analog Devices Inc. | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | #ifndef _MACH_GPIO_H_ | ||
| 11 | #define _MACH_GPIO_H_ | ||
| 12 | |||
| 13 | #define MAX_BLACKFIN_GPIOS 48 | ||
| 14 | |||
| 15 | #define GPIO_PF0 0 | ||
| 16 | #define GPIO_PF1 1 | ||
| 17 | #define GPIO_PF2 2 | ||
| 18 | #define GPIO_PF3 3 | ||
| 19 | #define GPIO_PF4 4 | ||
| 20 | #define GPIO_PF5 5 | ||
| 21 | #define GPIO_PF6 6 | ||
| 22 | #define GPIO_PF7 7 | ||
| 23 | #define GPIO_PF8 8 | ||
| 24 | #define GPIO_PF9 9 | ||
| 25 | #define GPIO_PF10 10 | ||
| 26 | #define GPIO_PF11 11 | ||
| 27 | #define GPIO_PF12 12 | ||
| 28 | #define GPIO_PF13 13 | ||
| 29 | #define GPIO_PF14 14 | ||
| 30 | #define GPIO_PF15 15 | ||
| 31 | #define GPIO_PF16 16 | ||
| 32 | #define GPIO_PF17 17 | ||
| 33 | #define GPIO_PF18 18 | ||
| 34 | #define GPIO_PF19 19 | ||
| 35 | #define GPIO_PF20 20 | ||
| 36 | #define GPIO_PF21 21 | ||
| 37 | #define GPIO_PF22 22 | ||
| 38 | #define GPIO_PF23 23 | ||
| 39 | #define GPIO_PF24 24 | ||
| 40 | #define GPIO_PF25 25 | ||
| 41 | #define GPIO_PF26 26 | ||
| 42 | #define GPIO_PF27 27 | ||
| 43 | #define GPIO_PF28 28 | ||
| 44 | #define GPIO_PF29 29 | ||
| 45 | #define GPIO_PF30 30 | ||
| 46 | #define GPIO_PF31 31 | ||
| 47 | #define GPIO_PF32 32 | ||
| 48 | #define GPIO_PF33 33 | ||
| 49 | #define GPIO_PF34 34 | ||
| 50 | #define GPIO_PF35 35 | ||
| 51 | #define GPIO_PF36 36 | ||
| 52 | #define GPIO_PF37 37 | ||
| 53 | #define GPIO_PF38 38 | ||
| 54 | #define GPIO_PF39 39 | ||
| 55 | #define GPIO_PF40 40 | ||
| 56 | #define GPIO_PF41 41 | ||
| 57 | #define GPIO_PF42 42 | ||
| 58 | #define GPIO_PF43 43 | ||
| 59 | #define GPIO_PF44 44 | ||
| 60 | #define GPIO_PF45 45 | ||
| 61 | #define GPIO_PF46 46 | ||
| 62 | #define GPIO_PF47 47 | ||
| 63 | |||
| 64 | #define PORT_FIO0 GPIO_0 | ||
| 65 | #define PORT_FIO1 GPIO_16 | ||
| 66 | #define PORT_FIO2 GPIO_32 | ||
| 67 | |||
| 68 | #endif /* _MACH_GPIO_H_ */ | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_init.h b/arch/blackfin/mach-bf561/include/mach/mem_init.h deleted file mode 100644 index e163260bca18..000000000000 --- a/arch/blackfin/mach-bf561/include/mach/mem_init.h +++ /dev/null | |||
| @@ -1,295 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf561/mem_init.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7) | ||
| 32 | #if (CONFIG_SCLK_HZ > 119402985) | ||
| 33 | #define SDRAM_tRP TRP_2 | ||
| 34 | #define SDRAM_tRP_num 2 | ||
| 35 | #define SDRAM_tRAS TRAS_7 | ||
| 36 | #define SDRAM_tRAS_num 7 | ||
| 37 | #define SDRAM_tRCD TRCD_2 | ||
| 38 | #define SDRAM_tWR TWR_2 | ||
| 39 | #endif | ||
| 40 | #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) | ||
| 41 | #define SDRAM_tRP TRP_2 | ||
| 42 | #define SDRAM_tRP_num 2 | ||
| 43 | #define SDRAM_tRAS TRAS_6 | ||
| 44 | #define SDRAM_tRAS_num 6 | ||
| 45 | #define SDRAM_tRCD TRCD_2 | ||
| 46 | #define SDRAM_tWR TWR_2 | ||
| 47 | #endif | ||
| 48 | #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) | ||
| 49 | #define SDRAM_tRP TRP_2 | ||
| 50 | #define SDRAM_tRP_num 2 | ||
| 51 | #define SDRAM_tRAS TRAS_5 | ||
| 52 | #define SDRAM_tRAS_num 5 | ||
| 53 | #define SDRAM_tRCD TRCD_2 | ||
| 54 | #define SDRAM_tWR TWR_2 | ||
| 55 | #endif | ||
| 56 | #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) | ||
| 57 | #define SDRAM_tRP TRP_2 | ||
| 58 | #define SDRAM_tRP_num 2 | ||
| 59 | #define SDRAM_tRAS TRAS_4 | ||
| 60 | #define SDRAM_tRAS_num 4 | ||
| 61 | #define SDRAM_tRCD TRCD_2 | ||
| 62 | #define SDRAM_tWR TWR_2 | ||
| 63 | #endif | ||
| 64 | #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) | ||
| 65 | #define SDRAM_tRP TRP_2 | ||
| 66 | #define SDRAM_tRP_num 2 | ||
| 67 | #define SDRAM_tRAS TRAS_3 | ||
| 68 | #define SDRAM_tRAS_num 3 | ||
| 69 | #define SDRAM_tRCD TRCD_2 | ||
| 70 | #define SDRAM_tWR TWR_2 | ||
| 71 | #endif | ||
| 72 | #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) | ||
| 73 | #define SDRAM_tRP TRP_1 | ||
| 74 | #define SDRAM_tRP_num 1 | ||
| 75 | #define SDRAM_tRAS TRAS_4 | ||
| 76 | #define SDRAM_tRAS_num 3 | ||
| 77 | #define SDRAM_tRCD TRCD_1 | ||
| 78 | #define SDRAM_tWR TWR_2 | ||
| 79 | #endif | ||
| 80 | #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) | ||
| 81 | #define SDRAM_tRP TRP_1 | ||
| 82 | #define SDRAM_tRP_num 1 | ||
| 83 | #define SDRAM_tRAS TRAS_3 | ||
| 84 | #define SDRAM_tRAS_num 3 | ||
| 85 | #define SDRAM_tRCD TRCD_1 | ||
| 86 | #define SDRAM_tWR TWR_2 | ||
| 87 | #endif | ||
| 88 | #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) | ||
| 89 | #define SDRAM_tRP TRP_1 | ||
| 90 | #define SDRAM_tRP_num 1 | ||
| 91 | #define SDRAM_tRAS TRAS_2 | ||
| 92 | #define SDRAM_tRAS_num 2 | ||
| 93 | #define SDRAM_tRCD TRCD_1 | ||
| 94 | #define SDRAM_tWR TWR_2 | ||
| 95 | #endif | ||
| 96 | #if (CONFIG_SCLK_HZ <= 29850746) | ||
| 97 | #define SDRAM_tRP TRP_1 | ||
| 98 | #define SDRAM_tRP_num 1 | ||
| 99 | #define SDRAM_tRAS TRAS_1 | ||
| 100 | #define SDRAM_tRAS_num 1 | ||
| 101 | #define SDRAM_tRCD TRCD_1 | ||
| 102 | #define SDRAM_tWR TWR_2 | ||
| 103 | #endif | ||
| 104 | #endif | ||
| 105 | |||
| 106 | #if (CONFIG_MEM_MT48LC16M16A2TG_75) | ||
| 107 | /*SDRAM INFORMATION: */ | ||
| 108 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 109 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 110 | #define SDRAM_CL CL_3 | ||
| 111 | #endif | ||
| 112 | |||
| 113 | #if (CONFIG_MEM_MT48LC64M4A2FB_7E) | ||
| 114 | /*SDRAM INFORMATION: */ | ||
| 115 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 116 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 117 | #define SDRAM_CL CL_3 | ||
| 118 | #endif | ||
| 119 | |||
| 120 | #if (CONFIG_MEM_MT48LC8M32B2B5_7) | ||
| 121 | /*SDRAM INFORMATION: */ | ||
| 122 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 123 | #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ | ||
| 124 | #define SDRAM_CL CL_3 | ||
| 125 | #endif | ||
| 126 | |||
| 127 | #if (CONFIG_MEM_GENERIC_BOARD) | ||
| 128 | /*SDRAM INFORMATION: Modify this for your board */ | ||
| 129 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 130 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 131 | #define SDRAM_CL CL_3 | ||
| 132 | #endif | ||
| 133 | |||
| 134 | /* Equation from section 17 (p17-46) of BF533 HRM */ | ||
| 135 | #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) | ||
| 136 | |||
| 137 | /* Enable SCLK Out */ | ||
| 138 | #define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) | ||
| 139 | |||
| 140 | #if defined CONFIG_CLKIN_HALF | ||
| 141 | #define CLKIN_HALF 1 | ||
| 142 | #else | ||
| 143 | #define CLKIN_HALF 0 | ||
| 144 | #endif | ||
| 145 | |||
| 146 | #if defined CONFIG_PLL_BYPASS | ||
| 147 | #define PLL_BYPASS 1 | ||
| 148 | #else | ||
| 149 | #define PLL_BYPASS 0 | ||
| 150 | #endif | ||
| 151 | |||
| 152 | /***************************************Currently Not Being Used *********************************/ | ||
| 153 | #define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 154 | #define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 155 | #define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) | ||
| 156 | #define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 157 | #define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 | ||
| 158 | |||
| 159 | #if (flash_EBIU_AMBCTL_TT > 3) | ||
| 160 | #define flash_EBIU_AMBCTL0_TT B0TT_4 | ||
| 161 | #endif | ||
| 162 | #if (flash_EBIU_AMBCTL_TT == 3) | ||
| 163 | #define flash_EBIU_AMBCTL0_TT B0TT_3 | ||
| 164 | #endif | ||
| 165 | #if (flash_EBIU_AMBCTL_TT == 2) | ||
| 166 | #define flash_EBIU_AMBCTL0_TT B0TT_2 | ||
| 167 | #endif | ||
| 168 | #if (flash_EBIU_AMBCTL_TT < 2) | ||
| 169 | #define flash_EBIU_AMBCTL0_TT B0TT_1 | ||
| 170 | #endif | ||
| 171 | |||
| 172 | #if (flash_EBIU_AMBCTL_ST > 3) | ||
| 173 | #define flash_EBIU_AMBCTL0_ST B0ST_4 | ||
| 174 | #endif | ||
| 175 | #if (flash_EBIU_AMBCTL_ST == 3) | ||
| 176 | #define flash_EBIU_AMBCTL0_ST B0ST_3 | ||
| 177 | #endif | ||
| 178 | #if (flash_EBIU_AMBCTL_ST == 2) | ||
| 179 | #define flash_EBIU_AMBCTL0_ST B0ST_2 | ||
| 180 | #endif | ||
| 181 | #if (flash_EBIU_AMBCTL_ST < 2) | ||
| 182 | #define flash_EBIU_AMBCTL0_ST B0ST_1 | ||
| 183 | #endif | ||
| 184 | |||
| 185 | #if (flash_EBIU_AMBCTL_HT > 2) | ||
| 186 | #define flash_EBIU_AMBCTL0_HT B0HT_3 | ||
| 187 | #endif | ||
| 188 | #if (flash_EBIU_AMBCTL_HT == 2) | ||
| 189 | #define flash_EBIU_AMBCTL0_HT B0HT_2 | ||
| 190 | #endif | ||
| 191 | #if (flash_EBIU_AMBCTL_HT == 1) | ||
| 192 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 193 | #endif | ||
| 194 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) | ||
| 195 | #define flash_EBIU_AMBCTL0_HT B0HT_0 | ||
| 196 | #endif | ||
| 197 | #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) | ||
| 198 | #define flash_EBIU_AMBCTL0_HT B0HT_1 | ||
| 199 | #endif | ||
| 200 | |||
| 201 | #if (flash_EBIU_AMBCTL_WAT > 14) | ||
| 202 | #define flash_EBIU_AMBCTL0_WAT B0WAT_15 | ||
| 203 | #endif | ||
| 204 | #if (flash_EBIU_AMBCTL_WAT == 14) | ||
| 205 | #define flash_EBIU_AMBCTL0_WAT B0WAT_14 | ||
| 206 | #endif | ||
| 207 | #if (flash_EBIU_AMBCTL_WAT == 13) | ||
| 208 | #define flash_EBIU_AMBCTL0_WAT B0WAT_13 | ||
| 209 | #endif | ||
| 210 | #if (flash_EBIU_AMBCTL_WAT == 12) | ||
| 211 | #define flash_EBIU_AMBCTL0_WAT B0WAT_12 | ||
| 212 | #endif | ||
| 213 | #if (flash_EBIU_AMBCTL_WAT == 11) | ||
| 214 | #define flash_EBIU_AMBCTL0_WAT B0WAT_11 | ||
| 215 | #endif | ||
| 216 | #if (flash_EBIU_AMBCTL_WAT == 10) | ||
| 217 | #define flash_EBIU_AMBCTL0_WAT B0WAT_10 | ||
| 218 | #endif | ||
| 219 | #if (flash_EBIU_AMBCTL_WAT == 9) | ||
| 220 | #define flash_EBIU_AMBCTL0_WAT B0WAT_9 | ||
| 221 | #endif | ||
| 222 | #if (flash_EBIU_AMBCTL_WAT == 8) | ||
| 223 | #define flash_EBIU_AMBCTL0_WAT B0WAT_8 | ||
| 224 | #endif | ||
| 225 | #if (flash_EBIU_AMBCTL_WAT == 7) | ||
| 226 | #define flash_EBIU_AMBCTL0_WAT B0WAT_7 | ||
| 227 | #endif | ||
| 228 | #if (flash_EBIU_AMBCTL_WAT == 6) | ||
| 229 | #define flash_EBIU_AMBCTL0_WAT B0WAT_6 | ||
| 230 | #endif | ||
| 231 | #if (flash_EBIU_AMBCTL_WAT == 5) | ||
| 232 | #define flash_EBIU_AMBCTL0_WAT B0WAT_5 | ||
| 233 | #endif | ||
| 234 | #if (flash_EBIU_AMBCTL_WAT == 4) | ||
| 235 | #define flash_EBIU_AMBCTL0_WAT B0WAT_4 | ||
| 236 | #endif | ||
| 237 | #if (flash_EBIU_AMBCTL_WAT == 3) | ||
| 238 | #define flash_EBIU_AMBCTL0_WAT B0WAT_3 | ||
| 239 | #endif | ||
| 240 | #if (flash_EBIU_AMBCTL_WAT == 2) | ||
| 241 | #define flash_EBIU_AMBCTL0_WAT B0WAT_2 | ||
| 242 | #endif | ||
| 243 | #if (flash_EBIU_AMBCTL_WAT == 1) | ||
| 244 | #define flash_EBIU_AMBCTL0_WAT B0WAT_1 | ||
| 245 | #endif | ||
| 246 | |||
| 247 | #if (flash_EBIU_AMBCTL_RAT > 14) | ||
| 248 | #define flash_EBIU_AMBCTL0_RAT B0RAT_15 | ||
| 249 | #endif | ||
| 250 | #if (flash_EBIU_AMBCTL_RAT == 14) | ||
| 251 | #define flash_EBIU_AMBCTL0_RAT B0RAT_14 | ||
| 252 | #endif | ||
| 253 | #if (flash_EBIU_AMBCTL_RAT == 13) | ||
| 254 | #define flash_EBIU_AMBCTL0_RAT B0RAT_13 | ||
| 255 | #endif | ||
| 256 | #if (flash_EBIU_AMBCTL_RAT == 12) | ||
| 257 | #define flash_EBIU_AMBCTL0_RAT B0RAT_12 | ||
| 258 | #endif | ||
| 259 | #if (flash_EBIU_AMBCTL_RAT == 11) | ||
| 260 | #define flash_EBIU_AMBCTL0_RAT B0RAT_11 | ||
| 261 | #endif | ||
| 262 | #if (flash_EBIU_AMBCTL_RAT == 10) | ||
| 263 | #define flash_EBIU_AMBCTL0_RAT B0RAT_10 | ||
| 264 | #endif | ||
| 265 | #if (flash_EBIU_AMBCTL_RAT == 9) | ||
| 266 | #define flash_EBIU_AMBCTL0_RAT B0RAT_9 | ||
| 267 | #endif | ||
| 268 | #if (flash_EBIU_AMBCTL_RAT == 8) | ||
| 269 | #define flash_EBIU_AMBCTL0_RAT B0RAT_8 | ||
| 270 | #endif | ||
| 271 | #if (flash_EBIU_AMBCTL_RAT == 7) | ||
| 272 | #define flash_EBIU_AMBCTL0_RAT B0RAT_7 | ||
| 273 | #endif | ||
| 274 | #if (flash_EBIU_AMBCTL_RAT == 6) | ||
| 275 | #define flash_EBIU_AMBCTL0_RAT B0RAT_6 | ||
| 276 | #endif | ||
| 277 | #if (flash_EBIU_AMBCTL_RAT == 5) | ||
| 278 | #define flash_EBIU_AMBCTL0_RAT B0RAT_5 | ||
| 279 | #endif | ||
| 280 | #if (flash_EBIU_AMBCTL_RAT == 4) | ||
| 281 | #define flash_EBIU_AMBCTL0_RAT B0RAT_4 | ||
| 282 | #endif | ||
| 283 | #if (flash_EBIU_AMBCTL_RAT == 3) | ||
| 284 | #define flash_EBIU_AMBCTL0_RAT B0RAT_3 | ||
| 285 | #endif | ||
| 286 | #if (flash_EBIU_AMBCTL_RAT == 2) | ||
| 287 | #define flash_EBIU_AMBCTL0_RAT B0RAT_2 | ||
| 288 | #endif | ||
| 289 | #if (flash_EBIU_AMBCTL_RAT == 1) | ||
| 290 | #define flash_EBIU_AMBCTL0_RAT B0RAT_1 | ||
| 291 | #endif | ||
| 292 | |||
| 293 | #define flash_EBIU_AMBCTL0 \ | ||
| 294 | (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ | ||
| 295 | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index f1d4c0637bd2..419dffdc96eb 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h | |||
| @@ -85,4 +85,84 @@ | |||
| 85 | #define L1_SCRATCH_START COREA_L1_SCRATCH_START | 85 | #define L1_SCRATCH_START COREA_L1_SCRATCH_START |
| 86 | #define L1_SCRATCH_LENGTH 0x1000 | 86 | #define L1_SCRATCH_LENGTH 0x1000 |
| 87 | 87 | ||
| 88 | #ifdef __ASSEMBLY__ | ||
| 89 | |||
| 90 | /* | ||
| 91 | * The following macros both return the address of the PDA for the | ||
| 92 | * current core. | ||
| 93 | * | ||
| 94 | * In its first safe (and hairy) form, the macro neither clobbers any | ||
| 95 | * register aside of the output Preg, nor uses the stack, since it | ||
| 96 | * could be called with an invalid stack pointer, or the current stack | ||
| 97 | * space being uncovered by any CPLB (e.g. early exception handling). | ||
| 98 | * | ||
| 99 | * The constraints on the second form are a bit relaxed, and the code | ||
| 100 | * is allowed to use the specified Dreg for determining the PDA | ||
| 101 | * address to be returned into Preg. | ||
| 102 | */ | ||
| 103 | #ifdef CONFIG_SMP | ||
| 104 | #define GET_PDA_SAFE(preg) \ | ||
| 105 | preg.l = lo(DSPID); \ | ||
| 106 | preg.h = hi(DSPID); \ | ||
| 107 | preg = [preg]; \ | ||
| 108 | preg = preg << 2; \ | ||
| 109 | preg = preg << 2; \ | ||
| 110 | preg = preg << 2; \ | ||
| 111 | preg = preg << 2; \ | ||
| 112 | preg = preg << 2; \ | ||
| 113 | preg = preg << 2; \ | ||
| 114 | preg = preg << 2; \ | ||
| 115 | preg = preg << 2; \ | ||
| 116 | preg = preg << 2; \ | ||
| 117 | preg = preg << 2; \ | ||
| 118 | preg = preg << 2; \ | ||
| 119 | preg = preg << 2; \ | ||
| 120 | if cc jump 2f; \ | ||
| 121 | cc = preg == 0x0; \ | ||
| 122 | preg.l = _cpu_pda; \ | ||
| 123 | preg.h = _cpu_pda; \ | ||
| 124 | if !cc jump 3f; \ | ||
| 125 | 1: \ | ||
| 126 | /* preg = 0x0; */ \ | ||
| 127 | cc = !cc; /* restore cc to 0 */ \ | ||
| 128 | jump 4f; \ | ||
| 129 | 2: \ | ||
| 130 | cc = preg == 0x0; \ | ||
| 131 | preg.l = _cpu_pda; \ | ||
| 132 | preg.h = _cpu_pda; \ | ||
| 133 | if cc jump 4f; \ | ||
| 134 | /* preg = 0x1000000; */ \ | ||
| 135 | cc = !cc; /* restore cc to 1 */ \ | ||
| 136 | 3: \ | ||
| 137 | preg = [preg]; \ | ||
| 138 | 4: | ||
| 139 | |||
| 140 | #define GET_PDA(preg, dreg) \ | ||
| 141 | preg.l = lo(DSPID); \ | ||
| 142 | preg.h = hi(DSPID); \ | ||
| 143 | dreg = [preg]; \ | ||
| 144 | preg.l = _cpu_pda; \ | ||
| 145 | preg.h = _cpu_pda; \ | ||
| 146 | cc = bittst(dreg, 0); \ | ||
| 147 | if !cc jump 1f; \ | ||
| 148 | preg = [preg]; \ | ||
| 149 | 1: \ | ||
| 150 | |||
| 151 | #define GET_CPUID(preg, dreg) \ | ||
| 152 | preg.l = lo(DSPID); \ | ||
| 153 | preg.h = hi(DSPID); \ | ||
| 154 | dreg = [preg]; \ | ||
| 155 | dreg = ROT dreg BY -1; \ | ||
| 156 | dreg = CC; | ||
| 157 | |||
| 158 | #else | ||
| 159 | #define GET_PDA_SAFE(preg) \ | ||
| 160 | preg.l = _cpu_pda; \ | ||
| 161 | preg.h = _cpu_pda; | ||
| 162 | |||
| 163 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 164 | #endif /* CONFIG_SMP */ | ||
| 165 | |||
| 166 | #endif /* __ASSEMBLY__ */ | ||
| 167 | |||
| 88 | #endif /* _MEM_MAP_533_H_ */ | 168 | #endif /* _MEM_MAP_533_H_ */ |
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h new file mode 100644 index 000000000000..f9e65ebe81b2 --- /dev/null +++ b/arch/blackfin/mach-bf561/include/mach/smp.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | #ifndef _MACH_BF561_SMP | ||
| 2 | #define _MACH_BF561_SMP | ||
| 3 | |||
| 4 | struct task_struct; | ||
| 5 | |||
| 6 | void platform_init_cpus(void); | ||
| 7 | |||
| 8 | void platform_prepare_cpus(unsigned int max_cpus); | ||
| 9 | |||
| 10 | int platform_boot_secondary(unsigned int cpu, struct task_struct *idle); | ||
| 11 | |||
| 12 | void platform_secondary_init(unsigned int cpu); | ||
| 13 | |||
| 14 | void platform_request_ipi(int (*handler)(int, void *)); | ||
| 15 | |||
| 16 | void platform_send_ipi(cpumask_t callmap); | ||
| 17 | |||
| 18 | void platform_send_ipi_cpu(unsigned int cpu); | ||
| 19 | |||
| 20 | void platform_clear_ipi(unsigned int cpu); | ||
| 21 | |||
| 22 | #endif /* !_MACH_BF561_SMP */ | ||
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S new file mode 100644 index 000000000000..35280f06b7b6 --- /dev/null +++ b/arch/blackfin/mach-bf561/secondary.S | |||
| @@ -0,0 +1,215 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf561/secondary.S | ||
| 3 | * Based on: arch/blackfin/mach-bf561/head.S | ||
| 4 | * Author: Philippe Gerum <rpm@xenomai.org> | ||
| 5 | * | ||
| 6 | * Copyright 2007 Analog Devices Inc. | ||
| 7 | * | ||
| 8 | * Description: BF561 coreB bootstrap file | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, see the file COPYING, or write | ||
| 22 | * to the Free Software Foundation, Inc., | ||
| 23 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 24 | */ | ||
| 25 | |||
| 26 | #include <linux/linkage.h> | ||
| 27 | #include <linux/init.h> | ||
| 28 | #include <asm/blackfin.h> | ||
| 29 | #include <asm/asm-offsets.h> | ||
| 30 | |||
| 31 | __INIT | ||
| 32 | |||
| 33 | /* Lay the initial stack into the L1 scratch area of Core B */ | ||
| 34 | #define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) | ||
| 35 | |||
| 36 | ENTRY(_coreb_trampoline_start) | ||
| 37 | /* Set the SYSCFG register */ | ||
| 38 | R0 = 0x36; | ||
| 39 | SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/ | ||
| 40 | R0 = 0; | ||
| 41 | |||
| 42 | /*Clear Out All the data and pointer Registers*/ | ||
| 43 | R1 = R0; | ||
| 44 | R2 = R0; | ||
| 45 | R3 = R0; | ||
| 46 | R4 = R0; | ||
| 47 | R5 = R0; | ||
| 48 | R6 = R0; | ||
| 49 | R7 = R0; | ||
| 50 | |||
| 51 | P0 = R0; | ||
| 52 | P1 = R0; | ||
| 53 | P2 = R0; | ||
| 54 | P3 = R0; | ||
| 55 | P4 = R0; | ||
| 56 | P5 = R0; | ||
| 57 | |||
| 58 | LC0 = r0; | ||
| 59 | LC1 = r0; | ||
| 60 | L0 = r0; | ||
| 61 | L1 = r0; | ||
| 62 | L2 = r0; | ||
| 63 | L3 = r0; | ||
| 64 | |||
| 65 | /* Clear Out All the DAG Registers*/ | ||
| 66 | B0 = r0; | ||
| 67 | B1 = r0; | ||
| 68 | B2 = r0; | ||
| 69 | B3 = r0; | ||
| 70 | |||
| 71 | I0 = r0; | ||
| 72 | I1 = r0; | ||
| 73 | I2 = r0; | ||
| 74 | I3 = r0; | ||
| 75 | |||
| 76 | M0 = r0; | ||
| 77 | M1 = r0; | ||
| 78 | M2 = r0; | ||
| 79 | M3 = r0; | ||
| 80 | |||
| 81 | /* Turn off the icache */ | ||
| 82 | p0.l = LO(IMEM_CONTROL); | ||
| 83 | p0.h = HI(IMEM_CONTROL); | ||
| 84 | R1 = [p0]; | ||
| 85 | R0 = ~ENICPLB; | ||
| 86 | R0 = R0 & R1; | ||
| 87 | |||
| 88 | /* Anomaly 05000125 */ | ||
| 89 | #ifdef ANOMALY_05000125 | ||
| 90 | CLI R2; | ||
| 91 | SSYNC; | ||
| 92 | #endif | ||
| 93 | [p0] = R0; | ||
| 94 | SSYNC; | ||
| 95 | #ifdef ANOMALY_05000125 | ||
| 96 | STI R2; | ||
| 97 | #endif | ||
| 98 | |||
| 99 | /* Turn off the dcache */ | ||
| 100 | p0.l = LO(DMEM_CONTROL); | ||
| 101 | p0.h = HI(DMEM_CONTROL); | ||
| 102 | R1 = [p0]; | ||
| 103 | R0 = ~ENDCPLB; | ||
| 104 | R0 = R0 & R1; | ||
| 105 | |||
| 106 | /* Anomaly 05000125 */ | ||
| 107 | #ifdef ANOMALY_05000125 | ||
| 108 | CLI R2; | ||
| 109 | SSYNC; | ||
| 110 | #endif | ||
| 111 | [p0] = R0; | ||
| 112 | SSYNC; | ||
| 113 | #ifdef ANOMALY_05000125 | ||
| 114 | STI R2; | ||
| 115 | #endif | ||
| 116 | |||
| 117 | /* in case of double faults, save a few things */ | ||
| 118 | p0.l = _init_retx_coreb; | ||
| 119 | p0.h = _init_retx_coreb; | ||
| 120 | R0 = RETX; | ||
| 121 | [P0] = R0; | ||
| 122 | |||
| 123 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | ||
| 124 | /* Only save these if we are storing them, | ||
| 125 | * This happens here, since L1 gets clobbered | ||
| 126 | * below | ||
| 127 | */ | ||
| 128 | GET_PDA(p0, r0); | ||
| 129 | r7 = [p0 + PDA_RETX]; | ||
| 130 | p1.l = _init_saved_retx_coreb; | ||
| 131 | p1.h = _init_saved_retx_coreb; | ||
| 132 | [p1] = r7; | ||
| 133 | |||
| 134 | r7 = [p0 + PDA_DCPLB]; | ||
| 135 | p1.l = _init_saved_dcplb_fault_addr_coreb; | ||
| 136 | p1.h = _init_saved_dcplb_fault_addr_coreb; | ||
| 137 | [p1] = r7; | ||
| 138 | |||
| 139 | r7 = [p0 + PDA_ICPLB]; | ||
| 140 | p1.l = _init_saved_icplb_fault_addr_coreb; | ||
| 141 | p1.h = _init_saved_icplb_fault_addr_coreb; | ||
| 142 | [p1] = r7; | ||
| 143 | |||
| 144 | r7 = [p0 + PDA_SEQSTAT]; | ||
| 145 | p1.l = _init_saved_seqstat_coreb; | ||
| 146 | p1.h = _init_saved_seqstat_coreb; | ||
| 147 | [p1] = r7; | ||
| 148 | #endif | ||
| 149 | |||
| 150 | /* Initialize stack pointer */ | ||
| 151 | sp.l = lo(INITIAL_STACK); | ||
| 152 | sp.h = hi(INITIAL_STACK); | ||
| 153 | fp = sp; | ||
| 154 | usp = sp; | ||
| 155 | |||
| 156 | /* This section keeps the processor in supervisor mode | ||
| 157 | * during core B startup. Branches to the idle task. | ||
| 158 | */ | ||
| 159 | |||
| 160 | /* EVT15 = _real_start */ | ||
| 161 | |||
| 162 | p0.l = lo(EVT15); | ||
| 163 | p0.h = hi(EVT15); | ||
| 164 | p1.l = _coreb_start; | ||
| 165 | p1.h = _coreb_start; | ||
| 166 | [p0] = p1; | ||
| 167 | csync; | ||
| 168 | |||
| 169 | p0.l = lo(IMASK); | ||
| 170 | p0.h = hi(IMASK); | ||
| 171 | p1.l = IMASK_IVG15; | ||
| 172 | p1.h = 0x0; | ||
| 173 | [p0] = p1; | ||
| 174 | csync; | ||
| 175 | |||
| 176 | raise 15; | ||
| 177 | p0.l = .LWAIT_HERE; | ||
| 178 | p0.h = .LWAIT_HERE; | ||
| 179 | reti = p0; | ||
| 180 | #if defined(ANOMALY_05000281) | ||
| 181 | nop; nop; nop; | ||
| 182 | #endif | ||
| 183 | rti; | ||
| 184 | |||
| 185 | .LWAIT_HERE: | ||
| 186 | jump .LWAIT_HERE; | ||
| 187 | ENDPROC(_coreb_trampoline_start) | ||
| 188 | ENTRY(_coreb_trampoline_end) | ||
| 189 | |||
| 190 | ENTRY(_coreb_start) | ||
| 191 | [--sp] = reti; | ||
| 192 | |||
| 193 | p0.l = lo(WDOGB_CTL); | ||
| 194 | p0.h = hi(WDOGB_CTL); | ||
| 195 | r0 = 0xAD6(z); | ||
| 196 | w[p0] = r0; /* Clear the watchdog. */ | ||
| 197 | ssync; | ||
| 198 | |||
| 199 | /* | ||
| 200 | * switch to IDLE stack. | ||
| 201 | */ | ||
| 202 | p0.l = _secondary_stack; | ||
| 203 | p0.h = _secondary_stack; | ||
| 204 | sp = [p0]; | ||
| 205 | usp = sp; | ||
| 206 | fp = sp; | ||
| 207 | sp += -12; | ||
| 208 | call _init_pda | ||
| 209 | sp += 12; | ||
| 210 | call _secondary_start_kernel; | ||
| 211 | .L_exit: | ||
| 212 | jump.s .L_exit; | ||
| 213 | ENDPROC(_coreb_start) | ||
| 214 | |||
| 215 | __FINIT | ||
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c new file mode 100644 index 000000000000..9b27e698c0b2 --- /dev/null +++ b/arch/blackfin/mach-bf561/smp.c | |||
| @@ -0,0 +1,167 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf561/smp.c | ||
| 3 | * Author: Philippe Gerum <rpm@xenomai.org> | ||
| 4 | * | ||
| 5 | * Copyright 2007 Analog Devices Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, see the file COPYING, or write | ||
| 19 | * to the Free Software Foundation, Inc., | ||
| 20 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/sched.h> | ||
| 26 | #include <linux/delay.h> | ||
| 27 | #include <asm/smp.h> | ||
| 28 | #include <asm/dma.h> | ||
| 29 | |||
| 30 | static DEFINE_SPINLOCK(boot_lock); | ||
| 31 | |||
| 32 | static cpumask_t cpu_callin_map; | ||
| 33 | |||
| 34 | /* | ||
| 35 | * platform_init_cpus() - Tell the world about how many cores we | ||
| 36 | * have. This is called while setting up the architecture support | ||
| 37 | * (setup_arch()), so don't be too demanding here with respect to | ||
| 38 | * available kernel services. | ||
| 39 | */ | ||
| 40 | |||
| 41 | void __init platform_init_cpus(void) | ||
| 42 | { | ||
| 43 | cpu_set(0, cpu_possible_map); /* CoreA */ | ||
| 44 | cpu_set(1, cpu_possible_map); /* CoreB */ | ||
| 45 | } | ||
| 46 | |||
| 47 | void __init platform_prepare_cpus(unsigned int max_cpus) | ||
| 48 | { | ||
| 49 | int len; | ||
| 50 | |||
| 51 | len = &coreb_trampoline_end - &coreb_trampoline_start + 1; | ||
| 52 | BUG_ON(len > L1_CODE_LENGTH); | ||
| 53 | |||
| 54 | dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len); | ||
| 55 | |||
| 56 | /* Both cores ought to be present on a bf561! */ | ||
| 57 | cpu_set(0, cpu_present_map); /* CoreA */ | ||
| 58 | cpu_set(1, cpu_present_map); /* CoreB */ | ||
| 59 | |||
| 60 | printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START); | ||
| 61 | } | ||
| 62 | |||
| 63 | int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ | ||
| 64 | { | ||
| 65 | return -EINVAL; | ||
| 66 | } | ||
| 67 | |||
| 68 | void __cpuinit platform_secondary_init(unsigned int cpu) | ||
| 69 | { | ||
| 70 | local_irq_disable(); | ||
| 71 | |||
| 72 | /* Clone setup for peripheral interrupt sources from CoreA. */ | ||
| 73 | bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); | ||
| 74 | bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); | ||
| 75 | SSYNC(); | ||
| 76 | |||
| 77 | /* Clone setup for IARs from CoreA. */ | ||
| 78 | bfin_write_SICB_IAR0(bfin_read_SICA_IAR0()); | ||
| 79 | bfin_write_SICB_IAR1(bfin_read_SICA_IAR1()); | ||
| 80 | bfin_write_SICB_IAR2(bfin_read_SICA_IAR2()); | ||
| 81 | bfin_write_SICB_IAR3(bfin_read_SICA_IAR3()); | ||
| 82 | bfin_write_SICB_IAR4(bfin_read_SICA_IAR4()); | ||
| 83 | bfin_write_SICB_IAR5(bfin_read_SICA_IAR5()); | ||
| 84 | bfin_write_SICB_IAR6(bfin_read_SICA_IAR6()); | ||
| 85 | bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); | ||
| 86 | SSYNC(); | ||
| 87 | |||
| 88 | local_irq_enable(); | ||
| 89 | |||
| 90 | /* Calibrate loops per jiffy value. */ | ||
| 91 | calibrate_delay(); | ||
| 92 | |||
| 93 | /* Store CPU-private information to the cpu_data array. */ | ||
| 94 | bfin_setup_cpudata(cpu); | ||
| 95 | |||
| 96 | /* We are done with local CPU inits, unblock the boot CPU. */ | ||
| 97 | cpu_set(cpu, cpu_callin_map); | ||
| 98 | spin_lock(&boot_lock); | ||
| 99 | spin_unlock(&boot_lock); | ||
| 100 | } | ||
| 101 | |||
| 102 | int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
| 103 | { | ||
| 104 | unsigned long timeout; | ||
| 105 | |||
| 106 | /* CoreB already running?! */ | ||
| 107 | BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0); | ||
| 108 | |||
| 109 | printk(KERN_INFO "Booting Core B.\n"); | ||
| 110 | |||
| 111 | spin_lock(&boot_lock); | ||
| 112 | |||
| 113 | /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ | ||
| 114 | SSYNC(); | ||
| 115 | bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT); | ||
| 116 | SSYNC(); | ||
| 117 | |||
| 118 | timeout = jiffies + 1 * HZ; | ||
| 119 | while (time_before(jiffies, timeout)) { | ||
| 120 | if (cpu_isset(cpu, cpu_callin_map)) | ||
| 121 | break; | ||
| 122 | udelay(100); | ||
| 123 | barrier(); | ||
| 124 | } | ||
| 125 | |||
| 126 | spin_unlock(&boot_lock); | ||
| 127 | |||
| 128 | return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS; | ||
| 129 | } | ||
| 130 | |||
| 131 | void __init platform_request_ipi(irq_handler_t handler) | ||
| 132 | { | ||
| 133 | int ret; | ||
| 134 | |||
| 135 | ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, | ||
| 136 | "SMP interrupt", handler); | ||
| 137 | if (ret) | ||
| 138 | panic("Cannot request supplemental interrupt 0 for IPI service\n"); | ||
| 139 | } | ||
| 140 | |||
| 141 | void platform_send_ipi(cpumask_t callmap) | ||
| 142 | { | ||
| 143 | unsigned int cpu; | ||
| 144 | |||
| 145 | for_each_cpu_mask(cpu, callmap) { | ||
| 146 | BUG_ON(cpu >= 2); | ||
| 147 | SSYNC(); | ||
| 148 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); | ||
| 149 | SSYNC(); | ||
| 150 | } | ||
| 151 | } | ||
| 152 | |||
| 153 | void platform_send_ipi_cpu(unsigned int cpu) | ||
| 154 | { | ||
| 155 | BUG_ON(cpu >= 2); | ||
| 156 | SSYNC(); | ||
| 157 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); | ||
| 158 | SSYNC(); | ||
| 159 | } | ||
| 160 | |||
| 161 | void platform_clear_ipi(unsigned int cpu) | ||
| 162 | { | ||
| 163 | BUG_ON(cpu >= 2); | ||
| 164 | SSYNC(); | ||
| 165 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu))); | ||
| 166 | SSYNC(); | ||
| 167 | } | ||
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index e6ed57c56d4b..1f3228ed713f 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile | |||
| @@ -3,10 +3,12 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y := \ | 5 | obj-y := \ |
| 6 | cache.o entry.o head.o \ | 6 | cache.o cache-c.o entry.o head.o \ |
| 7 | interrupt.o irqpanic.o arch_checks.o ints-priority.o | 7 | interrupt.o irqpanic.o arch_checks.o ints-priority.o |
| 8 | 8 | ||
| 9 | obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o | 9 | obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o |
| 10 | obj-$(CONFIG_PM) += pm.o dpmc_modes.o | 10 | obj-$(CONFIG_PM) += pm.o dpmc_modes.o |
| 11 | obj-$(CONFIG_CPU_FREQ) += cpufreq.o | 11 | obj-$(CONFIG_CPU_FREQ) += cpufreq.o |
| 12 | obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o | 12 | obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o |
| 13 | obj-$(CONFIG_SMP) += smp.o | ||
| 14 | obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o | ||
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c new file mode 100644 index 000000000000..e6ab1f815123 --- /dev/null +++ b/arch/blackfin/mach-common/cache-c.c | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * Blackfin cache control code (simpler control-style functions) | ||
| 3 | * | ||
| 4 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Enter bugs at http://blackfin.uclinux.org/ | ||
| 7 | * | ||
| 8 | * Licensed under the GPL-2 or later. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/blackfin.h> | ||
| 12 | |||
| 13 | /* Invalidate the Entire Data cache by | ||
| 14 | * clearing DMC[1:0] bits | ||
| 15 | */ | ||
| 16 | void blackfin_invalidate_entire_dcache(void) | ||
| 17 | { | ||
| 18 | u32 dmem = bfin_read_DMEM_CONTROL(); | ||
| 19 | SSYNC(); | ||
| 20 | bfin_write_DMEM_CONTROL(dmem & ~0xc); | ||
| 21 | SSYNC(); | ||
| 22 | bfin_write_DMEM_CONTROL(dmem); | ||
| 23 | SSYNC(); | ||
| 24 | } | ||
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index a028e9450419..3c98dacbf289 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S | |||
| @@ -49,13 +49,17 @@ | |||
| 49 | .ifnb \optflushins | 49 | .ifnb \optflushins |
| 50 | \optflushins [P0]; | 50 | \optflushins [P0]; |
| 51 | .endif | 51 | .endif |
| 52 | #if ANOMALY_05000443 | ||
| 52 | .ifb \optnopins | 53 | .ifb \optnopins |
| 53 | 2: | 54 | 2: |
| 54 | .endif | 55 | .endif |
| 55 | \flushins [P0++]; | 56 | \flushins [P0++]; |
| 56 | .ifnb \optnopins | 57 | .ifnb \optnopins |
| 57 | 2: \optnopins; | 58 | 2: \optnopins; |
| 58 | .endif | 59 | .endif |
| 60 | #else | ||
| 61 | 2: \flushins [P0++]; | ||
| 62 | #endif | ||
| 59 | 63 | ||
| 60 | RTS; | 64 | RTS; |
| 61 | .endm | 65 | .endm |
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c new file mode 100644 index 000000000000..5d182abefc7b --- /dev/null +++ b/arch/blackfin/mach-common/clocks-init.c | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory | ||
| 3 | * | ||
| 4 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * Licensed under the GPL-2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/linkage.h> | ||
| 10 | #include <linux/init.h> | ||
| 11 | #include <asm/blackfin.h> | ||
| 12 | |||
| 13 | #include <asm/dma.h> | ||
| 14 | #include <asm/clocks.h> | ||
| 15 | #include <asm/mem_init.h> | ||
| 16 | |||
| 17 | #define PLL_CTL_VAL \ | ||
| 18 | (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ | ||
| 19 | (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) | ||
| 20 | |||
| 21 | __attribute__((l1_text)) | ||
| 22 | static void do_sync(void) | ||
| 23 | { | ||
| 24 | __builtin_bfin_ssync(); | ||
| 25 | } | ||
| 26 | |||
| 27 | __attribute__((l1_text)) | ||
| 28 | void init_clocks(void) | ||
| 29 | { | ||
| 30 | /* Kill any active DMAs as they may trigger external memory accesses | ||
| 31 | * in the middle of reprogramming things, and that'll screw us up. | ||
| 32 | * For example, any automatic DMAs left by U-Boot for splash screens. | ||
| 33 | */ | ||
| 34 | size_t i; | ||
| 35 | for (i = 0; i < MAX_DMA_CHANNELS; ++i) { | ||
| 36 | struct dma_register *dma = dma_io_base_addr[i]; | ||
| 37 | dma->cfg = 0; | ||
| 38 | } | ||
| 39 | |||
| 40 | do_sync(); | ||
| 41 | |||
| 42 | #ifdef SIC_IWR0 | ||
| 43 | bfin_write_SIC_IWR0(IWR_ENABLE(0)); | ||
| 44 | # ifdef SIC_IWR1 | ||
| 45 | /* BF52x system reset does not properly reset SIC_IWR1 which | ||
| 46 | * will screw up the bootrom as it relies on MDMA0/1 waking it | ||
| 47 | * up from IDLE instructions. See this report for more info: | ||
| 48 | * http://blackfin.uclinux.org/gf/tracker/4323 | ||
| 49 | */ | ||
| 50 | if (ANOMALY_05000435) | ||
| 51 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | ||
| 52 | else | ||
| 53 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | ||
| 54 | # endif | ||
| 55 | # ifdef SIC_IWR2 | ||
| 56 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); | ||
| 57 | # endif | ||
| 58 | #else | ||
| 59 | bfin_write_SIC_IWR(IWR_ENABLE(0)); | ||
| 60 | #endif | ||
| 61 | do_sync(); | ||
| 62 | #ifdef EBIU_SDGCTL | ||
| 63 | bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); | ||
| 64 | do_sync(); | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifdef CLKBUFOE | ||
| 68 | bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE); | ||
| 69 | do_sync(); | ||
| 70 | __asm__ __volatile__("IDLE;"); | ||
| 71 | #endif | ||
| 72 | bfin_write_PLL_LOCKCNT(0x300); | ||
| 73 | do_sync(); | ||
| 74 | bfin_write16(PLL_CTL, PLL_CTL_VAL); | ||
| 75 | __asm__ __volatile__("IDLE;"); | ||
| 76 | bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); | ||
| 77 | #ifdef EBIU_SDGCTL | ||
| 78 | bfin_write_EBIU_SDRRC(mem_SDRRC); | ||
| 79 | bfin_write_EBIU_SDGCTL(mem_SDGCTL); | ||
| 80 | #else | ||
| 81 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); | ||
| 82 | do_sync(); | ||
| 83 | bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1); | ||
| 84 | bfin_write_EBIU_DDRCTL0(mem_DDRCTL0); | ||
| 85 | bfin_write_EBIU_DDRCTL1(mem_DDRCTL1); | ||
| 86 | bfin_write_EBIU_DDRCTL2(mem_DDRCTL2); | ||
| 87 | #ifdef CONFIG_MEM_EBIU_DDRQUE | ||
| 88 | bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); | ||
| 89 | #endif | ||
| 90 | #endif | ||
| 91 | do_sync(); | ||
| 92 | bfin_read16(0); | ||
| 93 | } | ||
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index dda5443b37ed..72e16605ca09 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c | |||
| @@ -104,7 +104,7 @@ static int bfin_target(struct cpufreq_policy *policy, | |||
| 104 | cclk_hz, target_freq, freqs.old); | 104 | cclk_hz, target_freq, freqs.old); |
| 105 | 105 | ||
| 106 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | 106 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
| 107 | local_irq_save(flags); | 107 | local_irq_save_hw(flags); |
| 108 | plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel; | 108 | plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel; |
| 109 | tscale = dpm_state_table[index].tscale; | 109 | tscale = dpm_state_table[index].tscale; |
| 110 | bfin_write_PLL_DIV(plldiv); | 110 | bfin_write_PLL_DIV(plldiv); |
| @@ -112,10 +112,10 @@ static int bfin_target(struct cpufreq_policy *policy, | |||
| 112 | bfin_write_TSCALE(tscale); | 112 | bfin_write_TSCALE(tscale); |
| 113 | cycles = get_cycles(); | 113 | cycles = get_cycles(); |
| 114 | SSYNC(); | 114 | SSYNC(); |
| 115 | cycles += 10; /* ~10 cycles we loose after get_cycles() */ | 115 | cycles += 10; /* ~10 cycles we lose after get_cycles() */ |
| 116 | __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index); | 116 | __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index); |
| 117 | __bfin_cycles_mod = index; | 117 | __bfin_cycles_mod = index; |
| 118 | local_irq_restore(flags); | 118 | local_irq_restore_hw(flags); |
| 119 | /* TODO: just test case for cycles clock source, remove later */ | 119 | /* TODO: just test case for cycles clock source, remove later */ |
| 120 | pr_debug("cpufreq: done\n"); | 120 | pr_debug("cpufreq: done\n"); |
| 121 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | 121 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); |
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index ad5431e2cd05..4da50bcd9300 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S | |||
| @@ -247,7 +247,8 @@ ENTRY(_unset_dram_srfs) | |||
| 247 | ENDPROC(_unset_dram_srfs) | 247 | ENDPROC(_unset_dram_srfs) |
| 248 | 248 | ||
| 249 | ENTRY(_set_sic_iwr) | 249 | ENTRY(_set_sic_iwr) |
| 250 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 250 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ |
| 251 | defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x) | ||
| 251 | P0.H = hi(SIC_IWR0); | 252 | P0.H = hi(SIC_IWR0); |
| 252 | P0.L = lo(SIC_IWR0); | 253 | P0.L = lo(SIC_IWR0); |
| 253 | P1.H = hi(SIC_IWR1); | 254 | P1.H = hi(SIC_IWR1); |
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index bde6dc4e2614..fae774651374 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include <linux/init.h> | 36 | #include <linux/init.h> |
| 37 | #include <linux/linkage.h> | 37 | #include <linux/linkage.h> |
| 38 | #include <linux/unistd.h> | 38 | #include <linux/unistd.h> |
| 39 | #include <linux/threads.h> | ||
| 39 | #include <asm/blackfin.h> | 40 | #include <asm/blackfin.h> |
| 40 | #include <asm/errno.h> | 41 | #include <asm/errno.h> |
| 41 | #include <asm/fixed_code.h> | 42 | #include <asm/fixed_code.h> |
| @@ -75,11 +76,11 @@ ENTRY(_ex_workaround_261) | |||
| 75 | * handle it. | 76 | * handle it. |
| 76 | */ | 77 | */ |
| 77 | P4 = R7; /* Store EXCAUSE */ | 78 | P4 = R7; /* Store EXCAUSE */ |
| 78 | p5.l = _last_cplb_fault_retx; | 79 | |
| 79 | p5.h = _last_cplb_fault_retx; | 80 | GET_PDA(p5, r7); |
| 80 | r7 = [p5]; | 81 | r7 = [p5 + PDA_LFRETX]; |
| 81 | r6 = retx; | 82 | r6 = retx; |
| 82 | [p5] = r6; | 83 | [p5 + PDA_LFRETX] = r6; |
| 83 | cc = r6 == r7; | 84 | cc = r6 == r7; |
| 84 | if !cc jump _bfin_return_from_exception; | 85 | if !cc jump _bfin_return_from_exception; |
| 85 | /* fall through */ | 86 | /* fall through */ |
| @@ -111,24 +112,21 @@ ENTRY(_ex_dcplb_viol) | |||
| 111 | ENTRY(_ex_dcplb_miss) | 112 | ENTRY(_ex_dcplb_miss) |
| 112 | ENTRY(_ex_icplb_miss) | 113 | ENTRY(_ex_icplb_miss) |
| 113 | (R7:6,P5:4) = [sp++]; | 114 | (R7:6,P5:4) = [sp++]; |
| 114 | ASTAT = [sp++]; | 115 | /* We leave the previously pushed ASTAT on the stack. */ |
| 115 | SAVE_ALL_SYS | 116 | SAVE_CONTEXT_CPLB |
| 116 | #ifdef CONFIG_MPU | 117 | |
| 117 | /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that | 118 | /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that |
| 118 | * will change the stack pointer. */ | 119 | * will change the stack pointer. */ |
| 119 | R0 = SEQSTAT; | 120 | R0 = SEQSTAT; |
| 120 | R1 = SP; | 121 | R1 = SP; |
| 121 | #endif | 122 | |
| 122 | DEBUG_HWTRACE_SAVE(p5, r7) | 123 | DEBUG_HWTRACE_SAVE(p5, r7) |
| 123 | #ifdef CONFIG_MPU | 124 | |
| 124 | sp += -12; | 125 | sp += -12; |
| 125 | call _cplb_hdr; | 126 | call _cplb_hdr; |
| 126 | sp += 12; | 127 | sp += 12; |
| 127 | CC = R0 == 0; | 128 | CC = R0 == 0; |
| 128 | IF !CC JUMP _handle_bad_cplb; | 129 | IF !CC JUMP _handle_bad_cplb; |
| 129 | #else | ||
| 130 | call __cplb_hdr; | ||
| 131 | #endif | ||
| 132 | 130 | ||
| 133 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | 131 | #ifdef CONFIG_DEBUG_DOUBLEFAULT |
| 134 | /* While we were processing this, did we double fault? */ | 132 | /* While we were processing this, did we double fault? */ |
| @@ -142,7 +140,8 @@ ENTRY(_ex_icplb_miss) | |||
| 142 | #endif | 140 | #endif |
| 143 | 141 | ||
| 144 | DEBUG_HWTRACE_RESTORE(p5, r7) | 142 | DEBUG_HWTRACE_RESTORE(p5, r7) |
| 145 | RESTORE_ALL_SYS | 143 | RESTORE_CONTEXT_CPLB |
| 144 | ASTAT = [SP++]; | ||
| 146 | SP = EX_SCRATCH_REG; | 145 | SP = EX_SCRATCH_REG; |
| 147 | rtx; | 146 | rtx; |
| 148 | ENDPROC(_ex_icplb_miss) | 147 | ENDPROC(_ex_icplb_miss) |
| @@ -297,9 +296,8 @@ ENTRY(_handle_bad_cplb) | |||
| 297 | * the stack to get ready so, we can fall through - we | 296 | * the stack to get ready so, we can fall through - we |
| 298 | * need to make a CPLB exception look like a normal exception | 297 | * need to make a CPLB exception look like a normal exception |
| 299 | */ | 298 | */ |
| 300 | 299 | RESTORE_CONTEXT_CPLB | |
| 301 | RESTORE_ALL_SYS | 300 | /* ASTAT is still on the stack, where it is needed. */ |
| 302 | [--sp] = ASTAT; | ||
| 303 | [--sp] = (R7:6,P5:4); | 301 | [--sp] = (R7:6,P5:4); |
| 304 | 302 | ||
| 305 | ENTRY(_ex_replaceable) | 303 | ENTRY(_ex_replaceable) |
| @@ -324,7 +322,9 @@ ENTRY(_ex_trap_c) | |||
| 324 | [p4] = p5; | 322 | [p4] = p5; |
| 325 | csync; | 323 | csync; |
| 326 | 324 | ||
| 325 | GET_PDA(p5, r6); | ||
| 327 | #ifndef CONFIG_DEBUG_DOUBLEFAULT | 326 | #ifndef CONFIG_DEBUG_DOUBLEFAULT |
| 327 | |||
| 328 | /* | 328 | /* |
| 329 | * Save these registers, as they are only valid in exception context | 329 | * Save these registers, as they are only valid in exception context |
| 330 | * (where we are now - as soon as we defer to IRQ5, they can change) | 330 | * (where we are now - as soon as we defer to IRQ5, they can change) |
| @@ -335,29 +335,25 @@ ENTRY(_ex_trap_c) | |||
| 335 | p4.l = lo(DCPLB_FAULT_ADDR); | 335 | p4.l = lo(DCPLB_FAULT_ADDR); |
| 336 | p4.h = hi(DCPLB_FAULT_ADDR); | 336 | p4.h = hi(DCPLB_FAULT_ADDR); |
| 337 | r7 = [p4]; | 337 | r7 = [p4]; |
| 338 | p5.h = _saved_dcplb_fault_addr; | 338 | [p5 + PDA_DCPLB] = r7; |
| 339 | p5.l = _saved_dcplb_fault_addr; | ||
| 340 | [p5] = r7; | ||
| 341 | 339 | ||
| 342 | r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)]; | 340 | p4.l = lo(ICPLB_FAULT_ADDR); |
| 343 | p5.h = _saved_icplb_fault_addr; | 341 | p4.h = hi(ICPLB_FAULT_ADDR); |
| 344 | p5.l = _saved_icplb_fault_addr; | 342 | r6 = [p4]; |
| 345 | [p5] = r7; | 343 | [p5 + PDA_ICPLB] = r6; |
| 346 | 344 | ||
| 347 | r6 = retx; | 345 | r6 = retx; |
| 348 | p4.l = _saved_retx; | 346 | [p5 + PDA_RETX] = r6; |
| 349 | p4.h = _saved_retx; | ||
| 350 | [p4] = r6; | ||
| 351 | #endif | 347 | #endif |
| 352 | r6 = SYSCFG; | 348 | r6 = SYSCFG; |
| 353 | [p4 + 4] = r6; | 349 | [p5 + PDA_SYSCFG] = r6; |
| 354 | BITCLR(r6, 0); | 350 | BITCLR(r6, 0); |
| 355 | SYSCFG = r6; | 351 | SYSCFG = r6; |
| 356 | 352 | ||
| 357 | /* Disable all interrupts, but make sure level 5 is enabled so | 353 | /* Disable all interrupts, but make sure level 5 is enabled so |
| 358 | * we can switch to that level. Save the old mask. */ | 354 | * we can switch to that level. Save the old mask. */ |
| 359 | cli r6; | 355 | cli r6; |
| 360 | [p4 + 8] = r6; | 356 | [p5 + PDA_EXIMASK] = r6; |
| 361 | 357 | ||
| 362 | p4.l = lo(SAFE_USER_INSTRUCTION); | 358 | p4.l = lo(SAFE_USER_INSTRUCTION); |
| 363 | p4.h = hi(SAFE_USER_INSTRUCTION); | 359 | p4.h = hi(SAFE_USER_INSTRUCTION); |
| @@ -371,9 +367,10 @@ ENTRY(_ex_trap_c) | |||
| 371 | ENDPROC(_ex_trap_c) | 367 | ENDPROC(_ex_trap_c) |
| 372 | 368 | ||
| 373 | /* We just realized we got an exception, while we were processing a different | 369 | /* We just realized we got an exception, while we were processing a different |
| 374 | * exception. This is a unrecoverable event, so crash | 370 | * exception. This is a unrecoverable event, so crash. |
| 371 | * Note: this cannot be ENTRY() as we jump here with "if cc jump" ... | ||
| 375 | */ | 372 | */ |
| 376 | ENTRY(_double_fault) | 373 | _double_fault: |
| 377 | /* Turn caches & protection off, to ensure we don't get any more | 374 | /* Turn caches & protection off, to ensure we don't get any more |
| 378 | * double exceptions | 375 | * double exceptions |
| 379 | */ | 376 | */ |
| @@ -424,17 +421,16 @@ ENDPROC(_double_fault) | |||
| 424 | ENTRY(_exception_to_level5) | 421 | ENTRY(_exception_to_level5) |
| 425 | SAVE_ALL_SYS | 422 | SAVE_ALL_SYS |
| 426 | 423 | ||
| 427 | p4.l = _saved_retx; | 424 | GET_PDA(p4, r7); /* Fetch current PDA */ |
| 428 | p4.h = _saved_retx; | 425 | r6 = [p4 + PDA_RETX]; |
| 429 | r6 = [p4]; | ||
| 430 | [sp + PT_PC] = r6; | 426 | [sp + PT_PC] = r6; |
| 431 | 427 | ||
| 432 | r6 = [p4 + 4]; | 428 | r6 = [p4 + PDA_SYSCFG]; |
| 433 | [sp + PT_SYSCFG] = r6; | 429 | [sp + PT_SYSCFG] = r6; |
| 434 | 430 | ||
| 435 | /* Restore interrupt mask. We haven't pushed RETI, so this | 431 | /* Restore interrupt mask. We haven't pushed RETI, so this |
| 436 | * doesn't enable interrupts until we return from this handler. */ | 432 | * doesn't enable interrupts until we return from this handler. */ |
| 437 | r6 = [p4 + 8]; | 433 | r6 = [p4 + PDA_EXIMASK]; |
| 438 | sti r6; | 434 | sti r6; |
| 439 | 435 | ||
| 440 | /* Restore the hardware error vector. */ | 436 | /* Restore the hardware error vector. */ |
| @@ -478,8 +474,8 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ | |||
| 478 | * scratch register (for want of a better option). | 474 | * scratch register (for want of a better option). |
| 479 | */ | 475 | */ |
| 480 | EX_SCRATCH_REG = sp; | 476 | EX_SCRATCH_REG = sp; |
| 481 | sp.l = _exception_stack_top; | 477 | GET_PDA_SAFE(sp); |
| 482 | sp.h = _exception_stack_top; | 478 | sp = [sp + PDA_EXSTACK] |
| 483 | /* Try to deal with syscalls quickly. */ | 479 | /* Try to deal with syscalls quickly. */ |
| 484 | [--sp] = ASTAT; | 480 | [--sp] = ASTAT; |
| 485 | [--sp] = (R7:6,P5:4); | 481 | [--sp] = (R7:6,P5:4); |
| @@ -501,27 +497,22 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/ | |||
| 501 | * but they are not very interesting, so don't save them | 497 | * but they are not very interesting, so don't save them |
| 502 | */ | 498 | */ |
| 503 | 499 | ||
| 500 | GET_PDA(p5, r7); | ||
| 504 | p4.l = lo(DCPLB_FAULT_ADDR); | 501 | p4.l = lo(DCPLB_FAULT_ADDR); |
| 505 | p4.h = hi(DCPLB_FAULT_ADDR); | 502 | p4.h = hi(DCPLB_FAULT_ADDR); |
| 506 | r7 = [p4]; | 503 | r7 = [p4]; |
| 507 | p5.h = _saved_dcplb_fault_addr; | 504 | [p5 + PDA_DCPLB] = r7; |
| 508 | p5.l = _saved_dcplb_fault_addr; | ||
| 509 | [p5] = r7; | ||
| 510 | 505 | ||
| 511 | r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)]; | 506 | p4.l = lo(ICPLB_FAULT_ADDR); |
| 512 | p5.h = _saved_icplb_fault_addr; | 507 | p4.h = hi(ICPLB_FAULT_ADDR); |
| 513 | p5.l = _saved_icplb_fault_addr; | 508 | r7 = [p4]; |
| 514 | [p5] = r7; | 509 | [p5 + PDA_ICPLB] = r7; |
| 515 | 510 | ||
| 516 | p4.l = _saved_retx; | ||
| 517 | p4.h = _saved_retx; | ||
| 518 | r6 = retx; | 511 | r6 = retx; |
| 519 | [p4] = r6; | 512 | [p5 + PDA_RETX] = r6; |
| 520 | 513 | ||
| 521 | r7 = SEQSTAT; /* reason code is in bit 5:0 */ | 514 | r7 = SEQSTAT; /* reason code is in bit 5:0 */ |
| 522 | p4.l = _saved_seqstat; | 515 | [p5 + PDA_SEQSTAT] = r7; |
| 523 | p4.h = _saved_seqstat; | ||
| 524 | [p4] = r7; | ||
| 525 | #else | 516 | #else |
| 526 | r7 = SEQSTAT; /* reason code is in bit 5:0 */ | 517 | r7 = SEQSTAT; /* reason code is in bit 5:0 */ |
| 527 | #endif | 518 | #endif |
| @@ -546,11 +537,11 @@ ENTRY(_kernel_execve) | |||
| 546 | p0 = sp; | 537 | p0 = sp; |
| 547 | r3 = SIZEOF_PTREGS / 4; | 538 | r3 = SIZEOF_PTREGS / 4; |
| 548 | r4 = 0(x); | 539 | r4 = 0(x); |
| 549 | 0: | 540 | .Lclear_regs: |
| 550 | [p0++] = r4; | 541 | [p0++] = r4; |
| 551 | r3 += -1; | 542 | r3 += -1; |
| 552 | cc = r3 == 0; | 543 | cc = r3 == 0; |
| 553 | if !cc jump 0b (bp); | 544 | if !cc jump .Lclear_regs (bp); |
| 554 | 545 | ||
| 555 | p0 = sp; | 546 | p0 = sp; |
| 556 | sp += -16; | 547 | sp += -16; |
| @@ -558,7 +549,7 @@ ENTRY(_kernel_execve) | |||
| 558 | call _do_execve; | 549 | call _do_execve; |
| 559 | SP += 16; | 550 | SP += 16; |
| 560 | cc = r0 == 0; | 551 | cc = r0 == 0; |
| 561 | if ! cc jump 1f; | 552 | if ! cc jump .Lexecve_failed; |
| 562 | /* Success. Copy our temporary pt_regs to the top of the kernel | 553 | /* Success. Copy our temporary pt_regs to the top of the kernel |
| 563 | * stack and do a normal exception return. | 554 | * stack and do a normal exception return. |
| 564 | */ | 555 | */ |
| @@ -574,12 +565,12 @@ ENTRY(_kernel_execve) | |||
| 574 | p0 = fp; | 565 | p0 = fp; |
| 575 | r4 = [p0--]; | 566 | r4 = [p0--]; |
| 576 | r3 = SIZEOF_PTREGS / 4; | 567 | r3 = SIZEOF_PTREGS / 4; |
| 577 | 0: | 568 | .Lcopy_regs: |
| 578 | r4 = [p0--]; | 569 | r4 = [p0--]; |
| 579 | [p1--] = r4; | 570 | [p1--] = r4; |
| 580 | r3 += -1; | 571 | r3 += -1; |
| 581 | cc = r3 == 0; | 572 | cc = r3 == 0; |
| 582 | if ! cc jump 0b (bp); | 573 | if ! cc jump .Lcopy_regs (bp); |
| 583 | 574 | ||
| 584 | r0 = (KERNEL_STACK_SIZE - SIZEOF_PTREGS) (z); | 575 | r0 = (KERNEL_STACK_SIZE - SIZEOF_PTREGS) (z); |
| 585 | p1 = r0; | 576 | p1 = r0; |
| @@ -591,7 +582,7 @@ ENTRY(_kernel_execve) | |||
| 591 | 582 | ||
| 592 | RESTORE_CONTEXT; | 583 | RESTORE_CONTEXT; |
| 593 | rti; | 584 | rti; |
| 594 | 1: | 585 | .Lexecve_failed: |
| 595 | unlink; | 586 | unlink; |
| 596 | rts; | 587 | rts; |
| 597 | ENDPROC(_kernel_execve) | 588 | ENDPROC(_kernel_execve) |
| @@ -925,9 +916,14 @@ _schedule_and_signal_from_int: | |||
| 925 | p1 = rets; | 916 | p1 = rets; |
| 926 | [sp + PT_RESERVED] = p1; | 917 | [sp + PT_RESERVED] = p1; |
| 927 | 918 | ||
| 928 | p0.l = _irq_flags; | 919 | #ifdef CONFIG_SMP |
| 929 | p0.h = _irq_flags; | 920 | GET_PDA(p0, r0); /* Fetch current PDA (can't migrate to other CPU here) */ |
| 921 | r0 = [p0 + PDA_IRQFLAGS]; | ||
| 922 | #else | ||
| 923 | p0.l = _bfin_irq_flags; | ||
| 924 | p0.h = _bfin_irq_flags; | ||
| 930 | r0 = [p0]; | 925 | r0 = [p0]; |
| 926 | #endif | ||
| 931 | sti r0; | 927 | sti r0; |
| 932 | 928 | ||
| 933 | r0 = sp; | 929 | r0 = sp; |
| @@ -1539,14 +1535,18 @@ ENTRY(_sys_call_table) | |||
| 1539 | .endr | 1535 | .endr |
| 1540 | END(_sys_call_table) | 1536 | END(_sys_call_table) |
| 1541 | 1537 | ||
| 1542 | _exception_stack: | 1538 | #ifdef CONFIG_EXCEPTION_L1_SCRATCH |
| 1543 | .rept 1024 | 1539 | /* .section .l1.bss.scratch */ |
| 1544 | .long 0; | 1540 | .set _exception_stack_top, L1_SCRATCH_START + L1_SCRATCH_LENGTH |
| 1541 | #else | ||
| 1542 | #ifdef CONFIG_SYSCALL_TAB_L1 | ||
| 1543 | .section .l1.bss | ||
| 1544 | #else | ||
| 1545 | .bss | ||
| 1546 | #endif | ||
| 1547 | ENTRY(_exception_stack) | ||
| 1548 | .rept 1024 * NR_CPUS | ||
| 1549 | .long 0 | ||
| 1545 | .endr | 1550 | .endr |
| 1546 | _exception_stack_top: | 1551 | _exception_stack_top: |
| 1547 | |||
| 1548 | #if ANOMALY_05000261 | ||
| 1549 | /* Used by the assembly entry point to work around an anomaly. */ | ||
| 1550 | _last_cplb_fault_retx: | ||
| 1551 | .long 0; | ||
| 1552 | #endif | 1552 | #endif |
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S index f123a62e2451..e1e42c029e15 100644 --- a/arch/blackfin/mach-common/head.S +++ b/arch/blackfin/mach-common/head.S | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <asm/blackfin.h> | 13 | #include <asm/blackfin.h> |
| 14 | #include <asm/thread_info.h> | 14 | #include <asm/thread_info.h> |
| 15 | #include <asm/trace.h> | 15 | #include <asm/trace.h> |
| 16 | #include <asm/asm-offsets.h> | ||
| 16 | 17 | ||
| 17 | __INIT | 18 | __INIT |
| 18 | 19 | ||
| @@ -111,33 +112,26 @@ ENTRY(__start) | |||
| 111 | * This happens here, since L1 gets clobbered | 112 | * This happens here, since L1 gets clobbered |
| 112 | * below | 113 | * below |
| 113 | */ | 114 | */ |
| 114 | p0.l = _saved_retx; | 115 | GET_PDA(p0, r0); |
| 115 | p0.h = _saved_retx; | 116 | r7 = [p0 + PDA_RETX]; |
| 116 | p1.l = _init_saved_retx; | 117 | p1.l = _init_saved_retx; |
| 117 | p1.h = _init_saved_retx; | 118 | p1.h = _init_saved_retx; |
| 118 | r0 = [p0]; | 119 | [p1] = r7; |
| 119 | [p1] = r0; | ||
| 120 | 120 | ||
| 121 | p0.l = _saved_dcplb_fault_addr; | 121 | r7 = [p0 + PDA_DCPLB]; |
| 122 | p0.h = _saved_dcplb_fault_addr; | ||
| 123 | p1.l = _init_saved_dcplb_fault_addr; | 122 | p1.l = _init_saved_dcplb_fault_addr; |
| 124 | p1.h = _init_saved_dcplb_fault_addr; | 123 | p1.h = _init_saved_dcplb_fault_addr; |
| 125 | r0 = [p0]; | 124 | [p1] = r7; |
| 126 | [p1] = r0; | ||
| 127 | 125 | ||
| 128 | p0.l = _saved_icplb_fault_addr; | 126 | r7 = [p0 + PDA_ICPLB]; |
| 129 | p0.h = _saved_icplb_fault_addr; | ||
| 130 | p1.l = _init_saved_icplb_fault_addr; | 127 | p1.l = _init_saved_icplb_fault_addr; |
| 131 | p1.h = _init_saved_icplb_fault_addr; | 128 | p1.h = _init_saved_icplb_fault_addr; |
| 132 | r0 = [p0]; | 129 | [p1] = r7; |
| 133 | [p1] = r0; | ||
| 134 | 130 | ||
| 135 | p0.l = _saved_seqstat; | 131 | r7 = [p0 + PDA_SEQSTAT]; |
| 136 | p0.h = _saved_seqstat; | ||
| 137 | p1.l = _init_saved_seqstat; | 132 | p1.l = _init_saved_seqstat; |
| 138 | p1.h = _init_saved_seqstat; | 133 | p1.h = _init_saved_seqstat; |
| 139 | r0 = [p0]; | 134 | [p1] = r7; |
| 140 | [p1] = r0; | ||
| 141 | #endif | 135 | #endif |
| 142 | 136 | ||
| 143 | /* Initialize stack pointer */ | 137 | /* Initialize stack pointer */ |
| @@ -153,7 +147,7 @@ ENTRY(__start) | |||
| 153 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ | 147 | /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ |
| 154 | call _bfin_relocate_l1_mem; | 148 | call _bfin_relocate_l1_mem; |
| 155 | #ifdef CONFIG_BFIN_KERNEL_CLOCK | 149 | #ifdef CONFIG_BFIN_KERNEL_CLOCK |
| 156 | call _start_dma_code; | 150 | call _init_clocks; |
| 157 | #endif | 151 | #endif |
| 158 | 152 | ||
| 159 | /* This section keeps the processor in supervisor mode | 153 | /* This section keeps the processor in supervisor mode |
| @@ -170,12 +164,8 @@ ENTRY(__start) | |||
| 170 | [p0] = p1; | 164 | [p0] = p1; |
| 171 | csync; | 165 | csync; |
| 172 | 166 | ||
| 173 | p0.l = lo(IMASK); | 167 | r0 = EVT_IVG15 (z); |
| 174 | p0.h = hi(IMASK); | 168 | sti r0; |
| 175 | p1.l = IMASK_IVG15; | ||
| 176 | p1.h = 0x0; | ||
| 177 | [p0] = p1; | ||
| 178 | csync; | ||
| 179 | 169 | ||
| 180 | raise 15; | 170 | raise 15; |
| 181 | p0.l = .LWAIT_HERE; | 171 | p0.l = .LWAIT_HERE; |
| @@ -195,6 +185,19 @@ ENDPROC(__start) | |||
| 195 | # define WDOG_CTL WDOGA_CTL | 185 | # define WDOG_CTL WDOGA_CTL |
| 196 | #endif | 186 | #endif |
| 197 | 187 | ||
| 188 | ENTRY(__init_clear_bss) | ||
| 189 | r2 = r2 - r1; | ||
| 190 | cc = r2 == 0; | ||
| 191 | if cc jump .L_bss_done; | ||
| 192 | r2 >>= 2; | ||
| 193 | p1 = r1; | ||
| 194 | p2 = r2; | ||
| 195 | lsetup (1f, 1f) lc0 = p2; | ||
| 196 | 1: [p1++] = r0; | ||
| 197 | .L_bss_done: | ||
| 198 | rts; | ||
| 199 | ENDPROC(__init_clear_bss) | ||
| 200 | |||
| 198 | ENTRY(_real_start) | 201 | ENTRY(_real_start) |
| 199 | /* Enable nested interrupts */ | 202 | /* Enable nested interrupts */ |
| 200 | [--sp] = reti; | 203 | [--sp] = reti; |
| @@ -206,87 +209,34 @@ ENTRY(_real_start) | |||
| 206 | w[p0] = r0; | 209 | w[p0] = r0; |
| 207 | ssync; | 210 | ssync; |
| 208 | 211 | ||
| 212 | r0 = 0 (x); | ||
| 213 | /* Zero out all of the fun bss regions */ | ||
| 209 | #if L1_DATA_A_LENGTH > 0 | 214 | #if L1_DATA_A_LENGTH > 0 |
| 210 | r1.l = __sbss_l1; | 215 | r1.l = __sbss_l1; |
| 211 | r1.h = __sbss_l1; | 216 | r1.h = __sbss_l1; |
| 212 | r2.l = __ebss_l1; | 217 | r2.l = __ebss_l1; |
| 213 | r2.h = __ebss_l1; | 218 | r2.h = __ebss_l1; |
| 214 | r0 = 0 (z); | 219 | call __init_clear_bss |
| 215 | r2 = r2 - r1; | ||
| 216 | cc = r2 == 0; | ||
| 217 | if cc jump .L_a_l1_done; | ||
| 218 | r2 >>= 2; | ||
| 219 | p1 = r1; | ||
| 220 | p2 = r2; | ||
| 221 | lsetup (.L_clear_a_l1, .L_clear_a_l1 ) lc0 = p2; | ||
| 222 | .L_clear_a_l1: | ||
| 223 | [p1++] = r0; | ||
| 224 | .L_a_l1_done: | ||
| 225 | #endif | 220 | #endif |
| 226 | |||
| 227 | #if L1_DATA_B_LENGTH > 0 | 221 | #if L1_DATA_B_LENGTH > 0 |
| 228 | r1.l = __sbss_b_l1; | 222 | r1.l = __sbss_b_l1; |
| 229 | r1.h = __sbss_b_l1; | 223 | r1.h = __sbss_b_l1; |
| 230 | r2.l = __ebss_b_l1; | 224 | r2.l = __ebss_b_l1; |
| 231 | r2.h = __ebss_b_l1; | 225 | r2.h = __ebss_b_l1; |
| 232 | r0 = 0 (z); | 226 | call __init_clear_bss |
| 233 | r2 = r2 - r1; | ||
| 234 | cc = r2 == 0; | ||
| 235 | if cc jump .L_b_l1_done; | ||
| 236 | r2 >>= 2; | ||
| 237 | p1 = r1; | ||
| 238 | p2 = r2; | ||
| 239 | lsetup (.L_clear_b_l1, .L_clear_b_l1 ) lc0 = p2; | ||
| 240 | .L_clear_b_l1: | ||
| 241 | [p1++] = r0; | ||
| 242 | .L_b_l1_done: | ||
| 243 | #endif | 227 | #endif |
| 244 | |||
| 245 | #if L2_LENGTH > 0 | 228 | #if L2_LENGTH > 0 |
| 246 | r1.l = __sbss_l2; | 229 | r1.l = __sbss_l2; |
| 247 | r1.h = __sbss_l2; | 230 | r1.h = __sbss_l2; |
| 248 | r2.l = __ebss_l2; | 231 | r2.l = __ebss_l2; |
| 249 | r2.h = __ebss_l2; | 232 | r2.h = __ebss_l2; |
| 250 | r0 = 0 (z); | 233 | call __init_clear_bss |
| 251 | r2 = r2 - r1; | ||
| 252 | cc = r2 == 0; | ||
| 253 | if cc jump .L_l2_done; | ||
| 254 | r2 >>= 2; | ||
| 255 | p1 = r1; | ||
| 256 | p2 = r2; | ||
| 257 | lsetup (.L_clear_l2, .L_clear_l2 ) lc0 = p2; | ||
| 258 | .L_clear_l2: | ||
| 259 | [p1++] = r0; | ||
| 260 | .L_l2_done: | ||
| 261 | #endif | 234 | #endif |
| 262 | |||
| 263 | /* Zero out the bss region | ||
| 264 | * Note: this will fail if bss is 0 bytes ... | ||
| 265 | */ | ||
| 266 | r0 = 0 (z); | ||
| 267 | r1.l = ___bss_start; | 235 | r1.l = ___bss_start; |
| 268 | r1.h = ___bss_start; | 236 | r1.h = ___bss_start; |
| 269 | r2.l = ___bss_stop; | 237 | r2.l = ___bss_stop; |
| 270 | r2.h = ___bss_stop; | 238 | r2.h = ___bss_stop; |
| 271 | r2 = r2 - r1; | 239 | call __init_clear_bss |
| 272 | r2 >>= 2; | ||
| 273 | p1 = r1; | ||
| 274 | p2 = r2; | ||
| 275 | lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2; | ||
| 276 | .L_clear_bss: | ||
| 277 | [p1++] = r0; | ||
| 278 | |||
| 279 | /* In case there is a NULL pointer reference, | ||
| 280 | * zero out region before stext | ||
| 281 | */ | ||
| 282 | p1 = r0; | ||
| 283 | r2.l = __stext; | ||
| 284 | r2.h = __stext; | ||
| 285 | r2 >>= 2; | ||
| 286 | p2 = r2; | ||
| 287 | lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2; | ||
| 288 | .L_clear_zero: | ||
| 289 | [p1++] = r0; | ||
| 290 | 240 | ||
| 291 | /* Pass the u-boot arguments to the global value command line */ | 241 | /* Pass the u-boot arguments to the global value command line */ |
| 292 | R0 = R7; | 242 | R0 = R7; |
| @@ -299,6 +249,9 @@ ENTRY(_real_start) | |||
| 299 | sp = sp + p1; | 249 | sp = sp + p1; |
| 300 | usp = sp; | 250 | usp = sp; |
| 301 | fp = sp; | 251 | fp = sp; |
| 252 | sp += -12; | ||
| 253 | call _init_pda | ||
| 254 | sp += 12; | ||
| 302 | jump.l _start_kernel; | 255 | jump.l _start_kernel; |
| 303 | ENDPROC(_real_start) | 256 | ENDPROC(_real_start) |
| 304 | 257 | ||
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 4a2ec7a9675a..473df0f7fa78 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S | |||
| @@ -129,8 +129,15 @@ __common_int_entry: | |||
| 129 | #endif | 129 | #endif |
| 130 | r1 = sp; | 130 | r1 = sp; |
| 131 | SP += -12; | 131 | SP += -12; |
| 132 | #ifdef CONFIG_IPIPE | ||
| 133 | call ___ipipe_grab_irq | ||
| 134 | SP += 12; | ||
| 135 | cc = r0 == 0; | ||
| 136 | if cc jump .Lcommon_restore_context; | ||
| 137 | #else /* CONFIG_IPIPE */ | ||
| 132 | call _do_irq; | 138 | call _do_irq; |
| 133 | SP += 12; | 139 | SP += 12; |
| 140 | #endif /* CONFIG_IPIPE */ | ||
| 134 | call _return_from_int; | 141 | call _return_from_int; |
| 135 | .Lcommon_restore_context: | 142 | .Lcommon_restore_context: |
| 136 | RESTORE_CONTEXT | 143 | RESTORE_CONTEXT |
| @@ -152,15 +159,6 @@ ENTRY(_evt_ivhw) | |||
| 152 | 1: | 159 | 1: |
| 153 | #endif | 160 | #endif |
| 154 | 161 | ||
| 155 | #ifdef CONFIG_HARDWARE_PM | ||
| 156 | r7 = [sp + PT_SEQSTAT]; | ||
| 157 | r7 = r7 >>> 0xe; | ||
| 158 | r6 = 0x1F; | ||
| 159 | r7 = r7 & r6; | ||
| 160 | r5 = 0x12; | ||
| 161 | cc = r7 == r5; | ||
| 162 | if cc jump .Lcall_do_ovf; /* deal with performance counter overflow */ | ||
| 163 | #endif | ||
| 164 | # We are going to dump something out, so make sure we print IPEND properly | 162 | # We are going to dump something out, so make sure we print IPEND properly |
| 165 | p2.l = lo(IPEND); | 163 | p2.l = lo(IPEND); |
| 166 | p2.h = hi(IPEND); | 164 | p2.h = hi(IPEND); |
| @@ -192,17 +190,6 @@ ENTRY(_evt_ivhw) | |||
| 192 | .Lcommon_restore_all_sys: | 190 | .Lcommon_restore_all_sys: |
| 193 | RESTORE_ALL_SYS | 191 | RESTORE_ALL_SYS |
| 194 | rti; | 192 | rti; |
| 195 | |||
| 196 | #ifdef CONFIG_HARDWARE_PM | ||
| 197 | .Lcall_do_ovf: | ||
| 198 | |||
| 199 | SP += -12; | ||
| 200 | call _pm_overflow; | ||
| 201 | SP += 12; | ||
| 202 | |||
| 203 | jump .Lcommon_restore_all_sys; | ||
| 204 | #endif | ||
| 205 | |||
| 206 | ENDPROC(_evt_ivhw) | 193 | ENDPROC(_evt_ivhw) |
| 207 | 194 | ||
| 208 | /* Interrupt routine for evt2 (NMI). | 195 | /* Interrupt routine for evt2 (NMI). |
| @@ -245,3 +232,56 @@ ENTRY(_evt_system_call) | |||
| 245 | call _system_call; | 232 | call _system_call; |
| 246 | jump .Lcommon_restore_context; | 233 | jump .Lcommon_restore_context; |
| 247 | ENDPROC(_evt_system_call) | 234 | ENDPROC(_evt_system_call) |
| 235 | |||
| 236 | #ifdef CONFIG_IPIPE | ||
| 237 | ENTRY(___ipipe_call_irqtail) | ||
| 238 | r0.l = 1f; | ||
| 239 | r0.h = 1f; | ||
| 240 | reti = r0; | ||
| 241 | rti; | ||
| 242 | 1: | ||
| 243 | [--sp] = rets; | ||
| 244 | [--sp] = ( r7:4, p5:3 ); | ||
| 245 | p0.l = ___ipipe_irq_tail_hook; | ||
| 246 | p0.h = ___ipipe_irq_tail_hook; | ||
| 247 | p0 = [p0]; | ||
| 248 | sp += -12; | ||
| 249 | call (p0); | ||
| 250 | sp += 12; | ||
| 251 | ( r7:4, p5:3 ) = [sp++]; | ||
| 252 | rets = [sp++]; | ||
| 253 | |||
| 254 | [--sp] = reti; | ||
| 255 | reti = [sp++]; /* IRQs are off. */ | ||
| 256 | r0.h = 3f; | ||
| 257 | r0.l = 3f; | ||
| 258 | p0.l = lo(EVT14); | ||
| 259 | p0.h = hi(EVT14); | ||
| 260 | [p0] = r0; | ||
| 261 | csync; | ||
| 262 | r0 = 0x401f; | ||
| 263 | sti r0; | ||
| 264 | raise 14; | ||
| 265 | [--sp] = reti; /* IRQs on. */ | ||
| 266 | 2: | ||
| 267 | jump 2b; /* Likely paranoid. */ | ||
| 268 | 3: | ||
| 269 | sp += 4; /* Discard saved RETI */ | ||
| 270 | r0.h = _evt14_softirq; | ||
| 271 | r0.l = _evt14_softirq; | ||
| 272 | p0.l = lo(EVT14); | ||
| 273 | p0.h = hi(EVT14); | ||
| 274 | [p0] = r0; | ||
| 275 | csync; | ||
| 276 | p0.l = _bfin_irq_flags; | ||
| 277 | p0.h = _bfin_irq_flags; | ||
| 278 | r0 = [p0]; | ||
| 279 | sti r0; | ||
| 280 | #if 0 /* FIXME: this actually raises scheduling latencies */ | ||
| 281 | /* Reenable interrupts */ | ||
| 282 | [--sp] = reti; | ||
| 283 | r0 = [sp++]; | ||
| 284 | #endif | ||
| 285 | rts; | ||
| 286 | ENDPROC(___ipipe_call_irqtail) | ||
| 287 | #endif /* CONFIG_IPIPE */ | ||
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 34e8a726ffda..1bba6030dce9 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
| @@ -1,9 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: arch/blackfin/mach-common/ints-priority.c | 2 | * File: arch/blackfin/mach-common/ints-priority.c |
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | 3 | * |
| 6 | * Created: ? | ||
| 7 | * Description: Set up the interrupt priorities | 4 | * Description: Set up the interrupt priorities |
| 8 | * | 5 | * |
| 9 | * Modified: | 6 | * Modified: |
| @@ -37,6 +34,9 @@ | |||
| 37 | #include <linux/kernel_stat.h> | 34 | #include <linux/kernel_stat.h> |
| 38 | #include <linux/seq_file.h> | 35 | #include <linux/seq_file.h> |
| 39 | #include <linux/irq.h> | 36 | #include <linux/irq.h> |
| 37 | #ifdef CONFIG_IPIPE | ||
| 38 | #include <linux/ipipe.h> | ||
| 39 | #endif | ||
| 40 | #ifdef CONFIG_KGDB | 40 | #ifdef CONFIG_KGDB |
| 41 | #include <linux/kgdb.h> | 41 | #include <linux/kgdb.h> |
| 42 | #endif | 42 | #endif |
| @@ -45,6 +45,8 @@ | |||
| 45 | #include <asm/gpio.h> | 45 | #include <asm/gpio.h> |
| 46 | #include <asm/irq_handler.h> | 46 | #include <asm/irq_handler.h> |
| 47 | 47 | ||
| 48 | #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) | ||
| 49 | |||
| 48 | #ifdef BF537_FAMILY | 50 | #ifdef BF537_FAMILY |
| 49 | # define BF537_GENERIC_ERROR_INT_DEMUX | 51 | # define BF537_GENERIC_ERROR_INT_DEMUX |
| 50 | #else | 52 | #else |
| @@ -58,13 +60,16 @@ | |||
| 58 | * - | 60 | * - |
| 59 | */ | 61 | */ |
| 60 | 62 | ||
| 63 | #ifndef CONFIG_SMP | ||
| 61 | /* Initialize this to an actual value to force it into the .data | 64 | /* Initialize this to an actual value to force it into the .data |
| 62 | * section so that we know it is properly initialized at entry into | 65 | * section so that we know it is properly initialized at entry into |
| 63 | * the kernel but before bss is initialized to zero (which is where | 66 | * the kernel but before bss is initialized to zero (which is where |
| 64 | * it would live otherwise). The 0x1f magic represents the IRQs we | 67 | * it would live otherwise). The 0x1f magic represents the IRQs we |
| 65 | * cannot actually mask out in hardware. | 68 | * cannot actually mask out in hardware. |
| 66 | */ | 69 | */ |
| 67 | unsigned long irq_flags = 0x1f; | 70 | unsigned long bfin_irq_flags = 0x1f; |
| 71 | EXPORT_SYMBOL(bfin_irq_flags); | ||
| 72 | #endif | ||
| 68 | 73 | ||
| 69 | /* The number of spurious interrupts */ | 74 | /* The number of spurious interrupts */ |
| 70 | atomic_t num_spurious; | 75 | atomic_t num_spurious; |
| @@ -103,12 +108,14 @@ static void __init search_IAR(void) | |||
| 103 | for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { | 108 | for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { |
| 104 | int iar_shift = (irqn & 7) * 4; | 109 | int iar_shift = (irqn & 7) * 4; |
| 105 | if (ivg == (0xf & | 110 | if (ivg == (0xf & |
| 106 | #ifndef CONFIG_BF52x | 111 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \ |
| 112 | || defined(CONFIG_BF539) || defined(CONFIG_BF51x) | ||
| 107 | bfin_read32((unsigned long *)SIC_IAR0 + | 113 | bfin_read32((unsigned long *)SIC_IAR0 + |
| 108 | (irqn >> 3)) >> iar_shift)) { | 114 | ((irqn % 32) >> 3) + ((irqn / 32) * |
| 115 | ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) { | ||
| 109 | #else | 116 | #else |
| 110 | bfin_read32((unsigned long *)SIC_IAR0 + | 117 | bfin_read32((unsigned long *)SIC_IAR0 + |
| 111 | ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) { | 118 | (irqn >> 3)) >> iar_shift)) { |
| 112 | #endif | 119 | #endif |
| 113 | ivg_table[irq_pos].irqno = IVG7 + irqn; | 120 | ivg_table[irq_pos].irqno = IVG7 + irqn; |
| 114 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); | 121 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
| @@ -130,25 +137,25 @@ static void bfin_ack_noop(unsigned int irq) | |||
| 130 | 137 | ||
| 131 | static void bfin_core_mask_irq(unsigned int irq) | 138 | static void bfin_core_mask_irq(unsigned int irq) |
| 132 | { | 139 | { |
| 133 | irq_flags &= ~(1 << irq); | 140 | bfin_irq_flags &= ~(1 << irq); |
| 134 | if (!irqs_disabled()) | 141 | if (!irqs_disabled_hw()) |
| 135 | local_irq_enable(); | 142 | local_irq_enable_hw(); |
| 136 | } | 143 | } |
| 137 | 144 | ||
| 138 | static void bfin_core_unmask_irq(unsigned int irq) | 145 | static void bfin_core_unmask_irq(unsigned int irq) |
| 139 | { | 146 | { |
| 140 | irq_flags |= 1 << irq; | 147 | bfin_irq_flags |= 1 << irq; |
| 141 | /* | 148 | /* |
| 142 | * If interrupts are enabled, IMASK must contain the same value | 149 | * If interrupts are enabled, IMASK must contain the same value |
| 143 | * as irq_flags. Make sure that invariant holds. If interrupts | 150 | * as bfin_irq_flags. Make sure that invariant holds. If interrupts |
| 144 | * are currently disabled we need not do anything; one of the | 151 | * are currently disabled we need not do anything; one of the |
| 145 | * callers will take care of setting IMASK to the proper value | 152 | * callers will take care of setting IMASK to the proper value |
| 146 | * when reenabling interrupts. | 153 | * when reenabling interrupts. |
| 147 | * local_irq_enable just does "STI irq_flags", so it's exactly | 154 | * local_irq_enable just does "STI bfin_irq_flags", so it's exactly |
| 148 | * what we need. | 155 | * what we need. |
| 149 | */ | 156 | */ |
| 150 | if (!irqs_disabled()) | 157 | if (!irqs_disabled_hw()) |
| 151 | local_irq_enable(); | 158 | local_irq_enable_hw(); |
| 152 | return; | 159 | return; |
| 153 | } | 160 | } |
| 154 | 161 | ||
| @@ -163,8 +170,11 @@ static void bfin_internal_mask_irq(unsigned int irq) | |||
| 163 | mask_bit = SIC_SYSIRQ(irq) % 32; | 170 | mask_bit = SIC_SYSIRQ(irq) % 32; |
| 164 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & | 171 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
| 165 | ~(1 << mask_bit)); | 172 | ~(1 << mask_bit)); |
| 173 | #ifdef CONFIG_SMP | ||
| 174 | bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & | ||
| 175 | ~(1 << mask_bit)); | ||
| 176 | #endif | ||
| 166 | #endif | 177 | #endif |
| 167 | SSYNC(); | ||
| 168 | } | 178 | } |
| 169 | 179 | ||
| 170 | static void bfin_internal_unmask_irq(unsigned int irq) | 180 | static void bfin_internal_unmask_irq(unsigned int irq) |
| @@ -178,14 +188,17 @@ static void bfin_internal_unmask_irq(unsigned int irq) | |||
| 178 | mask_bit = SIC_SYSIRQ(irq) % 32; | 188 | mask_bit = SIC_SYSIRQ(irq) % 32; |
| 179 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | | 189 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | |
| 180 | (1 << mask_bit)); | 190 | (1 << mask_bit)); |
| 191 | #ifdef CONFIG_SMP | ||
| 192 | bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) | | ||
| 193 | (1 << mask_bit)); | ||
| 194 | #endif | ||
| 181 | #endif | 195 | #endif |
| 182 | SSYNC(); | ||
| 183 | } | 196 | } |
| 184 | 197 | ||
| 185 | #ifdef CONFIG_PM | 198 | #ifdef CONFIG_PM |
| 186 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) | 199 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
| 187 | { | 200 | { |
| 188 | unsigned bank, bit, wakeup = 0; | 201 | u32 bank, bit, wakeup = 0; |
| 189 | unsigned long flags; | 202 | unsigned long flags; |
| 190 | bank = SIC_SYSIRQ(irq) / 32; | 203 | bank = SIC_SYSIRQ(irq) / 32; |
| 191 | bit = SIC_SYSIRQ(irq) % 32; | 204 | bit = SIC_SYSIRQ(irq) % 32; |
| @@ -225,7 +238,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state) | |||
| 225 | break; | 238 | break; |
| 226 | } | 239 | } |
| 227 | 240 | ||
| 228 | local_irq_save(flags); | 241 | local_irq_save_hw(flags); |
| 229 | 242 | ||
| 230 | if (state) { | 243 | if (state) { |
| 231 | bfin_sic_iwr[bank] |= (1 << bit); | 244 | bfin_sic_iwr[bank] |= (1 << bit); |
| @@ -236,7 +249,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state) | |||
| 236 | vr_wakeup &= ~wakeup; | 249 | vr_wakeup &= ~wakeup; |
| 237 | } | 250 | } |
| 238 | 251 | ||
| 239 | local_irq_restore(flags); | 252 | local_irq_restore_hw(flags); |
| 240 | 253 | ||
| 241 | return 0; | 254 | return 0; |
| 242 | } | 255 | } |
| @@ -262,6 +275,19 @@ static struct irq_chip bfin_internal_irqchip = { | |||
| 262 | #endif | 275 | #endif |
| 263 | }; | 276 | }; |
| 264 | 277 | ||
| 278 | static void bfin_handle_irq(unsigned irq) | ||
| 279 | { | ||
| 280 | #ifdef CONFIG_IPIPE | ||
| 281 | struct pt_regs regs; /* Contents not used. */ | ||
| 282 | ipipe_trace_irq_entry(irq); | ||
| 283 | __ipipe_handle_irq(irq, ®s); | ||
| 284 | ipipe_trace_irq_exit(irq); | ||
| 285 | #else /* !CONFIG_IPIPE */ | ||
| 286 | struct irq_desc *desc = irq_desc + irq; | ||
| 287 | desc->handle_irq(irq, desc); | ||
| 288 | #endif /* !CONFIG_IPIPE */ | ||
| 289 | } | ||
| 290 | |||
| 265 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | 291 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 266 | static int error_int_mask; | 292 | static int error_int_mask; |
| 267 | 293 | ||
| @@ -292,8 +318,6 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, | |||
| 292 | { | 318 | { |
| 293 | int irq = 0; | 319 | int irq = 0; |
| 294 | 320 | ||
| 295 | SSYNC(); | ||
| 296 | |||
| 297 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | 321 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
| 298 | if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) | 322 | if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) |
| 299 | irq = IRQ_MAC_ERROR; | 323 | irq = IRQ_MAC_ERROR; |
| @@ -317,10 +341,9 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, | |||
| 317 | irq = IRQ_UART1_ERROR; | 341 | irq = IRQ_UART1_ERROR; |
| 318 | 342 | ||
| 319 | if (irq) { | 343 | if (irq) { |
| 320 | if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) { | 344 | if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) |
| 321 | struct irq_desc *desc = irq_desc + irq; | 345 | bfin_handle_irq(irq); |
| 322 | desc->handle_irq(irq, desc); | 346 | else { |
| 323 | } else { | ||
| 324 | 347 | ||
| 325 | switch (irq) { | 348 | switch (irq) { |
| 326 | case IRQ_PPI_ERROR: | 349 | case IRQ_PPI_ERROR: |
| @@ -366,62 +389,57 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, | |||
| 366 | 389 | ||
| 367 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) | 390 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) |
| 368 | { | 391 | { |
| 392 | #ifdef CONFIG_IPIPE | ||
| 393 | _set_irq_handler(irq, handle_edge_irq); | ||
| 394 | #else | ||
| 369 | struct irq_desc *desc = irq_desc + irq; | 395 | struct irq_desc *desc = irq_desc + irq; |
| 370 | /* May not call generic set_irq_handler() due to spinlock | 396 | /* May not call generic set_irq_handler() due to spinlock |
| 371 | recursion. */ | 397 | recursion. */ |
| 372 | desc->handle_irq = handle; | 398 | desc->handle_irq = handle; |
| 399 | #endif | ||
| 373 | } | 400 | } |
| 374 | 401 | ||
| 375 | #if !defined(CONFIG_BF54x) | 402 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); |
| 376 | |||
| 377 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; | ||
| 378 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; | ||
| 379 | |||
| 380 | extern void bfin_gpio_irq_prepare(unsigned gpio); | 403 | extern void bfin_gpio_irq_prepare(unsigned gpio); |
| 381 | 404 | ||
| 405 | #if !defined(CONFIG_BF54x) | ||
| 406 | |||
| 382 | static void bfin_gpio_ack_irq(unsigned int irq) | 407 | static void bfin_gpio_ack_irq(unsigned int irq) |
| 383 | { | 408 | { |
| 384 | u16 gpionr = irq - IRQ_PF0; | 409 | /* AFAIK ack_irq in case mask_ack is provided |
| 385 | 410 | * get's only called for edge sense irqs | |
| 386 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { | 411 | */ |
| 387 | set_gpio_data(gpionr, 0); | 412 | set_gpio_data(irq_to_gpio(irq), 0); |
| 388 | SSYNC(); | ||
| 389 | } | ||
| 390 | } | 413 | } |
| 391 | 414 | ||
| 392 | static void bfin_gpio_mask_ack_irq(unsigned int irq) | 415 | static void bfin_gpio_mask_ack_irq(unsigned int irq) |
| 393 | { | 416 | { |
| 394 | u16 gpionr = irq - IRQ_PF0; | 417 | struct irq_desc *desc = irq_desc + irq; |
| 418 | u32 gpionr = irq_to_gpio(irq); | ||
| 395 | 419 | ||
| 396 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { | 420 | if (desc->handle_irq == handle_edge_irq) |
| 397 | set_gpio_data(gpionr, 0); | 421 | set_gpio_data(gpionr, 0); |
| 398 | SSYNC(); | ||
| 399 | } | ||
| 400 | 422 | ||
| 401 | set_gpio_maska(gpionr, 0); | 423 | set_gpio_maska(gpionr, 0); |
| 402 | SSYNC(); | ||
| 403 | } | 424 | } |
| 404 | 425 | ||
| 405 | static void bfin_gpio_mask_irq(unsigned int irq) | 426 | static void bfin_gpio_mask_irq(unsigned int irq) |
| 406 | { | 427 | { |
| 407 | set_gpio_maska(irq - IRQ_PF0, 0); | 428 | set_gpio_maska(irq_to_gpio(irq), 0); |
| 408 | SSYNC(); | ||
| 409 | } | 429 | } |
| 410 | 430 | ||
| 411 | static void bfin_gpio_unmask_irq(unsigned int irq) | 431 | static void bfin_gpio_unmask_irq(unsigned int irq) |
| 412 | { | 432 | { |
| 413 | set_gpio_maska(irq - IRQ_PF0, 1); | 433 | set_gpio_maska(irq_to_gpio(irq), 1); |
| 414 | SSYNC(); | ||
| 415 | } | 434 | } |
| 416 | 435 | ||
| 417 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) | 436 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) |
| 418 | { | 437 | { |
| 419 | u16 gpionr = irq - IRQ_PF0; | 438 | u32 gpionr = irq_to_gpio(irq); |
| 420 | 439 | ||
| 421 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) | 440 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
| 422 | bfin_gpio_irq_prepare(gpionr); | 441 | bfin_gpio_irq_prepare(gpionr); |
| 423 | 442 | ||
| 424 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | ||
| 425 | bfin_gpio_unmask_irq(irq); | 443 | bfin_gpio_unmask_irq(irq); |
| 426 | 444 | ||
| 427 | return 0; | 445 | return 0; |
| @@ -429,29 +447,39 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |||
| 429 | 447 | ||
| 430 | static void bfin_gpio_irq_shutdown(unsigned int irq) | 448 | static void bfin_gpio_irq_shutdown(unsigned int irq) |
| 431 | { | 449 | { |
| 450 | u32 gpionr = irq_to_gpio(irq); | ||
| 451 | |||
| 432 | bfin_gpio_mask_irq(irq); | 452 | bfin_gpio_mask_irq(irq); |
| 433 | gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0); | 453 | __clear_bit(gpionr, gpio_enabled); |
| 454 | bfin_gpio_irq_free(gpionr); | ||
| 434 | } | 455 | } |
| 435 | 456 | ||
| 436 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | 457 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) |
| 437 | { | 458 | { |
| 438 | u16 gpionr = irq - IRQ_PF0; | 459 | int ret; |
| 460 | char buf[16]; | ||
| 461 | u32 gpionr = irq_to_gpio(irq); | ||
| 439 | 462 | ||
| 440 | if (type == IRQ_TYPE_PROBE) { | 463 | if (type == IRQ_TYPE_PROBE) { |
| 441 | /* only probe unenabled GPIO interrupt lines */ | 464 | /* only probe unenabled GPIO interrupt lines */ |
| 442 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) | 465 | if (__test_bit(gpionr, gpio_enabled)) |
| 443 | return 0; | 466 | return 0; |
| 444 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | 467 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 445 | } | 468 | } |
| 446 | 469 | ||
| 447 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | 470 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
| 448 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | 471 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
| 449 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) | 472 | |
| 473 | snprintf(buf, 16, "gpio-irq%d", irq); | ||
| 474 | ret = bfin_gpio_irq_request(gpionr, buf); | ||
| 475 | if (ret) | ||
| 476 | return ret; | ||
| 477 | |||
| 478 | if (__test_and_set_bit(gpionr, gpio_enabled)) | ||
| 450 | bfin_gpio_irq_prepare(gpionr); | 479 | bfin_gpio_irq_prepare(gpionr); |
| 451 | 480 | ||
| 452 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | ||
| 453 | } else { | 481 | } else { |
| 454 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | 482 | __clear_bit(gpionr, gpio_enabled); |
| 455 | return 0; | 483 | return 0; |
| 456 | } | 484 | } |
| 457 | 485 | ||
| @@ -472,17 +500,13 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 472 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | 500 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 473 | set_gpio_edge(gpionr, 1); | 501 | set_gpio_edge(gpionr, 1); |
| 474 | set_gpio_inen(gpionr, 1); | 502 | set_gpio_inen(gpionr, 1); |
| 475 | gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr); | ||
| 476 | set_gpio_data(gpionr, 0); | 503 | set_gpio_data(gpionr, 0); |
| 477 | 504 | ||
| 478 | } else { | 505 | } else { |
| 479 | set_gpio_edge(gpionr, 0); | 506 | set_gpio_edge(gpionr, 0); |
| 480 | gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | ||
| 481 | set_gpio_inen(gpionr, 1); | 507 | set_gpio_inen(gpionr, 1); |
| 482 | } | 508 | } |
| 483 | 509 | ||
| 484 | SSYNC(); | ||
| 485 | |||
| 486 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | 510 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 487 | bfin_set_irq_handler(irq, handle_edge_irq); | 511 | bfin_set_irq_handler(irq, handle_edge_irq); |
| 488 | else | 512 | else |
| @@ -505,22 +529,6 @@ int bfin_gpio_set_wake(unsigned int irq, unsigned int state) | |||
| 505 | } | 529 | } |
| 506 | #endif | 530 | #endif |
| 507 | 531 | ||
| 508 | static struct irq_chip bfin_gpio_irqchip = { | ||
| 509 | .name = "GPIO", | ||
| 510 | .ack = bfin_gpio_ack_irq, | ||
| 511 | .mask = bfin_gpio_mask_irq, | ||
| 512 | .mask_ack = bfin_gpio_mask_ack_irq, | ||
| 513 | .unmask = bfin_gpio_unmask_irq, | ||
| 514 | .disable = bfin_gpio_mask_irq, | ||
| 515 | .enable = bfin_gpio_unmask_irq, | ||
| 516 | .set_type = bfin_gpio_irq_type, | ||
| 517 | .startup = bfin_gpio_irq_startup, | ||
| 518 | .shutdown = bfin_gpio_irq_shutdown, | ||
| 519 | #ifdef CONFIG_PM | ||
| 520 | .set_wake = bfin_gpio_set_wake, | ||
| 521 | #endif | ||
| 522 | }; | ||
| 523 | |||
| 524 | static void bfin_demux_gpio_irq(unsigned int inta_irq, | 532 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
| 525 | struct irq_desc *desc) | 533 | struct irq_desc *desc) |
| 526 | { | 534 | { |
| @@ -537,7 +545,11 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq, | |||
| 537 | irq = IRQ_PH0; | 545 | irq = IRQ_PH0; |
| 538 | break; | 546 | break; |
| 539 | # endif | 547 | # endif |
| 540 | #elif defined(CONFIG_BF52x) | 548 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 549 | case IRQ_PORTF_INTA: | ||
| 550 | irq = IRQ_PF0; | ||
| 551 | break; | ||
| 552 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) | ||
| 541 | case IRQ_PORTF_INTA: | 553 | case IRQ_PORTF_INTA: |
| 542 | irq = IRQ_PF0; | 554 | irq = IRQ_PF0; |
| 543 | break; | 555 | break; |
| @@ -567,30 +579,22 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq, | |||
| 567 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { | 579 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { |
| 568 | irq += i; | 580 | irq += i; |
| 569 | 581 | ||
| 570 | mask = get_gpiop_data(i) & | 582 | mask = get_gpiop_data(i) & get_gpiop_maska(i); |
| 571 | (gpio_enabled[gpio_bank(i)] & | ||
| 572 | get_gpiop_maska(i)); | ||
| 573 | 583 | ||
| 574 | while (mask) { | 584 | while (mask) { |
| 575 | if (mask & 1) { | 585 | if (mask & 1) |
| 576 | desc = irq_desc + irq; | 586 | bfin_handle_irq(irq); |
| 577 | desc->handle_irq(irq, desc); | ||
| 578 | } | ||
| 579 | irq++; | 587 | irq++; |
| 580 | mask >>= 1; | 588 | mask >>= 1; |
| 581 | } | 589 | } |
| 582 | } | 590 | } |
| 583 | } else { | 591 | } else { |
| 584 | gpio = irq_to_gpio(irq); | 592 | gpio = irq_to_gpio(irq); |
| 585 | mask = get_gpiop_data(gpio) & | 593 | mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); |
| 586 | (gpio_enabled[gpio_bank(gpio)] & | ||
| 587 | get_gpiop_maska(gpio)); | ||
| 588 | 594 | ||
| 589 | do { | 595 | do { |
| 590 | if (mask & 1) { | 596 | if (mask & 1) |
| 591 | desc = irq_desc + irq; | 597 | bfin_handle_irq(irq); |
| 592 | desc->handle_irq(irq, desc); | ||
| 593 | } | ||
| 594 | irq++; | 598 | irq++; |
| 595 | mask >>= 1; | 599 | mask >>= 1; |
| 596 | } while (mask); | 600 | } while (mask); |
| @@ -612,10 +616,6 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq, | |||
| 612 | static unsigned char irq2pint_lut[NR_PINTS]; | 616 | static unsigned char irq2pint_lut[NR_PINTS]; |
| 613 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; | 617 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
| 614 | 618 | ||
| 615 | static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS]; | ||
| 616 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; | ||
| 617 | |||
| 618 | |||
| 619 | struct pin_int_t { | 619 | struct pin_int_t { |
| 620 | unsigned int mask_set; | 620 | unsigned int mask_set; |
| 621 | unsigned int mask_clear; | 621 | unsigned int mask_clear; |
| @@ -636,12 +636,9 @@ static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { | |||
| 636 | (struct pin_int_t *)PINT3_MASK_SET, | 636 | (struct pin_int_t *)PINT3_MASK_SET, |
| 637 | }; | 637 | }; |
| 638 | 638 | ||
| 639 | extern void bfin_gpio_irq_prepare(unsigned gpio); | 639 | inline unsigned int get_irq_base(u32 bank, u8 bmap) |
| 640 | |||
| 641 | inline unsigned short get_irq_base(u8 bank, u8 bmap) | ||
| 642 | { | 640 | { |
| 643 | 641 | unsigned int irq_base; | |
| 644 | u16 irq_base; | ||
| 645 | 642 | ||
| 646 | if (bank < 2) { /*PA-PB */ | 643 | if (bank < 2) { /*PA-PB */ |
| 647 | irq_base = IRQ_PA0 + bmap * 16; | 644 | irq_base = IRQ_PA0 + bmap * 16; |
| @@ -650,7 +647,6 @@ inline unsigned short get_irq_base(u8 bank, u8 bmap) | |||
| 650 | } | 647 | } |
| 651 | 648 | ||
| 652 | return irq_base; | 649 | return irq_base; |
| 653 | |||
| 654 | } | 650 | } |
| 655 | 651 | ||
| 656 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | 652 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| @@ -677,20 +673,18 @@ void init_pint_lut(void) | |||
| 677 | 673 | ||
| 678 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; | 674 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
| 679 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; | 675 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
| 680 | |||
| 681 | } | 676 | } |
| 682 | |||
| 683 | } | 677 | } |
| 684 | |||
| 685 | } | 678 | } |
| 686 | 679 | ||
| 687 | static void bfin_gpio_ack_irq(unsigned int irq) | 680 | static void bfin_gpio_ack_irq(unsigned int irq) |
| 688 | { | 681 | { |
| 689 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | 682 | struct irq_desc *desc = irq_desc + irq; |
| 683 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; | ||
| 690 | u32 pintbit = PINT_BIT(pint_val); | 684 | u32 pintbit = PINT_BIT(pint_val); |
| 691 | u8 bank = PINT_2_BANK(pint_val); | 685 | u32 bank = PINT_2_BANK(pint_val); |
| 692 | 686 | ||
| 693 | if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) { | 687 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
| 694 | if (pint[bank]->invert_set & pintbit) | 688 | if (pint[bank]->invert_set & pintbit) |
| 695 | pint[bank]->invert_clear = pintbit; | 689 | pint[bank]->invert_clear = pintbit; |
| 696 | else | 690 | else |
| @@ -698,16 +692,16 @@ static void bfin_gpio_ack_irq(unsigned int irq) | |||
| 698 | } | 692 | } |
| 699 | pint[bank]->request = pintbit; | 693 | pint[bank]->request = pintbit; |
| 700 | 694 | ||
| 701 | SSYNC(); | ||
| 702 | } | 695 | } |
| 703 | 696 | ||
| 704 | static void bfin_gpio_mask_ack_irq(unsigned int irq) | 697 | static void bfin_gpio_mask_ack_irq(unsigned int irq) |
| 705 | { | 698 | { |
| 706 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | 699 | struct irq_desc *desc = irq_desc + irq; |
| 700 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; | ||
| 707 | u32 pintbit = PINT_BIT(pint_val); | 701 | u32 pintbit = PINT_BIT(pint_val); |
| 708 | u8 bank = PINT_2_BANK(pint_val); | 702 | u32 bank = PINT_2_BANK(pint_val); |
| 709 | 703 | ||
| 710 | if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) { | 704 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
| 711 | if (pint[bank]->invert_set & pintbit) | 705 | if (pint[bank]->invert_set & pintbit) |
| 712 | pint[bank]->invert_clear = pintbit; | 706 | pint[bank]->invert_clear = pintbit; |
| 713 | else | 707 | else |
| @@ -716,32 +710,29 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq) | |||
| 716 | 710 | ||
| 717 | pint[bank]->request = pintbit; | 711 | pint[bank]->request = pintbit; |
| 718 | pint[bank]->mask_clear = pintbit; | 712 | pint[bank]->mask_clear = pintbit; |
| 719 | SSYNC(); | ||
| 720 | } | 713 | } |
| 721 | 714 | ||
| 722 | static void bfin_gpio_mask_irq(unsigned int irq) | 715 | static void bfin_gpio_mask_irq(unsigned int irq) |
| 723 | { | 716 | { |
| 724 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | 717 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 725 | 718 | ||
| 726 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); | 719 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); |
| 727 | SSYNC(); | ||
| 728 | } | 720 | } |
| 729 | 721 | ||
| 730 | static void bfin_gpio_unmask_irq(unsigned int irq) | 722 | static void bfin_gpio_unmask_irq(unsigned int irq) |
| 731 | { | 723 | { |
| 732 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | 724 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 733 | u32 pintbit = PINT_BIT(pint_val); | 725 | u32 pintbit = PINT_BIT(pint_val); |
| 734 | u8 bank = PINT_2_BANK(pint_val); | 726 | u32 bank = PINT_2_BANK(pint_val); |
| 735 | 727 | ||
| 736 | pint[bank]->request = pintbit; | 728 | pint[bank]->request = pintbit; |
| 737 | pint[bank]->mask_set = pintbit; | 729 | pint[bank]->mask_set = pintbit; |
| 738 | SSYNC(); | ||
| 739 | } | 730 | } |
| 740 | 731 | ||
| 741 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) | 732 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) |
| 742 | { | 733 | { |
| 743 | u16 gpionr = irq_to_gpio(irq); | 734 | u32 gpionr = irq_to_gpio(irq); |
| 744 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | 735 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 745 | 736 | ||
| 746 | if (pint_val == IRQ_NOT_AVAIL) { | 737 | if (pint_val == IRQ_NOT_AVAIL) { |
| 747 | printk(KERN_ERR | 738 | printk(KERN_ERR |
| @@ -750,10 +741,9 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |||
| 750 | return -ENODEV; | 741 | return -ENODEV; |
| 751 | } | 742 | } |
| 752 | 743 | ||
| 753 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) | 744 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
| 754 | bfin_gpio_irq_prepare(gpionr); | 745 | bfin_gpio_irq_prepare(gpionr); |
| 755 | 746 | ||
| 756 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | ||
| 757 | bfin_gpio_unmask_irq(irq); | 747 | bfin_gpio_unmask_irq(irq); |
| 758 | 748 | ||
| 759 | return 0; | 749 | return 0; |
| @@ -761,38 +751,45 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |||
| 761 | 751 | ||
| 762 | static void bfin_gpio_irq_shutdown(unsigned int irq) | 752 | static void bfin_gpio_irq_shutdown(unsigned int irq) |
| 763 | { | 753 | { |
| 764 | u16 gpionr = irq_to_gpio(irq); | 754 | u32 gpionr = irq_to_gpio(irq); |
| 765 | 755 | ||
| 766 | bfin_gpio_mask_irq(irq); | 756 | bfin_gpio_mask_irq(irq); |
| 767 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | 757 | __clear_bit(gpionr, gpio_enabled); |
| 758 | bfin_gpio_irq_free(gpionr); | ||
| 768 | } | 759 | } |
| 769 | 760 | ||
| 770 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | 761 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) |
| 771 | { | 762 | { |
| 772 | 763 | int ret; | |
| 773 | u16 gpionr = irq_to_gpio(irq); | 764 | char buf[16]; |
| 774 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | 765 | u32 gpionr = irq_to_gpio(irq); |
| 766 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; | ||
| 775 | u32 pintbit = PINT_BIT(pint_val); | 767 | u32 pintbit = PINT_BIT(pint_val); |
| 776 | u8 bank = PINT_2_BANK(pint_val); | 768 | u32 bank = PINT_2_BANK(pint_val); |
| 777 | 769 | ||
| 778 | if (pint_val == IRQ_NOT_AVAIL) | 770 | if (pint_val == IRQ_NOT_AVAIL) |
| 779 | return -ENODEV; | 771 | return -ENODEV; |
| 780 | 772 | ||
| 781 | if (type == IRQ_TYPE_PROBE) { | 773 | if (type == IRQ_TYPE_PROBE) { |
| 782 | /* only probe unenabled GPIO interrupt lines */ | 774 | /* only probe unenabled GPIO interrupt lines */ |
| 783 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) | 775 | if (__test_bit(gpionr, gpio_enabled)) |
| 784 | return 0; | 776 | return 0; |
| 785 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | 777 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 786 | } | 778 | } |
| 787 | 779 | ||
| 788 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | 780 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
| 789 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | 781 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
| 790 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) | 782 | |
| 783 | snprintf(buf, 16, "gpio-irq%d", irq); | ||
| 784 | ret = bfin_gpio_irq_request(gpionr, buf); | ||
| 785 | if (ret) | ||
| 786 | return ret; | ||
| 787 | |||
| 788 | if (__test_and_set_bit(gpionr, gpio_enabled)) | ||
| 791 | bfin_gpio_irq_prepare(gpionr); | 789 | bfin_gpio_irq_prepare(gpionr); |
| 792 | 790 | ||
| 793 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | ||
| 794 | } else { | 791 | } else { |
| 795 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | 792 | __clear_bit(gpionr, gpio_enabled); |
| 796 | return 0; | 793 | return 0; |
| 797 | } | 794 | } |
| 798 | 795 | ||
| @@ -803,15 +800,10 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 803 | 800 | ||
| 804 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | 801 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 805 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | 802 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 806 | |||
| 807 | gpio_both_edge_triggered[bank] |= pintbit; | ||
| 808 | |||
| 809 | if (gpio_get_value(gpionr)) | 803 | if (gpio_get_value(gpionr)) |
| 810 | pint[bank]->invert_set = pintbit; | 804 | pint[bank]->invert_set = pintbit; |
| 811 | else | 805 | else |
| 812 | pint[bank]->invert_clear = pintbit; | 806 | pint[bank]->invert_clear = pintbit; |
| 813 | } else { | ||
| 814 | gpio_both_edge_triggered[bank] &= ~pintbit; | ||
| 815 | } | 807 | } |
| 816 | 808 | ||
| 817 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | 809 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| @@ -822,8 +814,6 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |||
| 822 | bfin_set_irq_handler(irq, handle_level_irq); | 814 | bfin_set_irq_handler(irq, handle_level_irq); |
| 823 | } | 815 | } |
| 824 | 816 | ||
| 825 | SSYNC(); | ||
| 826 | |||
| 827 | return 0; | 817 | return 0; |
| 828 | } | 818 | } |
| 829 | 819 | ||
| @@ -834,7 +824,7 @@ u32 pint_wakeup_masks[NR_PINT_SYS_IRQS]; | |||
| 834 | int bfin_gpio_set_wake(unsigned int irq, unsigned int state) | 824 | int bfin_gpio_set_wake(unsigned int irq, unsigned int state) |
| 835 | { | 825 | { |
| 836 | u32 pint_irq; | 826 | u32 pint_irq; |
| 837 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | 827 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 838 | u32 bank = PINT_2_BANK(pint_val); | 828 | u32 bank = PINT_2_BANK(pint_val); |
| 839 | u32 pintbit = PINT_BIT(pint_val); | 829 | u32 pintbit = PINT_BIT(pint_val); |
| 840 | 830 | ||
| @@ -895,26 +885,10 @@ void bfin_pm_restore(void) | |||
| 895 | } | 885 | } |
| 896 | #endif | 886 | #endif |
| 897 | 887 | ||
| 898 | static struct irq_chip bfin_gpio_irqchip = { | ||
| 899 | .name = "GPIO", | ||
| 900 | .ack = bfin_gpio_ack_irq, | ||
| 901 | .mask = bfin_gpio_mask_irq, | ||
| 902 | .mask_ack = bfin_gpio_mask_ack_irq, | ||
| 903 | .unmask = bfin_gpio_unmask_irq, | ||
| 904 | .disable = bfin_gpio_mask_irq, | ||
| 905 | .enable = bfin_gpio_unmask_irq, | ||
| 906 | .set_type = bfin_gpio_irq_type, | ||
| 907 | .startup = bfin_gpio_irq_startup, | ||
| 908 | .shutdown = bfin_gpio_irq_shutdown, | ||
| 909 | #ifdef CONFIG_PM | ||
| 910 | .set_wake = bfin_gpio_set_wake, | ||
| 911 | #endif | ||
| 912 | }; | ||
| 913 | |||
| 914 | static void bfin_demux_gpio_irq(unsigned int inta_irq, | 888 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
| 915 | struct irq_desc *desc) | 889 | struct irq_desc *desc) |
| 916 | { | 890 | { |
| 917 | u8 bank, pint_val; | 891 | u32 bank, pint_val; |
| 918 | u32 request, irq; | 892 | u32 request, irq; |
| 919 | 893 | ||
| 920 | switch (inta_irq) { | 894 | switch (inta_irq) { |
| @@ -941,8 +915,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq, | |||
| 941 | while (request) { | 915 | while (request) { |
| 942 | if (request & 1) { | 916 | if (request & 1) { |
| 943 | irq = pint2irq_lut[pint_val] + SYS_IRQS; | 917 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
| 944 | desc = irq_desc + irq; | 918 | bfin_handle_irq(irq); |
| 945 | desc->handle_irq(irq, desc); | ||
| 946 | } | 919 | } |
| 947 | pint_val++; | 920 | pint_val++; |
| 948 | request >>= 1; | 921 | request >>= 1; |
| @@ -951,10 +924,24 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq, | |||
| 951 | } | 924 | } |
| 952 | #endif | 925 | #endif |
| 953 | 926 | ||
| 954 | void __init init_exception_vectors(void) | 927 | static struct irq_chip bfin_gpio_irqchip = { |
| 955 | { | 928 | .name = "GPIO", |
| 956 | SSYNC(); | 929 | .ack = bfin_gpio_ack_irq, |
| 930 | .mask = bfin_gpio_mask_irq, | ||
| 931 | .mask_ack = bfin_gpio_mask_ack_irq, | ||
| 932 | .unmask = bfin_gpio_unmask_irq, | ||
| 933 | .disable = bfin_gpio_mask_irq, | ||
| 934 | .enable = bfin_gpio_unmask_irq, | ||
| 935 | .set_type = bfin_gpio_irq_type, | ||
| 936 | .startup = bfin_gpio_irq_startup, | ||
| 937 | .shutdown = bfin_gpio_irq_shutdown, | ||
| 938 | #ifdef CONFIG_PM | ||
| 939 | .set_wake = bfin_gpio_set_wake, | ||
| 940 | #endif | ||
| 941 | }; | ||
| 957 | 942 | ||
| 943 | void __cpuinit init_exception_vectors(void) | ||
| 944 | { | ||
| 958 | /* cannot program in software: | 945 | /* cannot program in software: |
| 959 | * evt0 - emulation (jtag) | 946 | * evt0 - emulation (jtag) |
| 960 | * evt1 - reset | 947 | * evt1 - reset |
| @@ -979,17 +966,23 @@ void __init init_exception_vectors(void) | |||
| 979 | * This function should be called during kernel startup to initialize | 966 | * This function should be called during kernel startup to initialize |
| 980 | * the BFin IRQ handling routines. | 967 | * the BFin IRQ handling routines. |
| 981 | */ | 968 | */ |
| 969 | |||
| 982 | int __init init_arch_irq(void) | 970 | int __init init_arch_irq(void) |
| 983 | { | 971 | { |
| 984 | int irq; | 972 | int irq; |
| 985 | unsigned long ilat = 0; | 973 | unsigned long ilat = 0; |
| 986 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ | 974 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ |
| 987 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 975 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
| 976 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) | ||
| 988 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); | 977 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
| 989 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); | 978 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); |
| 990 | # ifdef CONFIG_BF54x | 979 | # ifdef CONFIG_BF54x |
| 991 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); | 980 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
| 992 | # endif | 981 | # endif |
| 982 | # ifdef CONFIG_SMP | ||
| 983 | bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); | ||
| 984 | bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); | ||
| 985 | # endif | ||
| 993 | #else | 986 | #else |
| 994 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); | 987 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
| 995 | #endif | 988 | #endif |
| @@ -1029,7 +1022,7 @@ int __init init_arch_irq(void) | |||
| 1029 | case IRQ_PINT1: | 1022 | case IRQ_PINT1: |
| 1030 | case IRQ_PINT2: | 1023 | case IRQ_PINT2: |
| 1031 | case IRQ_PINT3: | 1024 | case IRQ_PINT3: |
| 1032 | #elif defined(CONFIG_BF52x) | 1025 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
| 1033 | case IRQ_PORTF_INTA: | 1026 | case IRQ_PORTF_INTA: |
| 1034 | case IRQ_PORTG_INTA: | 1027 | case IRQ_PORTG_INTA: |
| 1035 | case IRQ_PORTH_INTA: | 1028 | case IRQ_PORTH_INTA: |
| @@ -1037,18 +1030,41 @@ int __init init_arch_irq(void) | |||
| 1037 | case IRQ_PROG0_INTA: | 1030 | case IRQ_PROG0_INTA: |
| 1038 | case IRQ_PROG1_INTA: | 1031 | case IRQ_PROG1_INTA: |
| 1039 | case IRQ_PROG2_INTA: | 1032 | case IRQ_PROG2_INTA: |
| 1033 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) | ||
| 1034 | case IRQ_PORTF_INTA: | ||
| 1040 | #endif | 1035 | #endif |
| 1036 | |||
| 1041 | set_irq_chained_handler(irq, | 1037 | set_irq_chained_handler(irq, |
| 1042 | bfin_demux_gpio_irq); | 1038 | bfin_demux_gpio_irq); |
| 1043 | break; | 1039 | break; |
| 1044 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | 1040 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 1045 | case IRQ_GENERIC_ERROR: | 1041 | case IRQ_GENERIC_ERROR: |
| 1046 | set_irq_handler(irq, bfin_demux_error_irq); | 1042 | set_irq_chained_handler(irq, bfin_demux_error_irq); |
| 1047 | 1043 | break; | |
| 1044 | #endif | ||
| 1045 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | ||
| 1046 | case IRQ_TIMER0: | ||
| 1047 | set_irq_handler(irq, handle_percpu_irq); | ||
| 1048 | break; | ||
| 1049 | #endif | ||
| 1050 | #ifdef CONFIG_SMP | ||
| 1051 | case IRQ_SUPPLE_0: | ||
| 1052 | case IRQ_SUPPLE_1: | ||
| 1053 | set_irq_handler(irq, handle_percpu_irq); | ||
| 1048 | break; | 1054 | break; |
| 1049 | #endif | 1055 | #endif |
| 1050 | default: | 1056 | default: |
| 1057 | #ifdef CONFIG_IPIPE | ||
| 1058 | /* | ||
| 1059 | * We want internal interrupt sources to be masked, because | ||
| 1060 | * ISRs may trigger interrupts recursively (e.g. DMA), but | ||
| 1061 | * interrupts are _not_ masked at CPU level. So let's handle | ||
| 1062 | * them as level interrupts. | ||
| 1063 | */ | ||
| 1064 | set_irq_handler(irq, handle_level_irq); | ||
| 1065 | #else /* !CONFIG_IPIPE */ | ||
| 1051 | set_irq_handler(irq, handle_simple_irq); | 1066 | set_irq_handler(irq, handle_simple_irq); |
| 1067 | #endif /* !CONFIG_IPIPE */ | ||
| 1052 | break; | 1068 | break; |
| 1053 | } | 1069 | } |
| 1054 | } | 1070 | } |
| @@ -1073,7 +1089,7 @@ int __init init_arch_irq(void) | |||
| 1073 | CSYNC(); | 1089 | CSYNC(); |
| 1074 | 1090 | ||
| 1075 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); | 1091 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
| 1076 | /* IMASK=xxx is equivalent to STI xx or irq_flags=xx, | 1092 | /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, |
| 1077 | * local_irq_enable() | 1093 | * local_irq_enable() |
| 1078 | */ | 1094 | */ |
| 1079 | program_IAR(); | 1095 | program_IAR(); |
| @@ -1081,19 +1097,23 @@ int __init init_arch_irq(void) | |||
| 1081 | search_IAR(); | 1097 | search_IAR(); |
| 1082 | 1098 | ||
| 1083 | /* Enable interrupts IVG7-15 */ | 1099 | /* Enable interrupts IVG7-15 */ |
| 1084 | irq_flags = irq_flags | IMASK_IVG15 | | 1100 | bfin_irq_flags |= IMASK_IVG15 | |
| 1085 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | 1101 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
| 1086 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | 1102 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
| 1087 | 1103 | ||
| 1088 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 1104 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
| 1105 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) | ||
| 1089 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); | 1106 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
| 1090 | #if defined(CONFIG_BF52x) | 1107 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
| 1091 | /* BF52x system reset does not properly reset SIC_IWR1 which | 1108 | /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which |
| 1092 | * will screw up the bootrom as it relies on MDMA0/1 waking it | 1109 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
| 1093 | * up from IDLE instructions. See this report for more info: | 1110 | * up from IDLE instructions. See this report for more info: |
| 1094 | * http://blackfin.uclinux.org/gf/tracker/4323 | 1111 | * http://blackfin.uclinux.org/gf/tracker/4323 |
| 1095 | */ | 1112 | */ |
| 1096 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | 1113 | if (ANOMALY_05000435) |
| 1114 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | ||
| 1115 | else | ||
| 1116 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | ||
| 1097 | #else | 1117 | #else |
| 1098 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | 1118 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
| 1099 | #endif | 1119 | #endif |
| @@ -1104,6 +1124,14 @@ int __init init_arch_irq(void) | |||
| 1104 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); | 1124 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
| 1105 | #endif | 1125 | #endif |
| 1106 | 1126 | ||
| 1127 | #ifdef CONFIG_IPIPE | ||
| 1128 | for (irq = 0; irq < NR_IRQS; irq++) { | ||
| 1129 | struct irq_desc *desc = irq_desc + irq; | ||
| 1130 | desc->ic_prio = __ipipe_get_irq_priority(irq); | ||
| 1131 | desc->thr_prio = __ipipe_get_irqthread_priority(irq); | ||
| 1132 | } | ||
| 1133 | #endif /* CONFIG_IPIPE */ | ||
| 1134 | |||
| 1107 | return 0; | 1135 | return 0; |
| 1108 | } | 1136 | } |
| 1109 | 1137 | ||
| @@ -1117,11 +1145,20 @@ void do_irq(int vec, struct pt_regs *fp) | |||
| 1117 | } else { | 1145 | } else { |
| 1118 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; | 1146 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; |
| 1119 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; | 1147 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; |
| 1120 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 1148 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \ |
| 1149 | || defined(BF538_FAMILY) || defined(CONFIG_BF51x) | ||
| 1121 | unsigned long sic_status[3]; | 1150 | unsigned long sic_status[3]; |
| 1122 | 1151 | ||
| 1123 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); | 1152 | if (smp_processor_id()) { |
| 1124 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); | 1153 | #ifdef CONFIG_SMP |
| 1154 | /* This will be optimized out in UP mode. */ | ||
| 1155 | sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); | ||
| 1156 | sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); | ||
| 1157 | #endif | ||
| 1158 | } else { | ||
| 1159 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); | ||
| 1160 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); | ||
| 1161 | } | ||
| 1125 | #ifdef CONFIG_BF54x | 1162 | #ifdef CONFIG_BF54x |
| 1126 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); | 1163 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
| 1127 | #endif | 1164 | #endif |
| @@ -1150,3 +1187,161 @@ void do_irq(int vec, struct pt_regs *fp) | |||
| 1150 | } | 1187 | } |
| 1151 | asm_do_IRQ(vec, fp); | 1188 | asm_do_IRQ(vec, fp); |
| 1152 | } | 1189 | } |
| 1190 | |||
| 1191 | #ifdef CONFIG_IPIPE | ||
| 1192 | |||
| 1193 | int __ipipe_get_irq_priority(unsigned irq) | ||
| 1194 | { | ||
| 1195 | int ient, prio; | ||
| 1196 | |||
| 1197 | if (irq <= IRQ_CORETMR) | ||
| 1198 | return irq; | ||
| 1199 | |||
| 1200 | for (ient = 0; ient < NR_PERI_INTS; ient++) { | ||
| 1201 | struct ivgx *ivg = ivg_table + ient; | ||
| 1202 | if (ivg->irqno == irq) { | ||
| 1203 | for (prio = 0; prio <= IVG13-IVG7; prio++) { | ||
| 1204 | if (ivg7_13[prio].ifirst <= ivg && | ||
| 1205 | ivg7_13[prio].istop > ivg) | ||
| 1206 | return IVG7 + prio; | ||
| 1207 | } | ||
| 1208 | } | ||
| 1209 | } | ||
| 1210 | |||
| 1211 | return IVG15; | ||
| 1212 | } | ||
| 1213 | |||
| 1214 | int __ipipe_get_irqthread_priority(unsigned irq) | ||
| 1215 | { | ||
| 1216 | int ient, prio; | ||
| 1217 | int demux_irq; | ||
| 1218 | |||
| 1219 | /* The returned priority value is rescaled to [0..IVG13+1] | ||
| 1220 | * with 0 being the lowest effective priority level. */ | ||
| 1221 | |||
| 1222 | if (irq <= IRQ_CORETMR) | ||
| 1223 | return IVG13 - irq + 1; | ||
| 1224 | |||
| 1225 | /* GPIO IRQs are given the priority of the demux | ||
| 1226 | * interrupt. */ | ||
| 1227 | if (IS_GPIOIRQ(irq)) { | ||
| 1228 | #if defined(CONFIG_BF54x) | ||
| 1229 | u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]); | ||
| 1230 | demux_irq = (bank == 0 ? IRQ_PINT0 : | ||
| 1231 | bank == 1 ? IRQ_PINT1 : | ||
| 1232 | bank == 2 ? IRQ_PINT2 : | ||
| 1233 | IRQ_PINT3); | ||
| 1234 | #elif defined(CONFIG_BF561) | ||
| 1235 | demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA : | ||
| 1236 | irq >= IRQ_PF16 ? IRQ_PROG1_INTA : | ||
| 1237 | IRQ_PROG0_INTA); | ||
| 1238 | #elif defined(CONFIG_BF52x) | ||
| 1239 | demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA : | ||
| 1240 | irq >= IRQ_PG0 ? IRQ_PORTG_INTA : | ||
| 1241 | IRQ_PORTF_INTA); | ||
| 1242 | #else | ||
| 1243 | demux_irq = irq; | ||
| 1244 | #endif | ||
| 1245 | return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1; | ||
| 1246 | } | ||
| 1247 | |||
| 1248 | /* The GPIO demux interrupt is given a lower priority | ||
| 1249 | * than the GPIO IRQs, so that its threaded handler | ||
| 1250 | * unmasks the interrupt line after the decoded IRQs | ||
| 1251 | * have been processed. */ | ||
| 1252 | prio = PRIO_GPIODEMUX(irq); | ||
| 1253 | /* demux irq? */ | ||
| 1254 | if (prio != -1) | ||
| 1255 | return IVG13 - prio; | ||
| 1256 | |||
| 1257 | for (ient = 0; ient < NR_PERI_INTS; ient++) { | ||
| 1258 | struct ivgx *ivg = ivg_table + ient; | ||
| 1259 | if (ivg->irqno == irq) { | ||
| 1260 | for (prio = 0; prio <= IVG13-IVG7; prio++) { | ||
| 1261 | if (ivg7_13[prio].ifirst <= ivg && | ||
| 1262 | ivg7_13[prio].istop > ivg) | ||
| 1263 | return IVG7 - prio; | ||
| 1264 | } | ||
| 1265 | } | ||
| 1266 | } | ||
| 1267 | |||
| 1268 | return 0; | ||
| 1269 | } | ||
| 1270 | |||
| 1271 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ | ||
| 1272 | #ifdef CONFIG_DO_IRQ_L1 | ||
| 1273 | __attribute__((l1_text)) | ||
| 1274 | #endif | ||
| 1275 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | ||
| 1276 | { | ||
| 1277 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; | ||
| 1278 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; | ||
| 1279 | int irq; | ||
| 1280 | |||
| 1281 | if (likely(vec == EVT_IVTMR_P)) { | ||
| 1282 | irq = IRQ_CORETMR; | ||
| 1283 | goto handle_irq; | ||
| 1284 | } | ||
| 1285 | |||
| 1286 | SSYNC(); | ||
| 1287 | |||
| 1288 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | ||
| 1289 | { | ||
| 1290 | unsigned long sic_status[3]; | ||
| 1291 | |||
| 1292 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); | ||
| 1293 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); | ||
| 1294 | #ifdef CONFIG_BF54x | ||
| 1295 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); | ||
| 1296 | #endif | ||
| 1297 | for (;; ivg++) { | ||
| 1298 | if (ivg >= ivg_stop) { | ||
| 1299 | atomic_inc(&num_spurious); | ||
| 1300 | return 0; | ||
| 1301 | } | ||
| 1302 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) | ||
| 1303 | break; | ||
| 1304 | } | ||
| 1305 | } | ||
| 1306 | #else | ||
| 1307 | { | ||
| 1308 | unsigned long sic_status; | ||
| 1309 | |||
| 1310 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); | ||
| 1311 | |||
| 1312 | for (;; ivg++) { | ||
| 1313 | if (ivg >= ivg_stop) { | ||
| 1314 | atomic_inc(&num_spurious); | ||
| 1315 | return 0; | ||
| 1316 | } else if (sic_status & ivg->isrflag) | ||
| 1317 | break; | ||
| 1318 | } | ||
| 1319 | } | ||
| 1320 | #endif | ||
| 1321 | |||
| 1322 | irq = ivg->irqno; | ||
| 1323 | |||
| 1324 | if (irq == IRQ_SYSTMR) { | ||
| 1325 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ | ||
| 1326 | /* This is basically what we need from the register frame. */ | ||
| 1327 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; | ||
| 1328 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; | ||
| 1329 | if (!ipipe_root_domain_p) | ||
| 1330 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; | ||
| 1331 | else | ||
| 1332 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; | ||
| 1333 | } | ||
| 1334 | |||
| 1335 | handle_irq: | ||
| 1336 | |||
| 1337 | ipipe_trace_irq_entry(irq); | ||
| 1338 | __ipipe_handle_irq(irq, regs); | ||
| 1339 | ipipe_trace_irq_exit(irq); | ||
| 1340 | |||
| 1341 | if (ipipe_root_domain_p) | ||
| 1342 | return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); | ||
| 1343 | |||
| 1344 | return 0; | ||
| 1345 | } | ||
| 1346 | |||
| 1347 | #endif /* CONFIG_IPIPE */ | ||
diff --git a/arch/blackfin/mach-common/irqpanic.c b/arch/blackfin/mach-common/irqpanic.c index 606ded9ff4e1..05004df0f78b 100644 --- a/arch/blackfin/mach-common/irqpanic.c +++ b/arch/blackfin/mach-common/irqpanic.c | |||
| @@ -33,8 +33,6 @@ | |||
| 33 | #include <asm/traps.h> | 33 | #include <asm/traps.h> |
| 34 | #include <asm/blackfin.h> | 34 | #include <asm/blackfin.h> |
| 35 | 35 | ||
| 36 | #include "../oprofile/op_blackfin.h" | ||
| 37 | |||
| 38 | #ifdef CONFIG_DEBUG_ICACHE_CHECK | 36 | #ifdef CONFIG_DEBUG_ICACHE_CHECK |
| 39 | #define L1_ICACHE_START 0xffa10000 | 37 | #define L1_ICACHE_START 0xffa10000 |
| 40 | #define L1_ICACHE_END 0xffa13fff | 38 | #define L1_ICACHE_END 0xffa13fff |
| @@ -134,13 +132,3 @@ asmlinkage void irq_panic(int reason, struct pt_regs *regs) | |||
| 134 | #endif | 132 | #endif |
| 135 | 133 | ||
| 136 | } | 134 | } |
| 137 | |||
| 138 | #ifdef CONFIG_HARDWARE_PM | ||
| 139 | /* | ||
| 140 | * call the handler of Performance overflow | ||
| 141 | */ | ||
| 142 | asmlinkage void pm_overflow(int irq, struct pt_regs *regs) | ||
| 143 | { | ||
| 144 | pm_overflow_handler(irq, regs); | ||
| 145 | } | ||
| 146 | #endif | ||
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S index 9daf01201e9f..6c5f5f0ea7fe 100644 --- a/arch/blackfin/mach-common/lock.S +++ b/arch/blackfin/mach-common/lock.S | |||
| @@ -160,7 +160,7 @@ ENDPROC(_cache_grab_lock) | |||
| 160 | * R0 - Which way to be locked | 160 | * R0 - Which way to be locked |
| 161 | */ | 161 | */ |
| 162 | 162 | ||
| 163 | ENTRY(_cache_lock) | 163 | ENTRY(_bfin_cache_lock) |
| 164 | 164 | ||
| 165 | [--SP]=( R7:0,P5:0 ); | 165 | [--SP]=( R7:0,P5:0 ); |
| 166 | 166 | ||
| @@ -184,7 +184,7 @@ ENTRY(_cache_lock) | |||
| 184 | 184 | ||
| 185 | ( R7:0,P5:0 ) = [SP++]; | 185 | ( R7:0,P5:0 ) = [SP++]; |
| 186 | RTS; | 186 | RTS; |
| 187 | ENDPROC(_cache_lock) | 187 | ENDPROC(_bfin_cache_lock) |
| 188 | 188 | ||
| 189 | /* Invalidate the Entire Instruction cache by | 189 | /* Invalidate the Entire Instruction cache by |
| 190 | * disabling IMC bit | 190 | * disabling IMC bit |
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c index e28c6af1f415..d3d70fd67c16 100644 --- a/arch/blackfin/mach-common/pm.c +++ b/arch/blackfin/mach-common/pm.c | |||
| @@ -71,7 +71,7 @@ void bfin_pm_suspend_standby_enter(void) | |||
| 71 | gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE); | 71 | gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE); |
| 72 | #endif | 72 | #endif |
| 73 | 73 | ||
| 74 | local_irq_save(flags); | 74 | local_irq_save_hw(flags); |
| 75 | bfin_pm_standby_setup(); | 75 | bfin_pm_standby_setup(); |
| 76 | 76 | ||
| 77 | #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER | 77 | #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER |
| @@ -82,15 +82,19 @@ void bfin_pm_suspend_standby_enter(void) | |||
| 82 | 82 | ||
| 83 | bfin_pm_standby_restore(); | 83 | bfin_pm_standby_restore(); |
| 84 | 84 | ||
| 85 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) | 85 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ |
| 86 | defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x) | ||
| 86 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); | 87 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
| 87 | #if defined(CONFIG_BF52x) | 88 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
| 88 | /* BF52x system reset does not properly reset SIC_IWR1 which | 89 | /* BF52x system reset does not properly reset SIC_IWR1 which |
| 89 | * will screw up the bootrom as it relies on MDMA0/1 waking it | 90 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
| 90 | * up from IDLE instructions. See this report for more info: | 91 | * up from IDLE instructions. See this report for more info: |
| 91 | * http://blackfin.uclinux.org/gf/tracker/4323 | 92 | * http://blackfin.uclinux.org/gf/tracker/4323 |
| 92 | */ | 93 | */ |
| 93 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | 94 | if (ANOMALY_05000435) |
| 95 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | ||
| 96 | else | ||
| 97 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | ||
| 94 | #else | 98 | #else |
| 95 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | 99 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
| 96 | #endif | 100 | #endif |
| @@ -101,7 +105,7 @@ void bfin_pm_suspend_standby_enter(void) | |||
| 101 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); | 105 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
| 102 | #endif | 106 | #endif |
| 103 | 107 | ||
| 104 | local_irq_restore(flags); | 108 | local_irq_restore_hw(flags); |
| 105 | } | 109 | } |
| 106 | 110 | ||
| 107 | int bf53x_suspend_l1_mem(unsigned char *memptr) | 111 | int bf53x_suspend_l1_mem(unsigned char *memptr) |
| @@ -245,12 +249,12 @@ int bfin_pm_suspend_mem_enter(void) | |||
| 245 | wakeup |= GPWE; | 249 | wakeup |= GPWE; |
| 246 | #endif | 250 | #endif |
| 247 | 251 | ||
| 248 | local_irq_save(flags); | 252 | local_irq_save_hw(flags); |
| 249 | 253 | ||
| 250 | ret = blackfin_dma_suspend(); | 254 | ret = blackfin_dma_suspend(); |
| 251 | 255 | ||
| 252 | if (ret) { | 256 | if (ret) { |
| 253 | local_irq_restore(flags); | 257 | local_irq_restore_hw(flags); |
| 254 | kfree(memptr); | 258 | kfree(memptr); |
| 255 | return ret; | 259 | return ret; |
| 256 | } | 260 | } |
| @@ -271,7 +275,7 @@ int bfin_pm_suspend_mem_enter(void) | |||
| 271 | bfin_gpio_pm_hibernate_restore(); | 275 | bfin_gpio_pm_hibernate_restore(); |
| 272 | blackfin_dma_resume(); | 276 | blackfin_dma_resume(); |
| 273 | 277 | ||
| 274 | local_irq_restore(flags); | 278 | local_irq_restore_hw(flags); |
| 275 | kfree(memptr); | 279 | kfree(memptr); |
| 276 | 280 | ||
| 277 | return 0; | 281 | return 0; |
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c new file mode 100644 index 000000000000..77c992847094 --- /dev/null +++ b/arch/blackfin/mach-common/smp.c | |||
| @@ -0,0 +1,476 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/kernel/smp.c | ||
| 3 | * Author: Philippe Gerum <rpm@xenomai.org> | ||
| 4 | * IPI management based on arch/arm/kernel/smp.c. | ||
| 5 | * | ||
| 6 | * Copyright 2007 Analog Devices Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, see the file COPYING, or write | ||
| 20 | * to the Free Software Foundation, Inc., | ||
| 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 22 | */ | ||
| 23 | |||
| 24 | #include <linux/module.h> | ||
| 25 | #include <linux/delay.h> | ||
| 26 | #include <linux/init.h> | ||
| 27 | #include <linux/spinlock.h> | ||
| 28 | #include <linux/sched.h> | ||
| 29 | #include <linux/interrupt.h> | ||
| 30 | #include <linux/cache.h> | ||
| 31 | #include <linux/profile.h> | ||
| 32 | #include <linux/errno.h> | ||
| 33 | #include <linux/mm.h> | ||
| 34 | #include <linux/cpu.h> | ||
| 35 | #include <linux/smp.h> | ||
| 36 | #include <linux/seq_file.h> | ||
| 37 | #include <linux/irq.h> | ||
| 38 | #include <asm/atomic.h> | ||
| 39 | #include <asm/cacheflush.h> | ||
| 40 | #include <asm/mmu_context.h> | ||
| 41 | #include <asm/pgtable.h> | ||
| 42 | #include <asm/pgalloc.h> | ||
| 43 | #include <asm/processor.h> | ||
| 44 | #include <asm/ptrace.h> | ||
| 45 | #include <asm/cpu.h> | ||
| 46 | #include <linux/err.h> | ||
| 47 | |||
| 48 | struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); | ||
| 49 | |||
| 50 | void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, | ||
| 51 | *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, | ||
| 52 | *init_saved_dcplb_fault_addr_coreb; | ||
| 53 | |||
| 54 | cpumask_t cpu_possible_map; | ||
| 55 | EXPORT_SYMBOL(cpu_possible_map); | ||
| 56 | |||
| 57 | cpumask_t cpu_online_map; | ||
| 58 | EXPORT_SYMBOL(cpu_online_map); | ||
| 59 | |||
| 60 | #define BFIN_IPI_RESCHEDULE 0 | ||
| 61 | #define BFIN_IPI_CALL_FUNC 1 | ||
| 62 | #define BFIN_IPI_CPU_STOP 2 | ||
| 63 | |||
| 64 | struct blackfin_flush_data { | ||
| 65 | unsigned long start; | ||
| 66 | unsigned long end; | ||
| 67 | }; | ||
| 68 | |||
| 69 | void *secondary_stack; | ||
| 70 | |||
| 71 | |||
| 72 | struct smp_call_struct { | ||
| 73 | void (*func)(void *info); | ||
| 74 | void *info; | ||
| 75 | int wait; | ||
| 76 | cpumask_t pending; | ||
| 77 | cpumask_t waitmask; | ||
| 78 | }; | ||
| 79 | |||
| 80 | static struct blackfin_flush_data smp_flush_data; | ||
| 81 | |||
| 82 | static DEFINE_SPINLOCK(stop_lock); | ||
| 83 | |||
| 84 | struct ipi_message { | ||
| 85 | struct list_head list; | ||
| 86 | unsigned long type; | ||
| 87 | struct smp_call_struct call_struct; | ||
| 88 | }; | ||
| 89 | |||
| 90 | struct ipi_message_queue { | ||
| 91 | struct list_head head; | ||
| 92 | spinlock_t lock; | ||
| 93 | unsigned long count; | ||
| 94 | }; | ||
| 95 | |||
| 96 | static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue); | ||
| 97 | |||
| 98 | static void ipi_cpu_stop(unsigned int cpu) | ||
| 99 | { | ||
| 100 | spin_lock(&stop_lock); | ||
| 101 | printk(KERN_CRIT "CPU%u: stopping\n", cpu); | ||
| 102 | dump_stack(); | ||
| 103 | spin_unlock(&stop_lock); | ||
| 104 | |||
| 105 | cpu_clear(cpu, cpu_online_map); | ||
| 106 | |||
| 107 | local_irq_disable(); | ||
| 108 | |||
| 109 | while (1) | ||
| 110 | SSYNC(); | ||
| 111 | } | ||
| 112 | |||
| 113 | static void ipi_flush_icache(void *info) | ||
| 114 | { | ||
| 115 | struct blackfin_flush_data *fdata = info; | ||
| 116 | |||
| 117 | /* Invalidate the memory holding the bounds of the flushed region. */ | ||
| 118 | blackfin_dcache_invalidate_range((unsigned long)fdata, | ||
| 119 | (unsigned long)fdata + sizeof(*fdata)); | ||
| 120 | |||
| 121 | blackfin_icache_flush_range(fdata->start, fdata->end); | ||
| 122 | } | ||
| 123 | |||
| 124 | static void ipi_call_function(unsigned int cpu, struct ipi_message *msg) | ||
| 125 | { | ||
| 126 | int wait; | ||
| 127 | void (*func)(void *info); | ||
| 128 | void *info; | ||
| 129 | func = msg->call_struct.func; | ||
| 130 | info = msg->call_struct.info; | ||
| 131 | wait = msg->call_struct.wait; | ||
| 132 | cpu_clear(cpu, msg->call_struct.pending); | ||
| 133 | func(info); | ||
| 134 | if (wait) | ||
| 135 | cpu_clear(cpu, msg->call_struct.waitmask); | ||
| 136 | else | ||
| 137 | kfree(msg); | ||
| 138 | } | ||
| 139 | |||
| 140 | static irqreturn_t ipi_handler(int irq, void *dev_instance) | ||
| 141 | { | ||
| 142 | struct ipi_message *msg, *mg; | ||
| 143 | struct ipi_message_queue *msg_queue; | ||
| 144 | unsigned int cpu = smp_processor_id(); | ||
| 145 | |||
| 146 | platform_clear_ipi(cpu); | ||
| 147 | |||
| 148 | msg_queue = &__get_cpu_var(ipi_msg_queue); | ||
| 149 | msg_queue->count++; | ||
| 150 | |||
| 151 | spin_lock(&msg_queue->lock); | ||
| 152 | list_for_each_entry_safe(msg, mg, &msg_queue->head, list) { | ||
| 153 | list_del(&msg->list); | ||
| 154 | switch (msg->type) { | ||
| 155 | case BFIN_IPI_RESCHEDULE: | ||
| 156 | /* That's the easiest one; leave it to | ||
| 157 | * return_from_int. */ | ||
| 158 | kfree(msg); | ||
| 159 | break; | ||
| 160 | case BFIN_IPI_CALL_FUNC: | ||
| 161 | ipi_call_function(cpu, msg); | ||
| 162 | break; | ||
| 163 | case BFIN_IPI_CPU_STOP: | ||
| 164 | ipi_cpu_stop(cpu); | ||
| 165 | kfree(msg); | ||
| 166 | break; | ||
| 167 | default: | ||
| 168 | printk(KERN_CRIT "CPU%u: Unknown IPI message \ | ||
| 169 | 0x%lx\n", cpu, msg->type); | ||
| 170 | kfree(msg); | ||
| 171 | break; | ||
| 172 | } | ||
| 173 | } | ||
| 174 | spin_unlock(&msg_queue->lock); | ||
| 175 | return IRQ_HANDLED; | ||
| 176 | } | ||
| 177 | |||
| 178 | static void ipi_queue_init(void) | ||
| 179 | { | ||
| 180 | unsigned int cpu; | ||
| 181 | struct ipi_message_queue *msg_queue; | ||
| 182 | for_each_possible_cpu(cpu) { | ||
| 183 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | ||
| 184 | INIT_LIST_HEAD(&msg_queue->head); | ||
| 185 | spin_lock_init(&msg_queue->lock); | ||
| 186 | msg_queue->count = 0; | ||
| 187 | } | ||
| 188 | } | ||
| 189 | |||
| 190 | int smp_call_function(void (*func)(void *info), void *info, int wait) | ||
| 191 | { | ||
| 192 | unsigned int cpu; | ||
| 193 | cpumask_t callmap; | ||
| 194 | unsigned long flags; | ||
| 195 | struct ipi_message_queue *msg_queue; | ||
| 196 | struct ipi_message *msg; | ||
| 197 | |||
| 198 | callmap = cpu_online_map; | ||
| 199 | cpu_clear(smp_processor_id(), callmap); | ||
| 200 | if (cpus_empty(callmap)) | ||
| 201 | return 0; | ||
| 202 | |||
| 203 | msg = kmalloc(sizeof(*msg), GFP_ATOMIC); | ||
| 204 | INIT_LIST_HEAD(&msg->list); | ||
| 205 | msg->call_struct.func = func; | ||
| 206 | msg->call_struct.info = info; | ||
| 207 | msg->call_struct.wait = wait; | ||
| 208 | msg->call_struct.pending = callmap; | ||
| 209 | msg->call_struct.waitmask = callmap; | ||
| 210 | msg->type = BFIN_IPI_CALL_FUNC; | ||
| 211 | |||
| 212 | for_each_cpu_mask(cpu, callmap) { | ||
| 213 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | ||
| 214 | spin_lock_irqsave(&msg_queue->lock, flags); | ||
| 215 | list_add(&msg->list, &msg_queue->head); | ||
| 216 | spin_unlock_irqrestore(&msg_queue->lock, flags); | ||
| 217 | platform_send_ipi_cpu(cpu); | ||
| 218 | } | ||
| 219 | if (wait) { | ||
| 220 | while (!cpus_empty(msg->call_struct.waitmask)) | ||
| 221 | blackfin_dcache_invalidate_range( | ||
| 222 | (unsigned long)(&msg->call_struct.waitmask), | ||
| 223 | (unsigned long)(&msg->call_struct.waitmask)); | ||
| 224 | kfree(msg); | ||
| 225 | } | ||
| 226 | return 0; | ||
| 227 | } | ||
| 228 | EXPORT_SYMBOL_GPL(smp_call_function); | ||
| 229 | |||
| 230 | int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, | ||
| 231 | int wait) | ||
| 232 | { | ||
| 233 | unsigned int cpu = cpuid; | ||
| 234 | cpumask_t callmap; | ||
| 235 | unsigned long flags; | ||
| 236 | struct ipi_message_queue *msg_queue; | ||
| 237 | struct ipi_message *msg; | ||
| 238 | |||
| 239 | if (cpu_is_offline(cpu)) | ||
| 240 | return 0; | ||
| 241 | cpus_clear(callmap); | ||
| 242 | cpu_set(cpu, callmap); | ||
| 243 | |||
| 244 | msg = kmalloc(sizeof(*msg), GFP_ATOMIC); | ||
| 245 | INIT_LIST_HEAD(&msg->list); | ||
| 246 | msg->call_struct.func = func; | ||
| 247 | msg->call_struct.info = info; | ||
| 248 | msg->call_struct.wait = wait; | ||
| 249 | msg->call_struct.pending = callmap; | ||
| 250 | msg->call_struct.waitmask = callmap; | ||
| 251 | msg->type = BFIN_IPI_CALL_FUNC; | ||
| 252 | |||
| 253 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | ||
| 254 | spin_lock_irqsave(&msg_queue->lock, flags); | ||
| 255 | list_add(&msg->list, &msg_queue->head); | ||
| 256 | spin_unlock_irqrestore(&msg_queue->lock, flags); | ||
| 257 | platform_send_ipi_cpu(cpu); | ||
| 258 | |||
| 259 | if (wait) { | ||
| 260 | while (!cpus_empty(msg->call_struct.waitmask)) | ||
| 261 | blackfin_dcache_invalidate_range( | ||
| 262 | (unsigned long)(&msg->call_struct.waitmask), | ||
| 263 | (unsigned long)(&msg->call_struct.waitmask)); | ||
| 264 | kfree(msg); | ||
| 265 | } | ||
| 266 | return 0; | ||
| 267 | } | ||
| 268 | EXPORT_SYMBOL_GPL(smp_call_function_single); | ||
| 269 | |||
| 270 | void smp_send_reschedule(int cpu) | ||
| 271 | { | ||
| 272 | unsigned long flags; | ||
| 273 | struct ipi_message_queue *msg_queue; | ||
| 274 | struct ipi_message *msg; | ||
| 275 | |||
| 276 | if (cpu_is_offline(cpu)) | ||
| 277 | return; | ||
| 278 | |||
| 279 | msg = kmalloc(sizeof(*msg), GFP_ATOMIC); | ||
| 280 | memset(msg, 0, sizeof(msg)); | ||
| 281 | INIT_LIST_HEAD(&msg->list); | ||
| 282 | msg->type = BFIN_IPI_RESCHEDULE; | ||
| 283 | |||
| 284 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | ||
| 285 | spin_lock_irqsave(&msg_queue->lock, flags); | ||
| 286 | list_add(&msg->list, &msg_queue->head); | ||
| 287 | spin_unlock_irqrestore(&msg_queue->lock, flags); | ||
| 288 | platform_send_ipi_cpu(cpu); | ||
| 289 | |||
| 290 | return; | ||
| 291 | } | ||
| 292 | |||
| 293 | void smp_send_stop(void) | ||
| 294 | { | ||
| 295 | unsigned int cpu; | ||
| 296 | cpumask_t callmap; | ||
| 297 | unsigned long flags; | ||
| 298 | struct ipi_message_queue *msg_queue; | ||
| 299 | struct ipi_message *msg; | ||
| 300 | |||
| 301 | callmap = cpu_online_map; | ||
| 302 | cpu_clear(smp_processor_id(), callmap); | ||
| 303 | if (cpus_empty(callmap)) | ||
| 304 | return; | ||
| 305 | |||
| 306 | msg = kmalloc(sizeof(*msg), GFP_ATOMIC); | ||
| 307 | memset(msg, 0, sizeof(msg)); | ||
| 308 | INIT_LIST_HEAD(&msg->list); | ||
| 309 | msg->type = BFIN_IPI_CPU_STOP; | ||
| 310 | |||
| 311 | for_each_cpu_mask(cpu, callmap) { | ||
| 312 | msg_queue = &per_cpu(ipi_msg_queue, cpu); | ||
| 313 | spin_lock_irqsave(&msg_queue->lock, flags); | ||
| 314 | list_add(&msg->list, &msg_queue->head); | ||
| 315 | spin_unlock_irqrestore(&msg_queue->lock, flags); | ||
| 316 | platform_send_ipi_cpu(cpu); | ||
| 317 | } | ||
| 318 | return; | ||
| 319 | } | ||
| 320 | |||
| 321 | int __cpuinit __cpu_up(unsigned int cpu) | ||
| 322 | { | ||
| 323 | struct task_struct *idle; | ||
| 324 | int ret; | ||
| 325 | |||
| 326 | idle = fork_idle(cpu); | ||
| 327 | if (IS_ERR(idle)) { | ||
| 328 | printk(KERN_ERR "CPU%u: fork() failed\n", cpu); | ||
| 329 | return PTR_ERR(idle); | ||
| 330 | } | ||
| 331 | |||
| 332 | secondary_stack = task_stack_page(idle) + THREAD_SIZE; | ||
| 333 | smp_wmb(); | ||
| 334 | |||
| 335 | ret = platform_boot_secondary(cpu, idle); | ||
| 336 | |||
| 337 | if (ret) { | ||
| 338 | cpu_clear(cpu, cpu_present_map); | ||
| 339 | printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret); | ||
| 340 | free_task(idle); | ||
| 341 | } else | ||
| 342 | cpu_set(cpu, cpu_online_map); | ||
| 343 | |||
| 344 | secondary_stack = NULL; | ||
| 345 | |||
| 346 | return ret; | ||
| 347 | } | ||
| 348 | |||
| 349 | static void __cpuinit setup_secondary(unsigned int cpu) | ||
| 350 | { | ||
| 351 | #if !(defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)) | ||
| 352 | struct irq_desc *timer_desc; | ||
| 353 | #endif | ||
| 354 | unsigned long ilat; | ||
| 355 | |||
| 356 | bfin_write_IMASK(0); | ||
| 357 | CSYNC(); | ||
| 358 | ilat = bfin_read_ILAT(); | ||
| 359 | CSYNC(); | ||
| 360 | bfin_write_ILAT(ilat); | ||
| 361 | CSYNC(); | ||
| 362 | |||
| 363 | /* Reserve the PDA space for the secondary CPU. */ | ||
| 364 | reserve_pda(); | ||
| 365 | |||
| 366 | /* Enable interrupt levels IVG7-15. IARs have been already | ||
| 367 | * programmed by the boot CPU. */ | ||
| 368 | bfin_irq_flags |= IMASK_IVG15 | | ||
| 369 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | ||
| 370 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | ||
| 371 | |||
| 372 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE) | ||
| 373 | /* Power down the core timer, just to play safe. */ | ||
| 374 | bfin_write_TCNTL(0); | ||
| 375 | |||
| 376 | /* system timer0 has been setup by CoreA. */ | ||
| 377 | #else | ||
| 378 | timer_desc = irq_desc + IRQ_CORETMR; | ||
| 379 | setup_core_timer(); | ||
| 380 | timer_desc->chip->enable(IRQ_CORETMR); | ||
| 381 | #endif | ||
| 382 | } | ||
| 383 | |||
| 384 | void __cpuinit secondary_start_kernel(void) | ||
| 385 | { | ||
| 386 | unsigned int cpu = smp_processor_id(); | ||
| 387 | struct mm_struct *mm = &init_mm; | ||
| 388 | |||
| 389 | if (_bfin_swrst & SWRST_DBL_FAULT_B) { | ||
| 390 | printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n"); | ||
| 391 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | ||
| 392 | printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", | ||
| 393 | (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb); | ||
| 394 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb); | ||
| 395 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb); | ||
| 396 | #endif | ||
| 397 | printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", | ||
| 398 | init_retx_coreb); | ||
| 399 | } | ||
| 400 | |||
| 401 | /* | ||
| 402 | * We want the D-cache to be enabled early, in case the atomic | ||
| 403 | * support code emulates cache coherence (see | ||
| 404 | * __ARCH_SYNC_CORE_DCACHE). | ||
| 405 | */ | ||
| 406 | init_exception_vectors(); | ||
| 407 | |||
| 408 | bfin_setup_caches(cpu); | ||
| 409 | |||
| 410 | local_irq_disable(); | ||
| 411 | |||
| 412 | /* Attach the new idle task to the global mm. */ | ||
| 413 | atomic_inc(&mm->mm_users); | ||
| 414 | atomic_inc(&mm->mm_count); | ||
| 415 | current->active_mm = mm; | ||
| 416 | BUG_ON(current->mm); /* Can't be, but better be safe than sorry. */ | ||
| 417 | |||
| 418 | preempt_disable(); | ||
| 419 | |||
| 420 | setup_secondary(cpu); | ||
| 421 | |||
| 422 | local_irq_enable(); | ||
| 423 | |||
| 424 | platform_secondary_init(cpu); | ||
| 425 | |||
| 426 | cpu_idle(); | ||
| 427 | } | ||
| 428 | |||
| 429 | void __init smp_prepare_boot_cpu(void) | ||
| 430 | { | ||
| 431 | } | ||
| 432 | |||
| 433 | void __init smp_prepare_cpus(unsigned int max_cpus) | ||
| 434 | { | ||
| 435 | platform_prepare_cpus(max_cpus); | ||
| 436 | ipi_queue_init(); | ||
| 437 | platform_request_ipi(&ipi_handler); | ||
| 438 | } | ||
| 439 | |||
| 440 | void __init smp_cpus_done(unsigned int max_cpus) | ||
| 441 | { | ||
| 442 | unsigned long bogosum = 0; | ||
| 443 | unsigned int cpu; | ||
| 444 | |||
| 445 | for_each_online_cpu(cpu) | ||
| 446 | bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy; | ||
| 447 | |||
| 448 | printk(KERN_INFO "SMP: Total of %d processors activated " | ||
| 449 | "(%lu.%02lu BogoMIPS).\n", | ||
| 450 | num_online_cpus(), | ||
| 451 | bogosum / (500000/HZ), | ||
| 452 | (bogosum / (5000/HZ)) % 100); | ||
| 453 | } | ||
| 454 | |||
| 455 | void smp_icache_flush_range_others(unsigned long start, unsigned long end) | ||
| 456 | { | ||
| 457 | smp_flush_data.start = start; | ||
| 458 | smp_flush_data.end = end; | ||
| 459 | |||
| 460 | if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1)) | ||
| 461 | printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); | ||
| 462 | } | ||
| 463 | EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); | ||
| 464 | |||
| 465 | #ifdef __ARCH_SYNC_CORE_DCACHE | ||
| 466 | unsigned long barrier_mask __attribute__ ((__section__(".l2.bss"))); | ||
| 467 | |||
| 468 | void resync_core_dcache(void) | ||
| 469 | { | ||
| 470 | unsigned int cpu = get_cpu(); | ||
| 471 | blackfin_invalidate_entire_dcache(); | ||
| 472 | ++per_cpu(cpu_data, cpu).dcache_invld_count; | ||
| 473 | put_cpu(); | ||
| 474 | } | ||
| 475 | EXPORT_SYMBOL(resync_core_dcache); | ||
| 476 | #endif | ||
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index bc240abb8745..d0532b72bba5 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c | |||
| @@ -31,7 +31,8 @@ | |||
| 31 | #include <linux/bootmem.h> | 31 | #include <linux/bootmem.h> |
| 32 | #include <linux/uaccess.h> | 32 | #include <linux/uaccess.h> |
| 33 | #include <asm/bfin-global.h> | 33 | #include <asm/bfin-global.h> |
| 34 | #include <asm/l1layout.h> | 34 | #include <asm/pda.h> |
| 35 | #include <asm/cplbinit.h> | ||
| 35 | #include "blackfin_sram.h" | 36 | #include "blackfin_sram.h" |
| 36 | 37 | ||
| 37 | /* | 38 | /* |
| @@ -53,6 +54,11 @@ static unsigned long empty_bad_page; | |||
| 53 | 54 | ||
| 54 | unsigned long empty_zero_page; | 55 | unsigned long empty_zero_page; |
| 55 | 56 | ||
| 57 | extern unsigned long exception_stack[NR_CPUS][1024]; | ||
| 58 | |||
| 59 | struct blackfin_pda cpu_pda[NR_CPUS]; | ||
| 60 | EXPORT_SYMBOL(cpu_pda); | ||
| 61 | |||
| 56 | /* | 62 | /* |
| 57 | * paging_init() continues the virtual memory environment setup which | 63 | * paging_init() continues the virtual memory environment setup which |
| 58 | * was begun by the code in arch/head.S. | 64 | * was begun by the code in arch/head.S. |
| @@ -98,6 +104,32 @@ void __init paging_init(void) | |||
| 98 | } | 104 | } |
| 99 | } | 105 | } |
| 100 | 106 | ||
| 107 | asmlinkage void init_pda(void) | ||
| 108 | { | ||
| 109 | unsigned int cpu = raw_smp_processor_id(); | ||
| 110 | |||
| 111 | /* Initialize the PDA fields holding references to other parts | ||
| 112 | of the memory. The content of such memory is still | ||
| 113 | undefined at the time of the call, we are only setting up | ||
| 114 | valid pointers to it. */ | ||
| 115 | memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu])); | ||
| 116 | |||
| 117 | cpu_pda[0].next = &cpu_pda[1]; | ||
| 118 | cpu_pda[1].next = &cpu_pda[0]; | ||
| 119 | |||
| 120 | cpu_pda[cpu].ex_stack = exception_stack[cpu + 1]; | ||
| 121 | |||
| 122 | #ifdef CONFIG_SMP | ||
| 123 | cpu_pda[cpu].imask = 0x1f; | ||
| 124 | #endif | ||
| 125 | } | ||
| 126 | |||
| 127 | void __cpuinit reserve_pda(void) | ||
| 128 | { | ||
| 129 | printk(KERN_INFO "PDA for CPU%u reserved at %p\n", smp_processor_id(), | ||
| 130 | &cpu_pda[smp_processor_id()]); | ||
| 131 | } | ||
| 132 | |||
| 101 | void __init mem_init(void) | 133 | void __init mem_init(void) |
| 102 | { | 134 | { |
| 103 | unsigned int codek = 0, datak = 0, initk = 0; | 135 | unsigned int codek = 0, datak = 0, initk = 0; |
| @@ -141,21 +173,13 @@ void __init mem_init(void) | |||
| 141 | 173 | ||
| 142 | static int __init sram_init(void) | 174 | static int __init sram_init(void) |
| 143 | { | 175 | { |
| 144 | unsigned long tmp; | ||
| 145 | |||
| 146 | /* Initialize the blackfin L1 Memory. */ | 176 | /* Initialize the blackfin L1 Memory. */ |
| 147 | bfin_sram_init(); | 177 | bfin_sram_init(); |
| 148 | 178 | ||
| 149 | /* Allocate this once; never free it. We assume this gives us a | 179 | /* Reserve the PDA space for the boot CPU right after we |
| 150 | pointer to the start of L1 scratchpad memory; panic if it | 180 | * initialized the scratch memory allocator. |
| 151 | doesn't. */ | 181 | */ |
| 152 | tmp = (unsigned long)l1sram_alloc(sizeof(struct l1_scratch_task_info)); | 182 | reserve_pda(); |
| 153 | if (tmp != (unsigned long)L1_SCRATCH_TASK_INFO) { | ||
| 154 | printk(KERN_EMERG "mem_init(): Did not get the right address from l1sram_alloc: %08lx != %08lx\n", | ||
| 155 | tmp, (unsigned long)L1_SCRATCH_TASK_INFO); | ||
| 156 | panic("No L1, time to give up\n"); | ||
| 157 | } | ||
| 158 | |||
| 159 | return 0; | 183 | return 0; |
| 160 | } | 184 | } |
| 161 | pure_initcall(sram_init); | 185 | pure_initcall(sram_init); |
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c index cc6f336e7313..834cab7438a8 100644 --- a/arch/blackfin/mm/sram-alloc.c +++ b/arch/blackfin/mm/sram-alloc.c | |||
| @@ -39,10 +39,13 @@ | |||
| 39 | #include <linux/spinlock.h> | 39 | #include <linux/spinlock.h> |
| 40 | #include <linux/rtc.h> | 40 | #include <linux/rtc.h> |
| 41 | #include <asm/blackfin.h> | 41 | #include <asm/blackfin.h> |
| 42 | #include <asm/mem_map.h> | ||
| 42 | #include "blackfin_sram.h" | 43 | #include "blackfin_sram.h" |
| 43 | 44 | ||
| 44 | static spinlock_t l1sram_lock, l1_data_sram_lock, l1_inst_sram_lock; | 45 | static DEFINE_PER_CPU(spinlock_t, l1sram_lock) ____cacheline_aligned_in_smp; |
| 45 | static spinlock_t l2_sram_lock; | 46 | static DEFINE_PER_CPU(spinlock_t, l1_data_sram_lock) ____cacheline_aligned_in_smp; |
| 47 | static DEFINE_PER_CPU(spinlock_t, l1_inst_sram_lock) ____cacheline_aligned_in_smp; | ||
| 48 | static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp; | ||
| 46 | 49 | ||
| 47 | /* the data structure for L1 scratchpad and DATA SRAM */ | 50 | /* the data structure for L1 scratchpad and DATA SRAM */ |
| 48 | struct sram_piece { | 51 | struct sram_piece { |
| @@ -52,18 +55,22 @@ struct sram_piece { | |||
| 52 | struct sram_piece *next; | 55 | struct sram_piece *next; |
| 53 | }; | 56 | }; |
| 54 | 57 | ||
| 55 | static struct sram_piece free_l1_ssram_head, used_l1_ssram_head; | 58 | static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head); |
| 59 | static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head); | ||
| 56 | 60 | ||
| 57 | #if L1_DATA_A_LENGTH != 0 | 61 | #if L1_DATA_A_LENGTH != 0 |
| 58 | static struct sram_piece free_l1_data_A_sram_head, used_l1_data_A_sram_head; | 62 | static DEFINE_PER_CPU(struct sram_piece, free_l1_data_A_sram_head); |
| 63 | static DEFINE_PER_CPU(struct sram_piece, used_l1_data_A_sram_head); | ||
| 59 | #endif | 64 | #endif |
| 60 | 65 | ||
| 61 | #if L1_DATA_B_LENGTH != 0 | 66 | #if L1_DATA_B_LENGTH != 0 |
| 62 | static struct sram_piece free_l1_data_B_sram_head, used_l1_data_B_sram_head; | 67 | static DEFINE_PER_CPU(struct sram_piece, free_l1_data_B_sram_head); |
| 68 | static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head); | ||
| 63 | #endif | 69 | #endif |
| 64 | 70 | ||
| 65 | #if L1_CODE_LENGTH != 0 | 71 | #if L1_CODE_LENGTH != 0 |
| 66 | static struct sram_piece free_l1_inst_sram_head, used_l1_inst_sram_head; | 72 | static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head); |
| 73 | static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head); | ||
| 67 | #endif | 74 | #endif |
| 68 | 75 | ||
| 69 | #if L2_LENGTH != 0 | 76 | #if L2_LENGTH != 0 |
| @@ -75,102 +82,117 @@ static struct kmem_cache *sram_piece_cache; | |||
| 75 | /* L1 Scratchpad SRAM initialization function */ | 82 | /* L1 Scratchpad SRAM initialization function */ |
| 76 | static void __init l1sram_init(void) | 83 | static void __init l1sram_init(void) |
| 77 | { | 84 | { |
| 78 | free_l1_ssram_head.next = | 85 | unsigned int cpu; |
| 79 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); | 86 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { |
| 80 | if (!free_l1_ssram_head.next) { | 87 | per_cpu(free_l1_ssram_head, cpu).next = |
| 81 | printk(KERN_INFO "Failed to initialize Scratchpad data SRAM\n"); | 88 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); |
| 82 | return; | 89 | if (!per_cpu(free_l1_ssram_head, cpu).next) { |
| 90 | printk(KERN_INFO "Fail to initialize Scratchpad data SRAM.\n"); | ||
| 91 | return; | ||
| 92 | } | ||
| 93 | |||
| 94 | per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu); | ||
| 95 | per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH; | ||
| 96 | per_cpu(free_l1_ssram_head, cpu).next->pid = 0; | ||
| 97 | per_cpu(free_l1_ssram_head, cpu).next->next = NULL; | ||
| 98 | |||
| 99 | per_cpu(used_l1_ssram_head, cpu).next = NULL; | ||
| 100 | |||
| 101 | /* mutex initialize */ | ||
| 102 | spin_lock_init(&per_cpu(l1sram_lock, cpu)); | ||
| 103 | printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n", | ||
| 104 | L1_SCRATCH_LENGTH >> 10); | ||
| 83 | } | 105 | } |
| 84 | |||
| 85 | free_l1_ssram_head.next->paddr = (void *)L1_SCRATCH_START; | ||
| 86 | free_l1_ssram_head.next->size = L1_SCRATCH_LENGTH; | ||
| 87 | free_l1_ssram_head.next->pid = 0; | ||
| 88 | free_l1_ssram_head.next->next = NULL; | ||
| 89 | |||
| 90 | used_l1_ssram_head.next = NULL; | ||
| 91 | |||
| 92 | /* mutex initialize */ | ||
| 93 | spin_lock_init(&l1sram_lock); | ||
| 94 | |||
| 95 | printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n", | ||
| 96 | L1_SCRATCH_LENGTH >> 10); | ||
| 97 | } | 106 | } |
| 98 | 107 | ||
| 99 | static void __init l1_data_sram_init(void) | 108 | static void __init l1_data_sram_init(void) |
| 100 | { | 109 | { |
| 110 | #if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0 | ||
| 111 | unsigned int cpu; | ||
| 112 | #endif | ||
| 101 | #if L1_DATA_A_LENGTH != 0 | 113 | #if L1_DATA_A_LENGTH != 0 |
| 102 | free_l1_data_A_sram_head.next = | 114 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { |
| 103 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); | 115 | per_cpu(free_l1_data_A_sram_head, cpu).next = |
| 104 | if (!free_l1_data_A_sram_head.next) { | 116 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); |
| 105 | printk(KERN_INFO "Failed to initialize L1 Data A SRAM\n"); | 117 | if (!per_cpu(free_l1_data_A_sram_head, cpu).next) { |
| 106 | return; | 118 | printk(KERN_INFO "Fail to initialize L1 Data A SRAM.\n"); |
| 119 | return; | ||
| 120 | } | ||
| 121 | |||
| 122 | per_cpu(free_l1_data_A_sram_head, cpu).next->paddr = | ||
| 123 | (void *)get_l1_data_a_start_cpu(cpu) + (_ebss_l1 - _sdata_l1); | ||
| 124 | per_cpu(free_l1_data_A_sram_head, cpu).next->size = | ||
| 125 | L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1); | ||
| 126 | per_cpu(free_l1_data_A_sram_head, cpu).next->pid = 0; | ||
| 127 | per_cpu(free_l1_data_A_sram_head, cpu).next->next = NULL; | ||
| 128 | |||
| 129 | per_cpu(used_l1_data_A_sram_head, cpu).next = NULL; | ||
| 130 | |||
| 131 | printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n", | ||
| 132 | L1_DATA_A_LENGTH >> 10, | ||
| 133 | per_cpu(free_l1_data_A_sram_head, cpu).next->size >> 10); | ||
| 107 | } | 134 | } |
| 108 | |||
| 109 | free_l1_data_A_sram_head.next->paddr = | ||
| 110 | (void *)L1_DATA_A_START + (_ebss_l1 - _sdata_l1); | ||
| 111 | free_l1_data_A_sram_head.next->size = | ||
| 112 | L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1); | ||
| 113 | free_l1_data_A_sram_head.next->pid = 0; | ||
| 114 | free_l1_data_A_sram_head.next->next = NULL; | ||
| 115 | |||
| 116 | used_l1_data_A_sram_head.next = NULL; | ||
| 117 | |||
| 118 | printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n", | ||
| 119 | L1_DATA_A_LENGTH >> 10, | ||
| 120 | free_l1_data_A_sram_head.next->size >> 10); | ||
| 121 | #endif | 135 | #endif |
| 122 | #if L1_DATA_B_LENGTH != 0 | 136 | #if L1_DATA_B_LENGTH != 0 |
| 123 | free_l1_data_B_sram_head.next = | 137 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { |
| 124 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); | 138 | per_cpu(free_l1_data_B_sram_head, cpu).next = |
| 125 | if (!free_l1_data_B_sram_head.next) { | 139 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); |
| 126 | printk(KERN_INFO "Failed to initialize L1 Data B SRAM\n"); | 140 | if (!per_cpu(free_l1_data_B_sram_head, cpu).next) { |
| 127 | return; | 141 | printk(KERN_INFO "Fail to initialize L1 Data B SRAM.\n"); |
| 142 | return; | ||
| 143 | } | ||
| 144 | |||
| 145 | per_cpu(free_l1_data_B_sram_head, cpu).next->paddr = | ||
| 146 | (void *)get_l1_data_b_start_cpu(cpu) + (_ebss_b_l1 - _sdata_b_l1); | ||
| 147 | per_cpu(free_l1_data_B_sram_head, cpu).next->size = | ||
| 148 | L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1); | ||
| 149 | per_cpu(free_l1_data_B_sram_head, cpu).next->pid = 0; | ||
| 150 | per_cpu(free_l1_data_B_sram_head, cpu).next->next = NULL; | ||
| 151 | |||
| 152 | per_cpu(used_l1_data_B_sram_head, cpu).next = NULL; | ||
| 153 | |||
| 154 | printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n", | ||
| 155 | L1_DATA_B_LENGTH >> 10, | ||
| 156 | per_cpu(free_l1_data_B_sram_head, cpu).next->size >> 10); | ||
| 157 | /* mutex initialize */ | ||
| 128 | } | 158 | } |
| 129 | |||
| 130 | free_l1_data_B_sram_head.next->paddr = | ||
| 131 | (void *)L1_DATA_B_START + (_ebss_b_l1 - _sdata_b_l1); | ||
| 132 | free_l1_data_B_sram_head.next->size = | ||
| 133 | L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1); | ||
| 134 | free_l1_data_B_sram_head.next->pid = 0; | ||
| 135 | free_l1_data_B_sram_head.next->next = NULL; | ||
| 136 | |||
| 137 | used_l1_data_B_sram_head.next = NULL; | ||
| 138 | |||
| 139 | printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n", | ||
| 140 | L1_DATA_B_LENGTH >> 10, | ||
| 141 | free_l1_data_B_sram_head.next->size >> 10); | ||
| 142 | #endif | 159 | #endif |
| 143 | 160 | ||
| 144 | /* mutex initialize */ | 161 | #if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0 |
| 145 | spin_lock_init(&l1_data_sram_lock); | 162 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) |
| 163 | spin_lock_init(&per_cpu(l1_data_sram_lock, cpu)); | ||
| 164 | #endif | ||
| 146 | } | 165 | } |
| 147 | 166 | ||
| 148 | static void __init l1_inst_sram_init(void) | 167 | static void __init l1_inst_sram_init(void) |
| 149 | { | 168 | { |
| 150 | #if L1_CODE_LENGTH != 0 | 169 | #if L1_CODE_LENGTH != 0 |
| 151 | free_l1_inst_sram_head.next = | 170 | unsigned int cpu; |
| 152 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); | 171 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { |
| 153 | if (!free_l1_inst_sram_head.next) { | 172 | per_cpu(free_l1_inst_sram_head, cpu).next = |
| 154 | printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n"); | 173 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); |
| 155 | return; | 174 | if (!per_cpu(free_l1_inst_sram_head, cpu).next) { |
| 175 | printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n"); | ||
| 176 | return; | ||
| 177 | } | ||
| 178 | |||
| 179 | per_cpu(free_l1_inst_sram_head, cpu).next->paddr = | ||
| 180 | (void *)get_l1_code_start_cpu(cpu) + (_etext_l1 - _stext_l1); | ||
| 181 | per_cpu(free_l1_inst_sram_head, cpu).next->size = | ||
| 182 | L1_CODE_LENGTH - (_etext_l1 - _stext_l1); | ||
| 183 | per_cpu(free_l1_inst_sram_head, cpu).next->pid = 0; | ||
| 184 | per_cpu(free_l1_inst_sram_head, cpu).next->next = NULL; | ||
| 185 | |||
| 186 | per_cpu(used_l1_inst_sram_head, cpu).next = NULL; | ||
| 187 | |||
| 188 | printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n", | ||
| 189 | L1_CODE_LENGTH >> 10, | ||
| 190 | per_cpu(free_l1_inst_sram_head, cpu).next->size >> 10); | ||
| 191 | |||
| 192 | /* mutex initialize */ | ||
| 193 | spin_lock_init(&per_cpu(l1_inst_sram_lock, cpu)); | ||
| 156 | } | 194 | } |
| 157 | |||
| 158 | free_l1_inst_sram_head.next->paddr = | ||
| 159 | (void *)L1_CODE_START + (_etext_l1 - _stext_l1); | ||
| 160 | free_l1_inst_sram_head.next->size = | ||
| 161 | L1_CODE_LENGTH - (_etext_l1 - _stext_l1); | ||
| 162 | free_l1_inst_sram_head.next->pid = 0; | ||
| 163 | free_l1_inst_sram_head.next->next = NULL; | ||
| 164 | |||
| 165 | used_l1_inst_sram_head.next = NULL; | ||
| 166 | |||
| 167 | printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n", | ||
| 168 | L1_CODE_LENGTH >> 10, | ||
| 169 | free_l1_inst_sram_head.next->size >> 10); | ||
| 170 | #endif | 195 | #endif |
| 171 | |||
| 172 | /* mutex initialize */ | ||
| 173 | spin_lock_init(&l1_inst_sram_lock); | ||
| 174 | } | 196 | } |
| 175 | 197 | ||
| 176 | static void __init l2_sram_init(void) | 198 | static void __init l2_sram_init(void) |
| @@ -179,7 +201,7 @@ static void __init l2_sram_init(void) | |||
| 179 | free_l2_sram_head.next = | 201 | free_l2_sram_head.next = |
| 180 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); | 202 | kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); |
| 181 | if (!free_l2_sram_head.next) { | 203 | if (!free_l2_sram_head.next) { |
| 182 | printk(KERN_INFO "Failed to initialize L2 SRAM\n"); | 204 | printk(KERN_INFO "Fail to initialize L2 SRAM.\n"); |
| 183 | return; | 205 | return; |
| 184 | } | 206 | } |
| 185 | 207 | ||
| @@ -200,6 +222,7 @@ static void __init l2_sram_init(void) | |||
| 200 | /* mutex initialize */ | 222 | /* mutex initialize */ |
| 201 | spin_lock_init(&l2_sram_lock); | 223 | spin_lock_init(&l2_sram_lock); |
| 202 | } | 224 | } |
| 225 | |||
| 203 | void __init bfin_sram_init(void) | 226 | void __init bfin_sram_init(void) |
| 204 | { | 227 | { |
| 205 | sram_piece_cache = kmem_cache_create("sram_piece_cache", | 228 | sram_piece_cache = kmem_cache_create("sram_piece_cache", |
| @@ -353,20 +376,20 @@ int sram_free(const void *addr) | |||
| 353 | { | 376 | { |
| 354 | 377 | ||
| 355 | #if L1_CODE_LENGTH != 0 | 378 | #if L1_CODE_LENGTH != 0 |
| 356 | if (addr >= (void *)L1_CODE_START | 379 | if (addr >= (void *)get_l1_code_start() |
| 357 | && addr < (void *)(L1_CODE_START + L1_CODE_LENGTH)) | 380 | && addr < (void *)(get_l1_code_start() + L1_CODE_LENGTH)) |
| 358 | return l1_inst_sram_free(addr); | 381 | return l1_inst_sram_free(addr); |
| 359 | else | 382 | else |
| 360 | #endif | 383 | #endif |
| 361 | #if L1_DATA_A_LENGTH != 0 | 384 | #if L1_DATA_A_LENGTH != 0 |
| 362 | if (addr >= (void *)L1_DATA_A_START | 385 | if (addr >= (void *)get_l1_data_a_start() |
| 363 | && addr < (void *)(L1_DATA_A_START + L1_DATA_A_LENGTH)) | 386 | && addr < (void *)(get_l1_data_a_start() + L1_DATA_A_LENGTH)) |
| 364 | return l1_data_A_sram_free(addr); | 387 | return l1_data_A_sram_free(addr); |
| 365 | else | 388 | else |
| 366 | #endif | 389 | #endif |
| 367 | #if L1_DATA_B_LENGTH != 0 | 390 | #if L1_DATA_B_LENGTH != 0 |
| 368 | if (addr >= (void *)L1_DATA_B_START | 391 | if (addr >= (void *)get_l1_data_b_start() |
| 369 | && addr < (void *)(L1_DATA_B_START + L1_DATA_B_LENGTH)) | 392 | && addr < (void *)(get_l1_data_b_start() + L1_DATA_B_LENGTH)) |
| 370 | return l1_data_B_sram_free(addr); | 393 | return l1_data_B_sram_free(addr); |
| 371 | else | 394 | else |
| 372 | #endif | 395 | #endif |
| @@ -384,17 +407,20 @@ void *l1_data_A_sram_alloc(size_t size) | |||
| 384 | { | 407 | { |
| 385 | unsigned long flags; | 408 | unsigned long flags; |
| 386 | void *addr = NULL; | 409 | void *addr = NULL; |
| 410 | unsigned int cpu; | ||
| 387 | 411 | ||
| 412 | cpu = get_cpu(); | ||
| 388 | /* add mutex operation */ | 413 | /* add mutex operation */ |
| 389 | spin_lock_irqsave(&l1_data_sram_lock, flags); | 414 | spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); |
| 390 | 415 | ||
| 391 | #if L1_DATA_A_LENGTH != 0 | 416 | #if L1_DATA_A_LENGTH != 0 |
| 392 | addr = _sram_alloc(size, &free_l1_data_A_sram_head, | 417 | addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu), |
| 393 | &used_l1_data_A_sram_head); | 418 | &per_cpu(used_l1_data_A_sram_head, cpu)); |
| 394 | #endif | 419 | #endif |
| 395 | 420 | ||
| 396 | /* add mutex operation */ | 421 | /* add mutex operation */ |
| 397 | spin_unlock_irqrestore(&l1_data_sram_lock, flags); | 422 | spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); |
| 423 | put_cpu(); | ||
| 398 | 424 | ||
| 399 | pr_debug("Allocated address in l1_data_A_sram_alloc is 0x%lx+0x%lx\n", | 425 | pr_debug("Allocated address in l1_data_A_sram_alloc is 0x%lx+0x%lx\n", |
| 400 | (long unsigned int)addr, size); | 426 | (long unsigned int)addr, size); |
| @@ -407,19 +433,22 @@ int l1_data_A_sram_free(const void *addr) | |||
| 407 | { | 433 | { |
| 408 | unsigned long flags; | 434 | unsigned long flags; |
| 409 | int ret; | 435 | int ret; |
| 436 | unsigned int cpu; | ||
| 410 | 437 | ||
| 438 | cpu = get_cpu(); | ||
| 411 | /* add mutex operation */ | 439 | /* add mutex operation */ |
| 412 | spin_lock_irqsave(&l1_data_sram_lock, flags); | 440 | spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); |
| 413 | 441 | ||
| 414 | #if L1_DATA_A_LENGTH != 0 | 442 | #if L1_DATA_A_LENGTH != 0 |
| 415 | ret = _sram_free(addr, &free_l1_data_A_sram_head, | 443 | ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu), |
| 416 | &used_l1_data_A_sram_head); | 444 | &per_cpu(used_l1_data_A_sram_head, cpu)); |
| 417 | #else | 445 | #else |
| 418 | ret = -1; | 446 | ret = -1; |
| 419 | #endif | 447 | #endif |
| 420 | 448 | ||
| 421 | /* add mutex operation */ | 449 | /* add mutex operation */ |
| 422 | spin_unlock_irqrestore(&l1_data_sram_lock, flags); | 450 | spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); |
| 451 | put_cpu(); | ||
| 423 | 452 | ||
| 424 | return ret; | 453 | return ret; |
| 425 | } | 454 | } |
| @@ -430,15 +459,18 @@ void *l1_data_B_sram_alloc(size_t size) | |||
| 430 | #if L1_DATA_B_LENGTH != 0 | 459 | #if L1_DATA_B_LENGTH != 0 |
| 431 | unsigned long flags; | 460 | unsigned long flags; |
| 432 | void *addr; | 461 | void *addr; |
| 462 | unsigned int cpu; | ||
| 433 | 463 | ||
| 464 | cpu = get_cpu(); | ||
| 434 | /* add mutex operation */ | 465 | /* add mutex operation */ |
| 435 | spin_lock_irqsave(&l1_data_sram_lock, flags); | 466 | spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); |
| 436 | 467 | ||
| 437 | addr = _sram_alloc(size, &free_l1_data_B_sram_head, | 468 | addr = _sram_alloc(size, &per_cpu(free_l1_data_B_sram_head, cpu), |
| 438 | &used_l1_data_B_sram_head); | 469 | &per_cpu(used_l1_data_B_sram_head, cpu)); |
| 439 | 470 | ||
| 440 | /* add mutex operation */ | 471 | /* add mutex operation */ |
| 441 | spin_unlock_irqrestore(&l1_data_sram_lock, flags); | 472 | spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); |
| 473 | put_cpu(); | ||
| 442 | 474 | ||
| 443 | pr_debug("Allocated address in l1_data_B_sram_alloc is 0x%lx+0x%lx\n", | 475 | pr_debug("Allocated address in l1_data_B_sram_alloc is 0x%lx+0x%lx\n", |
| 444 | (long unsigned int)addr, size); | 476 | (long unsigned int)addr, size); |
| @@ -455,15 +487,18 @@ int l1_data_B_sram_free(const void *addr) | |||
| 455 | #if L1_DATA_B_LENGTH != 0 | 487 | #if L1_DATA_B_LENGTH != 0 |
| 456 | unsigned long flags; | 488 | unsigned long flags; |
| 457 | int ret; | 489 | int ret; |
| 490 | unsigned int cpu; | ||
| 458 | 491 | ||
| 492 | cpu = get_cpu(); | ||
| 459 | /* add mutex operation */ | 493 | /* add mutex operation */ |
| 460 | spin_lock_irqsave(&l1_data_sram_lock, flags); | 494 | spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags); |
| 461 | 495 | ||
| 462 | ret = _sram_free(addr, &free_l1_data_B_sram_head, | 496 | ret = _sram_free(addr, &per_cpu(free_l1_data_B_sram_head, cpu), |
| 463 | &used_l1_data_B_sram_head); | 497 | &per_cpu(used_l1_data_B_sram_head, cpu)); |
| 464 | 498 | ||
| 465 | /* add mutex operation */ | 499 | /* add mutex operation */ |
| 466 | spin_unlock_irqrestore(&l1_data_sram_lock, flags); | 500 | spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags); |
| 501 | put_cpu(); | ||
| 467 | 502 | ||
| 468 | return ret; | 503 | return ret; |
| 469 | #else | 504 | #else |
| @@ -509,15 +544,18 @@ void *l1_inst_sram_alloc(size_t size) | |||
| 509 | #if L1_CODE_LENGTH != 0 | 544 | #if L1_CODE_LENGTH != 0 |
| 510 | unsigned long flags; | 545 | unsigned long flags; |
| 511 | void *addr; | 546 | void *addr; |
| 547 | unsigned int cpu; | ||
| 512 | 548 | ||
| 549 | cpu = get_cpu(); | ||
| 513 | /* add mutex operation */ | 550 | /* add mutex operation */ |
| 514 | spin_lock_irqsave(&l1_inst_sram_lock, flags); | 551 | spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags); |
| 515 | 552 | ||
| 516 | addr = _sram_alloc(size, &free_l1_inst_sram_head, | 553 | addr = _sram_alloc(size, &per_cpu(free_l1_inst_sram_head, cpu), |
| 517 | &used_l1_inst_sram_head); | 554 | &per_cpu(used_l1_inst_sram_head, cpu)); |
| 518 | 555 | ||
| 519 | /* add mutex operation */ | 556 | /* add mutex operation */ |
| 520 | spin_unlock_irqrestore(&l1_inst_sram_lock, flags); | 557 | spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags); |
| 558 | put_cpu(); | ||
| 521 | 559 | ||
| 522 | pr_debug("Allocated address in l1_inst_sram_alloc is 0x%lx+0x%lx\n", | 560 | pr_debug("Allocated address in l1_inst_sram_alloc is 0x%lx+0x%lx\n", |
| 523 | (long unsigned int)addr, size); | 561 | (long unsigned int)addr, size); |
| @@ -534,15 +572,18 @@ int l1_inst_sram_free(const void *addr) | |||
| 534 | #if L1_CODE_LENGTH != 0 | 572 | #if L1_CODE_LENGTH != 0 |
| 535 | unsigned long flags; | 573 | unsigned long flags; |
| 536 | int ret; | 574 | int ret; |
| 575 | unsigned int cpu; | ||
| 537 | 576 | ||
| 577 | cpu = get_cpu(); | ||
| 538 | /* add mutex operation */ | 578 | /* add mutex operation */ |
| 539 | spin_lock_irqsave(&l1_inst_sram_lock, flags); | 579 | spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags); |
| 540 | 580 | ||
| 541 | ret = _sram_free(addr, &free_l1_inst_sram_head, | 581 | ret = _sram_free(addr, &per_cpu(free_l1_inst_sram_head, cpu), |
| 542 | &used_l1_inst_sram_head); | 582 | &per_cpu(used_l1_inst_sram_head, cpu)); |
| 543 | 583 | ||
| 544 | /* add mutex operation */ | 584 | /* add mutex operation */ |
| 545 | spin_unlock_irqrestore(&l1_inst_sram_lock, flags); | 585 | spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags); |
| 586 | put_cpu(); | ||
| 546 | 587 | ||
| 547 | return ret; | 588 | return ret; |
| 548 | #else | 589 | #else |
| @@ -556,15 +597,18 @@ void *l1sram_alloc(size_t size) | |||
| 556 | { | 597 | { |
| 557 | unsigned long flags; | 598 | unsigned long flags; |
| 558 | void *addr; | 599 | void *addr; |
| 600 | unsigned int cpu; | ||
| 559 | 601 | ||
| 602 | cpu = get_cpu(); | ||
| 560 | /* add mutex operation */ | 603 | /* add mutex operation */ |
| 561 | spin_lock_irqsave(&l1sram_lock, flags); | 604 | spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags); |
| 562 | 605 | ||
| 563 | addr = _sram_alloc(size, &free_l1_ssram_head, | 606 | addr = _sram_alloc(size, &per_cpu(free_l1_ssram_head, cpu), |
| 564 | &used_l1_ssram_head); | 607 | &per_cpu(used_l1_ssram_head, cpu)); |
| 565 | 608 | ||
| 566 | /* add mutex operation */ | 609 | /* add mutex operation */ |
| 567 | spin_unlock_irqrestore(&l1sram_lock, flags); | 610 | spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags); |
| 611 | put_cpu(); | ||
| 568 | 612 | ||
| 569 | return addr; | 613 | return addr; |
| 570 | } | 614 | } |
| @@ -574,15 +618,18 @@ void *l1sram_alloc_max(size_t *psize) | |||
| 574 | { | 618 | { |
| 575 | unsigned long flags; | 619 | unsigned long flags; |
| 576 | void *addr; | 620 | void *addr; |
| 621 | unsigned int cpu; | ||
| 577 | 622 | ||
| 623 | cpu = get_cpu(); | ||
| 578 | /* add mutex operation */ | 624 | /* add mutex operation */ |
| 579 | spin_lock_irqsave(&l1sram_lock, flags); | 625 | spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags); |
| 580 | 626 | ||
| 581 | addr = _sram_alloc_max(&free_l1_ssram_head, | 627 | addr = _sram_alloc_max(&per_cpu(free_l1_ssram_head, cpu), |
| 582 | &used_l1_ssram_head, psize); | 628 | &per_cpu(used_l1_ssram_head, cpu), psize); |
| 583 | 629 | ||
| 584 | /* add mutex operation */ | 630 | /* add mutex operation */ |
| 585 | spin_unlock_irqrestore(&l1sram_lock, flags); | 631 | spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags); |
| 632 | put_cpu(); | ||
| 586 | 633 | ||
| 587 | return addr; | 634 | return addr; |
| 588 | } | 635 | } |
| @@ -592,15 +639,18 @@ int l1sram_free(const void *addr) | |||
| 592 | { | 639 | { |
| 593 | unsigned long flags; | 640 | unsigned long flags; |
| 594 | int ret; | 641 | int ret; |
| 642 | unsigned int cpu; | ||
| 595 | 643 | ||
| 644 | cpu = get_cpu(); | ||
| 596 | /* add mutex operation */ | 645 | /* add mutex operation */ |
| 597 | spin_lock_irqsave(&l1sram_lock, flags); | 646 | spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags); |
| 598 | 647 | ||
| 599 | ret = _sram_free(addr, &free_l1_ssram_head, | 648 | ret = _sram_free(addr, &per_cpu(free_l1_ssram_head, cpu), |
| 600 | &used_l1_ssram_head); | 649 | &per_cpu(used_l1_ssram_head, cpu)); |
| 601 | 650 | ||
| 602 | /* add mutex operation */ | 651 | /* add mutex operation */ |
| 603 | spin_unlock_irqrestore(&l1sram_lock, flags); | 652 | spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags); |
| 653 | put_cpu(); | ||
| 604 | 654 | ||
| 605 | return ret; | 655 | return ret; |
| 606 | } | 656 | } |
| @@ -761,33 +811,36 @@ static int sram_proc_read(char *buf, char **start, off_t offset, int count, | |||
| 761 | int *eof, void *data) | 811 | int *eof, void *data) |
| 762 | { | 812 | { |
| 763 | int len = 0; | 813 | int len = 0; |
| 814 | unsigned int cpu; | ||
| 764 | 815 | ||
| 765 | if (_sram_proc_read(buf, &len, count, "Scratchpad", | 816 | for (cpu = 0; cpu < num_possible_cpus(); ++cpu) { |
| 766 | &free_l1_ssram_head, &used_l1_ssram_head)) | 817 | if (_sram_proc_read(buf, &len, count, "Scratchpad", |
| 767 | goto not_done; | 818 | &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu))) |
| 819 | goto not_done; | ||
| 768 | #if L1_DATA_A_LENGTH != 0 | 820 | #if L1_DATA_A_LENGTH != 0 |
| 769 | if (_sram_proc_read(buf, &len, count, "L1 Data A", | 821 | if (_sram_proc_read(buf, &len, count, "L1 Data A", |
| 770 | &free_l1_data_A_sram_head, | 822 | &per_cpu(free_l1_data_A_sram_head, cpu), |
| 771 | &used_l1_data_A_sram_head)) | 823 | &per_cpu(used_l1_data_A_sram_head, cpu))) |
| 772 | goto not_done; | 824 | goto not_done; |
| 773 | #endif | 825 | #endif |
| 774 | #if L1_DATA_B_LENGTH != 0 | 826 | #if L1_DATA_B_LENGTH != 0 |
| 775 | if (_sram_proc_read(buf, &len, count, "L1 Data B", | 827 | if (_sram_proc_read(buf, &len, count, "L1 Data B", |
| 776 | &free_l1_data_B_sram_head, | 828 | &per_cpu(free_l1_data_B_sram_head, cpu), |
| 777 | &used_l1_data_B_sram_head)) | 829 | &per_cpu(used_l1_data_B_sram_head, cpu))) |
| 778 | goto not_done; | 830 | goto not_done; |
| 779 | #endif | 831 | #endif |
| 780 | #if L1_CODE_LENGTH != 0 | 832 | #if L1_CODE_LENGTH != 0 |
| 781 | if (_sram_proc_read(buf, &len, count, "L1 Instruction", | 833 | if (_sram_proc_read(buf, &len, count, "L1 Instruction", |
| 782 | &free_l1_inst_sram_head, &used_l1_inst_sram_head)) | 834 | &per_cpu(free_l1_inst_sram_head, cpu), |
| 783 | goto not_done; | 835 | &per_cpu(used_l1_inst_sram_head, cpu))) |
| 836 | goto not_done; | ||
| 784 | #endif | 837 | #endif |
| 838 | } | ||
| 785 | #if L2_LENGTH != 0 | 839 | #if L2_LENGTH != 0 |
| 786 | if (_sram_proc_read(buf, &len, count, "L2", | 840 | if (_sram_proc_read(buf, &len, count, "L2", &free_l2_sram_head, |
| 787 | &free_l2_sram_head, &used_l2_sram_head)) | 841 | &used_l2_sram_head)) |
| 788 | goto not_done; | 842 | goto not_done; |
| 789 | #endif | 843 | #endif |
| 790 | |||
| 791 | *eof = 1; | 844 | *eof = 1; |
| 792 | not_done: | 845 | not_done: |
| 793 | return len; | 846 | return len; |
diff --git a/arch/blackfin/oprofile/Makefile b/arch/blackfin/oprofile/Makefile index 634e300d67e2..c70af3a01297 100644 --- a/arch/blackfin/oprofile/Makefile +++ b/arch/blackfin/oprofile/Makefile | |||
| @@ -10,5 +10,4 @@ DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \ | |||
| 10 | oprofilefs.o oprofile_stats.o \ | 10 | oprofilefs.o oprofile_stats.o \ |
| 11 | timer_int.o ) | 11 | timer_int.o ) |
| 12 | 12 | ||
| 13 | oprofile-y := $(DRIVER_OBJS) common.o | 13 | oprofile-y := $(DRIVER_OBJS) bfin_oprofile.o |
| 14 | oprofile-$(CONFIG_HARDWARE_PM) += op_model_bf533.o | ||
diff --git a/arch/blackfin/oprofile/bfin_oprofile.c b/arch/blackfin/oprofile/bfin_oprofile.c new file mode 100644 index 000000000000..c3b9713b23f8 --- /dev/null +++ b/arch/blackfin/oprofile/bfin_oprofile.c | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* | ||
| 2 | * bfin_oprofile.c - Blackfin oprofile code | ||
| 3 | * | ||
| 4 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/oprofile.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | |||
| 11 | int __init oprofile_arch_init(struct oprofile_operations *ops) | ||
| 12 | { | ||
| 13 | return -1; | ||
| 14 | } | ||
| 15 | |||
| 16 | void oprofile_arch_exit(void) | ||
| 17 | { | ||
| 18 | } | ||
diff --git a/arch/blackfin/oprofile/common.c b/arch/blackfin/oprofile/common.c deleted file mode 100644 index 0f6d303a8891..000000000000 --- a/arch/blackfin/oprofile/common.c +++ /dev/null | |||
| @@ -1,168 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/oprofile/common.c | ||
| 3 | * Based on: arch/alpha/oprofile/common.c | ||
| 4 | * Author: Anton Blanchard <anton@au.ibm.com> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM | ||
| 11 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/oprofile.h> | ||
| 32 | #include <linux/init.h> | ||
| 33 | #include <linux/smp.h> | ||
| 34 | #include <linux/errno.h> | ||
| 35 | #include <linux/mutex.h> | ||
| 36 | #include <linux/ptrace.h> | ||
| 37 | #include <linux/irq.h> | ||
| 38 | #include <linux/io.h> | ||
| 39 | |||
| 40 | #include <asm/system.h> | ||
| 41 | #include <asm/blackfin.h> | ||
| 42 | |||
| 43 | #include "op_blackfin.h" | ||
| 44 | |||
| 45 | #define BFIN_533_ID 0xE5040003 | ||
| 46 | #define BFIN_537_ID 0xE5040002 | ||
| 47 | |||
| 48 | static int pfmon_enabled; | ||
| 49 | static struct mutex pfmon_lock; | ||
| 50 | |||
| 51 | struct op_bfin533_model *model; | ||
| 52 | |||
| 53 | struct op_counter_config ctr[OP_MAX_COUNTER]; | ||
| 54 | |||
| 55 | static int op_bfin_setup(void) | ||
| 56 | { | ||
| 57 | int ret; | ||
| 58 | |||
| 59 | /* Pre-compute the values to stuff in the hardware registers. */ | ||
| 60 | spin_lock(&oprofilefs_lock); | ||
| 61 | ret = model->reg_setup(ctr); | ||
| 62 | spin_unlock(&oprofilefs_lock); | ||
| 63 | |||
| 64 | return ret; | ||
| 65 | } | ||
| 66 | |||
| 67 | static void op_bfin_shutdown(void) | ||
| 68 | { | ||
| 69 | #if 0 | ||
| 70 | /* what is the difference between shutdown and stop? */ | ||
| 71 | #endif | ||
| 72 | } | ||
| 73 | |||
| 74 | static int op_bfin_start(void) | ||
| 75 | { | ||
| 76 | int ret = -EBUSY; | ||
| 77 | |||
| 78 | printk(KERN_INFO "KSDBG:in %s\n", __func__); | ||
| 79 | mutex_lock(&pfmon_lock); | ||
| 80 | if (!pfmon_enabled) { | ||
| 81 | ret = model->start(ctr); | ||
| 82 | pfmon_enabled = !ret; | ||
| 83 | } | ||
| 84 | mutex_unlock(&pfmon_lock); | ||
| 85 | |||
| 86 | return ret; | ||
| 87 | } | ||
| 88 | |||
| 89 | static void op_bfin_stop(void) | ||
| 90 | { | ||
| 91 | mutex_lock(&pfmon_lock); | ||
| 92 | if (pfmon_enabled) { | ||
| 93 | model->stop(); | ||
| 94 | pfmon_enabled = 0; | ||
| 95 | } | ||
| 96 | mutex_unlock(&pfmon_lock); | ||
| 97 | } | ||
| 98 | |||
| 99 | static int op_bfin_create_files(struct super_block *sb, struct dentry *root) | ||
| 100 | { | ||
| 101 | int i; | ||
| 102 | |||
| 103 | for (i = 0; i < model->num_counters; ++i) { | ||
| 104 | struct dentry *dir; | ||
| 105 | char buf[3]; | ||
| 106 | printk(KERN_INFO "Oprofile: creating files... \n"); | ||
| 107 | |||
| 108 | snprintf(buf, sizeof buf, "%d", i); | ||
| 109 | dir = oprofilefs_mkdir(sb, root, buf); | ||
| 110 | |||
| 111 | oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled); | ||
| 112 | oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event); | ||
| 113 | oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count); | ||
| 114 | /* | ||
| 115 | * We dont support per counter user/kernel selection, but | ||
| 116 | * we leave the entries because userspace expects them | ||
| 117 | */ | ||
| 118 | oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel); | ||
| 119 | oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user); | ||
| 120 | oprofilefs_create_ulong(sb, dir, "unit_mask", | ||
| 121 | &ctr[i].unit_mask); | ||
| 122 | } | ||
| 123 | |||
| 124 | return 0; | ||
| 125 | } | ||
| 126 | int __init oprofile_arch_init(struct oprofile_operations *ops) | ||
| 127 | { | ||
| 128 | #ifdef CONFIG_HARDWARE_PM | ||
| 129 | unsigned int dspid; | ||
| 130 | |||
| 131 | mutex_init(&pfmon_lock); | ||
| 132 | |||
| 133 | dspid = bfin_read_DSPID(); | ||
| 134 | |||
| 135 | printk(KERN_INFO "Oprofile got the cpu id is 0x%x. \n", dspid); | ||
| 136 | |||
| 137 | switch (dspid) { | ||
| 138 | case BFIN_533_ID: | ||
| 139 | model = &op_model_bfin533; | ||
| 140 | model->num_counters = 2; | ||
| 141 | break; | ||
| 142 | case BFIN_537_ID: | ||
| 143 | model = &op_model_bfin533; | ||
| 144 | model->num_counters = 2; | ||
| 145 | break; | ||
| 146 | default: | ||
| 147 | return -ENODEV; | ||
| 148 | } | ||
| 149 | |||
| 150 | ops->cpu_type = model->name; | ||
| 151 | ops->create_files = op_bfin_create_files; | ||
| 152 | ops->setup = op_bfin_setup; | ||
| 153 | ops->shutdown = op_bfin_shutdown; | ||
| 154 | ops->start = op_bfin_start; | ||
| 155 | ops->stop = op_bfin_stop; | ||
| 156 | |||
| 157 | printk(KERN_INFO "oprofile: using %s performance monitoring.\n", | ||
| 158 | ops->cpu_type); | ||
| 159 | |||
| 160 | return 0; | ||
| 161 | #else | ||
| 162 | return -1; | ||
| 163 | #endif | ||
| 164 | } | ||
| 165 | |||
| 166 | void oprofile_arch_exit(void) | ||
| 167 | { | ||
| 168 | } | ||
diff --git a/arch/blackfin/oprofile/op_blackfin.h b/arch/blackfin/oprofile/op_blackfin.h deleted file mode 100644 index 05dd08c9d154..000000000000 --- a/arch/blackfin/oprofile/op_blackfin.h +++ /dev/null | |||
| @@ -1,98 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/oprofile/op_blackfin.h | ||
| 3 | * Based on: | ||
| 4 | * Author: Anton Blanchard <anton@au.ibm.com> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM | ||
| 11 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef OP_BLACKFIN_H | ||
| 32 | #define OP_BLACKFIN_H 1 | ||
| 33 | |||
| 34 | #define OP_MAX_COUNTER 2 | ||
| 35 | |||
| 36 | #include <asm/blackfin.h> | ||
| 37 | |||
| 38 | /* Per-counter configuration as set via oprofilefs. */ | ||
| 39 | struct op_counter_config { | ||
| 40 | unsigned long valid; | ||
| 41 | unsigned long enabled; | ||
| 42 | unsigned long event; | ||
| 43 | unsigned long count; | ||
| 44 | unsigned long kernel; | ||
| 45 | unsigned long user; | ||
| 46 | unsigned long unit_mask; | ||
| 47 | }; | ||
| 48 | |||
| 49 | /* System-wide configuration as set via oprofilefs. */ | ||
| 50 | struct op_system_config { | ||
| 51 | unsigned long enable_kernel; | ||
| 52 | unsigned long enable_user; | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* Per-arch configuration */ | ||
| 56 | struct op_bfin533_model { | ||
| 57 | int (*reg_setup) (struct op_counter_config *); | ||
| 58 | int (*start) (struct op_counter_config *); | ||
| 59 | void (*stop) (void); | ||
| 60 | int num_counters; | ||
| 61 | char *name; | ||
| 62 | }; | ||
| 63 | |||
| 64 | extern struct op_bfin533_model op_model_bfin533; | ||
| 65 | |||
| 66 | static inline unsigned int ctr_read(void) | ||
| 67 | { | ||
| 68 | unsigned int tmp; | ||
| 69 | |||
| 70 | tmp = bfin_read_PFCTL(); | ||
| 71 | CSYNC(); | ||
| 72 | |||
| 73 | return tmp; | ||
| 74 | } | ||
| 75 | |||
| 76 | static inline void ctr_write(unsigned int val) | ||
| 77 | { | ||
| 78 | bfin_write_PFCTL(val); | ||
| 79 | CSYNC(); | ||
| 80 | } | ||
| 81 | |||
| 82 | static inline void count_read(unsigned int *count) | ||
| 83 | { | ||
| 84 | count[0] = bfin_read_PFCNTR0(); | ||
| 85 | count[1] = bfin_read_PFCNTR1(); | ||
| 86 | CSYNC(); | ||
| 87 | } | ||
| 88 | |||
| 89 | static inline void count_write(unsigned int *count) | ||
| 90 | { | ||
| 91 | bfin_write_PFCNTR0(count[0]); | ||
| 92 | bfin_write_PFCNTR1(count[1]); | ||
| 93 | CSYNC(); | ||
| 94 | } | ||
| 95 | |||
| 96 | extern int pm_overflow_handler(int irq, struct pt_regs *regs); | ||
| 97 | |||
| 98 | #endif | ||
diff --git a/arch/blackfin/oprofile/op_model_bf533.c b/arch/blackfin/oprofile/op_model_bf533.c deleted file mode 100644 index d1c698bb9ee5..000000000000 --- a/arch/blackfin/oprofile/op_model_bf533.c +++ /dev/null | |||
| @@ -1,161 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/oprofile/op_model_bf533.c | ||
| 3 | * Based on: | ||
| 4 | * Author: Anton Blanchard <anton@au.ibm.com> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM | ||
| 11 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/oprofile.h> | ||
| 32 | #include <linux/init.h> | ||
| 33 | #include <linux/smp.h> | ||
| 34 | #include <linux/interrupt.h> | ||
| 35 | #include <linux/ptrace.h> | ||
| 36 | #include <linux/irq.h> | ||
| 37 | #include <linux/io.h> | ||
| 38 | #include <asm/system.h> | ||
| 39 | #include <asm/processor.h> | ||
| 40 | #include <asm/blackfin.h> | ||
| 41 | |||
| 42 | #include "op_blackfin.h" | ||
| 43 | |||
| 44 | #define PM_ENABLE 0x01; | ||
| 45 | #define PM_CTL1_ENABLE 0x18 | ||
| 46 | #define PM_CTL0_ENABLE 0xC000 | ||
| 47 | #define COUNT_EDGE_ONLY 0x3000000 | ||
| 48 | |||
| 49 | static int oprofile_running; | ||
| 50 | |||
| 51 | static unsigned curr_pfctl, curr_count[2]; | ||
| 52 | |||
| 53 | static int bfin533_reg_setup(struct op_counter_config *ctr) | ||
| 54 | { | ||
| 55 | unsigned int pfctl = ctr_read(); | ||
| 56 | unsigned int count[2]; | ||
| 57 | |||
| 58 | /* set Blackfin perf monitor regs with ctr */ | ||
| 59 | if (ctr[0].enabled) { | ||
| 60 | pfctl |= (PM_CTL0_ENABLE | ((char)ctr[0].event << 5)); | ||
| 61 | count[0] = 0xFFFFFFFF - ctr[0].count; | ||
| 62 | curr_count[0] = count[0]; | ||
| 63 | } | ||
| 64 | if (ctr[1].enabled) { | ||
| 65 | pfctl |= (PM_CTL1_ENABLE | ((char)ctr[1].event << 16)); | ||
| 66 | count[1] = 0xFFFFFFFF - ctr[1].count; | ||
| 67 | curr_count[1] = count[1]; | ||
| 68 | } | ||
| 69 | |||
| 70 | pr_debug("ctr[0].enabled=%d,ctr[1].enabled=%d,ctr[0].event<<5=0x%x,ctr[1].event<<16=0x%x\n", ctr[0].enabled, ctr[1].enabled, ctr[0].event << 5, ctr[1].event << 16); | ||
| 71 | pfctl |= COUNT_EDGE_ONLY; | ||
| 72 | curr_pfctl = pfctl; | ||
| 73 | |||
| 74 | pr_debug("write 0x%x to pfctl\n", pfctl); | ||
| 75 | ctr_write(pfctl); | ||
| 76 | count_write(count); | ||
| 77 | |||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | |||
| 81 | static int bfin533_start(struct op_counter_config *ctr) | ||
| 82 | { | ||
| 83 | unsigned int pfctl = ctr_read(); | ||
| 84 | |||
| 85 | pfctl |= PM_ENABLE; | ||
| 86 | curr_pfctl = pfctl; | ||
| 87 | |||
| 88 | ctr_write(pfctl); | ||
| 89 | |||
| 90 | oprofile_running = 1; | ||
| 91 | pr_debug("start oprofile counter \n"); | ||
| 92 | |||
| 93 | return 0; | ||
| 94 | } | ||
| 95 | |||
| 96 | static void bfin533_stop(void) | ||
| 97 | { | ||
| 98 | int pfctl; | ||
| 99 | |||
| 100 | pfctl = ctr_read(); | ||
| 101 | pfctl &= ~PM_ENABLE; | ||
| 102 | /* freeze counters */ | ||
| 103 | ctr_write(pfctl); | ||
| 104 | |||
| 105 | oprofile_running = 0; | ||
| 106 | pr_debug("stop oprofile counter \n"); | ||
| 107 | } | ||
| 108 | |||
| 109 | static int get_kernel(void) | ||
| 110 | { | ||
| 111 | int ipend, is_kernel; | ||
| 112 | |||
| 113 | ipend = bfin_read_IPEND(); | ||
| 114 | |||
| 115 | /* test bit 15 */ | ||
| 116 | is_kernel = ((ipend & 0x8000) != 0); | ||
| 117 | |||
| 118 | return is_kernel; | ||
| 119 | } | ||
| 120 | |||
| 121 | int pm_overflow_handler(int irq, struct pt_regs *regs) | ||
| 122 | { | ||
| 123 | int is_kernel; | ||
| 124 | int i, cpu; | ||
| 125 | unsigned int pc, pfctl; | ||
| 126 | unsigned int count[2]; | ||
| 127 | |||
| 128 | pr_debug("get interrupt in %s\n", __func__); | ||
| 129 | if (oprofile_running == 0) { | ||
| 130 | pr_debug("error: entering interrupt when oprofile is stopped.\n\r"); | ||
| 131 | return -1; | ||
| 132 | } | ||
| 133 | |||
| 134 | is_kernel = get_kernel(); | ||
| 135 | cpu = smp_processor_id(); | ||
| 136 | pc = regs->pc; | ||
| 137 | pfctl = ctr_read(); | ||
| 138 | |||
| 139 | /* read the two event counter regs */ | ||
| 140 | count_read(count); | ||
| 141 | |||
| 142 | /* if the counter overflows, add sample to oprofile buffer */ | ||
| 143 | for (i = 0; i < 2; ++i) { | ||
| 144 | if (oprofile_running) { | ||
| 145 | oprofile_add_sample(regs, i); | ||
| 146 | } | ||
| 147 | } | ||
| 148 | |||
| 149 | /* reset the perfmon counter */ | ||
| 150 | ctr_write(curr_pfctl); | ||
| 151 | count_write(curr_count); | ||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | struct op_bfin533_model op_model_bfin533 = { | ||
| 156 | .reg_setup = bfin533_reg_setup, | ||
| 157 | .start = bfin533_start, | ||
| 158 | .stop = bfin533_stop, | ||
| 159 | .num_counters = 2, | ||
| 160 | .name = "blackfin/bf533" | ||
| 161 | }; | ||
diff --git a/arch/blackfin/oprofile/timer_int.c b/arch/blackfin/oprofile/timer_int.c deleted file mode 100644 index 6c6f8606af4c..000000000000 --- a/arch/blackfin/oprofile/timer_int.c +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/oprofile/timer_int.c | ||
| 3 | * Based on: | ||
| 4 | * Author: Michael Kang | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/init.h> | ||
| 31 | #include <linux/smp.h> | ||
| 32 | #include <linux/irq.h> | ||
| 33 | #include <linux/oprofile.h> | ||
| 34 | #include <linux/ptrace.h> | ||
| 35 | |||
| 36 | static void enable_sys_timer0() | ||
| 37 | { | ||
| 38 | } | ||
| 39 | static void disable_sys_timer0() | ||
| 40 | { | ||
| 41 | } | ||
| 42 | |||
| 43 | static irqreturn_t sys_timer0_int_handler(int irq, void *dev_id, | ||
| 44 | struct pt_regs *regs) | ||
| 45 | { | ||
| 46 | oprofile_add_sample(regs, 0); | ||
| 47 | return IRQ_HANDLED; | ||
| 48 | } | ||
| 49 | |||
| 50 | static int sys_timer0_start(void) | ||
| 51 | { | ||
| 52 | enable_sys_timer0(); | ||
| 53 | return request_irq(IVG11, sys_timer0_int_handler, 0, "sys_timer0", NULL); | ||
| 54 | } | ||
| 55 | |||
| 56 | static void sys_timer0_stop(void) | ||
| 57 | { | ||
| 58 | disable_sys_timer(); | ||
| 59 | } | ||
| 60 | |||
| 61 | int __init sys_timer0_init(struct oprofile_operations *ops) | ||
| 62 | { | ||
| 63 | extern int nmi_active; | ||
| 64 | |||
| 65 | if (nmi_active <= 0) | ||
| 66 | return -ENODEV; | ||
| 67 | |||
| 68 | ops->start = timer_start; | ||
| 69 | ops->stop = timer_stop; | ||
| 70 | ops->cpu_type = "timer"; | ||
| 71 | printk(KERN_INFO "oprofile: using NMI timer interrupt.\n"); | ||
| 72 | return 0; | ||
| 73 | } | ||