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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-10-08 05:06:58 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-10-08 05:06:58 -0400 |
| commit | 4fa046655b80e9bb361a95da5c86ce778f5018b9 (patch) | |
| tree | 53105e279484895b3cb24dd73eb47a19f1381137 | |
| parent | 552dc340bce3b28f4af33c9134adafa5efacf1c9 (diff) | |
| parent | 846afbd1fe015e082c89d56dd42c484d896ef58e (diff) | |
Merge branch 'for-russell' of git://codeaurora.org/quic/kernel/dwalker/linux-msm into devel-stable
| -rw-r--r-- | arch/arm/common/gic.c | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 7dfa9a85bc0c..ada6359160eb 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
| @@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq) | |||
| 67 | 67 | ||
| 68 | /* | 68 | /* |
| 69 | * Routines to acknowledge, disable and enable interrupts | 69 | * Routines to acknowledge, disable and enable interrupts |
| 70 | * | ||
| 71 | * Linux assumes that when we're done with an interrupt we need to | ||
| 72 | * unmask it, in the same way we need to unmask an interrupt when | ||
| 73 | * we first enable it. | ||
| 74 | * | ||
| 75 | * The GIC has a separate notion of "end of interrupt" to re-enable | ||
| 76 | * an interrupt after handling, in order to support hardware | ||
| 77 | * prioritisation. | ||
| 78 | * | ||
| 79 | * We can make the GIC behave in the way that Linux expects by making | ||
| 80 | * our "acknowledge" routine disable the interrupt, then mark it as | ||
| 81 | * complete. | ||
| 82 | */ | 70 | */ |
| 83 | static void gic_ack_irq(unsigned int irq) | 71 | static void gic_ack_irq(unsigned int irq) |
| 84 | { | 72 | { |
| 85 | u32 mask = 1 << (irq % 32); | ||
| 86 | 73 | ||
| 87 | spin_lock(&irq_controller_lock); | 74 | spin_lock(&irq_controller_lock); |
| 88 | writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); | ||
| 89 | writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); | 75 | writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); |
| 90 | spin_unlock(&irq_controller_lock); | 76 | spin_unlock(&irq_controller_lock); |
| 91 | } | 77 | } |
