diff options
| author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2006-05-11 22:11:48 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-06-19 17:13:24 -0400 |
| commit | 4085399da3c2176ba8ed64e93a2722907d41df3f (patch) | |
| tree | fc923b10c70ededacf661b21285d852a8da8d886 | |
| parent | c4cecc1937cafd8505151452a9f7eea876a5bd9c (diff) | |
[PATCH] shpchp: Cleanup SHPC commands
This patch cleans up the code related to issuing SHPC commands. This
patch has no functional changes.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Cc: Kristen Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| -rw-r--r-- | drivers/pci/hotplug/shpchp_hpc.c | 98 |
1 files changed, 48 insertions, 50 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c index e0f8c1bbaf12..f6b3bf3ee7ca 100644 --- a/drivers/pci/hotplug/shpchp_hpc.c +++ b/drivers/pci/hotplug/shpchp_hpc.c | |||
| @@ -147,39 +147,37 @@ | |||
| 147 | #define CON_PFAULT_SERR_MASK (1 << 30) | 147 | #define CON_PFAULT_SERR_MASK (1 << 30) |
| 148 | #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) | 148 | #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) |
| 149 | 149 | ||
| 150 | /* SHPC 'write' operations/commands */ | 150 | /* |
| 151 | 151 | * SHPC Command Code definitnions | |
| 152 | /* Slot operation - 0x00h to 0x3Fh */ | 152 | * |
| 153 | 153 | * Slot Operation 00h - 3Fh | |
| 154 | #define NO_CHANGE 0x00 | 154 | * Set Bus Segment Speed/Mode A 40h - 47h |
| 155 | 155 | * Power-Only All Slots 48h | |
| 156 | /* Slot state - Bits 0 & 1 of controller command register */ | 156 | * Enable All Slots 49h |
| 157 | #define SET_SLOT_PWR 0x01 | 157 | * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh |
| 158 | #define SET_SLOT_ENABLE 0x02 | 158 | * Reserved Command Codes 60h - BFh |
| 159 | #define SET_SLOT_DISABLE 0x03 | 159 | * Vendor Specific Commands C0h - FFh |
| 160 | 160 | */ | |
| 161 | /* Power indicator state - Bits 2 & 3 of controller command register*/ | 161 | #define SET_SLOT_PWR 0x01 /* Slot Operation */ |
| 162 | #define SET_PWR_ON 0x04 | 162 | #define SET_SLOT_ENABLE 0x02 |
| 163 | #define SET_PWR_BLINK 0x08 | 163 | #define SET_SLOT_DISABLE 0x03 |
| 164 | #define SET_PWR_OFF 0x0C | 164 | #define SET_PWR_ON 0x04 |
| 165 | 165 | #define SET_PWR_BLINK 0x08 | |
| 166 | /* Attention indicator state - Bits 4 & 5 of controller command register*/ | 166 | #define SET_PWR_OFF 0x0c |
| 167 | #define SET_ATTN_ON 0x010 | 167 | #define SET_ATTN_ON 0x10 |
| 168 | #define SET_ATTN_BLINK 0x020 | 168 | #define SET_ATTN_BLINK 0x20 |
| 169 | #define SET_ATTN_OFF 0x030 | 169 | #define SET_ATTN_OFF 0x30 |
| 170 | 170 | #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ | |
| 171 | /* Set bus speed/mode A - 0x40h to 0x47h */ | ||
| 172 | #define SETA_PCI_33MHZ 0x40 | ||
| 173 | #define SETA_PCI_66MHZ 0x41 | 171 | #define SETA_PCI_66MHZ 0x41 |
| 174 | #define SETA_PCIX_66MHZ 0x42 | 172 | #define SETA_PCIX_66MHZ 0x42 |
| 175 | #define SETA_PCIX_100MHZ 0x43 | 173 | #define SETA_PCIX_100MHZ 0x43 |
| 176 | #define SETA_PCIX_133MHZ 0x44 | 174 | #define SETA_PCIX_133MHZ 0x44 |
| 177 | #define RESERV_1 0x45 | 175 | #define SETA_RESERVED1 0x45 |
| 178 | #define RESERV_2 0x46 | 176 | #define SETA_RESERVED2 0x46 |
| 179 | #define RESERV_3 0x47 | 177 | #define SETA_RESERVED3 0x47 |
| 180 | 178 | #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ | |
| 181 | /* Set bus speed/mode B - 0x50h to 0x5fh */ | 179 | #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ |
| 182 | #define SETB_PCI_33MHZ 0x50 | 180 | #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ |
| 183 | #define SETB_PCI_66MHZ 0x51 | 181 | #define SETB_PCI_66MHZ 0x51 |
| 184 | #define SETB_PCIX_66MHZ_PM 0x52 | 182 | #define SETB_PCIX_66MHZ_PM 0x52 |
| 185 | #define SETB_PCIX_100MHZ_PM 0x53 | 183 | #define SETB_PCIX_100MHZ_PM 0x53 |
| @@ -193,23 +191,21 @@ | |||
| 193 | #define SETB_PCIX_66MHZ_533 0x5b | 191 | #define SETB_PCIX_66MHZ_533 0x5b |
| 194 | #define SETB_PCIX_100MHZ_533 0x5c | 192 | #define SETB_PCIX_100MHZ_533 0x5c |
| 195 | #define SETB_PCIX_133MHZ_533 0x5d | 193 | #define SETB_PCIX_133MHZ_533 0x5d |
| 194 | #define SETB_RESERVED1 0x5e | ||
| 195 | #define SETB_RESERVED2 0x5f | ||
| 196 | 196 | ||
| 197 | 197 | /* | |
| 198 | /* Power-on all slots - 0x48h */ | 198 | * SHPC controller command error code |
| 199 | #define SET_PWR_ON_ALL 0x48 | 199 | */ |
| 200 | |||
| 201 | /* Enable all slots - 0x49h */ | ||
| 202 | #define SET_ENABLE_ALL 0x49 | ||
| 203 | |||
| 204 | /* SHPC controller command error code */ | ||
| 205 | #define SWITCH_OPEN 0x1 | 200 | #define SWITCH_OPEN 0x1 |
| 206 | #define INVALID_CMD 0x2 | 201 | #define INVALID_CMD 0x2 |
| 207 | #define INVALID_SPEED_MODE 0x4 | 202 | #define INVALID_SPEED_MODE 0x4 |
| 208 | 203 | ||
| 209 | /* For accessing SHPC Working Register Set */ | 204 | /* |
| 205 | * For accessing SHPC Working Register Set via PCI Configuration Space | ||
| 206 | */ | ||
| 210 | #define DWORD_SELECT 0x2 | 207 | #define DWORD_SELECT 0x2 |
| 211 | #define DWORD_DATA 0x4 | 208 | #define DWORD_DATA 0x4 |
| 212 | #define BASE_OFFSET 0x0 | ||
| 213 | 209 | ||
| 214 | /* Field Offset in Logical Slot Register - byte boundary */ | 210 | /* Field Offset in Logical Slot Register - byte boundary */ |
| 215 | #define SLOT_EVENT_LATCH 0x2 | 211 | #define SLOT_EVENT_LATCH 0x2 |
| @@ -630,13 +626,13 @@ static int hpc_set_attention_status(struct slot *slot, u8 value) | |||
| 630 | 626 | ||
| 631 | switch (value) { | 627 | switch (value) { |
| 632 | case 0 : | 628 | case 0 : |
| 633 | slot_cmd = 0x30; /* OFF */ | 629 | slot_cmd = SET_ATTN_OFF; /* OFF */ |
| 634 | break; | 630 | break; |
| 635 | case 1: | 631 | case 1: |
| 636 | slot_cmd = 0x10; /* ON */ | 632 | slot_cmd = SET_ATTN_ON; /* ON */ |
| 637 | break; | 633 | break; |
| 638 | case 2: | 634 | case 2: |
| 639 | slot_cmd = 0x20; /* BLINK */ | 635 | slot_cmd = SET_ATTN_BLINK; /* BLINK */ |
| 640 | break; | 636 | break; |
| 641 | default: | 637 | default: |
| 642 | return -1; | 638 | return -1; |
| @@ -648,17 +644,17 @@ static int hpc_set_attention_status(struct slot *slot, u8 value) | |||
| 648 | 644 | ||
| 649 | static void hpc_set_green_led_on(struct slot *slot) | 645 | static void hpc_set_green_led_on(struct slot *slot) |
| 650 | { | 646 | { |
| 651 | shpc_write_cmd(slot, slot->hp_slot, 0x04); | 647 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); |
| 652 | } | 648 | } |
| 653 | 649 | ||
| 654 | static void hpc_set_green_led_off(struct slot *slot) | 650 | static void hpc_set_green_led_off(struct slot *slot) |
| 655 | { | 651 | { |
| 656 | shpc_write_cmd(slot, slot->hp_slot, 0x0c); | 652 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); |
| 657 | } | 653 | } |
| 658 | 654 | ||
| 659 | static void hpc_set_green_led_blink(struct slot *slot) | 655 | static void hpc_set_green_led_blink(struct slot *slot) |
| 660 | { | 656 | { |
| 661 | shpc_write_cmd(slot, slot->hp_slot, 0x08); | 657 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); |
| 662 | } | 658 | } |
| 663 | 659 | ||
| 664 | int shpc_get_ctlr_slot_config(struct controller *ctrl, | 660 | int shpc_get_ctlr_slot_config(struct controller *ctrl, |
| @@ -769,7 +765,7 @@ static int hpc_power_on_slot(struct slot * slot) | |||
| 769 | 765 | ||
| 770 | DBG_ENTER_ROUTINE | 766 | DBG_ENTER_ROUTINE |
| 771 | 767 | ||
| 772 | retval = shpc_write_cmd(slot, slot->hp_slot, 0x01); | 768 | retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); |
| 773 | if (retval) { | 769 | if (retval) { |
| 774 | err("%s: Write command failed!\n", __FUNCTION__); | 770 | err("%s: Write command failed!\n", __FUNCTION__); |
| 775 | return retval; | 771 | return retval; |
| @@ -786,8 +782,9 @@ static int hpc_slot_enable(struct slot * slot) | |||
| 786 | 782 | ||
| 787 | DBG_ENTER_ROUTINE | 783 | DBG_ENTER_ROUTINE |
| 788 | 784 | ||
| 789 | /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ | 785 | /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ |
| 790 | retval = shpc_write_cmd(slot, slot->hp_slot, 0x3a); | 786 | retval = shpc_write_cmd(slot, slot->hp_slot, |
| 787 | SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); | ||
| 791 | if (retval) { | 788 | if (retval) { |
| 792 | err("%s: Write command failed!\n", __FUNCTION__); | 789 | err("%s: Write command failed!\n", __FUNCTION__); |
| 793 | return retval; | 790 | return retval; |
| @@ -803,8 +800,9 @@ static int hpc_slot_disable(struct slot * slot) | |||
| 803 | 800 | ||
| 804 | DBG_ENTER_ROUTINE | 801 | DBG_ENTER_ROUTINE |
| 805 | 802 | ||
| 806 | /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */ | 803 | /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ |
| 807 | retval = shpc_write_cmd(slot, slot->hp_slot, 0x1f); | 804 | retval = shpc_write_cmd(slot, slot->hp_slot, |
| 805 | SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); | ||
| 808 | if (retval) { | 806 | if (retval) { |
| 809 | err("%s: Write command failed!\n", __FUNCTION__); | 807 | err("%s: Write command failed!\n", __FUNCTION__); |
| 810 | return retval; | 808 | return retval; |
