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authorLinus Torvalds <torvalds@linux-foundation.org>2010-01-28 19:33:12 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-01-28 19:33:12 -0500
commit3d29935ff0773fe466e957f17284ca777a2aaa89 (patch)
treedcbadff76bb481124fe996e4103c138f1810e984
parent474118d06d1d5053f27450224f0541219483ec69 (diff)
parente8e06eae4ffd683931b928f460c11c40cd3f7fd8 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: x86/PCI: remove IOH range fetching PCI: fix nested spinlock hang in aer_inject
Diffstat
-rw-r--r--arch/x86/pci/Makefile2
-rw-r--r--arch/x86/pci/intel_bus.c94
-rw-r--r--drivers/pci/pcie/aer/aer_inject.c12
3 files changed, 7 insertions, 101 deletions
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index 564b008a51c7..39fba37f702f 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
15 15
16obj-y += common.o early.o 16obj-y += common.o early.o
17obj-y += amd_bus.o 17obj-y += amd_bus.o
18obj-$(CONFIG_X86_64) += bus_numa.o intel_bus.o 18obj-$(CONFIG_X86_64) += bus_numa.o
19 19
20ifeq ($(CONFIG_PCI_DEBUG),y) 20ifeq ($(CONFIG_PCI_DEBUG),y)
21EXTRA_CFLAGS += -DDEBUG 21EXTRA_CFLAGS += -DDEBUG
diff --git a/arch/x86/pci/intel_bus.c b/arch/x86/pci/intel_bus.c
deleted file mode 100644
index f81a2fa8fe25..000000000000
--- a/arch/x86/pci/intel_bus.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * to read io range from IOH pci conf, need to do it after mmconfig is there
3 */
4
5#include <linux/delay.h>
6#include <linux/dmi.h>
7#include <linux/pci.h>
8#include <linux/init.h>
9#include <asm/pci_x86.h>
10
11#include "bus_numa.h"
12
13static inline void print_ioh_resources(struct pci_root_info *info)
14{
15 int res_num;
16 int busnum;
17 int i;
18
19 printk(KERN_DEBUG "IOH bus: [%02x, %02x]\n",
20 info->bus_min, info->bus_max);
21 res_num = info->res_num;
22 busnum = info->bus_min;
23 for (i = 0; i < res_num; i++) {
24 struct resource *res;
25
26 res = &info->res[i];
27 printk(KERN_DEBUG "IOH bus: %02x index %x %s: [%llx, %llx]\n",
28 busnum, i,
29 (res->flags & IORESOURCE_IO) ? "io port" :
30 "mmio",
31 res->start, res->end);
32 }
33}
34
35#define IOH_LIO 0x108
36#define IOH_LMMIOL 0x10c
37#define IOH_LMMIOH 0x110
38#define IOH_LMMIOH_BASEU 0x114
39#define IOH_LMMIOH_LIMITU 0x118
40#define IOH_LCFGBUS 0x11c
41
42static void __devinit pci_root_bus_res(struct pci_dev *dev)
43{
44 u16 word;
45 u32 dword;
46 struct pci_root_info *info;
47 u16 io_base, io_end;
48 u32 mmiol_base, mmiol_end;
49 u64 mmioh_base, mmioh_end;
50 int bus_base, bus_end;
51
52 /* some sys doesn't get mmconf enabled */
53 if (dev->cfg_size < 0x120)
54 return;
55
56 if (pci_root_num >= PCI_ROOT_NR) {
57 printk(KERN_DEBUG "intel_bus.c: PCI_ROOT_NR is too small\n");
58 return;
59 }
60
61 info = &pci_root_info[pci_root_num];
62 pci_root_num++;
63
64 pci_read_config_word(dev, IOH_LCFGBUS, &word);
65 bus_base = (word & 0xff);
66 bus_end = (word & 0xff00) >> 8;
67 sprintf(info->name, "PCI Bus #%02x", bus_base);
68 info->bus_min = bus_base;
69 info->bus_max = bus_end;
70
71 pci_read_config_word(dev, IOH_LIO, &word);
72 io_base = (word & 0xf0) << (12 - 4);
73 io_end = (word & 0xf000) | 0xfff;
74 update_res(info, io_base, io_end, IORESOURCE_IO, 0);
75
76 pci_read_config_dword(dev, IOH_LMMIOL, &dword);
77 mmiol_base = (dword & 0xff00) << (24 - 8);
78 mmiol_end = (dword & 0xff000000) | 0xffffff;
79 update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0);
80
81 pci_read_config_dword(dev, IOH_LMMIOH, &dword);
82 mmioh_base = ((u64)(dword & 0xfc00)) << (26 - 10);
83 mmioh_end = ((u64)(dword & 0xfc000000) | 0x3ffffff);
84 pci_read_config_dword(dev, IOH_LMMIOH_BASEU, &dword);
85 mmioh_base |= ((u64)(dword & 0x7ffff)) << 32;
86 pci_read_config_dword(dev, IOH_LMMIOH_LIMITU, &dword);
87 mmioh_end |= ((u64)(dword & 0x7ffff)) << 32;
88 update_res(info, mmioh_base, mmioh_end, IORESOURCE_MEM, 0);
89
90 print_ioh_resources(info);
91}
92
93/* intel IOH */
94DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, pci_root_bus_res);
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c
index 8c30a9544d61..223052b73563 100644
--- a/drivers/pci/pcie/aer/aer_inject.c
+++ b/drivers/pci/pcie/aer/aer_inject.c
@@ -321,7 +321,7 @@ static int aer_inject(struct aer_error_inj *einj)
321 unsigned long flags; 321 unsigned long flags;
322 unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn); 322 unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
323 int pos_cap_err, rp_pos_cap_err; 323 int pos_cap_err, rp_pos_cap_err;
324 u32 sever, mask; 324 u32 sever, cor_mask, uncor_mask;
325 int ret = 0; 325 int ret = 0;
326 326
327 dev = pci_get_domain_bus_and_slot((int)einj->domain, einj->bus, devfn); 327 dev = pci_get_domain_bus_and_slot((int)einj->domain, einj->bus, devfn);
@@ -339,6 +339,9 @@ static int aer_inject(struct aer_error_inj *einj)
339 goto out_put; 339 goto out_put;
340 } 340 }
341 pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever); 341 pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever);
342 pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &cor_mask);
343 pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
344 &uncor_mask);
342 345
343 rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR); 346 rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR);
344 if (!rp_pos_cap_err) { 347 if (!rp_pos_cap_err) {
@@ -374,17 +377,14 @@ static int aer_inject(struct aer_error_inj *einj)
374 err->header_log2 = einj->header_log2; 377 err->header_log2 = einj->header_log2;
375 err->header_log3 = einj->header_log3; 378 err->header_log3 = einj->header_log3;
376 379
377 pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &mask); 380 if (einj->cor_status && !(einj->cor_status & ~cor_mask)) {
378 if (einj->cor_status && !(einj->cor_status & ~mask)) {
379 ret = -EINVAL; 381 ret = -EINVAL;
380 printk(KERN_WARNING "The correctable error(s) is masked " 382 printk(KERN_WARNING "The correctable error(s) is masked "
381 "by device\n"); 383 "by device\n");
382 spin_unlock_irqrestore(&inject_lock, flags); 384 spin_unlock_irqrestore(&inject_lock, flags);
383 goto out_put; 385 goto out_put;
384 } 386 }
385 387 if (einj->uncor_status && !(einj->uncor_status & ~uncor_mask)) {
386 pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK, &mask);
387 if (einj->uncor_status && !(einj->uncor_status & ~mask)) {
388 ret = -EINVAL; 388 ret = -EINVAL;
389 printk(KERN_WARNING "The uncorrectable error(s) is masked " 389 printk(KERN_WARNING "The uncorrectable error(s) is masked "
390 "by device\n"); 390 "by device\n");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-20 01:49:50 -0400
opt">(flags); return 0; } /* XXXKYMA: Must be called with interrupts disabled */ int kvm_mips_handle_kseg0_tlb_fault(unsigned long badvaddr, struct kvm_vcpu *vcpu) { gfn_t gfn; kvm_pfn_t pfn0, pfn1; unsigned long vaddr = 0; unsigned long entryhi = 0, entrylo0 = 0, entrylo1 = 0; int even; struct kvm *kvm = vcpu->kvm; const int flush_dcache_mask = 0; if (KVM_GUEST_KSEGX(badvaddr) != KVM_GUEST_KSEG0) { kvm_err("%s: Invalid BadVaddr: %#lx\n", __func__, badvaddr); kvm_mips_dump_host_tlbs(); return -1; } gfn = (KVM_GUEST_CPHYSADDR(badvaddr) >> PAGE_SHIFT); if (gfn >= kvm->arch.guest_pmap_npages) { kvm_err("%s: Invalid gfn: %#llx, BadVaddr: %#lx\n", __func__, gfn, badvaddr); kvm_mips_dump_host_tlbs(); return -1; } even = !(gfn & 0x1); vaddr = badvaddr & (PAGE_MASK << 1); if (kvm_mips_map_page(vcpu->kvm, gfn) < 0) return -1; if (kvm_mips_map_page(vcpu->kvm, gfn ^ 0x1) < 0) return -1; if (even) { pfn0 = kvm->arch.guest_pmap[gfn]; pfn1 = kvm->arch.guest_pmap[gfn ^ 0x1]; } else { pfn0 = kvm->arch.guest_pmap[gfn ^ 0x1]; pfn1 = kvm->arch.guest_pmap[gfn]; } entryhi = (vaddr | kvm_mips_get_kernel_asid(vcpu)); entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) | (1 << 2) | (0x1 << 1); entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) | (1 << 2) | (0x1 << 1); return kvm_mips_host_tlb_write(vcpu, entryhi, entrylo0, entrylo1, flush_dcache_mask); } EXPORT_SYMBOL_GPL(kvm_mips_handle_kseg0_tlb_fault); int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, struct kvm_vcpu *vcpu) { kvm_pfn_t pfn0, pfn1; unsigned long flags, old_entryhi = 0, vaddr = 0; unsigned long entrylo0 = 0, entrylo1 = 0; pfn0 = CPHYSADDR(vcpu->arch.kseg0_commpage) >> PAGE_SHIFT; pfn1 = 0; entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) | (1 << 2) | (0x1 << 1); entrylo1 = 0; local_irq_save(flags); old_entryhi = read_c0_entryhi(); vaddr = badvaddr & (PAGE_MASK << 1); write_c0_entryhi(vaddr | kvm_mips_get_kernel_asid(vcpu)); mtc0_tlbw_hazard(); write_c0_entrylo0(entrylo0); mtc0_tlbw_hazard(); write_c0_entrylo1(entrylo1); mtc0_tlbw_hazard(); write_c0_index(kvm_mips_get_commpage_asid(vcpu)); mtc0_tlbw_hazard(); tlb_write_indexed(); mtc0_tlbw_hazard(); tlbw_use_hazard(); kvm_debug("@ %#lx idx: %2d [entryhi(R): %#lx] entrylo0 (R): 0x%08lx, entrylo1(R): 0x%08lx\n", vcpu->arch.pc, read_c0_index(), read_c0_entryhi(), read_c0_entrylo0(), read_c0_entrylo1()); /* Restore old ASID */ write_c0_entryhi(old_entryhi); mtc0_tlbw_hazard(); tlbw_use_hazard(); local_irq_restore(flags); return 0; } EXPORT_SYMBOL_GPL(kvm_mips_handle_commpage_tlb_fault); int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, struct kvm_mips_tlb *tlb, unsigned long *hpa0, unsigned long *hpa1) { unsigned long entryhi = 0, entrylo0 = 0, entrylo1 = 0; struct kvm *kvm = vcpu->kvm; kvm_pfn_t pfn0, pfn1; if ((tlb->tlb_hi & VPN2_MASK) == 0) { pfn0 = 0; pfn1 = 0; } else { if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo0) >> PAGE_SHIFT) < 0) return -1; if (kvm_mips_map_page(kvm, mips3_tlbpfn_to_paddr(tlb->tlb_lo1) >> PAGE_SHIFT) < 0) return -1; pfn0 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo0) >> PAGE_SHIFT]; pfn1 = kvm->arch.guest_pmap[mips3_tlbpfn_to_paddr(tlb->tlb_lo1) >> PAGE_SHIFT]; } if (hpa0) *hpa0 = pfn0 << PAGE_SHIFT; if (hpa1) *hpa1 = pfn1 << PAGE_SHIFT; /* Get attributes from the Guest TLB */ entryhi = (tlb->tlb_hi & VPN2_MASK) | (KVM_GUEST_KERNEL_MODE(vcpu) ? kvm_mips_get_kernel_asid(vcpu) : kvm_mips_get_user_asid(vcpu)); entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) | (tlb->tlb_lo0 & MIPS3_PG_D) | (tlb->tlb_lo0 & MIPS3_PG_V); entrylo1 = mips3_paddr_to_tlbpfn(pfn1 << PAGE_SHIFT) | (0x3 << 3) | (tlb->tlb_lo1 & MIPS3_PG_D) | (tlb->tlb_lo1 & MIPS3_PG_V); kvm_debug("@ %#lx tlb_lo0: 0x%08lx tlb_lo1: 0x%08lx\n", vcpu->arch.pc, tlb->tlb_lo0, tlb->tlb_lo1); return kvm_mips_host_tlb_write(vcpu, entryhi, entrylo0, entrylo1, tlb->tlb_mask); } EXPORT_SYMBOL_GPL(kvm_mips_handle_mapped_seg_tlb_fault); int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long entryhi) { int i; int index = -1; struct kvm_mips_tlb *tlb = vcpu->arch.guest_tlb; for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) { if (TLB_HI_VPN2_HIT(tlb[i], entryhi) && TLB_HI_ASID_HIT(tlb[i], entryhi)) { index = i; break; } } kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n", __func__, entryhi, index, tlb[i].tlb_lo0, tlb[i].tlb_lo1); return index; } EXPORT_SYMBOL_GPL(kvm_mips_guest_tlb_lookup); int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr) { unsigned long old_entryhi, flags; int idx; local_irq_save(flags); old_entryhi = read_c0_entryhi(); if (KVM_GUEST_KERNEL_MODE(vcpu)) write_c0_entryhi((vaddr & VPN2_MASK) | kvm_mips_get_kernel_asid(vcpu)); else { write_c0_entryhi((vaddr & VPN2_MASK) | kvm_mips_get_user_asid(vcpu)); } mtc0_tlbw_hazard(); tlb_probe(); tlb_probe_hazard(); idx = read_c0_index(); /* Restore old ASID */ write_c0_entryhi(old_entryhi); mtc0_tlbw_hazard(); tlbw_use_hazard(); local_irq_restore(flags); kvm_debug("Host TLB lookup, %#lx, idx: %2d\n", vaddr, idx); return idx; } EXPORT_SYMBOL_GPL(kvm_mips_host_tlb_lookup); int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long va) { int idx; unsigned long flags, old_entryhi; local_irq_save(flags); old_entryhi = read_c0_entryhi(); write_c0_entryhi((va & VPN2_MASK) | kvm_mips_get_user_asid(vcpu)); mtc0_tlbw_hazard(); tlb_probe(); tlb_probe_hazard(); idx = read_c0_index(); if (idx >= current_cpu_data.tlbsize) BUG(); if (idx > 0) { write_c0_entryhi(UNIQUE_ENTRYHI(idx)); mtc0_tlbw_hazard(); write_c0_entrylo0(0); mtc0_tlbw_hazard(); write_c0_entrylo1(0); mtc0_tlbw_hazard(); tlb_write_indexed(); mtc0_tlbw_hazard(); } write_c0_entryhi(old_entryhi); mtc0_tlbw_hazard(); tlbw_use_hazard(); local_irq_restore(flags); if (idx > 0) kvm_debug("%s: Invalidated entryhi %#lx @ idx %d\n", __func__, (va & VPN2_MASK) | kvm_mips_get_user_asid(vcpu), idx); return 0; } EXPORT_SYMBOL_GPL(kvm_mips_host_tlb_inv); void kvm_mips_flush_host_tlb(int skip_kseg0) { unsigned long flags; unsigned long old_entryhi, entryhi; unsigned long old_pagemask; int entry = 0; int maxentry = current_cpu_data.tlbsize; local_irq_save(flags); old_entryhi = read_c0_entryhi(); old_pagemask = read_c0_pagemask(); /* Blast 'em all away. */ for (entry = 0; entry < maxentry; entry++) { write_c0_index(entry); mtc0_tlbw_hazard(); if (skip_kseg0) { tlb_read(); tlbw_use_hazard(); entryhi = read_c0_entryhi(); /* Don't blow away guest kernel entries */ if (KVM_GUEST_KSEGX(entryhi) == KVM_GUEST_KSEG0) continue; } /* Make sure all entries differ. */ write_c0_entryhi(UNIQUE_ENTRYHI(entry)); mtc0_tlbw_hazard(); write_c0_entrylo0(0); mtc0_tlbw_hazard(); write_c0_entrylo1(0); mtc0_tlbw_hazard(); tlb_write_indexed(); mtc0_tlbw_hazard(); } tlbw_use_hazard(); write_c0_entryhi(old_entryhi); write_c0_pagemask(old_pagemask); mtc0_tlbw_hazard(); tlbw_use_hazard(); local_irq_restore(flags); } EXPORT_SYMBOL_GPL(kvm_mips_flush_host_tlb); void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, struct kvm_vcpu *vcpu) { unsigned long asid = asid_cache(cpu); asid += ASID_INC; if (!(asid & ASID_MASK)) { if (cpu_has_vtag_icache) flush_icache_all(); kvm_local_flush_tlb_all(); /* start new asid cycle */ if (!asid) /* fix version if needed */ asid = ASID_FIRST_VERSION; } cpu_context(cpu, mm) = asid_cache(cpu) = asid; } void kvm_local_flush_tlb_all(void) { unsigned long flags; unsigned long old_ctx; int entry = 0; local_irq_save(flags); /* Save old context and create impossible VPN2 value */ old_ctx = read_c0_entryhi(); write_c0_entrylo0(0); write_c0_entrylo1(0); /* Blast 'em all away. */ while (entry < current_cpu_data.tlbsize) { /* Make sure all entries differ. */ write_c0_entryhi(UNIQUE_ENTRYHI(entry)); write_c0_index(entry); mtc0_tlbw_hazard(); tlb_write_indexed(); entry++; } tlbw_use_hazard(); write_c0_entryhi(old_ctx); mtc0_tlbw_hazard(); local_irq_restore(flags); } EXPORT_SYMBOL_GPL(kvm_local_flush_tlb_all); /** * kvm_mips_migrate_count() - Migrate timer. * @vcpu: Virtual CPU. * * Migrate CP0_Count hrtimer to the current CPU by cancelling and restarting it * if it was running prior to being cancelled. * * Must be called when the VCPU is migrated to a different CPU to ensure that * timer expiry during guest execution interrupts the guest and causes the * interrupt to be delivered in a timely manner. */ static void kvm_mips_migrate_count(struct kvm_vcpu *vcpu) { if (hrtimer_cancel(&vcpu->arch.comparecount_timer)) hrtimer_restart(&vcpu->arch.comparecount_timer); } /* Restore ASID once we are scheduled back after preemption */ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { unsigned long flags; int newasid = 0; kvm_debug("%s: vcpu %p, cpu: %d\n", __func__, vcpu, cpu); /* Alocate new kernel and user ASIDs if needed */ local_irq_save(flags); if ((vcpu->arch.guest_kernel_asid[cpu] ^ asid_cache(cpu)) & ASID_VERSION_MASK) { kvm_get_new_mmu_context(&vcpu->arch.guest_kernel_mm, cpu, vcpu); vcpu->arch.guest_kernel_asid[cpu] = vcpu->arch.guest_kernel_mm.context.asid[cpu]; kvm_get_new_mmu_context(&vcpu->arch.guest_user_mm, cpu, vcpu); vcpu->arch.guest_user_asid[cpu] = vcpu->arch.guest_user_mm.context.asid[cpu]; newasid++; kvm_debug("[%d]: cpu_context: %#lx\n", cpu, cpu_context(cpu, current->mm)); kvm_debug("[%d]: Allocated new ASID for Guest Kernel: %#x\n", cpu, vcpu->arch.guest_kernel_asid[cpu]); kvm_debug("[%d]: Allocated new ASID for Guest User: %#x\n", cpu, vcpu->arch.guest_user_asid[cpu]); } if (vcpu->arch.last_sched_cpu != cpu) { kvm_debug("[%d->%d]KVM VCPU[%d] switch\n", vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id); /* * Migrate the timer interrupt to the current CPU so that it * always interrupts the guest and synchronously triggers a * guest timer interrupt. */ kvm_mips_migrate_count(vcpu); } if (!newasid) { /* * If we preempted while the guest was executing, then reload * the pre-empted ASID */ if (current->flags & PF_VCPU) { write_c0_entryhi(vcpu->arch. preempt_entryhi & ASID_MASK); ehb(); } } else { /* New ASIDs were allocated for the VM */ /* * Were we in guest context? If so then the pre-empted ASID is * no longer valid, we need to set it to what it should be based * on the mode of the Guest (Kernel/User) */ if (current->flags & PF_VCPU) { if (KVM_GUEST_KERNEL_MODE(vcpu)) write_c0_entryhi(vcpu->arch. guest_kernel_asid[cpu] & ASID_MASK); else write_c0_entryhi(vcpu->arch. guest_user_asid[cpu] & ASID_MASK); ehb(); } } /* restore guest state to registers */ kvm_mips_callbacks->vcpu_set_regs(vcpu); local_irq_restore(flags); } EXPORT_SYMBOL_GPL(kvm_arch_vcpu_load); /* ASID can change if another task is scheduled during preemption */ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { unsigned long flags; uint32_t cpu; local_irq_save(flags); cpu = smp_processor_id(); vcpu->arch.preempt_entryhi = read_c0_entryhi(); vcpu->arch.last_sched_cpu = cpu; /* save guest state in registers */ kvm_mips_callbacks->vcpu_get_regs(vcpu); if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) & ASID_VERSION_MASK)) { kvm_debug("%s: Dropping MMU Context: %#lx\n", __func__, cpu_context(cpu, current->mm)); drop_mmu_context(current->mm, cpu); } write_c0_entryhi(cpu_asid(cpu, current->mm)); ehb(); local_irq_restore(flags); } EXPORT_SYMBOL_GPL(kvm_arch_vcpu_put); uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu) { struct mips_coproc *cop0 = vcpu->arch.cop0; unsigned long paddr, flags, vpn2, asid; uint32_t inst; int index; if (KVM_GUEST_KSEGX((unsigned long) opc) < KVM_GUEST_KSEG0 || KVM_GUEST_KSEGX((unsigned long) opc) == KVM_GUEST_KSEG23) { local_irq_save(flags); index = kvm_mips_host_tlb_lookup(vcpu, (unsigned long) opc); if (index >= 0) { inst = *(opc); } else { vpn2 = (unsigned long) opc & VPN2_MASK; asid = kvm_read_c0_guest_entryhi(cop0) & ASID_MASK; index = kvm_mips_guest_tlb_lookup(vcpu, vpn2 | asid); if (index < 0) { kvm_err("%s: get_user_failed for %p, vcpu: %p, ASID: %#lx\n", __func__, opc, vcpu, read_c0_entryhi()); kvm_mips_dump_host_tlbs(); local_irq_restore(flags); return KVM_INVALID_INST; } kvm_mips_handle_mapped_seg_tlb_fault(vcpu, &vcpu->arch. guest_tlb[index], NULL, NULL); inst = *(opc); } local_irq_restore(flags); } else if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) { paddr = kvm_mips_translate_guest_kseg0_to_hpa(vcpu, (unsigned long) opc); inst = *(uint32_t *) CKSEG0ADDR(paddr); } else { kvm_err("%s: illegal address: %p\n", __func__, opc); return KVM_INVALID_INST; } return inst; } EXPORT_SYMBOL_GPL(kvm_get_inst);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-20 01:49:50 -0400