Merge master.kernel.org:/home/rmk/linux-2.6-arm

author: Linus Torvalds <torvalds@g5.osdl.org> 2006-01-09 18:09:30 -0500
committer: Linus Torvalds <torvalds@g5.osdl.org> 2006-01-09 18:09:30 -0500
commit: 3995f4c5327595b51482bdac8c189736262eb6e0 (patch)
tree: ef768d0ecf243a2376bfc646b847964313146d3e
parent: 05814450070f13b671fc9dbf89477677aa0258cb (diff)
parent: fe38ea5623d262afc0b92ea47b8a7d8c988521d2 (diff)
135 files changed, 3346 insertions, 5052 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a74e3e5f916..50b9afa8ae6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -99,13 +99,6 @@ config ARCH_EBSA110
          Ethernet interface, two PCMCIA sockets, two serial ports and a
          parallel port.
-config ARCH_CAMELOT
-        bool "Epxa10db"
-        help
-          This enables support for Altera's Excalibur XA10 development board.
-          If you would like to build your kernel to run on one of these boards
-          then you must say 'Y' here. Otherwise say 'N'
 config ARCH_FOOTBRIDGE
        bool "FootBridge"
        select FOOTBRIDGE
@@ -213,12 +206,16 @@ config ARCH_AAEC2000
        help
          This enables support for systems based on the Agilent AAEC-2000
+config ARCH_AT91RM9200
+        bool "AT91RM9200"
+        help
+          Say Y here if you intend to run this kernel on an AT91RM9200-based
+          board.
 endchoice
 source "arch/arm/mach-clps711x/Kconfig"
-source "arch/arm/mach-epxa10db/Kconfig"
 source "arch/arm/mach-footbridge/Kconfig"
 source "arch/arm/mach-integrator/Kconfig"
@@ -253,6 +250,8 @@ source "arch/arm/mach-aaec2000/Kconfig"
 source "arch/arm/mach-realview/Kconfig"
+source "arch/arm/mach-at91rm9200/Kconfig"
 # Definitions to make life easier
 config ARCH_ACORN
        bool
@@ -418,7 +417,8 @@ config LEDS
                   ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
                   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
                   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
-                   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE
+                   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
+                   ARCH_AT91RM9200
        help
          If you say Y here, the LEDs on your machine will be used
          to provide useful information about your current system status.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index afaf3a1e903c..1fa2a1011584 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -84,7 +84,6 @@ endif
 machine-$(CONFIG_ARCH_PXA)        := pxa
 machine-$(CONFIG_ARCH_L7200)      := l7200
 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
- machine-$(CONFIG_ARCH_CAMELOT)    := epxa10db
 textofs-$(CONFIG_ARCH_CLPS711X)   := 0x00028000
 machine-$(CONFIG_ARCH_CLPS711X)   := clps711x
 machine-$(CONFIG_ARCH_IOP3XX)     := iop3xx
@@ -100,6 +99,7 @@ endif
 machine-$(CONFIG_ARCH_H720X)      := h720x
 machine-$(CONFIG_ARCH_AAEC2000)   := aaec2000
 machine-$(CONFIG_ARCH_REALVIEW)   := realview
+ machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 6b505ce41a75..35ffe0f4ece7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -21,10 +21,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
 OBJS            += head-shark.o ofw-shark.o
 endif
-ifeq ($(CONFIG_ARCH_CAMELOT),y)
-OBJS            += head-epxa10db.o
-endif
 ifeq ($(CONFIG_ARCH_L7200),y)
 OBJS            += head-l7200.o
 endif
@@ -50,6 +46,10 @@ ifeq ($(CONFIG_PXA_SHARPSL),y)
 OBJS            += head-sharpsl.o
 endif
+ifeq ($(CONFIG_ARCH_AT91RM9200),y)
+OBJS            += head-at91rm9200.o
+endif
 ifeq ($(CONFIG_DEBUG_ICEDCC),y)
 OBJS            += ice-dcc.o
 endif
diff --git a/arch/arm/boot/compressed/head-at91rm9200.S b/arch/arm/boot/compressed/head-at91rm9200.S
new file mode 100644
index 000000000000..2119ea62b547
--- /dev/null
+++ b/arch/arm/boot/compressed/head-at91rm9200.S
@@ -0,0 +1,57 @@
+/*
+ * linux/arch/arm/boot/compressed/head-at91rm9200.S
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <asm/mach-types.h>
+                .section        ".start", "ax"
+                @ Atmel AT91RM9200-DK : 262
+                mov     r3,     #(MACH_TYPE_AT91RM9200DK & 0xff)
+                orr     r3, r3, #(MACH_TYPE_AT91RM9200DK & 0xff00)
+                cmp     r7, r3
+                beq     99f
+                @ Cogent CSB337 : 399
+                mov     r3,     #(MACH_TYPE_CSB337 & 0xff)
+                orr     r3, r3, #(MACH_TYPE_CSB337 & 0xff00)
+                cmp     r7, r3
+                beq     99f
+                @ Cogent CSB637 : 648
+                mov     r3,     #(MACH_TYPE_CSB637 & 0xff)
+                orr     r3, r3, #(MACH_TYPE_CSB637 & 0xff00)
+                cmp     r7, r3
+                beq     99f
+                @ Atmel AT91RM9200-EK : 705
+                mov     r3,     #(MACH_TYPE_AT91RM9200EK & 0xff)
+                orr     r3, r3, #(MACH_TYPE_AT91RM9200EK & 0xff00)
+                cmp     r7, r3
+                beq     99f
+                @ Conitec Carmeva : 769
+                mov     r3,     #(MACH_TYPE_CARMEVA & 0xff)
+                orr     r3, r3, #(MACH_TYPE_CARMEVA & 0xff00)
+                cmp     r7, r3
+                beq     99f
+                @ KwikByte KB920x : 612
+                mov     r3,     #(MACH_TYPE_KB9200 & 0xff)
+                orr     r3, r3, #(MACH_TYPE_KB9200 & 0xff00)
+                cmp     r7, r3
+                beq     99f
+                @ Unknown board, use the AT91RM9200DK board
+                @ mov   r7, #MACH_TYPE_AT91RM9200
+                mov     r7,     #(MACH_TYPE_AT91RM9200DK & 0xff)
+                orr     r7, r7, #(MACH_TYPE_AT91RM9200DK & 0xff00)
+99:
diff --git a/arch/arm/boot/compressed/head-epxa10db.S b/arch/arm/boot/compressed/head-epxa10db.S
deleted file mode 100644
index 757681f12a39..000000000000
--- a/arch/arm/boot/compressed/head-epxa10db.S
+++ /dev/null
@@ -1,5 +0,0 @@
-#include <asm/mach-types.h>
-#include <asm/arch/excalibur.h>
-                .section        ".start", "ax"
-                mov     r7, #MACH_TYPE_CAMELOT
diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig
index ccbb4c0d58c4..089c9d598409 100644
--- a/arch/arm/configs/assabet_defconfig
+++ b/arch/arm/configs/assabet_defconfig
@@ -63,7 +63,6 @@ CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index 5d92af975d87..cfe6bd8e81cd 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -66,7 +66,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/bast_defconfig b/arch/arm/configs/bast_defconfig
index 35e3a99bcbb6..6886001b5366 100644
--- a/arch/arm/configs/bast_defconfig
+++ b/arch/arm/configs/bast_defconfig
@@ -64,7 +64,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig
index d8fe0f40408f..f81a60005cd3 100644
--- a/arch/arm/configs/cerfcube_defconfig
+++ b/arch/arm/configs/cerfcube_defconfig
@@ -65,7 +65,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/clps7500_defconfig b/arch/arm/configs/clps7500_defconfig
index 908758371405..af9ae5389131 100644
--- a/arch/arm/configs/clps7500_defconfig
+++ b/arch/arm/configs/clps7500_defconfig
@@ -57,7 +57,6 @@ CONFIG_ARCH_CLPS7500=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index 40dfe07a8bce..15468a0cf70e 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -71,7 +71,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index 06229026f78b..3c3461e83398 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -87,7 +87,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/ebsa110_defconfig b/arch/arm/configs/ebsa110_defconfig
index 6f61929b97a8..afcfff6140f2 100644
--- a/arch/arm/configs/ebsa110_defconfig
+++ b/arch/arm/configs/ebsa110_defconfig
@@ -63,7 +63,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 CONFIG_ARCH_EBSA110=y
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/edb7211_defconfig b/arch/arm/configs/edb7211_defconfig
index 78b08ed4d5f4..6ba7355ff85b 100644
--- a/arch/arm/configs/edb7211_defconfig
+++ b/arch/arm/configs/edb7211_defconfig
@@ -57,7 +57,6 @@ CONFIG_BASE_SMALL=0
 CONFIG_ARCH_CLPS711X=y
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/enp2611_defconfig b/arch/arm/configs/enp2611_defconfig
index fd7c0042bcca..9592e3925c79 100644
--- a/arch/arm/configs/enp2611_defconfig
+++ b/arch/arm/configs/enp2611_defconfig
@@ -86,7 +86,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/ep80219_defconfig b/arch/arm/configs/ep80219_defconfig
index 96342afa9c5f..fbe312e757cb 100644
--- a/arch/arm/configs/ep80219_defconfig
+++ b/arch/arm/configs/ep80219_defconfig
@@ -64,7 +64,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 CONFIG_ARCH_IOP3XX=y
diff --git a/arch/arm/configs/epxa10db_defconfig b/arch/arm/configs/epxa10db_defconfig
deleted file mode 100644
index 9fb8b58c4954..000000000000
--- a/arch/arm/configs/epxa10db_defconfig
+++ /dev/null
@@ -1,644 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Sun Mar 27 22:46:51 2005
-#
-CONFIG_ARM=y
-CONFIG_MMU=y
-CONFIG_UID16=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_IOMAP=y
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
-CONFIG_BROKEN_ON_SMP=y
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_KOBJECT_UEVENT=y
-# CONFIG_IKCONFIG is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-#
-# System Type
-#
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-CONFIG_ARCH_CAMELOT=y
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-#
-# Epxa10db
-#
-#
-# PLD hotswap support
-#
-CONFIG_PLD=y
-# CONFIG_PLD_HOTSWAP is not set
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_ARM922T=y
-CONFIG_CPU_32v4=y
-CONFIG_CPU_ABRT_EV4T=y
-CONFIG_CPU_CACHE_V4WT=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_TLB_V4WBI=y
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-#
-# Bus support
-#
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-#
-# Kernel Features
-#
-# CONFIG_PREEMPT is not set
-CONFIG_ALIGNMENT_TRAP=y
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyUA0,115200 initrd=0x00200000,8M root=/dev/ram0 rw"
-# CONFIG_XIP_KERNEL is not set
-#
-# Floating point emulation
-#
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
-#
-# Power management options
-#
-# CONFIG_PM is not set
-#
-# Device Drivers
-#
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-#
-# Plug and Play support
-#
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CDROM_PKTCDVD is not set
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_ATA_OVER_ETH is not set
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-#
-# Fusion MPT device support
-#
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
-# Networking support
-#
-CONFIG_NET=y
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_IP_TCPDIAG is not set
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-#
-# Ethernet (1000 Mbit)
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
-#
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-# CONFIG_PPP_BSDCOMP is not set
-# CONFIG_PPPOE is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-#
-# Input device support
-#
-CONFIG_INPUT=y
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_UART00=y
-CONFIG_SERIAL_UART00_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-#
-# Misc devices
-#
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB is not set
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-#
-# XFS support
-#
-# CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-#
-# Network File Systems
-#
-# CONFIG_NFS_FS is not set
-# CONFIG_NFSD is not set
-CONFIG_SMB_FS=y
-# CONFIG_SMB_NLS_DEFAULT is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_DEBUG_USER is not set
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-#
-# Hardware crypto devices
-#
-#
-# Library routines
-#
-CONFIG_CRC_CCITT=y
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig
index 9737c4850721..2a612d23120b 100644
--- a/arch/arm/configs/footbridge_defconfig
+++ b/arch/arm/configs/footbridge_defconfig
@@ -63,7 +63,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 CONFIG_ARCH_FOOTBRIDGE=y
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/fortunet_defconfig b/arch/arm/configs/fortunet_defconfig
index b6f688d850dc..65dc73a88c43 100644
--- a/arch/arm/configs/fortunet_defconfig
+++ b/arch/arm/configs/fortunet_defconfig
@@ -57,7 +57,6 @@ CONFIG_BASE_SMALL=0
 CONFIG_ARCH_CLPS711X=y
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index b9de07de80fe..7a0da0b7facb 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -65,7 +65,6 @@ CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/h7201_defconfig b/arch/arm/configs/h7201_defconfig
index 39c13a354541..116920aecef7 100644
--- a/arch/arm/configs/h7201_defconfig
+++ b/arch/arm/configs/h7201_defconfig
@@ -60,7 +60,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
index fbf5c244c696..9d62ed16bf57 100644
--- a/arch/arm/configs/h7202_defconfig
+++ b/arch/arm/configs/h7202_defconfig
@@ -63,7 +63,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
index fb41a36a5a68..a45b57582b86 100644
--- a/arch/arm/configs/hackkit_defconfig
+++ b/arch/arm/configs/hackkit_defconfig
@@ -66,7 +66,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 27ee76825254..d1ba7fdde818 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -65,7 +65,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 CONFIG_ARCH_INTEGRATOR=y
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/iq31244_defconfig b/arch/arm/configs/iq31244_defconfig
index e71443b97390..c07628ceaf0c 100644
--- a/arch/arm/configs/iq31244_defconfig
+++ b/arch/arm/configs/iq31244_defconfig
@@ -65,7 +65,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 CONFIG_ARCH_IOP3XX=y
diff --git a/arch/arm/configs/iq80321_defconfig b/arch/arm/configs/iq80321_defconfig
index ab5ad23b27da..18fa1615fdfd 100644
--- a/arch/arm/configs/iq80321_defconfig
+++ b/arch/arm/configs/iq80321_defconfig
@@ -64,7 +64,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 CONFIG_ARCH_IOP3XX=y
diff --git a/arch/arm/configs/iq80331_defconfig b/arch/arm/configs/iq80331_defconfig
index bb536133ef87..f50035de1fff 100644
--- a/arch/arm/configs/iq80331_defconfig
+++ b/arch/arm/configs/iq80331_defconfig
@@ -64,7 +64,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 CONFIG_ARCH_IOP3XX=y
diff --git a/arch/arm/configs/iq80332_defconfig b/arch/arm/configs/iq80332_defconfig
index 305f01f3a729..18b3f372ed68 100644
--- a/arch/arm/configs/iq80332_defconfig
+++ b/arch/arm/configs/iq80332_defconfig
@@ -64,7 +64,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 CONFIG_ARCH_IOP3XX=y
diff --git a/arch/arm/configs/ixdp2400_defconfig b/arch/arm/configs/ixdp2400_defconfig
index e6a4d2656fe5..d9d6bb86a6fa 100644
--- a/arch/arm/configs/ixdp2400_defconfig
+++ b/arch/arm/configs/ixdp2400_defconfig
@@ -86,7 +86,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/ixdp2401_defconfig b/arch/arm/configs/ixdp2401_defconfig
index 5572cf95d5f8..2dc9d499c7d7 100644
--- a/arch/arm/configs/ixdp2401_defconfig
+++ b/arch/arm/configs/ixdp2401_defconfig
@@ -86,7 +86,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/ixdp2800_defconfig b/arch/arm/configs/ixdp2800_defconfig
index 0fddbde85835..4248123815e9 100644
--- a/arch/arm/configs/ixdp2800_defconfig
+++ b/arch/arm/configs/ixdp2800_defconfig
@@ -86,7 +86,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/ixdp2801_defconfig b/arch/arm/configs/ixdp2801_defconfig
index 89b9aa06aa91..ea8f4b478fa3 100644
--- a/arch/arm/configs/ixdp2801_defconfig
+++ b/arch/arm/configs/ixdp2801_defconfig
@@ -86,7 +86,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index 613afab62720..4975b914f923 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -85,7 +85,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index b88aeba82bc0..ad1048db96fb 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -63,7 +63,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig
index 7033829ed145..c3a932844160 100644
--- a/arch/arm/configs/lart_defconfig
+++ b/arch/arm/configs/lart_defconfig
@@ -62,7 +62,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig
index d64706d3ff35..67eaa26c2647 100644
--- a/arch/arm/configs/lpd7a400_defconfig
+++ b/arch/arm/configs/lpd7a400_defconfig
@@ -60,7 +60,6 @@ CONFIG_BASE_SMALL=0
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
index 87cbedfb303f..208d591ebfce 100644
--- a/arch/arm/configs/lpd7a404_defconfig
+++ b/arch/arm/configs/lpd7a404_defconfig
@@ -60,7 +60,6 @@ CONFIG_BASE_SMALL=0
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
index 4bc8717c6f57..81daadcbe0ba 100644
--- a/arch/arm/configs/lubbock_defconfig
+++ b/arch/arm/configs/lubbock_defconfig
@@ -63,7 +63,6 @@ CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/lusl7200_defconfig b/arch/arm/configs/lusl7200_defconfig
index 3ca64cabc92c..42f6a77bc3c0 100644
--- a/arch/arm/configs/lusl7200_defconfig
+++ b/arch/arm/configs/lusl7200_defconfig
@@ -62,7 +62,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
index 153d68594beb..b112bd75bda2 100644
--- a/arch/arm/configs/mainstone_defconfig
+++ b/arch/arm/configs/mainstone_defconfig
@@ -63,7 +63,6 @@ CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/mx1ads_defconfig b/arch/arm/configs/mx1ads_defconfig
index 6517d167acf0..d16f6cd6e039 100644
--- a/arch/arm/configs/mx1ads_defconfig
+++ b/arch/arm/configs/mx1ads_defconfig
@@ -63,7 +63,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
index 7fb1f7c7bf43..3d35255c64ed 100644
--- a/arch/arm/configs/neponset_defconfig
+++ b/arch/arm/configs/neponset_defconfig
@@ -65,7 +65,6 @@ CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig
index 6e81acf94c2f..2cae1ead9f9b 100644
--- a/arch/arm/configs/netwinder_defconfig
+++ b/arch/arm/configs/netwinder_defconfig
@@ -58,7 +58,6 @@ CONFIG_BASE_SMALL=0
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 CONFIG_ARCH_FOOTBRIDGE=y
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig
index 529f0f72e1e9..ee3ecbd9002d 100644
--- a/arch/arm/configs/omap_h2_1610_defconfig
+++ b/arch/arm/configs/omap_h2_1610_defconfig
@@ -85,7 +85,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig
index 10fec890578d..24e8bdd4cb91 100644
--- a/arch/arm/configs/pleb_defconfig
+++ b/arch/arm/configs/pleb_defconfig
@@ -63,7 +63,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig
index 21c327883d8c..b71d31a4bb56 100644
--- a/arch/arm/configs/pxa255-idp_defconfig
+++ b/arch/arm/configs/pxa255-idp_defconfig
@@ -63,7 +63,6 @@ CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 0485b2f1cc20..3f1ec4e304f7 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -65,7 +65,6 @@ CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index 19184c1010ad..b498afdc03b6 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -66,7 +66,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index 3f97590c91f2..33f31080a98c 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -85,7 +85,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig
index e3facc4fe792..d052c8f80515 100644
--- a/arch/arm/configs/shannon_defconfig
+++ b/arch/arm/configs/shannon_defconfig
@@ -62,7 +62,6 @@ CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig
index 271823f0d708..c48d17062262 100644
--- a/arch/arm/configs/shark_defconfig
+++ b/arch/arm/configs/shark_defconfig
@@ -66,7 +66,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig
index 5373eeb7d578..2e5a616cc98d 100644
--- a/arch/arm/configs/simpad_defconfig
+++ b/arch/arm/configs/simpad_defconfig
@@ -64,7 +64,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/smdk2410_defconfig b/arch/arm/configs/smdk2410_defconfig
index 2c60865fda19..4d123d33c7df 100644
--- a/arch/arm/configs/smdk2410_defconfig
+++ b/arch/arm/configs/smdk2410_defconfig
@@ -58,7 +58,6 @@ CONFIG_BASE_SMALL=0
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index 9895539533d6..d1ace3abfd8a 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -87,7 +87,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index d72f2c754268..2687a225aa6a 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -64,7 +64,6 @@ CONFIG_KMOD=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_IOP3XX is not set
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index b5645c4462cf..1d50d2b98f55 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -710,7 +710,8 @@ int setup_irq(unsigned int irq, struct irqaction *new)
                desc->pending = 0;
                desc->disable_depth = 1;
-                if (new->flags & SA_TRIGGER_MASK) {
+                if (new->flags & SA_TRIGGER_MASK &&
+                    desc->chip->set_type) {
                        unsigned int type = new->flags & SA_TRIGGER_MASK;
                        desc->chip->set_type(irq, type);
                }
diff --git a/arch/arm/mach-at91rm9200/Kconfig b/arch/arm/mach-at91rm9200/Kconfig
new file mode 100644
index 000000000000..4b7218fc3eb1
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/Kconfig
@@ -0,0 +1,54 @@
+if ARCH_AT91RM9200
+menu "AT91RM9200 Implementations"
+comment "AT91RM9200 Board Type"
+config ARCH_AT91RM9200DK
+        bool "Atmel AT91RM9200-DK Development board"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using Atmel's AT91RM9200-DK Development board
+config MACH_AT91RM9200EK
+        bool "Atmel AT91RM9200-EK Evaluation Kit"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit
+config MACH_CSB337
+        bool "Cogent CSB337 board"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using Cogent's CSB337 board
+config MACH_CSB637
+        bool "Cogent CSB637 board"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using Cogent's CSB637 board
+config MACH_CARMEVA
+        bool "Conitec's ARM&EVA"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using Conitec's AT91RM9200-MCU-Module
+config MACH_KB9200
+        bool "KwikByte's KB920x"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using KwikByte's KB920x board
+comment "AT91RM9200 Feature Selections"
+config AT91_PROGRAMMABLE_CLOCKS
+        bool "Programmable Clocks"
+        help
+          Select this if you need to program one or more of the PCK0..PCK3
+          programmable clock outputs.
+endmenu
+endif
diff --git a/arch/arm/mach-at91rm9200/Makefile b/arch/arm/mach-at91rm9200/Makefile
new file mode 100644
index 000000000000..1f2805ca6e21
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/Makefile
@@ -0,0 +1,27 @@
+#
+# Makefile for the linux kernel.
+#
+obj-y           := clock.o irq.o time.o gpio.o common.o devices.o
+obj-m           :=
+obj-n           :=
+obj-            :=
+# Board-specific support
+#obj-$(CONFIG_ARCH_AT91RM9200DK)        += board-dk.o
+#obj-$(CONFIG_MACH_AT91RM9200EK)        += board-ek.o
+#obj-$(CONFIG_MACH_CSB337)      += board-csb337.o
+#obj-$(CONFIG_MACH_CSB637)      += board-csb637.o
+#obj-$(CONFIG_MACH_CARMEVA)     += board-carmeva.o
+#obj-$(CONFIG_MACH_KB9200)      += board-kb9202.o
+# LEDs support
+#led-$(CONFIG_ARCH_AT91RM9200DK)        += leds.o
+#led-$(CONFIG_MACH_AT91RM9200EK)        += leds.o
+#led-$(CONFIG_MACH_CSB337)      += leds.o
+#led-$(CONFIG_MACH_CSB637)      += leds.o
+#led-$(CONFIG_MACH_KB9200)      += leds.o
+obj-$(CONFIG_LEDS) += $(led-y)
+# VGA support
+#obj-$(CONFIG_FB_S1D13XXX)      += ics1523.o
diff --git a/arch/arm/mach-at91rm9200/Makefile.boot b/arch/arm/mach-at91rm9200/Makefile.boot
new file mode 100644
index 000000000000..e667dcc7cd34
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/Makefile.boot
@@ -0,0 +1,9 @@
+# Note: the following conditions must always be true:
+#   ZRELADDR == virt_to_phys(TEXTADDR)
+#   PARAMS_PHYS must be within 4MB of ZRELADDR
+#   INITRD_PHYS must be in RAM
+   zreladdr-y   := 0x20008000
+params_phys-y   := 0x20000100
+initrd_phys-y   := 0x20410000
diff --git a/arch/arm/mach-at91rm9200/clock.c b/arch/arm/mach-at91rm9200/clock.c
new file mode 100644
index 000000000000..ec8195a2a3cc
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/clock.c
@@ -0,0 +1,620 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/clock.c
+ *
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <asm/semaphore.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/board.h>             /* for master clock global */
+#include "generic.h"
+#undef  DEBUG
+/*
+ * There's a lot more which can be done with clocks, including cpufreq
+ * integration, slow clock mode support (for system suspend), letting
+ * PLLB be used at other rates (on boards that don't need USB), etc.
+ */
+struct clk {
+        const char      *name;
+        unsigned long   rate_hz;
+        struct clk      *parent;
+        u32             pmc_mask;
+        void            (*mode)(struct clk *, int);
+        unsigned        id:2;           /* PCK0..3, or 32k/main/a/b */
+        unsigned        primary:1;
+        unsigned        pll:1;
+        unsigned        programmable:1;
+        u16             users;
+};
+static spinlock_t       clk_lock;
+static u32              at91_pllb_usb_init;
+/*
+ * Four primary clock sources:  two crystal oscillators (32K, main), and
+ * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
+ * 48 MHz (unless no USB function clocks are needed).  The main clock and
+ * both PLLs are turned off to run in "slow clock mode" (system suspend).
+ */
+static struct clk clk32k = {
+        .name           = "clk32k",
+        .rate_hz        = AT91_SLOW_CLOCK,
+        .users          = 1,            /* always on */
+        .id             = 0,
+        .primary        = 1,
+};
+static struct clk main_clk = {
+        .name           = "main",
+        .pmc_mask       = 1 << 0,       /* in PMC_SR */
+        .users          = 1,
+        .id             = 1,
+        .primary        = 1,
+};
+static struct clk plla = {
+        .name           = "plla",
+        .parent         = &main_clk,
+        .pmc_mask       = 1 << 1,       /* in PMC_SR */
+        .id             = 2,
+        .primary        = 1,
+        .pll            = 1,
+};
+static void pllb_mode(struct clk *clk, int is_on)
+{
+        u32     value;
+        if (is_on) {
+                is_on = AT91_PMC_LOCKB;
+                value = at91_pllb_usb_init;
+        } else
+                value = 0;
+        at91_sys_write(AT91_CKGR_PLLBR, value);
+        do {
+                cpu_relax();
+        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
+}
+static struct clk pllb = {
+        .name           = "pllb",
+        .parent         = &main_clk,
+        .pmc_mask       = 1 << 2,       /* in PMC_SR */
+        .mode           = pllb_mode,
+        .id             = 3,
+        .primary        = 1,
+        .pll            = 1,
+};
+static void pmc_sys_mode(struct clk *clk, int is_on)
+{
+        if (is_on)
+                at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
+        else
+                at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
+}
+/* USB function clocks (PLLB must be 48 MHz) */
+static struct clk udpck = {
+        .name           = "udpck",
+        .parent         = &pllb,
+        .pmc_mask       = AT91_PMC_UDP,
+        .mode           = pmc_sys_mode,
+};
+static struct clk uhpck = {
+        .name           = "uhpck",
+        .parent         = &pllb,
+        .pmc_mask       = AT91_PMC_UHP,
+        .mode           = pmc_sys_mode,
+};
+#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
+/*
+ * The four programmable clocks can be parented by any primary clock.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .mode           = pmc_sys_mode,
+        .programmable   = 1,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .mode           = pmc_sys_mode,
+        .programmable   = 1,
+        .id             = 1,
+};
+static struct clk pck2 = {
+        .name           = "pck2",
+        .pmc_mask       = AT91_PMC_PCK2,
+        .mode           = pmc_sys_mode,
+        .programmable   = 1,
+        .id             = 2,
+};
+static struct clk pck3 = {
+        .name           = "pck3",
+        .pmc_mask       = AT91_PMC_PCK3,
+        .mode           = pmc_sys_mode,
+        .programmable   = 1,
+        .id             = 3,
+};
+#endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
+/*
+ * The master clock is divided from the CPU clock (by 1-4).  It's used for
+ * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
+ * (e.g baud rate generation).  It's sourced from one of the primary clocks.
+ */
+static struct clk mck = {
+        .name           = "mck",
+        .pmc_mask       = 1 << 3,       /* in PMC_SR */
+        .users          = 1,            /* (must be) always on */
+};
+static void pmc_periph_mode(struct clk *clk, int is_on)
+{
+        if (is_on)
+                at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
+        else
+                at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
+}
+static struct clk udc_clk = {
+        .name           = "udc_clk",
+        .parent         = &mck,
+        .pmc_mask       = 1 << AT91_ID_UDP,
+        .mode           = pmc_periph_mode,
+};
+static struct clk ohci_clk = {
+        .name           = "ohci_clk",
+        .parent         = &mck,
+        .pmc_mask       = 1 << AT91_ID_UHP,
+        .mode           = pmc_periph_mode,
+};
+static struct clk *const clock_list[] = {
+        /* four primary clocks -- MUST BE FIRST! */
+        &clk32k,
+        &main_clk,
+        &plla,
+        &pllb,
+        /* PLLB children (USB) */
+        &udpck,
+        &uhpck,
+#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
+        /* programmable clocks */
+        &pck0,
+        &pck1,
+        &pck2,
+        &pck3,
+#endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
+        /* MCK and peripherals */
+        &mck,
+        // usart0..usart3
+        // mmc
+        &udc_clk,
+        // i2c
+        // spi
+        // ssc0..ssc2
+        // tc0..tc5
+        &ohci_clk,
+        // ether
+};
+/* clocks are all static for now; no refcounting necessary */
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
+                if (strcmp(id, clock_list[i]->name) == 0)
+                        return clock_list[i];
+        }
+        return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+static void __clk_enable(struct clk *clk)
+{
+        if (clk->parent)
+                __clk_enable(clk->parent);
+        if (clk->users++ == 0 && clk->mode)
+                clk->mode(clk, 1);
+}
+int clk_enable(struct clk *clk)
+{
+        unsigned long   flags;
+        spin_lock_irqsave(&clk_lock, flags);
+        __clk_enable(clk);
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+static void __clk_disable(struct clk *clk)
+{
+        BUG_ON(clk->users == 0);
+        if (--clk->users == 0 && clk->mode)
+                clk->mode(clk, 0);
+        if (clk->parent)
+                __clk_disable(clk->parent);
+}
+void clk_disable(struct clk *clk)
+{
+        unsigned long   flags;
+        spin_lock_irqsave(&clk_lock, flags);
+        __clk_disable(clk);
+        spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long   flags;
+        unsigned long   rate;
+        spin_lock_irqsave(&clk_lock, flags);
+        for (;;) {
+                rate = clk->rate_hz;
+                if (rate || !clk->parent)
+                        break;
+                clk = clk->parent;
+        }
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+/*------------------------------------------------------------------------*/
+#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
+/*
+ * For now, only the programmable clocks support reparenting (MCK could
+ * do this too, with care) or rate changing (the PLLs could do this too,
+ * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
+ * a better rate match; we don't.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long   flags;
+        unsigned        prescale;
+        unsigned long   actual;
+        if (!clk->programmable)
+                return -EINVAL;
+        spin_lock_irqsave(&clk_lock, flags);
+        actual = clk->parent->rate_hz;
+        for (prescale = 0; prescale < 7; prescale++) {
+                if (actual && actual <= rate)
+                        break;
+                actual >>= 1;
+        }
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return (prescale < 7) ? actual : -ENOENT;
+}
+EXPORT_SYMBOL(clk_round_rate);
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long   flags;
+        unsigned        prescale;
+        unsigned long   actual;
+        if (!clk->programmable)
+                return -EINVAL;
+        if (clk->users)
+                return -EBUSY;
+        spin_lock_irqsave(&clk_lock, flags);
+        actual = clk->parent->rate_hz;
+        for (prescale = 0; prescale < 7; prescale++) {
+                if (actual && actual <= rate) {
+                        u32     pckr;
+                        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+                        pckr &= 0x03;
+                        pckr |= prescale << 2;
+                        at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
+                        clk->rate_hz = actual;
+                        break;
+                }
+                actual >>= 1;
+        }
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return (prescale < 7) ? actual : -ENOENT;
+}
+EXPORT_SYMBOL(clk_set_rate);
+struct clk *clk_get_parent(struct clk *clk)
+{
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        unsigned long   flags;
+        if (clk->users)
+                return -EBUSY;
+        if (!parent->primary || !clk->programmable)
+                return -EINVAL;
+        spin_lock_irqsave(&clk_lock, flags);
+        clk->rate_hz = parent->rate_hz;
+        clk->parent = parent;
+        at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+#endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
+/*------------------------------------------------------------------------*/
+#ifdef CONFIG_DEBUG_FS
+static int at91_clk_show(struct seq_file *s, void *unused)
+{
+        u32             scsr, pcsr, sr;
+        unsigned        i;
+        seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
+        seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
+        seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
+        seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
+        seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
+        seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
+        seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
+        for (i = 0; i < 4; i++)
+                seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
+        seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
+        seq_printf(s, "\n");
+        for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
+                char            *state;
+                struct clk      *clk = clock_list[i];
+                if (clk->mode == pmc_sys_mode)
+                        state = (scsr & clk->pmc_mask) ? "on" : "off";
+                else if (clk->mode == pmc_periph_mode)
+                        state = (pcsr & clk->pmc_mask) ? "on" : "off";
+                else if (clk->pmc_mask)
+                        state = (sr & clk->pmc_mask) ? "on" : "off";
+                else if (clk == &clk32k || clk == &main_clk)
+                        state = "on";
+                else
+                        state = "";
+                seq_printf(s, "%-10s users=%d %-3s %9ld Hz %s\n",
+                        clk->name, clk->users, state, clk_get_rate(clk),
+                        clk->parent ? clk->parent->name : "");
+        }
+        return 0;
+}
+static int at91_clk_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, at91_clk_show, NULL);
+}
+static struct file_operations at91_clk_operations = {
+        .open           = at91_clk_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+static int __init at91_clk_debugfs_init(void)
+{
+        /* /sys/kernel/debug/at91_clk */
+        (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
+        return 0;
+}
+postcore_initcall(at91_clk_debugfs_init);
+#endif
+/*------------------------------------------------------------------------*/
+static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
+{
+        unsigned mul, div;
+        div = reg & 0xff;
+        mul = (reg >> 16) & 0x7ff;
+        if (div && mul) {
+                freq /= div;
+                freq *= mul + 1;
+        } else
+                freq = 0;
+        if (pll == &pllb && (reg & (1 << 28)))
+                freq /= 2;
+        return freq;
+}
+static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
+{
+        unsigned i, div = 0, mul = 0, diff = 1 << 30;
+        unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+        /* PLL output max 240 MHz (or 180 MHz per errata) */
+        if (out_freq > 240000000)
+                goto fail;
+        for (i = 1; i < 256; i++) {
+                int diff1;
+                unsigned input, mul1;
+                /*
+                 * PLL input between 1MHz and 32MHz per spec, but lower
+                 * frequences seem necessary in some cases so allow 100K.
+                 */
+                input = main_freq / i;
+                if (input < 100000)
+                        continue;
+                if (input > 32000000)
+                        continue;
+                mul1 = out_freq / input;
+                if (mul1 > 2048)
+                        continue;
+                if (mul1 < 2)
+                        goto fail;
+                diff1 = out_freq - input * mul1;
+                if (diff1 < 0)
+                        diff1 = -diff1;
+                if (diff > diff1) {
+                        diff = diff1;
+                        div = i;
+                        mul = mul1;
+                        if (diff == 0)
+                                break;
+                }
+        }
+        if (i == 256 && diff > (out_freq >> 5))
+                goto fail;
+        return ret | ((mul - 1) << 16) | div;
+fail:
+        return 0;
+}
+int __init at91_clock_init(unsigned long main_clock)
+{
+        unsigned tmp, freq, mckr;
+        spin_lock_init(&clk_lock);
+        /*
+         * When the bootloader initialized the main oscillator correctly,
+         * there's no problem using the cycle counter.  But if it didn't,
+         * or when using oscillator bypass mode, we must be told the speed
+         * of the main clock.
+         */
+        if (!main_clock) {
+                do {
+                        tmp = at91_sys_read(AT91_CKGR_MCFR);
+                } while (!(tmp & 0x10000));
+                main_clock = (tmp & 0xffff) * (AT91_SLOW_CLOCK / 16);
+        }
+        main_clk.rate_hz = main_clock;
+        /* report if PLLA is more than mildly overclocked */
+        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+        if (plla.rate_hz > 209000000)
+                pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+        /*
+         * USB clock init:  choose 48 MHz PLLB value, turn all clocks off,
+         * disable 48MHz clock during usb peripheral suspend.
+         *
+         * REVISIT:  assumes MCK doesn't derive from PLLB!
+         */
+        at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | 0x10000000;
+        pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+        at91_sys_write(AT91_PMC_PCDR, (1 << AT91_ID_UHP) | (1 << AT91_ID_UDP));
+        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
+        at91_sys_write(AT91_CKGR_PLLBR, 0);
+        at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
+        /*
+         * MCK and CPU derive from one of those primary clocks.
+         * For now, assume this parentage won't change.
+         */
+        mckr = at91_sys_read(AT91_PMC_MCKR);
+        mck.parent = clock_list[mckr & AT91_PMC_CSS];
+        mck.parent->users++;
+        freq = mck.parent->rate_hz;
+        freq /= (1 << ((mckr >> 2) & 3));               /* prescale */
+        mck.rate_hz = freq / (1 + ((mckr >> 8) & 3));   /* mdiv */
+        printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+                freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+                (unsigned) main_clock / 1000000,
+                ((unsigned) main_clock % 1000000) / 1000);
+        /* FIXME get rid of master_clock global */
+        at91_master_clock = mck.rate_hz;
+#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
+        /* establish PCK0..PCK3 parentage */
+        for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
+                struct clk      *clk = clock_list[tmp], *parent;
+                u32             pckr;
+                if (!clk->programmable)
+                        continue;
+                pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+                parent = clock_list[pckr & 3];
+                clk->parent = parent;
+                clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
+        }
+#else
+        /* disable unused clocks */
+        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
+#endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
+        /* FIXME several unused clocks may still be active...  provide
+         * a CONFIG option to turn off all unused clocks at some point
+         * before driver init starts.
+         */
+        return 0;
+}
diff --git a/arch/arm/mach-at91rm9200/common.c b/arch/arm/mach-at91rm9200/common.c
new file mode 100644
index 000000000000..3848fd2d5596
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/common.c
@@ -0,0 +1,115 @@
+/*
+ * arch/arm/mach-at91rm9200/common.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/arch/hardware.h>
+static struct map_desc at91rm9200_io_desc[] __initdata = {
+        {
+                .virtual        = AT91_VA_BASE_SYS,
+                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_SPI,
+                .pfn            = __phys_to_pfn(AT91_BASE_SPI),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_SSC2,
+                .pfn            = __phys_to_pfn(AT91_BASE_SSC2),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_SSC1,
+                .pfn            = __phys_to_pfn(AT91_BASE_SSC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_SSC0,
+                .pfn            = __phys_to_pfn(AT91_BASE_SSC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_US3,
+                .pfn            = __phys_to_pfn(AT91_BASE_US3),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_US2,
+                .pfn            = __phys_to_pfn(AT91_BASE_US2),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_US1,
+                .pfn            = __phys_to_pfn(AT91_BASE_US1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_US0,
+                .pfn            = __phys_to_pfn(AT91_BASE_US0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_EMAC,
+                .pfn            = __phys_to_pfn(AT91_BASE_EMAC),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_TWI,
+                .pfn            = __phys_to_pfn(AT91_BASE_TWI),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_MCI,
+                .pfn            = __phys_to_pfn(AT91_BASE_MCI),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_UDP,
+                .pfn            = __phys_to_pfn(AT91_BASE_UDP),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_TCB1,
+                .pfn            = __phys_to_pfn(AT91_BASE_TCB1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_VA_BASE_TCB0,
+                .pfn            = __phys_to_pfn(AT91_BASE_TCB0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        },
+};
+void __init at91rm9200_map_io(void)
+{
+        iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
+}
+unsigned long at91_master_clock;
+EXPORT_SYMBOL(at91_master_clock);
+int at91_serial_map[AT91_NR_UART];
+int at91_console_port;
+EXPORT_SYMBOL(at91_serial_map);
+EXPORT_SYMBOL(at91_console_port);
diff --git a/arch/arm/mach-at91rm9200/devices.c b/arch/arm/mach-at91rm9200/devices.c
new file mode 100644
index 000000000000..8df3e5245651
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/devices.c
@@ -0,0 +1,291 @@
+/*
+ * arch/arm/mach-at91rm9200/devices.c
+ *
+ *  Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
+ *  Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <linux/config.h>
+#include <linux/platform_device.h>
+#include <asm/arch/board.h>
+#include <asm/arch/pio.h>
+/* --------------------------------------------------------------------
+ *  USB Host
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = 0xffffffffUL;
+static struct at91_usbh_data usbh_data;
+static struct resource at91rm9200_usbh_resource[] = {
+        [0] = {
+                .start  = AT91_UHP_BASE,
+                .end    = AT91_UHP_BASE + SZ_1M -1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_UHP,
+                .end    = AT91_ID_UHP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91rm9200_usbh_device = {
+        .name           = "at91rm9200-ohci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ohci_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &usbh_data,
+        },
+        .resource       = at91rm9200_usbh_resource,
+        .num_resources  = ARRAY_SIZE(at91rm9200_usbh_resource),
+};
+void __init at91_add_device_usbh(struct at91_usbh_data *data)
+{
+        if (!data)
+                return;
+        usbh_data = *data;
+        platform_device_register(&at91rm9200_usbh_device);
+}
+#else
+void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  USB Device (Gadget)
+ * -------------------------------------------------------------------- */
+#ifdef CONFIG_USB_GADGET_AT91
+static struct at91_udc_data udc_data;
+static struct resource at91_udc_resources[] = {
+        {
+                .start  = AT91_BASE_UDP,
+                .end    = AT91_BASE_UDP + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device at91rm9200_udc_device = {
+        .name           = "at91_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data          = &udc_data,
+        },
+        .resource       = at91_udc_resources,
+        .num_resources  = ARRAY_SIZE(at91_udc_resources),
+};
+void __init at91_add_device_udc(struct at91_udc_data *data)
+{
+        if (!data)
+                return;
+        if (data->vbus_pin) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+        }
+        if (data->pullup_pin)
+                at91_set_gpio_output(data->pullup_pin, 0);
+        udc_data = *data;
+        platform_device_register(&at91rm9200_udc_device);
+}
+#else
+void __init at91_add_device_udc(struct at91_udc_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
+static u64 eth_dmamask = 0xffffffffUL;
+static struct at91_eth_data eth_data;
+static struct platform_device at91rm9200_eth_device = {
+        .name           = "at91_ether",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &eth_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &eth_data,
+        },
+        .num_resources  = 0,
+};
+void __init at91_add_device_eth(struct at91_eth_data *data)
+{
+        if (!data)
+                return;
+        if (data->phy_irq_pin) {
+                at91_set_gpio_input(data->phy_irq_pin, 0);
+                at91_set_deglitch(data->phy_irq_pin, 1);
+        }
+        /* Pins used for MII and RMII */
+        at91_set_A_periph(AT91_PIN_PA16, 0);    /* EMDIO */
+        at91_set_A_periph(AT91_PIN_PA15, 0);    /* EMDC */
+        at91_set_A_periph(AT91_PIN_PA14, 0);    /* ERXER */
+        at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
+        at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
+        at91_set_A_periph(AT91_PIN_PA11, 0);    /* ECRS_ECRSDV */
+        at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX1 */
+        at91_set_A_periph(AT91_PIN_PA9, 0);     /* ETX0 */
+        at91_set_A_periph(AT91_PIN_PA8, 0);     /* ETXEN */
+        at91_set_A_periph(AT91_PIN_PA7, 0);     /* ETXCK_EREFCK */
+        if (!data->is_rmii) {
+                at91_set_B_periph(AT91_PIN_PB19, 0);    /* ERXCK */
+                at91_set_B_periph(AT91_PIN_PB18, 0);    /* ECOL */
+                at91_set_B_periph(AT91_PIN_PB17, 0);    /* ERXDV */
+                at91_set_B_periph(AT91_PIN_PB16, 0);    /* ERX3 */
+                at91_set_B_periph(AT91_PIN_PB15, 0);    /* ERX2 */
+                at91_set_B_periph(AT91_PIN_PB14, 0);    /* ETXER */
+                at91_set_B_periph(AT91_PIN_PB13, 0);    /* ETX3 */
+                at91_set_B_periph(AT91_PIN_PB12, 0);    /* ETX2 */
+        }
+        eth_data = *data;
+        platform_device_register(&at91rm9200_eth_device);
+}
+#else
+void __init at91_add_device_eth(struct at91_eth_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  Compact Flash / PCMCIA
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
+static struct at91_cf_data cf_data;
+static struct platform_device at91rm9200_cf_device = {
+        .name           = "at91_cf",
+        .id             = -1,
+        .dev            = {
+                                .platform_data          = &cf_data,
+        },
+        .num_resources  = 0,
+};
+void __init at91_add_device_cf(struct at91_cf_data *data)
+{
+        if (!data)
+                return;
+        /* input/irq */
+        if (data->irq_pin) {
+                at91_set_gpio_input(data->irq_pin, 1);
+                at91_set_deglitch(data->irq_pin, 1);
+        }
+        at91_set_gpio_input(data->det_pin, 1);
+        at91_set_deglitch(data->det_pin, 1);
+        /* outputs, initially off */
+        if (data->vcc_pin)
+                at91_set_gpio_output(data->vcc_pin, 0);
+        at91_set_gpio_output(data->rst_pin, 0);
+        cf_data = *data;
+        platform_device_register(&at91rm9200_cf_device);
+}
+#else
+void __init at91_add_device_cf(struct at91_cf_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  MMC / SD
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_MMC_AT91RM9200) || defined(CONFIG_MMC_AT91RM9200_MODULE)
+static u64 mmc_dmamask = 0xffffffffUL;
+static struct at91_mmc_data mmc_data;
+static struct resource at91_mmc_resources[] = {
+        {
+                .start  = AT91_BASE_MCI,
+                .end    = AT91_BASE_MCI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device at91rm9200_mmc_device = {
+        .name           = "at91rm9200_mci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &mmc_dmamask,
+                                .coherent_dma_mask      = 0xffffffff,
+                                .platform_data          = &mmc_data,
+        },
+        .resource       = at91_mmc_resources,
+        .num_resources  = ARRAY_SIZE(at91_mmc_resources),
+};
+void __init at91_add_device_mmc(struct at91_mmc_data *data)
+{
+        if (!data)
+                return;
+        /* input/irq */
+        if (data->det_pin) {
+                at91_set_gpio_input(data->det_pin, 1);
+                at91_set_deglitch(data->det_pin, 1);
+        }
+        if (data->wp_pin)
+                at91_set_gpio_input(data->wp_pin, 1);
+        /* CLK */
+        at91_set_A_periph(AT91_PIN_PA27, 0);
+        if (data->is_b) {
+                /* CMD */
+                at91_set_B_periph(AT91_PIN_PA8, 0);
+                /* DAT0, maybe DAT1..DAT3 */
+                at91_set_B_periph(AT91_PIN_PA9, 0);
+                if (data->wire4) {
+                        at91_set_B_periph(AT91_PIN_PA10, 0);
+                        at91_set_B_periph(AT91_PIN_PA11, 0);
+                        at91_set_B_periph(AT91_PIN_PA12, 0);
+                }
+        } else {
+                /* CMD */
+                at91_set_A_periph(AT91_PIN_PA28, 0);
+                /* DAT0, maybe DAT1..DAT3 */
+                at91_set_A_periph(AT91_PIN_PA29, 0);
+                if (data->wire4) {
+                        at91_set_B_periph(AT91_PIN_PB3, 0);
+                        at91_set_B_periph(AT91_PIN_PB4, 0);
+                        at91_set_B_periph(AT91_PIN_PB5, 0);
+                }
+        }
+        mmc_data = *data;
+        platform_device_register(&at91rm9200_mmc_device);
+}
+#else
+void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
+#endif
+/* -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h
new file mode 100644
index 000000000000..9bd541eba0a0
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/generic.h
@@ -0,0 +1,18 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/generic.h
+ *
+ *  Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+void at91_gpio_irq_setup(unsigned banks);
+struct sys_timer;
+extern struct sys_timer at91rm9200_timer;
+extern void __init at91rm9200_map_io(void);
+extern int __init at91_clock_init(unsigned long main_clock);
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
new file mode 100644
index 000000000000..2fd2ef583e4d
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -0,0 +1,302 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/gpio.c
+ *
+ * Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <asm/io.h>
+#include <asm/mach/irq.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+static const u32 pio_controller_offset[4] = {
+        AT91_PIOA,
+        AT91_PIOB,
+        AT91_PIOC,
+        AT91_PIOD,
+};
+static inline void __iomem *pin_to_controller(unsigned pin)
+{
+        void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
+        pin -= PIN_BASE;
+        pin /= 32;
+        if (likely(pin < BGA_GPIO_BANKS))
+                return sys_base + pio_controller_offset[pin];
+        return NULL;
+}
+static inline unsigned pin_to_mask(unsigned pin)
+{
+        pin -= PIN_BASE;
+        return 1 << (pin % 32);
+}
+/*--------------------------------------------------------------------------*/
+/* Not all hardware capabilities are exposed through these calls; they
+ * only encapsulate the most common features and modes.  (So if you
+ * want to change signals in groups, do it directly.)
+ *
+ * Bootloaders will usually handle some of the pin multiplexing setup.
+ * The intent is certainly that by the time Linux is fully booted, all
+ * pins should have been fully initialized.  These setup calls should
+ * only be used by board setup routines, or possibly in driver probe().
+ *
+ * For bootloaders doing all that setup, these calls could be inlined
+ * as NOPs so Linux won't duplicate any setup code
+ */
+/*
+ * mux the pin to the "A" internal peripheral role.
+ */
+int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio)
+                return -EINVAL;
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(mask, pio + PIO_ASR);
+        __raw_writel(mask, pio + PIO_PDR);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_A_periph);
+/*
+ * mux the pin to the "B" internal peripheral role.
+ */
+int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio)
+                return -EINVAL;
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(mask, pio + PIO_BSR);
+        __raw_writel(mask, pio + PIO_PDR);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_B_periph);
+/*
+ * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
+ * configure it for an input.
+ */
+int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio)
+                return -EINVAL;
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(mask, pio + PIO_ODR);
+        __raw_writel(mask, pio + PIO_PER);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_gpio_input);
+/*
+ * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
+ * and configure it for an output.
+ */
+int __init_or_module at91_set_gpio_output(unsigned pin, int value)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio)
+                return -EINVAL;
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + PIO_PUDR);
+        __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+        __raw_writel(mask, pio + PIO_OER);
+        __raw_writel(mask, pio + PIO_PER);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_gpio_output);
+/*
+ * enable/disable the glitch filter; mostly used with IRQ handling.
+ */
+int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio)
+                return -EINVAL;
+        __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_deglitch);
+/*--------------------------------------------------------------------------*/
+/*
+ * assuming the pin is muxed as a gpio output, set its value.
+ */
+int at91_set_gpio_value(unsigned pin, int value)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio)
+                return -EINVAL;
+        __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_gpio_value);
+/*
+ * read the pin's value (works even if it's not muxed as a gpio).
+ */
+int at91_get_gpio_value(unsigned pin)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        u32             pdsr;
+        if (!pio)
+                return -EINVAL;
+        pdsr = __raw_readl(pio + PIO_PDSR);
+        return (pdsr & mask) != 0;
+}
+EXPORT_SYMBOL(at91_get_gpio_value);
+/*--------------------------------------------------------------------------*/
+/* Several AIC controller irqs are dispatched through this GPIO handler.
+ * To use any AT91_PIN_* as an externally triggered IRQ, first call
+ * at91_set_gpio_input() then maybe enable its glitch filter.
+ * Then just request_irq() with the pin ID; it works like any ARM IRQ
+ * handler, though it always triggers on rising and falling edges.
+ *
+ * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
+ * configuring them with at91_set_a_periph() or at91_set_b_periph().
+ * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
+ */
+static void gpio_irq_mask(unsigned pin)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (pio)
+                __raw_writel(mask, pio + PIO_IDR);
+}
+static void gpio_irq_unmask(unsigned pin)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (pio)
+                __raw_writel(mask, pio + PIO_IER);
+}
+static int gpio_irq_type(unsigned pin, unsigned type)
+{
+        return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
+}
+static struct irqchip gpio_irqchip = {
+        .mask           = gpio_irq_mask,
+        .unmask         = gpio_irq_unmask,
+        .set_type       = gpio_irq_type,
+};
+static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+        unsigned        pin;
+        struct irqdesc  *gpio;
+        void __iomem    *pio;
+        u32             isr;
+        pio = (void __force __iomem *) desc->chipdata;
+        /* temporarily mask (level sensitive) parent IRQ */
+        desc->chip->ack(irq);
+        for (;;) {
+                isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
+                if (!isr)
+                        break;
+                pin = (unsigned) desc->data;
+                gpio = &irq_desc[pin];
+                while (isr) {
+                        if (isr & 1)
+                                gpio->handle(pin, gpio, regs);
+                        pin++;
+                        gpio++;
+                        isr >>= 1;
+                }
+        }
+        desc->chip->unmask(irq);
+        /* now it may re-trigger */
+}
+/* call this from board-specific init_irq */
+void __init at91_gpio_irq_setup(unsigned banks)
+{
+        unsigned        pioc, pin, id;
+        if (banks > 4)
+                banks = 4;
+        for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
+                        pioc < banks;
+                        pioc++, id++) {
+                void __iomem    *controller;
+                unsigned        i;
+                controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
+                __raw_writel(~0, controller + PIO_IDR);
+                set_irq_data(id, (void *) pin);
+                set_irq_chipdata(id, (void __force *) controller);
+                for (i = 0; i < 32; i++, pin++) {
+                        set_irq_chip(pin, &gpio_irqchip);
+                        set_irq_handler(pin, do_simple_IRQ);
+                        set_irq_flags(pin, IRQF_VALID);
+                }
+                set_irq_chained_handler(id, gpio_irq_handler);
+                /* enable the PIO peripheral clock */
+                at91_sys_write(AT91_PMC_PCER, 1 << id);
+        }
+        pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
+}
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
new file mode 100644
index 000000000000..cb62bc83a1dd
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -0,0 +1,170 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/irq.c
+ *
+ *  Copyright (C) 2004 SAN People
+ *  Copyright (C) 2004 ATMEL
+ *  Copyright (C) Rick Bronson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include "generic.h"
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller */
+        7,      /* System Peripheral */
+        0,      /* Parallel IO Controller A */
+        0,      /* Parallel IO Controller B */
+        0,      /* Parallel IO Controller C */
+        0,      /* Parallel IO Controller D */
+        6,      /* USART 0 */
+        6,      /* USART 1 */
+        6,      /* USART 2 */
+        6,      /* USART 3 */
+        0,      /* Multimedia Card Interface */
+        4,      /* USB Device Port */
+        0,      /* Two-Wire Interface */
+        6,      /* Serial Peripheral Interface */
+        5,      /* Serial Synchronous Controller */
+        5,      /* Serial Synchronous Controller */
+        5,      /* Serial Synchronous Controller */
+        0,      /* Timer Counter 0 */
+        0,      /* Timer Counter 1 */
+        0,      /* Timer Counter 2 */
+        0,      /* Timer Counter 3 */
+        0,      /* Timer Counter 4 */
+        0,      /* Timer Counter 5 */
+        3,      /* USB Host port */
+        3,      /* Ethernet MAC */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0       /* Advanced Interrupt Controller */
+};
+static void at91rm9200_mask_irq(unsigned int irq)
+{
+        /* Disable interrupt on AIC */
+        at91_sys_write(AT91_AIC_IDCR, 1 << irq);
+}
+static void at91rm9200_unmask_irq(unsigned int irq)
+{
+        /* Enable interrupt on AIC */
+        at91_sys_write(AT91_AIC_IECR, 1 << irq);
+}
+static int at91rm9200_irq_type(unsigned irq, unsigned type)
+{
+        unsigned int smr, srctype;
+        /* change triggering only for FIQ and external IRQ0..IRQ6 */
+        if ((irq < AT91_ID_IRQ0) && (irq != AT91_ID_FIQ))
+                return -EINVAL;
+        switch (type) {
+        case IRQT_HIGH:
+                srctype = AT91_AIC_SRCTYPE_HIGH;
+                break;
+        case IRQT_RISING:
+                srctype = AT91_AIC_SRCTYPE_RISING;
+                break;
+        case IRQT_LOW:
+                srctype = AT91_AIC_SRCTYPE_LOW;
+                break;
+        case IRQT_FALLING:
+                srctype = AT91_AIC_SRCTYPE_FALLING;
+                break;
+        default:
+                return -EINVAL;
+        }
+        smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
+        at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
+        return 0;
+}
+static struct irqchip at91rm9200_irq_chip = {
+        .ack            = at91rm9200_mask_irq,
+        .mask           = at91rm9200_mask_irq,
+        .unmask         = at91rm9200_unmask_irq,
+        .set_type       = at91rm9200_irq_type,
+};
+/*
+ * Initialize the AIC interrupt controller.
+ */
+void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
+{
+        unsigned int i;
+        /* No priority list specified for this board -> use defaults */
+        if (priority == NULL)
+                priority = at91rm9200_default_irq_priority;
+        /*
+         * The IVR is used by macro get_irqnr_and_base to read and verify.
+         * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
+         */
+        for (i = 0; i < NR_AIC_IRQS; i++) {
+                /* Put irq number in Source Vector Register: */
+                at91_sys_write(AT91_AIC_SVR(i), i);
+                /* Store the Source Mode Register as defined in table above */
+                at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
+                set_irq_chip(i, &at91rm9200_irq_chip);
+                set_irq_handler(i, do_level_IRQ);
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+                /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
+                if (i < 8)
+                        at91_sys_write(AT91_AIC_EOICR, 0);
+        }
+        /*
+         * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
+         * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
+         */
+        at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);
+        /* No debugging in AIC: Debug (Protect) Control Register */
+        at91_sys_write(AT91_AIC_DCR, 0);
+        /* Disable and clear all interrupts initially */
+        at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
+        at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+}
diff --git a/arch/arm/mach-at91rm9200/time.c b/arch/arm/mach-at91rm9200/time.c
new file mode 100644
index 000000000000..1b6dd2deeb22
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/time.c
@@ -0,0 +1,127 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/time.c
+ *
+ *  Copyright (C) 2003 SAN People
+ *  Copyright (C) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/time.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach/time.h>
+/*
+ * The ST_CRTR is updated asynchronously to the master clock.  It is therefore
+ *  necessary to read it twice (with the same value) to ensure accuracy.
+ */
+static inline unsigned long read_CRTR(void) {
+        unsigned long x1, x2;
+        do {
+                x1 = at91_sys_read(AT91_ST_CRTR);
+                x2 = at91_sys_read(AT91_ST_CRTR);
+        } while (x1 != x2);
+        return x1;
+}
+/*
+ * Returns number of microseconds since last timer interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeofday()
+ *  'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ *  'tick' is usecs per jiffy (linux/timex.h).
+ */
+static unsigned long at91rm9200_gettimeoffset(void)
+{
+        unsigned long elapsed;
+        elapsed = (read_CRTR() - at91_sys_read(AT91_ST_RTAR)) & AT91_ST_ALMV;
+        return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+}
+/*
+ * IRQ handler for the timer.
+ */
+static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+        unsigned long rtar;
+        if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */
+                write_seqlock(&xtime_lock);
+                do {
+                        timer_tick(regs);
+                        rtar = (at91_sys_read(AT91_ST_RTAR) + LATCH) & AT91_ST_ALMV;
+                        at91_sys_write(AT91_ST_RTAR, rtar);
+                } while (((read_CRTR() - at91_sys_read(AT91_ST_RTAR)) & AT91_ST_ALMV) >= LATCH);
+                write_sequnlock(&xtime_lock);
+                return IRQ_HANDLED;
+        }
+        else
+                return IRQ_NONE;                /* not handled */
+}
+static struct irqaction at91rm9200_timer_irq = {
+        .name           = "at91_tick",
+        .flags          = SA_SHIRQ | SA_INTERRUPT,
+        .handler        = at91rm9200_timer_interrupt
+};
+/*
+ * Set up timer interrupt.
+ */
+void __init at91rm9200_timer_init(void)
+{
+        /* Disable all timer interrupts */
+        at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
+        (void) at91_sys_read(AT91_ST_SR);       /* Clear any pending interrupts */
+        /*
+         * Make IRQs happen for the system timer.
+         */
+        setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
+        /* Set initial alarm to 0 */
+        at91_sys_write(AT91_ST_RTAR, 0);
+        /* Real time counter incremented every 30.51758 microseconds */
+        at91_sys_write(AT91_ST_RTMR, 1);
+        /* Set Period Interval timer */
+        at91_sys_write(AT91_ST_PIMR, LATCH);
+        /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */
+        tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE;
+        /* Enable Period Interval Timer interrupt */
+        at91_sys_write(AT91_ST_IER, AT91_ST_PITS);
+}
+struct sys_timer at91rm9200_timer = {
+        .init           = at91rm9200_timer_init,
+        .offset         = at91rm9200_gettimeoffset,
+};
diff --git a/arch/arm/mach-epxa10db/Kconfig b/arch/arm/mach-epxa10db/Kconfig
deleted file mode 100644
index 55d896dd4950..000000000000
--- a/arch/arm/mach-epxa10db/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-if ARCH_CAMELOT
-menu "Epxa10db"
-comment "PLD hotswap support"
-config PLD
-        bool
-        default y
-config PLD_HOTSWAP
-        bool "Support for PLD device hotplugging (experimental)"
-        depends on EXPERIMENTAL
-        help
-          This enables support for the dynamic loading and configuration of
-          compatible drivers when the contents of the PLD are changed. This
-          is still experimental and requires configuration tools which are
-          not yet generally available. Say N here. You must enable the kernel
-          module loader for this feature to work.
-endmenu
-endif
diff --git a/arch/arm/mach-epxa10db/Makefile b/arch/arm/mach-epxa10db/Makefile
deleted file mode 100644
index 24fbd7d3a3c1..000000000000
--- a/arch/arm/mach-epxa10db/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-# Object file lists.
-obj-y                   := arch.o irq.o mm.o time.o 
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
diff --git a/arch/arm/mach-epxa10db/Makefile.boot b/arch/arm/mach-epxa10db/Makefile.boot
deleted file mode 100644
index 28bec7d3fc88..000000000000
--- a/arch/arm/mach-epxa10db/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y   := 0x00008000
diff --git a/arch/arm/mach-epxa10db/arch.c b/arch/arm/mach-epxa10db/arch.c
deleted file mode 100644
index 44c56571d183..000000000000
--- a/arch/arm/mach-epxa10db/arch.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- *  linux/arch/arm/mach-epxa10db/arch.c
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_8250.h>
-#include <asm/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-static struct plat_serial8250_port serial_platform_data[] = {
-        {
-                .iobase         = 0x3f8,
-                .irq            = IRQ_UARTINT0,
-#error FIXME
-                .uartclk        = 0,
-                .regshift       = 0,
-                .iotype         = UPIO_PORT,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-        {
-                .iobase         = 0x2f8,
-                .irq            = IRQ_UARTINT1,
-#error FIXME
-                .uartclk        = 0,
-                .regshift       = 0,
-                .iotype         = UPIO_PORT,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-        { },
-};
-static struct platform_device serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = serial_platform_data,
-        },
-};
-extern void epxa10db_map_io(void);
-extern void epxa10db_init_irq(void);
-extern struct sys_timer epxa10db_timer;
-MACHINE_START(CAMELOT, "Altera Epxa10db")
-        /* Maintainer: Altera Corporation */
-        .phys_ram       = 0x00000000,
-        .phys_io        = 0x7fffc000,
-        .io_pg_offst    = ((0xffffc000) >> 18) & 0xfffc,
-        .map_io         = epxa10db_map_io,
-        .init_irq       = epxa10db_init_irq,
-        .timer          = &epxa10db_timer,
-MACHINE_END
diff --git a/arch/arm/mach-epxa10db/irq.c b/arch/arm/mach-epxa10db/irq.c
deleted file mode 100644
index 9bf927e13309..000000000000
--- a/arch/arm/mach-epxa10db/irq.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *  linux/arch/arm/mach-epxa10db/irq.c
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/stddef.h>
-#include <linux/timer.h>
-#include <linux/list.h>
-#include <asm/io.h>
-#include <asm/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-#include <asm/arch/platform.h>
-#include <asm/arch/int_ctrl00.h>
-static void epxa_mask_irq(unsigned int irq)
-{
-        writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
-}
-static void epxa_unmask_irq(unsigned int irq)
-{
-        writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
-}
- 
-static struct irqchip epxa_irq_chip = {
-        .ack            = epxa_mask_irq,
-        .mask           = epxa_mask_irq,
-        .unmask         = epxa_unmask_irq,
-};
-static struct resource irq_resource = {
-        .name   = "irq_handler",
-        .start  = IO_ADDRESS(EXC_INT_CTRL00_BASE),
-        .end    = IO_ADDRESS(INT_PRIORITY_FC(EXC_INT_CTRL00_BASE))+4,
-};
-void __init epxa10db_init_irq(void)
-{
-        unsigned int i;
-        
-        request_resource(&iomem_resource, &irq_resource);
-        /*
-         * This bit sets up the interrupt controller using 
-         * the 6 PLD interrupts mode (the default) each 
-         * irqs is assigned a priority which is the same
-         * as its interrupt number. This scheme is used because 
-         * its easy, but you may want to change it depending
-         * on the contents of your PLD
-         */
-        writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
-        for (i = 0; i < NR_IRQS; i++){
-                writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
-                set_irq_chip(i,&epxa_irq_chip);
-                set_irq_handler(i,do_level_IRQ);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-        }
-        /* Disable all interrupts */
-        writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
-}
diff --git a/arch/arm/mach-epxa10db/mm.c b/arch/arm/mach-epxa10db/mm.c
deleted file mode 100644
index cfd0d2182d44..000000000000
--- a/arch/arm/mach-epxa10db/mm.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- *  linux/arch/arm/mach-epxa10db/mm.c
- *
- *  MM routines for Altera'a Epxa10db board
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/sizes.h>
-#include <asm/page.h>
- 
-#include <asm/mach/map.h>
-/* Page table mapping for I/O region */
- 
-static struct map_desc epxa10db_io_desc[] __initdata = {
-        {
-                .virtual        = IO_ADDRESS(EXC_REGISTERS_BASE),
-                .pfn            = __phys_to_pfn(EXC_REGISTERS_BASE),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = IO_ADDRESS(EXC_PLD_BLOCK0_BASE),
-                .pfn            = __phys_to_pfn(EXC_PLD_BLOCK0_BASE),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = IO_ADDRESS(EXC_PLD_BLOCK1_BASE),
-                .pfn            =__phys_to_pfn(EXC_PLD_BLOCK1_BASE),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = IO_ADDRESS(EXC_PLD_BLOCK2_BASE),
-                .physical       = __phys_to_pfn(EXC_PLD_BLOCK2_BASE),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = IO_ADDRESS(EXC_PLD_BLOCK3_BASE),
-                .pfn            = __phys_to_pfn(EXC_PLD_BLOCK3_BASE),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = FLASH_VADDR(EXC_EBI_BLOCK0_BASE),
-                .pfn            = __phys_to_pfn(EXC_EBI_BLOCK0_BASE),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE
-        }
-};
-void __init epxa10db_map_io(void)
-{
-        iotable_init(epxa10db_io_desc, ARRAY_SIZE(epxa10db_io_desc));
-}
diff --git a/arch/arm/mach-epxa10db/time.c b/arch/arm/mach-epxa10db/time.c
deleted file mode 100644
index 4b1084dde8dd..000000000000
--- a/arch/arm/mach-epxa10db/time.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  linux/arch/arm/mach-epxa10db/time.c
- *
- *  Copyright (C) 2000 Deep Blue Solutions
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <asm/hardware.h>
-#include <asm/system.h>
-#include <asm/leds.h>
-#include <asm/mach/time.h>
-#define TIMER00_TYPE (volatile unsigned int*)
-#include <asm/arch/timer00.h>
-static int epxa10db_set_rtc(void)
-{
-        return 1;
-}
-static int epxa10db_rtc_init(void)
-{
-        set_rtc = epxa10db_set_rtc;
-        return 0;
-}
-__initcall(epxa10db_rtc_init);
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-epxa10db_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-{
-        write_seqlock(&xtime_lock);
-        // ...clear the interrupt
-        *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))|=TIMER0_CR_CI_MSK;
-        timer_tick(regs);
-        write_sequnlock(&xtime_lock);
-        return IRQ_HANDLED;
-}
-static struct irqaction epxa10db_timer_irq = {
-        .name           = "Excalibur Timer Tick",
-        .flags          = SA_INTERRUPT | SA_TIMER,
-        .handler        = epxa10db_timer_interrupt,
-};
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-static void __init epxa10db_timer_init(void)
-{
-        /* Start the timer */
-        *TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/200);
-        *TIMER0_PRESCALE(IO_ADDRESS(EXC_TIMER00_BASE))=1;
-        *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=TIMER0_CR_IE_MSK | TIMER0_CR_S_MSK;
-        setup_irq(IRQ_TIMER0, &epxa10db_timer_irq);
-}
-struct sys_timer epxa10db_timer = {
-        .init           = epxa10db_timer_init,
-};
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 5830ae3ddd19..fc09ba92d66a 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -253,100 +253,101 @@ struct clk s3c24xx_uclk = {
 /* clock definitions */
 static struct clk init_clocks[] = {
-        { .name    = "nand",
+        {
-          .id      = -1,
+                .name           = "nand",
-          .parent  = &clk_h,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_h,
-          .ctrlbit = S3C2410_CLKCON_NAND
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_NAND,
-        { .name    = "lcd",
+        }, {
-          .id      = -1,
+                .name           = "lcd",
-          .parent  = &clk_h,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_h,
-          .ctrlbit = S3C2410_CLKCON_LCDC
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_LCDC,
-        { .name    = "usb-host",
+        }, {
-          .id      = -1,
+                .name           = "usb-host",
-          .parent  = &clk_h,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_h,
-          .ctrlbit = S3C2410_CLKCON_USBH
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_USBH,
-        { .name    = "usb-device",
+        }, {
-          .id      = -1,
+                .name           = "usb-device",
-          .parent  = &clk_h,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_h,
-          .ctrlbit = S3C2410_CLKCON_USBD
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_USBD,
-        { .name    = "timers",
+        }, {
-          .id      = -1,
+                .name           = "timers",
-          .parent  = &clk_p,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_PWMT
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_PWMT,
-        { .name    = "sdi",
+        }, {
-          .id      = -1,
+                .name           = "sdi",
-          .parent  = &clk_p,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_SDI
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_SDI,
-        { .name    = "uart",
+        }, {
-          .id      = 0,
+                .name           = "uart",
-          .parent  = &clk_p,
+                .id             = 0,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_UART0
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_UART0,
-        { .name    = "uart",
+        }, {
-          .id      = 1,
+                .name           = "uart",
-          .parent  = &clk_p,
+                .id             = 1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_UART1
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_UART1,
-        { .name    = "uart",
+        }, {
-          .id      = 2,
+                .name           = "uart",
-          .parent  = &clk_p,
+                .id             = 2,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_UART2
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_UART2,
-        { .name    = "gpio",
+        }, {
-          .id      = -1,
+                .name           = "gpio",
-          .parent  = &clk_p,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_GPIO
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_GPIO,
-        { .name    = "rtc",
+        }, {
-          .id      = -1,
+                .name           = "rtc",
-          .parent  = &clk_p,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_RTC
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_RTC,
-        { .name    = "adc",
+        }, {
-          .id      = -1,
+                .name           = "adc",
-          .parent  = &clk_p,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_ADC
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_ADC,
-        { .name    = "i2c",
+        }, {
-          .id      = -1,
+                .name           = "i2c",
-          .parent  = &clk_p,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_IIC
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_IIC,
-        { .name    = "iis",
+        }, {
-          .id      = -1,
+                .name           = "iis",
-          .parent  = &clk_p,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_IIS
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_IIS,
-        { .name    = "spi",
+        }, {
-          .id      = -1,
+                .name           = "spi",
-          .parent  = &clk_p,
+                .id             = -1,
-          .enable  = s3c24xx_clkcon_enable,
+                .parent         = &clk_p,
-          .ctrlbit = S3C2410_CLKCON_SPI
+                .enable         = s3c24xx_clkcon_enable,
-        },
+                .ctrlbit        = S3C2410_CLKCON_SPI,
-        { .name    = "watchdog",
+        }, {
-          .id      = -1,
+                .name           = "watchdog",
-          .parent  = &clk_p,
+                .id             = -1,
-          .ctrlbit = 0
+                .parent         = &clk_p,
+                .ctrlbit        = 0,
        }
 };
@@ -390,16 +391,15 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
        clk_p.rate = pclk;
        clk_f.rate = fclk;
-        /* it looks like just setting the register here is not good
+        /* We must be careful disabling the clocks we are not intending to
-         * enough, and causes the odd hang at initial boot time, so
+         * be using at boot time, as subsytems such as the LCD which do
-         * do all of them indivdually.
+         * their own DMA requests to the bus can cause the system to lockup
+         * if they where in the middle of requesting bus access.
         *
-         * I think disabling the LCD clock if the LCD is active is
+         * Disabling the LCD clock if the LCD is active is very dangerous,
-         * very dangerous, and therefore the bootloader should be
+         * and therefore the bootloader should be  careful to not enable
-         * careful to not enable the LCD clock if it is not needed.
+         * the LCD clock if it is not needed.
-         *
+        */
-         * and of course, this looks neater
-         */
        s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
        s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e84fdde6edf8..3b79d0e23455 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -62,8 +62,8 @@ config CPU_ARM720T
 # ARM920T
 config CPU_ARM920T
        bool "Support ARM920T processor" if !ARCH_S3C2410
-        depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000
+        depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
-        default y if ARCH_S3C2410
+        default y if ARCH_S3C2410 || ARCH_AT91RM9200
        select CPU_32v4
        select CPU_ABRT_EV4T
        select CPU_CACHE_V4WT
@@ -83,8 +83,8 @@ config CPU_ARM920T
 # ARM922T
 config CPU_ARM922T
        bool "Support ARM922T processor" if ARCH_INTEGRATOR
-        depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR
+        depends on ARCH_LH7A40X || ARCH_INTEGRATOR
-        default y if ARCH_CAMELOT || ARCH_LH7A40X
+        default y if ARCH_LH7A40X
        select CPU_32v4
        select CPU_ABRT_EV4T
        select CPU_CACHE_V4WT
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 10901398e4a2..de3ce1eec2ec 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -86,11 +86,12 @@ remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size,
 }
 static int
-remap_area_pages(unsigned long start, unsigned long phys_addr,
+remap_area_pages(unsigned long start, unsigned long pfn,
                 unsigned long size, unsigned long flags)
 {
        unsigned long address = start;
        unsigned long end = start + size;
+        unsigned long phys_addr = __pfn_to_phys(pfn);
        int err = 0;
        pgd_t * dir;
@@ -130,36 +131,44 @@ remap_area_pages(unsigned long start, unsigned long phys_addr,
 * mapping.  See include/asm-arm/proc-armv/pgtable.h for more information.
 */
 void __iomem *
+__ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
+              unsigned long flags)
+{
+        unsigned long addr;
+        struct vm_struct * area;
+        area = get_vm_area(size, VM_IOREMAP);
+        if (!area)
+                return NULL;
+        addr = (unsigned long)area->addr;
+        if (remap_area_pages(addr, pfn, size, flags)) {
+                vfree(addr);
+                return NULL;
+        }
+        return (void __iomem *) (offset + (char *)addr);
+}
+EXPORT_SYMBOL(__ioremap_pfn);
+void __iomem *
 __ioremap(unsigned long phys_addr, size_t size, unsigned long flags)
 {
-        void * addr;
+        unsigned long last_addr;
-        struct vm_struct * area;
+        unsigned long offset = phys_addr & ~PAGE_MASK;
-        unsigned long offset, last_addr;
+        unsigned long pfn = __phys_to_pfn(phys_addr);
-        /* Don't allow wraparound or zero size */
+        /*
+         * Don't allow wraparound or zero size
+         */
        last_addr = phys_addr + size - 1;
        if (!size || last_addr < phys_addr)
                return NULL;
        /*
-         * Mappings have to be page-aligned
+         * Page align the mapping size
         */
-        offset = phys_addr & ~PAGE_MASK;
-        phys_addr &= PAGE_MASK;
        size = PAGE_ALIGN(last_addr + 1) - phys_addr;
-        /*
+        return __ioremap_pfn(pfn, offset, size, flags);
-         * Ok, go for it..
-         */
-        area = get_vm_area(size, VM_IOREMAP);
-        if (!area)
-                return NULL;
-        addr = area->addr;
-        if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) {
-                vfree(addr);
-                return NULL;
-        }
-        return (void __iomem *) (offset + (char *)addr);
 }
 EXPORT_SYMBOL(__ioremap);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 465487470d0e..d0f9bb5e9023 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Fri Nov 25 14:43:04 2005
+# Last update: Mon Jan 9 12:56:42 2006
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -910,3 +910,31 @@ mbus			MACH_MBUS		MBUS			896
 nadia2vb                MACH_NADIA2VB           NADIA2VB                897
 r1000                   MACH_R1000              R1000                   898
 hw90250                 MACH_HW90250            HW90250                 899
+omap_2430sdp            MACH_OMAP_2430SDP       OMAP_2430SDP            900
+davinci_evm             MACH_DAVINCI_EVM        DAVINCI_EVM             901
+omap_tornado            MACH_OMAP_TORNADO       OMAP_TORNADO            902
+olocreek                MACH_OLOCREEK           OLOCREEK                903
+palmz72                 MACH_PALMZ72            PALMZ72                 904
+nxdb500                 MACH_NXDB500            NXDB500                 905
+apf9328                 MACH_APF9328            APF9328                 906
+omap_wipoq              MACH_OMAP_WIPOQ         OMAP_WIPOQ              907
+omap_twip               MACH_OMAP_TWIP          OMAP_TWIP               908
+xscale_treo650          MACH_XSCALE_PALMTREO650 XSCALE_PALMTREO650      909
+acumen                  MACH_ACUMEN             ACUMEN                  910
+xp100                   MACH_XP100              XP100                   911
+fs2410                  MACH_FS2410             FS2410                  912
+pxa270_cerf             MACH_PXA270_CERF        PXA270_CERF             913
+sq2ftlpalm              MACH_SQ2FTLPALM         SQ2FTLPALM              914
+bsemserver              MACH_BSEMSERVER         BSEMSERVER              915
+netclient               MACH_NETCLIENT          NETCLIENT               916
+xscale_palmtt5          MACH_XSCALE_PALMTT5     XSCALE_PALMTT5          917
+xscale_palmtc           MACH_OMAP_PALMTC        OMAP_PALMTC             918
+omap_apollon            MACH_OMAP_APOLLON       OMAP_APOLLON            919
+argonlvevb              MACH_ARGONLVEVB         ARGONLVEVB              920
+rea_2d                  MACH_REA_2D             REA_2D                  921
+eti3e524                MACH_TI3E524            TI3E524                 922
+ateb9200                MACH_ATEB9200           ATEB9200                923
+auckland                MACH_AUCKLAND           AUCKLAND                924
+ak3220m                 MACH_AK3320M            AK3320M                 925
+duramax                 MACH_DURAMAX            DURAMAX                 926
+n35                     MACH_N35                N35                     927
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 1bbdd1693d57..889855d8d9f9 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -15,7 +15,6 @@
 #include <linux/amba/bus.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/sizes.h>
 #define to_amba_device(d)       container_of(d, struct amba_device, dev)
diff --git a/drivers/input/serio/sa1111ps2.c b/drivers/input/serio/sa1111ps2.c
index 3f0df3330fb2..ebd9976fc811 100644
--- a/drivers/input/serio/sa1111ps2.c
+++ b/drivers/input/serio/sa1111ps2.c
@@ -20,7 +20,6 @@
 #include <linux/spinlock.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/hardware/sa1111.h>
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index b9b77cf39a18..7abd7fee0dda 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -473,14 +473,6 @@ config MTD_IXP2000
          IXDP425 and Coyote. If you have an IXP2000 based board and
          would like to use the flash chips on it, say 'Y'.
-config MTD_EPXA10DB
-        tristate "CFI Flash device mapped on Epxa10db"
-        depends on MTD_CFI && MTD_PARTITIONS && ARCH_CAMELOT
-        help
-          This enables support for the flash devices on the Altera
-          Excalibur XA10 Development Board. If you are building a kernel
-          for on of these boards then you should say 'Y' otherwise say 'N'.
 config MTD_FORTUNET
        tristate "CFI Flash device mapped on the FortuNet board"
        depends on MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 2f7e254912f0..ab71f172eb77 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_MTD_CFI_FLAGADM)	+= cfi_flagadm.o
 obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o
 obj-$(CONFIG_MTD_DC21285)       += dc21285.o
 obj-$(CONFIG_MTD_DILNETPC)      += dilnetpc.o
-obj-$(CONFIG_MTD_EPXA10DB)      += epxa10db-flash.o
 obj-$(CONFIG_MTD_IQ80310)       += iq80310.o
 obj-$(CONFIG_MTD_L440GX)        += l440gx.o
 obj-$(CONFIG_MTD_AMD76XROM)     += amd76xrom.o
diff --git a/drivers/mtd/maps/epxa10db-flash.c b/drivers/mtd/maps/epxa10db-flash.c
deleted file mode 100644
index 265b079fe934..000000000000
--- a/drivers/mtd/maps/epxa10db-flash.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Flash memory access on EPXA based devices
- *
- * (C) 2000 Nicolas Pitre <nico@cam.org>
- *  Copyright (C) 2001 Altera Corporation
- *  Copyright (C) 2001 Red Hat, Inc.
- *
- * $Id: epxa10db-flash.c,v 1.15 2005/11/07 11:14:27 gleixner Exp $
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <asm/io.h>
-#include <asm/hardware.h>
-#ifdef CONFIG_EPXA10DB
-#define BOARD_NAME "EPXA10DB"
-#else
-#define BOARD_NAME "EPXA1DB"
-#endif
-static int nr_parts = 0;
-static struct mtd_partition *parts;
-static struct mtd_info *mymtd;
-static int epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts);
-static struct map_info epxa_map = {
-        .name =         "EPXA flash",
-        .size =         FLASH_SIZE,
-        .bankwidth =    2,
-        .phys =         FLASH_START,
-};
-static const char *probes[] = { "RedBoot", "afs", NULL };
-static int __init epxa_mtd_init(void)
-{
-        int i;
-        printk(KERN_NOTICE "%s flash device: 0x%x at 0x%x\n", BOARD_NAME, FLASH_SIZE, FLASH_START);
-        epxa_map.virt = ioremap(FLASH_START, FLASH_SIZE);
-        if (!epxa_map.virt) {
-                printk("Failed to ioremap %s flash\n",BOARD_NAME);
-                return -EIO;
-        }
-        simple_map_init(&epxa_map);
-        mymtd = do_map_probe("cfi_probe", &epxa_map);
-        if (!mymtd) {
-                iounmap((void *)epxa_map.virt);
-                return -ENXIO;
-        }
-        mymtd->owner = THIS_MODULE;
-        /* Unlock the flash device. */
-        if(mymtd->unlock){
-                for (i=0; i<mymtd->numeraseregions;i++){
-                        int j;
-                        for(j=0;j<mymtd->eraseregions[i].numblocks;j++){
-                                mymtd->unlock(mymtd,mymtd->eraseregions[i].offset + j * mymtd->eraseregions[i].erasesize,mymtd->eraseregions[i].erasesize);
-                        }
-                }
-        }
-#ifdef CONFIG_MTD_PARTITIONS
-        nr_parts = parse_mtd_partitions(mymtd, probes, &parts, 0);
-        if (nr_parts > 0) {
-                add_mtd_partitions(mymtd, parts, nr_parts);
-                return 0;
-        }
-#endif
-        /* No recognised partitioning schemes found - use defaults */
-        nr_parts = epxa_default_partitions(mymtd, &parts);
-        if (nr_parts > 0) {
-                add_mtd_partitions(mymtd, parts, nr_parts);
-                return 0;
-        }
-        /* If all else fails... */
-        add_mtd_device(mymtd);
-        return 0;
-}
-static void __exit epxa_mtd_cleanup(void)
-{
-        if (mymtd) {
-                if (nr_parts)
-                        del_mtd_partitions(mymtd);
-                else
-                        del_mtd_device(mymtd);
-                map_destroy(mymtd);
-        }
-        if (epxa_map.virt) {
-                iounmap((void *)epxa_map.virt);
-                epxa_map.virt = 0;
-        }
-}
-/*
- * This will do for now, once we decide which bootldr we're finally
- * going to use then we'll remove this function and do it properly
- *
- * Partions are currently (as offsets from base of flash):
- * 0x00000000 - 0x003FFFFF - bootloader (!)
- * 0x00400000 - 0x00FFFFFF - Flashdisk
- */
-static int __init epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts)
-{
-        struct mtd_partition *parts;
-        int ret, i;
-        int npartitions = 0;
-        char *names;
-        const char *name = "jffs";
-        printk("Using default partitions for %s\n",BOARD_NAME);
-        npartitions=1;
-        parts = kmalloc(npartitions*sizeof(*parts)+strlen(name), GFP_KERNEL);
-        memzero(parts,npartitions*sizeof(*parts)+strlen(name));
-        if (!parts) {
-                ret = -ENOMEM;
-                goto out;
-        }
-        i=0;
-        names = (char *)&parts[npartitions];
-        parts[i].name = names;
-        names += strlen(name) + 1;
-        strcpy(parts[i].name, name);
-#ifdef CONFIG_EPXA10DB
-        parts[i].size = FLASH_SIZE-0x00400000;
-        parts[i].offset = 0x00400000;
-#else
-        parts[i].size = FLASH_SIZE-0x00180000;
-        parts[i].offset = 0x00180000;
-#endif
- out:
-        *pparts = parts;
-        return npartitions;
-}
-module_init(epxa_mtd_init);
-module_exit(epxa_mtd_cleanup);
-MODULE_AUTHOR("Clive Davies");
-MODULE_DESCRIPTION("Altera epxa mtd flash map");
-MODULE_LICENSE("GPL");
diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
index 470364deded0..625184b65e38 100644
--- a/drivers/net/arm/Kconfig
+++ b/drivers/net/arm/Kconfig
@@ -31,16 +31,3 @@ config ARM_ETHERH
        help
          If you have an Acorn system with one of these network cards, you
          should say Y to this option if you wish to use it with Linux.
-config ARM_ETHER00
-        tristate "Altera Ether00 support"
-        depends on NET_ETHERNET && ARM && ARCH_CAMELOT
-        help
-          This is the driver for Altera's ether00 ethernet mac IP core. Say
-          Y here if you want to build support for this into the kernel. It
-          is also available as a module (say M here) that can be inserted/
-          removed from the kernel at the same time as the PLD is configured.
-          If this driver is running on an epxa10 development board then it
-          will generate a suitable hw address based on the board serial
-          number (MTD support is required for this). Otherwise you will
-          need to set a suitable hw address using ifconfig.
diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile
index b0d706834d89..bc263edf06a7 100644
--- a/drivers/net/arm/Makefile
+++ b/drivers/net/arm/Makefile
@@ -4,7 +4,6 @@
 #
 obj-$(CONFIG_ARM_AM79C961A)     += am79c961a.o
-obj-$(CONFIG_ARM_ETHER00)       += ether00.o
 obj-$(CONFIG_ARM_ETHERH)        += etherh.o
 obj-$(CONFIG_ARM_ETHER3)        += ether3.o
 obj-$(CONFIG_ARM_ETHER1)        += ether1.o
diff --git a/drivers/net/arm/am79c961a.c b/drivers/net/arm/am79c961a.c
index 877891a29aaa..53e3afc1b7b7 100644
--- a/drivers/net/arm/am79c961a.c
+++ b/drivers/net/arm/am79c961a.c
@@ -668,9 +668,8 @@ static void __init am79c961_banner(void)
                printk(KERN_INFO "%s", version);
 }
-static int __init am79c961_probe(struct device *_dev)
+static int __init am79c961_probe(struct platform_device *pdev)
 {
-        struct platform_device *pdev = to_platform_device(_dev);
        struct resource *res;
        struct net_device *dev;
        struct dev_priv *priv;
@@ -758,15 +757,16 @@ out:
        return ret;
 }
-static struct device_driver am79c961_driver = {
+static struct platform_driver am79c961_driver = {
-        .name           = "am79c961",
-        .bus            = &platform_bus_type,
        .probe          = am79c961_probe,
+        .driver         = {
+                .name   = "am79c961",
+        },
 };
 static int __init am79c961_init(void)
 {
-        return driver_register(&am79c961_driver);
+        return platform_driver_register(&am79c961_driver);
 }
 __initcall(am79c961_init);
diff --git a/drivers/net/arm/ether00.c b/drivers/net/arm/ether00.c
deleted file mode 100644
index 4f1f4e31bda5..000000000000
--- a/drivers/net/arm/ether00.c
+++ /dev/null
@@ -1,1017 +0,0 @@
-/*
- *  drivers/net/ether00.c
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* includes */
-#include <linux/config.h>
-#include <linux/pci.h>
-#include <linux/sched.h>
-#include <linux/netdevice.h>
-#include <linux/skbuff.h>
-#include <linux/etherdevice.h>
-#include <linux/module.h>
-#include <linux/tqueue.h>
-#include <linux/mtd/mtd.h>
-#include <linux/pld/pld_hotswap.h>
-#include <asm/arch/excalibur.h>
-#include <asm/arch/hardware.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/sizes.h>
-#include <asm/arch/ether00.h>
-#include <asm/arch/tdkphy.h>
-MODULE_AUTHOR("Clive Davies");
-MODULE_DESCRIPTION("Altera Ether00 IP core driver");
-MODULE_LICENSE("GPL");
-#define PKT_BUF_SZ 1540 /* Size of each rx buffer */
-#define ETH_NR 4 /* Number of MACs this driver supports */
-#define DEBUG(x)
-#define __dma_va(x) (unsigned int)((unsigned int)priv->dma_data+(((unsigned int)(x))&(EXC_SPSRAM_BLOCK0_SIZE-1)))
-#define __dma_pa(x) (unsigned int)(EXC_SPSRAM_BLOCK0_BASE+(((unsigned int)(x))-(unsigned int)priv->dma_data))
-#define ETHER00_BASE    0
-#define ETHER00_TYPE
-#define ETHER00_NAME "ether00"
-#define MAC_REG_SIZE 0x400 /* size of MAC register area */
-/* typedefs */
-/* The definition of the driver control structure */
-#define RX_NUM_BUFF     10
-#define RX_NUM_FDESC    10
-#define TX_NUM_FDESC    10
-struct tx_fda_ent{
-        FDA_DESC  fd;
-        BUF_DESC  bd;
-        BUF_DESC  pad;
-};
-struct rx_fda_ent{
-        FDA_DESC  fd;
-        BUF_DESC  bd;
-        BUF_DESC  pad;
-};
-struct rx_blist_ent{
-        FDA_DESC  fd;
-        BUF_DESC  bd;
-        BUF_DESC  pad;
-};
-struct net_priv
-{
-        struct net_device_stats stats;
-        struct sk_buff* skb;
-        void* dma_data;
-        struct rx_blist_ent*  rx_blist_vp;
-        struct rx_fda_ent* rx_fda_ptr;
-        struct tx_fda_ent* tx_fdalist_vp;
-        struct tq_struct  tq_memupdate;
-        unsigned char   memupdate_scheduled;
-        unsigned char   rx_disabled;
-        unsigned char   queue_stopped;
-        spinlock_t rx_lock;
-};
-static const char vendor_id[2]={0x07,0xed};
-#ifdef ETHER00_DEBUG
-/* Dump (most) registers for debugging puposes */
-static void dump_regs(struct net_device *dev){
-        struct net_priv* priv=dev->priv;
-        unsigned int* i;
-        printk("\n RX free descriptor area:\n");
-        for(i=(unsigned int*)priv->rx_fda_ptr;
-            i<((unsigned int*)(priv->rx_fda_ptr+RX_NUM_FDESC));){
-                printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
-                i+=4;
-        }
-        printk("\n RX buffer list:\n");
-        for(i=(unsigned int*)priv->rx_blist_vp;
-            i<((unsigned int*)(priv->rx_blist_vp+RX_NUM_BUFF));){
-                printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
-                i+=4;
-        }
-        printk("\n TX frame descriptor list:\n");
-        for(i=(unsigned int*)priv->tx_fdalist_vp;
-            i<((unsigned int*)(priv->tx_fdalist_vp+TX_NUM_FDESC));){
-                printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
-                i+=4;
-        }
-        printk("\ndma ctl=%#x\n",readw(ETHER_DMA_CTL(dev->base_addr)));
-        printk("txfrmptr=%#x\n",readw(ETHER_TXFRMPTR(dev->base_addr)));
-        printk("txthrsh=%#x\n",readw(ETHER_TXTHRSH(dev->base_addr)));
-        printk("txpollctr=%#x\n",readw(ETHER_TXPOLLCTR(dev->base_addr)));
-        printk("blfrmptr=%#x\n",readw(ETHER_BLFRMPTR(dev->base_addr)));
-        printk("rxfragsize=%#x\n",readw(ETHER_RXFRAGSIZE(dev->base_addr)));
-        printk("tx_int_en=%#x\n",readw(ETHER_INT_EN(dev->base_addr)));
-        printk("fda_bas=%#x\n",readw(ETHER_FDA_BAS(dev->base_addr)));
-        printk("fda_lim=%#x\n",readw(ETHER_FDA_LIM(dev->base_addr)));
-        printk("int_src=%#x\n",readw(ETHER_INT_SRC(dev->base_addr)));
-        printk("pausecnt=%#x\n",readw(ETHER_PAUSECNT(dev->base_addr)));
-        printk("rempaucnt=%#x\n",readw(ETHER_REMPAUCNT(dev->base_addr)));
-        printk("txconfrmstat=%#x\n",readw(ETHER_TXCONFRMSTAT(dev->base_addr)));
-        printk("mac_ctl=%#x\n",readw(ETHER_MAC_CTL(dev->base_addr)));
-        printk("arc_ctl=%#x\n",readw(ETHER_ARC_CTL(dev->base_addr)));
-        printk("tx_ctl=%#x\n",readw(ETHER_TX_CTL(dev->base_addr)));
-}
-#endif /* ETHER00_DEBUG */
-static int ether00_write_phy(struct net_device *dev, short address, short value)
-{
-        volatile int count = 1024;
-        writew(value,ETHER_MD_DATA(dev->base_addr));
-        writew( ETHER_MD_CA_BUSY_MSK |
-                ETHER_MD_CA_WR_MSK |
-                (address & ETHER_MD_CA_ADDR_MSK),
-                ETHER_MD_CA(dev->base_addr));
-        /* Wait for the command to complete */
-        while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
-                count--;
-        }
-        if (!count){
-                printk("Write to phy failed, addr=%#x, data=%#x\n",address, value);
-                return -EIO;
-        }
-        return 0;
-}
-static int ether00_read_phy(struct net_device *dev, short address)
-{
-        volatile int count = 1024;
-        writew( ETHER_MD_CA_BUSY_MSK |
-                (address & ETHER_MD_CA_ADDR_MSK),
-                ETHER_MD_CA(dev->base_addr));
-        /* Wait for the command to complete */
-        while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
-                count--;
-        }
-        if (!count){
-                printk(KERN_WARNING "Read from phy timed out\n");
-                return -EIO;
-        }
-        return readw(ETHER_MD_DATA(dev->base_addr));
-}
-static void ether00_phy_int(int irq_num, void* dev_id, struct pt_regs* regs)
-{
-        struct net_device* dev=dev_id;
-        int irq_status;
-        irq_status=ether00_read_phy(dev, PHY_IRQ_CONTROL);
-        if(irq_status & PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK){
-                /*
-                 * Autonegotiation complete on epxa10db. The mac doesn't
-                 * twig if we're in full duplex so we need to check the
-                 * phy status register and configure the mac accordingly
-                 */
-                if(ether00_read_phy(dev, PHY_STATUS)&(PHY_STATUS_10T_F_MSK|PHY_STATUS_100_X_F_MSK)){
-                        int tmp;
-                        tmp=readl(ETHER_MAC_CTL(dev->base_addr));
-                        writel(tmp|ETHER_MAC_CTL_FULLDUP_MSK,ETHER_MAC_CTL(dev->base_addr));
-                }
-        }
-        if(irq_status&PHY_IRQ_CONTROL_LS_CHG_INT_MSK){
-                if(ether00_read_phy(dev, PHY_STATUS)& PHY_STATUS_LINK_MSK){
-                        /* Link is up */
-                        netif_carrier_on(dev);
-                        //printk("Carrier on\n");
-                }else{
-                        netif_carrier_off(dev);
-                        //printk("Carrier off\n");
-                }
-        }
-}
-static void setup_blist_entry(struct sk_buff* skb,struct rx_blist_ent* blist_ent_ptr){
-        /* Make the buffer consistent with the cache as the mac is going to write
-         * directly into it*/
-        blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
-        blist_ent_ptr->bd.BuffData=(char*)__pa(skb->data);
-        consistent_sync(skb->data,PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
-        /* align IP on 16 Byte (DMA_CTL set to skip 2 bytes) */
-        skb_reserve(skb,2);
-        blist_ent_ptr->bd.BuffLength=PKT_BUF_SZ-2;
-        blist_ent_ptr->fd.FDLength=1;
-        blist_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
-        blist_ent_ptr->bd.BDCtl=BDCTL_COWNSBD_MSK;
-}
-static int ether00_mem_init(struct net_device* dev)
-{
-        struct net_priv* priv=dev->priv;
-        struct tx_fda_ent *tx_fd_ptr,*tx_end_ptr;
-        struct rx_blist_ent* blist_ent_ptr;
-        int i;
-        /*
-         * Grab a block of on chip SRAM to contain the control stuctures for
-         * the ethernet MAC. This uncached becuase it needs to be accesses by both
-         * bus masters (cpu + mac). However, it shouldn't matter too much in terms
-         * of speed as its on chip memory
-         */
-        priv->dma_data=ioremap_nocache(EXC_SPSRAM_BLOCK0_BASE,EXC_SPSRAM_BLOCK0_SIZE );
-        if (!priv->dma_data)
-                return -ENOMEM;
-        priv->rx_fda_ptr=(struct rx_fda_ent*)priv->dma_data;
-        /*
-         * Now share it out amongst the Frame descriptors and the buffer list
-         */
-        priv->rx_blist_vp=(struct rx_blist_ent*)((unsigned int)priv->dma_data+RX_NUM_FDESC*sizeof(struct rx_fda_ent));
-        /*
-         *Initalise the FDA list
-         */
-        /* set ownership to the controller */
-        memset(priv->rx_fda_ptr,0x80,RX_NUM_FDESC*sizeof(struct rx_fda_ent));
-        /*
-         *Initialise the buffer list
-         */
-        blist_ent_ptr=priv->rx_blist_vp;
-        i=0;
-        while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
-                struct sk_buff *skb;
-                blist_ent_ptr->fd.FDLength=1;
-                skb=dev_alloc_skb(PKT_BUF_SZ);
-                if(skb){
-                        setup_blist_entry(skb,blist_ent_ptr);
-                        blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(blist_ent_ptr+1);
-                        blist_ent_ptr->bd.BDStat=i++;
-                        blist_ent_ptr++;
-                }
-                else
-                {
-                        printk("Failed to initalise buffer list\n");
-                }
-        }
-        blist_ent_ptr--;
-        blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->rx_blist_vp);
-        priv->tx_fdalist_vp=(struct tx_fda_ent*)(priv->rx_blist_vp+RX_NUM_BUFF);
-        /* Initialise the buffers to be a circular list. The mac will then go poll
-         * the list until it finds a frame ready to transmit */
-        tx_end_ptr=priv->tx_fdalist_vp+TX_NUM_FDESC;
-        for(tx_fd_ptr=priv->tx_fdalist_vp;tx_fd_ptr<tx_end_ptr;tx_fd_ptr++){
-                tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa((tx_fd_ptr+1));
-                tx_fd_ptr->fd.FDCtl=1;
-                tx_fd_ptr->fd.FDStat=0;
-                tx_fd_ptr->fd.FDLength=1;
-        }
-        /* Change the last FDNext pointer to make a circular list */
-        tx_fd_ptr--;
-        tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->tx_fdalist_vp);
-        /* Point the device at the chain of Rx and Tx Buffers */
-        writel((unsigned int)__dma_pa(priv->rx_fda_ptr),ETHER_FDA_BAS(dev->base_addr));
-        writel((RX_NUM_FDESC-1)*sizeof(struct rx_fda_ent),ETHER_FDA_LIM(dev->base_addr));
-        writel((unsigned int)__dma_pa(priv->rx_blist_vp),ETHER_BLFRMPTR(dev->base_addr));
-        writel((unsigned int)__dma_pa(priv->tx_fdalist_vp),ETHER_TXFRMPTR(dev->base_addr));
-        return 0;
-}
-void ether00_mem_update(void* dev_id)
-{
-        struct net_device* dev=dev_id;
-        struct net_priv* priv=dev->priv;
-        struct sk_buff* skb;
-        struct tx_fda_ent *fda_ptr=priv->tx_fdalist_vp;
-        struct rx_blist_ent* blist_ent_ptr;
-        unsigned long flags;
-        priv->tq_memupdate.sync=0;
-        //priv->tq_memupdate.list=
-        priv->memupdate_scheduled=0;
-        /* Transmit interrupt */
-        while(fda_ptr<(priv->tx_fdalist_vp+TX_NUM_FDESC)){
-                if(!(FDCTL_COWNSFD_MSK&fda_ptr->fd.FDCtl) && (ETHER_TX_STAT_COMP_MSK&fda_ptr->fd.FDStat)){
-                        priv->stats.tx_packets++;
-                        priv->stats.tx_bytes+=fda_ptr->bd.BuffLength;
-                        skb=(struct sk_buff*)fda_ptr->fd.FDSystem;
-                        //printk("%d:txcln:fda=%#x skb=%#x\n",jiffies,fda_ptr,skb);
-                        dev_kfree_skb(skb);
-                        fda_ptr->fd.FDSystem=0;
-                        fda_ptr->fd.FDStat=0;
-                        fda_ptr->fd.FDCtl=0;
-                }
-                fda_ptr++;
-        }
-        /* Fill in any missing buffers from the received queue */
-        spin_lock_irqsave(&priv->rx_lock,flags);
-        blist_ent_ptr=priv->rx_blist_vp;
-        while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
-                /* fd.FDSystem of 0 indicates we failed to allocate the buffer in the ISR */
-                if(!blist_ent_ptr->fd.FDSystem){
-                        struct sk_buff *skb;
-                        skb=dev_alloc_skb(PKT_BUF_SZ);
-                        blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
-                        if(skb){
-                                setup_blist_entry(skb,blist_ent_ptr);
-                        }
-                        else
-                        {
-                                break;
-                        }
-                }
-                blist_ent_ptr++;
-        }
-        spin_unlock_irqrestore(&priv->rx_lock,flags);
-        if(priv->queue_stopped){
-                //printk("%d:cln:start q\n",jiffies);
-                netif_start_queue(dev);
-        }
-        if(priv->rx_disabled){
-                //printk("%d:enable_irq\n",jiffies);
-                priv->rx_disabled=0;
-                writel(ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
-        }
-}
-static void ether00_int( int irq_num, void* dev_id, struct pt_regs* regs)
-{
-        struct net_device* dev=dev_id;
-        struct net_priv* priv=dev->priv;
-        unsigned int   interruptValue;
-        interruptValue=readl(ETHER_INT_SRC(dev->base_addr));
-        //printk("INT_SRC=%x\n",interruptValue);
-        if(!(readl(ETHER_INT_SRC(dev->base_addr)) & ETHER_INT_SRC_IRQ_MSK))
-        {
-                return;         /* Interrupt wasn't caused by us!! */
-        }
-        if(readl(ETHER_INT_SRC(dev->base_addr))&
-           (ETHER_INT_SRC_INTMACRX_MSK |
-            ETHER_INT_SRC_FDAEX_MSK |
-            ETHER_INT_SRC_BLEX_MSK)) {
-                struct rx_blist_ent* blist_ent_ptr;
-                struct rx_fda_ent* fda_ent_ptr;
-                struct sk_buff* skb;
-                fda_ent_ptr=priv->rx_fda_ptr;
-                spin_lock(&priv->rx_lock);
-                while(fda_ent_ptr<(priv->rx_fda_ptr+RX_NUM_FDESC)){
-                        int result;
-                        if(!(fda_ent_ptr->fd.FDCtl&FDCTL_COWNSFD_MSK))
-                        {
-                                /* This frame is ready for processing */
-                                /*find the corresponding buffer in the bufferlist */
-                                blist_ent_ptr=priv->rx_blist_vp+fda_ent_ptr->bd.BDStat;
-                                skb=(struct sk_buff*)blist_ent_ptr->fd.FDSystem;
-                                /* Pass this skb up the stack */
-                                skb->dev=dev;
-                                skb_put(skb,fda_ent_ptr->fd.FDLength);
-                                skb->protocol=eth_type_trans(skb,dev);
-                                skb->ip_summed=CHECKSUM_UNNECESSARY;
-                                result=netif_rx(skb);
-                                /* Update statistics */
-                                priv->stats.rx_packets++;
-                                priv->stats.rx_bytes+=fda_ent_ptr->fd.FDLength;
-                                /* Free the FDA entry */
-                                fda_ent_ptr->bd.BDStat=0xff;
-                                fda_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
-                                /* Allocate a new skb and point the bd entry to it */
-                                blist_ent_ptr->fd.FDSystem=0;
-                                skb=dev_alloc_skb(PKT_BUF_SZ);
-                                //printk("allocskb=%#x\n",skb);
-                                if(skb){
-                                        setup_blist_entry(skb,blist_ent_ptr);
-                                }
-                                else if(!priv->memupdate_scheduled){
-                                        int tmp;
-                                        /* There are no buffers at the moment, so schedule */
-                                        /* the background task to sort this out */
-                                        schedule_task(&priv->tq_memupdate);
-                                        priv->memupdate_scheduled=1;
-                                        printk(KERN_DEBUG "%s:No buffers",dev->name);
-                                        /* If this interrupt was due to a lack of buffers then
-                                         * we'd better stop the receiver too */
-                                        if(interruptValue&ETHER_INT_SRC_BLEX_MSK){
-                                                priv->rx_disabled=1;
-                                                tmp=readl(ETHER_INT_SRC(dev->base_addr));
-                                                writel(tmp&~ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
-                                                printk(KERN_DEBUG "%s:Halting rx",dev->name);
-                                        }
-                                }
-                        }
-                        fda_ent_ptr++;
-                }
-                spin_unlock(&priv->rx_lock);
-                /* Clear the  interrupts */
-                writel(ETHER_INT_SRC_INTMACRX_MSK | ETHER_INT_SRC_FDAEX_MSK
-                       | ETHER_INT_SRC_BLEX_MSK,ETHER_INT_SRC(dev->base_addr));
-        }
-        if(readl(ETHER_INT_SRC(dev->base_addr))&ETHER_INT_SRC_INTMACTX_MSK){
-                if(!priv->memupdate_scheduled){
-                        schedule_task(&priv->tq_memupdate);
-                        priv->memupdate_scheduled=1;
-                }
-                /* Clear the interrupt */
-                writel(ETHER_INT_SRC_INTMACTX_MSK,ETHER_INT_SRC(dev->base_addr));
-        }
-        if (readl(ETHER_INT_SRC(dev->base_addr)) & (ETHER_INT_SRC_SWINT_MSK|
-                                                    ETHER_INT_SRC_INTEARNOT_MSK|
-                                                    ETHER_INT_SRC_INTLINK_MSK|
-                                                    ETHER_INT_SRC_INTEXBD_MSK|
-                                                    ETHER_INT_SRC_INTTXCTLCMP_MSK))
-        {
-                /*
-                 *      Not using any of these so they shouldn't happen
-                 *
-                 *      In the cased of INTEXBD - if you allocate more
-                 *      than 28 decsriptors you may need to think about this
-                 */
-                printk("Not using this interrupt\n");
-        }
-        if (readl(ETHER_INT_SRC(dev->base_addr)) &
-            (ETHER_INT_SRC_INTSBUS_MSK |
-             ETHER_INT_SRC_INTNRABT_MSK
-             |ETHER_INT_SRC_DMPARERR_MSK))
-        {
-                /*
-                 * Hardware errors, we can either ignore them and hope they go away
-                 *or reset the device, I'll try the first for now to see if they happen
-                 */
-                printk("Hardware error\n");
-        }
-}
-static void ether00_setup_ethernet_address(struct net_device* dev)
-{
-        int tmp;
-        dev->addr_len=6;
-        writew(0,ETHER_ARC_ADR(dev->base_addr));
-        writel((dev->dev_addr[0]<<24) |
-                (dev->dev_addr[1]<<16) |
-                (dev->dev_addr[2]<<8) |
-                dev->dev_addr[3],
-                ETHER_ARC_DATA(dev->base_addr));
-        writew(4,ETHER_ARC_ADR(dev->base_addr));
-        tmp=readl(ETHER_ARC_DATA(dev->base_addr));
-        tmp&=0xffff;
-        tmp|=(dev->dev_addr[4]<<24) | (dev->dev_addr[5]<<16);
-        writel(tmp, ETHER_ARC_DATA(dev->base_addr));
-        /* Enable this entry in the ARC */
-        writel(1,ETHER_ARC_ENA(dev->base_addr));
-        return;
-}
-static void ether00_reset(struct net_device *dev)
-{
-        /* reset the controller */
-        writew(ETHER_MAC_CTL_RESET_MSK,ETHER_MAC_CTL(dev->base_addr));
-        /*
-         * Make sure we're not going to send anything
-         */
-        writew(ETHER_TX_CTL_TXHALT_MSK,ETHER_TX_CTL(dev->base_addr));
-        /*
-         * Make sure we're not going to receive anything
-         */
-        writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
-        /*
-         * Disable Interrupts for now, and set the burst size to 8 bytes
-         */
-        writel(ETHER_DMA_CTL_INTMASK_MSK |
-               ((8 << ETHER_DMA_CTL_DMBURST_OFST) & ETHER_DMA_CTL_DMBURST_MSK)
-               |(2<<ETHER_DMA_CTL_RXALIGN_OFST),
-               ETHER_DMA_CTL(dev->base_addr));
-        /*
-         * Set TxThrsh - start transmitting a packet after 1514
-         * bytes or when a packet is complete, whichever comes first
-         */
-         writew(1514,ETHER_TXTHRSH(dev->base_addr));
-        /*
-         * Set TxPollCtr.  Each cycle is
-         * 61.44 microseconds with a 33 MHz bus
-         */
-         writew(1,ETHER_TXPOLLCTR(dev->base_addr));
-        /*
-         * Set Rx_Ctl - Turn off reception and let RxData turn it
-         * on later
-         */
-         writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
-}
-static void ether00_set_multicast(struct net_device* dev)
-{
-        int count=dev->mc_count;
-        /* Set promiscuous mode if it's asked for. */
-        if (dev->flags&IFF_PROMISC){
-                writew( ETHER_ARC_CTL_COMPEN_MSK |
-                        ETHER_ARC_CTL_BROADACC_MSK |
-                        ETHER_ARC_CTL_GROUPACC_MSK |
-                        ETHER_ARC_CTL_STATIONACC_MSK,
-                        ETHER_ARC_CTL(dev->base_addr));
-                return;
-        }
-        /*
-         * Get all multicast packets if required, or if there are too
-         * many addresses to fit in hardware
-         */
-        if (dev->flags & IFF_ALLMULTI){
-                writew( ETHER_ARC_CTL_COMPEN_MSK |
-                        ETHER_ARC_CTL_GROUPACC_MSK |
-                        ETHER_ARC_CTL_BROADACC_MSK,
-                        ETHER_ARC_CTL(dev->base_addr));
-                return;
-        }
-        if (dev->mc_count > (ETHER_ARC_SIZE - 1)){
-                printk(KERN_WARNING "Too many multicast addresses for hardware to filter - receiving all multicast packets\n");
-                writew( ETHER_ARC_CTL_COMPEN_MSK |
-                        ETHER_ARC_CTL_GROUPACC_MSK |
-                        ETHER_ARC_CTL_BROADACC_MSK,
-                        ETHER_ARC_CTL(dev->base_addr));
-                return;
-        }
-        if(dev->mc_count){
-                struct dev_mc_list *mc_list_ent=dev->mc_list;
-                unsigned int temp,i;
-                DEBUG(printk("mc_count=%d mc_list=%#x\n",dev-> mc_count, dev->mc_list));
-                DEBUG(printk("mc addr=%02#x%02x%02x%02x%02x%02x\n",
-                             mc_list_ent->dmi_addr[5],
-                             mc_list_ent->dmi_addr[4],
-                             mc_list_ent->dmi_addr[3],
-                             mc_list_ent->dmi_addr[2],
-                             mc_list_ent->dmi_addr[1],
-                             mc_list_ent->dmi_addr[0]);)
-                /*
-                 * The first 6 bytes are the MAC address, so
-                 * don't change them!
-                 */
-                writew(4,ETHER_ARC_ADR(dev->base_addr));
-                temp=readl(ETHER_ARC_DATA(dev->base_addr));
-                temp&=0xffff0000;
-                /* Disable the current multicast stuff */
-                writel(1,ETHER_ARC_ENA(dev->base_addr));
-                for(;;){
-                        temp|=mc_list_ent->dmi_addr[1] |
-                                mc_list_ent->dmi_addr[0]<<8;
-                        writel(temp,ETHER_ARC_DATA(dev->base_addr));
-                        i=readl(ETHER_ARC_ADR(dev->base_addr));
-                        writew(i+4,ETHER_ARC_ADR(dev->base_addr));
-                        temp=mc_list_ent->dmi_addr[5]|
-                                mc_list_ent->dmi_addr[4]<<8 |
-                                mc_list_ent->dmi_addr[3]<<16 |
-                                mc_list_ent->dmi_addr[2]<<24;
-                        writel(temp,ETHER_ARC_DATA(dev->base_addr));
-                        count--;
-                        if(!mc_list_ent->next || !count){
-                                break;
-                        }
-                        DEBUG(printk("mc_list_next=%#x\n",mc_list_ent->next);)
-                        mc_list_ent=mc_list_ent->next;
-                        i=readl(ETHER_ARC_ADR(dev->base_addr));
-                        writel(i+4,ETHER_ARC_ADR(dev->base_addr));
-                        temp=mc_list_ent->dmi_addr[3]|
-                                mc_list_ent->dmi_addr[2]<<8 |
-                                mc_list_ent->dmi_addr[1]<<16 |
-                                mc_list_ent->dmi_addr[0]<<24;
-                        writel(temp,ETHER_ARC_DATA(dev->base_addr));
-                        i=readl(ETHER_ARC_ADR(dev->base_addr));
-                        writel(i+4,ETHER_ARC_ADR(dev->base_addr));
-                        temp=mc_list_ent->dmi_addr[4]<<16 |
-                                mc_list_ent->dmi_addr[5]<<24;
-                        writel(temp,ETHER_ARC_DATA(dev->base_addr));
-                        count--;
-                        if(!mc_list_ent->next || !count){
-                                break;
-                        }
-                        mc_list_ent=mc_list_ent->next;
-                }
-                if(count)
-                        printk(KERN_WARNING "Multicast list size error\n");
-                writew( ETHER_ARC_CTL_BROADACC_MSK|
-                        ETHER_ARC_CTL_COMPEN_MSK,
-                        ETHER_ARC_CTL(dev->base_addr));
-        }
-        /* enable the active ARC enties */
-        writew((1<<(count+2))-1,ETHER_ARC_ENA(dev->base_addr));
-}
-static int ether00_open(struct net_device* dev)
-{
-        int result,tmp;
-        struct net_priv* priv;
-        if (!is_valid_ether_addr(dev->dev_addr))
-                return -EINVAL;
-        /* Install interrupt handlers */
-        result=request_irq(dev->irq,ether00_int,0,"ether00",dev);
-        if(result)
-                goto open_err1;
-        result=request_irq(2,ether00_phy_int,0,"ether00_phy",dev);
-        if(result)
-                goto open_err2;
-        ether00_reset(dev);
-        result=ether00_mem_init(dev);
-        if(result)
-                goto open_err3;
-        ether00_setup_ethernet_address(dev);
-        ether00_set_multicast(dev);
-        result=ether00_write_phy(dev,PHY_CONTROL, PHY_CONTROL_ANEGEN_MSK | PHY_CONTROL_RANEG_MSK);
-        if(result)
-                goto open_err4;
-        result=ether00_write_phy(dev,PHY_IRQ_CONTROL, PHY_IRQ_CONTROL_LS_CHG_IE_MSK |
-                                 PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK);
-        if(result)
-                goto open_err4;
-        /* Start the device enable interrupts */
-        writew(ETHER_RX_CTL_RXEN_MSK
-//             | ETHER_RX_CTL_STRIPCRC_MSK
-               | ETHER_RX_CTL_ENGOOD_MSK
-               | ETHER_RX_CTL_ENRXPAR_MSK| ETHER_RX_CTL_ENLONGERR_MSK
-               | ETHER_RX_CTL_ENOVER_MSK| ETHER_RX_CTL_ENCRCERR_MSK,
-               ETHER_RX_CTL(dev->base_addr));
-        writew(ETHER_TX_CTL_TXEN_MSK|
-               ETHER_TX_CTL_ENEXDEFER_MSK|
-               ETHER_TX_CTL_ENLCARR_MSK|
-               ETHER_TX_CTL_ENEXCOLL_MSK|
-               ETHER_TX_CTL_ENLATECOLL_MSK|
-               ETHER_TX_CTL_ENTXPAR_MSK|
-               ETHER_TX_CTL_ENCOMP_MSK,
-               ETHER_TX_CTL(dev->base_addr));
-        tmp=readl(ETHER_DMA_CTL(dev->base_addr));
-        writel(tmp&~ETHER_DMA_CTL_INTMASK_MSK,ETHER_DMA_CTL(dev->base_addr));
-        return 0;
- open_err4:
-        ether00_reset(dev);
- open_err3:
-        free_irq(2,dev);
- open_err2:
-        free_irq(dev->irq,dev);
- open_err1:
-        return result;
-}
-static int ether00_tx(struct sk_buff* skb, struct net_device* dev)
-{
-        struct net_priv *priv=dev->priv;
-        struct tx_fda_ent *fda_ptr;
-        int i;
-        /*
-         *      Find an empty slot in which to stick the frame
-         */
-        fda_ptr=(struct tx_fda_ent*)__dma_va(readl(ETHER_TXFRMPTR(dev->base_addr)));
-        i=0;
-        while(i<TX_NUM_FDESC){
-                if (fda_ptr->fd.FDStat||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
-                        fda_ptr =(struct tx_fda_ent*) __dma_va((struct tx_fda_ent*)fda_ptr->fd.FDNext);
-                }
-                else {
-                        break;
-                }
-                i++;
-        }
-        /* Write the skb data from the cache*/
-        consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE);
-        fda_ptr->bd.BuffData=(char*)__pa(skb->data);
-        fda_ptr->bd.BuffLength=(unsigned short)skb->len;
-        /* Save the pointer to the skb for freeing later */
-        fda_ptr->fd.FDSystem=(unsigned int)skb;
-        fda_ptr->fd.FDStat=0;
-        /* Pass ownership of the buffers to the controller */
-        fda_ptr->fd.FDCtl=1;
-        fda_ptr->fd.FDCtl|=FDCTL_COWNSFD_MSK;
-        /* If the next buffer in the list is full, stop the queue */
-        fda_ptr=(struct tx_fda_ent*)__dma_va(fda_ptr->fd.FDNext);
-        if ((fda_ptr->fd.FDStat)||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
-                netif_stop_queue(dev);
-                priv->queue_stopped=1;
-        }
-        return 0;
-}
-static struct net_device_stats *ether00_stats(struct net_device* dev)
-{
-        struct net_priv *priv=dev->priv;
-        return &priv->stats;
-}
-static int ether00_stop(struct net_device* dev)
-{
-        struct net_priv *priv=dev->priv;
-        int tmp;
-        /* Stop/disable the device. */
-        tmp=readw(ETHER_RX_CTL(dev->base_addr));
-        tmp&=~(ETHER_RX_CTL_RXEN_MSK | ETHER_RX_CTL_ENGOOD_MSK);
-        tmp|=ETHER_RX_CTL_RXHALT_MSK;
-        writew(tmp,ETHER_RX_CTL(dev->base_addr));
-        tmp=readl(ETHER_TX_CTL(dev->base_addr));
-        tmp&=~ETHER_TX_CTL_TXEN_MSK;
-        tmp|=ETHER_TX_CTL_TXHALT_MSK;
-        writel(tmp,ETHER_TX_CTL(dev->base_addr));
-        /* Free up system resources */
-        free_irq(dev->irq,dev);
-        free_irq(2,dev);
-        iounmap(priv->dma_data);
-        return 0;
-}
-static void ether00_get_ethernet_address(struct net_device* dev)
-{
-        struct mtd_info *mymtd=NULL;
-        int i;
-        size_t retlen;
-        /*
-         * For the Epxa10 dev board (camelot), the ethernet MAC
-         * address is of the form  00:aa:aa:00:xx:xx where
-         * 00:aa:aa is the Altera vendor ID and xx:xx is the
-         * last 2 bytes of the board serial number, as programmed
-         * into the OTP area of the flash device on EBI1. If this
-         * isn't an expa10 dev board, or there's no mtd support to
-         * read the serial number from flash then we'll force the
-         * use to set their own mac address using ifconfig.
-         */
-#ifdef CONFIG_ARCH_CAMELOT
-#ifdef CONFIG_MTD
-        /* get the mtd_info structure for the first mtd device*/
-        for(i=0;i<MAX_MTD_DEVICES;i++){
-                mymtd=get_mtd_device(NULL,i);
-                if(!mymtd||!strcmp(mymtd->name,"EPXA10DB flash"))
-                        break;
-        }
-        if(!mymtd || !mymtd->read_user_prot_reg){
-                printk(KERN_WARNING "%s: Failed to read MAC address from flash\n",dev->name);
-        }else{
-                mymtd->read_user_prot_reg(mymtd,2,1,&retlen,&dev->dev_addr[5]);
-                mymtd->read_user_prot_reg(mymtd,3,1,&retlen,&dev->dev_addr[4]);
-                dev->dev_addr[3]=0;
-                dev->dev_addr[2]=vendor_id[1];
-                dev->dev_addr[1]=vendor_id[0];
-                dev->dev_addr[0]=0;
-        }
-#else
-        printk(KERN_WARNING "%s: MTD support required to read MAC address from EPXA10 dev board\n", dev->name);
-#endif
-#endif
-        if (!is_valid_ether_addr(dev->dev_addr))
-                printk("%s: Invalid ethernet MAC address.  Please set using "
-                        "ifconfig\n", dev->name);
-}
-/*
- * Keep a mapping of dev_info addresses -> port lines to use when
- * removing ports dev==NULL indicates unused entry
- */
-static struct net_device* dev_list[ETH_NR];
-static int ether00_add_device(struct pldhs_dev_info* dev_info,void* dev_ps_data)
-{
-        struct net_device *dev;
-        struct net_priv *priv;
-        void *map_addr;
-        int result;
-        int i;
-        i=0;
-        while(dev_list[i] && i < ETH_NR)
-                i++;
-        if(i==ETH_NR){
-                printk(KERN_WARNING "ether00: Maximum number of ports reached\n");
-                return 0;
-        }
-        if (!request_mem_region(dev_info->base_addr, MAC_REG_SIZE, "ether00"))
-                return -EBUSY;
-        dev = alloc_etherdev(sizeof(struct net_priv));
-        if(!dev) {
-                result = -ENOMEM;
-                goto out_release;
-        }
-        priv = dev->priv;
-        priv->tq_memupdate.routine=ether00_mem_update;
-        priv->tq_memupdate.data=(void*) dev;
-        spin_lock_init(&priv->rx_lock);
-        map_addr=ioremap_nocache(dev_info->base_addr,SZ_4K);
-        if(!map_addr){
-                result = -ENOMEM;
-                out_kfree;
-        }
-        dev->open=ether00_open;
-        dev->stop=ether00_stop;
-        dev->set_multicast_list=ether00_set_multicast;
-        dev->hard_start_xmit=ether00_tx;
-        dev->get_stats=ether00_stats;
-        ether00_get_ethernet_address(dev);
-        SET_MODULE_OWNER(dev);
-        dev->base_addr=(unsigned int)map_addr;
-        dev->irq=dev_info->irq;
-        dev->features=NETIF_F_DYNALLOC | NETIF_F_HW_CSUM;
-        result=register_netdev(dev);
-        if(result){
-                printk("Ether00: Error %i registering driver\n",result);
-                goto out_unmap;
-        }
-        printk("registered ether00 device at %#x\n",dev_info->base_addr);
-        dev_list[i]=dev;
-        return result;
- out_unmap:
-        iounmap(map_addr);
- out_kfree:
-        free_netdev(dev);
- out_release:
-        release_mem_region(dev_info->base_addr, MAC_REG_SIZE);
-        return result;
-}
-static int ether00_remove_devices(void)
-{
-        int i;
-        for(i=0;i<ETH_NR;i++){
-                if(dev_list[i]){
-                        netif_device_detach(dev_list[i]);
-                        unregister_netdev(dev_list[i]);
-                        iounmap((void*)dev_list[i]->base_addr);
-                        release_mem_region(dev_list[i]->base_addr, MAC_REG_SIZE);
-                        free_netdev(dev_list[i]);
-                        dev_list[i]=0;
-                }
-        }
-        return 0;
-}
-static struct pld_hotswap_ops ether00_pldhs_ops={
-        .name = ETHER00_NAME,
-        .add_device = ether00_add_device,
-        .remove_devices = ether00_remove_devices,
-};
-static void __exit ether00_cleanup_module(void)
-{
-        int result;
-        result=ether00_remove_devices();
-        if(result)
-                printk(KERN_WARNING "ether00: failed to remove all devices\n");
-        pldhs_unregister_driver(ETHER00_NAME);
-}
-module_exit(ether00_cleanup_module);
-static int __init ether00_mod_init(void)
-{
-        printk("mod init\n");
-        return pldhs_register_driver(&ether00_pldhs_ops);
-}
-module_init(ether00_mod_init);
diff --git a/drivers/net/arm/ether3.c b/drivers/net/arm/ether3.c
index 1cc53abc3a39..f1d5b1027ff7 100644
--- a/drivers/net/arm/ether3.c
+++ b/drivers/net/arm/ether3.c
@@ -69,7 +69,6 @@
 #include <asm/system.h>
 #include <asm/ecard.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 static char version[] __initdata = "ether3 ethernet driver (c) 1995-2000 R.M.King v1.17\n";
diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c
index 942a2819576c..6a93b666eb72 100644
--- a/drivers/net/arm/etherh.c
+++ b/drivers/net/arm/etherh.c
@@ -50,7 +50,6 @@
 #include <asm/system.h>
 #include <asm/ecard.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include "../8390.h"
diff --git a/drivers/scsi/arm/acornscsi.c b/drivers/scsi/arm/acornscsi.c
index 09ed05727bcb..dda5a5f79c53 100644
--- a/drivers/scsi/arm/acornscsi.c
+++ b/drivers/scsi/arm/acornscsi.c
@@ -146,7 +146,6 @@
 #include <asm/system.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/ecard.h>
 #include "../scsi.h"
diff --git a/drivers/scsi/arm/arxescsi.c b/drivers/scsi/arm/arxescsi.c
index 804125e35fc3..a28940156703 100644
--- a/drivers/scsi/arm/arxescsi.c
+++ b/drivers/scsi/arm/arxescsi.c
@@ -33,7 +33,6 @@
 #include <asm/dma.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/ecard.h>
 #include "../scsi.h"
diff --git a/drivers/scsi/arm/cumana_1.c b/drivers/scsi/arm/cumana_1.c
index 81e266be26d0..e6c9491dc5c0 100644
--- a/drivers/scsi/arm/cumana_1.c
+++ b/drivers/scsi/arm/cumana_1.c
@@ -13,7 +13,6 @@
 #include <asm/ecard.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include "../scsi.h"
diff --git a/drivers/scsi/arm/cumana_2.c b/drivers/scsi/arm/cumana_2.c
index 3a7a46b0dc41..583d2d8c8335 100644
--- a/drivers/scsi/arm/cumana_2.c
+++ b/drivers/scsi/arm/cumana_2.c
@@ -31,7 +31,6 @@
 #include <asm/dma.h>
 #include <asm/ecard.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/pgtable.h>
 #include "../scsi.h"
diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c
index 4d1e8f52c924..3ffec7efc9d5 100644
--- a/drivers/scsi/arm/eesox.c
+++ b/drivers/scsi/arm/eesox.c
@@ -35,7 +35,6 @@
 #include <linux/dma-mapping.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/dma.h>
 #include <asm/ecard.h>
 #include <asm/pgtable.h>
diff --git a/drivers/scsi/arm/powertec.c b/drivers/scsi/arm/powertec.c
index 3333d7b39139..3113bdcedb13 100644
--- a/drivers/scsi/arm/powertec.c
+++ b/drivers/scsi/arm/powertec.c
@@ -22,7 +22,6 @@
 #include <asm/dma.h>
 #include <asm/ecard.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/pgtable.h>
 #include "../scsi.h"
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 3fd5b999fdac..1bae26a8a503 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -369,29 +369,6 @@ config SERIAL_21285_CONSOLE
          your boot loader (lilo or loadlin) about how to pass options to the
          kernel at boot time.)
-config SERIAL_UART00
-        bool "Excalibur serial port (uart00) support"
-        depends on ARM && ARCH_CAMELOT
-        select SERIAL_CORE
-        help
-          Say Y here if you want to use the hard logic uart on Excalibur. This
-          driver also supports soft logic implementations of this uart core.
-config SERIAL_UART00_CONSOLE
-        bool "Support for console on Excalibur serial port"
-        depends on SERIAL_UART00
-        select SERIAL_CORE_CONSOLE
-        help
-          Say Y here if you want to support a serial console on an Excalibur
-          hard logic uart or uart00 IP core.
-          Even if you say Y here, the currently visible virtual console
-          (/dev/tty0) will still be used as the system console by default, but
-          you can alter that using a kernel command line option such as
-          "console=ttyS1". (Try "man bootparam" or see the documentation of
-          your boot loader (lilo or loadlin) about how to pass options to the
-          kernel at boot time.)
 config SERIAL_MPSC
        bool "Marvell MPSC serial port support"
        depends on PPC32 && MV64X60
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d7c7c7180e33..137148bba4fa 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
 obj-$(CONFIG_SERIAL_PXA) += pxa.o
 obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
 obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
-obj-$(CONFIG_SERIAL_UART00) += uart00.o
 obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
 obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
 obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
diff --git a/drivers/serial/uart00.c b/drivers/serial/uart00.c
deleted file mode 100644
index 47b504ff38b2..000000000000
--- a/drivers/serial/uart00.c
+++ /dev/null
@@ -1,782 +0,0 @@
-/*
- *  linux/drivers/serial/uart00.c
- *
- *  Driver for UART00 serial ports
- *
- *  Based on drivers/char/serial_amba.c, by ARM Limited & 
- *                                          Deep Blue Solutions Ltd.
- *  Copyright 2001 Altera Corporation
- *
- *  Update for 2.6.4 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *  $Id: uart00.c,v 1.35 2002/07/28 10:03:28 rmk Exp $
- *
- */
-#include <linux/config.h>
-#if defined(CONFIG_SERIAL_UART00_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-#define SUPPORT_SYSRQ
-#endif
-#include <linux/module.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/sysrq.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
-#include <linux/serial_core.h>
-#include <linux/serial.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/sizes.h>
-#include <asm/arch/excalibur.h>
-#define UART00_TYPE (volatile unsigned int*)
-#include <asm/arch/uart00.h>
-#include <asm/arch/int_ctrl00.h>
-#define UART_NR         2
-#define SERIAL_UART00_NAME      "ttyUA"
-#define SERIAL_UART00_MAJOR     204
-#define SERIAL_UART00_MINOR     16      /* Temporary - will change in future */
-#define SERIAL_UART00_NR        UART_NR
-#define UART_PORT_SIZE 0x50
-#define UART00_ISR_PASS_LIMIT   256
-/*
- * Access macros for the UART00 UARTs
- */
-#define UART_GET_INT_STATUS(p)  inl(UART_ISR((p)->membase))
-#define UART_PUT_IES(p, c)      outl(c,UART_IES((p)->membase))
-#define UART_GET_IES(p)         inl(UART_IES((p)->membase))
-#define UART_PUT_IEC(p, c)      outl(c,UART_IEC((p)->membase))
-#define UART_GET_IEC(p)         inl(UART_IEC((p)->membase))
-#define UART_PUT_CHAR(p, c)     outl(c,UART_TD((p)->membase))
-#define UART_GET_CHAR(p)        inl(UART_RD((p)->membase))
-#define UART_GET_RSR(p)         inl(UART_RSR((p)->membase))
-#define UART_GET_RDS(p)         inl(UART_RDS((p)->membase))
-#define UART_GET_MSR(p)         inl(UART_MSR((p)->membase))
-#define UART_GET_MCR(p)         inl(UART_MCR((p)->membase))
-#define UART_PUT_MCR(p, c)      outl(c,UART_MCR((p)->membase))
-#define UART_GET_MC(p)          inl(UART_MC((p)->membase))
-#define UART_PUT_MC(p, c)       outl(c,UART_MC((p)->membase))
-#define UART_GET_TSR(p)         inl(UART_TSR((p)->membase))
-#define UART_GET_DIV_HI(p)      inl(UART_DIV_HI((p)->membase))
-#define UART_PUT_DIV_HI(p,c)    outl(c,UART_DIV_HI((p)->membase))
-#define UART_GET_DIV_LO(p)      inl(UART_DIV_LO((p)->membase))
-#define UART_PUT_DIV_LO(p,c)    outl(c,UART_DIV_LO((p)->membase))
-#define UART_RX_DATA(s)         ((s) & UART_RSR_RX_LEVEL_MSK)
-#define UART_TX_READY(s)        (((s) & UART_TSR_TX_LEVEL_MSK) < 15)
-//#define UART_TX_EMPTY(p)      ((UART_GET_FR(p) & UART00_UARTFR_TMSK) == 0)
-static void uart00_stop_tx(struct uart_port *port)
-{
-        UART_PUT_IEC(port, UART_IEC_TIE_MSK);
-}
-static void uart00_stop_rx(struct uart_port *port)
-{
-        UART_PUT_IEC(port, UART_IEC_RE_MSK);
-}
-static void uart00_enable_ms(struct uart_port *port)
-{
-        UART_PUT_IES(port, UART_IES_ME_MSK);
-}
-static void
-uart00_rx_chars(struct uart_port *port, struct pt_regs *regs)
-{
-        struct tty_struct *tty = port->info->tty;
-        unsigned int status, ch, rds, flg, ignored = 0;
-        status = UART_GET_RSR(port);
-        while (UART_RX_DATA(status)) {
-                /* 
-                 * We need to read rds before reading the 
-                 * character from the fifo
-                 */
-                rds = UART_GET_RDS(port);
-                ch = UART_GET_CHAR(port);
-                port->icount.rx++;
-                if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-                        goto ignore_char;
-                flg = TTY_NORMAL;
-                /*
-                 * Note that the error handling code is
-                 * out of the main execution path
-                 */
-                if (rds & (UART_RDS_BI_MSK |UART_RDS_FE_MSK|
-                           UART_RDS_PE_MSK |UART_RDS_PE_MSK))
-                        goto handle_error;
-                if (uart_handle_sysrq_char(port, ch, regs))
-                        goto ignore_char;
-        error_return:
-                tty_insert_flip_char(tty, ch, flg);
-        ignore_char:
-                status = UART_GET_RSR(port);
-        }
- out:
-        tty_flip_buffer_push(tty);
-        return;
- handle_error:
-        if (rds & UART_RDS_BI_MSK) {
-                status &= ~(UART_RDS_FE_MSK | UART_RDS_PE_MSK);
-                port->icount.brk++;
-                if (uart_handle_break(port))
-                        goto ignore_char;
-        } else if (rds & UART_RDS_PE_MSK)
-                port->icount.parity++;
-        else if (rds & UART_RDS_FE_MSK)
-                port->icount.frame++;
-        if (rds & UART_RDS_OE_MSK)
-                port->icount.overrun++;
-        if (rds & port->ignore_status_mask) {
-                if (++ignored > 100)
-                        goto out;
-                goto ignore_char;
-        }
-        rds &= port->read_status_mask;
-        if (rds & UART_RDS_BI_MSK)
-                flg = TTY_BREAK;
-        else if (rds & UART_RDS_PE_MSK)
-                flg = TTY_PARITY;
-        else if (rds & UART_RDS_FE_MSK)
-                flg = TTY_FRAME;
-        if (rds & UART_RDS_OE_MSK) {
-                /*
-                 * CHECK: does overrun affect the current character?
-                 * ASSUMPTION: it does not.
-                 */
-                tty_insert_flip_char(tty, ch, flg);
-                ch = 0;
-                flg = TTY_OVERRUN;
-        }
-#ifdef SUPPORT_SYSRQ
-        port->sysrq = 0;
-#endif
-        goto error_return;
-}
-static void uart00_tx_chars(struct uart_port *port)
-{
-        struct circ_buf *xmit = &port->info->xmit;
-        int count;
-        if (port->x_char) {
-                while ((UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK) == 15)
-                        barrier();
-                UART_PUT_CHAR(port, port->x_char);
-                port->icount.tx++;
-                port->x_char = 0;
-                return;
-        }
-        if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
-                uart00_stop_tx(port);
-                return;
-        }
-        count = port->fifosize >> 1;
-        do {
-                while ((UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK) == 15)
-                        barrier();
-                UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
-                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-                port->icount.tx++;
-                if (uart_circ_empty(xmit))
-                        break;
-        } while (--count > 0);
-        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-                uart_write_wakeup(port);
-        if (uart_circ_empty(xmit))
-                uart00_stop_tx(port);
-}
-static void uart00_start_tx(struct uart_port *port)
-{
-        UART_PUT_IES(port, UART_IES_TIE_MSK);
-        uart00_tx_chars(port);
-}
-static void uart00_modem_status(struct uart_port *port)
-{
-        unsigned int status;
-        status = UART_GET_MSR(port);
-        if (!(status & (UART_MSR_DCTS_MSK | UART_MSR_DDSR_MSK | 
-                        UART_MSR_TERI_MSK | UART_MSR_DDCD_MSK)))
-                return;
-        if (status & UART_MSR_DDCD_MSK)
-                uart_handle_dcd_change(port, status & UART_MSR_DCD_MSK);
-        if (status & UART_MSR_DDSR_MSK)
-                port->icount.dsr++;
-        if (status & UART_MSR_DCTS_MSK)
-                uart_handle_cts_change(port, status & UART_MSR_CTS_MSK);
-        wake_up_interruptible(&port->info->delta_msr_wait);
-}
-static irqreturn_t uart00_int(int irq, void *dev_id, struct pt_regs *regs)
-{
-        struct uart_port *port = dev_id;
-        unsigned int status, pass_counter = 0;
-        status = UART_GET_INT_STATUS(port);
-        do {
-                if (status & UART_ISR_RI_MSK)
-                        uart00_rx_chars(port, regs);
-                if (status & UART_ISR_MI_MSK)
-                        uart00_modem_status(port);
-                if (status & (UART_ISR_TI_MSK | UART_ISR_TII_MSK))
-                        uart00_tx_chars(port);
-                if (pass_counter++ > UART00_ISR_PASS_LIMIT)
-                        break;
-                status = UART_GET_INT_STATUS(port);
-        } while (status);
-        return IRQ_HANDLED;
-}
-static unsigned int uart00_tx_empty(struct uart_port *port)
-{
-        return UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK? 0 : TIOCSER_TEMT;
-}
-static unsigned int uart00_get_mctrl(struct uart_port *port)
-{
-        unsigned int result = 0;
-        unsigned int status;
-        status = UART_GET_MSR(port);
-        if (status & UART_MSR_DCD_MSK)
-                result |= TIOCM_CAR;
-        if (status & UART_MSR_DSR_MSK)
-                result |= TIOCM_DSR;
-        if (status & UART_MSR_CTS_MSK)
-                result |= TIOCM_CTS;
-        if (status & UART_MSR_RI_MSK)
-                result |= TIOCM_RI;
-        return result;
-}
-static void uart00_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
-{
-}
-static void uart00_break_ctl(struct uart_port *port, int break_state)
-{
-        unsigned long flags;
-        unsigned int mcr;
-        spin_lock_irqsave(&port->lock, flags);
-        mcr = UART_GET_MCR(port);
-        if (break_state == -1)
-                mcr |= UART_MCR_BR_MSK;
-        else
-                mcr &= ~UART_MCR_BR_MSK;
-        UART_PUT_MCR(port, mcr);
-        spin_unlock_irqrestore(&port->lock, flags);
-}
-static void
-uart00_set_termios(struct uart_port *port, struct termios *termios,
-                   struct termios *old)
-{
-        unsigned int uart_mc, old_ies, baud, quot;
-        unsigned long flags;
-        /*
-         * We don't support CREAD (yet)
-         */
-        termios->c_cflag |= CREAD;
-        /*
-         * Ask the core to calculate the divisor for us.
-         */
-        baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 
-        quot = uart_get_divisor(port, baud);
-        /* byte size and parity */
-        switch (termios->c_cflag & CSIZE) {
-        case CS5:
-                uart_mc = UART_MC_CLS_CHARLEN_5;
-                break;
-        case CS6:
-                uart_mc = UART_MC_CLS_CHARLEN_6;
-                break;
-        case CS7:
-                uart_mc = UART_MC_CLS_CHARLEN_7;
-                break;
-        default: // CS8
-                uart_mc = UART_MC_CLS_CHARLEN_8;
-                break;
-        }
-        if (termios->c_cflag & CSTOPB)
-                uart_mc|= UART_MC_ST_TWO;
-        if (termios->c_cflag & PARENB) {
-                uart_mc |= UART_MC_PE_MSK;
-                if (!(termios->c_cflag & PARODD))
-                        uart_mc |= UART_MC_EP_MSK;
-        }
-        spin_lock_irqsave(&port->lock, flags);
-        /*
-         * Update the per-port timeout.
-         */
-        uart_update_timeout(port, termios->c_cflag, baud);
-        port->read_status_mask = UART_RDS_OE_MSK;
-        if (termios->c_iflag & INPCK)
-                port->read_status_mask |= UART_RDS_FE_MSK | UART_RDS_PE_MSK;
-        if (termios->c_iflag & (BRKINT | PARMRK))
-                port->read_status_mask |= UART_RDS_BI_MSK;
-        /*
-         * Characters to ignore
-         */
-        port->ignore_status_mask = 0;
-        if (termios->c_iflag & IGNPAR)
-                port->ignore_status_mask |= UART_RDS_FE_MSK | UART_RDS_PE_MSK;
-        if (termios->c_iflag & IGNBRK) {
-                port->ignore_status_mask |= UART_RDS_BI_MSK;
-                /*
-                 * If we're ignoring parity and break indicators,
-                 * ignore overruns to (for real raw support).
-                 */
-                if (termios->c_iflag & IGNPAR)
-                        port->ignore_status_mask |= UART_RDS_OE_MSK;
-        }
-        /* first, disable everything */
-        old_ies = UART_GET_IES(port); 
-        if (UART_ENABLE_MS(port, termios->c_cflag))
-                old_ies |= UART_IES_ME_MSK;
-        /* Set baud rate */
-        UART_PUT_DIV_LO(port, (quot & 0xff));
-        UART_PUT_DIV_HI(port, ((quot & 0xf00) >> 8));
-        UART_PUT_MC(port, uart_mc);
-        UART_PUT_IES(port, old_ies);
-        spin_unlock_irqrestore(&port->lock, flags);
-}
-static int uart00_startup(struct uart_port *port)
-{
-        int result;
-        /*
-         * Allocate the IRQ
-         */
-        result = request_irq(port->irq, uart00_int, 0, "uart00", port);
-        if (result) {
-                printk(KERN_ERR "Request of irq %d failed\n", port->irq);
-                return result;
-        }
-        /*
-         * Finally, enable interrupts. Use the TII interrupt to minimise 
-         * the number of interrupts generated. If higher performance is 
-         * needed, consider using the TI interrupt with a suitable FIFO
-         * threshold
-         */
-        UART_PUT_IES(port, UART_IES_RE_MSK | UART_IES_TIE_MSK);
-        return 0;
-}
-static void uart00_shutdown(struct uart_port *port)
-{
-        /*
-         * disable all interrupts, disable the port
-         */
-        UART_PUT_IEC(port, 0xff);
-        /* disable break condition and fifos */
-        UART_PUT_MCR(port, UART_GET_MCR(port) &~UART_MCR_BR_MSK);
-        /*
-         * Free the interrupt
-         */
-        free_irq(port->irq, port);
-}
-static const char *uart00_type(struct uart_port *port)
-{
-        return port->type == PORT_UART00 ? "Altera UART00" : NULL;
-}
-/*
- * Release the memory region(s) being used by 'port'
- */
-static void uart00_release_port(struct uart_port *port)
-{
-        release_mem_region(port->mapbase, UART_PORT_SIZE);
-#ifdef CONFIG_ARCH_CAMELOT
-        if (port->membase != (void*)IO_ADDRESS(EXC_UART00_BASE)) {
-                iounmap(port->membase);
-        }
-#endif
-}
-/*
- * Request the memory region(s) being used by 'port'
- */
-static int uart00_request_port(struct uart_port *port)
-{
-        return request_mem_region(port->mapbase, UART_PORT_SIZE, "serial_uart00")
-                        != NULL ? 0 : -EBUSY;
-}
-/*
- * Configure/autoconfigure the port.
- */
-static void uart00_config_port(struct uart_port *port, int flags)
-{
-        /*
-         * Map the io memory if this is a soft uart
-         */
-        if (!port->membase)
-                port->membase = ioremap_nocache(port->mapbase,SZ_4K);
-        if (!port->membase)
-                printk(KERN_ERR "serial00: cannot map io memory\n");
-        else
-                port->type = PORT_UART00;
-}
-/*
- * verify the new serial_struct (for TIOCSSERIAL).
- */
-static int uart00_verify_port(struct uart_port *port, struct serial_struct *ser)
-{
-        int ret = 0;
-        if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00)
-                ret = -EINVAL;
-        if (ser->irq < 0 || ser->irq >= NR_IRQS)
-                ret = -EINVAL;
-        if (ser->baud_base < 9600)
-                ret = -EINVAL;
-        return ret;
-}
-static struct uart_ops uart00_pops = {
-        .tx_empty       = uart00_tx_empty,
-        .set_mctrl      = uart00_set_mctrl_null,
-        .get_mctrl      = uart00_get_mctrl,
-        .stop_tx        = uart00_stop_tx,
-        .start_tx       = uart00_start_tx,
-        .stop_rx        = uart00_stop_rx,
-        .enable_ms      = uart00_enable_ms,
-        .break_ctl      = uart00_break_ctl,
-        .startup        = uart00_startup,
-        .shutdown       = uart00_shutdown,
-        .set_termios    = uart00_set_termios,
-        .type           = uart00_type,
-        .release_port   = uart00_release_port,
-        .request_port   = uart00_request_port,
-        .config_port    = uart00_config_port,
-        .verify_port    = uart00_verify_port,
-};
-#ifdef CONFIG_ARCH_CAMELOT
-static struct uart_port epxa10db_port = {
-        .membase        = (void*)IO_ADDRESS(EXC_UART00_BASE),
-        .mapbase        = EXC_UART00_BASE,
-        .iotype         = SERIAL_IO_MEM,
-        .irq            = IRQ_UART,
-        .uartclk        = EXC_AHB2_CLK_FREQUENCY,
-        .fifosize       = 16,
-        .ops            = &uart00_pops,
-        .flags          = ASYNC_BOOT_AUTOCONF,
-};
-#endif
-#ifdef CONFIG_SERIAL_UART00_CONSOLE
-static void uart00_console_write(struct console *co, const char *s, unsigned count)
-{
-#ifdef CONFIG_ARCH_CAMELOT
-        struct uart_port *port = &epxa10db_port;
-        unsigned int status, old_ies;
-        int i;
-        /*
-         *      First save the CR then disable the interrupts
-         */
-        old_ies = UART_GET_IES(port);
-        UART_PUT_IEC(port,0xff);
-        /*
-         *      Now, do each character
-         */
-        for (i = 0; i < count; i++) {
-                do {
-                        status = UART_GET_TSR(port);
-                } while (!UART_TX_READY(status));
-                UART_PUT_CHAR(port, s[i]);
-                if (s[i] == '\n') {
-                        do {
-                                status = UART_GET_TSR(port);
-                        } while (!UART_TX_READY(status));
-                        UART_PUT_CHAR(port, '\r');
-                }
-        }
-        /*
-         *      Finally, wait for transmitter to become empty
-         *      and restore the IES
-         */
-        do {
-                status = UART_GET_TSR(port);
-        } while (status & UART_TSR_TX_LEVEL_MSK);
-        UART_PUT_IES(port, old_ies);
-#endif
-}
-static void __init
-uart00_console_get_options(struct uart_port *port, int *baud,
-                           int *parity, int *bits)
-{
-        unsigned int uart_mc, quot;
-        uart_mc = UART_GET_MC(port);
-        *parity = 'n';
-        if (uart_mc & UART_MC_PE_MSK) {
-                if (uart_mc & UART_MC_EP_MSK)
-                        *parity = 'e';
-                else
-                        *parity = 'o';
-        }
-        switch (uart_mc & UART_MC_CLS_MSK) {
-        case UART_MC_CLS_CHARLEN_5:
-                *bits = 5;
-                break;
-        case UART_MC_CLS_CHARLEN_6:
-                *bits = 6;
-                break;
-        case UART_MC_CLS_CHARLEN_7:
-                *bits = 7;
-                break;
-        case UART_MC_CLS_CHARLEN_8:
-                *bits = 8;
-                break;
-        }
-        quot = UART_GET_DIV_LO(port) | (UART_GET_DIV_HI(port) << 8);
-        *baud = port->uartclk / (16 *quot );
-}
-static int __init uart00_console_setup(struct console *co, char *options)
-{
-        struct uart_port *port;
-        int baud = 115200;
-        int bits = 8;
-        int parity = 'n';
-        int flow = 'n';
-#ifdef CONFIG_ARCH_CAMELOT
-        port = &epxa10db_port;             ;
-#else
-        return -ENODEV;
-#endif
-        if (options)
-                uart_parse_options(options, &baud, &parity, &bits, &flow);
-        else
-                uart00_console_get_options(port, &baud, &parity, &bits);
-        return uart_set_options(port, co, baud, parity, bits, flow);
-}
-extern struct uart_driver uart00_reg;
-static struct console uart00_console = {
-        .name           = SERIAL_UART00_NAME,
-        .write          = uart00_console_write,
-        .device         = uart_console_device,
-        .setup          = uart00_console_setup,
-        .flags          = CON_PRINTBUFFER,
-        .index          = 0,
-        .data           = &uart00_reg,
-};
-static int __init uart00_console_init(void)
-{
-        register_console(&uart00_console);
-        return 0;
-}
-console_initcall(uart00_console_init);
-#define UART00_CONSOLE  &uart00_console
-#else
-#define UART00_CONSOLE  NULL
-#endif
-static struct uart_driver uart00_reg = {
-        .owner                  = NULL,
-        .driver_name            = SERIAL_UART00_NAME,
-        .dev_name               = SERIAL_UART00_NAME,
-        .major                  = SERIAL_UART00_MAJOR,
-        .minor                  = SERIAL_UART00_MINOR,
-        .nr                     = UART_NR,
-        .cons                   = UART00_CONSOLE,
-};
-struct dev_port_entry{
-        unsigned int base_addr;
-        struct uart_port *port;
-};
-#ifdef CONFIG_PLD_HOTSWAP
-static struct dev_port_entry dev_port_map[UART_NR];
-/*
- * Keep a mapping of dev_info addresses -> port lines to use when
- * removing ports dev==NULL indicates unused entry
- */
-struct uart00_ps_data{
-        unsigned int clk;
-        unsigned int fifosize;
-};
-int uart00_add_device(struct pldhs_dev_info* dev_info, void* dev_ps_data)
-{
-        struct uart00_ps_data* dev_ps=dev_ps_data;
-        struct uart_port * port;
-        int i,result;
-        i=0;
-        while(dev_port_map[i].port)
-                i++;
-        if(i==UART_NR){
-                printk(KERN_WARNING "uart00: Maximum number of ports reached\n");
-                return 0;
-        }
-        port=kmalloc(sizeof(struct uart_port),GFP_KERNEL);
-        if(!port)
-                return -ENOMEM;
-        printk("clk=%d fifo=%d\n",dev_ps->clk,dev_ps->fifosize);
-        port->membase=0;
-        port->mapbase=dev_info->base_addr;
-        port->iotype=SERIAL_IO_MEM;
-        port->irq=dev_info->irq;
-        port->uartclk=dev_ps->clk;
-        port->fifosize=dev_ps->fifosize;
-        port->ops=&uart00_pops;
-        port->line=i;
-        port->flags=ASYNC_BOOT_AUTOCONF;
-        result=uart_add_one_port(&uart00_reg, port);
-        if(result){
-                printk("uart_add_one_port returned %d\n",result);
-                return result;
-        }
-        dev_port_map[i].base_addr=dev_info->base_addr;
-        dev_port_map[i].port=port;
-        printk("uart00: added device at %x as ttyUA%d\n",dev_port_map[i].base_addr,i);
-        return 0;
-}
-int uart00_remove_devices(void)
-{
-        int i,result;
-        result=0;
-        for(i=1;i<UART_NR;i++){
-                if(dev_port_map[i].base_addr){
-                        result=uart_remove_one_port(&uart00_reg, dev_port_map[i].port);
-                        if(result)
-                                return result;
-                        /* port removed sucessfully, so now tidy up */
-                        kfree(dev_port_map[i].port);
-                        dev_port_map[i].base_addr=0;
-                        dev_port_map[i].port=NULL;
-                }
-        }
-        return 0;
-}
-struct pld_hotswap_ops uart00_pldhs_ops={
-        .name           = "uart00",
-        .add_device     = uart00_add_device,
-        .remove_devices = uart00_remove_devices,
-};
-#endif
-static int __init uart00_init(void)
-{
-        int result;
-        printk(KERN_INFO "Serial: UART00 driver $Revision: 1.35 $\n");
-        printk(KERN_WARNING "serial_uart00:Using temporary major/minor pairs"
-                " - these WILL change in the future\n");
-        result = uart_register_driver(&uart00_reg);
-        if (result)
-                return result;
-#ifdef CONFIG_ARCH_CAMELOT
-        result = uart_add_one_port(&uart00_reg,&epxa10db_port);
-#endif
-        if (result)
-                uart_unregister_driver(&uart00_reg);
-#ifdef  CONFIG_PLD_HOTSWAP
-        pldhs_register_driver(&uart00_pldhs_ops);
-#endif
-        return result;
-}
-__initcall(uart00_init);
diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c
index a9300f930ef2..55a3514157ed 100644
--- a/drivers/video/cyber2000fb.c
+++ b/drivers/video/cyber2000fb.c
@@ -50,7 +50,6 @@
 #include <linux/init.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
index 2ea1354e439f..087e58689e4c 100644
--- a/drivers/video/sa1100fb.c
+++ b/drivers/video/sa1100fb.c
@@ -178,7 +178,6 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
-#include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/uaccess.h>
 #include <asm/arch/assabet.h>
@@ -1455,7 +1454,11 @@ static struct sa1100fb_info * __init sa1100fb_init_fbinfo(struct device *dev)
 static int __init sa1100fb_probe(struct platform_device *pdev)
 {
        struct sa1100fb_info *fbi;
-        int ret;
+        int ret, irq;
+        irq = platform_get_irq(pdev, 0);
+        if (irq <= 0)
+                return -EINVAL;
        if (!request_mem_region(0xb0100000, 0x10000, "LCD"))
                return -EBUSY;
@@ -1470,7 +1473,7 @@ static int __init sa1100fb_probe(struct platform_device *pdev)
        if (ret)
                goto failed;
-        ret = request_irq(IRQ_LCD, sa1100fb_handle_irq, SA_INTERRUPT,
+        ret = request_irq(irq, sa1100fb_handle_irq, SA_INTERRUPT,
                          "LCD", fbi);
        if (ret) {
                printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret);
@@ -1492,7 +1495,7 @@ static int __init sa1100fb_probe(struct platform_device *pdev)
        ret = register_framebuffer(&fbi->fb);
        if (ret < 0)
-                goto failed;
+                goto err_free_irq;
 #ifdef CONFIG_CPU_FREQ
        fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
@@ -1504,7 +1507,9 @@ static int __init sa1100fb_probe(struct platform_device *pdev)
        /* This driver cannot be unloaded at the moment */
        return 0;
-failed:
+ err_free_irq:
+        free_irq(irq, fbi);
+ failed:
        platform_set_drvdata(pdev, NULL);
        kfree(fbi);
        release_mem_region(0xb0100000, 0x10000);
diff --git a/fs/partitions/Kconfig b/fs/partitions/Kconfig
index e227a04261ab..7490cc9208b3 100644
--- a/fs/partitions/Kconfig
+++ b/fs/partitions/Kconfig
@@ -21,26 +21,30 @@ config ACORN_PARTITION
          Support hard disks partitioned under Acorn operating systems.
 config ACORN_PARTITION_CUMANA
-        bool "Cumana partition support" if PARTITION_ADVANCED && ACORN_PARTITION
+        bool "Cumana partition support" if PARTITION_ADVANCED
        default y if ARCH_ACORN
+        depends on ACORN_PARTITION
        help
          Say Y here if you would like to use hard disks under Linux which
          were partitioned using the Cumana interface on Acorn machines.
 config ACORN_PARTITION_EESOX
-        bool "EESOX partition support" if PARTITION_ADVANCED && ACORN_PARTITION
+        bool "EESOX partition support" if PARTITION_ADVANCED
        default y if ARCH_ACORN
+        depends on ACORN_PARTITION
 config ACORN_PARTITION_ICS
-        bool "ICS partition support" if PARTITION_ADVANCED && ACORN_PARTITION
+        bool "ICS partition support" if PARTITION_ADVANCED
        default y if ARCH_ACORN
+        depends on ACORN_PARTITION
        help
          Say Y here if you would like to use hard disks under Linux which
          were partitioned using the ICS interface on Acorn machines.
 config ACORN_PARTITION_ADFS
-        bool "Native filecore partition support" if PARTITION_ADVANCED && ACORN_PARTITION
+        bool "Native filecore partition support" if PARTITION_ADVANCED
        default y if ARCH_ACORN
+        depends on ACORN_PARTITION
        help
          The Acorn Disc Filing System is the standard file system of the
          RiscOS operating system which runs on Acorn's ARM-based Risc PC
@@ -48,15 +52,17 @@ config ACORN_PARTITION_ADFS
          `Y' here, Linux will support disk partitions created under ADFS.
 config ACORN_PARTITION_POWERTEC
-        bool "PowerTec partition support" if PARTITION_ADVANCED && ACORN_PARTITION
+        bool "PowerTec partition support" if PARTITION_ADVANCED
        default y if ARCH_ACORN
+        depends on ACORN_PARTITION
        help
          Support reading partition tables created on Acorn machines using
          the PowerTec SCSI drive.
 config ACORN_PARTITION_RISCIX
-        bool "RISCiX partition support" if PARTITION_ADVANCED && ACORN_PARTITION
+        bool "RISCiX partition support" if PARTITION_ADVANCED
        default y if ARCH_ACORN
+        depends on ACORN_PARTITION
        help
          Once upon a time, there was a native Unix port for the Acorn series
          of machines called RISCiX.  If you say 'Y' here, Linux will be able
@@ -224,5 +230,3 @@ config EFI_PARTITION
          Say Y here if you would like to use hard disks under Linux which
          were partitioned using EFI GPT.  Presently only useful on the
          IA-64 platform.
-#      define_bool CONFIG_ACORN_PARTITION_CUMANA y
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
new file mode 100644
index 000000000000..58f40931a5c1
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -0,0 +1,261 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Common definitions.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ     0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS     1       /* System Peripheral */
+#define AT91_ID_PIOA    2       /* Parallel IO Controller A */
+#define AT91_ID_PIOB    3       /* Parallel IO Controller B */
+#define AT91_ID_PIOC    4       /* Parallel IO Controller C */
+#define AT91_ID_PIOD    5       /* Parallel IO Controller D */
+#define AT91_ID_US0     6       /* USART 0 */
+#define AT91_ID_US1     7       /* USART 1 */
+#define AT91_ID_US2     8       /* USART 2 */
+#define AT91_ID_US3     9       /* USART 3 */
+#define AT91_ID_MCI     10      /* Multimedia Card Interface */
+#define AT91_ID_UDP     11      /* USB Device Port */
+#define AT91_ID_TWI     12      /* Two-Wire Interface */
+#define AT91_ID_SPI     13      /* Serial Peripheral Interface */
+#define AT91_ID_SSC0    14      /* Serial Synchronous Controller 0 */
+#define AT91_ID_SSC1    15      /* Serial Synchronous Controller 1 */
+#define AT91_ID_SSC2    16      /* Serial Synchronous Controller 2 */
+#define AT91_ID_TC0     17      /* Timer Counter 0 */
+#define AT91_ID_TC1     18      /* Timer Counter 1 */
+#define AT91_ID_TC2     19      /* Timer Counter 2 */
+#define AT91_ID_TC3     20      /* Timer Counter 3 */
+#define AT91_ID_TC4     21      /* Timer Counter 4 */
+#define AT91_ID_TC5     22      /* Timer Counter 5 */
+#define AT91_ID_UHP     23      /* USB Host port */
+#define AT91_ID_EMAC    24      /* Ethernet MAC */
+#define AT91_ID_IRQ0    25      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91_ID_IRQ1    26      /* Advanced Interrupt Controller (IRQ1) */
+#define AT91_ID_IRQ2    27      /* Advanced Interrupt Controller (IRQ2) */
+#define AT91_ID_IRQ3    28      /* Advanced Interrupt Controller (IRQ3) */
+#define AT91_ID_IRQ4    29      /* Advanced Interrupt Controller (IRQ4) */
+#define AT91_ID_IRQ5    30      /* Advanced Interrupt Controller (IRQ5) */
+#define AT91_ID_IRQ6    31      /* Advanced Interrupt Controller (IRQ6) */
+/*
+ * Peripheral physical base addresses.
+ */
+#define AT91_BASE_TCB0          0xfffa0000
+#define AT91_BASE_TC0           0xfffa0000
+#define AT91_BASE_TC1           0xfffa0040
+#define AT91_BASE_TC2           0xfffa0080
+#define AT91_BASE_TCB1          0xfffa4000
+#define AT91_BASE_TC3           0xfffa4000
+#define AT91_BASE_TC4           0xfffa4040
+#define AT91_BASE_TC5           0xfffa4080
+#define AT91_BASE_UDP           0xfffb0000
+#define AT91_BASE_MCI           0xfffb4000
+#define AT91_BASE_TWI           0xfffb8000
+#define AT91_BASE_EMAC          0xfffbc000
+#define AT91_BASE_US0           0xfffc0000
+#define AT91_BASE_US1           0xfffc4000
+#define AT91_BASE_US2           0xfffc8000
+#define AT91_BASE_US3           0xfffcc000
+#define AT91_BASE_SSC0          0xfffd0000
+#define AT91_BASE_SSC1          0xfffd4000
+#define AT91_BASE_SSC2          0xfffd8000
+#define AT91_BASE_SPI           0xfffe0000
+#define AT91_BASE_SYS           0xfffff000
+/*
+ * PIO pin definitions (peripheral A/B multiplexing).
+ */
+#define AT91_PA0_MISO           (1 <<  0)       /* A: SPI Master-In Slave-Out */
+#define AT91_PA0_PCK3           (1 <<  0)       /* B: PMC Programmable Clock Output 3 */
+#define AT91_PA1_MOSI           (1 <<  1)       /* A: SPI Master-Out Slave-In */
+#define AT91_PA1_PCK0           (1 <<  1)       /* B: PMC Programmable Clock Output 0 */
+#define AT91_PA2_SPCK           (1 <<  2)       /* A: SPI Serial Clock */
+#define AT91_PA2_IRQ4           (1 <<  2)       /* B: External Interrupt 4 */
+#define AT91_PA3_NPCS0          (1 <<  3)       /* A: SPI Peripheral Chip Select 0 */
+#define AT91_PA3_IRQ5           (1 <<  3)       /* B: External Interrupt 5 */
+#define AT91_PA4_NPCS1          (1 <<  4)       /* A: SPI Peripheral Chip Select 1 */
+#define AT91_PA4_PCK1           (1 <<  4)       /* B: PMC Programmable Clock Output 1 */
+#define AT91_PA5_NPCS2          (1 <<  5)       /* A: SPI Peripheral Chip Select 2 */
+#define AT91_PA5_TXD3           (1 <<  5)       /* B: USART Transmit Data 3 */
+#define AT91_PA6_NPCS3          (1 <<  6)       /* A: SPI Peripheral Chip Select 3 */
+#define AT91_PA6_RXD3           (1 <<  6)       /* B: USART Receive Data 3 */
+#define AT91_PA7_ETXCK_EREFCK   (1 <<  7)       /* A: Ethernet Reference Clock / Transmit Clock */
+#define AT91_PA7_PCK2           (1 <<  7)       /* B: PMC Programmable Clock Output 2 */
+#define AT91_PA8_ETXEN          (1 <<  8)       /* A: Ethernet Transmit Enable */
+#define AT91_PA8_MCCDB          (1 <<  8)       /* B: MMC Multimedia Card B Command */
+#define AT91_PA9_ETX0           (1 <<  9)       /* A: Ethernet Transmit Data 0 */
+#define AT91_PA9_MCDB0          (1 <<  9)       /* B: MMC Multimedia Card B Data 0 */
+#define AT91_PA10_ETX1          (1 << 10)       /* A: Ethernet Transmit Data 1 */
+#define AT91_PA10_MCDB1         (1 << 10)       /* B: MMC Multimedia Card B Data 1 */
+#define AT91_PA11_ECRS_ECRSDV   (1 << 11)       /* A: Ethernet Carrier Sense / Data Valid */
+#define AT91_PA11_MCDB2         (1 << 11)       /* B: MMC Multimedia Card B Data 2 */
+#define AT91_PA12_ERX0          (1 << 12)       /* A: Ethernet Receive Data 0 */
+#define AT91_PA12_MCDB3         (1 << 12)       /* B: MMC Multimedia Card B Data 3 */
+#define AT91_PA13_ERX1          (1 << 13)       /* A: Ethernet Receive Data 1 */
+#define AT91_PA13_TCLK0         (1 << 13)       /* B: TC External Clock Input 0 */
+#define AT91_PA14_ERXER         (1 << 14)       /* A: Ethernet Receive Error */
+#define AT91_PA14_TCLK1         (1 << 14)       /* B: TC External Clock Input 1 */
+#define AT91_PA15_EMDC          (1 << 15)       /* A: Ethernet Management Data Clock */
+#define AT91_PA15_TCLK2         (1 << 15)       /* B: TC External Clock Input 2 */
+#define AT91_PA16_EMDIO         (1 << 16)       /* A: Ethernet Management Data I/O */
+#define AT91_PA16_IRQ6          (1 << 16)       /* B: External Interrupt 6 */
+#define AT91_PA17_TXD0          (1 << 17)       /* A: USART Transmit Data 0 */
+#define AT91_PA17_TIOA0         (1 << 17)       /* B: TC I/O Line A 0 */
+#define AT91_PA18_RXD0          (1 << 18)       /* A: USART Receive Data 0 */
+#define AT91_PA18_TIOB0         (1 << 18)       /* B: TC I/O Line B 0 */
+#define AT91_PA19_SCK0          (1 << 19)       /* A: USART Serial Clock 0 */
+#define AT91_PA19_TIOA1         (1 << 19)       /* B: TC I/O Line A 1 */
+#define AT91_PA20_CTS0          (1 << 20)       /* A: USART Clear To Send 0 */
+#define AT91_PA20_TIOB1         (1 << 20)       /* B: TC I/O Line B 1 */
+#define AT91_PA21_RTS0          (1 << 21)       /* A: USART Ready To Send 0 */
+#define AT91_PA21_TIOA2         (1 << 21)       /* B: TC I/O Line A 2 */
+#define AT91_PA22_RXD2          (1 << 22)       /* A: USART Receive Data 2 */
+#define AT91_PA22_TIOB2         (1 << 22)       /* B: TC I/O Line B 2 */
+#define AT91_PA23_TXD2          (1 << 23)       /* A: USART Transmit Data 2 */
+#define AT91_PA23_IRQ3          (1 << 23)       /* B: External Interrupt 3 */
+#define AT91_PA24_SCK2          (1 << 24)       /* A: USART Serial Clock 2 */
+#define AT91_PA24_PCK1          (1 << 24)       /* B: PMC Programmable Clock Output 1 */
+#define AT91_PA25_TWD           (1 << 25)       /* A: TWI Two-wire Serial Data */
+#define AT91_PA25_IRQ2          (1 << 25)       /* B: External Interrupt 2 */
+#define AT91_PA26_TWCK          (1 << 26)       /* A: TWI Two-wire Serial Clock */
+#define AT91_PA26_IRQ1          (1 << 26)       /* B: External Interrupt 1 */
+#define AT91_PA27_MCCK          (1 << 27)       /* A: MMC Multimedia Card Clock */
+#define AT91_PA27_TCLK3         (1 << 27)       /* B: TC External Clock Input 3 */
+#define AT91_PA28_MCCDA         (1 << 28)       /* A: MMC Multimedia Card A Command */
+#define AT91_PA28_TCLK4         (1 << 28)       /* B: TC External Clock Input 4 */
+#define AT91_PA29_MCDA0         (1 << 29)       /* A: MMC Multimedia Card A Data 0 */
+#define AT91_PA29_TCLK5         (1 << 29)       /* B: TC External Clock Input 5 */
+#define AT91_PA30_DRXD          (1 << 30)       /* A: DBGU Receive Data */
+#define AT91_PA30_CTS2          (1 << 30)       /* B: USART Clear To Send 2 */
+#define AT91_PA31_DTXD          (1 << 31)       /* A: DBGU Transmit Data */
+#define AT91_PA31_RTS2          (1 << 31)       /* B: USART Ready To Send 2 */
+#define AT91_PB0_TF0            (1 <<  0)       /* A: SSC Transmit Frame Sync 0 */
+#define AT91_PB0_RTS3           (1 <<  0)       /* B: USART Ready To Send 3 */
+#define AT91_PB1_TK0            (1 <<  1)       /* A: SSC Transmit Clock 0 */
+#define AT91_PB1_CTS3           (1 <<  1)       /* B: USART Clear To Send 3 */
+#define AT91_PB2_TD0            (1 <<  2)       /* A: SSC Transmit Data 0 */
+#define AT91_PB2_SCK3           (1 <<  2)       /* B: USART Serial Clock 3 */
+#define AT91_PB3_RD0            (1 <<  3)       /* A: SSC Receive Data 0 */
+#define AT91_PB3_MCDA1          (1 <<  3)       /* B: MMC Multimedia Card A Data 1 */
+#define AT91_PB4_RK0            (1 <<  4)       /* A: SSC Receive Clock 0 */
+#define AT91_PB4_MCDA2          (1 <<  4)       /* B: MMC Multimedia Card A Data 2 */
+#define AT91_PB5_RF0            (1 <<  5)       /* A: SSC Receive Frame Sync 0 */
+#define AT91_PB5_MCDA3          (1 <<  5)       /* B: MMC Multimedia Card A Data 3 */
+#define AT91_PB6_TF1            (1 <<  6)       /* A: SSC Transmit Frame Sync 1 */
+#define AT91_PB6_TIOA3          (1 <<  6)       /* B: TC I/O Line A 3 */
+#define AT91_PB7_TK1            (1 <<  7)       /* A: SSC Transmit Clock 1 */
+#define AT91_PB7_TIOB3          (1 <<  7)       /* B: TC I/O Line B 3 */
+#define AT91_PB8_TD1            (1 <<  8)       /* A: SSC Transmit Data 1 */
+#define AT91_PB8_TIOA4          (1 <<  8)       /* B: TC I/O Line A 4 */
+#define AT91_PB9_RD1            (1 <<  9)       /* A: SSC Receive Data 1 */
+#define AT91_PB9_TIOB4          (1 <<  9)       /* B: TC I/O Line B 4 */
+#define AT91_PB10_RK1           (1 << 10)       /* A: SSC Receive Clock 1 */
+#define AT91_PB10_TIOA5         (1 << 10)       /* B: TC I/O Line A 5 */
+#define AT91_PB11_RF1           (1 << 11)       /* A: SSC Receive Frame Sync 1 */
+#define AT91_PB11_TIOB5         (1 << 11)       /* B: TC I/O Line B 5 */
+#define AT91_PB12_TF2           (1 << 12)       /* A: SSC Transmit Frame Sync 2 */
+#define AT91_PB12_ETX2          (1 << 12)       /* B: Ethernet Transmit Data 2 */
+#define AT91_PB13_TK2           (1 << 13)       /* A: SSC Transmit Clock 3 */
+#define AT91_PB13_ETX3          (1 << 13)       /* B: Ethernet Transmit Data 3 */
+#define AT91_PB14_TD2           (1 << 14)       /* A: SSC Transmit Data 2 */
+#define AT91_PB14_ETXER         (1 << 14)       /* B: Ethernet Transmit Coding Error */
+#define AT91_PB15_RD2           (1 << 15)       /* A: SSC Receive Data 2 */
+#define AT91_PB15_ERX2          (1 << 15)       /* B: Ethernet Receive Data 2 */
+#define AT91_PB16_RK2           (1 << 16)       /* A: SSC Receive Clock 2 */
+#define AT91_PB16_ERX3          (1 << 16)       /* B: Ethernet Receive Data 3 */
+#define AT91_PB17_RF2           (1 << 17)       /* A: SSC Receive Frame Sync 2 */
+#define AT91_PB17_ERXDV         (1 << 17)       /* B: Ethernet Receive Data Valid */
+#define AT91_PB18_RI1           (1 << 18)       /* A: USART Ring Indicator 1 */
+#define AT91_PB18_ECOL          (1 << 18)       /* B: Ethernet Collision Detected */
+#define AT91_PB19_DTR1          (1 << 19)       /* A: USART Data Terminal Ready 1 */
+#define AT91_PB19_ERXCK         (1 << 19)       /* B: Ethernet Receive Clock */
+#define AT91_PB20_TXD1          (1 << 20)       /* A: USART Transmit Data 1 */
+#define AT91_PB21_RXD1          (1 << 21)       /* A: USART Receive Data 1 */
+#define AT91_PB22_SCK1          (1 << 22)       /* A: USART Serial Clock 1 */
+#define AT91_PB23_DCD1          (1 << 23)       /* A: USART Data Carrier Detect 1 */
+#define AT91_PB24_CTS1          (1 << 24)       /* A: USART Clear To Send 1 */
+#define AT91_PB25_DSR1          (1 << 25)       /* A: USART Data Set Ready 1 */
+#define AT91_PB25_EF100         (1 << 25)       /* B: Ethernet Force 100 Mbit */
+#define AT91_PB26_RTS1          (1 << 26)       /* A: USART Ready To Send 1 */
+#define AT91_PB27_PCK0          (1 << 27)       /* B: PMC Programmable Clock Output 0 */
+#define AT91_PB28_FIQ           (1 << 28)       /* A: Fast Interrupt */
+#define AT91_PB29_IRQ0          (1 << 29)       /* A: External Interrupt 0 */
+#define AT91_PC0_BFCK           (1 <<  0)       /* A: Burst Flash Clock */
+#define AT91_PC1_BFRDY_SMOE     (1 <<  1)       /* A: Burst Flash Ready / SmartMedia Output Enable */
+#define AT91_PC2_BFAVD          (1 <<  2)       /* A: Burst Flash Address Valid */
+#define AT91_PC3_BFBAA_SMWE     (1 <<  3)       /* A: Burst Flash Address Advance / SmartMedia Write Enable */
+#define AT91_PC4_BFOE           (1 <<  4)       /* A: Burst Flash Output Enable */
+#define AT91_PC5_BFWE           (1 <<  5)       /* A: Burst Flash Write Enable */
+#define AT91_PC6_NWAIT          (1 <<  6)       /* A: SMC Wait Signal */
+#define AT91_PC7_A23            (1 <<  7)       /* A: Address Bus 23 */
+#define AT91_PC8_A24            (1 <<  8)       /* A: Address Bus 24 */
+#define AT91_PC9_A25_CFRNW      (1 <<  9)       /* A: Address Bus 25 / Compact Flash Read Not Write */
+#define AT91_PC10_NCS4_CFCS     (1 << 10)       /* A: SMC Chip Select 4 / Compact Flash Chip Select */
+#define AT91_PC11_NCS5_CFCE1    (1 << 11)       /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
+#define AT91_PC12_NCS6_CFCE2    (1 << 12)       /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
+#define AT91_PC13_NCS7          (1 << 13)       /* A: Chip Select 7 */
+#define AT91_PD0_ETX0           (1 <<  0)       /* A: Ethernet Transmit Data 0 */
+#define AT91_PD1_ETX1           (1 <<  1)       /* A: Ethernet Transmit Data 1 */
+#define AT91_PD2_ETX2           (1 <<  2)       /* A: Ethernet Transmit Data 2 */
+#define AT91_PD3_ETX3           (1 <<  3)       /* A: Ethernet Transmit Data 3 */
+#define AT91_PD4_ETXEN          (1 <<  4)       /* A: Ethernet Transmit Enable */
+#define AT91_PD5_ETXER          (1 <<  5)       /* A: Ethernet Transmit Coding Error */
+#define AT91_PD6_DTXD           (1 <<  6)       /* A: DBGU Transmit Data */
+#define AT91_PD7_PCK0           (1 <<  7)       /* A: PMC Programmable Clock Output 0 */
+#define AT91_PD7_TSYNC          (1 <<  7)       /* B: ETM Trace Synchronization Signal */
+#define AT91_PD8_PCK1           (1 <<  8)       /* A: PMC Programmable Clock Output 1 */
+#define AT91_PD8_TCLK           (1 <<  8)       /* B: ETM Trace Clock */
+#define AT91_PD9_PCK2           (1 <<  9)       /* A: PMC Programmable Clock Output 2 */
+#define AT91_PD9_TPS0           (1 <<  9)       /* B: ETM Trace ARM Pipeline Status 0 */
+#define AT91_PD10_PCK3          (1 << 10)       /* A: PMC Programmable Clock Output 3 */
+#define AT91_PD10_TPS1          (1 << 10)       /* B: ETM Trace ARM Pipeline Status 1 */
+#define AT91_PD11_TPS2          (1 << 11)       /* B: ETM Trace ARM Pipeline Status 2 */
+#define AT91_PD12_TPK0          (1 << 12)       /* B: ETM Trace Packet Port 0 */
+#define AT91_PD13_TPK1          (1 << 13)       /* B: ETM Trace Packet Port 1 */
+#define AT91_PD14_TPK2          (1 << 14)       /* B: ETM Trace Packet Port 2 */
+#define AT91_PD15_TD0           (1 << 15)       /* A: SSC Transmit Data 0 */
+#define AT91_PD15_TPK3          (1 << 15)       /* B: ETM Trace Packet Port 3 */
+#define AT91_PD16_TD1           (1 << 16)       /* A: SSC Transmit Data 1 */
+#define AT91_PD16_TPK4          (1 << 16)       /* B: ETM Trace Packet Port 4 */
+#define AT91_PD17_TD2           (1 << 17)       /* A: SSC Transmit Data 2 */
+#define AT91_PD17_TPK5          (1 << 17)       /* B: ETM Trace Packet Port 5 */
+#define AT91_PD18_NPCS1         (1 << 18)       /* A: SPI Peripheral Chip Select 1 */
+#define AT91_PD18_TPK6          (1 << 18)       /* B: ETM Trace Packet Port 6 */
+#define AT91_PD19_NPCS2         (1 << 19)       /* A: SPI Peripheral Chip Select 2 */
+#define AT91_PD19_TPK7          (1 << 19)       /* B: ETM Trace Packet Port 7 */
+#define AT91_PD20_NPCS3         (1 << 20)       /* A: SPI Peripheral Chip Select 3 */
+#define AT91_PD20_TPK8          (1 << 20)       /* B: ETM Trace Packet Port 8 */
+#define AT91_PD21_RTS0          (1 << 21)       /* A: USART Ready To Send 0 */
+#define AT91_PD21_TPK9          (1 << 21)       /* B: ETM Trace Packet Port 9 */
+#define AT91_PD22_RTS1          (1 << 22)       /* A: USART Ready To Send 1 */
+#define AT91_PD22_TPK10         (1 << 22)       /* B: ETM Trace Packet Port 10 */
+#define AT91_PD23_RTS2          (1 << 23)       /* A: USART Ready To Send 2 */
+#define AT91_PD23_TPK11         (1 << 23)       /* B: ETM Trace Packet Port 11 */
+#define AT91_PD24_RTS3          (1 << 24)       /* A: USART Ready To Send 3 */
+#define AT91_PD24_TPK12         (1 << 24)       /* B: ETM Trace Packet Port 12 */
+#define AT91_PD25_DTR1          (1 << 25)       /* A: USART Data Terminal Ready 1 */
+#define AT91_PD25_TPK13         (1 << 25)       /* B: ETM Trace Packet Port 13 */
+#define AT91_PD26_TPK14         (1 << 26)       /* B: ETM Trace Packet Port 14 */
+#define AT91_PD27_TPK15         (1 << 27)       /* B: ETM Trace Packet Port 15 */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
new file mode 100644
index 000000000000..9bfffdbf1e0b
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -0,0 +1,328 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_SYS_H
+#define AT91RM9200_SYS_H
+/*
+ * Advanced Interrupt Controller.
+ */
+#define AT91_AIC        0x000
+#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
+#define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
+#define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
+#define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
+#define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
+#define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
+#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
+#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
+#define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
+#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
+#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
+#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
+#define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
+#define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
+#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
+#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
+#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
+#define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
+#define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
+/*
+ * Debug Unit.
+ */
+#define AT91_DBGU       0x200
+#define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
+#define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
+#define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
+#define         AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
+#define         AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
+#define AT91_DBGU_IDR           (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
+#define AT91_DBGU_IMR           (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
+#define AT91_DBGU_SR            (AT91_DBGU + 0x14)      /* Status Register */
+#define AT91_DBGU_RHR           (AT91_DBGU + 0x18)      /* Receiver Holding Register */
+#define AT91_DBGU_THR           (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
+#define AT91_DBGU_BRGR          (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
+#define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
+#define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
+/*
+ * PIO Controllers.
+ */
+#define AT91_PIOA       0x400
+#define AT91_PIOB       0x600
+#define AT91_PIOC       0x800
+#define AT91_PIOD       0xa00
+#define PIO_PER         0x00    /* Enable Register */
+#define PIO_PDR         0x04    /* Disable Register */
+#define PIO_PSR         0x08    /* Status Register */
+#define PIO_OER         0x10    /* Output Enable Register */
+#define PIO_ODR         0x14    /* Output Disable Register */
+#define PIO_OSR         0x18    /* Output Status Register */
+#define PIO_IFER        0x20    /* Glitch Input Filter Enable */
+#define PIO_IFDR        0x24    /* Glitch Input Filter Disable */
+#define PIO_IFSR        0x28    /* Glitch Input Filter Status */
+#define PIO_SODR        0x30    /* Set Output Data Register */
+#define PIO_CODR        0x34    /* Clear Output Data Register */
+#define PIO_ODSR        0x38    /* Output Data Status Register */
+#define PIO_PDSR        0x3c    /* Pin Data Status Register */
+#define PIO_IER         0x40    /* Interrupt Enable Register */
+#define PIO_IDR         0x44    /* Interrupt Disable Register */
+#define PIO_IMR         0x48    /* Interrupt Mask Register */
+#define PIO_ISR         0x4c    /* Interrupt Status Register */
+#define PIO_MDER        0x50    /* Multi-driver Enable Register */
+#define PIO_MDDR        0x54    /* Multi-driver Disable Register */
+#define PIO_MDSR        0x58    /* Multi-driver Status Register */
+#define PIO_PUDR        0x60    /* Pull-up Disable Register */
+#define PIO_PUER        0x64    /* Pull-up Enable Register */
+#define PIO_PUSR        0x68    /* Pull-up Status Register */
+#define PIO_ASR         0x70    /* Peripheral A Select Register */
+#define PIO_BSR         0x74    /* Peripheral B Select Register */
+#define PIO_ABSR        0x78    /* AB Status Register */
+#define PIO_OWER        0xa0    /* Output Write Enable Register */
+#define PIO_OWDR        0xa4    /* Output Write Disable Register */
+#define PIO_OWSR        0xa8    /* Output Write Status Register */
+#define AT91_PIO_P(n)   (1 << (n))
+/*
+ * Power Management Controller.
+ */
+#define AT91_PMC        0xc00
+#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
+#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
+#define         AT91_PMC_UDP            (1 <<  1)               /* USB Devcice Port Clock */
+#define         AT91_PMC_MCKUDP         (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend */
+#define         AT91_PMC_UHP            (1 <<  4)               /* USB Host Port Clock */
+#define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
+#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
+#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
+#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
+#define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
+#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
+#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
+#define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
+#define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
+#define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
+#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
+#define                 AT91_PMC_CSS_SLOW               (0 << 0)
+#define                 AT91_PMC_CSS_MAIN               (1 << 0)
+#define                 AT91_PMC_CSS_PLLA               (2 << 0)
+#define                 AT91_PMC_CSS_PLLB               (3 << 0)
+#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
+#define                 AT91_PMC_PRES_1                 (0 << 2)
+#define                 AT91_PMC_PRES_2                 (1 << 2)
+#define                 AT91_PMC_PRES_4                 (2 << 2)
+#define                 AT91_PMC_PRES_8                 (3 << 2)
+#define                 AT91_PMC_PRES_16                (4 << 2)
+#define                 AT91_PMC_PRES_32                (5 << 2)
+#define                 AT91_PMC_PRES_64                (6 << 2)
+#define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
+#define                 AT91_PMC_MDIV_1                 (0 << 8)
+#define                 AT91_PMC_MDIV_2                 (1 << 8)
+#define                 AT91_PMC_MDIV_3                 (2 << 8)
+#define                 AT91_PMC_MDIV_4                 (3 << 8)
+#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
+#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
+#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
+#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
+#define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
+#define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
+#define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
+#define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
+#define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
+#define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
+#define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
+#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+/*
+ * System Timer.
+ */
+#define AT91_ST         0xd00
+#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
+#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
+#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
+#define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
+#define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
+#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
+#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
+#define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
+#define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
+#define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
+#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
+#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
+#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
+#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
+/*
+ * Real-time Clock.
+ */
+#define AT91_RTC        0xe00
+#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
+#define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
+#define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
+#define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
+#define                 AT91_RTC_TIMEVSEL_MINUTE        (0 << 8)
+#define                 AT91_RTC_TIMEVSEL_HOUR          (1 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY24         (2 << 8)
+#define                 AT91_RTC_TIMEVSEL_DAY12         (3 << 8)
+#define         AT91_RTC_CALEVSEL       (3 << 16)               /* Calendar Event Selection */
+#define                 AT91_RTC_CALEVSEL_WEEK          (0 << 16)
+#define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
+#define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
+#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
+#define         AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
+#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
+#define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
+#define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
+#define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
+#define         At91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
+#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
+#define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
+#define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
+#define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
+#define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
+#define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
+#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
+#define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
+#define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
+#define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
+#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
+#define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
+#define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
+#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
+#define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
+#define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
+#define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
+#define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
+#define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
+#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
+#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
+#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
+#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
+#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
+#define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
+#define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
+#define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
+#define         AT91_RTC_NVCALALR       (1 <<  3)               /* Non valid Calendar Alarm */
+/*
+ * Memory Controller.
+ */
+#define AT91_MC         0xf00
+#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
+#define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
+#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
+#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
+#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
+/* External Bus Interface (EBI) registers */
+#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
+#define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
+#define                 AT91_EBI_CS0A_SMC               (0 << 0)
+#define                 AT91_EBI_CS0A_BFC               (1 << 0)
+#define         AT91_EBI_CS1A           (1 << 1)                /* Chip Select 1 Assignment */
+#define                 AT91_EBI_CS1A_SMC               (0 << 1)
+#define                 AT91_EBI_CS1A_SDRAMC            (1 << 1)
+#define         AT91_EBI_CS3A           (1 << 3)                /* Chip Select 2 Assignment */
+#define                 AT91_EBI_CS3A_SMC               (0 << 3)
+#define                 AT91_EBI_CS3A_SMC_SMARTMEDIA    (1 << 3)
+#define         AT91_EBI_CS4A           (1 << 4)                /* Chip Select 3 Assignment */
+#define                 AT91_EBI_CS4A_SMC               (0 << 4)
+#define                 AT91_EBI_CS4A_SMC_COMPACTFLASH  (1 << 4)
+#define AT91_EBI_CFGR           (AT91_MC + 0x64)        /* Configuration Register */
+#define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
+/* Static Memory Controller (SMC) registers */
+#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
+#define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
+#define         AT91_SMC_TDF            (0xf  <<  8)            /* Data Float Time */
+#define         AT91_SMC_BAT            (1    << 12)            /* Byte Access Type */
+#define         AT91_SMC_DBW            (3    << 13)            /* Data Bus Width */
+#define                 AT91_SMC_DBW_16         (1 << 13)
+#define                 AT91_SMC_DBW_8          (2 << 13)
+#define         AT91_SMC_DPR            (1 << 15)               /* Data Read Protocol */
+#define         AT91_SMC_ACSS           (3 << 16)               /* Address to Chip Select Setup */
+#define                 AT91_SMC_ACSS_STD       (0 << 16)
+#define                 AT91_SMC_ACSS_1         (1 << 16)
+#define                 AT91_SMC_ACSS_2         (2 << 16)
+#define                 AT91_SMC_ACSS_3         (3 << 16)
+#define         AT91_SMC_RWSETUP        (7 << 24)               /* Read & Write Signal Time Setup */
+#define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
new file mode 100644
index 000000000000..2e7d1139a799
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -0,0 +1,80 @@
+/*
+ * include/asm-arm/arch-at91rm9200/board.h
+ *
+ *  Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/*
+ * These are data structures found in platform_device.dev.platform_data,
+ * and describing board-specfic data needed by drivers.  For example,
+ * which pin is used for a given GPIO role.
+ *
+ * In 2.6, drivers should strongly avoid board-specific knowledge so
+ * that supporting new boards normally won't require driver patches.
+ * Most board-specific knowledge should be in arch/.../board-*.c files.
+ */
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+ /* Clocks */
+extern unsigned long at91_master_clock;
+ /* Serial Port */
+extern int at91_serial_map[AT91_NR_UART];
+extern int at91_console_port;
+ /* USB Device */
+struct at91_udc_data {
+        u8      vbus_pin;               /* high == host powering us */
+        u8      pullup_pin;             /* high == D+ pulled up */
+};
+extern void __init at91_add_device_udc(struct at91_udc_data *data);
+ /* Compact Flash */
+struct at91_cf_data {
+        u8      irq_pin;                /* I/O IRQ */
+        u8      det_pin;                /* Card detect */
+        u8      vcc_pin;                /* power switching */
+        u8      rst_pin;                /* card reset */
+};
+extern void __init at91_add_device_cf(struct at91_cf_data *data);
+ /* MMC / SD */
+struct at91_mmc_data {
+        u8              det_pin;        /* card detect IRQ */
+        unsigned        is_b:1;         /* uses B side (vs A) */
+        unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
+        u8              wp_pin;         /* (SD) writeprotect detect */
+        u8              vcc_pin;        /* power switching (high == on) */
+};
+extern void __init at91_add_device_mmc(struct at91_mmc_data *data);
+ /* Ethernet */
+struct at91_eth_data {
+        u8              phy_irq_pin;    /* PHY IRQ */
+        u8              is_rmii;        /* using RMII interface? */
+};
+extern void __init at91_add_device_eth(struct at91_eth_data *data);
+ /* USB Host */
+struct at91_usbh_data {
+        u8              ports;          /* number of ports on root hub */
+};
+extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/debug-macro.S b/include/asm-arm/arch-at91rm9200/debug-macro.S
new file mode 100644
index 000000000000..f496b54c4c3e
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/debug-macro.S
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-at91rm9200/debug-macro.S
+ *
+ *  Copyright (C) 2003-2005 SAN People
+ *
+ * Debugging macro include header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <asm/hardware.h>
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                         @ MMU enabled?
+        ldreq   \rx, =AT91_BASE_SYS             @ System peripherals (phys address)
+        ldrne   \rx, =AT91_VA_BASE_SYS          @ System peripherals (virt address)
+        .endm
+        .macro  senduart,rd,rx
+        strb    \rd, [\rx, #AT91_DBGU_THR]      @ Write to Transmitter Holding Register
+        .endm
+        .macro  waituart,rd,rx
+1001:   ldr     \rd, [\rx, #AT91_DBGU_SR]       @ Read Status Register
+        tst     \rd, #AT91_DBGU_TXRDY           @ DBGU_TXRDY = 1 when ready to transmit
+        beq     1001b
+        .endm
+        .macro  busyuart,rd,rx
+1001:   ldr     \rd, [\rx, #AT91_DBGU_SR]       @ Read Status Register
+        tst     \rd, #AT91_DBGU_TXEMPTY         @ DBGU_TXEMPTY = 1 when transmission complete
+        beq     1001b
+        .endm
diff --git a/include/asm-arm/arch-epxa10db/param.h b/include/asm-arm/arch-at91rm9200/dma.h
index 783dedd71c8f..22c1dfdd8da3 100644
--- a/include/asm-arm/arch-epxa10db/param.h
+++ b/include/asm-arm/arch-at91rm9200/dma.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10db/param.h
+ * include/asm-arm/arch-at91rm9200/dma.h
 *
- *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2003 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S
new file mode 100644
index 000000000000..61a326e94909
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/entry-macro.S
@@ -0,0 +1,25 @@
+/*
+ * include/asm-arm/arch-at91rm9200/entry-macro.S
+ *
+ *  Copyright (C) 2003-2005 SAN People
+ *
+ * Low-level IRQ helper macros for AT91RM9200 platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware.h>
+        .macro  disable_fiq
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \base, =(AT91_VA_BASE_SYS)              @ base virtual address of SYS peripherals
+        ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
+        ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
+        teq     \irqstat, #0                            @ ISR is 0 when no current interrupt, or spurious interrupt
+        streq   \tmp, [\base, #AT91_AIC_EOICR]          @ not going to be handled further, then ACK it now.
+        .endm
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
new file mode 100644
index 000000000000..0f0a61e2f129
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -0,0 +1,193 @@
+/*
+ * include/asm-arm/arch-at91rm9200/gpio.h
+ *
+ *  Copyright (C) 2005 HP Labs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
+#define __ASM_ARCH_AT91RM9200_GPIO_H
+#define PIN_BASE                NR_AIC_IRQS
+#define PQFP_GPIO_BANKS         3       /* PQFP package has 3 banks */
+#define BGA_GPIO_BANKS          4       /* BGA package has 4 banks */
+/* these pin numbers double as IRQ numbers, like AT91_ID_* values */
+#define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
+#define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
+#define AT91_PIN_PA2    (PIN_BASE + 0x00 + 2)
+#define AT91_PIN_PA3    (PIN_BASE + 0x00 + 3)
+#define AT91_PIN_PA4    (PIN_BASE + 0x00 + 4)
+#define AT91_PIN_PA5    (PIN_BASE + 0x00 + 5)
+#define AT91_PIN_PA6    (PIN_BASE + 0x00 + 6)
+#define AT91_PIN_PA7    (PIN_BASE + 0x00 + 7)
+#define AT91_PIN_PA8    (PIN_BASE + 0x00 + 8)
+#define AT91_PIN_PA9    (PIN_BASE + 0x00 + 9)
+#define AT91_PIN_PA10   (PIN_BASE + 0x00 + 10)
+#define AT91_PIN_PA11   (PIN_BASE + 0x00 + 11)
+#define AT91_PIN_PA12   (PIN_BASE + 0x00 + 12)
+#define AT91_PIN_PA13   (PIN_BASE + 0x00 + 13)
+#define AT91_PIN_PA14   (PIN_BASE + 0x00 + 14)
+#define AT91_PIN_PA15   (PIN_BASE + 0x00 + 15)
+#define AT91_PIN_PA16   (PIN_BASE + 0x00 + 16)
+#define AT91_PIN_PA17   (PIN_BASE + 0x00 + 17)
+#define AT91_PIN_PA18   (PIN_BASE + 0x00 + 18)
+#define AT91_PIN_PA19   (PIN_BASE + 0x00 + 19)
+#define AT91_PIN_PA20   (PIN_BASE + 0x00 + 20)
+#define AT91_PIN_PA21   (PIN_BASE + 0x00 + 21)
+#define AT91_PIN_PA22   (PIN_BASE + 0x00 + 22)
+#define AT91_PIN_PA23   (PIN_BASE + 0x00 + 23)
+#define AT91_PIN_PA24   (PIN_BASE + 0x00 + 24)
+#define AT91_PIN_PA25   (PIN_BASE + 0x00 + 25)
+#define AT91_PIN_PA26   (PIN_BASE + 0x00 + 26)
+#define AT91_PIN_PA27   (PIN_BASE + 0x00 + 27)
+#define AT91_PIN_PA28   (PIN_BASE + 0x00 + 28)
+#define AT91_PIN_PA29   (PIN_BASE + 0x00 + 29)
+#define AT91_PIN_PA30   (PIN_BASE + 0x00 + 30)
+#define AT91_PIN_PA31   (PIN_BASE + 0x00 + 31)
+#define AT91_PIN_PB0    (PIN_BASE + 0x20 + 0)
+#define AT91_PIN_PB1    (PIN_BASE + 0x20 + 1)
+#define AT91_PIN_PB2    (PIN_BASE + 0x20 + 2)
+#define AT91_PIN_PB3    (PIN_BASE + 0x20 + 3)
+#define AT91_PIN_PB4    (PIN_BASE + 0x20 + 4)
+#define AT91_PIN_PB5    (PIN_BASE + 0x20 + 5)
+#define AT91_PIN_PB6    (PIN_BASE + 0x20 + 6)
+#define AT91_PIN_PB7    (PIN_BASE + 0x20 + 7)
+#define AT91_PIN_PB8    (PIN_BASE + 0x20 + 8)
+#define AT91_PIN_PB9    (PIN_BASE + 0x20 + 9)
+#define AT91_PIN_PB10   (PIN_BASE + 0x20 + 10)
+#define AT91_PIN_PB11   (PIN_BASE + 0x20 + 11)
+#define AT91_PIN_PB12   (PIN_BASE + 0x20 + 12)
+#define AT91_PIN_PB13   (PIN_BASE + 0x20 + 13)
+#define AT91_PIN_PB14   (PIN_BASE + 0x20 + 14)
+#define AT91_PIN_PB15   (PIN_BASE + 0x20 + 15)
+#define AT91_PIN_PB16   (PIN_BASE + 0x20 + 16)
+#define AT91_PIN_PB17   (PIN_BASE + 0x20 + 17)
+#define AT91_PIN_PB18   (PIN_BASE + 0x20 + 18)
+#define AT91_PIN_PB19   (PIN_BASE + 0x20 + 19)
+#define AT91_PIN_PB20   (PIN_BASE + 0x20 + 20)
+#define AT91_PIN_PB21   (PIN_BASE + 0x20 + 21)
+#define AT91_PIN_PB22   (PIN_BASE + 0x20 + 22)
+#define AT91_PIN_PB23   (PIN_BASE + 0x20 + 23)
+#define AT91_PIN_PB24   (PIN_BASE + 0x20 + 24)
+#define AT91_PIN_PB25   (PIN_BASE + 0x20 + 25)
+#define AT91_PIN_PB26   (PIN_BASE + 0x20 + 26)
+#define AT91_PIN_PB27   (PIN_BASE + 0x20 + 27)
+#define AT91_PIN_PB28   (PIN_BASE + 0x20 + 28)
+#define AT91_PIN_PB29   (PIN_BASE + 0x20 + 29)
+#define AT91_PIN_PB30   (PIN_BASE + 0x20 + 30)
+#define AT91_PIN_PB31   (PIN_BASE + 0x20 + 31)
+#define AT91_PIN_PC0    (PIN_BASE + 0x40 + 0)
+#define AT91_PIN_PC1    (PIN_BASE + 0x40 + 1)
+#define AT91_PIN_PC2    (PIN_BASE + 0x40 + 2)
+#define AT91_PIN_PC3    (PIN_BASE + 0x40 + 3)
+#define AT91_PIN_PC4    (PIN_BASE + 0x40 + 4)
+#define AT91_PIN_PC5    (PIN_BASE + 0x40 + 5)
+#define AT91_PIN_PC6    (PIN_BASE + 0x40 + 6)
+#define AT91_PIN_PC7    (PIN_BASE + 0x40 + 7)
+#define AT91_PIN_PC8    (PIN_BASE + 0x40 + 8)
+#define AT91_PIN_PC9    (PIN_BASE + 0x40 + 9)
+#define AT91_PIN_PC10   (PIN_BASE + 0x40 + 10)
+#define AT91_PIN_PC11   (PIN_BASE + 0x40 + 11)
+#define AT91_PIN_PC12   (PIN_BASE + 0x40 + 12)
+#define AT91_PIN_PC13   (PIN_BASE + 0x40 + 13)
+#define AT91_PIN_PC14   (PIN_BASE + 0x40 + 14)
+#define AT91_PIN_PC15   (PIN_BASE + 0x40 + 15)
+#define AT91_PIN_PC16   (PIN_BASE + 0x40 + 16)
+#define AT91_PIN_PC17   (PIN_BASE + 0x40 + 17)
+#define AT91_PIN_PC18   (PIN_BASE + 0x40 + 18)
+#define AT91_PIN_PC19   (PIN_BASE + 0x40 + 19)
+#define AT91_PIN_PC20   (PIN_BASE + 0x40 + 20)
+#define AT91_PIN_PC21   (PIN_BASE + 0x40 + 21)
+#define AT91_PIN_PC22   (PIN_BASE + 0x40 + 22)
+#define AT91_PIN_PC23   (PIN_BASE + 0x40 + 23)
+#define AT91_PIN_PC24   (PIN_BASE + 0x40 + 24)
+#define AT91_PIN_PC25   (PIN_BASE + 0x40 + 25)
+#define AT91_PIN_PC26   (PIN_BASE + 0x40 + 26)
+#define AT91_PIN_PC27   (PIN_BASE + 0x40 + 27)
+#define AT91_PIN_PC28   (PIN_BASE + 0x40 + 28)
+#define AT91_PIN_PC29   (PIN_BASE + 0x40 + 29)
+#define AT91_PIN_PC30   (PIN_BASE + 0x40 + 30)
+#define AT91_PIN_PC31   (PIN_BASE + 0x40 + 31)
+#define AT91_PIN_PD0    (PIN_BASE + 0x60 + 0)
+#define AT91_PIN_PD1    (PIN_BASE + 0x60 + 1)
+#define AT91_PIN_PD2    (PIN_BASE + 0x60 + 2)
+#define AT91_PIN_PD3    (PIN_BASE + 0x60 + 3)
+#define AT91_PIN_PD4    (PIN_BASE + 0x60 + 4)
+#define AT91_PIN_PD5    (PIN_BASE + 0x60 + 5)
+#define AT91_PIN_PD6    (PIN_BASE + 0x60 + 6)
+#define AT91_PIN_PD7    (PIN_BASE + 0x60 + 7)
+#define AT91_PIN_PD8    (PIN_BASE + 0x60 + 8)
+#define AT91_PIN_PD9    (PIN_BASE + 0x60 + 9)
+#define AT91_PIN_PD10   (PIN_BASE + 0x60 + 10)
+#define AT91_PIN_PD11   (PIN_BASE + 0x60 + 11)
+#define AT91_PIN_PD12   (PIN_BASE + 0x60 + 12)
+#define AT91_PIN_PD13   (PIN_BASE + 0x60 + 13)
+#define AT91_PIN_PD14   (PIN_BASE + 0x60 + 14)
+#define AT91_PIN_PD15   (PIN_BASE + 0x60 + 15)
+#define AT91_PIN_PD16   (PIN_BASE + 0x60 + 16)
+#define AT91_PIN_PD17   (PIN_BASE + 0x60 + 17)
+#define AT91_PIN_PD18   (PIN_BASE + 0x60 + 18)
+#define AT91_PIN_PD19   (PIN_BASE + 0x60 + 19)
+#define AT91_PIN_PD20   (PIN_BASE + 0x60 + 20)
+#define AT91_PIN_PD21   (PIN_BASE + 0x60 + 21)
+#define AT91_PIN_PD22   (PIN_BASE + 0x60 + 22)
+#define AT91_PIN_PD23   (PIN_BASE + 0x60 + 23)
+#define AT91_PIN_PD24   (PIN_BASE + 0x60 + 24)
+#define AT91_PIN_PD25   (PIN_BASE + 0x60 + 25)
+#define AT91_PIN_PD26   (PIN_BASE + 0x60 + 26)
+#define AT91_PIN_PD27   (PIN_BASE + 0x60 + 27)
+#define AT91_PIN_PD28   (PIN_BASE + 0x60 + 28)
+#define AT91_PIN_PD29   (PIN_BASE + 0x60 + 29)
+#define AT91_PIN_PD30   (PIN_BASE + 0x60 + 30)
+#define AT91_PIN_PD31   (PIN_BASE + 0x60 + 31)
+#ifndef __ASSEMBLY__
+/* setup setup routines, called from board init or driver probe() */
+extern int at91_set_A_periph(unsigned pin, int use_pullup);
+extern int at91_set_B_periph(unsigned pin, int use_pullup);
+extern int at91_set_gpio_input(unsigned pin, int use_pullup);
+extern int at91_set_gpio_output(unsigned pin, int value);
+extern int at91_set_deglitch(unsigned pin, int is_on);
+/* callable at any time */
+extern int at91_set_gpio_value(unsigned pin, int value);
+extern int at91_get_gpio_value(unsigned pin);
+#endif
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
new file mode 100644
index 000000000000..2646c01f8e97
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -0,0 +1,92 @@
+/*
+ * include/asm-arm/arch-at91rm9200/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *  Copyright (C) 2003 ATMEL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/sizes.h>
+#include <asm/arch/at91rm9200.h>
+#include <asm/arch/at91rm9200_sys.h>
+/*
+ * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
+ * to 0xFEFA0000 .. 0xFF000000.  (384Kb)
+ */
+#define AT91_IO_PHYS_BASE       0xFFFA0000
+#define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
+#define AT91_IO_VIRT_BASE       (0xFF000000 - AT91_IO_SIZE)
+ /* Convert a physical IO address to virtual IO address */
+#define AT91_IO_P2V(x)  ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
+/*
+ * Virtual to Physical Address mapping for IO devices.
+ */
+#define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
+#define AT91_VA_BASE_SPI        AT91_IO_P2V(AT91_BASE_SPI)
+#define AT91_VA_BASE_SSC2       AT91_IO_P2V(AT91_BASE_SSC2)
+#define AT91_VA_BASE_SSC1       AT91_IO_P2V(AT91_BASE_SSC1)
+#define AT91_VA_BASE_SSC0       AT91_IO_P2V(AT91_BASE_SSC0)
+#define AT91_VA_BASE_US3        AT91_IO_P2V(AT91_BASE_US3)
+#define AT91_VA_BASE_US2        AT91_IO_P2V(AT91_BASE_US2)
+#define AT91_VA_BASE_US1        AT91_IO_P2V(AT91_BASE_US1)
+#define AT91_VA_BASE_US0        AT91_IO_P2V(AT91_BASE_US0)
+#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91_BASE_EMAC)
+#define AT91_VA_BASE_TWI        AT91_IO_P2V(AT91_BASE_TWI)
+#define AT91_VA_BASE_MCI        AT91_IO_P2V(AT91_BASE_MCI)
+#define AT91_VA_BASE_UDP        AT91_IO_P2V(AT91_BASE_UDP)
+#define AT91_VA_BASE_TCB1       AT91_IO_P2V(AT91_BASE_TCB1)
+#define AT91_VA_BASE_TCB0       AT91_IO_P2V(AT91_BASE_TCB0)
+/* Internal SRAM */
+#define AT91_BASE_SRAM          0x00200000      /* Internal SRAM base address */
+#define AT91_SRAM_SIZE          0x00004000      /* Internal SRAM SIZE (16Kb) */
+/* Serial ports */
+#define AT91_NR_UART            5               /* 4 USART3's and one DBGU port */
+/* FLASH */
+#define AT91_FLASH_BASE         0x10000000      /* NCS0: Flash physical base address */
+/* SDRAM */
+#define AT91_SDRAM_BASE         0x20000000      /* NCS1: SDRAM physical base address */
+/* SmartMedia */
+#define AT91_SMARTMEDIA_BASE    0x40000000      /* NCS3: Smartmedia physical base address */
+/* Multi-Master Memory controller */
+#define AT91_UHP_BASE           0x00300000      /* USB Host controller */
+/* Clocks */
+#define AT91_SLOW_CLOCK         32768           /* slow clock */
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+static inline unsigned int at91_sys_read(unsigned int reg_offset)
+{
+        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
+        return readl(addr + reg_offset);
+}
+static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
+{
+        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
+        writel(value, addr + reg_offset);
+}
+#endif
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/io.h b/include/asm-arm/arch-at91rm9200/io.h
new file mode 100644
index 000000000000..23e670d85c9d
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/io.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-at91rm9200/io.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+#include <asm/arch/at91rm9200.h>
+#include <asm/io.h>
+#define IO_SPACE_LIMIT          0xFFFFFFFF
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
new file mode 100644
index 000000000000..27b0497f1b36
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -0,0 +1,52 @@
+/*
+ * include/asm-arm/arch-at91rm9200/irqs.h
+ *
+ *  Copyright (C) 2004 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+#define NR_AIC_IRQS 32
+/*
+ * Acknowledge interrupt with AIC after interrupt has been handled.
+ *   (by kernel/irq.c)
+ */
+#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
+/*
+ * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h
+ * for IRQs handled directly through the AIC, or else the AT91_PIN_*
+ * symbols in gpio.h for ones handled indirectly as GPIOs.
+ * We make provision for 4 banks of GPIO.
+ */
+#include <asm/arch/gpio.h>
+#define NR_IRQS         (NR_AIC_IRQS + (4 * 32))
+#ifndef __ASSEMBLY__
+/*
+ * Initialize the IRQ controller.
+ */
+extern void at91rm9200_init_irq(unsigned int priority[]);
+#endif
+#endif
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-at91rm9200/memory.h
index 999541b6a9f5..462f1f0ad67c 100644
--- a/include/asm-arm/arch-epxa10db/memory.h
+++ b/include/asm-arm/arch-at91rm9200/memory.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10/memory.h
+ * include/asm-arm/arch-at91rm9200/memory.h
 *
- *  Copyright (C) 2001 Altera Corporation
+ *  Copyright (C) 2004 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -17,13 +17,14 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-/*
+#include <asm/arch/hardware.h>
- * Physical DRAM offset.
- */
+#define PHYS_OFFSET     (AT91_SDRAM_BASE)
-#define PHYS_OFFSET     UL(0x00000000)
 /*
 * Virtual view <-> DMA view memory address translations
@@ -32,7 +33,9 @@
 * bus_to_virt: Used to convert an address for DMA operations
 *              to an address that the kernel can use.
 */
-#define __virt_to_bus(x)        (x - PAGE_OFFSET + /*SDRAM_BASE*/0)
+#define __virt_to_bus__is_a_macro
-#define __bus_to_virt(x)        (x - /*SDRAM_BASE*/0 + PAGE_OFFSET)
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) __phys_to_virt(x)
 #endif
diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-at91rm9200/param.h
index 546fb7d2b6ad..9480f8446852 100644
--- a/include/asm-arm/arch-epxa10db/vmalloc.h
+++ b/include/asm-arm/arch-at91rm9200/param.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10db/vmalloc.h
+ * include/asm-arm/arch-at91rm9200/param.h
 *
- *  Copyright (C) 2000 Russell King.
+ *  Copyright (C) 2003 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -17,4 +17,12 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+/*
+ * We use default params
+ */
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/pio.h b/include/asm-arm/arch-at91rm9200/pio.h
new file mode 100644
index 000000000000..a89501b4a703
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/pio.h
@@ -0,0 +1,115 @@
+/*
+ * include/asm-arm/arch-at91rm9200/pio.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ASM_ARCH_PIO_H
+#define __ASM_ARCH_PIO_H
+#include <asm/arch/hardware.h>
+static inline void AT91_CfgPIO_USART0(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA17_TXD0 | AT91_PA18_RXD0 | AT91_PA20_CTS0);
+        /*
+         * Errata #39 - RTS0 is not internally connected to PA21.  We need to drive
+         *  the pin manually.  Default is off (RTS is active low).
+         */
+        at91_sys_write(AT91_PIOA + PIO_PER, AT91_PA21_RTS0);
+        at91_sys_write(AT91_PIOA + PIO_OER, AT91_PA21_RTS0);
+        at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
+}
+static inline void AT91_CfgPIO_USART1(void) {
+        at91_sys_write(AT91_PIOB + PIO_PDR, AT91_PB18_RI1 | AT91_PB19_DTR1
+                        | AT91_PB20_TXD1 | AT91_PB21_RXD1 | AT91_PB23_DCD1
+                        | AT91_PB24_CTS1 | AT91_PB25_DSR1 | AT91_PB26_RTS1);
+}
+static inline void AT91_CfgPIO_USART2(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA22_RXD2 | AT91_PA23_TXD2);
+}
+static inline void AT91_CfgPIO_USART3(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
+        at91_sys_write(AT91_PIOA + PIO_BSR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
+}
+static inline void AT91_CfgPIO_DBGU(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA31_DTXD | AT91_PA30_DRXD);
+}
+/*
+ * Enable the Two-Wire interface.
+ */
+static inline void AT91_CfgPIO_TWI(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA25_TWD | AT91_PA26_TWCK);
+        at91_sys_write(AT91_PIOA + PIO_ASR, AT91_PA25_TWD | AT91_PA26_TWCK);
+        at91_sys_write(AT91_PIOA + PIO_MDER, AT91_PA25_TWD | AT91_PA26_TWCK);           /* open drain */
+}
+/*
+ * Enable the Serial Peripheral Interface.
+ */
+static inline void AT91_CfgPIO_SPI(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA0_MISO | AT91_PA1_MOSI | AT91_PA2_SPCK);
+}
+static inline void AT91_CfgPIO_SPI_CS0(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA3_NPCS0);
+}
+static inline void AT91_CfgPIO_SPI_CS1(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA4_NPCS1);
+}
+static inline void AT91_CfgPIO_SPI_CS2(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_NPCS2);
+}
+static inline void AT91_CfgPIO_SPI_CS3(void) {
+        at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA6_NPCS3);
+}
+/*
+ * Select the DataFlash card.
+ */
+static inline void AT91_CfgPIO_DataFlashCard(void) {
+        at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(7));
+        at91_sys_write(AT91_PIOB + PIO_OER, AT91_PIO_P(7));
+        at91_sys_write(AT91_PIOB + PIO_CODR, AT91_PIO_P(7));
+}
+/*
+ * Enable NAND Flash (SmartMedia) interface.
+ */
+static inline void AT91_CfgPIO_SmartMedia(void) {
+        /* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */
+        at91_sys_write(AT91_PIOC + PIO_ASR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
+        at91_sys_write(AT91_PIOC + PIO_PDR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
+        /* Configure PC2 as input (signal READY of the SmartMedia) */
+        at91_sys_write(AT91_PIOC + PIO_PER, AT91_PC2_BFAVD);    /* enable direct output enable */
+        at91_sys_write(AT91_PIOC + PIO_ODR, AT91_PC2_BFAVD);    /* disable output */
+        /* Configure PB1 as input (signal Card Detect of the SmartMedia) */
+        at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(1));     /* enable direct output enable */
+        at91_sys_write(AT91_PIOB + PIO_ODR, AT91_PIO_P(1));     /* disable output */
+}
+static inline int AT91_PIO_SmartMedia_RDY(void) {
+        return (at91_sys_read(AT91_PIOC + PIO_PDSR) & AT91_PIO_P(2)) ? 1 : 0;
+}
+static inline int AT91_PIO_SmartMedia_CardDetect(void) {
+        return (at91_sys_read(AT91_PIOB + PIO_PDSR) & AT91_PIO_P(1)) ? 1 : 0;
+}
+#endif
diff --git a/include/asm-arm/arch-epxa10db/system.h b/include/asm-arm/arch-at91rm9200/system.h
index 345b092a1ed5..29c42655f05c 100644
--- a/include/asm-arm/arch-epxa10db/system.h
+++ b/include/asm-arm/arch-at91rm9200/system.h
@@ -1,9 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10db/system.h
+ * include/asm-arm/arch-at91rm9200/system.h
 *
- *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2003 SAN People
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2001 Altera Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -19,23 +17,35 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <asm/arch/platform.h>
+#include <asm/arch/hardware.h>
 static inline void arch_idle(void)
 {
        /*
-         * This should do all the clock switching
+         * Disable the processor clock.  The processor will be automatically
-         * and wait for interrupt tricks
+         * re-enabled by an interrupt or by a reset.
+         */
+//      at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+        /*
+         * Set the processor (CP15) into 'Wait for Interrupt' mode.
+         * Unlike disabling the processor clock via the PMC (above)
+         *  this allows the processor to be woken via JTAG.
         */
        cpu_do_idle();
 }
-extern __inline__ void arch_reset(char mode)
+static inline void arch_reset(char mode)
 {
-        /* Hmm... We can probably do something with the watchdog... */
+        /*
+         * Perform a hardware reset with the use of the Watchdog timer.
+         */
+        at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 #endif
diff --git a/include/asm-arm/arch-epxa10db/dma.h b/include/asm-arm/arch-at91rm9200/timex.h
index de20ec8e74b1..3f112dd12587 100644
--- a/include/asm-arm/arch-epxa10db/dma.h
+++ b/include/asm-arm/arch-at91rm9200/timex.h
@@ -1,7 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-camelot/dma.h
+ * include/asm-arm/arch-at91rm9200/timex.h
 *
- *  Copyright (C) 1997,1998 Russell King
+ *  Copyright (C) 2003 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -17,3 +17,12 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+#include <asm/arch/hardware.h>
+#define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
new file mode 100644
index 000000000000..b30dd5520713
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -0,0 +1,55 @@
+/*
+ * include/asm-arm/arch-at91rm9200/uncompress.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+#include <asm/arch/hardware.h>
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        void __iomem *sys = (void __iomem *) AT91_BASE_SYS;     /* physical address */
+        while (*s) {
+                while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
+                __raw_writel(*s, sys + AT91_DBGU_THR);
+                if (*s == '\n') {
+                        while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
+                        __raw_writel('\r', sys + AT91_DBGU_THR);
+                }
+                s++;
+        }
+        /* wait for transmission to complete */
+        while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) { barrier(); }
+}
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+#endif
diff --git a/include/asm-arm/arch-epxa10db/timex.h b/include/asm-arm/arch-at91rm9200/vmalloc.h
index b87a75fc9589..34d9718feb90 100644
--- a/include/asm-arm/arch-epxa10db/timex.h
+++ b/include/asm-arm/arch-at91rm9200/vmalloc.h
@@ -1,9 +1,7 @@
 /*
- *  linux/include/asm-arm/arch-epxa10db/timex.h
+ * include/asm-arm/arch-at91rm9200/vmalloc.h
 *
- *  Excalibur timex specifications
+ *  Copyright (C) 2003 SAN People
- *
- *  Copyright (C) 2001 Altera Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -20,7 +18,9 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-/*
+#ifndef __ASM_ARCH_VMALLOC_H
- * ??
+#define __ASM_ARCH_VMALLOC_H
- */
-#define CLOCK_TICK_RATE         (50000000 / 16)
+#define VMALLOC_END             (AT91_IO_VIRT_BASE & PGDIR_MASK)
+#endif
diff --git a/include/asm-arm/arch-epxa10db/debug-macro.S b/include/asm-arm/arch-epxa10db/debug-macro.S
deleted file mode 100644
index 1d11c51f498f..000000000000
--- a/include/asm-arm/arch-epxa10db/debug-macro.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/* linux/include/asm-arm/arch-epxa10db/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-#include <asm/arch/excalibur.h>
-#define UART00_TYPE
-#include <asm/arch/uart00.h>
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                ldr     \rx, =EXC_UART00_BASE   @ physical base address
-                orrne   \rx, \rx, #0xff000000   @ virtual base
-                orrne   \rx, \rx, #0x00f00000
-                .endm
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #UART_TD(0)]
-                .endm
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #UART_TSR(0)]
-                and     \rd, \rd,  #UART_TSR_TX_LEVEL_MSK
-                cmp     \rd, #15
-                beq     1001b
-                .endm
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #UART_TSR(0)]
-                ands    \rd, \rd,  #UART_TSR_TX_LEVEL_MSK
-                bne     1001b
-                .endm
diff --git a/include/asm-arm/arch-epxa10db/entry-macro.S b/include/asm-arm/arch-epxa10db/entry-macro.S
deleted file mode 100644
index de6ae08334e2..000000000000
--- a/include/asm-arm/arch-epxa10db/entry-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * include/asm-arm/arch-epxa10db/entry-macro.S
- *
- * Low-level IRQ helper macros for epxa10db platform
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/arch/platform.h>
-#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
-#include <asm/arch/int_ctrl00.h>
-                .macro  disable_fiq
-                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
-                ldr     \irqnr,[\irqstat]
-                cmp     \irqnr,#0
-                subne   \irqnr,\irqnr,#1
-                .endm
diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h
deleted file mode 100644
index b737b8aabe2f..000000000000
--- a/include/asm-arm/arch-epxa10db/ether00.h
+++ /dev/null
@@ -1,482 +0,0 @@
-#ifndef __ETHER00_H
-#define __ETHER00_H
-/*
- * Register definitions for the Ethernet MAC
- */
-/*
- * Copyright (c) Altera Corporation 2000.
- * All rights reserved.
- */
-/*
-*       Structures for the DMA controller
-*/
-typedef struct fda_desc
-        {
-        struct fda_desc *       FDNext;
-        long                            FDSystem;
-        long                            FDStat;
-        short                           FDLength;
-        short                           FDCtl;
-        }FDA_DESC;
-typedef struct buf_desc
-        {
-        char *  BuffData;
-        short   BuffLength;
-        char    BDStat;
-        char    BDCtl;
-        }BUF_DESC;
-/*
-*       Control masks for the DMA controller
-*/
-#define FDCTL_BDCOUNT_MSK                                               (0x1F)
-#define FDCTL_BDCOUNT_OFST                                              (0)
-#define FDCTL_FRMOPT_MSK                                                (0x7C00)
-#define FDCTL_FRMOPT_OFST                                               (10)
-#define FDCTL_COWNSFD_MSK                                               (0x8000)
-#define FDCTL_COWNSFD_OFST                                              (15)
-#define BDCTL_RXBDSEQN_MSK                                              (0x7F)
-#define BDCTL_RXBDSEQN_OFST                                             (0)
-#define BDCTL_COWNSBD_MSK                                               (0x80)
-#define BDCTL_COWNSBD_OFST                                              (7)
-#define FDNEXT_EOL_MSK                                                  (0x1)
-#define FDNEXT_EOL_OFST                                                 (0)
-#define FDNEXT_EOL_POINTER_MSK                                  (0xFFFFFFF0)
-#define FDNEXT_EOL_POINTER_OFST                                 (4)
-#define ETHER_ARC_SIZE         (21)
-/*
-*       Register definitions and masks
-*/
-#define ETHER_DMA_CTL(base)                                                     (ETHER00_TYPE (base + 0x100))
-#define ETHER_DMA_CTL_DMBURST_OFST                              (2)
-#define ETHER_DMA_CTL_DMBURST_MSK                               (0x1FC)
-#define ETHER_DMA_CTL_POWRMGMNT_OFST                    (11)
-#define ETHER_DMA_CTL_POWRMGMNT_MSK                             (0x1000)
-#define ETHER_DMA_CTL_TXBIGE_OFST                               (14)
-#define ETHER_DMA_CTL_TXBIGE_MSK                                (0x4000)
-#define ETHER_DMA_CTL_RXBIGE_OFST                               (15)
-#define ETHER_DMA_CTL_RXBIGE_MSK                                (0x8000)
-#define ETHER_DMA_CTL_TXWAKEUP_OFST                             (16)
-#define ETHER_DMA_CTL_TXWAKEUP_MSK                              (0x10000)
-#define ETHER_DMA_CTL_SWINTREQ_OFST                             (17)
-#define ETHER_DMA_CTL_SWINTREQ_MSK                              (0x20000)
-#define ETHER_DMA_CTL_INTMASK_OFST                              (18)
-#define ETHER_DMA_CTL_INTMASK_MSK                               (0x40000)
-#define ETHER_DMA_CTL_M66ENSTAT_OFST                    (19)
-#define ETHER_DMA_CTL_M66ENSTAT_MSK                             (0x80000)
-#define ETHER_DMA_CTL_RMTXINIT_OFST                             (20)
-#define ETHER_DMA_CTL_RMTXINIT_MSK                              (0x100000)
-#define ETHER_DMA_CTL_RMRXINIT_OFST                             (21)
-#define ETHER_DMA_CTL_RMRXINIT_MSK                              (0x200000)
-#define ETHER_DMA_CTL_RXALIGN_OFST                              (22)
-#define ETHER_DMA_CTL_RXALIGN_MSK                               (0xC00000)
-#define ETHER_DMA_CTL_RMSWRQ_OFST                               (24)
-#define ETHER_DMA_CTL_RMSWRQ_MSK                                (0x1000000)
-#define ETHER_DMA_CTL_RMEMBANK_OFST                             (25)
-#define ETHER_DMA_CTL_RMEMBANK_MSK                              (0x2000000)
-#define ETHER_TXFRMPTR(base)                                                    (ETHER00_TYPE (base + 0x104))
-#define ETHER_TXTHRSH(base)                                                     (ETHER00_TYPE (base + 0x308))
-#define ETHER_TXPOLLCTR(base)                                                   (ETHER00_TYPE (base + 0x30c))
-#define ETHER_BLFRMPTR(base)                                                    (ETHER00_TYPE (base + 0x110))
-#define ETHER_BLFFRMPTR_EOL_OFST                                (0)
-#define ETHER_BLFFRMPTR_EOL_MSK                                 (0x1)
-#define ETHER_BLFFRMPTR_ADDRESS_OFST                    (4)
-#define ETHER_BLFFRMPTR_ADDRESS_MSK                             (0xFFFFFFF0)
-#define ETHER_RXFRAGSIZE(base)                                          (ETHER00_TYPE (base + 0x114))
-#define ETHER_RXFRAGSIZE_MINFRAG_OFST                   (2)
-#define ETHER_RXFRAGSIZE_MINFRAG_MSK                    (0xFFC)
-#define ETHER_RXFRAGSIZE_ENPACK_OFST                    (15)
-#define ETHER_RXFRAGSIZE_ENPACK_MSK                             (0x8000)
-#define ETHER_INT_EN(base)                                                      (ETHER00_TYPE (base + 0x118))
-#define ETHER_INT_EN_FDAEXEN_OFST                               (0)
-#define ETHER_INT_EN_FDAEXEN_MSK                                (0x1)
-#define ETHER_INT_EN_BLEXEN_OFST                                (1)
-#define ETHER_INT_EN_BLEXN_MSK                                  (0x2)
-#define ETHER_INT_EN_STARGABTEN_OFST                    (2)
-#define ETHER_INT_EN_STARGABTEN_MSK                             (0x4)
-#define ETHER_INT_EN_RTARGABTEN_OFST                    (3)
-#define ETHER_INT_EN_RTARGABTEN_MSK                             (0x8)
-#define ETHER_INT_EN_RMASABTEN_OFST                             (4)
-#define ETHER_INT_EN_RMASABTEN_MSK                              (0x10)
-#define ETHER_INT_EN_SSYSERREN_OFST                             (5)
-#define ETHER_INT_EN_SSYSERREN_MSK                              (0x20)
-#define ETHER_INT_EN_DPARERREN_OFST                             (6)
-#define ETHER_INT_EN_DPARERREN_MSK                              (0x40)
-#define ETHER_INT_EN_EARNOTEN_OFST                              (7)
-#define ETHER_INT_EN_EARNOTEN_MSK                               (0x80)
-#define ETHER_INT_EN_DPARDEN_OFST                               (8)
-#define ETHER_INT_EN_DPARDEN_MSK                                (0x100)
-#define ETHER_INT_EN_DMPARERREN_OFST                    (9)
-#define ETHER_INT_EN_DMPARERREN_MSK                             (0x200)
-#define ETHER_INT_EN_TXCTLCMPEN_OFST                    (10)
-#define ETHER_INT_EN_TXCTLCMPEN_MSK                             (0x400)
-#define ETHER_INT_EN_NRABTEN_OFST                               (11)
-#define ETHER_INT_EN_NRABTEN_MSK                                (0x800)
-#define ETHER_FDA_BAS(base)                                                     (ETHER00_TYPE (base + 0x11C))
-#define ETHER_FDA_BAS_ADDRESS_OFST                              (4)
-#define ETHER_FDA_BAS_ADDRESS_MSK                               (0xFFFFFFF0)
-#define ETHER_FDA_LIM(base)                                                     (ETHER00_TYPE (base + 0x120))
-#define ETHER_FDA_LIM_COUNT_OFST                                (4)
-#define ETHER_FDA_LIM_COUNT_MSK                                 (0xFFF0)
-#define ETHER_INT_SRC(base)                                                     (ETHER00_TYPE (base + 0x124))
-#define ETHER_INT_SRC_INTMACTX_OFST                             (0)
-#define ETHER_INT_SRC_INTMACTX_MSK                              (0x1)
-#define ETHER_INT_SRC_INTMACRX_OFST                             (1)
-#define ETHER_INT_SRC_INTMACRX_MSK                              (0x2)
-#define ETHER_INT_SRC_INTSBUS_OFST                              (2)
-#define ETHER_INT_SRC_INTSBUS_MSK                               (0x4)
-#define ETHER_INT_SRC_INTFDAEX_OFST                             (3)
-#define ETHER_INT_SRC_INTFDAEX_MSK                              (0x8)
-#define ETHER_INT_SRC_INTBLEX_OFST                              (4)
-#define ETHER_INT_SRC_INTBLEX_MSK                               (0x10)
-#define ETHER_INT_SRC_SWINT_OFST                                (5)
-#define ETHER_INT_SRC_SWINT_MSK                                 (0x20)
-#define ETHER_INT_SRC_INTEARNOT_OFST                    (6)
-#define ETHER_INT_SRC_INTEARNOT_MSK                             (0x40)
-#define ETHER_INT_SRC_DMPARERR_OFST                             (7)
-#define ETHER_INT_SRC_DMPARERR_MSK                              (0x80)
-#define ETHER_INT_SRC_INTEXBD_OFST                              (8)
-#define ETHER_INT_SRC_INTEXBD_MSK                               (0x100)
-#define ETHER_INT_SRC_INTTXCTLCMP_OFST                  (9)
-#define ETHER_INT_SRC_INTTXCTLCMP_MSK                   (0x200)
-#define ETHER_INT_SRC_INTNRABT_OFST                             (10)
-#define ETHER_INT_SRC_INTNRABT_MSK                              (0x400)
-#define ETHER_INT_SRC_FDAEX_OFST                                (11)
-#define ETHER_INT_SRC_FDAEX_MSK                                 (0x800)
-#define ETHER_INT_SRC_BLEX_OFST                                 (12)
-#define ETHER_INT_SRC_BLEX_MSK                                  (0x1000)
-#define ETHER_INT_SRC_DMPARERRSTAT_OFST                 (13)
-#define ETHER_INT_SRC_DMPARERRSTAT_MSK                  (0x2000)
-#define ETHER_INT_SRC_NRABT_OFST                                (14)
-#define ETHER_INT_SRC_NRABT_MSK                                 (0x4000)
-#define ETHER_INT_SRC_INTLINK_OFST                              (15)
-#define ETHER_INT_SRC_INTLINK_MSK                               (0x8000)
-#define ETHER_INT_SRC_INTEXDEFER_OFST                   (16)
-#define ETHER_INT_SRC_INTEXDEFER_MSK                    (0x10000)
-#define ETHER_INT_SRC_INTRMON_OFST                              (17)
-#define ETHER_INT_SRC_INTRMON_MSK                               (0x20000)
-#define ETHER_INT_SRC_IRQ_MSK                                   (0x83FF)
-#define ETHER_PAUSECNT(base)                                                    (ETHER00_TYPE (base + 0x40))
-#define ETHER_PAUSECNT_COUNT_OFST                               (0)
-#define ETHER_PAUSECNT_COUNT_MSK                                (0xFFFF)
-#define ETHER_REMPAUCNT(base)                                                   (ETHER00_TYPE (base + 0x44))
-#define ETHER_REMPAUCNT_COUNT_OFST                              (0)
-#define ETHER_REMPAUCNT_COUNT_MSK                               (0xFFFF)
-#define ETHER_TXCONFRMSTAT(base)                                                (ETHER00_TYPE (base + 0x348))
-#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST   (0)
-#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK    (0x3FFFFF)
-#define ETHER_MAC_CTL(base)                                                     (ETHER00_TYPE (base + 0))
-#define ETHER_MAC_CTL_HALTREQ_OFST                              (0)
-#define ETHER_MAC_CTL_HALTREQ_MSK                               (0x1)
-#define ETHER_MAC_CTL_HALTIMM_OFST                              (1)
-#define ETHER_MAC_CTL_HALTIMM_MSK                               (0x2)
-#define ETHER_MAC_CTL_RESET_OFST                                (2)
-#define ETHER_MAC_CTL_RESET_MSK                                 (0x4)
-#define ETHER_MAC_CTL_FULLDUP_OFST                              (3)
-#define ETHER_MAC_CTL_FULLDUP_MSK                               (0x8)
-#define ETHER_MAC_CTL_MACLOOP_OFST                              (4)
-#define ETHER_MAC_CTL_MACLOOP_MSK                               (0x10)
-#define ETHER_MAC_CTL_CONN_OFST                                 (5)
-#define ETHER_MAC_CTL_CONN_MSK                                  (0x60)
-#define ETHER_MAC_CTL_LOOP10_OFST                               (7)
-#define ETHER_MAC_CTL_LOOP10_MSK                                (0x80)
-#define ETHER_MAC_CTL_LNKCHG_OFST                               (8)
-#define ETHER_MAC_CTL_LNKCHG_MSK                                (0x100)
-#define ETHER_MAC_CTL_MISSROLL_OFST                             (10)
-#define ETHER_MAC_CTL_MISSROLL_MSK                              (0x400)
-#define ETHER_MAC_CTL_ENMISSROLL_OFST                   (13)
-#define ETHER_MAC_CTL_ENMISSROLL_MSK                    (0x2000)
-#define ETHER_MAC_CTL_LINK10_OFST                               (15)
-#define ETHER_MAC_CTL_LINK10_MSK                                (0x8000)
-#define ETHER_ARC_CTL(base)                                                     (ETHER00_TYPE (base + 0x4))
-#define ETHER_ARC_CTL_STATIONACC_OFST                   (0)
-#define ETHER_ARC_CTL_STATIONACC_MSK                    (0x1)
-#define ETHER_ARC_CTL_GROUPACC_OFST                             (1)
-#define ETHER_ARC_CTL_GROUPACC_MSK                              (0x2)
-#define ETHER_ARC_CTL_BROADACC_OFST                             (2)
-#define ETHER_ARC_CTL_BROADACC_MSK                              (0x4)
-#define ETHER_ARC_CTL_NEGARC_OFST                               (3)
-#define ETHER_ARC_CTL_NEGARC_MSK                                (0x8)
-#define ETHER_ARC_CTL_COMPEN_OFST                               (4)
-#define ETHER_ARC_CTL_COMPEN_MSK                                (0x10)
-#define ETHER_TX_CTL(base)                                                      (ETHER00_TYPE (base + 0x8))
-#define ETHER_TX_CTL_TXEN_OFST                                  (0)
-#define ETHER_TX_CTL_TXEN_MSK                                   (0x1)
-#define ETHER_TX_CTL_TXHALT_OFST                                (1)
-#define ETHER_TX_CTL_TXHALT_MSK                                 (0x2)
-#define ETHER_TX_CTL_NOPAD_OFST                                 (2)
-#define ETHER_TX_CTL_NOPAD_MSK                                  (0x4)
-#define ETHER_TX_CTL_NOCRC_OFST                                 (3)
-#define ETHER_TX_CTL_NOCRC_MSK                                  (0x8)
-#define ETHER_TX_CTL_FBACK_OFST                                 (4)
-#define ETHER_TX_CTL_FBACK_MSK                                  (0x10)
-#define ETHER_TX_CTL_NOEXDEF_OFST                               (5)
-#define ETHER_TX_CTL_NOEXDEF_MSK                                (0x20)
-#define ETHER_TX_CTL_SDPAUSE_OFST                               (6)
-#define ETHER_TX_CTL_SDPAUSE_MSK                                (0x40)
-#define ETHER_TX_CTL_MII10_OFST                                 (7)
-#define ETHER_TX_CTL_MII10_MSK                                  (0x80)
-#define ETHER_TX_CTL_ENUNDER_OFST                               (8)
-#define ETHER_TX_CTL_ENUNDER_MSK                                (0x100)
-#define ETHER_TX_CTL_ENEXDEFER_OFST                             (9)
-#define ETHER_TX_CTL_ENEXDEFER_MSK                              (0x200)
-#define ETHER_TX_CTL_ENLCARR_OFST                               (10)
-#define ETHER_TX_CTL_ENLCARR_MSK                                (0x400)
-#define ETHER_TX_CTL_ENEXCOLL_OFST                              (11)
-#define ETHER_TX_CTL_ENEXCOLL_MSK                               (0x800)
-#define ETHER_TX_CTL_ENLATECOLL_OFST                            (12)
-#define ETHER_TX_CTL_ENLATECOLL_MSK                             (0x1000)
-#define ETHER_TX_CTL_ENTXPAR_OFST                               (13)
-#define ETHER_TX_CTL_ENTXPAR_MSK                                (0x2000)
-#define ETHER_TX_CTL_ENCOMP_OFST                                (14)
-#define ETHER_TX_CTL_ENCOMP_MSK                                 (0x4000)
-#define ETHER_TX_STAT(base)                                                     (ETHER00_TYPE (base + 0xc))
-#define ETHER_TX_STAT_TXCOLL_OFST                               (0)
-#define ETHER_TX_STAT_TXCOLL_MSK                                (0xF)
-#define ETHER_TX_STAT_EXCOLL_OFST                               (4)
-#define ETHER_TX_STAT_EXCOLL_MSK                                (0x10)
-#define ETHER_TX_STAT_TXDEFER_OFST                              (5)
-#define ETHER_TX_STAT_TXDEFER_MSK                               (0x20)
-#define ETHER_TX_STAT_PAUSED_OFST                               (6)
-#define ETHER_TX_STAT_PAUSED_MSK                                (0x40)
-#define ETHER_TX_STAT_INTTX_OFST                                (7)
-#define ETHER_TX_STAT_INTTX_MSK                                 (0x80)
-#define ETHER_TX_STAT_UNDER_OFST                                (8)
-#define ETHER_TX_STAT_UNDER_MSK                                 (0x100)
-#define ETHER_TX_STAT_EXDEFER_OFST                              (9)
-#define ETHER_TX_STAT_EXDEFER_MSK                               (0x200)
-#define ETHER_TX_STAT_LCARR_OFST                                (10)
-#define ETHER_TX_STAT_LCARR_MSK                                 (0x400)
-#define ETHER_TX_STAT_TX10STAT_OFST                             (11)
-#define ETHER_TX_STAT_TX10STAT_MSK                              (0x800)
-#define ETHER_TX_STAT_LATECOLL_OFST                             (12)
-#define ETHER_TX_STAT_LATECOLL_MSK                              (0x1000)
-#define ETHER_TX_STAT_TXPAR_OFST                                (13)
-#define ETHER_TX_STAT_TXPAR_MSK                                 (0x2000)
-#define ETHER_TX_STAT_COMP_OFST                                 (14)
-#define ETHER_TX_STAT_COMP_MSK                                  (0x4000)
-#define ETHER_TX_STAT_TXHALTED_OFST                             (15)
-#define ETHER_TX_STAT_TXHALTED_MSK                              (0x8000)
-#define ETHER_TX_STAT_SQERR_OFST                                (16)
-#define ETHER_TX_STAT_SQERR_MSK                                 (0x10000)
-#define ETHER_TX_STAT_TXMCAST_OFST                              (17)
-#define ETHER_TX_STAT_TXMCAST_MSK                               (0x20000)
-#define ETHER_TX_STAT_TXBCAST_OFST                              (18)
-#define ETHER_TX_STAT_TXBCAST_MSK                               (0x40000)
-#define ETHER_TX_STAT_VLAN_OFST                                 (19)
-#define ETHER_TX_STAT_VLAN_MSK                                  (0x80000)
-#define ETHER_TX_STAT_MACC_OFST                                 (20)
-#define ETHER_TX_STAT_MACC_MSK                                  (0x100000)
-#define ETHER_TX_STAT_TXPAUSE_OFST                              (21)
-#define ETHER_TX_STAT_TXPAUSE_MSK                               (0x200000)
-#define ETHER_RX_CTL(base)                                                      (ETHER00_TYPE (base + 0x10))
-#define ETHER_RX_CTL_RXEN_OFST                                  (0)
-#define ETHER_RX_CTL_RXEN_MSK                                   (0x1)
-#define ETHER_RX_CTL_RXHALT_OFST                                (1)
-#define ETHER_RX_CTL_RXHALT_MSK                                 (0x2)
-#define ETHER_RX_CTL_LONGEN_OFST                                (2)
-#define ETHER_RX_CTL_LONGEN_MSK                                 (0x4)
-#define ETHER_RX_CTL_SHORTEN_OFST                               (3)
-#define ETHER_RX_CTL_SHORTEN_MSK                                (0x8)
-#define ETHER_RX_CTL_STRIPCRC_OFST                              (4)
-#define ETHER_RX_CTL_STRIPCRC_MSK                               (0x10)
-#define ETHER_RX_CTL_PASSCTL_OFST                               (5)
-#define ETHER_RX_CTL_PASSCTL_MSK                                (0x20)
-#define ETHER_RX_CTL_IGNORECRC_OFST                             (6)
-#define ETHER_RX_CTL_IGNORECRC_MSK                              (0x40)
-#define ETHER_RX_CTL_ENALIGN_OFST                               (8)
-#define ETHER_RX_CTL_ENALIGN_MSK                                (0x100)
-#define ETHER_RX_CTL_ENCRCERR_OFST                              (9)
-#define ETHER_RX_CTL_ENCRCERR_MSK                               (0x200)
-#define ETHER_RX_CTL_ENOVER_OFST                                (10)
-#define ETHER_RX_CTL_ENOVER_MSK                                 (0x400)
-#define ETHER_RX_CTL_ENLONGERR_OFST                             (11)
-#define ETHER_RX_CTL_ENLONGERR_MSK                              (0x800)
-#define ETHER_RX_CTL_ENRXPAR_OFST                               (13)
-#define ETHER_RX_CTL_ENRXPAR_MSK                                (0x2000)
-#define ETHER_RX_CTL_ENGOOD_OFST                                (14)
-#define ETHER_RX_CTL_ENGOOD_MSK                                 (0x4000)
-#define ETHER_RX_STAT(base)                                                     (ETHER00_TYPE (base + 0x14))
-#define ETHER_RX_STAT_LENERR_OFST                               (4)
-#define ETHER_RX_STAT_LENERR_MSK                                (0x10)
-#define ETHER_RX_STAT_CTLRECD_OFST                              (5)
-#define ETHER_RX_STAT_CTLRECD_MSK                               (0x20)
-#define ETHER_RX_STAT_INTRX_OFST                                (6)
-#define ETHER_RX_STAT_INTRX_MSK                                 (0x40)
-#define ETHER_RX_STAT_RX10STAT_OFST                             (7)
-#define ETHER_RX_STAT_RX10STAT_MSK                              (0x80)
-#define ETHER_RX_STAT_ALIGNERR_OFST                             (8)
-#define ETHER_RX_STAT_ALIGNERR_MSK                              (0x100)
-#define ETHER_RX_STAT_CRCERR_OFST                               (9)
-#define ETHER_RX_STAT_CRCERR_MSK                                (0x200)
-#define ETHER_RX_STAT_OVERFLOW_OFST                             (10)
-#define ETHER_RX_STAT_OVERFLOW_MSK                              (0x400)
-#define ETHER_RX_STAT_LONGERR_OFST                              (11)
-#define ETHER_RX_STAT_LONGERR_MSK                               (0x800)
-#define ETHER_RX_STAT_RXPAR_OFST                                (13)
-#define ETHER_RX_STAT_RXPAR_MSK                                 (0x2000)
-#define ETHER_RX_STAT_GOOD_OFST                                 (14)
-#define ETHER_RX_STAT_GOOD_MSK                                  (0x4000)
-#define ETHER_RX_STAT_RXHALTED_OFST                             (15)
-#define ETHER_RX_STAT_RXHALTED_MSK                              (0x8000)
-#define ETHER_RX_STAT_RXMCAST_OFST                              (17)
-#define ETHER_RX_STAT_RXMCAST_MSK                               (0x10000)
-#define ETHER_RX_STAT_RXBCAST_OFST                              (18)
-#define ETHER_RX_STAT_RXBCAST_MSK                               (0x20000)
-#define ETHER_RX_STAT_RXVLAN_OFST                               (19)
-#define ETHER_RX_STAT_RXVLAN_MSK                                (0x40000)
-#define ETHER_RX_STAT_RXPAUSE_OFST                              (20)
-#define ETHER_RX_STAT_RXPAUSE_MSK                               (0x80000)
-#define ETHER_RX_STAT_ARCSTATUS_OFST                            (21)
-#define ETHER_RX_STAT_ARCSTATUS_MSK                             (0xF00000)
-#define ETHER_RX_STAT_ARCENT_OFST                               (25)
-#define ETHER_RX_STAT_ARCENT_MSK                                (0x1F000000)
-#define ETHER_MD_DATA(base)                                                     (ETHER00_TYPE (base + 0x18))
-#define ETHER_MD_CA(base)                                                               (ETHER00_TYPE (base + 0x1c))
-#define ETHER_MD_CA_ADDR_OFST                                   (0)
-#define ETHER_MD_CA_ADDR_MSK                                    (0x1F)
-#define ETHER_MD_CA_PHY_OFST                                    (5)
-#define ETHER_MD_CA_PHY_MSK                                     (0x3E0)
-#define ETHER_MD_CA_WR_OFST                                     (10)
-#define ETHER_MD_CA_WR_MSK                                      (0x400)
-#define ETHER_MD_CA_BUSY_OFST                                   (11)
-#define ETHER_MD_CA_BUSY_MSK                                    (0x800)
-#define ETHER_MD_CA_PRESUPP_OFST                                (12)
-#define ETHER_MD_CA_PRESUPP_MSK                                 (0x1000)
-#define ETHER_ARC_ADR(base)           (ETHER00_TYPE (base + 0x160))
-#define ETHER_ARC_ADR_ARC_LOC_OFST                              (2)
-#define ETHER_ARC_ADR_ARC_LOC_MSK                               (0xFFC)
-#define ETHER_ARC_DATA(base)  (ETHER00_TYPE (base + 0x364))
-#define ETHER_ARC_ENA(base)   (ETHER00_TYPE (base + 0x28))
-#define ETHER_ARC_ENA_MSK                                       (0x1FFFFF)
-#define ETHER_PROM_CTL(base)                                                    (ETHER00_TYPE (base + 0x2c))
-#define ETHER_PROM_CTL_PROM_ADDR_OFST                   (0)
-#define ETHER_PROM_CTL_PROM_ADDR_MSK                    (0x3F)
-#define ETHER_PROM_CTL_OPCODE_OFST                              (13)
-#define ETHER_PROM_CTL_OPCODE_MSK                               (0x6000)
-#define ETHER_PROM_CTL_OPCODE_READ_MSK                  (0x4000)
-#define ETHER_PROM_CTL_OPCODE_WRITE_MSK                 (0x2000)
-#define ETHER_PROM_CTL_OPCODE_ERASE_MSK                 (0x6000)
-#define ETHER_PROM_CTL_ENABLE_MSK                               (0x0030)
-#define ETHER_PROM_CTL_DISABLE_MSK                              (0x0000)
-#define ETHER_PROM_CTL_BUSY_OFST                                (15)
-#define ETHER_PROM_CTL_BUSY_MSK                                 (0x8000)
-#define ETHER_PROM_DATA(base)                                                   (ETHER00_TYPE (base + 0x30))
-#define ETHER_MISS_CNT(base)                                                    (ETHER00_TYPE (base + 0x3c))
-#define ETHER_MISS_CNT_COUNT_OFST                               (0)
-#define ETHER_MISS_CNT_COUNT_MSK                                (0xFFFF)
-#define ETHER_CNTDATA(base)                                                     (ETHER00_TYPE (base + 0x80))
-#define ETHER_CNTACC(base)                                                      (ETHER00_TYPE (base + 0x84))
-#define ETHER_CNTACC_ADDR_OFST                                  (0)
-#define ETHER_CNTACC_ADDR_MSK                                   (0xFF)
-#define ETHER_CNTACC_WRRDN_OFST                                 (8)
-#define ETHER_CNTACC_WRRDN_MSK                                  (0x100)
-#define ETHER_CNTACC_CLEAR_OFST                                 (9)
-#define ETHER_CNTACC_CLEAR_MSK                                  (0x200)
-#define ETHER_TXRMINTEN(base)                                                   (ETHER00_TYPE (base + 0x88))
-#define ETHER_TXRMINTEN_MSK                                             (0x3FFFFFFF)
-#define ETHER_RXRMINTEN(base)                                                   (ETHER00_TYPE (base + 0x8C))
-#define ETHER_RXRMINTEN_MSK                                             (0xFFFFFF)
-/*
-*       RMON Registers
-*/
-#define         RMON_COLLISION0                                         0x0
-#define         RMON_COLLISION1                                         0x1
-#define         RMON_COLLISION2                                         0x2
-#define         RMON_COLLISION3                                         0x3
-#define         RMON_COLLISION4                                         0x4
-#define         RMON_COLLISION5                                         0x5
-#define         RMON_COLLISION6                                         0x6
-#define         RMON_COLLISION7                                         0x7
-#define         RMON_COLLISION8                                         0x8
-#define         RMON_COLLISION9                                         0x9
-#define         RMON_COLLISION10                                        0xa
-#define         RMON_COLLISION11                                        0xb
-#define         RMON_COLLISION12                                        0xc
-#define         RMON_COLLISION13                                        0xd
-#define         RMON_COLLISION14                                        0xe
-#define         RMON_COLLISION15                                        0xf
-#define         RMON_COLLISION16                                        0x10
-#define         RMON_FRAMES_WITH_DEFERRED_XMISSIONS     0x11
-#define         RMON_LATE_COLLISIONS                            0x12
-#define         RMON_FRAMES_LOST_DUE_TO_MAC_XMIT        0x13
-#define         RMON_CARRIER_SENSE_ERRORS                       0x14
-#define         RMON_FRAMES_WITH_EXCESSIVE_DEFERAL      0x15
-#define         RMON_UNICAST_FRAMES_TRANSMITTED_OK      0x16
-#define         RMON_MULTICAST_FRAMES_XMITTED_OK        0x17
-#define         RMON_BROADCAST_FRAMES_XMITTED_OK        0x18
-#define         RMON_SQE_TEST_ERRORS                            0x19
-#define         RMON_PAUSE_MACCTRL_FRAMES_XMITTED       0x1A
-#define         RMON_MACCTRL_FRAMES_XMITTED                     0x1B
-#define         RMON_VLAN_FRAMES_XMITTED                        0x1C
-#define         RMON_OCTETS_XMITTED_OK                          0x1D
-#define         RMON_OCTETS_XMITTED_OK_HI                       0x1E
-#define         RMON_RX_PACKET_SIZES0                           0x40
-#define         RMON_RX_PACKET_SIZES1                           0x41
-#define         RMON_RX_PACKET_SIZES2                           0x42
-#define         RMON_RX_PACKET_SIZES3                           0x43
-#define         RMON_RX_PACKET_SIZES4                           0x44
-#define         RMON_RX_PACKET_SIZES5                           0x45
-#define         RMON_RX_PACKET_SIZES6                           0x46
-#define         RMON_RX_PACKET_SIZES7                           0x47
-#define         RMON_FRAME_CHECK_SEQUENCE_ERRORS        0x48
-#define         RMON_ALIGNMENT_ERRORS                           0x49
-#define         RMON_FRAGMENTS                                          0x4A
-#define         RMON_JABBERS                                            0x4B
-#define         RMON_FRAMES_LOST_TO_INTMACRCVERR        0x4C
-#define         RMON_UNICAST_FRAMES_RCVD_OK                     0x4D
-#define         RMON_MULTICAST_FRAMES_RCVD_OK           0x4E
-#define         RMON_BROADCAST_FRAMES_RCVD_OK           0x4F
-#define         RMON_IN_RANGE_LENGTH_ERRORS                     0x50
-#define         RMON_OUT_OF_RANGE_LENGTH_ERRORS         0x51
-#define         RMON_VLAN_FRAMES_RCVD                           0x52
-#define         RMON_PAUSE_MAC_CTRL_FRAMES_RCVD         0x53
-#define         RMON_MAC_CTRL_FRAMES_RCVD                       0x54
-#define         RMON_OCTETS_RCVD_OK                                     0x55
-#define         RMON_OCTETS_RCVD_OK_HI                          0x56
-#define         RMON_OCTETS_RCVD_OTHER                          0x57
-#define         RMON_OCTETS_RCVD_OTHER_HI                       0x58
-#endif /* __ETHER00_H */
diff --git a/include/asm-arm/arch-epxa10db/excalibur.h b/include/asm-arm/arch-epxa10db/excalibur.h
deleted file mode 100644
index 5c91dd6d7822..000000000000
--- a/include/asm-arm/arch-epxa10db/excalibur.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* megafunction wizard: %ARM-Based Excalibur%
-   GENERATION: STANDARD
-   VERSION: WM1.0
-   MODULE: ARM-Based Excalibur
-   PROJECT: excalibur
-   ============================================================
-   File Name: v:\embedded\linux\bootldr\excalibur.h
-   Megafunction Name(s): ARM-Based Excalibur
-   ============================================================
-   ************************************************************
-   THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-   ************************************************************/
-#ifndef EXCALIBUR_H_INCLUDED
-#define EXCALIBUR_H_INCLUDED
-#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
-#define EXC_DEFINE_BOOT_FROM_FLASH
-#define EXC_INPUT_CLK_FREQUENCY (50000000)
-#define EXC_AHB1_CLK_FREQUENCY (150000000)
-#define EXC_AHB2_CLK_FREQUENCY (75000000)
-#define EXC_SDRAM_CLK_FREQUENCY (75000000)
-/* Registers Block */
-#define EXC_REGISTERS_BASE (0x7fffc000)
-#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
-#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
-#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
-#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
-#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
-#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
-#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
-#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
-#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
-#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
-#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
-#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
-#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
-#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
-#define EXC_REGISTERS_SIZE (0x00004000)
-/* EBI Block(s) */
-#define EXC_EBI_BLOCK0_BASE (0x40000000)
-#define EXC_EBI_BLOCK0_SIZE (0x00400000)
-#define EXC_EBI_BLOCK0_WIDTH (8)
-#define EXC_EBI_BLOCK0_NON_CACHEABLE
-#define EXC_EBI_BLOCK1_BASE (0x40400000)
-#define EXC_EBI_BLOCK1_SIZE (0x00400000)
-#define EXC_EBI_BLOCK1_WIDTH (16)
-#define EXC_EBI_BLOCK1_NON_CACHEABLE
-#define EXC_EBI_BLOCK2_BASE (0x40800000)
-#define EXC_EBI_BLOCK2_SIZE (0x00400000)
-#define EXC_EBI_BLOCK2_WIDTH (16)
-#define EXC_EBI_BLOCK2_NON_CACHEABLE
-#define EXC_EBI_BLOCK3_BASE (0x40c00000)
-#define EXC_EBI_BLOCK3_SIZE (0x00400000)
-#define EXC_EBI_BLOCK3_WIDTH (16)
-#define EXC_EBI_BLOCK3_NON_CACHEABLE
-/* SDRAM Block(s) */
-#define EXC_SDRAM_BLOCK0_BASE (0x00000000)
-#define EXC_SDRAM_BLOCK0_SIZE (0x04000000)
-#define EXC_SDRAM_BLOCK0_WIDTH (32)
-#define EXC_SDRAM_BLOCK1_BASE (0x04000000)
-#define EXC_SDRAM_BLOCK1_SIZE (0x04000000)
-#define EXC_SDRAM_BLOCK1_WIDTH (32)
-/* Single Port SRAM Block(s) */
-#define EXC_SPSRAM_BLOCK0_BASE (0x08000000)
-#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000)
-#define EXC_SPSRAM_BLOCK1_BASE (0x08020000)
-#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000)
-/* PLD Block(s) */
-#define EXC_PLD_BLOCK0_BASE (0x80000000)
-#define EXC_PLD_BLOCK0_SIZE (0x00004000)
-#define EXC_PLD_BLOCK0_NON_CACHEABLE
-#define EXC_PLD_BLOCK1_BASE (0xf000000)
-#define EXC_PLD_BLOCK1_SIZE (0x00004000)
-#define EXC_PLD_BLOCK1_NON_CACHEABLE
-#define EXC_PLD_BLOCK2_BASE (0x80008000)
-#define EXC_PLD_BLOCK2_SIZE (0x00004000)
-#define EXC_PLD_BLOCK2_NON_CACHEABLE
-#define EXC_PLD_BLOCK3_BASE (0x8000c000)
-#define EXC_PLD_BLOCK3_SIZE (0x00004000)
-#define EXC_PLD_BLOCK3_NON_CACHEABLE
-#endif
diff --git a/include/asm-arm/arch-epxa10db/hardware.h b/include/asm-arm/arch-epxa10db/hardware.h
deleted file mode 100644
index b992c2924a77..000000000000
--- a/include/asm-arm/arch-epxa10db/hardware.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-epxa10/hardware.h
- *
- *  This file contains the hardware definitions of the Integrator.
- *
- *  Copyright (C) 1999 ARM Limited.
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/arch/platform.h>
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define IO_BASE                 0xf0000000                 // VA of IO 
-#define IO_SIZE                 0x10000000                 // How much?
-#define IO_START                EXC_REGISTERS_BASE              // PA of IO
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) ((x) | 0xf0000000) 
-#define FLASH_VBASE             0xFE000000
-#define FLASH_SIZE              0x01000000
-#define FLASH_START             EXC_EBI_BLOCK0_BASE
-#define FLASH_VADDR(x) ((x)|0xFE000000)
-/*
- * Similar to above, but for PCI addresses (memory, IO, Config and the
- * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
- */
-#if 0
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
-#define PCIO_BASE               PCI_IO_VADDR
-#define PCIMEM_BASE             PCI_MEMORY_VADDR
-#define pcibios_assign_all_busses()     1
-#define PCIBIOS_MIN_IO          0x6000
-#define PCIBIOS_MIN_MEM         0x00100000
-#endif
-#endif
diff --git a/include/asm-arm/arch-epxa10db/int_ctrl00.h b/include/asm-arm/arch-epxa10db/int_ctrl00.h
deleted file mode 100644
index 23ec864c40bb..000000000000
--- a/include/asm-arm/arch-epxa10db/int_ctrl00.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- *  
- *  This file contains the register definitions for the Excalibur
- *  Timer TIMER00.
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __INT_CTRL00_H
-#define __INT_CTRL00_H
-#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x00 ))
-#define INT_MS_FC_MSK (0x10000)
-#define INT_MS_FC_OFST (16)
-#define INT_MS_M1_MSK (0x8000)
-#define INT_MS_M1_OFST (15)
-#define INT_MS_M0_MSK (0x4000)
-#define INT_MS_M0_OFST (14)
-#define INT_MS_AE_MSK (0x2000)
-#define INT_MS_AE_OFST (13)
-#define INT_MS_PE_MSK (0x1000)
-#define INT_MS_PE_OFST (12)
-#define INT_MS_EE_MSK (0x0800)
-#define INT_MS_EE_OFST (11)
-#define INT_MS_PS_MSK (0x0400)
-#define INT_MS_PS_OFST (10)
-#define INT_MS_T1_MSK (0x0200)
-#define INT_MS_T1_OFST (9)
-#define INT_MS_T0_MSK (0x0100)
-#define INT_MS_T0_OFST (8)
-#define INT_MS_UA_MSK (0x0080)
-#define INT_MS_UA_OFST (7)
-#define INT_MS_IP_MSK (0x0040)
-#define INT_MS_IP_OFST (6)
-#define INT_MS_P5_MSK (0x0020)
-#define INT_MS_P5_OFST (5)
-#define INT_MS_P4_MSK (0x0010)
-#define INT_MS_P4_OFST (4)
-#define INT_MS_P3_MSK (0x0008)
-#define INT_MS_P3_OFST (3)
-#define INT_MS_P2_MSK (0x0004)
-#define INT_MS_P2_OFST (2)
-#define INT_MS_P1_MSK (0x0002)
-#define INT_MS_P1_OFST (1)
-#define INT_MS_P0_MSK (0x0001)
-#define INT_MS_P0_OFST (0)
-#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x04 ))
-#define INT_MC_FC_MSK (0x10000)
-#define INT_MC_FC_OFST (16)
-#define INT_MC_M1_MSK (0x8000)
-#define INT_MC_M1_OFST (15)
-#define INT_MC_M0_MSK (0x4000)
-#define INT_MC_M0_OFST (14)
-#define INT_MC_AE_MSK (0x2000)
-#define INT_MC_AE_OFST (13)
-#define INT_MC_PE_MSK (0x1000)
-#define INT_MC_PE_OFST (12)
-#define INT_MC_EE_MSK (0x0800)
-#define INT_MC_EE_OFST (11)
-#define INT_MC_PS_MSK (0x0400)
-#define INT_MC_PS_OFST (10)
-#define INT_MC_T1_MSK (0x0200)
-#define INT_MC_T1_OFST (9)
-#define INT_MC_T0_MSK (0x0100)
-#define INT_MC_T0_OFST (8)
-#define INT_MC_UA_MSK (0x0080)
-#define INT_MC_UA_OFST (7)
-#define INT_MC_IP_MSK (0x0040)
-#define INT_MC_IP_OFST (6)
-#define INT_MC_P5_MSK (0x0020)
-#define INT_MC_P5_OFST (5)
-#define INT_MC_P4_MSK (0x0010)
-#define INT_MC_P4_OFST (4)
-#define INT_MC_P3_MSK (0x0008)
-#define INT_MC_P3_OFST (3)
-#define INT_MC_P2_MSK (0x0004)
-#define INT_MC_P2_OFST (2)
-#define INT_MC_P1_MSK (0x0002)
-#define INT_MC_P1_OFST (1)
-#define INT_MC_P0_MSK (0x0001)
-#define INT_MC_P0_OFST (0)
-#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x08 ))
-#define INT_SS_FC_SSK (0x8000)
-#define INT_SS_FC_OFST (15)
-#define INT_SS_M1_SSK (0x8000)
-#define INT_SS_M1_OFST (15)
-#define INT_SS_M0_SSK (0x4000)
-#define INT_SS_M0_OFST (14)
-#define INT_SS_AE_SSK (0x2000)
-#define INT_SS_AE_OFST (13)
-#define INT_SS_PE_SSK (0x1000)
-#define INT_SS_PE_OFST (12)
-#define INT_SS_EE_SSK (0x0800)
-#define INT_SS_EE_OFST (11)
-#define INT_SS_PS_SSK (0x0400)
-#define INT_SS_PS_OFST (10)
-#define INT_SS_T1_SSK (0x0200)
-#define INT_SS_T1_OFST (9)
-#define INT_SS_T0_SSK (0x0100)
-#define INT_SS_T0_OFST (8)
-#define INT_SS_UA_SSK (0x0080)
-#define INT_SS_UA_OFST (7)
-#define INT_SS_IP_SSK (0x0040)
-#define INT_SS_IP_OFST (6)
-#define INT_SS_P5_SSK (0x0020)
-#define INT_SS_P5_OFST (5)
-#define INT_SS_P4_SSK (0x0010)
-#define INT_SS_P4_OFST (4)
-#define INT_SS_P3_SSK (0x0008)
-#define INT_SS_P3_OFST (3)
-#define INT_SS_P2_SSK (0x0004)
-#define INT_SS_P2_OFST (2)
-#define INT_SS_P1_SSK (0x0002)
-#define INT_SS_P1_OFST (1)
-#define INT_SS_P0_SSK (0x0001)
-#define INT_SS_P0_OFST (0)
-#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x0C ))
-#define INT_RS_FC_RSK (0x10000)
-#define INT_RS_FC_OFST (16)
-#define INT_RS_M1_RSK (0x8000)
-#define INT_RS_M1_OFST (15)
-#define INT_RS_M0_RSK (0x4000)
-#define INT_RS_M0_OFST (14)
-#define INT_RS_AE_RSK (0x2000)
-#define INT_RS_AE_OFST (13)
-#define INT_RS_PE_RSK (0x1000)
-#define INT_RS_PE_OFST (12)
-#define INT_RS_EE_RSK (0x0800)
-#define INT_RS_EE_OFST (11)
-#define INT_RS_PS_RSK (0x0400)
-#define INT_RS_PS_OFST (10)
-#define INT_RS_T1_RSK (0x0200)
-#define INT_RS_T1_OFST (9)
-#define INT_RS_T0_RSK (0x0100)
-#define INT_RS_T0_OFST (8)
-#define INT_RS_UA_RSK (0x0080)
-#define INT_RS_UA_OFST (7)
-#define INT_RS_IP_RSK (0x0040)
-#define INT_RS_IP_OFST (6)
-#define INT_RS_P5_RSK (0x0020)
-#define INT_RS_P5_OFST (5)
-#define INT_RS_P4_RSK (0x0010)
-#define INT_RS_P4_OFST (4)
-#define INT_RS_P3_RSK (0x0008)
-#define INT_RS_P3_OFST (3)
-#define INT_RS_P2_RSK (0x0004)
-#define INT_RS_P2_OFST (2)
-#define INT_RS_P1_RSK (0x0002)
-#define INT_RS_P1_OFST (1)
-#define INT_RS_P0_RSK (0x0001)
-#define INT_RS_P0_OFST (0)
-#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x10 ))
-#define INT_ID_ID_MSK (0x3F)
-#define INT_ID_ID_OFST (0)
-#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x14 ))
-#define INT_PLD_PRIORITY_PRI_MSK (0x3F)
-#define INT_PLD_PRIORITY_PRI_OFST (0)
-#define INT_PLD_PRIORITY_GA_MSK (0x40)
-#define INT_PLD_PRIORITY_GA_OFST (6)
-#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x18 ))
-#define INT_MODE_MODE_MSK (0x3)
-#define INT_MODE_MODE_OFST (0)
-#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x80 ))
-#define INT_PRIORITY_P0_PRI_MSK (0x3F)
-#define INT_PRIORITY_P0_PRI_OFST (0)
-#define INT_PRIORITY_P0_FQ_MSK (0x40)
-#define INT_PRIORITY_P0_FQ_OFST (6)
-#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x84 ))
-#define INT_PRIORITY_P1_PRI_MSK (0x3F)
-#define INT_PRIORITY_P1_PRI_OFST (0)
-#define INT_PRIORITY_P1_FQ_MSK (0x40)
-#define INT_PRIORITY_P1_FQ_OFST (6)
-#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x88 ))
-#define INT_PRIORITY_P2_PRI_MSK (0x3F)
-#define INT_PRIORITY_P2_PRI_OFST (0)
-#define INT_PRIORITY_P2_FQ_MSK (0x40)
-#define INT_PRIORITY_P2_FQ_OFST (6)
-#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x8C ))
-#define INT_PRIORITY_P3_PRI_MSK (0x3F)
-#define INT_PRIORITY_P3_PRI_OFST (0)
-#define INT_PRIORITY_P3_FQ_MSK (0x40)
-#define INT_PRIORITY_P3_FQ_OFST (6)
-#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x90 ))
-#define INT_PRIORITY_P4_PRI_MSK (0x3F)
-#define INT_PRIORITY_P4_PRI_OFST (0)
-#define INT_PRIORITY_P4_FQ_MSK (0x40)
-#define INT_PRIORITY_P4_FQ_OFST (6)
-#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x94 ))
-#define INT_PRIORITY_P5_PRI_MSK (0x3F)
-#define INT_PRIORITY_P5_PRI_OFST (0)
-#define INT_PRIORITY_P5_FQ_MSK (0x40)
-#define INT_PRIORITY_P5_FQ_OFST (6)
-#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x94 ))
-#define INT_PRIORITY_IP_PRI_MSK (0x3F)
-#define INT_PRIORITY_IP_PRI_OFST (0)
-#define INT_PRIORITY_IP_FQ_MSK (0x40)
-#define INT_PRIORITY_IP_FQ_OFST (6)
-#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x9C ))
-#define INT_PRIORITY_UA_PRI_MSK (0x3F)
-#define INT_PRIORITY_UA_PRI_OFST (0)
-#define INT_PRIORITY_UA_FQ_MSK (0x40)
-#define INT_PRIORITY_UA_FQ_OFST (6)
-#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA0 ))
-#define INT_PRIORITY_T0_PRI_MSK (0x3F)
-#define INT_PRIORITY_T0_PRI_OFST (0)
-#define INT_PRIORITY_T0_FQ_MSK (0x40)
-#define INT_PRIORITY_T0_FQ_OFST (6)
-#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA4 ))
-#define INT_PRIORITY_T1_PRI_MSK (0x3F)
-#define INT_PRIORITY_T1_PRI_OFST (0)
-#define INT_PRIORITY_T1_FQ_MSK (0x40)
-#define INT_PRIORITY_T1_FQ_OFST (6)
-#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA8 ))
-#define INT_PRIORITY_PS_PRI_MSK (0x3F)
-#define INT_PRIORITY_PS_PRI_OFST (0)
-#define INT_PRIORITY_PS_FQ_MSK (0x40)
-#define INT_PRIORITY_PS_FQ_OFST (6)
-#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xAC ))
-#define INT_PRIORITY_EE_PRI_MSK (0x3F)
-#define INT_PRIORITY_EE_PRI_OFST (0)
-#define INT_PRIORITY_EE_FQ_MSK (0x40)
-#define INT_PRIORITY_EE_FQ_OFST (6)
-#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB0 ))
-#define INT_PRIORITY_PE_PRI_MSK (0x3F)
-#define INT_PRIORITY_PE_PRI_OFST (0)
-#define INT_PRIORITY_PE_FQ_MSK (0x40)
-#define INT_PRIORITY_PE_FQ_OFST (6)
-#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB4 ))
-#define INT_PRIORITY_AE_PRI_MSK (0x3F)
-#define INT_PRIORITY_AE_PRI_OFST (0)
-#define INT_PRIORITY_AE_FQ_MSK (0x40)
-#define INT_PRIORITY_AE_FQ_OFST (6)
-#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB8 ))
-#define INT_PRIORITY_M0_PRI_MSK (0x3F)
-#define INT_PRIORITY_M0_PRI_OFST (0)
-#define INT_PRIORITY_M0_FQ_MSK (0x40)
-#define INT_PRIORITY_M0_FQ_OFST (6)
-#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xBC ))
-#define INT_PRIORITY_M1_PRI_MSK (0x3F)
-#define INT_PRIORITY_M1_PRI_OFST (0)
-#define INT_PRIORITY_M1_FQ_MSK (0x40)
-#define INT_PRIORITY_M1_FQ_OFST (6)
-#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xC0 ))
-#define INT_PRIORITY_FC_PRI_MSK (0x3F)
-#define INT_PRIORITY_FC_PRI_OFST (0)
-#define INT_PRIORITY_FC_FQ_MSK (0x40)
-#define INT_PRIORITY_FC_FQ_OFST (6)
-#endif /* __INT_CTRL00_H */
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h
deleted file mode 100644
index 9fe100c9d6be..000000000000
--- a/include/asm-arm/arch-epxa10db/io.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-epxa10db/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-#include <asm/hardware.h>
-#define IO_SPACE_LIMIT 0xffff
-/*
- * Generic virtual read/write
- */
-/*#define outsw   __arch_writesw
-#define outsl   __arch_writesl
-#define outsb   __arch_writesb
-#define insb    __arch_readsb
-#define insw    __arch_readsw
-#define insl    __arch_readsl*/
-#define __io(a)                 ((void __iomem *)(a))
-#define __mem_pci(a)            (a) 
-#endif
diff --git a/include/asm-arm/arch-epxa10db/irqs.h b/include/asm-arm/arch-epxa10db/irqs.h
deleted file mode 100644
index c3758a3b5d9d..000000000000
--- a/include/asm-arm/arch-epxa10db/irqs.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-camelot/irqs.h
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Use the Excalibur chip definitions */
-#define INT_CTRL00_TYPE
-#include "asm/arch/int_ctrl00.h"
-#define IRQ_PLD0                     INT_MS_P0_OFST
-#define IRQ_PLD1                     INT_MS_P1_OFST
-#define IRQ_PLD2                     INT_MS_P2_OFST
-#define IRQ_PLD3                     INT_MS_P3_OFST
-#define IRQ_PLD4                     INT_MS_P4_OFST
-#define IRQ_PLD5                     INT_MS_P5_OFST
-#define IRQ_EXT                      INT_MS_IP_OFST
-#define IRQ_UART                     INT_MS_UA_OFST
-#define IRQ_TIMER0                   INT_MS_T0_OFST
-#define IRQ_TIMER1                   INT_MS_T1_OFST
-#define IRQ_PLL                      INT_MS_PLL_OFST
-#define IRQ_EBI                      INT_MS_EBI_OFST
-#define IRQ_STRIPE_BRIDGE            INT_MS_PLL_OFST
-#define IRQ_AHB_BRIDGE               INT_MS_PLL_OFST
-#define IRQ_COMMRX                   INT_MS_CR_OFST
-#define IRQ_COMMTX                   INT_MS_CT_OFST
-#define IRQ_FAST_COMM                INT_MS_FC_OFST
-#define NR_IRQS                         (INT_MS_FC_OFST + 1)
diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h
deleted file mode 100644
index d8a7efa12e19..000000000000
--- a/include/asm-arm/arch-epxa10db/mode_ctrl00.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef __MODE_CTRL00_H
-#define __MODE_CTRL00_H
-/*
- * Register definitions for the reset and mode control
- */
-/*
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  ))
-#define BOOT_CR_BF_MSK (0x1)
-#define BOOT_CR_BF_OFST (0)
-#define BOOT_CR_HM_MSK (0x2)
-#define BOOT_CR_HM_OFST (1)
-#define BOOT_CR_RE_MSK (0x4)
-#define BOOT_CR_RE_OFST (2)
-#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x4 ))
-#define RESET_SR_WR_MSK (0x1)
-#define RESET_SR_WR_OFST (0)
-#define RESET_SR_CR_MSK (0x2)
-#define RESET_SR_CR_OFST (1)
-#define RESET_SR_JT_MSK (0x4)
-#define RESET_SR_JT_OFST (2)
-#define RESET_SR_ER_MSK (0x8)
-#define RESET_SR_ER_OFST (3)
-#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x08 ))
-#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x20 ))
-#define SRAM0_SR_SIZE_MSK (0xFFFFF000)
-#define SRAM0_SR_SIZE_OFST (12)
-#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x24 ))
-#define SRAM1_SR_SIZE_MSK (0xFFFFF000)
-#define SRAM1_SR_SIZE_OFST (12)
-#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x30 ))
-#define DPSRAM0_SR_MODE_MSK (0xF)
-#define DPSRAM0_SR_MODE_OFST (0)
-#define DPSRAM0_SR_GLBL_MSK (0x30)
-#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
-#define DPSRAM0_SR_SIZE_OFST (12)
-#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x34 ))
-#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
-#define DPSRAM0_LCR_LCKADDR_OFST (4)
-#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x38 ))
-#define DPSRAM1_SR_MODE_MSK (0xF)
-#define DPSRAM1_SR_MODE_OFST (0)
-#define DPSRAM1_SR_GLBL_MSK (0x30)
-#define DPSRAM1_SR_GLBL_OFST (4)
-#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
-#define DPSRAM1_SR_SIZE_OFST (12)
-#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x3C ))
-#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
-#define DPSRAM1_LCR_LCKADDR_OFST (4)
-#endif /* __MODE_CTRL00_H */
diff --git a/include/asm-arm/arch-epxa10db/platform.h b/include/asm-arm/arch-epxa10db/platform.h
deleted file mode 100644
index 129bb0f212a0..000000000000
--- a/include/asm-arm/arch-epxa10db/platform.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef PLATFORM_H
-#define PLATFORM_H
-#include "excalibur.h"
-#define MAXIRQNUM 15 
-#endif
diff --git a/include/asm-arm/arch-epxa10db/pld_conf00.h b/include/asm-arm/arch-epxa10db/pld_conf00.h
deleted file mode 100644
index 7af2c38dacc6..000000000000
--- a/include/asm-arm/arch-epxa10db/pld_conf00.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef __PLD_CONF00_H
-#define __PLD_CONF00_H
-/*
- * Register definitions for the PLD Configuration Logic
- */
-/*
- *  
- *  This file contains the register definitions for the Excalibur
- *  Interrupt controller INT_CTRL00.
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
- 
-#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR))  
-#define CONFIG_CONTROL_LK_MSK (0x1)
-#define CONFIG_CONTROL_LK_OFST (0)
-#define CONFIG_CONTROL_CO_MSK (0x2)
-#define CONFIG_CONTROL_CO_OFST (1)
-#define CONFIG_CONTROL_B_MSK  (0x4)
-#define CONFIG_CONTROL_B_OFST (2)
-#define CONFIG_CONTROL_PC_MSK (0x8)
-#define CONFIG_CONTROL_PC_OFST (3)
-#define CONFIG_CONTROL_E_MSK (0x10)
-#define CONFIG_CONTROL_E_OFST (4)
-#define CONFIG_CONTROL_ES_MSK (0xE0)
-#define CONFIG_CONTROL_ES_OFST (5)
-#define CONFIG_CONTROL_ES_0_MSK (0x20)
-#define CONFIG_CONTROL_ES_1_MSK (0x40)
-#define CONFIG_CONTROL_ES_2_MSK (0x80)
-#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0x4 ))
-#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF)
-#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0)
-#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0x8 ))
-#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF)
-#define CONFIG_CONTROL_DATA_OFST (0)
-#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0xC )) 
-#define CONFIG_UNLOCK_MSK (0xFFFFFFFF)
-#define CONFIG_UNLOCK_OFST (0)
-#define CONFIG_UNLOCK_MAGIC (0x554E4C4B)
-#endif /* __PLD_CONF00_H */
diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h
deleted file mode 100644
index 5e107bd4e109..000000000000
--- a/include/asm-arm/arch-epxa10db/tdkphy.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- *  linux/drivers/tdkphy.h
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TDKPHY_H
-#define __TDKPHY_H
-/*
- * Register definitions for the TDK 78Q2120 PHY 
- * which is on the Camelot board
- */
-/*
- * Copyright (c) Altera Corporation 2000.
- * All rights reserved.
- */
-#define PHY_CONTROL                                                                                     (0)
-#define PHY_CONTROL_COLT_MSK                                                            (0x80)
-#define PHY_CONTROL_COLT_OFST                                                           (7)
-#define PHY_CONTROL_DUPLEX_MSK                                                          (0x100)
-#define PHY_CONTROL_DUPLEX_OFST                                                         (8)
-#define PHY_CONTROL_RANEG_MSK                                                           (0x200)
-#define PHY_CONTROL_RANEG_OFST                                                          (9)
-#define PHY_CONTROL_ISO_MSK                                                                     (0x400)
-#define PHY_CONTROL_ISO_OFST                                                            (10)
-#define PHY_CONTROL_PWRDN_MSK                                                           (0x800)
-#define PHY_CONTROL_PWRDN_OFST                                                          (11)
-#define PHY_CONTROL_ANEGEN_MSK                                                          (0x1000)
-#define PHY_CONTROL_ANEGEN_OFST                                                         (12)
-#define PHY_CONTROL_SPEEDSL_MSK                                                         (0x2000)
-#define PHY_CONTROL_SPEEDSL_OFST                                                        (13)
-#define PHY_CONTROL_LOOPBK_MSK                                                          (0x4000)
-#define PHY_CONTROL_LOOPBK_OFST                                                         (14)
-#define PHY_CONTROL_RESET_MSK                                                           (0x8000)
-#define PHY_CONTROL_RESET_OFST                                                          (15)
-#define PHY_STATUS                                                                                      (1)
-#define PHY_STATUS_ETXD_MSK                                                                     (0x1)
-#define PHY_STATUS_EXTD_OFST                                                            (0)
-#define PHY_STATUS_JAB_MSK                                                                      (0x2)
-#define PHY_STATUS_JAB_OFST                                                                     (1)
-#define PHY_STATUS_LINK_MSK                                                                     (0x4)
-#define PHY_STATUS_LINK_OFST                                                            (2)
-#define PHY_STATUS_ANEGA_MSK                                                            (0x8)
-#define PHY_STATUS_ANEGA_OFST                                                           (3)
-#define PHY_STATUS_RFAULT_MSK                                                           (0x10)
-#define PHY_STATUS_RFAULT_OFST                                                          (4)
-#define PHY_STATUS_ANEGC_MSK                                                            (0x20)
-#define PHY_STATUS_ANEGC_OFST                                                           (5)
-#define PHY_STATUS_10T_H_MSK                                                            (0x800)
-#define PHY_STATUS_10T_H_OFST                                                           (11)
-#define PHY_STATUS_10T_F_MSK                                                            (0x1000)
-#define PHY_STATUS_10T_F_OFST                                                           (12)
-#define PHY_STATUS_100_X_H_MSK                                                          (0x2000)
-#define PHY_STATUS_100_X_H_OFST                                                         (13)
-#define PHY_STATUS_100_X_F_MSK                                                          (0x4000)
-#define PHY_STATUS_100_X_F_OFST                                                         (14)
-#define PHY_STATUS_100T4_MSK                                                            (0x8000)
-#define PHY_STATUS_100T4_OFST                                                           (15)
-#define PHY_ID1                                                                                         (2)
-#define PHY_ID1_OUI_MSK                                                                         (0xFFFF)
-#define PHY_ID1_OUI_OFST                                                                        (0)
-#define PHY_ID2                                                                                         (3)
-#define PHY_ID2_RN_MSK                                                                          (0xF)
-#define PHY_ID2_RN_OFST                                                                         (0)
-#define PHY_ID2_MN_MSK                                                                          (0x3F0)
-#define PHY_ID2_MN_OFST                                                                         (4)
-#define PHY_ID2_OUI_MSK                                                                         (0xFC00)
-#define PHY_ID2_OUI_OFST                                                                        (10)
-#define PHY_AUTO_NEG_ADVERTISEMENT                                                      (4)
-#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK                         (0x1F)
-#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST                        (0)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK                                       (0x20)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST                                      (5)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK                                       (0x40)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST                                      (6)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK                                       (0x80)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST                                      (7)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK                                       (0x100)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST                                      (8)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK                                       (0x200)
-#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST                                      (9)
-#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK                                      (0x1FE0)
-#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST                                     (5)
-#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK                                       (0x2000)
-#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST                                      (13)
-#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK                                     (0x4000)
-#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST                            (14)
-#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK                                       (0x8000)
-#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST                                      (15)
-#define PHY_AUTO_NEG_LINK_PARTNER                                                       (5)
-#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK                                        (0x1F)
-#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST                                       (0)
-#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK                                        (0x1FE0)
-#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST                                       (5)
-#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK                                        (0x2000)
-#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST                                       (13)
-#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK                                       (0x4000)
-#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST                                      (14)
-#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK                                        (0x8000)
-#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST                                       (15)
-#define PHY_AUTO_NEG_EXPANSION                                                          (6)
-#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK                                      (0x1)
-#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST                                     (0)
-#define PHY_AUTO_NEG_EXPANSION_PRX_MSK                                          (0x2)
-#define PHY_AUTO_NEG_EXPANSION_PRX_OFST                                         (1)
-#define PHY_AUTO_NEG_EXPANSION_NPA_MSK                                          (0x4)
-#define PHY_AUTO_NEG_EXPANSION_NPA_OFST                                         (2)
-#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK                                        (0x8)
-#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST                                       (3)
-#define PHY_AUTO_NEG_EXPANSION_PDF_MSK                                          (0x10)
-#define PHY_AUTO_NEG_EXPANSION_PDF_OFST                                         (4)
-#define PHY_VENDOR_SPECIFIC                                                                     (16)
-#define PHY_VENDOR_SPECIFIC_RXCC_MSK                                            (0x1)
-#define PHY_VENDOR_SPECIFIC_RXCC_OFST                                           (0)
-#define PHY_VENDOR_SPECIFIC_PCSBP_MSK                                           (0x2)
-#define PHY_VENDOR_SPECIFIC_PCSBP_OFST                                          (1)
-#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK                                          (0x10)
-#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST                                         (4)
-#define PHY_VENDOR_SPECIFIC_APOL_MSK                                            (0x20)  
-#define PHY_VENDOR_SPECIFIC_APOL_OFST                                           (5)
-#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK                                       (0x40)
-#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST                                      (6)
-#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK                                       (0x80)
-#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST                                      (7)
-#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK                                       (0x100)
-#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST                                      (8)
-#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK                                       (0x200)
-#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST                                      (9)
-#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK       (0x400)
-#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST      (10)
-#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK           (0x800)
-#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST          (11)
-#define PHY_VENDOR_SPECIFIC_TXHIM_MSK                                           (0x1000)
-#define PHY_VENDOR_SPECIFIC_TXHIM_OFST                                          (12)
-#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK                                       (0x4000)
-#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST                                      (14)
-#define PHY_VENDOR_SPECIFIC_RPTR_MSK                                            (0x8000)
-#define PHY_VENDOR_SPECIFIC_RPTR_OFST                                           (15)
-#define PHY_IRQ_CONTROL                                                                         (17)
-#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK                                       (0x1)
-#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST                                      (0)
-#define PHY_IRQ_CONTROL_RFAULT_INT_MSK                                          (0x2)
-#define PHY_IRQ_CONTROL_RFAULT_INT_OFST                                         (1)
-#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK                                          (0x4)
-#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST                                         (2)
-#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK                                          (0x8)
-#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST                                         (3)
-#define PHY_IRQ_CONTROL_PDF_INT_MSK                                                     (0x10)
-#define PHY_IRQ_CONTROL_PDF_INT_OFST                                            (4)
-#define PHY_IRQ_CONTROL_PRX_INT_MSK                                                     (0x20)
-#define PHY_IRQ_CONTROL_PRX_INT_OFST                                            (5)
-#define PHY_IRQ_CONTROL_RXER_INT_MSK                                            (0x40)
-#define PHY_IRQ_CONTROL_RXER_INT_OFST                                           (6)
-#define PHY_IRQ_CONTROL_JABBER_INT_MSK                                          (0x80)
-#define PHY_IRQ_CONTROL_JABBER_INT_OFST                                         (7)
-#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK                                        (0x100)
-#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST                                       (8)
-#define PHY_IRQ_CONTROL_RFAULT_IE_MSK                                           (0x200)
-#define PHY_IRQ_CONTROL_RFAULT_IE_OFST                                          (9)
-#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK                                           (0x400)
-#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST                                          (10)
-#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK                                           (0x800)
-#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST                                          (11)
-#define PHY_IRQ_CONTROL_PDF_IE_MSK                                                      (0x1000)
-#define PHY_IRQ_CONTROL_PDF_IE_OFST                                                     (12)
-#define PHY_IRQ_CONTROL_PRX_IE_MSK                                                      (0x2000)
-#define PHY_IRQ_CONTROL_PRX_IE_OFST                                                     (13)
-#define PHY_IRQ_CONTROL_RXER_IE_MSK                                                     (0x4000)
-#define PHY_IRQ_CONTROL_RXER_IE_OFST                                            (14)
-#define PHY_IRQ_CONTROL_JABBER_IE_MSK                                           (0x8000)
-#define PHY_IRQ_CONTROL_JABBER_IE_OFST                                          (15)
-#define PHY_DIAGNOSTIC                                                                          (18)
-#define PHY_DIAGNOSTIC_RX_LOCK_MSK                                                      (0x100)
-#define PHY_DIAGNOSTIC_RX_LOCK_OFST                                                     (8)
-#define PHY_DIAGNOSTIC_RX_PASS_MSK                                                      (0x200)
-#define PHY_DIAGNOSTIC_RX_PASS_OFST                                                     (9)
-#define PHY_DIAGNOSTIC_RATE_MSK                                                         (0x400)
-#define PHY_DIAGNOSTIC_RATE_OFST                                                        (10)
-#define PHY_DIAGNOSTIC_DPLX_MSK                                                         (0x800)
-#define PHY_DIAGNOSTIC_DPLX_OFST                                                        (11)
-#define PHY_DIAGNOSTIC_ANEGF_MSK                                                        (0x1000)
-#define PHY_DIAGNOSTIC_ANEGF_OFST                                                       (12)
-#endif /* __TDKPHY_H */
diff --git a/include/asm-arm/arch-epxa10db/timer00.h b/include/asm-arm/arch-epxa10db/timer00.h
deleted file mode 100644
index 52a3fb58b59d..000000000000
--- a/include/asm-arm/arch-epxa10db/timer00.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *  
- *  This file contains the register definitions for the Excalibur
- *  Timer TIMER00.
- *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TIMER00_H
-#define __TIMER00_H
-/*
- * Register definitions for the timers
- */
-#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x00 ))
-#define TIMER0_CR_B_MSK (0x20)
-#define TIMER0_CR_B_OFST (0x5)
-#define TIMER0_CR_S_MSK  (0x10)
-#define TIMER0_CR_S_OFST (0x4)
-#define TIMER0_CR_CI_MSK (0x08)
-#define TIMER0_CR_CI_OFST (0x3)
-#define TIMER0_CR_IE_MSK (0x04)
-#define TIMER0_CR_IE_OFST (0x2)
-#define TIMER0_CR_MODE_MSK (0x3)
-#define TIMER0_CR_MODE_OFST (0)
-#define TIMER0_CR_MODE_FREE (0)
-#define TIMER0_CR_MODE_ONE  (1)
-#define TIMER0_CR_MODE_INTVL (2)
-#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x00 ))
-#define TIMER0_SR_B_MSK (0x20)
-#define TIMER0_SR_B_OFST (0x5)
-#define TIMER0_SR_S_MSK  (0x10)
-#define TIMER0_SR_S_OFST (0x4)
-#define TIMER0_SR_CI_MSK (0x08)
-#define TIMER0_SR_CI_OFST (0x3)
-#define TIMER0_SR_IE_MSK (0x04)
-#define TIMER0_SR_IE_OFST (0x2)
-#define TIMER0_SR_MODE_MSK (0x3)
-#define TIMER0_SR_MODE_OFST (0)
-#define TIMER0_SR_MODE_FREE (0)
-#define TIMER0_SR_MODE_ONE  (1)
-#define TIMER0_SR_MODE_INTVL (2)
-#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x010 ))
-#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x020 ))
-#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x030 ))
-#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x40 ))
-#define TIMER1_CR_B_MSK (0x20)
-#define TIMER1_CR_B_OFST (0x5)
-#define TIMER1_CR_S_MSK  (0x10)
-#define TIMER1_CR_S_OFST (0x4)
-#define TIMER1_CR_CI_MSK (0x08)
-#define TIMER1_CR_CI_OFST (0x3)
-#define TIMER1_CR_IE_MSK (0x04)
-#define TIMER1_CR_IE_OFST (0x2)
-#define TIMER1_CR_MODE_MSK (0x3)
-#define TIMER1_CR_MODE_OFST (0)
-#define TIMER1_CR_MODE_FREE (0)
-#define TIMER1_CR_MODE_ONE  (1)
-#define TIMER1_CR_MODE_INTVL (2)
-#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x40 ))
-#define TIMER1_SR_B_MSK (0x20)
-#define TIMER1_SR_B_OFST (0x5)
-#define TIMER1_SR_S_MSK  (0x10)
-#define TIMER1_SR_S_OFST (0x4)
-#define TIMER1_SR_CI_MSK (0x08)
-#define TIMER1_SR_CI_OFST (0x3)
-#define TIMER1_SR_IE_MSK (0x04)
-#define TIMER1_SR_IE_OFST (0x2)
-#define TIMER1_SR_MODE_MSK (0x3)
-#define TIMER1_SR_MODE_OFST (0)
-#define TIMER1_SR_MODE_FREE (0)
-#define TIMER1_SR_MODE_ONE  (1)
-#define TIMER1_SR_MODE_INTVL (2)
-#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x050 ))
-#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x060 ))
-#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x070 ))
-#endif /* __TIMER00_H */
diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h
deleted file mode 100644
index 5abd8914d68b..000000000000
--- a/include/asm-arm/arch-epxa10db/uart00.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* *
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __UART00_H
-#define __UART00_H
-/*
- * Register definitions for the UART
- */
-#define UART_TX_FIFO_SIZE      (15)
-#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x00 ))
-#define UART_RSR_RX_LEVEL_MSK (0x1f)
-#define UART_RSR_RX_LEVEL_OFST (0)
-#define UART_RSR_RE_MSK (0x80)
-#define UART_RSR_RE_OFST (7)
-#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x04 ))
-#define UART_RDS_BI_MSK (0x8)
-#define UART_RDS_BI_OFST (4)
-#define UART_RDS_FE_MSK (0x4)
-#define UART_RDS_FE_OFST (2)
-#define UART_RDS_PE_MSK (0x2)
-#define UART_RDS_PE_OFST (1)
-#define UART_RDS_OE_MSK (0x1)
-#define UART_RDS_OE_OFST (0)
-#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x08 ))
-#define UART_RD_RX_DATA_MSK (0xff)
-#define UART_RD_RX_DATA_OFST (0)
-#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x0c ))
-#define UART_TSR_TX_LEVEL_MSK (0x1f)
-#define UART_TSR_TX_LEVEL_OFST (0)
-#define UART_TSR_TXI_MSK (0x80)
-#define UART_TSR_TXI_OFST (7)
-#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x10 ))
-#define UART_TD_TX_DATA_MSK (0xff)
-#define UART_TD_TX_DATA_OFST (0)
-#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x14 ))
-#define UART_FCR_RX_THR_MSK (0xd0)
-#define UART_FCR_RX_THR_OFST (5)
-#define UART_FCR_RX_THR_1 (0x00)
-#define UART_FCR_RX_THR_2 (0x20)
-#define UART_FCR_RX_THR_4 (0x40)
-#define UART_FCR_RX_THR_6 (0x60)
-#define UART_FCR_RX_THR_8 (0x80)
-#define UART_FCR_RX_THR_10 (0xa0)
-#define UART_FCR_RX_THR_12 (0xc0)
-#define UART_FCR_RX_THR_14 (0xd0)
-#define UART_FCR_TX_THR_MSK (0x1c)
-#define UART_FCR_TX_THR_OFST (2)
-#define UART_FCR_TX_THR_0 (0x00)
-#define UART_FCR_TX_THR_2 (0x04)
-#define UART_FCR_TX_THR_4 (0x08)
-#define UART_FCR_TX_THR_8 (0x0c)
-#define UART_FCR_TX_THR_10 (0x10)
-#define UART_FCR_TX_THR_12 (0x14)
-#define UART_FCR_TX_THR_14 (0x18)
-#define UART_FCR_TX_THR_15 (0x1c)
-#define UART_FCR_RC_MSK (0x02)
-#define UART_FCR_RC_OFST (1)
-#define UART_FCR_TC_MSK (0x01)
-#define UART_FCR_TC_OFST (0)
-#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x18 ))
-#define UART_IES_ME_MSK (0x8)
-#define UART_IES_ME_OFST (3)
-#define UART_IES_TIE_MSK (0x4)
-#define UART_IES_TIE_OFST (2)
-#define UART_IES_TE_MSK (0x2)
-#define UART_IES_TE_OFST (1)
-#define UART_IES_RE_MSK (0x1)
-#define UART_IES_RE_OFST (0)
-#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x1c ))
-#define UART_IEC_ME_MSK (0x8)
-#define UART_IEC_ME_OFST (3)
-#define UART_IEC_TIE_MSK (0x4)
-#define UART_IEC_TIE_OFST (2)
-#define UART_IEC_TE_MSK (0x2)
-#define UART_IEC_TE_OFST (1)
-#define UART_IEC_RE_MSK (0x1)
-#define UART_IEC_RE_OFST (0)
-#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x20 ))
-#define UART_ISR_MI_MSK (0x8)
-#define UART_ISR_MI_OFST (3)
-#define UART_ISR_TII_MSK (0x4)
-#define UART_ISR_TII_OFST (2)
-#define UART_ISR_TI_MSK (0x2)
-#define UART_ISR_TI_OFST (1)
-#define UART_ISR_RI_MSK (0x1)
-#define UART_ISR_RI_OFST (0)
-#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x24 ))
-#define UART_IID_IID_MSK (0x7)
-#define UART_IID_IID_OFST (0)
-#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x28 ))
-#define UART_MC_OE_MSK (0x40)
-#define UART_MC_OE_OFST (6)
-#define UART_MC_SP_MSK (0x20)
-#define UART_MC_SP_OFST (5)
-#define UART_MC_EP_MSK (0x10)
-#define UART_MC_EP_OFST (4)
-#define UART_MC_PE_MSK (0x08)
-#define UART_MC_PE_OFST (3)
-#define UART_MC_ST_MSK (0x04)
-#define UART_MC_ST_ONE (0x0)
-#define UART_MC_ST_TWO (0x04)
-#define UART_MC_ST_OFST (2)
-#define UART_MC_CLS_MSK (0x03)
-#define UART_MC_CLS_OFST (0)
-#define UART_MC_CLS_CHARLEN_5 (0)
-#define UART_MC_CLS_CHARLEN_6 (1)
-#define UART_MC_CLS_CHARLEN_7 (2)
-#define UART_MC_CLS_CHARLEN_8 (3)
-#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x2c ))
-#define UART_MCR_AC_MSK (0x80)
-#define UART_MCR_AC_OFST (7)
-#define UART_MCR_AR_MSK (0x40)
-#define UART_MCR_AR_OFST (6)
-#define UART_MCR_BR_MSK (0x20)
-#define UART_MCR_BR_OFST (5)
-#define UART_MCR_LB_MSK (0x10)
-#define UART_MCR_LB_OFST (4)
-#define UART_MCR_DCD_MSK (0x08)
-#define UART_MCR_DCD_OFST (3)
-#define UART_MCR_RI_MSK (0x04)
-#define UART_MCR_RI_OFST (2)
-#define UART_MCR_DTR_MSK (0x02)
-#define UART_MCR_DTR_OFST (1)
-#define UART_MCR_RTS_MSK (0x01)
-#define UART_MCR_RTS_OFST (0)
-#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x30 ))
-#define UART_MSR_DCD_MSK (0x80)
-#define UART_MSR_DCD_OFST (7)
-#define UART_MSR_RI_MSK (0x40)
-#define UART_MSR_RI_OFST (6)
-#define UART_MSR_DSR_MSK (0x20)
-#define UART_MSR_DSR_OFST (5)
-#define UART_MSR_CTS_MSK (0x10)
-#define UART_MSR_CTS_OFST (4)
-#define UART_MSR_DDCD_MSK (0x08)
-#define UART_MSR_DDCD_OFST (3)
-#define UART_MSR_TERI_MSK (0x04)
-#define UART_MSR_TERI_OFST (2)
-#define UART_MSR_DDSR_MSK (0x02)
-#define UART_MSR_DDSR_OFST (1)
-#define UART_MSR_DCTS_MSK (0x01)
-#define UART_MSR_DCTS_OFST (0)
-#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x34 ))
-#define UART_DIV_LO_DIV_MSK (0xff)
-#define UART_DIV_LO_DIV_OFST (0)
-#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x38 ))
-#define UART_DIV_HI_DIV_MSK (0xff)
-#define UART_DIV_HI_DIV_OFST (0)
-#endif /* __UART00_H */
diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h
deleted file mode 100644
index fdfe0e6848f8..000000000000
--- a/include/asm-arm/arch-epxa10db/uncompress.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  linux/include/asm-arm/arch-epxa10db/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2001 Altera Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include "asm/arch/platform.h"
-#include "asm/hardware.h"
-#define UART00_TYPE (volatile unsigned int*)
-#include "asm/arch/uart00.h"
-/*
- * This does not append a newline
- */
-static void putstr(const char *s)
-{
-        while (*s) {
-                while ((*UART_TSR(EXC_UART00_BASE) &
-                       UART_TSR_TX_LEVEL_MSK)==15)
-                        barrier();
-                *UART_TD(EXC_UART00_BASE) = *s;
-                if (*s == '\n') {
-                        while ((*UART_TSR(EXC_UART00_BASE) &
-                               UART_TSR_TX_LEVEL_MSK)==15)
-                                barrier();
-                        *UART_TD(EXC_UART00_BASE) = '\r';
-                }
-                s++;
-        }
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 0cf4d4f99600..fd0147e52dbb 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -56,7 +56,12 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 /*
 * Architecture ioremap implementation.
+ *
+ * __ioremap takes CPU physical address.
+ *
+ * __ioremap_pfn takes a Page Frame Number and an offset into that page
 */
+extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long);
 extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
 extern void __iounmap(void __iomem *addr);
@@ -261,6 +266,7 @@ out:
 *
 * ioremap takes a PCI memory address, as specified in
 * Documentation/IO-mapping.txt.
+ *
 */
 #ifndef __arch_ioremap
 #define ioremap(cookie,size)            __ioremap(cookie,size,0)
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
index b338936bde4f..3351b77fab36 100644
--- a/include/asm-arm/mach/map.h
+++ b/include/asm-arm/mach/map.h
@@ -27,9 +27,6 @@ struct meminfo;
 #define MT_ROM                  6
 #define MT_IXP2000_DEVICE       7
-#define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
-#define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
 extern void create_memmap_holes(struct meminfo *);
 extern void memtable_init(struct meminfo *);
 extern void iotable_init(struct map_desc *, int);
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 3e572364ee73..3d7f08bd9030 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -58,6 +58,12 @@
 #endif
 /*
+ * Convert a physical address to a Page Frame Number and back
+ */
+#define __phys_to_pfn(paddr)    ((paddr) >> PAGE_SHIFT)
+#define __pfn_to_phys(pfn)      ((pfn) << PAGE_SHIFT)
+/*
 * The module space lives between the addresses given by TASK_SIZE
 * and PAGE_OFFSET - it must be within 32MB of the kernel text.
 */
author	Linus Torvalds <torvalds@g5.osdl.org>	2006-01-09 18:09:30 -0500
committer	Linus Torvalds <torvalds@g5.osdl.org>	2006-01-09 18:09:30 -0500
commit	3995f4c5327595b51482bdac8c189736262eb6e0 (patch)
tree	ef768d0ecf243a2376bfc646b847964313146d3e
parent	05814450070f13b671fc9dbf89477677aa0258cb (diff)
parent	fe38ea5623d262afc0b92ea47b8a7d8c988521d2 (diff)