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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-10 17:48:43 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-10 17:48:43 -0400
commit0f166396e7e8931bb4acfd1a6ea1bd4f0b43f1dd (patch)
tree6279fa70695a4c56b7e935018a4c0fc1dfa82e68
parent5f60cfd932b42c69ed3226400cb5eab152576c3a (diff)
parent105b1bca4d7bed85bb296f7e7caec2fc643e9fbf (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (62 commits) [MIPS] PNX8550: Cleanup proc code. [MIPS] WRPPMC: Fix build. [MIPS] Yosemite: Fix modpost warnings. [MIPS] Change names of local variables to silence sparse [MIPS] SB1: Fix modpost warning. [MIPS] PNX: Fix modpost warnings. [MIPS] Alchemy: Fix modpost warnings. [MIPS] Non-FPAFF: Fix warning. [MIPS] DEC: Fix modpost warning. [MIPS] MIPSsim: Enable MIPSsim virtual network driver. [MIPS] Delete Ocelot 3 support. [MIPS] remove LASAT Networks platforms support [MIPS] Early check for SMTC kernel on non-MT processor [MIPS] Add debugfs files to show fpuemu statistics [MIPS] Add some debugfs files to debug unaligned accesses [MIPS] rbtx4938: Fix secondary PCIC and glue internal NICs [MIPS] tc35815: Load MAC address via platform_device [MIPS] Move FPU affinity code into separate file. [MIPS] Make ioremap() work on TX39/49 special unmapped segment [MIPS] rbtx4938: Update and minimize defconfig ...
Diffstat
-rw-r--r--arch/mips/Kconfig198
-rw-r--r--arch/mips/Makefile84
-rw-r--r--arch/mips/au1000/common/gpio.c124
-rw-r--r--arch/mips/au1000/common/platform.c2
-rw-r--r--arch/mips/configs/atlas_defconfig4
-rw-r--r--arch/mips/configs/bigsur_defconfig4
-rw-r--r--arch/mips/configs/capcella_defconfig4
-rw-r--r--arch/mips/configs/cobalt_defconfig502
-rw-r--r--arch/mips/configs/db1000_defconfig4
-rw-r--r--arch/mips/configs/db1100_defconfig4
-rw-r--r--arch/mips/configs/db1200_defconfig4
-rw-r--r--arch/mips/configs/db1500_defconfig4
-rw-r--r--arch/mips/configs/db1550_defconfig4
-rw-r--r--arch/mips/configs/ddb5477_defconfig4
-rw-r--r--arch/mips/configs/decstation_defconfig4
-rw-r--r--arch/mips/configs/e55_defconfig4
-rw-r--r--arch/mips/configs/emma2rh_defconfig4
-rw-r--r--arch/mips/configs/ev64120_defconfig985
-rw-r--r--arch/mips/configs/excite_defconfig4
-rw-r--r--arch/mips/configs/fulong_defconfig1765
-rw-r--r--arch/mips/configs/ip22_defconfig4
-rw-r--r--arch/mips/configs/ip27_defconfig4
-rw-r--r--arch/mips/configs/ip32_defconfig4
-rw-r--r--arch/mips/configs/jazz_defconfig4
-rw-r--r--arch/mips/configs/jmr3927_defconfig4
-rw-r--r--arch/mips/configs/lasat200_defconfig1118
-rw-r--r--arch/mips/configs/malta_defconfig4
-rw-r--r--arch/mips/configs/mipssim_defconfig37
-rw-r--r--arch/mips/configs/mpc30x_defconfig4
-rw-r--r--arch/mips/configs/msp71xx_defconfig (renamed from arch/mips/configs/ocelot_3_defconfig)972
-rw-r--r--arch/mips/configs/ocelot_c_defconfig982
-rw-r--r--arch/mips/configs/ocelot_defconfig4
-rw-r--r--arch/mips/configs/pb1100_defconfig4
-rw-r--r--arch/mips/configs/pb1500_defconfig4
-rw-r--r--arch/mips/configs/pb1550_defconfig4
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig4
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig4
-rw-r--r--arch/mips/configs/qemu_defconfig4
-rw-r--r--arch/mips/configs/rbhma4200_defconfig4
-rw-r--r--arch/mips/configs/rbhma4500_defconfig945
-rw-r--r--arch/mips/configs/rm200_defconfig4
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig4
-rw-r--r--arch/mips/configs/sead_defconfig4
-rw-r--r--arch/mips/configs/tb0219_defconfig4
-rw-r--r--arch/mips/configs/tb0226_defconfig4
-rw-r--r--arch/mips/configs/tb0287_defconfig4
-rw-r--r--arch/mips/configs/workpad_defconfig4
-rw-r--r--arch/mips/configs/wrppmc_defconfig4
-rw-r--r--arch/mips/configs/yosemite_defconfig4
-rw-r--r--arch/mips/ddb5xxx/ddb5477/Makefile3
-rw-r--r--arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c49
-rw-r--r--arch/mips/dec/prom/console.c32
-rw-r--r--arch/mips/dec/prom/init.c5
-rw-r--r--arch/mips/dec/reset.c10
-rw-r--r--arch/mips/defconfig4
-rw-r--r--arch/mips/gt64120/ev64120/Kconfig3
-rw-r--r--arch/mips/gt64120/ev64120/Makefile9
-rw-r--r--arch/mips/gt64120/ev64120/irq.c116
-rw-r--r--arch/mips/gt64120/ev64120/promcon.c48
-rw-r--r--arch/mips/gt64120/ev64120/reset.c45
-rw-r--r--arch/mips/gt64120/ev64120/serialGT.c212
-rw-r--r--arch/mips/gt64120/ev64120/setup.c99
-rw-r--r--arch/mips/gt64120/momenco_ocelot/Makefile2
-rw-r--r--arch/mips/gt64120/momenco_ocelot/ocelot-platform.c46
-rw-r--r--arch/mips/gt64120/wrppmc/setup.c4
-rw-r--r--arch/mips/jazz/Makefile2
-rw-r--r--arch/mips/jazz/jazz-platform.c60
-rw-r--r--arch/mips/kernel/8250-platform.c47
-rw-r--r--arch/mips/kernel/Makefile17
-rw-r--r--arch/mips/kernel/cpu-probe.c30
-rw-r--r--arch/mips/kernel/head.S10
-rw-r--r--arch/mips/kernel/irq-mv6434x.c111
-rw-r--r--arch/mips/kernel/mips-mt-fpaff.c176
-rw-r--r--arch/mips/kernel/mips-mt.c205
-rw-r--r--arch/mips/kernel/proc.c2
-rw-r--r--arch/mips/kernel/process.c4
-rw-r--r--arch/mips/kernel/setup.c16
-rw-r--r--arch/mips/kernel/smp.c2
-rw-r--r--arch/mips/kernel/smtc.c2
-rw-r--r--arch/mips/kernel/syscall.c5
-rw-r--r--arch/mips/kernel/traps.c77
-rw-r--r--arch/mips/kernel/unaligned.c41
-rw-r--r--arch/mips/lasat/Kconfig15
-rw-r--r--arch/mips/lasat/Makefile14
-rw-r--r--arch/mips/lasat/at93c.c148
-rw-r--r--arch/mips/lasat/at93c.h18
-rw-r--r--arch/mips/lasat/ds1603.c183
-rw-r--r--arch/mips/lasat/ds1603.h33
-rw-r--r--arch/mips/lasat/image/Makefile53
-rw-r--r--arch/mips/lasat/image/head.S31
-rw-r--r--arch/mips/lasat/image/romscript.normal23
-rw-r--r--arch/mips/lasat/interrupt.c130
-rw-r--r--arch/mips/lasat/lasat_board.c279
-rw-r--r--arch/mips/lasat/lasat_models.h63
-rw-r--r--arch/mips/lasat/picvue.c240
-rw-r--r--arch/mips/lasat/picvue.h48
-rw-r--r--arch/mips/lasat/picvue_proc.c186
-rw-r--r--arch/mips/lasat/prom.c117
-rw-r--r--arch/mips/lasat/prom.h5
-rw-r--r--arch/mips/lasat/reset.c69
-rw-r--r--arch/mips/lasat/setup.c182
-rw-r--r--arch/mips/lasat/sysctl.c441
-rw-r--r--arch/mips/lasat/sysctl.h24
-rw-r--r--arch/mips/lemote/lm2e/Makefile7
-rw-r--r--arch/mips/lemote/lm2e/bonito-irq.c74
-rw-r--r--arch/mips/lemote/lm2e/dbg_io.c146
-rw-r--r--arch/mips/lemote/lm2e/irq.c145
-rw-r--r--arch/mips/lemote/lm2e/mem.c23
-rw-r--r--arch/mips/lemote/lm2e/pci.c93
-rw-r--r--arch/mips/lemote/lm2e/prom.c104
-rw-r--r--arch/mips/lemote/lm2e/reset.c41
-rw-r--r--arch/mips/lemote/lm2e/setup.c134
-rw-r--r--arch/mips/lib-32/Makefile23
-rw-r--r--arch/mips/lib-32/dump_tlb.c242
-rw-r--r--arch/mips/lib-32/r3k_dump_tlb.c182
-rw-r--r--arch/mips/lib-32/watch.S60
-rw-r--r--arch/mips/lib-64/Makefile23
-rw-r--r--arch/mips/lib-64/dump_tlb.c216
-rw-r--r--arch/mips/lib-64/watch.S57
-rw-r--r--arch/mips/lib/Makefile19
-rw-r--r--arch/mips/lib/dump_tlb.c100
-rw-r--r--arch/mips/lib/r3k_dump_tlb.c62
-rw-r--r--arch/mips/math-emu/cp1emu.c34
-rw-r--r--arch/mips/mips-boards/malta/Makefile3
-rw-r--r--arch/mips/mips-boards/malta/malta_platform.c65
-rw-r--r--arch/mips/mipssim/Makefile (renamed from arch/mips/mips-boards/sim/Makefile)0
-rw-r--r--arch/mips/mipssim/sim_cmdline.c (renamed from arch/mips/mips-boards/sim/sim_cmdline.c)0
-rw-r--r--arch/mips/mipssim/sim_console.c (renamed from arch/mips/mips-boards/sim/sim_console.c)2
-rw-r--r--arch/mips/mipssim/sim_int.c88
-rw-r--r--arch/mips/mipssim/sim_mem.c (renamed from arch/mips/mips-boards/sim/sim_mem.c)2
-rw-r--r--arch/mips/mipssim/sim_platform.c (renamed from arch/mips/mips-boards/sim/sim_platform.c)0
-rw-r--r--arch/mips/mipssim/sim_setup.c (renamed from arch/mips/mips-boards/sim/sim_setup.c)8
-rw-r--r--arch/mips/mipssim/sim_smp.c (renamed from arch/mips/mips-boards/sim/sim_smp.c)18
-rw-r--r--arch/mips/mipssim/sim_time.c (renamed from arch/mips/mips-boards/sim/sim_time.c)30
-rw-r--r--arch/mips/mm/Makefile1
-rw-r--r--arch/mips/mm/c-r4k.c54
-rw-r--r--arch/mips/mm/c-sb1.c2
-rw-r--r--arch/mips/mm/cache.c10
-rw-r--r--arch/mips/mm/tlb-r4k.c23
-rw-r--r--arch/mips/mm/tlbex.c8
-rw-r--r--arch/mips/momentum/ocelot_3/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_3/irq.c109
-rw-r--r--arch/mips/momentum/ocelot_3/platform.c208
-rw-r--r--arch/mips/momentum/ocelot_3/prom.c189
-rw-r--r--arch/mips/momentum/ocelot_3/reset.c59
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c398
-rw-r--r--arch/mips/momentum/ocelot_c/Makefile8
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c100
-rw-r--r--arch/mips/momentum/ocelot_c/dbg_io.c121
-rw-r--r--arch/mips/momentum/ocelot_c/irq.c107
-rw-r--r--arch/mips/momentum/ocelot_c/platform.c183
-rw-r--r--arch/mips/momentum/ocelot_c/prom.c183
-rw-r--r--arch/mips/momentum/ocelot_c/reset.c58
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c362
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c91
-rw-r--r--arch/mips/pci/Makefile10
-rw-r--r--arch/mips/pci/fixup-atlas.c2
-rw-r--r--arch/mips/pci/fixup-au1000.c2
-rw-r--r--arch/mips/pci/fixup-capcella.c2
-rw-r--r--arch/mips/pci/fixup-cobalt.c2
-rw-r--r--arch/mips/pci/fixup-emma2rh.c2
-rw-r--r--arch/mips/pci/fixup-excite.c2
-rw-r--r--arch/mips/pci/fixup-ip32.c2
-rw-r--r--arch/mips/pci/fixup-jmr3927.c2
-rw-r--r--arch/mips/pci/fixup-lm2e.c242
-rw-r--r--arch/mips/pci/fixup-malta.c2
-rw-r--r--arch/mips/pci/fixup-mpc30x.c2
-rw-r--r--arch/mips/pci/fixup-ocelot-c.c41
-rw-r--r--arch/mips/pci/fixup-ocelot3.c41
-rw-r--r--arch/mips/pci/fixup-pmcmsp.c216
-rw-r--r--arch/mips/pci/fixup-pnx8550.c2
-rw-r--r--arch/mips/pci/fixup-rbtx4927.c2
-rw-r--r--arch/mips/pci/fixup-sni.c2
-rw-r--r--arch/mips/pci/fixup-tb0219.c2
-rw-r--r--arch/mips/pci/fixup-tb0226.c2
-rw-r--r--arch/mips/pci/fixup-tb0287.c2
-rw-r--r--arch/mips/pci/fixup-tx4938.c2
-rw-r--r--arch/mips/pci/fixup-vr4133.c2
-rw-r--r--arch/mips/pci/fixup-wrppmc.c2
-rw-r--r--arch/mips/pci/fixup-yosemite.c2
-rw-r--r--arch/mips/pci/ops-bonito64.c88
-rw-r--r--arch/mips/pci/ops-marvell.c93
-rw-r--r--arch/mips/pci/ops-nile4.c147
-rw-r--r--arch/mips/pci/ops-pmcmsp.c994
-rw-r--r--arch/mips/pci/ops-tx4938.c80
-rw-r--r--arch/mips/pci/pci-bcm1480.c3
-rw-r--r--arch/mips/pci/pci-ddb5477.c2
-rw-r--r--arch/mips/pci/pci-ev64120.c22
-rw-r--r--arch/mips/pci/pci-ip27.c2
-rw-r--r--arch/mips/pci/pci-lasat.c91
-rw-r--r--arch/mips/pci/pci-ocelot-c.c145
-rw-r--r--arch/mips/pci/pci-sb1250.c2
-rw-r--r--arch/mips/philips/pnx8550/common/platform.c2
-rw-r--r--arch/mips/philips/pnx8550/common/proc.c30
-rw-r--r--arch/mips/pmc-sierra/Kconfig46
-rw-r--r--arch/mips/pmc-sierra/msp71xx/Makefile11
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_elb.c (renamed from arch/mips/momentum/ocelot_c/ocelot_c_fpga.h)53
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c179
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq.c124
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c134
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c109
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_pci.c (renamed from arch/mips/momentum/ocelot_3/ocelot_3_fpga.h)57
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_prom.c566
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_setup.c256
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_time.c94
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_usb.c150
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-reset.c6
-rw-r--r--arch/mips/sgi-ip27/ip27-berr.c1
-rw-r--r--arch/mips/sgi-ip32/ip32-platform.c52
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c36
-rw-r--r--arch/mips/sibyte/cfe/setup.c6
-rw-r--r--arch/mips/sni/Makefile2
-rw-r--r--arch/mips/sni/a20r.c31
-rw-r--r--arch/mips/sni/ds1216.c81
-rw-r--r--arch/mips/sni/pcimt.c26
-rw-r--r--arch/mips/sni/pcit.c26
-rw-r--r--arch/mips/sni/rm200.c32
-rw-r--r--arch/mips/sni/sniprom.c5
-rw-r--r--arch/mips/tx4938/common/Makefile2
-rw-r--r--arch/mips/tx4938/common/rtc_rx5c348.c192
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/Makefile2
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c6
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c306
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c261
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c164
-rw-r--r--drivers/char/mem.c7
-rw-r--r--drivers/mtd/devices/docprobe.c2
-rw-r--r--drivers/mtd/maps/Kconfig6
-rw-r--r--drivers/mtd/maps/Makefile1
-rw-r--r--drivers/mtd/maps/lasat.c103
-rw-r--r--drivers/mtd/nand/diskonchip.c2
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/tc35815.c50
-rw-r--r--drivers/tc/zs.c6
-rw-r--r--include/asm-mips/addrspace.h29
-rw-r--r--include/asm-mips/bootinfo.h36
-rw-r--r--include/asm-mips/cacheops.h4
-rw-r--r--include/asm-mips/cpu-features.h4
-rw-r--r--include/asm-mips/cpu.h10
-rw-r--r--include/asm-mips/div64.h9
-rw-r--r--include/asm-mips/gpio.h6
-rw-r--r--include/asm-mips/io.h8
-rw-r--r--include/asm-mips/lasat/ds1603.h18
-rw-r--r--include/asm-mips/lasat/eeprom.h17
-rw-r--r--include/asm-mips/lasat/head.h22
-rw-r--r--include/asm-mips/lasat/lasat.h253
-rw-r--r--include/asm-mips/lasat/lasatint.h12
-rw-r--r--include/asm-mips/lasat/picvue.h15
-rw-r--r--include/asm-mips/lasat/serial.h13
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_gpio.h20
-rw-r--r--include/asm-mips/mach-au1x00/gpio.h69
-rw-r--r--include/asm-mips/mach-au1x00/ioremap.h11
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h5
-rw-r--r--include/asm-mips/mach-ev64120/mach-gt64120.h62
-rw-r--r--include/asm-mips/mach-generic/gpio.h15
-rw-r--r--include/asm-mips/mach-generic/ioremap.h11
-rw-r--r--include/asm-mips/mach-generic/spaces.h64
-rw-r--r--include/asm-mips/mach-ip22/spaces.h33
-rw-r--r--include/asm-mips/mach-ip27/spaces.h9
-rw-r--r--include/asm-mips/mach-ip32/spaces.h36
-rw-r--r--include/asm-mips/mach-jmr3927/ioremap.h38
-rw-r--r--include/asm-mips/mach-lasat/mach-gt64120.h27
-rw-r--r--include/asm-mips/mach-lemote/dma-coherence.h42
-rw-r--r--include/asm-mips/mach-lemote/mc146818rtc.h36
-rw-r--r--include/asm-mips/mach-mips/kernel-entry-init.h52
-rw-r--r--include/asm-mips/mach-mipssim/cpu-feature-overrides.h (renamed from include/asm-mips/mach-sim/cpu-feature-overrides.h)0
-rw-r--r--include/asm-mips/mach-ocelot3/cpu-feature-overrides.h48
-rw-r--r--include/asm-mips/mach-tx49xx/ioremap.h42
-rw-r--r--include/asm-mips/mips-boards/bonito64.h7
-rw-r--r--include/asm-mips/mipsregs.h39
-rw-r--r--include/asm-mips/module.h2
-rw-r--r--include/asm-mips/nile4.h310
-rw-r--r--include/asm-mips/page.h21
-rw-r--r--include/asm-mips/pci.h2
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h151
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_int.h43
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_pci.h205
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_prom.h176
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_regops.h236
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_regs.h667
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h141
-rw-r--r--include/asm-mips/processor.h92
-rw-r--r--include/asm-mips/serial.h155
-rw-r--r--include/asm-mips/smp.h7
-rw-r--r--include/asm-mips/sni.h3
-rw-r--r--include/asm-mips/system.h14
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h6
-rw-r--r--include/asm-mips/tx4938/spi.h56
-rw-r--r--include/asm-mips/war.h25
-rw-r--r--include/asm-mips/watch.h35
-rw-r--r--include/linux/mv643xx.h4
292 files changed, 10760 insertions, 14142 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 73455389257a..a00fabe2e4e0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -15,6 +15,29 @@ choice
15 prompt "System type" 15 prompt "System type"
16 default SGI_IP22 16 default SGI_IP22
17 17
18config LEMOTE_FULONG
19 bool "Lemote Fulong mini-PC"
20 select ARCH_SPARSEMEM_ENABLE
21 select SYS_HAS_CPU_LOONGSON2
22 select DMA_NONCOHERENT
23 select BOOT_ELF32
24 select BOARD_SCACHE
25 select HAVE_STD_PC_SERIAL_PORT
26 select HW_HAS_PCI
27 select I8259
28 select ISA
29 select IRQ_CPU
30 select SYS_SUPPORTS_32BIT_KERNEL
31 select SYS_SUPPORTS_64BIT_KERNEL
32 select SYS_SUPPORTS_LITTLE_ENDIAN
33 select SYS_SUPPORTS_HIGHMEM
34 select SYS_HAS_EARLY_PRINTK
35 select GENERIC_HARDIRQS_NO__DO_IRQ
36 select CPU_HAS_WB
37 help
38 Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
39 an FPGA northbridge
40
18config MACH_ALCHEMY 41config MACH_ALCHEMY
19 bool "Alchemy processor based machines" 42 bool "Alchemy processor based machines"
20 43
@@ -63,7 +86,7 @@ config MACH_DECSTATION
63 bool "DECstations" 86 bool "DECstations"
64 select BOOT_ELF32 87 select BOOT_ELF32
65 select DMA_NONCOHERENT 88 select DMA_NONCOHERENT
66 select SYS_HAS_EARLY_PRINTK 89 select NO_IOPORT
67 select IRQ_CPU 90 select IRQ_CPU
68 select SYS_HAS_CPU_R3000 91 select SYS_HAS_CPU_R3000
69 select SYS_HAS_CPU_R4X00 92 select SYS_HAS_CPU_R4X00
@@ -88,24 +111,6 @@ config MACH_DECSTATION
88 111
89 otherwise choose R3000. 112 otherwise choose R3000.
90 113
91config MIPS_EV64120
92 bool "Galileo EV64120 Evaluation board (EXPERIMENTAL)"
93 depends on EXPERIMENTAL
94 select DMA_NONCOHERENT
95 select HW_HAS_PCI
96 select PCI_GT64XXX_PCI0
97 select SYS_HAS_CPU_R5000
98 select SYS_SUPPORTS_32BIT_KERNEL
99 select SYS_SUPPORTS_64BIT_KERNEL
100 select SYS_SUPPORTS_BIG_ENDIAN
101 select SYS_SUPPORTS_KGDB
102 help
103 This is an evaluation board based on the Galileo GT-64120
104 single-chip system controller that contains a MIPS R5000 compatible
105 core running at 75/100MHz. Their website is located at
106 <http://www.marvell.com/>. Say Y here if you wish to build a
107 kernel for this platform.
108
109config MACH_JAZZ 114config MACH_JAZZ
110 bool "Jazz family of machines" 115 bool "Jazz family of machines"
111 select ARC 116 select ARC
@@ -126,20 +131,6 @@ config MACH_JAZZ
126 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and 131 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
127 Olivetti M700-10 workstations. 132 Olivetti M700-10 workstations.
128 133
129config LASAT
130 bool "LASAT Networks platforms"
131 select DMA_NONCOHERENT
132 select SYS_HAS_EARLY_PRINTK
133 select HW_HAS_PCI
134 select PCI_GT64XXX_PCI0
135 select MIPS_NILE4
136 select R5000_CPU_SCACHE
137 select SYS_HAS_CPU_R5000
138 select SYS_SUPPORTS_32BIT_KERNEL
139 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
140 select SYS_SUPPORTS_LITTLE_ENDIAN
141 select GENERIC_HARDIRQS_NO__DO_IRQ
142
143config MIPS_ATLAS 134config MIPS_ATLAS
144 bool "MIPS Atlas board" 135 bool "MIPS Atlas board"
145 select BOOT_ELF32 136 select BOOT_ELF32
@@ -173,7 +164,6 @@ config MIPS_MALTA
173 bool "MIPS Malta board" 164 bool "MIPS Malta board"
174 select ARCH_MAY_HAVE_PC_FDC 165 select ARCH_MAY_HAVE_PC_FDC
175 select BOOT_ELF32 166 select BOOT_ELF32
176 select HAVE_STD_PC_SERIAL_PORT
177 select DMA_NONCOHERENT 167 select DMA_NONCOHERENT
178 select GENERIC_ISA_DMA 168 select GENERIC_ISA_DMA
179 select IRQ_CPU 169 select IRQ_CPU
@@ -246,11 +236,13 @@ config MIPS_SIM
246 select DMA_NONCOHERENT 236 select DMA_NONCOHERENT
247 select SYS_HAS_EARLY_PRINTK 237 select SYS_HAS_EARLY_PRINTK
248 select IRQ_CPU 238 select IRQ_CPU
239 select BOOT_RAW
249 select SYS_HAS_CPU_MIPS32_R1 240 select SYS_HAS_CPU_MIPS32_R1
250 select SYS_HAS_CPU_MIPS32_R2 241 select SYS_HAS_CPU_MIPS32_R2
251 select SYS_HAS_EARLY_PRINTK 242 select SYS_HAS_EARLY_PRINTK
252 select SYS_SUPPORTS_32BIT_KERNEL 243 select SYS_SUPPORTS_32BIT_KERNEL
253 select SYS_SUPPORTS_BIG_ENDIAN 244 select SYS_SUPPORTS_BIG_ENDIAN
245 select SYS_SUPPORTS_MULTITHREADING
254 select SYS_SUPPORTS_LITTLE_ENDIAN 246 select SYS_SUPPORTS_LITTLE_ENDIAN
255 help 247 help
256 This option enables support for MIPS Technologies MIPSsim software 248 This option enables support for MIPS Technologies MIPSsim software
@@ -274,43 +266,6 @@ config MOMENCO_OCELOT
274 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 266 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
275 Momentum Computer <http://www.momenco.com/>. 267 Momentum Computer <http://www.momenco.com/>.
276 268
277config MOMENCO_OCELOT_3
278 bool "Momentum Ocelot-3 board"
279 select BOOT_ELF32
280 select DMA_NONCOHERENT
281 select HW_HAS_PCI
282 select IRQ_CPU
283 select IRQ_CPU_RM7K
284 select IRQ_MV64340
285 select PCI_MARVELL
286 select RM7000_CPU_SCACHE
287 select SWAP_IO_SPACE
288 select SYS_HAS_CPU_RM9000
289 select SYS_SUPPORTS_32BIT_KERNEL
290 select SYS_SUPPORTS_64BIT_KERNEL
291 select SYS_SUPPORTS_BIG_ENDIAN
292 help
293 The Ocelot-3 is based off Discovery III System Controller and
294 PMC-Sierra Rm79000 core.
295
296config MOMENCO_OCELOT_C
297 bool "Momentum Ocelot-C board"
298 select DMA_NONCOHERENT
299 select HW_HAS_PCI
300 select IRQ_CPU
301 select IRQ_MV64340
302 select PCI_MARVELL
303 select RM7000_CPU_SCACHE
304 select SWAP_IO_SPACE
305 select SYS_HAS_CPU_RM7000
306 select SYS_SUPPORTS_32BIT_KERNEL
307 select SYS_SUPPORTS_64BIT_KERNEL
308 select SYS_SUPPORTS_BIG_ENDIAN
309 select GENERIC_HARDIRQS_NO__DO_IRQ
310 help
311 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
312 Momentum Computer <http://www.momenco.com/>.
313
314config PNX8550_JBS 269config PNX8550_JBS
315 bool "Philips PNX8550 based JBS board" 270 bool "Philips PNX8550 based JBS board"
316 select PNX8550 271 select PNX8550
@@ -346,6 +301,27 @@ config MACH_VR41XX
346 select SYS_HAS_CPU_VR41XX 301 select SYS_HAS_CPU_VR41XX
347 select GENERIC_HARDIRQS_NO__DO_IRQ 302 select GENERIC_HARDIRQS_NO__DO_IRQ
348 303
304config PMC_MSP
305 bool "PMC-Sierra MSP chipsets"
306 depends on EXPERIMENTAL
307 select DMA_NONCOHERENT
308 select SWAP_IO_SPACE
309 select NO_EXCEPT_FILL
310 select BOOT_RAW
311 select SYS_HAS_CPU_MIPS32_R1
312 select SYS_HAS_CPU_MIPS32_R2
313 select SYS_SUPPORTS_32BIT_KERNEL
314 select SYS_SUPPORTS_BIG_ENDIAN
315 select SYS_SUPPORTS_KGDB
316 select IRQ_CPU
317 select SERIAL_8250
318 select SERIAL_8250_CONSOLE
319 help
320 This adds support for the PMC-Sierra family of Multi-Service
321 Processor System-On-A-Chips. These parts include a number
322 of integrated peripherals, interfaces and DSPs in addition to
323 a variety of MIPS cores.
324
349config PMC_YOSEMITE 325config PMC_YOSEMITE
350 bool "PMC-Sierra Yosemite eval board" 326 bool "PMC-Sierra Yosemite eval board"
351 select DMA_COHERENT 327 select DMA_COHERENT
@@ -450,8 +426,7 @@ config SGI_IP27
450 here. 426 here.
451 427
452config SGI_IP32 428config SGI_IP32
453 bool "SGI IP32 (O2) (EXPERIMENTAL)" 429 bool "SGI IP32 (O2)"
454 depends on EXPERIMENTAL
455 select ARC 430 select ARC
456 select ARC32 431 select ARC32
457 select BOOT_ELF32 432 select BOOT_ELF32
@@ -652,6 +627,7 @@ config TOSHIBA_RBTX4938
652 select SYS_SUPPORTS_BIG_ENDIAN 627 select SYS_SUPPORTS_BIG_ENDIAN
653 select SYS_SUPPORTS_KGDB 628 select SYS_SUPPORTS_KGDB
654 select GENERIC_HARDIRQS_NO__DO_IRQ 629 select GENERIC_HARDIRQS_NO__DO_IRQ
630 select GENERIC_GPIO
655 help 631 help
656 This Toshiba board is based on the TX4938 processor. Say Y here to 632 This Toshiba board is based on the TX4938 processor. Say Y here to
657 support this machine type 633 support this machine type
@@ -660,9 +636,7 @@ endchoice
660 636
661source "arch/mips/au1000/Kconfig" 637source "arch/mips/au1000/Kconfig"
662source "arch/mips/ddb5xxx/Kconfig" 638source "arch/mips/ddb5xxx/Kconfig"
663source "arch/mips/gt64120/ev64120/Kconfig"
664source "arch/mips/jazz/Kconfig" 639source "arch/mips/jazz/Kconfig"
665source "arch/mips/lasat/Kconfig"
666source "arch/mips/pmc-sierra/Kconfig" 640source "arch/mips/pmc-sierra/Kconfig"
667source "arch/mips/sgi-ip27/Kconfig" 641source "arch/mips/sgi-ip27/Kconfig"
668source "arch/mips/sibyte/Kconfig" 642source "arch/mips/sibyte/Kconfig"
@@ -721,6 +695,9 @@ config ARC
721config ARCH_MAY_HAVE_PC_FDC 695config ARCH_MAY_HAVE_PC_FDC
722 bool 696 bool
723 697
698config BOOT_RAW
699 bool
700
724config DMA_COHERENT 701config DMA_COHERENT
725 bool 702 bool
726 703
@@ -768,16 +745,19 @@ config MIPS_BONITO64
768config MIPS_MSC 745config MIPS_MSC
769 bool 746 bool
770 747
771config MIPS_NILE4
772 bool
773
774config MIPS_DISABLE_OBSOLETE_IDE 748config MIPS_DISABLE_OBSOLETE_IDE
775 bool 749 bool
776 750
751config NO_IOPORT
752 def_bool n
753
777config GENERIC_ISA_DMA_SUPPORT_BROKEN 754config GENERIC_ISA_DMA_SUPPORT_BROKEN
778 bool 755 bool
779 select ZONE_DMA 756 select ZONE_DMA
780 757
758config GENERIC_GPIO
759 bool
760
781# 761#
782# Endianess selection. Sufficiently obscure so many users don't know what to 762# Endianess selection. Sufficiently obscure so many users don't know what to
783# answer,so we try hard to limit the available choices. Also the use of a 763# answer,so we try hard to limit the available choices. Also the use of a
@@ -821,7 +801,10 @@ config IRQ_CPU_RM7K
821config IRQ_CPU_RM9K 801config IRQ_CPU_RM9K
822 bool 802 bool
823 803
824config IRQ_MV64340 804config IRQ_MSP_SLP
805 bool
806
807config IRQ_MSP_CIC
825 bool 808 bool
826 809
827config DDB5XXX_COMMON 810config DDB5XXX_COMMON
@@ -834,6 +817,9 @@ config MIPS_BOARDS_GEN
834config PCI_GT64XXX_PCI0 817config PCI_GT64XXX_PCI0
835 bool 818 bool
836 819
820config NO_EXCEPT_FILL
821 bool
822
837config MIPS_TX3927 823config MIPS_TX3927
838 bool 824 bool
839 select HAS_TXX9_SERIAL 825 select HAS_TXX9_SERIAL
@@ -841,14 +827,6 @@ config MIPS_TX3927
841config MIPS_RM9122 827config MIPS_RM9122
842 bool 828 bool
843 select SERIAL_RM9000 829 select SERIAL_RM9000
844 select GPI_RM9000
845 select WDT_RM9000
846
847config PCI_MARVELL
848 bool
849
850config SERIAL_RM9000
851 bool
852 830
853config PNX8550 831config PNX8550
854 bool 832 bool
@@ -863,6 +841,7 @@ config SOC_PNX8550
863 select SYS_SUPPORTS_32BIT_KERNEL 841 select SYS_SUPPORTS_32BIT_KERNEL
864 select GENERIC_HARDIRQS_NO__DO_IRQ 842 select GENERIC_HARDIRQS_NO__DO_IRQ
865 select SYS_SUPPORTS_KGDB 843 select SYS_SUPPORTS_KGDB
844 select GENERIC_GPIO
866 845
867config SWAP_IO_SPACE 846config SWAP_IO_SPACE
868 bool 847 bool
@@ -875,31 +854,17 @@ config EMMA2RH
875config SERIAL_RM9000 854config SERIAL_RM9000
876 bool 855 bool
877 856
878config GPI_RM9000
879 bool
880
881config WDT_RM9000
882 bool
883
884# 857#
885# Unfortunately not all GT64120 systems run the chip at the same clock. 858# Unfortunately not all GT64120 systems run the chip at the same clock.
886# As the user for the clock rate and try to minimize the available options. 859# As the user for the clock rate and try to minimize the available options.
887# 860#
888choice 861choice
889 prompt "Galileo Chip Clock" 862 prompt "Galileo Chip Clock"
890 #default SYSCLK_83 if MIPS_EV64120 863 depends on MOMENCO_OCELOT
891 depends on MIPS_EV64120 || MOMENCO_OCELOT
892 default SYSCLK_83 if MIPS_EV64120
893 default SYSCLK_100 if MOMENCO_OCELOT 864 default SYSCLK_100 if MOMENCO_OCELOT
894 865
895config SYSCLK_75
896 bool "75" if MIPS_EV64120
897
898config SYSCLK_83
899 bool "83.3" if MIPS_EV64120
900
901config SYSCLK_100 866config SYSCLK_100
902 bool "100" if MIPS_EV64120 || MOMENCO_OCELOT 867 bool "100" if MOMENCO_OCELOT
903 868
904endchoice 869endchoice
905 870
@@ -911,8 +876,9 @@ config BOOT_ELF32
911 876
912config MIPS_L1_CACHE_SHIFT 877config MIPS_L1_CACHE_SHIFT
913 int 878 int
914 default "4" if MACH_DECSTATION || SNI_RM 879 default "4" if MACH_DECSTATION
915 default "7" if SGI_IP27 880 default "7" if SGI_IP27 || SNI_RM
881 default "4" if PMC_MSP4200_EVAL
916 default "5" 882 default "5"
917 883
918config HAVE_STD_PC_SERIAL_PORT 884config HAVE_STD_PC_SERIAL_PORT
@@ -944,6 +910,16 @@ choice
944 prompt "CPU type" 910 prompt "CPU type"
945 default CPU_R4X00 911 default CPU_R4X00
946 912
913config CPU_LOONGSON2
914 bool "Loongson 2"
915 depends on SYS_HAS_CPU_LOONGSON2
916 select CPU_SUPPORTS_32BIT_KERNEL
917 select CPU_SUPPORTS_64BIT_KERNEL
918 select CPU_SUPPORTS_HIGHMEM
919 help
920 The Loongson 2E processor implements the MIPS III instruction set
921 with many extensions.
922
947config CPU_MIPS32_R1 923config CPU_MIPS32_R1
948 bool "MIPS32 Release 1" 924 bool "MIPS32 Release 1"
949 depends on SYS_HAS_CPU_MIPS32_R1 925 depends on SYS_HAS_CPU_MIPS32_R1
@@ -1154,6 +1130,9 @@ config CPU_SB1
1154 1130
1155endchoice 1131endchoice
1156 1132
1133config SYS_HAS_CPU_LOONGSON2
1134 bool
1135
1157config SYS_HAS_CPU_MIPS32_R1 1136config SYS_HAS_CPU_MIPS32_R1
1158 bool 1137 bool
1159 1138
@@ -1488,6 +1467,15 @@ config CPU_HAS_SMARTMIPS
1488config CPU_HAS_WB 1467config CPU_HAS_WB
1489 bool 1468 bool
1490 1469
1470config 64BIT_CONTEXT
1471 bool "Save 64bit integer registers"
1472 depends on 32BIT && CPU_LOONGSON2
1473 help
1474 Loongson2 CPU is 64bit , when used in 32BIT mode, its integer
1475 registers can still be accessed as 64bit, mainly for multimedia
1476 instructions. We must have all 64bit save/restored to make sure
1477 those instructions to get correct result.
1478
1491# 1479#
1492# Vectored interrupt mode is an R2 feature 1480# Vectored interrupt mode is an R2 feature
1493# 1481#
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index f450066b6241..20d19c9b7761 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -118,6 +118,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
118cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap 118cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
119cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap 119cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
120cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap 120cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
121cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap
121cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ 122cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
122 -Wa,-mips32 -Wa,--trap 123 -Wa,-mips32 -Wa,--trap
123cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ 124cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -283,14 +284,6 @@ load-$(CONFIG_MACH_DECSTATION) += 0xffffffff80040000
283CLEAN_FILES += drivers/tc/lk201-map.c 284CLEAN_FILES += drivers/tc/lk201-map.c
284 285
285# 286#
286# Galileo EV64120 Board
287#
288core-$(CONFIG_MIPS_EV64120) += arch/mips/gt64120/ev64120/
289core-$(CONFIG_MIPS_EV64120) += arch/mips/gt64120/common/
290cflags-$(CONFIG_MIPS_EV64120) += -Iinclude/asm-mips/mach-ev64120
291load-$(CONFIG_MIPS_EV64120) += 0xffffffff80100000
292
293#
294# Wind River PPMC Board (4KC + GT64120) 287# Wind River PPMC Board (4KC + GT64120)
295# 288#
296core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/ 289core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/
@@ -298,6 +291,13 @@ cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc
298load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 291load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
299 292
300# 293#
294# lemote fulong mini-PC board
295#
296core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/
297load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000
298cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote
299
300#
301# For all MIPS, Inc. eval boards 301# For all MIPS, Inc. eval boards
302# 302#
303core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ 303core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/
@@ -327,7 +327,7 @@ load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000
327# 327#
328# MIPS SIM 328# MIPS SIM
329# 329#
330core-$(CONFIG_MIPS_SIM) += arch/mips/mips-boards/sim/ 330core-$(CONFIG_MIPS_SIM) += arch/mips/mipssim/
331cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-sim 331cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-sim
332load-$(CONFIG_MIPS_SIM) += 0x80100000 332load-$(CONFIG_MIPS_SIM) += 0x80100000
333 333
@@ -343,12 +343,12 @@ cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot
343load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000 343load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000
344 344
345# 345#
346# Momentum Ocelot-C and -CS boards 346# PMC-Sierra MSP SOCs
347# 347#
348# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the 348core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/
349# mips_io_port_base. 349cflags-$(CONFIG_PMC_MSP) += -Iinclude/asm-mips/pmc-sierra/msp71xx \
350core-$(CONFIG_MOMENCO_OCELOT_C) += arch/mips/momentum/ocelot_c/ 350 -mno-branch-likely
351load-$(CONFIG_MOMENCO_OCELOT_C) += 0xffffffff80100000 351load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
352 352
353# 353#
354# PMC-Sierra Yosemite 354# PMC-Sierra Yosemite
@@ -365,13 +365,6 @@ cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu
365load-$(CONFIG_QEMU) += 0xffffffff80010000 365load-$(CONFIG_QEMU) += 0xffffffff80010000
366 366
367# 367#
368# Momentum Ocelot-3
369#
370core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/
371cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3
372load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000
373
374#
375# Basler eXcite 368# Basler eXcite
376# 369#
377core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/ 370core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
@@ -389,10 +382,6 @@ core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/
389core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/ 382core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/
390load-$(CONFIG_DDB5477) += 0xffffffff80100000 383load-$(CONFIG_DDB5477) += 0xffffffff80100000
391 384
392core-$(CONFIG_LASAT) += arch/mips/lasat/
393cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat
394load-$(CONFIG_LASAT) += 0xffffffff80000000
395
396# 385#
397# Common VR41xx 386# Common VR41xx
398# 387#
@@ -580,6 +569,7 @@ load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
580# 569#
581core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ 570core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/
582core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ 571core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/
572cflags-$(CONFIG_TOSHIBA_RBTX4927) += -Iinclude/asm-mips/mach-tx49xx
583load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 573load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000
584 574
585# 575#
@@ -587,6 +577,7 @@ load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000
587# 577#
588core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/ 578core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/
589core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/ 579core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/
580cflags-$(CONFIG_TOSHIBA_RBTX4938) += -Iinclude/asm-mips/mach-tx49xx
590load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000 581load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000
591 582
592cflags-y += -Iinclude/asm-mips/mach-generic 583cflags-y += -Iinclude/asm-mips/mach-generic
@@ -603,7 +594,8 @@ JIFFIES = jiffies_64
603endif 594endif
604 595
605AFLAGS += $(cflags-y) 596AFLAGS += $(cflags-y)
606CFLAGS += $(cflags-y) 597CFLAGS += $(cflags-y) \
598 -D"VMLINUX_LOAD_ADDRESS=$(load-y)"
607 599
608LDFLAGS += -m $(ld-emul) 600LDFLAGS += -m $(ld-emul)
609 601
@@ -633,18 +625,11 @@ CPPFLAGS_vmlinux.lds := \
633head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o 625head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o
634 626
635libs-y += arch/mips/lib/ 627libs-y += arch/mips/lib/
636libs-$(CONFIG_32BIT) += arch/mips/lib-32/
637libs-$(CONFIG_64BIT) += arch/mips/lib-64/
638 628
639core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ 629core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
640 630
641drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ 631drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
642 632
643ifdef CONFIG_LASAT
644rom.bin rom.sw: vmlinux
645 $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
646endif
647
648# 633#
649# Some machines like the Indy need 32-bit ELF binaries for booting purposes. 634# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
650# Other need ECOFF, so we build a 32-bit ELF binary for them which we then 635# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
@@ -702,32 +687,19 @@ vmlinux.srec: $(vmlinux-32)
702CLEAN_FILES += vmlinux.ecoff \ 687CLEAN_FILES += vmlinux.ecoff \
703 vmlinux.srec 688 vmlinux.srec
704 689
690archprepare:
691ifdef CONFIG_MIPS32_N32
692 @echo ' Checking missing-syscalls for N32'
693 $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=n32"
694endif
695ifdef CONFIG_MIPS32_O32
696 @echo ' Checking missing-syscalls for O32'
697 $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32"
698endif
699
705archclean: 700archclean:
706 @$(MAKE) $(clean)=arch/mips/boot 701 @$(MAKE) $(clean)=arch/mips/boot
707 @$(MAKE) $(clean)=arch/mips/lasat
708 702
709CLEAN_FILES += vmlinux.32 \ 703CLEAN_FILES += vmlinux.32 \
710 vmlinux.64 \ 704 vmlinux.64 \
711 vmlinux.ecoff 705 vmlinux.ecoff
712
713quiet_cmd_syscalls_n32 = CALL-N32 $<
714 cmd_syscalls_n32 = $(CONFIG_SHELL) $< $(CC) $(c_flags) -mabi=n32
715
716quiet_cmd_syscalls_o32 = CALL-O32 $<
717 cmd_syscalls_o32 = $(CONFIG_SHELL) $< $(CC) $(c_flags) -mabi=32
718
719PHONY += missing-syscalls-n32 missing-syscalls-o32
720
721missing-syscalls-n32: scripts/checksyscalls.sh FORCE
722 $(call cmd,syscalls_n32)
723
724missing-syscalls-o32: scripts/checksyscalls.sh FORCE
725 $(call cmd,syscalls_o32)
726
727archprepare:
728ifdef CONFIG_MIPS32_N32
729 $(Q)$(MAKE) $(build)=arch/mips missing-syscalls-n32
730endif
731ifdef CONFIG_MIPS32_O32
732 $(Q)$(MAKE) $(build)=arch/mips missing-syscalls-o32
733endif
diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/au1000/common/gpio.c
index ce55297dcb8c..7abe42099439 100644
--- a/arch/mips/au1000/common/gpio.c
+++ b/arch/mips/au1000/common/gpio.c
@@ -1,4 +1,7 @@
1/* 1/*
2 * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * Architecture specific GPIO support
4 *
2 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your 7 * Free Software Foundation; either version 2 of the License, or (at your
@@ -18,101 +21,136 @@
18 * You should have received a copy of the GNU General Public License along 21 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc., 22 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Notes :
26 * au1000 SoC have only one GPIO line : GPIO1
27 * others have a second one : GPIO2
21 */ 28 */
29
30#include <linux/autoconf.h>
31#include <linux/init.h>
32#include <linux/io.h>
33#include <linux/types.h>
22#include <linux/module.h> 34#include <linux/module.h>
23#include <au1000.h> 35
24#include <au1xxx_gpio.h> 36#include <asm/addrspace.h>
37
38#include <asm/mach-au1x00/au1000.h>
39#include <asm/gpio.h>
25 40
26#define gpio1 sys 41#define gpio1 sys
27#if !defined(CONFIG_SOC_AU1000) 42#if !defined(CONFIG_SOC_AU1000)
28static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE;
29 43
30#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 44static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;
45#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
31 46
32int au1xxx_gpio2_read(int signal) 47static int au1xxx_gpio2_read(unsigned gpio)
33{ 48{
34 signal -= 200; 49 gpio -= AU1XXX_GPIO_BASE;
35/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */ 50 return ((gpio2->pinstate >> gpio) & 0x01);
36 return ((gpio2->pinstate >> signal) & 0x01);
37} 51}
38 52
39void au1xxx_gpio2_write(int signal, int value) 53static void au1xxx_gpio2_write(unsigned gpio, int value)
40{ 54{
41 signal -= 200; 55 gpio -= AU1XXX_GPIO_BASE;
42 56
43 gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) | 57 gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | (value << gpio);
44 (value << signal);
45} 58}
46 59
47void au1xxx_gpio2_tristate(int signal) 60static int au1xxx_gpio2_direction_input(unsigned gpio)
48{ 61{
49 signal -= 200; 62 gpio -= AU1XXX_GPIO_BASE;
50 gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */ 63 gpio2->dir &= ~(0x01 << gpio);
64 return 0;
51} 65}
52#endif
53 66
54int au1xxx_gpio1_read(int signal) 67static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
68{
69 gpio -= AU1XXX_GPIO_BASE;
70 gpio2->dir = (0x01 << gpio) | (value << gpio);
71 return 0;
72}
73
74#endif /* !defined(CONFIG_SOC_AU1000) */
75
76static int au1xxx_gpio1_read(unsigned gpio)
55{ 77{
56/* gpio1->trioutclr |= (0x01 << signal); */ 78 return ((gpio1->pinstaterd >> gpio) & 0x01);
57 return ((gpio1->pinstaterd >> signal) & 0x01);
58} 79}
59 80
60void au1xxx_gpio1_write(int signal, int value) 81static void au1xxx_gpio1_write(unsigned gpio, int value)
61{ 82{
62 if(value) 83 if (value)
63 gpio1->outputset = (0x01 << signal); 84 gpio1->outputset = (0x01 << gpio);
64 else 85 else
65 gpio1->outputclr = (0x01 << signal); /* Output a Zero */ 86 /* Output a zero */
87 gpio1->outputclr = (0x01 << gpio);
66} 88}
67 89
68void au1xxx_gpio1_tristate(int signal) 90static int au1xxx_gpio1_direction_input(unsigned gpio)
69{ 91{
70 gpio1->trioutclr = (0x01 << signal); /* Tristate signal */ 92 gpio1->pininputen = (0x01 << gpio);
93 return 0;
71} 94}
72 95
96static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
97{
98 gpio1->trioutclr = (0x01 & gpio);
99 return 0;
100}
73 101
74int au1xxx_gpio_read(int signal) 102int au1xxx_gpio_get_value(unsigned gpio)
75{ 103{
76 if(signal >= 200) 104 if (gpio >= AU1XXX_GPIO_BASE)
77#if defined(CONFIG_SOC_AU1000) 105#if defined(CONFIG_SOC_AU1000)
78 return 0; 106 return 0;
79#else 107#else
80 return au1xxx_gpio2_read(signal); 108 return au1xxx_gpio2_read(gpio);
81#endif 109#endif
82 else 110 else
83 return au1xxx_gpio1_read(signal); 111 return au1xxx_gpio1_read(gpio);
84} 112}
85 113
86void au1xxx_gpio_write(int signal, int value) 114EXPORT_SYMBOL(au1xxx_gpio_get_value);
115
116void au1xxx_gpio_set_value(unsigned gpio, int value)
87{ 117{
88 if(signal >= 200) 118 if (gpio >= AU1XXX_GPIO_BASE)
89#if defined(CONFIG_SOC_AU1000) 119#if defined(CONFIG_SOC_AU1000)
90 ; 120 ;
91#else 121#else
92 au1xxx_gpio2_write(signal, value); 122 au1xxx_gpio2_write(gpio, value);
93#endif 123#endif
94 else 124 else
95 au1xxx_gpio1_write(signal, value); 125 au1xxx_gpio1_write(gpio, value);
96} 126}
97 127
98void au1xxx_gpio_tristate(int signal) 128EXPORT_SYMBOL(au1xxx_gpio_set_value);
129
130int au1xxx_gpio_direction_input(unsigned gpio)
99{ 131{
100 if(signal >= 200) 132 if (gpio >= AU1XXX_GPIO_BASE)
101#if defined(CONFIG_SOC_AU1000) 133#if defined(CONFIG_SOC_AU1000)
102 ; 134 ;
103#else 135#else
104 au1xxx_gpio2_tristate(signal); 136 return au1xxx_gpio2_direction_input(gpio);
105#endif 137#endif
106 else 138 else
107 au1xxx_gpio1_tristate(signal); 139 return au1xxx_gpio1_direction_input(gpio);
108} 140}
109 141
110void au1xxx_gpio1_set_inputs(void) 142EXPORT_SYMBOL(au1xxx_gpio_direction_input);
143
144int au1xxx_gpio_direction_output(unsigned gpio, int value)
111{ 145{
112 gpio1->pininputen = 0; 146 if (gpio >= AU1XXX_GPIO_BASE)
147#if defined(CONFIG_SOC_AU1000)
148 ;
149#else
150 return au1xxx_gpio2_direction_output(gpio, value);
151#endif
152 else
153 return au1xxx_gpio1_direction_output(gpio, value);
113} 154}
114 155
115EXPORT_SYMBOL(au1xxx_gpio1_set_inputs); 156EXPORT_SYMBOL(au1xxx_gpio_direction_output);
116EXPORT_SYMBOL(au1xxx_gpio_tristate);
117EXPORT_SYMBOL(au1xxx_gpio_write);
118EXPORT_SYMBOL(au1xxx_gpio_read);
diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c
index 8fd203d4a339..d51e18fb789b 100644
--- a/arch/mips/au1000/common/platform.c
+++ b/arch/mips/au1000/common/platform.c
@@ -289,7 +289,7 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
289#endif 289#endif
290}; 290};
291 291
292int au1xxx_platform_init(void) 292int __init au1xxx_platform_init(void)
293{ 293{
294 return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices)); 294 return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices));
295} 295}
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 39e251300c64..129e2c961fec 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31CONFIG_MIPS_ATLAS=y 29CONFIG_MIPS_ATLAS=y
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_MIPS_ATLAS=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 4713a13211ce..dc3e1bf4e42e 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 5e7ae56b1f3c..4c7031222e64 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 631b2138ad68..c8c05785a86d 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -1,44 +1,24 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.21-rc7 3# Linux kernel version: 2.6.22-rc2
4# Wed Apr 18 14:25:45 2007 4# Fri May 25 11:17:29 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set 12# CONFIG_BASLER_EXCITE is not set
26CONFIG_MIPS_COBALT=y 13CONFIG_MIPS_COBALT=y
27# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 15# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 16# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 17# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 18# CONFIG_MIPS_SEAD is not set
34# CONFIG_WR_PPMC is not set 19# CONFIG_WR_PPMC is not set
35# CONFIG_MIPS_SIM is not set 20# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 21# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 22# CONFIG_PNX8550_JBS is not set
43# CONFIG_PNX8550_STB810 is not set 23# CONFIG_PNX8550_STB810 is not set
44# CONFIG_DDB5477 is not set 24# CONFIG_DDB5477 is not set
@@ -138,7 +118,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
138# CONFIG_SPARSEMEM_STATIC is not set 118# CONFIG_SPARSEMEM_STATIC is not set
139CONFIG_SPLIT_PTLOCK_CPUS=4 119CONFIG_SPLIT_PTLOCK_CPUS=4
140# CONFIG_RESOURCES_64BIT is not set 120# CONFIG_RESOURCES_64BIT is not set
141CONFIG_ZONE_DMA_FLAG=1 121CONFIG_ZONE_DMA_FLAG=0
142# CONFIG_HZ_48 is not set 122# CONFIG_HZ_48 is not set
143# CONFIG_HZ_100 is not set 123# CONFIG_HZ_100 is not set
144# CONFIG_HZ_128 is not set 124# CONFIG_HZ_128 is not set
@@ -178,6 +158,7 @@ CONFIG_SYSVIPC_SYSCTL=y
178# CONFIG_UTS_NS is not set 158# CONFIG_UTS_NS is not set
179# CONFIG_AUDIT is not set 159# CONFIG_AUDIT is not set
180# CONFIG_IKCONFIG is not set 160# CONFIG_IKCONFIG is not set
161CONFIG_LOG_BUF_SHIFT=14
181CONFIG_SYSFS_DEPRECATED=y 162CONFIG_SYSFS_DEPRECATED=y
182CONFIG_RELAY=y 163CONFIG_RELAY=y
183# CONFIG_BLK_DEV_INITRD is not set 164# CONFIG_BLK_DEV_INITRD is not set
@@ -193,14 +174,19 @@ CONFIG_BUG=y
193CONFIG_ELF_CORE=y 174CONFIG_ELF_CORE=y
194CONFIG_BASE_FULL=y 175CONFIG_BASE_FULL=y
195CONFIG_FUTEX=y 176CONFIG_FUTEX=y
177CONFIG_ANON_INODES=y
196CONFIG_EPOLL=y 178CONFIG_EPOLL=y
179CONFIG_SIGNALFD=y
180CONFIG_TIMERFD=y
181CONFIG_EVENTFD=y
197CONFIG_SHMEM=y 182CONFIG_SHMEM=y
198CONFIG_SLAB=y
199CONFIG_VM_EVENT_COUNTERS=y 183CONFIG_VM_EVENT_COUNTERS=y
184CONFIG_SLAB=y
185# CONFIG_SLUB is not set
186# CONFIG_SLOB is not set
200CONFIG_RT_MUTEXES=y 187CONFIG_RT_MUTEXES=y
201# CONFIG_TINY_SHMEM is not set 188# CONFIG_TINY_SHMEM is not set
202CONFIG_BASE_SMALL=0 189CONFIG_BASE_SMALL=0
203# CONFIG_SLOB is not set
204 190
205# 191#
206# Loadable module support 192# Loadable module support
@@ -233,16 +219,13 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
233# 219#
234CONFIG_HW_HAS_PCI=y 220CONFIG_HW_HAS_PCI=y
235CONFIG_PCI=y 221CONFIG_PCI=y
222# CONFIG_ARCH_SUPPORTS_MSI is not set
236CONFIG_MMU=y 223CONFIG_MMU=y
237 224
238# 225#
239# PCCARD (PCMCIA/CardBus) support 226# PCCARD (PCMCIA/CardBus) support
240# 227#
241# CONFIG_PCCARD is not set 228# CONFIG_PCCARD is not set
242
243#
244# PCI Hotplug Support
245#
246# CONFIG_HOTPLUG_PCI is not set 229# CONFIG_HOTPLUG_PCI is not set
247 230
248# 231#
@@ -268,7 +251,6 @@ CONFIG_NET=y
268# 251#
269# Networking options 252# Networking options
270# 253#
271# CONFIG_NETDEBUG is not set
272CONFIG_PACKET=y 254CONFIG_PACKET=y
273# CONFIG_PACKET_MMAP is not set 255# CONFIG_PACKET_MMAP is not set
274CONFIG_UNIX=y 256CONFIG_UNIX=y
@@ -300,11 +282,11 @@ CONFIG_INET_TCP_DIAG=y
300# CONFIG_TCP_CONG_ADVANCED is not set 282# CONFIG_TCP_CONG_ADVANCED is not set
301CONFIG_TCP_CONG_CUBIC=y 283CONFIG_TCP_CONG_CUBIC=y
302CONFIG_DEFAULT_TCP_CONG="cubic" 284CONFIG_DEFAULT_TCP_CONG="cubic"
303CONFIG_TCP_MD5SIG=y 285# CONFIG_TCP_MD5SIG is not set
304# CONFIG_IPV6 is not set 286# CONFIG_IPV6 is not set
305# CONFIG_INET6_XFRM_TUNNEL is not set 287# CONFIG_INET6_XFRM_TUNNEL is not set
306# CONFIG_INET6_TUNNEL is not set 288# CONFIG_INET6_TUNNEL is not set
307CONFIG_NETWORK_SECMARK=y 289# CONFIG_NETWORK_SECMARK is not set
308# CONFIG_NETFILTER is not set 290# CONFIG_NETFILTER is not set
309 291
310# 292#
@@ -345,13 +327,16 @@ CONFIG_NETWORK_SECMARK=y
345# CONFIG_HAMRADIO is not set 327# CONFIG_HAMRADIO is not set
346# CONFIG_IRDA is not set 328# CONFIG_IRDA is not set
347# CONFIG_BT is not set 329# CONFIG_BT is not set
348CONFIG_IEEE80211=y 330# CONFIG_AF_RXRPC is not set
349# CONFIG_IEEE80211_DEBUG is not set 331
350CONFIG_IEEE80211_CRYPT_WEP=y 332#
351CONFIG_IEEE80211_CRYPT_CCMP=y 333# Wireless
352CONFIG_IEEE80211_SOFTMAC=y 334#
353# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set 335# CONFIG_CFG80211 is not set
354CONFIG_WIRELESS_EXT=y 336# CONFIG_WIRELESS_EXT is not set
337# CONFIG_MAC80211 is not set
338# CONFIG_IEEE80211 is not set
339# CONFIG_RFKILL is not set
355 340
356# 341#
357# Device Drivers 342# Device Drivers
@@ -370,10 +355,6 @@ CONFIG_FW_LOADER=y
370# 355#
371CONFIG_CONNECTOR=y 356CONFIG_CONNECTOR=y
372CONFIG_PROC_EVENTS=y 357CONFIG_PROC_EVENTS=y
373
374#
375# Memory Technology Devices (MTD)
376#
377CONFIG_MTD=y 358CONFIG_MTD=y
378# CONFIG_MTD_DEBUG is not set 359# CONFIG_MTD_DEBUG is not set
379# CONFIG_MTD_CONCAT is not set 360# CONFIG_MTD_CONCAT is not set
@@ -418,7 +399,6 @@ CONFIG_MTD_CFI_UTIL=y
418# CONFIG_MTD_RAM is not set 399# CONFIG_MTD_RAM is not set
419# CONFIG_MTD_ROM is not set 400# CONFIG_MTD_ROM is not set
420# CONFIG_MTD_ABSENT is not set 401# CONFIG_MTD_ABSENT is not set
421# CONFIG_MTD_OBSOLETE_CHIPS is not set
422 402
423# 403#
424# Mapping drivers for chip access 404# Mapping drivers for chip access
@@ -445,16 +425,13 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
445# CONFIG_MTD_DOC2000 is not set 425# CONFIG_MTD_DOC2000 is not set
446# CONFIG_MTD_DOC2001 is not set 426# CONFIG_MTD_DOC2001 is not set
447# CONFIG_MTD_DOC2001PLUS is not set 427# CONFIG_MTD_DOC2001PLUS is not set
448
449#
450# NAND Flash Device Drivers
451#
452# CONFIG_MTD_NAND is not set 428# CONFIG_MTD_NAND is not set
429# CONFIG_MTD_ONENAND is not set
453 430
454# 431#
455# OneNAND Flash Device Drivers 432# UBI - Unsorted block images
456# 433#
457# CONFIG_MTD_ONENAND is not set 434# CONFIG_MTD_UBI is not set
458 435
459# 436#
460# Parallel port support 437# Parallel port support
@@ -479,87 +456,145 @@ CONFIG_BLK_DEV_LOOP=y
479# CONFIG_BLK_DEV_NBD is not set 456# CONFIG_BLK_DEV_NBD is not set
480# CONFIG_BLK_DEV_SX8 is not set 457# CONFIG_BLK_DEV_SX8 is not set
481# CONFIG_BLK_DEV_RAM is not set 458# CONFIG_BLK_DEV_RAM is not set
482CONFIG_CDROM_PKTCDVD=y 459# CONFIG_CDROM_PKTCDVD is not set
483CONFIG_CDROM_PKTCDVD_BUFFERS=8 460# CONFIG_ATA_OVER_ETH is not set
484# CONFIG_CDROM_PKTCDVD_WCACHE is not set
485CONFIG_ATA_OVER_ETH=y
486 461
487# 462#
488# Misc devices 463# Misc devices
489# 464#
490CONFIG_SGI_IOC4=y 465# CONFIG_PHANTOM is not set
466# CONFIG_SGI_IOC4 is not set
491# CONFIG_TIFM_CORE is not set 467# CONFIG_TIFM_CORE is not set
492 468# CONFIG_BLINK is not set
493# 469# CONFIG_IDE is not set
494# ATA/ATAPI/MFM/RLL support
495#
496CONFIG_IDE=y
497CONFIG_IDE_MAX_HWIFS=4
498CONFIG_BLK_DEV_IDE=y
499
500#
501# Please see Documentation/ide.txt for help/info on IDE drives
502#
503# CONFIG_BLK_DEV_IDE_SATA is not set
504CONFIG_BLK_DEV_IDEDISK=y
505# CONFIG_IDEDISK_MULTI_MODE is not set
506# CONFIG_BLK_DEV_IDECD is not set
507# CONFIG_BLK_DEV_IDETAPE is not set
508# CONFIG_BLK_DEV_IDEFLOPPY is not set
509# CONFIG_IDE_TASK_IOCTL is not set
510
511#
512# IDE chipset support/bugfixes
513#
514CONFIG_IDE_GENERIC=y
515CONFIG_BLK_DEV_IDEPCI=y
516# CONFIG_IDEPCI_SHARE_IRQ is not set
517# CONFIG_BLK_DEV_OFFBOARD is not set
518# CONFIG_BLK_DEV_GENERIC is not set
519# CONFIG_BLK_DEV_OPTI621 is not set
520CONFIG_BLK_DEV_IDEDMA_PCI=y
521# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
522# CONFIG_IDEDMA_ONLYDISK is not set
523# CONFIG_BLK_DEV_AEC62XX is not set
524# CONFIG_BLK_DEV_ALI15X3 is not set
525# CONFIG_BLK_DEV_AMD74XX is not set
526# CONFIG_BLK_DEV_CMD64X is not set
527# CONFIG_BLK_DEV_TRIFLEX is not set
528# CONFIG_BLK_DEV_CY82C693 is not set
529# CONFIG_BLK_DEV_CS5520 is not set
530# CONFIG_BLK_DEV_CS5530 is not set
531# CONFIG_BLK_DEV_HPT34X is not set
532# CONFIG_BLK_DEV_HPT366 is not set
533# CONFIG_BLK_DEV_JMICRON is not set
534# CONFIG_BLK_DEV_SC1200 is not set
535# CONFIG_BLK_DEV_PIIX is not set
536CONFIG_BLK_DEV_IT8213=y
537# CONFIG_BLK_DEV_IT821X is not set
538# CONFIG_BLK_DEV_NS87415 is not set
539# CONFIG_BLK_DEV_PDC202XX_OLD is not set
540# CONFIG_BLK_DEV_PDC202XX_NEW is not set
541# CONFIG_BLK_DEV_SVWKS is not set
542# CONFIG_BLK_DEV_SIIMAGE is not set
543# CONFIG_BLK_DEV_SLC90E66 is not set
544# CONFIG_BLK_DEV_TRM290 is not set
545CONFIG_BLK_DEV_VIA82CXXX=y
546CONFIG_BLK_DEV_TC86C001=y
547# CONFIG_IDE_ARM is not set
548CONFIG_BLK_DEV_IDEDMA=y
549# CONFIG_IDEDMA_IVB is not set
550# CONFIG_BLK_DEV_HD is not set
551 470
552# 471#
553# SCSI device support 472# SCSI device support
554# 473#
555CONFIG_RAID_ATTRS=y 474CONFIG_RAID_ATTRS=y
556# CONFIG_SCSI is not set 475CONFIG_SCSI=y
476# CONFIG_SCSI_TGT is not set
557# CONFIG_SCSI_NETLINK is not set 477# CONFIG_SCSI_NETLINK is not set
558 478CONFIG_SCSI_PROC_FS=y
559# 479
560# Serial ATA (prod) and Parallel ATA (experimental) drivers 480#
561# 481# SCSI support type (disk, tape, CD-ROM)
562# CONFIG_ATA is not set 482#
483CONFIG_BLK_DEV_SD=y
484# CONFIG_CHR_DEV_ST is not set
485# CONFIG_CHR_DEV_OSST is not set
486# CONFIG_BLK_DEV_SR is not set
487# CONFIG_CHR_DEV_SG is not set
488# CONFIG_CHR_DEV_SCH is not set
489
490#
491# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
492#
493# CONFIG_SCSI_MULTI_LUN is not set
494# CONFIG_SCSI_CONSTANTS is not set
495# CONFIG_SCSI_LOGGING is not set
496# CONFIG_SCSI_SCAN_ASYNC is not set
497
498#
499# SCSI Transports
500#
501# CONFIG_SCSI_SPI_ATTRS is not set
502# CONFIG_SCSI_FC_ATTRS is not set
503# CONFIG_SCSI_ISCSI_ATTRS is not set
504# CONFIG_SCSI_SAS_ATTRS is not set
505# CONFIG_SCSI_SAS_LIBSAS is not set
506
507#
508# SCSI low-level drivers
509#
510# CONFIG_ISCSI_TCP is not set
511# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
512# CONFIG_SCSI_3W_9XXX is not set
513# CONFIG_SCSI_ACARD is not set
514# CONFIG_SCSI_AACRAID is not set
515# CONFIG_SCSI_AIC7XXX is not set
516# CONFIG_SCSI_AIC7XXX_OLD is not set
517# CONFIG_SCSI_AIC79XX is not set
518# CONFIG_SCSI_AIC94XX is not set
519# CONFIG_SCSI_DPT_I2O is not set
520# CONFIG_SCSI_ARCMSR is not set
521# CONFIG_MEGARAID_NEWGEN is not set
522# CONFIG_MEGARAID_LEGACY is not set
523# CONFIG_MEGARAID_SAS is not set
524# CONFIG_SCSI_HPTIOP is not set
525# CONFIG_SCSI_DMX3191D is not set
526# CONFIG_SCSI_FUTURE_DOMAIN is not set
527# CONFIG_SCSI_IPS is not set
528# CONFIG_SCSI_INITIO is not set
529# CONFIG_SCSI_INIA100 is not set
530# CONFIG_SCSI_STEX is not set
531# CONFIG_SCSI_SYM53C8XX_2 is not set
532# CONFIG_SCSI_IPR is not set
533# CONFIG_SCSI_QLOGIC_1280 is not set
534# CONFIG_SCSI_QLA_FC is not set
535# CONFIG_SCSI_QLA_ISCSI is not set
536# CONFIG_SCSI_LPFC is not set
537# CONFIG_SCSI_DC395x is not set
538# CONFIG_SCSI_DC390T is not set
539# CONFIG_SCSI_NSP32 is not set
540# CONFIG_SCSI_DEBUG is not set
541# CONFIG_SCSI_ESP_CORE is not set
542# CONFIG_SCSI_SRP is not set
543CONFIG_ATA=y
544# CONFIG_ATA_NONSTANDARD is not set
545# CONFIG_SATA_AHCI is not set
546# CONFIG_SATA_SVW is not set
547# CONFIG_ATA_PIIX is not set
548# CONFIG_SATA_MV is not set
549# CONFIG_SATA_NV is not set
550# CONFIG_PDC_ADMA is not set
551# CONFIG_SATA_QSTOR is not set
552# CONFIG_SATA_PROMISE is not set
553# CONFIG_SATA_SX4 is not set
554# CONFIG_SATA_SIL is not set
555# CONFIG_SATA_SIL24 is not set
556# CONFIG_SATA_SIS is not set
557# CONFIG_SATA_ULI is not set
558# CONFIG_SATA_VIA is not set
559# CONFIG_SATA_VITESSE is not set
560# CONFIG_SATA_INIC162X is not set
561# CONFIG_PATA_ALI is not set
562# CONFIG_PATA_AMD is not set
563# CONFIG_PATA_ARTOP is not set
564# CONFIG_PATA_ATIIXP is not set
565# CONFIG_PATA_CMD640_PCI is not set
566# CONFIG_PATA_CMD64X is not set
567# CONFIG_PATA_CS5520 is not set
568# CONFIG_PATA_CS5530 is not set
569# CONFIG_PATA_CYPRESS is not set
570# CONFIG_PATA_EFAR is not set
571# CONFIG_ATA_GENERIC is not set
572# CONFIG_PATA_HPT366 is not set
573# CONFIG_PATA_HPT37X is not set
574# CONFIG_PATA_HPT3X2N is not set
575# CONFIG_PATA_HPT3X3 is not set
576# CONFIG_PATA_IT821X is not set
577# CONFIG_PATA_IT8213 is not set
578# CONFIG_PATA_JMICRON is not set
579# CONFIG_PATA_TRIFLEX is not set
580# CONFIG_PATA_MARVELL is not set
581# CONFIG_PATA_MPIIX is not set
582# CONFIG_PATA_OLDPIIX is not set
583# CONFIG_PATA_NETCELL is not set
584# CONFIG_PATA_NS87410 is not set
585# CONFIG_PATA_OPTI is not set
586# CONFIG_PATA_OPTIDMA is not set
587# CONFIG_PATA_PDC_OLD is not set
588# CONFIG_PATA_RADISYS is not set
589# CONFIG_PATA_RZ1000 is not set
590# CONFIG_PATA_SC1200 is not set
591# CONFIG_PATA_SERVERWORKS is not set
592# CONFIG_PATA_PDC2027X is not set
593# CONFIG_PATA_SIL680 is not set
594# CONFIG_PATA_SIS is not set
595CONFIG_PATA_VIA=y
596# CONFIG_PATA_WINBOND is not set
597# CONFIG_PATA_PLATFORM is not set
563 598
564# 599#
565# Multi-device support (RAID and LVM) 600# Multi-device support (RAID and LVM)
@@ -570,10 +605,14 @@ CONFIG_RAID_ATTRS=y
570# Fusion MPT device support 605# Fusion MPT device support
571# 606#
572# CONFIG_FUSION is not set 607# CONFIG_FUSION is not set
608# CONFIG_FUSION_SPI is not set
609# CONFIG_FUSION_FC is not set
610# CONFIG_FUSION_SAS is not set
573 611
574# 612#
575# IEEE 1394 (FireWire) support 613# IEEE 1394 (FireWire) support
576# 614#
615# CONFIG_FIREWIRE is not set
577# CONFIG_IEEE1394 is not set 616# CONFIG_IEEE1394 is not set
578 617
579# 618#
@@ -594,24 +633,7 @@ CONFIG_NETDEVICES=y
594# ARCnet devices 633# ARCnet devices
595# 634#
596# CONFIG_ARCNET is not set 635# CONFIG_ARCNET is not set
597 636# CONFIG_PHYLIB is not set
598#
599# PHY device support
600#
601CONFIG_PHYLIB=y
602
603#
604# MII PHY device drivers
605#
606CONFIG_MARVELL_PHY=y
607CONFIG_DAVICOM_PHY=y
608CONFIG_QSEMI_PHY=y
609CONFIG_LXT_PHY=y
610CONFIG_CICADA_PHY=y
611CONFIG_VITESSE_PHY=y
612CONFIG_SMSC_PHY=y
613# CONFIG_BROADCOM_PHY is not set
614# CONFIG_FIXED_PHY is not set
615 637
616# 638#
617# Ethernet (10 or 100Mbit) 639# Ethernet (10 or 100Mbit)
@@ -639,35 +661,8 @@ CONFIG_TULIP=y
639# CONFIG_ULI526X is not set 661# CONFIG_ULI526X is not set
640# CONFIG_HP100 is not set 662# CONFIG_HP100 is not set
641# CONFIG_NET_PCI is not set 663# CONFIG_NET_PCI is not set
642 664# CONFIG_NETDEV_1000 is not set
643# 665# CONFIG_NETDEV_10000 is not set
644# Ethernet (1000 Mbit)
645#
646# CONFIG_ACENIC is not set
647# CONFIG_DL2K is not set
648# CONFIG_E1000 is not set
649# CONFIG_NS83820 is not set
650# CONFIG_HAMACHI is not set
651# CONFIG_YELLOWFIN is not set
652# CONFIG_R8169 is not set
653# CONFIG_SIS190 is not set
654# CONFIG_SKGE is not set
655# CONFIG_SKY2 is not set
656# CONFIG_SK98LIN is not set
657# CONFIG_TIGON3 is not set
658# CONFIG_BNX2 is not set
659CONFIG_QLA3XXX=y
660# CONFIG_ATL1 is not set
661
662#
663# Ethernet (10000 Mbit)
664#
665# CONFIG_CHELSIO_T1 is not set
666CONFIG_CHELSIO_T3=y
667# CONFIG_IXGB is not set
668# CONFIG_S2IO is not set
669# CONFIG_MYRI10GE is not set
670CONFIG_NETXEN_NIC=y
671 666
672# 667#
673# Token Ring devices 668# Token Ring devices
@@ -675,18 +670,16 @@ CONFIG_NETXEN_NIC=y
675# CONFIG_TR is not set 670# CONFIG_TR is not set
676 671
677# 672#
678# Wireless LAN (non-hamradio) 673# Wireless LAN
679#
680# CONFIG_NET_RADIO is not set
681
682#
683# Wan interfaces
684# 674#
675# CONFIG_WLAN_PRE80211 is not set
676# CONFIG_WLAN_80211 is not set
685# CONFIG_WAN is not set 677# CONFIG_WAN is not set
686# CONFIG_FDDI is not set 678# CONFIG_FDDI is not set
687# CONFIG_HIPPI is not set 679# CONFIG_HIPPI is not set
688# CONFIG_PPP is not set 680# CONFIG_PPP is not set
689# CONFIG_SLIP is not set 681# CONFIG_SLIP is not set
682# CONFIG_NET_FC is not set
690# CONFIG_SHAPER is not set 683# CONFIG_SHAPER is not set
691# CONFIG_NETCONSOLE is not set 684# CONFIG_NETCONSOLE is not set
692# CONFIG_NETPOLL is not set 685# CONFIG_NETPOLL is not set
@@ -711,10 +704,7 @@ CONFIG_INPUT=y
711# 704#
712# Userland interfaces 705# Userland interfaces
713# 706#
714CONFIG_INPUT_MOUSEDEV=y 707# CONFIG_INPUT_MOUSEDEV is not set
715CONFIG_INPUT_MOUSEDEV_PSAUX=y
716CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
717CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
718# CONFIG_INPUT_JOYDEV is not set 708# CONFIG_INPUT_JOYDEV is not set
719# CONFIG_INPUT_TSDEV is not set 709# CONFIG_INPUT_TSDEV is not set
720# CONFIG_INPUT_EVDEV is not set 710# CONFIG_INPUT_EVDEV is not set
@@ -726,18 +716,23 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
726# CONFIG_INPUT_KEYBOARD is not set 716# CONFIG_INPUT_KEYBOARD is not set
727# CONFIG_INPUT_MOUSE is not set 717# CONFIG_INPUT_MOUSE is not set
728# CONFIG_INPUT_JOYSTICK is not set 718# CONFIG_INPUT_JOYSTICK is not set
719# CONFIG_INPUT_TABLET is not set
729# CONFIG_INPUT_TOUCHSCREEN is not set 720# CONFIG_INPUT_TOUCHSCREEN is not set
730# CONFIG_INPUT_MISC is not set 721CONFIG_INPUT_MISC=y
722# CONFIG_INPUT_PCSPKR is not set
723CONFIG_INPUT_COBALT_BTNS=y
724# CONFIG_INPUT_ATI_REMOTE is not set
725# CONFIG_INPUT_ATI_REMOTE2 is not set
726# CONFIG_INPUT_KEYSPAN_REMOTE is not set
727# CONFIG_INPUT_POWERMATE is not set
728# CONFIG_INPUT_YEALINK is not set
729# CONFIG_INPUT_UINPUT is not set
730CONFIG_INPUT_POLLDEV=y
731 731
732# 732#
733# Hardware I/O ports 733# Hardware I/O ports
734# 734#
735CONFIG_SERIO=y 735# CONFIG_SERIO is not set
736# CONFIG_SERIO_I8042 is not set
737CONFIG_SERIO_SERPORT=y
738# CONFIG_SERIO_PCIPS2 is not set
739# CONFIG_SERIO_LIBPS2 is not set
740CONFIG_SERIO_RAW=y
741# CONFIG_GAMEPORT is not set 736# CONFIG_GAMEPORT is not set
742 737
743# 738#
@@ -754,7 +749,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
754# 749#
755CONFIG_SERIAL_8250=y 750CONFIG_SERIAL_8250=y
756CONFIG_SERIAL_8250_CONSOLE=y 751CONFIG_SERIAL_8250_CONSOLE=y
757CONFIG_SERIAL_8250_PCI=y 752# CONFIG_SERIAL_8250_PCI is not set
758CONFIG_SERIAL_8250_NR_UARTS=4 753CONFIG_SERIAL_8250_NR_UARTS=4
759CONFIG_SERIAL_8250_RUNTIME_UARTS=4 754CONFIG_SERIAL_8250_RUNTIME_UARTS=4
760# CONFIG_SERIAL_8250_EXTENDED is not set 755# CONFIG_SERIAL_8250_EXTENDED is not set
@@ -773,16 +768,11 @@ CONFIG_LEGACY_PTY_COUNT=256
773# IPMI 768# IPMI
774# 769#
775# CONFIG_IPMI_HANDLER is not set 770# CONFIG_IPMI_HANDLER is not set
776
777#
778# Watchdog Cards
779#
780# CONFIG_WATCHDOG is not set 771# CONFIG_WATCHDOG is not set
781# CONFIG_HW_RANDOM is not set 772# CONFIG_HW_RANDOM is not set
782# CONFIG_RTC is not set 773# CONFIG_RTC is not set
783# CONFIG_GEN_RTC is not set 774# CONFIG_GEN_RTC is not set
784CONFIG_COBALT_LCD=y 775CONFIG_COBALT_LCD=y
785# CONFIG_DTLK is not set
786# CONFIG_R3964 is not set 776# CONFIG_R3964 is not set
787# CONFIG_APPLICOM is not set 777# CONFIG_APPLICOM is not set
788# CONFIG_DRM is not set 778# CONFIG_DRM is not set
@@ -792,10 +782,7 @@ CONFIG_COBALT_LCD=y
792# TPM devices 782# TPM devices
793# 783#
794# CONFIG_TCG_TPM is not set 784# CONFIG_TCG_TPM is not set
795 785CONFIG_DEVPORT=y
796#
797# I2C support
798#
799# CONFIG_I2C is not set 786# CONFIG_I2C is not set
800 787
801# 788#
@@ -808,12 +795,7 @@ CONFIG_COBALT_LCD=y
808# Dallas's 1-wire bus 795# Dallas's 1-wire bus
809# 796#
810# CONFIG_W1 is not set 797# CONFIG_W1 is not set
811
812#
813# Hardware Monitoring support
814#
815# CONFIG_HWMON is not set 798# CONFIG_HWMON is not set
816# CONFIG_HWMON_VID is not set
817 799
818# 800#
819# Multifunction device drivers 801# Multifunction device drivers
@@ -824,16 +806,19 @@ CONFIG_COBALT_LCD=y
824# Multimedia devices 806# Multimedia devices
825# 807#
826# CONFIG_VIDEO_DEV is not set 808# CONFIG_VIDEO_DEV is not set
809# CONFIG_DVB_CORE is not set
810# CONFIG_DAB is not set
827 811
828# 812#
829# Digital Video Broadcasting Devices 813# Graphics support
830# 814#
831# CONFIG_DVB is not set 815# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
832 816
833# 817#
834# Graphics support 818# Display device support
835# 819#
836# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 820# CONFIG_DISPLAY_SUPPORT is not set
821# CONFIG_VGASTATE is not set
837# CONFIG_FB is not set 822# CONFIG_FB is not set
838 823
839# 824#
@@ -868,10 +853,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
868# USB Gadget Support 853# USB Gadget Support
869# 854#
870# CONFIG_USB_GADGET is not set 855# CONFIG_USB_GADGET is not set
871
872#
873# MMC/SD Card support
874#
875# CONFIG_MMC is not set 856# CONFIG_MMC is not set
876 857
877# 858#
@@ -912,18 +893,30 @@ CONFIG_RTC_INTF_SYSFS=y
912CONFIG_RTC_INTF_PROC=y 893CONFIG_RTC_INTF_PROC=y
913CONFIG_RTC_INTF_DEV=y 894CONFIG_RTC_INTF_DEV=y
914# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set 895# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
896# CONFIG_RTC_DRV_TEST is not set
915 897
916# 898#
917# RTC drivers 899# I2C RTC drivers
900#
901
902#
903# SPI RTC drivers
904#
905
906#
907# Platform RTC drivers
918# 908#
919CONFIG_RTC_DRV_CMOS=y 909CONFIG_RTC_DRV_CMOS=y
920# CONFIG_RTC_DRV_DS1553 is not set 910# CONFIG_RTC_DRV_DS1553 is not set
921# CONFIG_RTC_DRV_DS1742 is not set 911# CONFIG_RTC_DRV_DS1742 is not set
922# CONFIG_RTC_DRV_M48T86 is not set 912# CONFIG_RTC_DRV_M48T86 is not set
923# CONFIG_RTC_DRV_TEST is not set
924# CONFIG_RTC_DRV_V3020 is not set 913# CONFIG_RTC_DRV_V3020 is not set
925 914
926# 915#
916# on-CPU RTC drivers
917#
918
919#
927# DMA Engine support 920# DMA Engine support
928# 921#
929# CONFIG_DMA_ENGINE is not set 922# CONFIG_DMA_ENGINE is not set
@@ -937,14 +930,6 @@ CONFIG_RTC_DRV_CMOS=y
937# 930#
938 931
939# 932#
940# Auxiliary Display support
941#
942
943#
944# Virtualization
945#
946
947#
948# File systems 933# File systems
949# 934#
950CONFIG_EXT2_FS=y 935CONFIG_EXT2_FS=y
@@ -952,8 +937,13 @@ CONFIG_EXT2_FS_XATTR=y
952CONFIG_EXT2_FS_POSIX_ACL=y 937CONFIG_EXT2_FS_POSIX_ACL=y
953CONFIG_EXT2_FS_SECURITY=y 938CONFIG_EXT2_FS_SECURITY=y
954# CONFIG_EXT2_FS_XIP is not set 939# CONFIG_EXT2_FS_XIP is not set
955# CONFIG_EXT3_FS is not set 940CONFIG_EXT3_FS=y
941CONFIG_EXT3_FS_XATTR=y
942CONFIG_EXT3_FS_POSIX_ACL=y
943CONFIG_EXT3_FS_SECURITY=y
956# CONFIG_EXT4DEV_FS is not set 944# CONFIG_EXT4DEV_FS is not set
945CONFIG_JBD=y
946# CONFIG_JBD_DEBUG is not set
957CONFIG_FS_MBCACHE=y 947CONFIG_FS_MBCACHE=y
958# CONFIG_REISERFS_FS is not set 948# CONFIG_REISERFS_FS is not set
959# CONFIG_JFS_FS is not set 949# CONFIG_JFS_FS is not set
@@ -969,7 +959,7 @@ CONFIG_INOTIFY_USER=y
969CONFIG_DNOTIFY=y 959CONFIG_DNOTIFY=y
970# CONFIG_AUTOFS_FS is not set 960# CONFIG_AUTOFS_FS is not set
971# CONFIG_AUTOFS4_FS is not set 961# CONFIG_AUTOFS4_FS is not set
972CONFIG_FUSE_FS=y 962# CONFIG_FUSE_FS is not set
973CONFIG_GENERIC_ACL=y 963CONFIG_GENERIC_ACL=y
974 964
975# 965#
@@ -1003,7 +993,6 @@ CONFIG_CONFIGFS_FS=y
1003# 993#
1004# CONFIG_ADFS_FS is not set 994# CONFIG_ADFS_FS is not set
1005# CONFIG_AFFS_FS is not set 995# CONFIG_AFFS_FS is not set
1006# CONFIG_ECRYPT_FS is not set
1007# CONFIG_HFS_FS is not set 996# CONFIG_HFS_FS is not set
1008# CONFIG_HFSPLUS_FS is not set 997# CONFIG_HFSPLUS_FS is not set
1009# CONFIG_BEFS_FS is not set 998# CONFIG_BEFS_FS is not set
@@ -1021,13 +1010,23 @@ CONFIG_CONFIGFS_FS=y
1021# Network File Systems 1010# Network File Systems
1022# 1011#
1023CONFIG_NFS_FS=y 1012CONFIG_NFS_FS=y
1024# CONFIG_NFS_V3 is not set 1013CONFIG_NFS_V3=y
1014CONFIG_NFS_V3_ACL=y
1025# CONFIG_NFS_V4 is not set 1015# CONFIG_NFS_V4 is not set
1026# CONFIG_NFS_DIRECTIO is not set 1016# CONFIG_NFS_DIRECTIO is not set
1027# CONFIG_NFSD is not set 1017CONFIG_NFSD=y
1018CONFIG_NFSD_V2_ACL=y
1019CONFIG_NFSD_V3=y
1020CONFIG_NFSD_V3_ACL=y
1021# CONFIG_NFSD_V4 is not set
1022CONFIG_NFSD_TCP=y
1028CONFIG_LOCKD=y 1023CONFIG_LOCKD=y
1024CONFIG_LOCKD_V4=y
1025CONFIG_EXPORTFS=y
1026CONFIG_NFS_ACL_SUPPORT=y
1029CONFIG_NFS_COMMON=y 1027CONFIG_NFS_COMMON=y
1030CONFIG_SUNRPC=y 1028CONFIG_SUNRPC=y
1029# CONFIG_SUNRPC_BIND34 is not set
1031# CONFIG_RPCSEC_GSS_KRB5 is not set 1030# CONFIG_RPCSEC_GSS_KRB5 is not set
1032# CONFIG_RPCSEC_GSS_SPKM3 is not set 1031# CONFIG_RPCSEC_GSS_SPKM3 is not set
1033# CONFIG_SMB_FS is not set 1032# CONFIG_SMB_FS is not set
@@ -1051,10 +1050,7 @@ CONFIG_MSDOS_PARTITION=y
1051# 1050#
1052# Distributed Lock Manager 1051# Distributed Lock Manager
1053# 1052#
1054CONFIG_DLM=y 1053# CONFIG_DLM is not set
1055CONFIG_DLM_TCP=y
1056# CONFIG_DLM_SCTP is not set
1057# CONFIG_DLM_DEBUG is not set
1058 1054
1059# 1055#
1060# Profiling support 1056# Profiling support
@@ -1072,72 +1068,30 @@ CONFIG_ENABLE_MUST_CHECK=y
1072# CONFIG_DEBUG_FS is not set 1068# CONFIG_DEBUG_FS is not set
1073# CONFIG_HEADERS_CHECK is not set 1069# CONFIG_HEADERS_CHECK is not set
1074# CONFIG_DEBUG_KERNEL is not set 1070# CONFIG_DEBUG_KERNEL is not set
1075CONFIG_LOG_BUF_SHIFT=14
1076CONFIG_CROSSCOMPILE=y 1071CONFIG_CROSSCOMPILE=y
1077CONFIG_CMDLINE="" 1072CONFIG_CMDLINE=""
1078 1073
1079# 1074#
1080# Security options 1075# Security options
1081# 1076#
1082CONFIG_KEYS=y 1077# CONFIG_KEYS is not set
1083CONFIG_KEYS_DEBUG_PROC_KEYS=y
1084# CONFIG_SECURITY is not set 1078# CONFIG_SECURITY is not set
1085 1079
1086# 1080#
1087# Cryptographic options 1081# Cryptographic options
1088# 1082#
1089CONFIG_CRYPTO=y 1083# CONFIG_CRYPTO is not set
1090CONFIG_CRYPTO_ALGAPI=y
1091CONFIG_CRYPTO_BLKCIPHER=y
1092CONFIG_CRYPTO_HASH=y
1093CONFIG_CRYPTO_MANAGER=y
1094CONFIG_CRYPTO_HMAC=y
1095CONFIG_CRYPTO_XCBC=y
1096CONFIG_CRYPTO_NULL=y
1097CONFIG_CRYPTO_MD4=y
1098CONFIG_CRYPTO_MD5=y
1099CONFIG_CRYPTO_SHA1=y
1100CONFIG_CRYPTO_SHA256=y
1101CONFIG_CRYPTO_SHA512=y
1102CONFIG_CRYPTO_WP512=y
1103CONFIG_CRYPTO_TGR192=y
1104CONFIG_CRYPTO_GF128MUL=y
1105CONFIG_CRYPTO_ECB=y
1106CONFIG_CRYPTO_CBC=y
1107CONFIG_CRYPTO_PCBC=y
1108CONFIG_CRYPTO_LRW=y
1109CONFIG_CRYPTO_DES=y
1110CONFIG_CRYPTO_FCRYPT=y
1111CONFIG_CRYPTO_BLOWFISH=y
1112CONFIG_CRYPTO_TWOFISH=y
1113CONFIG_CRYPTO_TWOFISH_COMMON=y
1114CONFIG_CRYPTO_SERPENT=y
1115CONFIG_CRYPTO_AES=y
1116CONFIG_CRYPTO_CAST5=y
1117CONFIG_CRYPTO_CAST6=y
1118CONFIG_CRYPTO_TEA=y
1119CONFIG_CRYPTO_ARC4=y
1120CONFIG_CRYPTO_KHAZAD=y
1121CONFIG_CRYPTO_ANUBIS=y
1122CONFIG_CRYPTO_DEFLATE=y
1123CONFIG_CRYPTO_MICHAEL_MIC=y
1124CONFIG_CRYPTO_CRC32C=y
1125CONFIG_CRYPTO_CAMELLIA=y
1126
1127#
1128# Hardware crypto devices
1129#
1130 1084
1131# 1085#
1132# Library routines 1086# Library routines
1133# 1087#
1134CONFIG_BITREVERSE=y 1088CONFIG_BITREVERSE=y
1135# CONFIG_CRC_CCITT is not set 1089# CONFIG_CRC_CCITT is not set
1136CONFIG_CRC16=y 1090# CONFIG_CRC16 is not set
1091# CONFIG_CRC_ITU_T is not set
1137CONFIG_CRC32=y 1092CONFIG_CRC32=y
1138CONFIG_LIBCRC32C=y 1093CONFIG_LIBCRC32C=y
1139CONFIG_ZLIB_INFLATE=y
1140CONFIG_ZLIB_DEFLATE=y
1141CONFIG_PLIST=y 1094CONFIG_PLIST=y
1142CONFIG_HAS_IOMEM=y 1095CONFIG_HAS_IOMEM=y
1143CONFIG_HAS_IOPORT=y 1096CONFIG_HAS_IOPORT=y
1097CONFIG_HAS_DMA=y
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 10f6af43753d..ec60beb888b2 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -26,9 +26,7 @@ CONFIG_MIPS_DB1000=y
26# CONFIG_BASLER_EXCITE is not set 26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_MIPS_DB1000=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 4b0862927748..f3c25f08bfad 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -26,9 +26,7 @@ CONFIG_MIPS_DB1100=y
26# CONFIG_BASLER_EXCITE is not set 26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_MIPS_DB1100=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 820659e810dc..6d400befbacc 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -26,9 +26,7 @@ CONFIG_MIPS_DB1200=y
26# CONFIG_BASLER_EXCITE is not set 26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_MIPS_DB1200=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 4050b9b91bcb..82aea6e08823 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -26,9 +26,7 @@ CONFIG_MIPS_DB1500=y
26# CONFIG_BASLER_EXCITE is not set 26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_MIPS_DB1500=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 7b3519058ab8..82697714a9e3 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -26,9 +26,7 @@ CONFIG_MIPS_DB1550=y
26# CONFIG_BASLER_EXCITE is not set 26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_MIPS_DB1550=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index 5b502a2013fb..a42ab9ae7d4b 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 4bbdab078ff1..d6e3fffbc80d 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27CONFIG_MACH_DECSTATION=y 27CONFIG_MACH_DECSTATION=y
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_MACH_DECSTATION=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index b5714a6a5398..78f5004fb721 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
index 2e3e155b4c55..b29bff0f56c3 100644
--- a/arch/mips/configs/emma2rh_defconfig
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig
deleted file mode 100644
index c10e4e063226..000000000000
--- a/arch/mips/configs/ev64120_defconfig
+++ /dev/null
@@ -1,985 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20
4# Tue Feb 20 21:47:30 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set
28CONFIG_MIPS_EV64120=y
29# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set
34# CONFIG_WR_PPMC is not set
35# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set
43# CONFIG_PNX8550_STB810 is not set
44# CONFIG_DDB5477 is not set
45# CONFIG_MACH_VR41XX is not set
46# CONFIG_PMC_YOSEMITE is not set
47# CONFIG_QEMU is not set
48# CONFIG_MARKEINS is not set
49# CONFIG_SGI_IP22 is not set
50# CONFIG_SGI_IP27 is not set
51# CONFIG_SGI_IP32 is not set
52# CONFIG_SIBYTE_BIGSUR is not set
53# CONFIG_SIBYTE_SWARM is not set
54# CONFIG_SIBYTE_SENTOSA is not set
55# CONFIG_SIBYTE_RHONE is not set
56# CONFIG_SIBYTE_CARMEL is not set
57# CONFIG_SIBYTE_PTSWARM is not set
58# CONFIG_SIBYTE_LITTLESUR is not set
59# CONFIG_SIBYTE_CRHINE is not set
60# CONFIG_SIBYTE_CRHONE is not set
61# CONFIG_SNI_RM is not set
62# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set
64# CONFIG_TOSHIBA_RBTX4938 is not set
65# CONFIG_EVB_PCI1 is not set
66CONFIG_RWSEM_GENERIC_SPINLOCK=y
67# CONFIG_ARCH_HAS_ILOG2_U32 is not set
68# CONFIG_ARCH_HAS_ILOG2_U64 is not set
69CONFIG_GENERIC_FIND_NEXT_BIT=y
70CONFIG_GENERIC_HWEIGHT=y
71CONFIG_GENERIC_CALIBRATE_DELAY=y
72CONFIG_GENERIC_TIME=y
73CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
74# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
75CONFIG_DMA_NONCOHERENT=y
76CONFIG_DMA_NEED_PCI_MAP_STATE=y
77CONFIG_CPU_BIG_ENDIAN=y
78# CONFIG_CPU_LITTLE_ENDIAN is not set
79CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
80CONFIG_MIPS_GT64120=y
81# CONFIG_SYSCLK_75 is not set
82# CONFIG_SYSCLK_83 is not set
83CONFIG_SYSCLK_100=y
84CONFIG_MIPS_L1_CACHE_SHIFT=5
85
86#
87# CPU selection
88#
89# CONFIG_CPU_MIPS32_R1 is not set
90# CONFIG_CPU_MIPS32_R2 is not set
91# CONFIG_CPU_MIPS64_R1 is not set
92# CONFIG_CPU_MIPS64_R2 is not set
93# CONFIG_CPU_R3000 is not set
94# CONFIG_CPU_TX39XX is not set
95# CONFIG_CPU_VR41XX is not set
96# CONFIG_CPU_R4300 is not set
97# CONFIG_CPU_R4X00 is not set
98# CONFIG_CPU_TX49XX is not set
99CONFIG_CPU_R5000=y
100# CONFIG_CPU_R5432 is not set
101# CONFIG_CPU_R6000 is not set
102# CONFIG_CPU_NEVADA is not set
103# CONFIG_CPU_R8000 is not set
104# CONFIG_CPU_R10000 is not set
105# CONFIG_CPU_RM7000 is not set
106# CONFIG_CPU_RM9000 is not set
107# CONFIG_CPU_SB1 is not set
108CONFIG_SYS_HAS_CPU_R5000=y
109CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
110CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
111CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
112CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
113
114#
115# Kernel type
116#
117CONFIG_32BIT=y
118# CONFIG_64BIT is not set
119CONFIG_PAGE_SIZE_4KB=y
120# CONFIG_PAGE_SIZE_8KB is not set
121# CONFIG_PAGE_SIZE_16KB is not set
122# CONFIG_PAGE_SIZE_64KB is not set
123CONFIG_MIPS_MT_DISABLED=y
124# CONFIG_MIPS_MT_SMP is not set
125# CONFIG_MIPS_MT_SMTC is not set
126# CONFIG_MIPS_VPE_LOADER is not set
127# CONFIG_64BIT_PHYS_ADDR is not set
128CONFIG_CPU_HAS_LLSC=y
129CONFIG_CPU_HAS_SYNC=y
130CONFIG_GENERIC_HARDIRQS=y
131CONFIG_GENERIC_IRQ_PROBE=y
132CONFIG_ARCH_FLATMEM_ENABLE=y
133CONFIG_SELECT_MEMORY_MODEL=y
134CONFIG_FLATMEM_MANUAL=y
135# CONFIG_DISCONTIGMEM_MANUAL is not set
136# CONFIG_SPARSEMEM_MANUAL is not set
137CONFIG_FLATMEM=y
138CONFIG_FLAT_NODE_MEM_MAP=y
139# CONFIG_SPARSEMEM_STATIC is not set
140CONFIG_SPLIT_PTLOCK_CPUS=4
141# CONFIG_RESOURCES_64BIT is not set
142CONFIG_ZONE_DMA_FLAG=1
143# CONFIG_HZ_48 is not set
144# CONFIG_HZ_100 is not set
145# CONFIG_HZ_128 is not set
146# CONFIG_HZ_250 is not set
147# CONFIG_HZ_256 is not set
148CONFIG_HZ_1000=y
149# CONFIG_HZ_1024 is not set
150CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
151CONFIG_HZ=1000
152CONFIG_PREEMPT_NONE=y
153# CONFIG_PREEMPT_VOLUNTARY is not set
154# CONFIG_PREEMPT is not set
155# CONFIG_KEXEC is not set
156CONFIG_LOCKDEP_SUPPORT=y
157CONFIG_STACKTRACE_SUPPORT=y
158CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
159
160#
161# Code maturity level options
162#
163CONFIG_EXPERIMENTAL=y
164CONFIG_BROKEN_ON_SMP=y
165CONFIG_INIT_ENV_ARG_LIMIT=32
166
167#
168# General setup
169#
170CONFIG_LOCALVERSION=""
171CONFIG_LOCALVERSION_AUTO=y
172CONFIG_SWAP=y
173CONFIG_SYSVIPC=y
174# CONFIG_IPC_NS is not set
175CONFIG_SYSVIPC_SYSCTL=y
176# CONFIG_POSIX_MQUEUE is not set
177# CONFIG_BSD_PROCESS_ACCT is not set
178# CONFIG_TASKSTATS is not set
179# CONFIG_UTS_NS is not set
180# CONFIG_AUDIT is not set
181# CONFIG_IKCONFIG is not set
182CONFIG_SYSFS_DEPRECATED=y
183CONFIG_RELAY=y
184# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
185CONFIG_SYSCTL=y
186CONFIG_EMBEDDED=y
187CONFIG_SYSCTL_SYSCALL=y
188CONFIG_KALLSYMS=y
189# CONFIG_KALLSYMS_EXTRA_PASS is not set
190CONFIG_HOTPLUG=y
191CONFIG_PRINTK=y
192CONFIG_BUG=y
193CONFIG_ELF_CORE=y
194CONFIG_BASE_FULL=y
195CONFIG_FUTEX=y
196CONFIG_EPOLL=y
197CONFIG_SHMEM=y
198CONFIG_SLAB=y
199CONFIG_VM_EVENT_COUNTERS=y
200CONFIG_RT_MUTEXES=y
201# CONFIG_TINY_SHMEM is not set
202CONFIG_BASE_SMALL=0
203# CONFIG_SLOB is not set
204
205#
206# Loadable module support
207#
208CONFIG_MODULES=y
209CONFIG_MODULE_UNLOAD=y
210# CONFIG_MODULE_FORCE_UNLOAD is not set
211CONFIG_MODVERSIONS=y
212CONFIG_MODULE_SRCVERSION_ALL=y
213# CONFIG_KMOD is not set
214
215#
216# Block layer
217#
218CONFIG_BLOCK=y
219# CONFIG_LBD is not set
220# CONFIG_BLK_DEV_IO_TRACE is not set
221# CONFIG_LSF is not set
222
223#
224# IO Schedulers
225#
226CONFIG_IOSCHED_NOOP=y
227CONFIG_IOSCHED_AS=y
228CONFIG_IOSCHED_DEADLINE=y
229CONFIG_IOSCHED_CFQ=y
230CONFIG_DEFAULT_AS=y
231# CONFIG_DEFAULT_DEADLINE is not set
232# CONFIG_DEFAULT_CFQ is not set
233# CONFIG_DEFAULT_NOOP is not set
234CONFIG_DEFAULT_IOSCHED="anticipatory"
235
236#
237# Bus options (PCI, PCMCIA, EISA, ISA, TC)
238#
239CONFIG_HW_HAS_PCI=y
240CONFIG_PCI=y
241CONFIG_MMU=y
242
243#
244# PCCARD (PCMCIA/CardBus) support
245#
246# CONFIG_PCCARD is not set
247
248#
249# PCI Hotplug Support
250#
251# CONFIG_HOTPLUG_PCI is not set
252
253#
254# Executable file formats
255#
256CONFIG_BINFMT_ELF=y
257# CONFIG_BINFMT_MISC is not set
258CONFIG_TRAD_SIGNALS=y
259
260#
261# Power management options
262#
263CONFIG_PM=y
264# CONFIG_PM_LEGACY is not set
265# CONFIG_PM_DEBUG is not set
266# CONFIG_PM_SYSFS_DEPRECATED is not set
267
268#
269# Networking
270#
271CONFIG_NET=y
272
273#
274# Networking options
275#
276# CONFIG_NETDEBUG is not set
277# CONFIG_PACKET is not set
278CONFIG_UNIX=y
279CONFIG_XFRM=y
280CONFIG_XFRM_USER=m
281# CONFIG_XFRM_SUB_POLICY is not set
282CONFIG_XFRM_MIGRATE=y
283CONFIG_NET_KEY=y
284CONFIG_NET_KEY_MIGRATE=y
285CONFIG_INET=y
286# CONFIG_IP_MULTICAST is not set
287# CONFIG_IP_ADVANCED_ROUTER is not set
288CONFIG_IP_FIB_HASH=y
289CONFIG_IP_PNP=y
290# CONFIG_IP_PNP_DHCP is not set
291# CONFIG_IP_PNP_BOOTP is not set
292# CONFIG_IP_PNP_RARP is not set
293# CONFIG_NET_IPIP is not set
294# CONFIG_NET_IPGRE is not set
295# CONFIG_ARPD is not set
296# CONFIG_SYN_COOKIES is not set
297# CONFIG_INET_AH is not set
298# CONFIG_INET_ESP is not set
299# CONFIG_INET_IPCOMP is not set
300# CONFIG_INET_XFRM_TUNNEL is not set
301# CONFIG_INET_TUNNEL is not set
302CONFIG_INET_XFRM_MODE_TRANSPORT=m
303CONFIG_INET_XFRM_MODE_TUNNEL=m
304CONFIG_INET_XFRM_MODE_BEET=m
305CONFIG_INET_DIAG=y
306CONFIG_INET_TCP_DIAG=y
307# CONFIG_TCP_CONG_ADVANCED is not set
308CONFIG_TCP_CONG_CUBIC=y
309CONFIG_DEFAULT_TCP_CONG="cubic"
310CONFIG_TCP_MD5SIG=y
311# CONFIG_IPV6 is not set
312# CONFIG_INET6_XFRM_TUNNEL is not set
313# CONFIG_INET6_TUNNEL is not set
314CONFIG_NETWORK_SECMARK=y
315# CONFIG_NETFILTER is not set
316
317#
318# DCCP Configuration (EXPERIMENTAL)
319#
320# CONFIG_IP_DCCP is not set
321
322#
323# SCTP Configuration (EXPERIMENTAL)
324#
325# CONFIG_IP_SCTP is not set
326
327#
328# TIPC Configuration (EXPERIMENTAL)
329#
330# CONFIG_TIPC is not set
331# CONFIG_ATM is not set
332# CONFIG_BRIDGE is not set
333# CONFIG_VLAN_8021Q is not set
334# CONFIG_DECNET is not set
335# CONFIG_LLC2 is not set
336# CONFIG_IPX is not set
337# CONFIG_ATALK is not set
338# CONFIG_X25 is not set
339# CONFIG_LAPB is not set
340# CONFIG_ECONET is not set
341# CONFIG_WAN_ROUTER is not set
342
343#
344# QoS and/or fair queueing
345#
346# CONFIG_NET_SCHED is not set
347
348#
349# Network testing
350#
351# CONFIG_NET_PKTGEN is not set
352# CONFIG_HAMRADIO is not set
353# CONFIG_IRDA is not set
354# CONFIG_BT is not set
355CONFIG_IEEE80211=m
356# CONFIG_IEEE80211_DEBUG is not set
357CONFIG_IEEE80211_CRYPT_WEP=m
358CONFIG_IEEE80211_CRYPT_CCMP=m
359CONFIG_IEEE80211_SOFTMAC=m
360# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
361CONFIG_WIRELESS_EXT=y
362
363#
364# Device Drivers
365#
366
367#
368# Generic Driver Options
369#
370CONFIG_STANDALONE=y
371CONFIG_PREVENT_FIRMWARE_BUILD=y
372CONFIG_FW_LOADER=m
373# CONFIG_SYS_HYPERVISOR is not set
374
375#
376# Connector - unified userspace <-> kernelspace linker
377#
378CONFIG_CONNECTOR=m
379
380#
381# Memory Technology Devices (MTD)
382#
383# CONFIG_MTD is not set
384
385#
386# Parallel port support
387#
388# CONFIG_PARPORT is not set
389
390#
391# Plug and Play support
392#
393# CONFIG_PNPACPI is not set
394
395#
396# Block devices
397#
398# CONFIG_BLK_CPQ_DA is not set
399# CONFIG_BLK_CPQ_CISS_DA is not set
400# CONFIG_BLK_DEV_DAC960 is not set
401# CONFIG_BLK_DEV_UMEM is not set
402# CONFIG_BLK_DEV_COW_COMMON is not set
403# CONFIG_BLK_DEV_LOOP is not set
404# CONFIG_BLK_DEV_NBD is not set
405# CONFIG_BLK_DEV_SX8 is not set
406# CONFIG_BLK_DEV_RAM is not set
407# CONFIG_BLK_DEV_INITRD is not set
408CONFIG_CDROM_PKTCDVD=m
409CONFIG_CDROM_PKTCDVD_BUFFERS=8
410# CONFIG_CDROM_PKTCDVD_WCACHE is not set
411CONFIG_ATA_OVER_ETH=m
412
413#
414# Misc devices
415#
416CONFIG_SGI_IOC4=m
417# CONFIG_TIFM_CORE is not set
418
419#
420# ATA/ATAPI/MFM/RLL support
421#
422# CONFIG_IDE is not set
423
424#
425# SCSI device support
426#
427CONFIG_RAID_ATTRS=m
428# CONFIG_SCSI is not set
429# CONFIG_SCSI_NETLINK is not set
430
431#
432# Serial ATA (prod) and Parallel ATA (experimental) drivers
433#
434# CONFIG_ATA is not set
435
436#
437# Multi-device support (RAID and LVM)
438#
439# CONFIG_MD is not set
440
441#
442# Fusion MPT device support
443#
444# CONFIG_FUSION is not set
445
446#
447# IEEE 1394 (FireWire) support
448#
449# CONFIG_IEEE1394 is not set
450
451#
452# I2O device support
453#
454# CONFIG_I2O is not set
455
456#
457# Network device support
458#
459CONFIG_NETDEVICES=y
460# CONFIG_DUMMY is not set
461# CONFIG_BONDING is not set
462# CONFIG_EQUALIZER is not set
463# CONFIG_TUN is not set
464
465#
466# ARCnet devices
467#
468# CONFIG_ARCNET is not set
469
470#
471# PHY device support
472#
473CONFIG_PHYLIB=m
474
475#
476# MII PHY device drivers
477#
478CONFIG_MARVELL_PHY=m
479CONFIG_DAVICOM_PHY=m
480CONFIG_QSEMI_PHY=m
481CONFIG_LXT_PHY=m
482CONFIG_CICADA_PHY=m
483CONFIG_VITESSE_PHY=m
484CONFIG_SMSC_PHY=m
485# CONFIG_BROADCOM_PHY is not set
486# CONFIG_FIXED_PHY is not set
487
488#
489# Ethernet (10 or 100Mbit)
490#
491CONFIG_NET_ETHERNET=y
492# CONFIG_MII is not set
493# CONFIG_HAPPYMEAL is not set
494# CONFIG_SUNGEM is not set
495# CONFIG_CASSINI is not set
496# CONFIG_NET_VENDOR_3COM is not set
497# CONFIG_DM9000 is not set
498
499#
500# Tulip family network device support
501#
502# CONFIG_NET_TULIP is not set
503# CONFIG_HP100 is not set
504# CONFIG_NET_PCI is not set
505
506#
507# Ethernet (1000 Mbit)
508#
509# CONFIG_ACENIC is not set
510# CONFIG_DL2K is not set
511# CONFIG_E1000 is not set
512# CONFIG_NS83820 is not set
513# CONFIG_HAMACHI is not set
514# CONFIG_YELLOWFIN is not set
515# CONFIG_R8169 is not set
516# CONFIG_SIS190 is not set
517# CONFIG_SKGE is not set
518# CONFIG_SKY2 is not set
519# CONFIG_SK98LIN is not set
520# CONFIG_TIGON3 is not set
521# CONFIG_BNX2 is not set
522CONFIG_QLA3XXX=m
523# CONFIG_ATL1 is not set
524
525#
526# Ethernet (10000 Mbit)
527#
528# CONFIG_CHELSIO_T1 is not set
529CONFIG_CHELSIO_T3=m
530# CONFIG_IXGB is not set
531# CONFIG_S2IO is not set
532# CONFIG_MYRI10GE is not set
533CONFIG_NETXEN_NIC=m
534
535#
536# Token Ring devices
537#
538# CONFIG_TR is not set
539
540#
541# Wireless LAN (non-hamradio)
542#
543# CONFIG_NET_RADIO is not set
544
545#
546# Wan interfaces
547#
548# CONFIG_WAN is not set
549# CONFIG_FDDI is not set
550# CONFIG_HIPPI is not set
551CONFIG_PPP=y
552# CONFIG_PPP_MULTILINK is not set
553# CONFIG_PPP_FILTER is not set
554CONFIG_PPP_ASYNC=y
555# CONFIG_PPP_SYNC_TTY is not set
556# CONFIG_PPP_DEFLATE is not set
557# CONFIG_PPP_BSDCOMP is not set
558CONFIG_PPP_MPPE=m
559# CONFIG_PPPOE is not set
560# CONFIG_SLIP is not set
561CONFIG_SLHC=y
562# CONFIG_SHAPER is not set
563# CONFIG_NETCONSOLE is not set
564# CONFIG_NETPOLL is not set
565# CONFIG_NET_POLL_CONTROLLER is not set
566
567#
568# ISDN subsystem
569#
570# CONFIG_ISDN is not set
571
572#
573# Telephony Support
574#
575# CONFIG_PHONE is not set
576
577#
578# Input device support
579#
580CONFIG_INPUT=y
581# CONFIG_INPUT_FF_MEMLESS is not set
582
583#
584# Userland interfaces
585#
586CONFIG_INPUT_MOUSEDEV=y
587CONFIG_INPUT_MOUSEDEV_PSAUX=y
588CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
589CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
590# CONFIG_INPUT_JOYDEV is not set
591# CONFIG_INPUT_TSDEV is not set
592# CONFIG_INPUT_EVDEV is not set
593# CONFIG_INPUT_EVBUG is not set
594
595#
596# Input Device Drivers
597#
598# CONFIG_INPUT_KEYBOARD is not set
599# CONFIG_INPUT_MOUSE is not set
600# CONFIG_INPUT_JOYSTICK is not set
601# CONFIG_INPUT_TOUCHSCREEN is not set
602# CONFIG_INPUT_MISC is not set
603
604#
605# Hardware I/O ports
606#
607CONFIG_SERIO=y
608# CONFIG_SERIO_I8042 is not set
609CONFIG_SERIO_SERPORT=y
610# CONFIG_SERIO_PCIPS2 is not set
611# CONFIG_SERIO_LIBPS2 is not set
612CONFIG_SERIO_RAW=m
613# CONFIG_GAMEPORT is not set
614
615#
616# Character devices
617#
618CONFIG_VT=y
619CONFIG_VT_CONSOLE=y
620CONFIG_HW_CONSOLE=y
621CONFIG_VT_HW_CONSOLE_BINDING=y
622# CONFIG_SERIAL_NONSTANDARD is not set
623
624#
625# Serial drivers
626#
627CONFIG_SERIAL_8250=y
628CONFIG_SERIAL_8250_CONSOLE=y
629CONFIG_SERIAL_8250_PCI=y
630CONFIG_SERIAL_8250_NR_UARTS=4
631CONFIG_SERIAL_8250_RUNTIME_UARTS=4
632# CONFIG_SERIAL_8250_EXTENDED is not set
633
634#
635# Non-8250 serial port support
636#
637CONFIG_SERIAL_CORE=y
638CONFIG_SERIAL_CORE_CONSOLE=y
639# CONFIG_SERIAL_JSM is not set
640CONFIG_UNIX98_PTYS=y
641CONFIG_LEGACY_PTYS=y
642CONFIG_LEGACY_PTY_COUNT=256
643
644#
645# IPMI
646#
647# CONFIG_IPMI_HANDLER is not set
648
649#
650# Watchdog Cards
651#
652# CONFIG_WATCHDOG is not set
653# CONFIG_HW_RANDOM is not set
654# CONFIG_RTC is not set
655# CONFIG_GEN_RTC is not set
656# CONFIG_DTLK is not set
657# CONFIG_R3964 is not set
658# CONFIG_APPLICOM is not set
659# CONFIG_DRM is not set
660# CONFIG_RAW_DRIVER is not set
661
662#
663# TPM devices
664#
665# CONFIG_TCG_TPM is not set
666
667#
668# I2C support
669#
670# CONFIG_I2C is not set
671
672#
673# SPI support
674#
675# CONFIG_SPI is not set
676# CONFIG_SPI_MASTER is not set
677
678#
679# Dallas's 1-wire bus
680#
681# CONFIG_W1 is not set
682
683#
684# Hardware Monitoring support
685#
686# CONFIG_HWMON is not set
687# CONFIG_HWMON_VID is not set
688
689#
690# Multimedia devices
691#
692# CONFIG_VIDEO_DEV is not set
693
694#
695# Digital Video Broadcasting Devices
696#
697# CONFIG_DVB is not set
698
699#
700# Graphics support
701#
702# CONFIG_FIRMWARE_EDID is not set
703# CONFIG_FB is not set
704
705#
706# Console display driver support
707#
708# CONFIG_VGA_CONSOLE is not set
709CONFIG_DUMMY_CONSOLE=y
710# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
711
712#
713# Sound
714#
715# CONFIG_SOUND is not set
716
717#
718# HID Devices
719#
720# CONFIG_HID is not set
721
722#
723# USB support
724#
725CONFIG_USB_ARCH_HAS_HCD=y
726CONFIG_USB_ARCH_HAS_OHCI=y
727CONFIG_USB_ARCH_HAS_EHCI=y
728# CONFIG_USB is not set
729
730#
731# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
732#
733
734#
735# USB Gadget Support
736#
737# CONFIG_USB_GADGET is not set
738
739#
740# MMC/SD Card support
741#
742# CONFIG_MMC is not set
743
744#
745# LED devices
746#
747# CONFIG_NEW_LEDS is not set
748
749#
750# LED drivers
751#
752
753#
754# LED Triggers
755#
756
757#
758# InfiniBand support
759#
760# CONFIG_INFINIBAND is not set
761
762#
763# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
764#
765
766#
767# Real Time Clock
768#
769# CONFIG_RTC_CLASS is not set
770
771#
772# DMA Engine support
773#
774# CONFIG_DMA_ENGINE is not set
775
776#
777# DMA Clients
778#
779
780#
781# DMA Devices
782#
783
784#
785# Auxiliary Display support
786#
787
788#
789# Virtualization
790#
791
792#
793# File systems
794#
795CONFIG_EXT2_FS=y
796# CONFIG_EXT2_FS_XATTR is not set
797# CONFIG_EXT2_FS_XIP is not set
798# CONFIG_EXT3_FS is not set
799# CONFIG_EXT4DEV_FS is not set
800# CONFIG_REISERFS_FS is not set
801# CONFIG_JFS_FS is not set
802# CONFIG_FS_POSIX_ACL is not set
803# CONFIG_XFS_FS is not set
804# CONFIG_GFS2_FS is not set
805# CONFIG_OCFS2_FS is not set
806# CONFIG_MINIX_FS is not set
807# CONFIG_ROMFS_FS is not set
808CONFIG_INOTIFY=y
809CONFIG_INOTIFY_USER=y
810# CONFIG_QUOTA is not set
811CONFIG_DNOTIFY=y
812# CONFIG_AUTOFS_FS is not set
813# CONFIG_AUTOFS4_FS is not set
814CONFIG_FUSE_FS=m
815
816#
817# CD-ROM/DVD Filesystems
818#
819# CONFIG_ISO9660_FS is not set
820# CONFIG_UDF_FS is not set
821
822#
823# DOS/FAT/NT Filesystems
824#
825# CONFIG_MSDOS_FS is not set
826# CONFIG_VFAT_FS is not set
827# CONFIG_NTFS_FS is not set
828
829#
830# Pseudo filesystems
831#
832CONFIG_PROC_FS=y
833CONFIG_PROC_KCORE=y
834CONFIG_PROC_SYSCTL=y
835CONFIG_SYSFS=y
836# CONFIG_TMPFS is not set
837# CONFIG_HUGETLB_PAGE is not set
838CONFIG_RAMFS=y
839CONFIG_CONFIGFS_FS=m
840
841#
842# Miscellaneous filesystems
843#
844# CONFIG_ADFS_FS is not set
845# CONFIG_AFFS_FS is not set
846# CONFIG_ECRYPT_FS is not set
847# CONFIG_HFS_FS is not set
848# CONFIG_HFSPLUS_FS is not set
849# CONFIG_BEFS_FS is not set
850# CONFIG_BFS_FS is not set
851# CONFIG_EFS_FS is not set
852# CONFIG_CRAMFS is not set
853# CONFIG_VXFS_FS is not set
854# CONFIG_HPFS_FS is not set
855# CONFIG_QNX4FS_FS is not set
856# CONFIG_SYSV_FS is not set
857# CONFIG_UFS_FS is not set
858
859#
860# Network File Systems
861#
862CONFIG_NFS_FS=y
863# CONFIG_NFS_V3 is not set
864# CONFIG_NFS_V4 is not set
865# CONFIG_NFS_DIRECTIO is not set
866# CONFIG_NFSD is not set
867CONFIG_ROOT_NFS=y
868CONFIG_LOCKD=y
869CONFIG_NFS_COMMON=y
870CONFIG_SUNRPC=y
871# CONFIG_RPCSEC_GSS_KRB5 is not set
872# CONFIG_RPCSEC_GSS_SPKM3 is not set
873# CONFIG_SMB_FS is not set
874# CONFIG_CIFS is not set
875# CONFIG_NCP_FS is not set
876# CONFIG_CODA_FS is not set
877# CONFIG_AFS_FS is not set
878# CONFIG_9P_FS is not set
879
880#
881# Partition Types
882#
883# CONFIG_PARTITION_ADVANCED is not set
884CONFIG_MSDOS_PARTITION=y
885
886#
887# Native Language Support
888#
889# CONFIG_NLS is not set
890
891#
892# Distributed Lock Manager
893#
894CONFIG_DLM=m
895CONFIG_DLM_TCP=y
896# CONFIG_DLM_SCTP is not set
897# CONFIG_DLM_DEBUG is not set
898
899#
900# Profiling support
901#
902# CONFIG_PROFILING is not set
903
904#
905# Kernel hacking
906#
907CONFIG_TRACE_IRQFLAGS_SUPPORT=y
908# CONFIG_PRINTK_TIME is not set
909CONFIG_ENABLE_MUST_CHECK=y
910# CONFIG_MAGIC_SYSRQ is not set
911# CONFIG_UNUSED_SYMBOLS is not set
912# CONFIG_DEBUG_FS is not set
913# CONFIG_HEADERS_CHECK is not set
914# CONFIG_DEBUG_KERNEL is not set
915CONFIG_LOG_BUF_SHIFT=14
916CONFIG_CROSSCOMPILE=y
917CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw nfsroot=192.168.1.1:/mnt/disk2/fs.gal ip=192.168.1.211:192.168.1.1:::gt::"
918CONFIG_SYS_SUPPORTS_KGDB=y
919
920#
921# Security options
922#
923CONFIG_KEYS=y
924CONFIG_KEYS_DEBUG_PROC_KEYS=y
925# CONFIG_SECURITY is not set
926
927#
928# Cryptographic options
929#
930CONFIG_CRYPTO=y
931CONFIG_CRYPTO_ALGAPI=y
932CONFIG_CRYPTO_BLKCIPHER=m
933CONFIG_CRYPTO_HASH=y
934CONFIG_CRYPTO_MANAGER=y
935CONFIG_CRYPTO_HMAC=y
936CONFIG_CRYPTO_XCBC=m
937CONFIG_CRYPTO_NULL=m
938CONFIG_CRYPTO_MD4=m
939CONFIG_CRYPTO_MD5=y
940CONFIG_CRYPTO_SHA1=m
941CONFIG_CRYPTO_SHA256=m
942CONFIG_CRYPTO_SHA512=m
943CONFIG_CRYPTO_WP512=m
944CONFIG_CRYPTO_TGR192=m
945CONFIG_CRYPTO_GF128MUL=m
946CONFIG_CRYPTO_ECB=m
947CONFIG_CRYPTO_CBC=m
948CONFIG_CRYPTO_PCBC=m
949CONFIG_CRYPTO_LRW=m
950CONFIG_CRYPTO_DES=m
951CONFIG_CRYPTO_FCRYPT=m
952CONFIG_CRYPTO_BLOWFISH=m
953CONFIG_CRYPTO_TWOFISH=m
954CONFIG_CRYPTO_TWOFISH_COMMON=m
955CONFIG_CRYPTO_SERPENT=m
956CONFIG_CRYPTO_AES=m
957CONFIG_CRYPTO_CAST5=m
958CONFIG_CRYPTO_CAST6=m
959CONFIG_CRYPTO_TEA=m
960CONFIG_CRYPTO_ARC4=m
961CONFIG_CRYPTO_KHAZAD=m
962CONFIG_CRYPTO_ANUBIS=m
963CONFIG_CRYPTO_DEFLATE=m
964CONFIG_CRYPTO_MICHAEL_MIC=m
965CONFIG_CRYPTO_CRC32C=m
966CONFIG_CRYPTO_CAMELLIA=m
967# CONFIG_CRYPTO_TEST is not set
968
969#
970# Hardware crypto devices
971#
972
973#
974# Library routines
975#
976CONFIG_BITREVERSE=m
977CONFIG_CRC_CCITT=y
978CONFIG_CRC16=m
979CONFIG_CRC32=m
980CONFIG_LIBCRC32C=m
981CONFIG_ZLIB_INFLATE=m
982CONFIG_ZLIB_DEFLATE=m
983CONFIG_PLIST=y
984CONFIG_HAS_IOMEM=y
985CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 460d7a26a8ba..69810592aa6b 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -26,9 +26,7 @@ CONFIG_BASLER_EXCITE=y
26# CONFIG_BASLER_EXCITE_PROTOTYPE is not set 26# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_BASLER_EXCITE=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig
new file mode 100644
index 000000000000..6ab94d8cf08b
--- /dev/null
+++ b/arch/mips/configs/fulong_defconfig
@@ -0,0 +1,1765 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22-rc4
4# Mon Jun 11 00:23:51 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_LEMOTE_FULONG=y
12# CONFIG_MACH_ALCHEMY is not set
13# CONFIG_BASLER_EXCITE is not set
14# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set
17# CONFIG_MIPS_ATLAS is not set
18# CONFIG_MIPS_MALTA is not set
19# CONFIG_MIPS_SEAD is not set
20# CONFIG_WR_PPMC is not set
21# CONFIG_MIPS_SIM is not set
22# CONFIG_MOMENCO_OCELOT is not set
23# CONFIG_PNX8550_JBS is not set
24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_DDB5477 is not set
26# CONFIG_MACH_VR41XX is not set
27# CONFIG_PMC_YOSEMITE is not set
28# CONFIG_QEMU is not set
29# CONFIG_MARKEINS is not set
30# CONFIG_SGI_IP22 is not set
31# CONFIG_SGI_IP27 is not set
32# CONFIG_SGI_IP32 is not set
33# CONFIG_SIBYTE_BIGSUR is not set
34# CONFIG_SIBYTE_SWARM is not set
35# CONFIG_SIBYTE_SENTOSA is not set
36# CONFIG_SIBYTE_RHONE is not set
37# CONFIG_SIBYTE_CARMEL is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_LITTLESUR is not set
40# CONFIG_SIBYTE_CRHINE is not set
41# CONFIG_SIBYTE_CRHONE is not set
42# CONFIG_SNI_RM is not set
43# CONFIG_TOSHIBA_JMR3927 is not set
44# CONFIG_TOSHIBA_RBTX4927 is not set
45# CONFIG_TOSHIBA_RBTX4938 is not set
46CONFIG_RWSEM_GENERIC_SPINLOCK=y
47# CONFIG_ARCH_HAS_ILOG2_U32 is not set
48# CONFIG_ARCH_HAS_ILOG2_U64 is not set
49CONFIG_GENERIC_FIND_NEXT_BIT=y
50CONFIG_GENERIC_HWEIGHT=y
51CONFIG_GENERIC_CALIBRATE_DELAY=y
52CONFIG_GENERIC_TIME=y
53CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
54CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
55CONFIG_DMA_NONCOHERENT=y
56CONFIG_DMA_NEED_PCI_MAP_STATE=y
57CONFIG_EARLY_PRINTK=y
58CONFIG_SYS_HAS_EARLY_PRINTK=y
59CONFIG_I8259=y
60# CONFIG_NO_IOPORT is not set
61# CONFIG_CPU_BIG_ENDIAN is not set
62CONFIG_CPU_LITTLE_ENDIAN=y
63CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
64CONFIG_IRQ_CPU=y
65CONFIG_BOOT_ELF32=y
66CONFIG_MIPS_L1_CACHE_SHIFT=5
67
68#
69# CPU selection
70#
71CONFIG_CPU_LOONGSON2=y
72# CONFIG_CPU_MIPS32_R1 is not set
73# CONFIG_CPU_MIPS32_R2 is not set
74# CONFIG_CPU_MIPS64_R1 is not set
75# CONFIG_CPU_MIPS64_R2 is not set
76# CONFIG_CPU_R3000 is not set
77# CONFIG_CPU_TX39XX is not set
78# CONFIG_CPU_VR41XX is not set
79# CONFIG_CPU_R4300 is not set
80# CONFIG_CPU_R4X00 is not set
81# CONFIG_CPU_TX49XX is not set
82# CONFIG_CPU_R5000 is not set
83# CONFIG_CPU_R5432 is not set
84# CONFIG_CPU_R6000 is not set
85# CONFIG_CPU_NEVADA is not set
86# CONFIG_CPU_R8000 is not set
87# CONFIG_CPU_R10000 is not set
88# CONFIG_CPU_RM7000 is not set
89# CONFIG_CPU_RM9000 is not set
90# CONFIG_CPU_SB1 is not set
91CONFIG_SYS_HAS_CPU_LOONGSON2=y
92CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
93CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
94CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
95CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
96
97#
98# Kernel type
99#
100# CONFIG_32BIT is not set
101CONFIG_64BIT=y
102# CONFIG_PAGE_SIZE_4KB is not set
103# CONFIG_PAGE_SIZE_8KB is not set
104CONFIG_PAGE_SIZE_16KB=y
105# CONFIG_PAGE_SIZE_64KB is not set
106CONFIG_BOARD_SCACHE=y
107CONFIG_MIPS_MT_DISABLED=y
108# CONFIG_MIPS_MT_SMP is not set
109# CONFIG_MIPS_MT_SMTC is not set
110# CONFIG_MIPS_VPE_LOADER is not set
111CONFIG_CPU_HAS_WB=y
112CONFIG_CPU_HAS_SYNC=y
113CONFIG_GENERIC_HARDIRQS=y
114CONFIG_GENERIC_IRQ_PROBE=y
115CONFIG_CPU_SUPPORTS_HIGHMEM=y
116CONFIG_SYS_SUPPORTS_HIGHMEM=y
117CONFIG_ARCH_FLATMEM_ENABLE=y
118CONFIG_ARCH_SPARSEMEM_ENABLE=y
119CONFIG_SELECT_MEMORY_MODEL=y
120CONFIG_FLATMEM_MANUAL=y
121# CONFIG_DISCONTIGMEM_MANUAL is not set
122# CONFIG_SPARSEMEM_MANUAL is not set
123CONFIG_FLATMEM=y
124CONFIG_FLAT_NODE_MEM_MAP=y
125CONFIG_SPARSEMEM_STATIC=y
126CONFIG_SPLIT_PTLOCK_CPUS=4
127CONFIG_RESOURCES_64BIT=y
128CONFIG_ZONE_DMA_FLAG=0
129# CONFIG_HZ_48 is not set
130# CONFIG_HZ_100 is not set
131# CONFIG_HZ_128 is not set
132CONFIG_HZ_250=y
133# CONFIG_HZ_256 is not set
134# CONFIG_HZ_1000 is not set
135# CONFIG_HZ_1024 is not set
136CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
137CONFIG_HZ=250
138# CONFIG_PREEMPT_NONE is not set
139CONFIG_PREEMPT_VOLUNTARY=y
140# CONFIG_PREEMPT is not set
141# CONFIG_KEXEC is not set
142CONFIG_LOCKDEP_SUPPORT=y
143CONFIG_STACKTRACE_SUPPORT=y
144CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
145
146#
147# Code maturity level options
148#
149CONFIG_EXPERIMENTAL=y
150CONFIG_BROKEN_ON_SMP=y
151CONFIG_INIT_ENV_ARG_LIMIT=32
152
153#
154# General setup
155#
156CONFIG_LOCALVERSION="lm32"
157# CONFIG_LOCALVERSION_AUTO is not set
158CONFIG_SWAP=y
159CONFIG_SYSVIPC=y
160# CONFIG_IPC_NS is not set
161CONFIG_SYSVIPC_SYSCTL=y
162CONFIG_POSIX_MQUEUE=y
163CONFIG_BSD_PROCESS_ACCT=y
164# CONFIG_BSD_PROCESS_ACCT_V3 is not set
165# CONFIG_TASKSTATS is not set
166# CONFIG_UTS_NS is not set
167# CONFIG_AUDIT is not set
168CONFIG_IKCONFIG=y
169CONFIG_IKCONFIG_PROC=y
170CONFIG_LOG_BUF_SHIFT=14
171CONFIG_SYSFS_DEPRECATED=y
172# CONFIG_RELAY is not set
173# CONFIG_BLK_DEV_INITRD is not set
174# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
175CONFIG_SYSCTL=y
176CONFIG_EMBEDDED=y
177CONFIG_SYSCTL_SYSCALL=y
178CONFIG_KALLSYMS=y
179# CONFIG_KALLSYMS_EXTRA_PASS is not set
180CONFIG_HOTPLUG=y
181CONFIG_PRINTK=y
182CONFIG_BUG=y
183CONFIG_ELF_CORE=y
184CONFIG_BASE_FULL=y
185CONFIG_FUTEX=y
186CONFIG_ANON_INODES=y
187CONFIG_EPOLL=y
188CONFIG_SIGNALFD=y
189CONFIG_TIMERFD=y
190CONFIG_EVENTFD=y
191CONFIG_SHMEM=y
192CONFIG_VM_EVENT_COUNTERS=y
193CONFIG_SLAB=y
194# CONFIG_SLUB is not set
195# CONFIG_SLOB is not set
196CONFIG_RT_MUTEXES=y
197# CONFIG_TINY_SHMEM is not set
198CONFIG_BASE_SMALL=0
199
200#
201# Loadable module support
202#
203CONFIG_MODULES=y
204CONFIG_MODULE_UNLOAD=y
205CONFIG_MODULE_FORCE_UNLOAD=y
206# CONFIG_MODVERSIONS is not set
207# CONFIG_MODULE_SRCVERSION_ALL is not set
208CONFIG_KMOD=y
209
210#
211# Block layer
212#
213CONFIG_BLOCK=y
214# CONFIG_BLK_DEV_IO_TRACE is not set
215
216#
217# IO Schedulers
218#
219CONFIG_IOSCHED_NOOP=y
220CONFIG_IOSCHED_AS=y
221CONFIG_IOSCHED_DEADLINE=y
222CONFIG_IOSCHED_CFQ=y
223# CONFIG_DEFAULT_AS is not set
224# CONFIG_DEFAULT_DEADLINE is not set
225CONFIG_DEFAULT_CFQ=y
226# CONFIG_DEFAULT_NOOP is not set
227CONFIG_DEFAULT_IOSCHED="cfq"
228
229#
230# Bus options (PCI, PCMCIA, EISA, ISA, TC)
231#
232CONFIG_HW_HAS_PCI=y
233CONFIG_PCI=y
234# CONFIG_ARCH_SUPPORTS_MSI is not set
235CONFIG_ISA=y
236CONFIG_MMU=y
237
238#
239# PCCARD (PCMCIA/CardBus) support
240#
241# CONFIG_PCCARD is not set
242# CONFIG_HOTPLUG_PCI is not set
243
244#
245# Executable file formats
246#
247CONFIG_BINFMT_ELF=y
248CONFIG_BINFMT_MISC=y
249# CONFIG_BUILD_ELF64 is not set
250CONFIG_MIPS32_COMPAT=y
251CONFIG_COMPAT=y
252CONFIG_SYSVIPC_COMPAT=y
253CONFIG_MIPS32_O32=y
254CONFIG_MIPS32_N32=y
255CONFIG_BINFMT_ELF32=y
256
257#
258# Power management options
259#
260CONFIG_PM=y
261# CONFIG_PM_LEGACY is not set
262# CONFIG_PM_DEBUG is not set
263# CONFIG_PM_SYSFS_DEPRECATED is not set
264
265#
266# Networking
267#
268CONFIG_NET=y
269
270#
271# Networking options
272#
273CONFIG_PACKET=y
274CONFIG_PACKET_MMAP=y
275CONFIG_UNIX=y
276CONFIG_XFRM=y
277# CONFIG_XFRM_USER is not set
278# CONFIG_XFRM_SUB_POLICY is not set
279# CONFIG_XFRM_MIGRATE is not set
280# CONFIG_NET_KEY is not set
281CONFIG_INET=y
282CONFIG_IP_MULTICAST=y
283# CONFIG_IP_ADVANCED_ROUTER is not set
284CONFIG_IP_FIB_HASH=y
285CONFIG_IP_PNP=y
286# CONFIG_IP_PNP_DHCP is not set
287CONFIG_IP_PNP_BOOTP=y
288# CONFIG_IP_PNP_RARP is not set
289CONFIG_NET_IPIP=m
290CONFIG_NET_IPGRE=m
291CONFIG_NET_IPGRE_BROADCAST=y
292# CONFIG_IP_MROUTE is not set
293# CONFIG_ARPD is not set
294# CONFIG_SYN_COOKIES is not set
295# CONFIG_INET_AH is not set
296# CONFIG_INET_ESP is not set
297# CONFIG_INET_IPCOMP is not set
298# CONFIG_INET_XFRM_TUNNEL is not set
299CONFIG_INET_TUNNEL=m
300# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
301# CONFIG_INET_XFRM_MODE_TUNNEL is not set
302CONFIG_INET_XFRM_MODE_BEET=y
303# CONFIG_INET_DIAG is not set
304# CONFIG_TCP_CONG_ADVANCED is not set
305CONFIG_TCP_CONG_CUBIC=y
306CONFIG_DEFAULT_TCP_CONG="cubic"
307# CONFIG_TCP_MD5SIG is not set
308# CONFIG_IP_VS is not set
309# CONFIG_IPV6 is not set
310# CONFIG_INET6_XFRM_TUNNEL is not set
311# CONFIG_INET6_TUNNEL is not set
312# CONFIG_NETWORK_SECMARK is not set
313CONFIG_NETFILTER=y
314# CONFIG_NETFILTER_DEBUG is not set
315
316#
317# Core Netfilter Configuration
318#
319CONFIG_NETFILTER_NETLINK=m
320CONFIG_NETFILTER_NETLINK_QUEUE=m
321CONFIG_NETFILTER_NETLINK_LOG=m
322# CONFIG_NF_CONNTRACK_ENABLED is not set
323# CONFIG_NF_CONNTRACK is not set
324CONFIG_NETFILTER_XTABLES=m
325CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
326# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
327CONFIG_NETFILTER_XT_TARGET_MARK=m
328CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
329# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
330# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
331CONFIG_NETFILTER_XT_MATCH_COMMENT=m
332CONFIG_NETFILTER_XT_MATCH_DCCP=m
333# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
334CONFIG_NETFILTER_XT_MATCH_ESP=m
335CONFIG_NETFILTER_XT_MATCH_LENGTH=m
336CONFIG_NETFILTER_XT_MATCH_LIMIT=m
337CONFIG_NETFILTER_XT_MATCH_MAC=m
338CONFIG_NETFILTER_XT_MATCH_MARK=m
339# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
340CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
341CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
342CONFIG_NETFILTER_XT_MATCH_QUOTA=m
343CONFIG_NETFILTER_XT_MATCH_REALM=m
344CONFIG_NETFILTER_XT_MATCH_SCTP=m
345CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
346CONFIG_NETFILTER_XT_MATCH_STRING=m
347CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
348# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
349
350#
351# IP: Netfilter Configuration
352#
353CONFIG_IP_NF_QUEUE=m
354CONFIG_IP_NF_IPTABLES=m
355CONFIG_IP_NF_MATCH_IPRANGE=m
356CONFIG_IP_NF_MATCH_TOS=m
357CONFIG_IP_NF_MATCH_RECENT=m
358CONFIG_IP_NF_MATCH_ECN=m
359CONFIG_IP_NF_MATCH_AH=m
360CONFIG_IP_NF_MATCH_TTL=m
361CONFIG_IP_NF_MATCH_OWNER=m
362CONFIG_IP_NF_MATCH_ADDRTYPE=m
363CONFIG_IP_NF_FILTER=m
364CONFIG_IP_NF_TARGET_REJECT=m
365CONFIG_IP_NF_TARGET_LOG=m
366CONFIG_IP_NF_TARGET_ULOG=m
367CONFIG_IP_NF_MANGLE=m
368CONFIG_IP_NF_TARGET_TOS=m
369CONFIG_IP_NF_TARGET_ECN=m
370CONFIG_IP_NF_TARGET_TTL=m
371CONFIG_IP_NF_RAW=m
372CONFIG_IP_NF_ARPTABLES=m
373CONFIG_IP_NF_ARPFILTER=m
374CONFIG_IP_NF_ARP_MANGLE=m
375# CONFIG_IP_DCCP is not set
376# CONFIG_IP_SCTP is not set
377# CONFIG_TIPC is not set
378# CONFIG_ATM is not set
379# CONFIG_BRIDGE is not set
380# CONFIG_VLAN_8021Q is not set
381# CONFIG_DECNET is not set
382# CONFIG_LLC2 is not set
383# CONFIG_IPX is not set
384# CONFIG_ATALK is not set
385# CONFIG_X25 is not set
386# CONFIG_LAPB is not set
387# CONFIG_ECONET is not set
388# CONFIG_WAN_ROUTER is not set
389
390#
391# QoS and/or fair queueing
392#
393# CONFIG_NET_SCHED is not set
394CONFIG_NET_CLS_ROUTE=y
395
396#
397# Network testing
398#
399# CONFIG_NET_PKTGEN is not set
400# CONFIG_HAMRADIO is not set
401# CONFIG_IRDA is not set
402# CONFIG_BT is not set
403# CONFIG_AF_RXRPC is not set
404
405#
406# Wireless
407#
408# CONFIG_CFG80211 is not set
409CONFIG_WIRELESS_EXT=y
410# CONFIG_MAC80211 is not set
411CONFIG_IEEE80211=m
412# CONFIG_IEEE80211_DEBUG is not set
413CONFIG_IEEE80211_CRYPT_WEP=m
414# CONFIG_IEEE80211_CRYPT_CCMP is not set
415# CONFIG_IEEE80211_CRYPT_TKIP is not set
416# CONFIG_IEEE80211_SOFTMAC is not set
417# CONFIG_RFKILL is not set
418
419#
420# Device Drivers
421#
422
423#
424# Generic Driver Options
425#
426CONFIG_STANDALONE=y
427CONFIG_PREVENT_FIRMWARE_BUILD=y
428CONFIG_FW_LOADER=m
429# CONFIG_SYS_HYPERVISOR is not set
430
431#
432# Connector - unified userspace <-> kernelspace linker
433#
434# CONFIG_CONNECTOR is not set
435CONFIG_MTD=m
436# CONFIG_MTD_DEBUG is not set
437# CONFIG_MTD_CONCAT is not set
438# CONFIG_MTD_PARTITIONS is not set
439
440#
441# User Modules And Translation Layers
442#
443CONFIG_MTD_CHAR=m
444CONFIG_MTD_BLKDEVS=m
445CONFIG_MTD_BLOCK=m
446# CONFIG_MTD_BLOCK_RO is not set
447# CONFIG_FTL is not set
448# CONFIG_NFTL is not set
449# CONFIG_INFTL is not set
450# CONFIG_RFD_FTL is not set
451# CONFIG_SSFDC is not set
452
453#
454# RAM/ROM/Flash chip drivers
455#
456CONFIG_MTD_CFI=m
457CONFIG_MTD_JEDECPROBE=m
458CONFIG_MTD_GEN_PROBE=m
459CONFIG_MTD_CFI_ADV_OPTIONS=y
460CONFIG_MTD_CFI_NOSWAP=y
461# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
462# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
463# CONFIG_MTD_CFI_GEOMETRY is not set
464CONFIG_MTD_MAP_BANK_WIDTH_1=y
465CONFIG_MTD_MAP_BANK_WIDTH_2=y
466CONFIG_MTD_MAP_BANK_WIDTH_4=y
467# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
468# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
469# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
470CONFIG_MTD_CFI_I1=y
471CONFIG_MTD_CFI_I2=y
472# CONFIG_MTD_CFI_I4 is not set
473# CONFIG_MTD_CFI_I8 is not set
474# CONFIG_MTD_OTP is not set
475# CONFIG_MTD_CFI_INTELEXT is not set
476CONFIG_MTD_CFI_AMDSTD=m
477CONFIG_MTD_CFI_STAA=m
478CONFIG_MTD_CFI_UTIL=m
479# CONFIG_MTD_RAM is not set
480# CONFIG_MTD_ROM is not set
481# CONFIG_MTD_ABSENT is not set
482
483#
484# Mapping drivers for chip access
485#
486# CONFIG_MTD_COMPLEX_MAPPINGS is not set
487CONFIG_MTD_PHYSMAP=m
488CONFIG_MTD_PHYSMAP_START=0x1fc00000
489CONFIG_MTD_PHYSMAP_LEN=0x80000
490CONFIG_MTD_PHYSMAP_BANKWIDTH=1
491# CONFIG_MTD_PLATRAM is not set
492
493#
494# Self-contained MTD device drivers
495#
496# CONFIG_MTD_PMC551 is not set
497# CONFIG_MTD_SLRAM is not set
498# CONFIG_MTD_PHRAM is not set
499# CONFIG_MTD_MTDRAM is not set
500# CONFIG_MTD_BLOCK2MTD is not set
501
502#
503# Disk-On-Chip Device Drivers
504#
505# CONFIG_MTD_DOC2000 is not set
506# CONFIG_MTD_DOC2001 is not set
507# CONFIG_MTD_DOC2001PLUS is not set
508# CONFIG_MTD_NAND is not set
509# CONFIG_MTD_ONENAND is not set
510
511#
512# UBI - Unsorted block images
513#
514# CONFIG_MTD_UBI is not set
515
516#
517# Parallel port support
518#
519# CONFIG_PARPORT is not set
520
521#
522# Plug and Play support
523#
524# CONFIG_PNP is not set
525# CONFIG_PNPACPI is not set
526
527#
528# Block devices
529#
530# CONFIG_BLK_CPQ_DA is not set
531# CONFIG_BLK_CPQ_CISS_DA is not set
532# CONFIG_BLK_DEV_DAC960 is not set
533# CONFIG_BLK_DEV_UMEM is not set
534# CONFIG_BLK_DEV_COW_COMMON is not set
535CONFIG_BLK_DEV_LOOP=y
536CONFIG_BLK_DEV_CRYPTOLOOP=m
537# CONFIG_BLK_DEV_NBD is not set
538# CONFIG_BLK_DEV_SX8 is not set
539# CONFIG_BLK_DEV_UB is not set
540CONFIG_BLK_DEV_RAM=m
541CONFIG_BLK_DEV_RAM_COUNT=16
542CONFIG_BLK_DEV_RAM_SIZE=4096
543CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
544CONFIG_CDROM_PKTCDVD=m
545CONFIG_CDROM_PKTCDVD_BUFFERS=8
546# CONFIG_CDROM_PKTCDVD_WCACHE is not set
547CONFIG_ATA_OVER_ETH=m
548
549#
550# Misc devices
551#
552# CONFIG_PHANTOM is not set
553# CONFIG_SGI_IOC4 is not set
554# CONFIG_TIFM_CORE is not set
555# CONFIG_BLINK is not set
556CONFIG_IDE=y
557CONFIG_IDE_MAX_HWIFS=4
558CONFIG_BLK_DEV_IDE=y
559
560#
561# Please see Documentation/ide.txt for help/info on IDE drives
562#
563# CONFIG_BLK_DEV_IDE_SATA is not set
564CONFIG_BLK_DEV_IDEDISK=y
565CONFIG_IDEDISK_MULTI_MODE=y
566CONFIG_BLK_DEV_IDECD=y
567# CONFIG_BLK_DEV_IDETAPE is not set
568# CONFIG_BLK_DEV_IDEFLOPPY is not set
569CONFIG_BLK_DEV_IDESCSI=y
570CONFIG_IDE_TASK_IOCTL=y
571CONFIG_IDE_PROC_FS=y
572
573#
574# IDE chipset support/bugfixes
575#
576CONFIG_IDE_GENERIC=y
577CONFIG_BLK_DEV_IDEPCI=y
578CONFIG_IDEPCI_SHARE_IRQ=y
579CONFIG_IDEPCI_PCIBUS_ORDER=y
580# CONFIG_BLK_DEV_OFFBOARD is not set
581CONFIG_BLK_DEV_GENERIC=y
582# CONFIG_BLK_DEV_OPTI621 is not set
583CONFIG_BLK_DEV_IDEDMA_PCI=y
584# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
585# CONFIG_IDEDMA_ONLYDISK is not set
586# CONFIG_BLK_DEV_AEC62XX is not set
587# CONFIG_BLK_DEV_ALI15X3 is not set
588# CONFIG_BLK_DEV_AMD74XX is not set
589# CONFIG_BLK_DEV_CMD64X is not set
590# CONFIG_BLK_DEV_TRIFLEX is not set
591# CONFIG_BLK_DEV_CY82C693 is not set
592# CONFIG_BLK_DEV_CS5520 is not set
593# CONFIG_BLK_DEV_CS5530 is not set
594# CONFIG_BLK_DEV_HPT34X is not set
595# CONFIG_BLK_DEV_HPT366 is not set
596# CONFIG_BLK_DEV_JMICRON is not set
597# CONFIG_BLK_DEV_SC1200 is not set
598# CONFIG_BLK_DEV_PIIX is not set
599# CONFIG_BLK_DEV_IT8213 is not set
600# CONFIG_BLK_DEV_IT821X is not set
601# CONFIG_BLK_DEV_NS87415 is not set
602# CONFIG_BLK_DEV_PDC202XX_OLD is not set
603# CONFIG_BLK_DEV_PDC202XX_NEW is not set
604# CONFIG_BLK_DEV_SVWKS is not set
605# CONFIG_BLK_DEV_SIIMAGE is not set
606# CONFIG_BLK_DEV_SLC90E66 is not set
607# CONFIG_BLK_DEV_TRM290 is not set
608CONFIG_BLK_DEV_VIA82CXXX=y
609# CONFIG_BLK_DEV_TC86C001 is not set
610# CONFIG_IDE_ARM is not set
611# CONFIG_IDE_CHIPSETS is not set
612CONFIG_BLK_DEV_IDEDMA=y
613# CONFIG_IDEDMA_IVB is not set
614# CONFIG_BLK_DEV_HD is not set
615
616#
617# SCSI device support
618#
619# CONFIG_RAID_ATTRS is not set
620CONFIG_SCSI=y
621# CONFIG_SCSI_TGT is not set
622# CONFIG_SCSI_NETLINK is not set
623CONFIG_SCSI_PROC_FS=y
624
625#
626# SCSI support type (disk, tape, CD-ROM)
627#
628CONFIG_BLK_DEV_SD=y
629# CONFIG_CHR_DEV_ST is not set
630# CONFIG_CHR_DEV_OSST is not set
631CONFIG_BLK_DEV_SR=y
632CONFIG_BLK_DEV_SR_VENDOR=y
633CONFIG_CHR_DEV_SG=y
634# CONFIG_CHR_DEV_SCH is not set
635
636#
637# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
638#
639# CONFIG_SCSI_MULTI_LUN is not set
640CONFIG_SCSI_CONSTANTS=y
641# CONFIG_SCSI_LOGGING is not set
642# CONFIG_SCSI_SCAN_ASYNC is not set
643CONFIG_SCSI_WAIT_SCAN=m
644
645#
646# SCSI Transports
647#
648# CONFIG_SCSI_SPI_ATTRS is not set
649# CONFIG_SCSI_FC_ATTRS is not set
650# CONFIG_SCSI_ISCSI_ATTRS is not set
651# CONFIG_SCSI_SAS_ATTRS is not set
652# CONFIG_SCSI_SAS_LIBSAS is not set
653
654#
655# SCSI low-level drivers
656#
657# CONFIG_ISCSI_TCP is not set
658# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
659# CONFIG_SCSI_3W_9XXX is not set
660# CONFIG_SCSI_ACARD is not set
661# CONFIG_SCSI_AACRAID is not set
662# CONFIG_SCSI_AIC7XXX is not set
663# CONFIG_SCSI_AIC7XXX_OLD is not set
664# CONFIG_SCSI_AIC79XX is not set
665# CONFIG_SCSI_AIC94XX is not set
666# CONFIG_SCSI_IN2000 is not set
667# CONFIG_SCSI_ARCMSR is not set
668# CONFIG_MEGARAID_NEWGEN is not set
669# CONFIG_MEGARAID_LEGACY is not set
670# CONFIG_MEGARAID_SAS is not set
671# CONFIG_SCSI_HPTIOP is not set
672# CONFIG_SCSI_DMX3191D is not set
673# CONFIG_SCSI_DTC3280 is not set
674# CONFIG_SCSI_FUTURE_DOMAIN is not set
675# CONFIG_SCSI_GENERIC_NCR5380 is not set
676# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
677# CONFIG_SCSI_IPS is not set
678# CONFIG_SCSI_INITIO is not set
679# CONFIG_SCSI_INIA100 is not set
680# CONFIG_SCSI_NCR53C406A is not set
681# CONFIG_SCSI_STEX is not set
682# CONFIG_SCSI_SYM53C8XX_2 is not set
683# CONFIG_SCSI_PAS16 is not set
684# CONFIG_SCSI_PSI240I is not set
685# CONFIG_SCSI_QLOGIC_FAS is not set
686# CONFIG_SCSI_QLOGIC_1280 is not set
687# CONFIG_SCSI_QLA_FC is not set
688# CONFIG_SCSI_QLA_ISCSI is not set
689# CONFIG_SCSI_LPFC is not set
690# CONFIG_SCSI_SYM53C416 is not set
691# CONFIG_SCSI_DC395x is not set
692# CONFIG_SCSI_DC390T is not set
693# CONFIG_SCSI_T128 is not set
694# CONFIG_SCSI_DEBUG is not set
695# CONFIG_SCSI_SRP is not set
696# CONFIG_ATA is not set
697
698#
699# Old CD-ROM drivers (not SCSI, not IDE)
700#
701# CONFIG_CD_NO_IDESCSI is not set
702
703#
704# Multi-device support (RAID and LVM)
705#
706# CONFIG_MD is not set
707
708#
709# Fusion MPT device support
710#
711# CONFIG_FUSION is not set
712# CONFIG_FUSION_SPI is not set
713# CONFIG_FUSION_FC is not set
714# CONFIG_FUSION_SAS is not set
715
716#
717# IEEE 1394 (FireWire) support
718#
719# CONFIG_FIREWIRE is not set
720# CONFIG_IEEE1394 is not set
721
722#
723# I2O device support
724#
725# CONFIG_I2O is not set
726
727#
728# Network device support
729#
730CONFIG_NETDEVICES=y
731# CONFIG_DUMMY is not set
732# CONFIG_BONDING is not set
733# CONFIG_EQUALIZER is not set
734# CONFIG_TUN is not set
735# CONFIG_ARCNET is not set
736CONFIG_PHYLIB=m
737
738#
739# MII PHY device drivers
740#
741CONFIG_MARVELL_PHY=m
742CONFIG_DAVICOM_PHY=m
743CONFIG_QSEMI_PHY=m
744CONFIG_LXT_PHY=m
745CONFIG_CICADA_PHY=m
746# CONFIG_VITESSE_PHY is not set
747# CONFIG_SMSC_PHY is not set
748# CONFIG_BROADCOM_PHY is not set
749# CONFIG_FIXED_PHY is not set
750
751#
752# Ethernet (10 or 100Mbit)
753#
754CONFIG_NET_ETHERNET=y
755CONFIG_MII=y
756# CONFIG_HAPPYMEAL is not set
757# CONFIG_SUNGEM is not set
758# CONFIG_CASSINI is not set
759# CONFIG_NET_VENDOR_3COM is not set
760# CONFIG_NET_VENDOR_SMC is not set
761# CONFIG_DM9000 is not set
762# CONFIG_NET_VENDOR_RACAL is not set
763
764#
765# Tulip family network device support
766#
767# CONFIG_NET_TULIP is not set
768# CONFIG_AT1700 is not set
769# CONFIG_DEPCA is not set
770# CONFIG_HP100 is not set
771# CONFIG_NET_ISA is not set
772CONFIG_NET_PCI=y
773# CONFIG_PCNET32 is not set
774# CONFIG_AMD8111_ETH is not set
775# CONFIG_ADAPTEC_STARFIRE is not set
776# CONFIG_AC3200 is not set
777# CONFIG_APRICOT is not set
778# CONFIG_B44 is not set
779# CONFIG_FORCEDETH is not set
780# CONFIG_CS89x0 is not set
781# CONFIG_TC35815 is not set
782# CONFIG_DGRS is not set
783# CONFIG_EEPRO100 is not set
784# CONFIG_E100 is not set
785# CONFIG_FEALNX is not set
786# CONFIG_NATSEMI is not set
787# CONFIG_NE2K_PCI is not set
788# CONFIG_8139CP is not set
789CONFIG_8139TOO=y
790# CONFIG_8139TOO_PIO is not set
791# CONFIG_8139TOO_TUNE_TWISTER is not set
792# CONFIG_8139TOO_8129 is not set
793# CONFIG_8139_OLD_RX_RESET is not set
794# CONFIG_SIS900 is not set
795# CONFIG_EPIC100 is not set
796# CONFIG_SUNDANCE is not set
797# CONFIG_VIA_RHINE is not set
798# CONFIG_SC92031 is not set
799CONFIG_NETDEV_1000=y
800# CONFIG_ACENIC is not set
801# CONFIG_DL2K is not set
802# CONFIG_E1000 is not set
803# CONFIG_NS83820 is not set
804# CONFIG_HAMACHI is not set
805# CONFIG_YELLOWFIN is not set
806# CONFIG_R8169 is not set
807# CONFIG_SIS190 is not set
808# CONFIG_SKGE is not set
809# CONFIG_SKY2 is not set
810# CONFIG_SK98LIN is not set
811# CONFIG_VIA_VELOCITY is not set
812# CONFIG_TIGON3 is not set
813# CONFIG_BNX2 is not set
814# CONFIG_QLA3XXX is not set
815# CONFIG_ATL1 is not set
816CONFIG_NETDEV_10000=y
817# CONFIG_CHELSIO_T1 is not set
818# CONFIG_CHELSIO_T3 is not set
819# CONFIG_IXGB is not set
820# CONFIG_S2IO is not set
821# CONFIG_MYRI10GE is not set
822# CONFIG_NETXEN_NIC is not set
823# CONFIG_MLX4_CORE is not set
824# CONFIG_TR is not set
825
826#
827# Wireless LAN
828#
829# CONFIG_WLAN_PRE80211 is not set
830# CONFIG_WLAN_80211 is not set
831
832#
833# USB Network Adapters
834#
835# CONFIG_USB_CATC is not set
836# CONFIG_USB_KAWETH is not set
837# CONFIG_USB_PEGASUS is not set
838# CONFIG_USB_RTL8150 is not set
839# CONFIG_USB_USBNET_MII is not set
840# CONFIG_USB_USBNET is not set
841# CONFIG_WAN is not set
842# CONFIG_FDDI is not set
843# CONFIG_HIPPI is not set
844CONFIG_PPP=m
845CONFIG_PPP_MULTILINK=y
846CONFIG_PPP_FILTER=y
847CONFIG_PPP_ASYNC=m
848CONFIG_PPP_SYNC_TTY=m
849CONFIG_PPP_DEFLATE=m
850CONFIG_PPP_BSDCOMP=m
851CONFIG_PPP_MPPE=m
852CONFIG_PPPOE=m
853CONFIG_SLIP=m
854CONFIG_SLIP_COMPRESSED=y
855CONFIG_SLHC=m
856CONFIG_SLIP_SMART=y
857CONFIG_SLIP_MODE_SLIP6=y
858CONFIG_NET_FC=y
859# CONFIG_SHAPER is not set
860# CONFIG_NETCONSOLE is not set
861# CONFIG_NETPOLL is not set
862# CONFIG_NET_POLL_CONTROLLER is not set
863
864#
865# ISDN subsystem
866#
867# CONFIG_ISDN is not set
868
869#
870# Telephony Support
871#
872# CONFIG_PHONE is not set
873
874#
875# Input device support
876#
877CONFIG_INPUT=y
878CONFIG_INPUT_FF_MEMLESS=y
879
880#
881# Userland interfaces
882#
883CONFIG_INPUT_MOUSEDEV=y
884CONFIG_INPUT_MOUSEDEV_PSAUX=y
885CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
886CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
887# CONFIG_INPUT_JOYDEV is not set
888# CONFIG_INPUT_TSDEV is not set
889# CONFIG_INPUT_EVDEV is not set
890# CONFIG_INPUT_EVBUG is not set
891
892#
893# Input Device Drivers
894#
895CONFIG_INPUT_KEYBOARD=y
896CONFIG_KEYBOARD_ATKBD=m
897# CONFIG_KEYBOARD_SUNKBD is not set
898# CONFIG_KEYBOARD_LKKBD is not set
899# CONFIG_KEYBOARD_XTKBD is not set
900# CONFIG_KEYBOARD_NEWTON is not set
901# CONFIG_KEYBOARD_STOWAWAY is not set
902CONFIG_INPUT_MOUSE=y
903CONFIG_MOUSE_PS2=y
904CONFIG_MOUSE_PS2_ALPS=y
905CONFIG_MOUSE_PS2_LOGIPS2PP=y
906CONFIG_MOUSE_PS2_SYNAPTICS=y
907CONFIG_MOUSE_PS2_LIFEBOOK=y
908CONFIG_MOUSE_PS2_TRACKPOINT=y
909# CONFIG_MOUSE_PS2_TOUCHKIT is not set
910CONFIG_MOUSE_SERIAL=y
911# CONFIG_MOUSE_APPLETOUCH is not set
912# CONFIG_MOUSE_INPORT is not set
913# CONFIG_MOUSE_LOGIBM is not set
914# CONFIG_MOUSE_PC110PAD is not set
915# CONFIG_MOUSE_VSXXXAA is not set
916# CONFIG_INPUT_JOYSTICK is not set
917# CONFIG_INPUT_TABLET is not set
918# CONFIG_INPUT_TOUCHSCREEN is not set
919# CONFIG_INPUT_MISC is not set
920
921#
922# Hardware I/O ports
923#
924CONFIG_SERIO=y
925CONFIG_SERIO_I8042=y
926CONFIG_SERIO_SERPORT=y
927# CONFIG_SERIO_PCIPS2 is not set
928CONFIG_SERIO_LIBPS2=y
929# CONFIG_SERIO_RAW is not set
930# CONFIG_GAMEPORT is not set
931
932#
933# Character devices
934#
935CONFIG_VT=y
936CONFIG_VT_CONSOLE=y
937CONFIG_HW_CONSOLE=y
938# CONFIG_VT_HW_CONSOLE_BINDING is not set
939# CONFIG_SERIAL_NONSTANDARD is not set
940
941#
942# Serial drivers
943#
944CONFIG_SERIAL_8250=y
945CONFIG_SERIAL_8250_CONSOLE=y
946CONFIG_SERIAL_8250_PCI=y
947CONFIG_SERIAL_8250_NR_UARTS=2
948CONFIG_SERIAL_8250_RUNTIME_UARTS=2
949# CONFIG_SERIAL_8250_EXTENDED is not set
950
951#
952# Non-8250 serial port support
953#
954CONFIG_SERIAL_CORE=y
955CONFIG_SERIAL_CORE_CONSOLE=y
956# CONFIG_SERIAL_JSM is not set
957CONFIG_UNIX98_PTYS=y
958CONFIG_LEGACY_PTYS=y
959CONFIG_LEGACY_PTY_COUNT=256
960
961#
962# IPMI
963#
964# CONFIG_IPMI_HANDLER is not set
965# CONFIG_WATCHDOG is not set
966CONFIG_HW_RANDOM=y
967CONFIG_RTC=y
968# CONFIG_DTLK is not set
969# CONFIG_R3964 is not set
970# CONFIG_APPLICOM is not set
971# CONFIG_DRM is not set
972# CONFIG_RAW_DRIVER is not set
973
974#
975# TPM devices
976#
977# CONFIG_TCG_TPM is not set
978CONFIG_DEVPORT=y
979CONFIG_I2C=m
980CONFIG_I2C_BOARDINFO=y
981CONFIG_I2C_CHARDEV=m
982
983#
984# I2C Algorithms
985#
986# CONFIG_I2C_ALGOBIT is not set
987# CONFIG_I2C_ALGOPCF is not set
988# CONFIG_I2C_ALGOPCA is not set
989
990#
991# I2C Hardware Bus support
992#
993# CONFIG_I2C_ALI1535 is not set
994# CONFIG_I2C_ALI1563 is not set
995# CONFIG_I2C_ALI15X3 is not set
996# CONFIG_I2C_AMD756 is not set
997# CONFIG_I2C_AMD8111 is not set
998# CONFIG_I2C_ELEKTOR is not set
999# CONFIG_I2C_I801 is not set
1000# CONFIG_I2C_I810 is not set
1001# CONFIG_I2C_PIIX4 is not set
1002# CONFIG_I2C_NFORCE2 is not set
1003# CONFIG_I2C_OCORES is not set
1004# CONFIG_I2C_PARPORT_LIGHT is not set
1005# CONFIG_I2C_PROSAVAGE is not set
1006# CONFIG_I2C_SAVAGE4 is not set
1007# CONFIG_I2C_SIMTEC is not set
1008# CONFIG_I2C_SIS5595 is not set
1009# CONFIG_I2C_SIS630 is not set
1010# CONFIG_I2C_SIS96X is not set
1011# CONFIG_I2C_STUB is not set
1012# CONFIG_I2C_TINY_USB is not set
1013# CONFIG_I2C_VIA is not set
1014CONFIG_I2C_VIAPRO=m
1015# CONFIG_I2C_VOODOO3 is not set
1016# CONFIG_I2C_PCA_ISA is not set
1017
1018#
1019# Miscellaneous I2C Chip support
1020#
1021# CONFIG_SENSORS_DS1337 is not set
1022# CONFIG_SENSORS_DS1374 is not set
1023# CONFIG_SENSORS_EEPROM is not set
1024# CONFIG_SENSORS_PCF8574 is not set
1025# CONFIG_SENSORS_PCA9539 is not set
1026# CONFIG_SENSORS_PCF8591 is not set
1027# CONFIG_SENSORS_MAX6875 is not set
1028# CONFIG_I2C_DEBUG_CORE is not set
1029# CONFIG_I2C_DEBUG_ALGO is not set
1030# CONFIG_I2C_DEBUG_BUS is not set
1031# CONFIG_I2C_DEBUG_CHIP is not set
1032
1033#
1034# SPI support
1035#
1036# CONFIG_SPI is not set
1037# CONFIG_SPI_MASTER is not set
1038
1039#
1040# Dallas's 1-wire bus
1041#
1042# CONFIG_W1 is not set
1043# CONFIG_HWMON is not set
1044
1045#
1046# Multifunction device drivers
1047#
1048# CONFIG_MFD_SM501 is not set
1049
1050#
1051# Multimedia devices
1052#
1053CONFIG_VIDEO_DEV=m
1054CONFIG_VIDEO_V4L1=y
1055CONFIG_VIDEO_V4L1_COMPAT=y
1056CONFIG_VIDEO_V4L2=y
1057CONFIG_VIDEO_CAPTURE_DRIVERS=y
1058# CONFIG_VIDEO_ADV_DEBUG is not set
1059CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1060# CONFIG_VIDEO_VIVI is not set
1061# CONFIG_VIDEO_BT848 is not set
1062# CONFIG_VIDEO_PMS is not set
1063# CONFIG_VIDEO_CPIA is not set
1064# CONFIG_VIDEO_CPIA2 is not set
1065# CONFIG_VIDEO_SAA5246A is not set
1066# CONFIG_VIDEO_SAA5249 is not set
1067# CONFIG_TUNER_3036 is not set
1068# CONFIG_VIDEO_STRADIS is not set
1069# CONFIG_VIDEO_SAA7134 is not set
1070# CONFIG_VIDEO_MXB is not set
1071# CONFIG_VIDEO_DPC is not set
1072# CONFIG_VIDEO_HEXIUM_ORION is not set
1073# CONFIG_VIDEO_HEXIUM_GEMINI is not set
1074# CONFIG_VIDEO_CX88 is not set
1075# CONFIG_VIDEO_IVTV is not set
1076# CONFIG_VIDEO_CAFE_CCIC is not set
1077CONFIG_V4L_USB_DRIVERS=y
1078# CONFIG_VIDEO_PVRUSB2 is not set
1079# CONFIG_VIDEO_EM28XX is not set
1080# CONFIG_VIDEO_USBVISION is not set
1081CONFIG_VIDEO_USBVIDEO=m
1082CONFIG_USB_VICAM=m
1083CONFIG_USB_IBMCAM=m
1084CONFIG_USB_KONICAWC=m
1085CONFIG_USB_QUICKCAM_MESSENGER=m
1086CONFIG_USB_ET61X251=m
1087# CONFIG_VIDEO_OVCAMCHIP is not set
1088# CONFIG_USB_W9968CF is not set
1089CONFIG_USB_OV511=m
1090CONFIG_USB_SE401=m
1091CONFIG_USB_SN9C102=m
1092CONFIG_USB_STV680=m
1093CONFIG_USB_ZC0301=m
1094CONFIG_USB_PWC=m
1095# CONFIG_USB_PWC_DEBUG is not set
1096# CONFIG_USB_ZR364XX is not set
1097CONFIG_RADIO_ADAPTERS=y
1098# CONFIG_RADIO_CADET is not set
1099# CONFIG_RADIO_RTRACK is not set
1100# CONFIG_RADIO_RTRACK2 is not set
1101# CONFIG_RADIO_AZTECH is not set
1102# CONFIG_RADIO_GEMTEK is not set
1103# CONFIG_RADIO_GEMTEK_PCI is not set
1104# CONFIG_RADIO_MAXIRADIO is not set
1105# CONFIG_RADIO_MAESTRO is not set
1106# CONFIG_RADIO_SF16FMI is not set
1107# CONFIG_RADIO_SF16FMR2 is not set
1108# CONFIG_RADIO_TERRATEC is not set
1109# CONFIG_RADIO_TRUST is not set
1110# CONFIG_RADIO_TYPHOON is not set
1111# CONFIG_RADIO_ZOLTRIX is not set
1112# CONFIG_USB_DSBR is not set
1113# CONFIG_DVB_CORE is not set
1114CONFIG_DAB=y
1115# CONFIG_USB_DABUSB is not set
1116
1117#
1118# Graphics support
1119#
1120CONFIG_BACKLIGHT_LCD_SUPPORT=y
1121CONFIG_BACKLIGHT_CLASS_DEVICE=y
1122CONFIG_LCD_CLASS_DEVICE=m
1123
1124#
1125# Display device support
1126#
1127# CONFIG_DISPLAY_SUPPORT is not set
1128# CONFIG_VGASTATE is not set
1129CONFIG_FB=y
1130# CONFIG_FIRMWARE_EDID is not set
1131# CONFIG_FB_DDC is not set
1132CONFIG_FB_CFB_FILLRECT=y
1133CONFIG_FB_CFB_COPYAREA=y
1134CONFIG_FB_CFB_IMAGEBLIT=y
1135# CONFIG_FB_SYS_FILLRECT is not set
1136# CONFIG_FB_SYS_COPYAREA is not set
1137# CONFIG_FB_SYS_IMAGEBLIT is not set
1138# CONFIG_FB_SYS_FOPS is not set
1139CONFIG_FB_DEFERRED_IO=y
1140# CONFIG_FB_SVGALIB is not set
1141# CONFIG_FB_MACMODES is not set
1142CONFIG_FB_BACKLIGHT=y
1143CONFIG_FB_MODE_HELPERS=y
1144# CONFIG_FB_TILEBLITTING is not set
1145
1146#
1147# Frame buffer hardware drivers
1148#
1149# CONFIG_FB_CIRRUS is not set
1150# CONFIG_FB_PM2 is not set
1151# CONFIG_FB_CYBER2000 is not set
1152# CONFIG_FB_ASILIANT is not set
1153# CONFIG_FB_IMSTT is not set
1154# CONFIG_FB_S1D13XXX is not set
1155# CONFIG_FB_NVIDIA is not set
1156# CONFIG_FB_RIVA is not set
1157# CONFIG_FB_MATROX is not set
1158CONFIG_FB_RADEON=y
1159# CONFIG_FB_RADEON_I2C is not set
1160CONFIG_FB_RADEON_BACKLIGHT=y
1161# CONFIG_FB_RADEON_DEBUG is not set
1162# CONFIG_FB_ATY128 is not set
1163# CONFIG_FB_ATY is not set
1164# CONFIG_FB_S3 is not set
1165# CONFIG_FB_SAVAGE is not set
1166# CONFIG_FB_SIS is not set
1167# CONFIG_FB_NEOMAGIC is not set
1168# CONFIG_FB_KYRO is not set
1169# CONFIG_FB_3DFX is not set
1170# CONFIG_FB_VOODOO1 is not set
1171# CONFIG_FB_SMIVGX is not set
1172# CONFIG_FB_VT8623 is not set
1173# CONFIG_FB_TRIDENT is not set
1174# CONFIG_FB_ARK is not set
1175# CONFIG_FB_PM3 is not set
1176# CONFIG_FB_VIRTUAL is not set
1177
1178#
1179# Console display driver support
1180#
1181# CONFIG_VGA_CONSOLE is not set
1182# CONFIG_MDA_CONSOLE is not set
1183CONFIG_DUMMY_CONSOLE=y
1184CONFIG_FRAMEBUFFER_CONSOLE=y
1185# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
1186# CONFIG_FONTS is not set
1187CONFIG_FONT_8x8=y
1188CONFIG_FONT_8x16=y
1189# CONFIG_LOGO is not set
1190
1191#
1192# Sound
1193#
1194CONFIG_SOUND=y
1195
1196#
1197# Advanced Linux Sound Architecture
1198#
1199CONFIG_SND=m
1200CONFIG_SND_TIMER=m
1201CONFIG_SND_PCM=m
1202CONFIG_SND_RAWMIDI=m
1203CONFIG_SND_SEQUENCER=m
1204CONFIG_SND_SEQ_DUMMY=m
1205CONFIG_SND_OSSEMUL=y
1206CONFIG_SND_MIXER_OSS=m
1207CONFIG_SND_PCM_OSS=m
1208CONFIG_SND_PCM_OSS_PLUGINS=y
1209CONFIG_SND_SEQUENCER_OSS=y
1210CONFIG_SND_RTCTIMER=m
1211CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y
1212# CONFIG_SND_DYNAMIC_MINORS is not set
1213CONFIG_SND_SUPPORT_OLD_API=y
1214CONFIG_SND_VERBOSE_PROCFS=y
1215# CONFIG_SND_VERBOSE_PRINTK is not set
1216# CONFIG_SND_DEBUG is not set
1217
1218#
1219# Generic devices
1220#
1221CONFIG_SND_MPU401_UART=m
1222CONFIG_SND_AC97_CODEC=m
1223# CONFIG_SND_DUMMY is not set
1224# CONFIG_SND_VIRMIDI is not set
1225# CONFIG_SND_MTPAV is not set
1226# CONFIG_SND_SERIAL_U16550 is not set
1227# CONFIG_SND_MPU401 is not set
1228
1229#
1230# PCI devices
1231#
1232# CONFIG_SND_AD1889 is not set
1233# CONFIG_SND_ALS300 is not set
1234# CONFIG_SND_ALI5451 is not set
1235# CONFIG_SND_ATIIXP is not set
1236# CONFIG_SND_ATIIXP_MODEM is not set
1237# CONFIG_SND_AU8810 is not set
1238# CONFIG_SND_AU8820 is not set
1239# CONFIG_SND_AU8830 is not set
1240# CONFIG_SND_AZT3328 is not set
1241# CONFIG_SND_BT87X is not set
1242# CONFIG_SND_CA0106 is not set
1243# CONFIG_SND_CMIPCI is not set
1244# CONFIG_SND_CS4281 is not set
1245# CONFIG_SND_CS46XX is not set
1246# CONFIG_SND_DARLA20 is not set
1247# CONFIG_SND_GINA20 is not set
1248# CONFIG_SND_LAYLA20 is not set
1249# CONFIG_SND_DARLA24 is not set
1250# CONFIG_SND_GINA24 is not set
1251# CONFIG_SND_LAYLA24 is not set
1252# CONFIG_SND_MONA is not set
1253# CONFIG_SND_MIA is not set
1254# CONFIG_SND_ECHO3G is not set
1255# CONFIG_SND_INDIGO is not set
1256# CONFIG_SND_INDIGOIO is not set
1257# CONFIG_SND_INDIGODJ is not set
1258# CONFIG_SND_EMU10K1 is not set
1259# CONFIG_SND_EMU10K1X is not set
1260# CONFIG_SND_ENS1370 is not set
1261# CONFIG_SND_ENS1371 is not set
1262# CONFIG_SND_ES1938 is not set
1263# CONFIG_SND_ES1968 is not set
1264# CONFIG_SND_FM801 is not set
1265# CONFIG_SND_HDA_INTEL is not set
1266# CONFIG_SND_HDSP is not set
1267# CONFIG_SND_HDSPM is not set
1268# CONFIG_SND_ICE1712 is not set
1269# CONFIG_SND_ICE1724 is not set
1270# CONFIG_SND_INTEL8X0 is not set
1271# CONFIG_SND_INTEL8X0M is not set
1272# CONFIG_SND_KORG1212 is not set
1273# CONFIG_SND_MAESTRO3 is not set
1274# CONFIG_SND_MIXART is not set
1275# CONFIG_SND_NM256 is not set
1276# CONFIG_SND_PCXHR is not set
1277# CONFIG_SND_RIPTIDE is not set
1278# CONFIG_SND_RME32 is not set
1279# CONFIG_SND_RME96 is not set
1280# CONFIG_SND_RME9652 is not set
1281# CONFIG_SND_SONICVIBES is not set
1282# CONFIG_SND_TRIDENT is not set
1283CONFIG_SND_VIA82XX=m
1284# CONFIG_SND_VIA82XX_MODEM is not set
1285# CONFIG_SND_VX222 is not set
1286# CONFIG_SND_YMFPCI is not set
1287# CONFIG_SND_AC97_POWER_SAVE is not set
1288
1289#
1290# ALSA MIPS devices
1291#
1292
1293#
1294# USB devices
1295#
1296# CONFIG_SND_USB_AUDIO is not set
1297# CONFIG_SND_USB_CAIAQ is not set
1298
1299#
1300# System on Chip audio support
1301#
1302# CONFIG_SND_SOC is not set
1303
1304#
1305# Open Sound System
1306#
1307# CONFIG_SOUND_PRIME is not set
1308CONFIG_AC97_BUS=m
1309
1310#
1311# HID Devices
1312#
1313CONFIG_HID=y
1314# CONFIG_HID_DEBUG is not set
1315
1316#
1317# USB Input Devices
1318#
1319CONFIG_USB_HID=m
1320# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1321# CONFIG_HID_FF is not set
1322CONFIG_USB_HIDDEV=y
1323
1324#
1325# USB HID Boot Protocol drivers
1326#
1327# CONFIG_USB_KBD is not set
1328# CONFIG_USB_MOUSE is not set
1329
1330#
1331# USB support
1332#
1333CONFIG_USB_ARCH_HAS_HCD=y
1334CONFIG_USB_ARCH_HAS_OHCI=y
1335CONFIG_USB_ARCH_HAS_EHCI=y
1336CONFIG_USB=y
1337# CONFIG_USB_DEBUG is not set
1338
1339#
1340# Miscellaneous USB options
1341#
1342CONFIG_USB_DEVICEFS=y
1343# CONFIG_USB_DEVICE_CLASS is not set
1344# CONFIG_USB_DYNAMIC_MINORS is not set
1345# CONFIG_USB_SUSPEND is not set
1346# CONFIG_USB_OTG is not set
1347
1348#
1349# USB Host Controller Drivers
1350#
1351CONFIG_USB_EHCI_HCD=y
1352CONFIG_USB_EHCI_SPLIT_ISO=y
1353CONFIG_USB_EHCI_ROOT_HUB_TT=y
1354CONFIG_USB_EHCI_TT_NEWSCHED=y
1355# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
1356# CONFIG_USB_ISP116X_HCD is not set
1357CONFIG_USB_OHCI_HCD=y
1358# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1359# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1360CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1361CONFIG_USB_UHCI_HCD=m
1362# CONFIG_USB_SL811_HCD is not set
1363
1364#
1365# USB Device Class drivers
1366#
1367CONFIG_USB_ACM=y
1368CONFIG_USB_PRINTER=y
1369
1370#
1371# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1372#
1373
1374#
1375# may also be needed; see USB_STORAGE Help for more information
1376#
1377CONFIG_USB_STORAGE=y
1378# CONFIG_USB_STORAGE_DEBUG is not set
1379# CONFIG_USB_STORAGE_DATAFAB is not set
1380# CONFIG_USB_STORAGE_FREECOM is not set
1381# CONFIG_USB_STORAGE_ISD200 is not set
1382# CONFIG_USB_STORAGE_DPCM is not set
1383# CONFIG_USB_STORAGE_USBAT is not set
1384# CONFIG_USB_STORAGE_SDDR09 is not set
1385# CONFIG_USB_STORAGE_SDDR55 is not set
1386# CONFIG_USB_STORAGE_JUMPSHOT is not set
1387# CONFIG_USB_STORAGE_ALAUDA is not set
1388# CONFIG_USB_STORAGE_KARMA is not set
1389CONFIG_USB_LIBUSUAL=y
1390
1391#
1392# USB Imaging devices
1393#
1394# CONFIG_USB_MDC800 is not set
1395# CONFIG_USB_MICROTEK is not set
1396# CONFIG_USB_MON is not set
1397
1398#
1399# USB port drivers
1400#
1401
1402#
1403# USB Serial Converter support
1404#
1405# CONFIG_USB_SERIAL is not set
1406
1407#
1408# USB Miscellaneous drivers
1409#
1410# CONFIG_USB_EMI62 is not set
1411# CONFIG_USB_EMI26 is not set
1412# CONFIG_USB_ADUTUX is not set
1413# CONFIG_USB_AUERSWALD is not set
1414# CONFIG_USB_RIO500 is not set
1415# CONFIG_USB_LEGOTOWER is not set
1416# CONFIG_USB_LCD is not set
1417# CONFIG_USB_BERRY_CHARGE is not set
1418# CONFIG_USB_LED is not set
1419# CONFIG_USB_CYPRESS_CY7C63 is not set
1420# CONFIG_USB_CYTHERM is not set
1421# CONFIG_USB_PHIDGET is not set
1422# CONFIG_USB_IDMOUSE is not set
1423# CONFIG_USB_FTDI_ELAN is not set
1424# CONFIG_USB_APPLEDISPLAY is not set
1425# CONFIG_USB_SISUSBVGA is not set
1426# CONFIG_USB_LD is not set
1427# CONFIG_USB_TRANCEVIBRATOR is not set
1428# CONFIG_USB_IOWARRIOR is not set
1429# CONFIG_USB_TEST is not set
1430
1431#
1432# USB DSL modem support
1433#
1434
1435#
1436# USB Gadget Support
1437#
1438# CONFIG_USB_GADGET is not set
1439# CONFIG_MMC is not set
1440
1441#
1442# LED devices
1443#
1444# CONFIG_NEW_LEDS is not set
1445
1446#
1447# LED drivers
1448#
1449
1450#
1451# LED Triggers
1452#
1453
1454#
1455# InfiniBand support
1456#
1457# CONFIG_INFINIBAND is not set
1458
1459#
1460# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
1461#
1462
1463#
1464# Real Time Clock
1465#
1466# CONFIG_RTC_CLASS is not set
1467
1468#
1469# DMA Engine support
1470#
1471# CONFIG_DMA_ENGINE is not set
1472
1473#
1474# DMA Clients
1475#
1476
1477#
1478# DMA Devices
1479#
1480
1481#
1482# File systems
1483#
1484CONFIG_EXT2_FS=y
1485# CONFIG_EXT2_FS_XATTR is not set
1486CONFIG_EXT2_FS_XIP=y
1487CONFIG_FS_XIP=y
1488CONFIG_EXT3_FS=y
1489# CONFIG_EXT3_FS_XATTR is not set
1490# CONFIG_EXT4DEV_FS is not set
1491CONFIG_JBD=y
1492# CONFIG_JBD_DEBUG is not set
1493CONFIG_REISERFS_FS=m
1494# CONFIG_REISERFS_CHECK is not set
1495# CONFIG_REISERFS_PROC_INFO is not set
1496# CONFIG_REISERFS_FS_XATTR is not set
1497# CONFIG_JFS_FS is not set
1498CONFIG_FS_POSIX_ACL=y
1499# CONFIG_XFS_FS is not set
1500# CONFIG_GFS2_FS is not set
1501# CONFIG_OCFS2_FS is not set
1502# CONFIG_MINIX_FS is not set
1503# CONFIG_ROMFS_FS is not set
1504CONFIG_INOTIFY=y
1505CONFIG_INOTIFY_USER=y
1506# CONFIG_QUOTA is not set
1507CONFIG_DNOTIFY=y
1508CONFIG_AUTOFS_FS=y
1509CONFIG_AUTOFS4_FS=y
1510CONFIG_FUSE_FS=y
1511
1512#
1513# CD-ROM/DVD Filesystems
1514#
1515CONFIG_ISO9660_FS=m
1516CONFIG_JOLIET=y
1517CONFIG_ZISOFS=y
1518CONFIG_UDF_FS=m
1519CONFIG_UDF_NLS=y
1520
1521#
1522# DOS/FAT/NT Filesystems
1523#
1524CONFIG_FAT_FS=m
1525CONFIG_MSDOS_FS=m
1526CONFIG_VFAT_FS=m
1527CONFIG_FAT_DEFAULT_CODEPAGE=936
1528CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
1529CONFIG_NTFS_FS=m
1530# CONFIG_NTFS_DEBUG is not set
1531CONFIG_NTFS_RW=y
1532
1533#
1534# Pseudo filesystems
1535#
1536CONFIG_PROC_FS=y
1537CONFIG_PROC_KCORE=y
1538CONFIG_PROC_SYSCTL=y
1539CONFIG_SYSFS=y
1540CONFIG_TMPFS=y
1541# CONFIG_TMPFS_POSIX_ACL is not set
1542# CONFIG_HUGETLB_PAGE is not set
1543CONFIG_RAMFS=y
1544# CONFIG_CONFIGFS_FS is not set
1545
1546#
1547# Miscellaneous filesystems
1548#
1549# CONFIG_ADFS_FS is not set
1550# CONFIG_AFFS_FS is not set
1551# CONFIG_HFS_FS is not set
1552# CONFIG_HFSPLUS_FS is not set
1553# CONFIG_BEFS_FS is not set
1554# CONFIG_BFS_FS is not set
1555# CONFIG_EFS_FS is not set
1556# CONFIG_JFFS2_FS is not set
1557# CONFIG_CRAMFS is not set
1558# CONFIG_VXFS_FS is not set
1559# CONFIG_HPFS_FS is not set
1560# CONFIG_QNX4FS_FS is not set
1561# CONFIG_SYSV_FS is not set
1562# CONFIG_UFS_FS is not set
1563
1564#
1565# Network File Systems
1566#
1567CONFIG_NFS_FS=m
1568CONFIG_NFS_V3=y
1569CONFIG_NFS_V3_ACL=y
1570CONFIG_NFS_V4=y
1571CONFIG_NFS_DIRECTIO=y
1572CONFIG_NFSD=m
1573CONFIG_NFSD_V2_ACL=y
1574CONFIG_NFSD_V3=y
1575CONFIG_NFSD_V3_ACL=y
1576CONFIG_NFSD_V4=y
1577CONFIG_NFSD_TCP=y
1578CONFIG_LOCKD=m
1579CONFIG_LOCKD_V4=y
1580CONFIG_EXPORTFS=m
1581CONFIG_NFS_ACL_SUPPORT=m
1582CONFIG_NFS_COMMON=y
1583CONFIG_SUNRPC=m
1584CONFIG_SUNRPC_GSS=m
1585# CONFIG_SUNRPC_BIND34 is not set
1586CONFIG_RPCSEC_GSS_KRB5=m
1587# CONFIG_RPCSEC_GSS_SPKM3 is not set
1588CONFIG_SMB_FS=m
1589CONFIG_SMB_NLS_DEFAULT=y
1590CONFIG_SMB_NLS_REMOTE="cp936"
1591CONFIG_CIFS=m
1592CONFIG_CIFS_STATS=y
1593CONFIG_CIFS_STATS2=y
1594CONFIG_CIFS_WEAK_PW_HASH=y
1595CONFIG_CIFS_XATTR=y
1596CONFIG_CIFS_POSIX=y
1597CONFIG_CIFS_DEBUG2=y
1598CONFIG_CIFS_EXPERIMENTAL=y
1599# CONFIG_NCP_FS is not set
1600# CONFIG_CODA_FS is not set
1601# CONFIG_AFS_FS is not set
1602# CONFIG_9P_FS is not set
1603
1604#
1605# Partition Types
1606#
1607CONFIG_PARTITION_ADVANCED=y
1608# CONFIG_ACORN_PARTITION is not set
1609# CONFIG_OSF_PARTITION is not set
1610# CONFIG_AMIGA_PARTITION is not set
1611# CONFIG_ATARI_PARTITION is not set
1612# CONFIG_MAC_PARTITION is not set
1613CONFIG_MSDOS_PARTITION=y
1614# CONFIG_BSD_DISKLABEL is not set
1615# CONFIG_MINIX_SUBPARTITION is not set
1616# CONFIG_SOLARIS_X86_PARTITION is not set
1617# CONFIG_UNIXWARE_DISKLABEL is not set
1618# CONFIG_LDM_PARTITION is not set
1619# CONFIG_SGI_PARTITION is not set
1620# CONFIG_ULTRIX_PARTITION is not set
1621# CONFIG_SUN_PARTITION is not set
1622# CONFIG_KARMA_PARTITION is not set
1623# CONFIG_EFI_PARTITION is not set
1624# CONFIG_SYSV68_PARTITION is not set
1625
1626#
1627# Native Language Support
1628#
1629CONFIG_NLS=y
1630CONFIG_NLS_DEFAULT="utf8"
1631# CONFIG_NLS_CODEPAGE_437 is not set
1632# CONFIG_NLS_CODEPAGE_737 is not set
1633# CONFIG_NLS_CODEPAGE_775 is not set
1634# CONFIG_NLS_CODEPAGE_850 is not set
1635# CONFIG_NLS_CODEPAGE_852 is not set
1636# CONFIG_NLS_CODEPAGE_855 is not set
1637# CONFIG_NLS_CODEPAGE_857 is not set
1638# CONFIG_NLS_CODEPAGE_860 is not set
1639# CONFIG_NLS_CODEPAGE_861 is not set
1640# CONFIG_NLS_CODEPAGE_862 is not set
1641# CONFIG_NLS_CODEPAGE_863 is not set
1642# CONFIG_NLS_CODEPAGE_864 is not set
1643# CONFIG_NLS_CODEPAGE_865 is not set
1644# CONFIG_NLS_CODEPAGE_866 is not set
1645# CONFIG_NLS_CODEPAGE_869 is not set
1646CONFIG_NLS_CODEPAGE_936=y
1647# CONFIG_NLS_CODEPAGE_950 is not set
1648# CONFIG_NLS_CODEPAGE_932 is not set
1649# CONFIG_NLS_CODEPAGE_949 is not set
1650# CONFIG_NLS_CODEPAGE_874 is not set
1651# CONFIG_NLS_ISO8859_8 is not set
1652# CONFIG_NLS_CODEPAGE_1250 is not set
1653# CONFIG_NLS_CODEPAGE_1251 is not set
1654# CONFIG_NLS_ASCII is not set
1655CONFIG_NLS_ISO8859_1=y
1656# CONFIG_NLS_ISO8859_2 is not set
1657# CONFIG_NLS_ISO8859_3 is not set
1658# CONFIG_NLS_ISO8859_4 is not set
1659# CONFIG_NLS_ISO8859_5 is not set
1660# CONFIG_NLS_ISO8859_6 is not set
1661# CONFIG_NLS_ISO8859_7 is not set
1662# CONFIG_NLS_ISO8859_9 is not set
1663# CONFIG_NLS_ISO8859_13 is not set
1664# CONFIG_NLS_ISO8859_14 is not set
1665# CONFIG_NLS_ISO8859_15 is not set
1666# CONFIG_NLS_KOI8_R is not set
1667# CONFIG_NLS_KOI8_U is not set
1668CONFIG_NLS_UTF8=y
1669
1670#
1671# Distributed Lock Manager
1672#
1673# CONFIG_DLM is not set
1674
1675#
1676# Profiling support
1677#
1678CONFIG_PROFILING=y
1679CONFIG_OPROFILE=m
1680
1681#
1682# Kernel hacking
1683#
1684CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1685# CONFIG_PRINTK_TIME is not set
1686# CONFIG_ENABLE_MUST_CHECK is not set
1687# CONFIG_MAGIC_SYSRQ is not set
1688# CONFIG_UNUSED_SYMBOLS is not set
1689# CONFIG_DEBUG_FS is not set
1690# CONFIG_HEADERS_CHECK is not set
1691# CONFIG_DEBUG_KERNEL is not set
1692CONFIG_CROSSCOMPILE=y
1693CONFIG_CMDLINE=""
1694
1695#
1696# Security options
1697#
1698# CONFIG_KEYS is not set
1699# CONFIG_SECURITY is not set
1700
1701#
1702# Cryptographic options
1703#
1704CONFIG_CRYPTO=y
1705CONFIG_CRYPTO_ALGAPI=y
1706CONFIG_CRYPTO_BLKCIPHER=m
1707CONFIG_CRYPTO_HASH=y
1708CONFIG_CRYPTO_MANAGER=y
1709CONFIG_CRYPTO_HMAC=y
1710# CONFIG_CRYPTO_XCBC is not set
1711# CONFIG_CRYPTO_NULL is not set
1712# CONFIG_CRYPTO_MD4 is not set
1713CONFIG_CRYPTO_MD5=m
1714CONFIG_CRYPTO_SHA1=m
1715# CONFIG_CRYPTO_SHA256 is not set
1716# CONFIG_CRYPTO_SHA512 is not set
1717# CONFIG_CRYPTO_WP512 is not set
1718# CONFIG_CRYPTO_TGR192 is not set
1719# CONFIG_CRYPTO_GF128MUL is not set
1720CONFIG_CRYPTO_ECB=m
1721CONFIG_CRYPTO_CBC=m
1722CONFIG_CRYPTO_PCBC=m
1723# CONFIG_CRYPTO_LRW is not set
1724# CONFIG_CRYPTO_CRYPTD is not set
1725CONFIG_CRYPTO_DES=m
1726# CONFIG_CRYPTO_FCRYPT is not set
1727# CONFIG_CRYPTO_BLOWFISH is not set
1728# CONFIG_CRYPTO_TWOFISH is not set
1729# CONFIG_CRYPTO_SERPENT is not set
1730# CONFIG_CRYPTO_AES is not set
1731# CONFIG_CRYPTO_CAST5 is not set
1732# CONFIG_CRYPTO_CAST6 is not set
1733# CONFIG_CRYPTO_TEA is not set
1734CONFIG_CRYPTO_ARC4=m
1735# CONFIG_CRYPTO_KHAZAD is not set
1736# CONFIG_CRYPTO_ANUBIS is not set
1737CONFIG_CRYPTO_DEFLATE=m
1738# CONFIG_CRYPTO_MICHAEL_MIC is not set
1739# CONFIG_CRYPTO_CRC32C is not set
1740# CONFIG_CRYPTO_CAMELLIA is not set
1741# CONFIG_CRYPTO_TEST is not set
1742
1743#
1744# Hardware crypto devices
1745#
1746
1747#
1748# Library routines
1749#
1750CONFIG_BITREVERSE=y
1751CONFIG_CRC_CCITT=y
1752# CONFIG_CRC16 is not set
1753# CONFIG_CRC_ITU_T is not set
1754CONFIG_CRC32=y
1755# CONFIG_LIBCRC32C is not set
1756CONFIG_ZLIB_INFLATE=m
1757CONFIG_ZLIB_DEFLATE=m
1758CONFIG_TEXTSEARCH=y
1759CONFIG_TEXTSEARCH_KMP=m
1760CONFIG_TEXTSEARCH_BM=m
1761CONFIG_TEXTSEARCH_FSM=m
1762CONFIG_PLIST=y
1763CONFIG_HAS_IOMEM=y
1764CONFIG_HAS_IOPORT=y
1765CONFIG_HAS_DMA=y
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 7ec618f3c8b9..405c9f505a77 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 9ddc3eff4793..a9dcbcf563cb 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index 8fc18809d5ff..a040459bec11 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index 9331cb0a19b1..dd04eece9fd3 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29CONFIG_MACH_JAZZ=y 28CONFIG_MACH_JAZZ=y
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_MACH_JAZZ=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 1b364cf69140..9a25e770abd8 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig
deleted file mode 100644
index fd4272c1458a..000000000000
--- a/arch/mips/configs/lasat200_defconfig
+++ /dev/null
@@ -1,1118 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20
4# Tue Feb 20 21:47:34 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set
30CONFIG_LASAT=y
31# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set
34# CONFIG_WR_PPMC is not set
35# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set
43# CONFIG_PNX8550_STB810 is not set
44# CONFIG_DDB5477 is not set
45# CONFIG_MACH_VR41XX is not set
46# CONFIG_PMC_YOSEMITE is not set
47# CONFIG_QEMU is not set
48# CONFIG_MARKEINS is not set
49# CONFIG_SGI_IP22 is not set
50# CONFIG_SGI_IP27 is not set
51# CONFIG_SGI_IP32 is not set
52# CONFIG_SIBYTE_BIGSUR is not set
53# CONFIG_SIBYTE_SWARM is not set
54# CONFIG_SIBYTE_SENTOSA is not set
55# CONFIG_SIBYTE_RHONE is not set
56# CONFIG_SIBYTE_CARMEL is not set
57# CONFIG_SIBYTE_PTSWARM is not set
58# CONFIG_SIBYTE_LITTLESUR is not set
59# CONFIG_SIBYTE_CRHINE is not set
60# CONFIG_SIBYTE_CRHONE is not set
61# CONFIG_SNI_RM is not set
62# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set
64# CONFIG_TOSHIBA_RBTX4938 is not set
65CONFIG_PICVUE=y
66CONFIG_PICVUE_PROC=y
67CONFIG_DS1603=y
68CONFIG_LASAT_SYSCTL=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set
71# CONFIG_ARCH_HAS_ILOG2_U64 is not set
72CONFIG_GENERIC_FIND_NEXT_BIT=y
73CONFIG_GENERIC_HWEIGHT=y
74CONFIG_GENERIC_CALIBRATE_DELAY=y
75CONFIG_GENERIC_TIME=y
76CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
77CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
78CONFIG_DMA_NONCOHERENT=y
79CONFIG_DMA_NEED_PCI_MAP_STATE=y
80CONFIG_MIPS_NILE4=y
81# CONFIG_CPU_BIG_ENDIAN is not set
82CONFIG_CPU_LITTLE_ENDIAN=y
83CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
84CONFIG_MIPS_GT64120=y
85CONFIG_MIPS_L1_CACHE_SHIFT=5
86
87#
88# CPU selection
89#
90# CONFIG_CPU_MIPS32_R1 is not set
91# CONFIG_CPU_MIPS32_R2 is not set
92# CONFIG_CPU_MIPS64_R1 is not set
93# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set
95# CONFIG_CPU_TX39XX is not set
96# CONFIG_CPU_VR41XX is not set
97# CONFIG_CPU_R4300 is not set
98# CONFIG_CPU_R4X00 is not set
99# CONFIG_CPU_TX49XX is not set
100CONFIG_CPU_R5000=y
101# CONFIG_CPU_R5432 is not set
102# CONFIG_CPU_R6000 is not set
103# CONFIG_CPU_NEVADA is not set
104# CONFIG_CPU_R8000 is not set
105# CONFIG_CPU_R10000 is not set
106# CONFIG_CPU_RM7000 is not set
107# CONFIG_CPU_RM9000 is not set
108# CONFIG_CPU_SB1 is not set
109CONFIG_SYS_HAS_CPU_R5000=y
110CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
111CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
112CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
113CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
114
115#
116# Kernel type
117#
118CONFIG_32BIT=y
119# CONFIG_64BIT is not set
120CONFIG_PAGE_SIZE_4KB=y
121# CONFIG_PAGE_SIZE_8KB is not set
122# CONFIG_PAGE_SIZE_16KB is not set
123# CONFIG_PAGE_SIZE_64KB is not set
124CONFIG_BOARD_SCACHE=y
125CONFIG_R5000_CPU_SCACHE=y
126CONFIG_MIPS_MT_DISABLED=y
127# CONFIG_MIPS_MT_SMP is not set
128# CONFIG_MIPS_MT_SMTC is not set
129# CONFIG_MIPS_VPE_LOADER is not set
130# CONFIG_64BIT_PHYS_ADDR is not set
131CONFIG_CPU_HAS_LLSC=y
132CONFIG_CPU_HAS_SYNC=y
133CONFIG_GENERIC_HARDIRQS=y
134CONFIG_GENERIC_IRQ_PROBE=y
135CONFIG_ARCH_FLATMEM_ENABLE=y
136CONFIG_SELECT_MEMORY_MODEL=y
137CONFIG_FLATMEM_MANUAL=y
138# CONFIG_DISCONTIGMEM_MANUAL is not set
139# CONFIG_SPARSEMEM_MANUAL is not set
140CONFIG_FLATMEM=y
141CONFIG_FLAT_NODE_MEM_MAP=y
142# CONFIG_SPARSEMEM_STATIC is not set
143CONFIG_SPLIT_PTLOCK_CPUS=4
144# CONFIG_RESOURCES_64BIT is not set
145CONFIG_ZONE_DMA_FLAG=1
146# CONFIG_HZ_48 is not set
147# CONFIG_HZ_100 is not set
148# CONFIG_HZ_128 is not set
149# CONFIG_HZ_250 is not set
150# CONFIG_HZ_256 is not set
151CONFIG_HZ_1000=y
152# CONFIG_HZ_1024 is not set
153CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
154CONFIG_HZ=1000
155CONFIG_PREEMPT_NONE=y
156# CONFIG_PREEMPT_VOLUNTARY is not set
157# CONFIG_PREEMPT is not set
158# CONFIG_KEXEC is not set
159CONFIG_LOCKDEP_SUPPORT=y
160CONFIG_STACKTRACE_SUPPORT=y
161CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
162
163#
164# Code maturity level options
165#
166CONFIG_EXPERIMENTAL=y
167CONFIG_BROKEN_ON_SMP=y
168CONFIG_INIT_ENV_ARG_LIMIT=32
169
170#
171# General setup
172#
173CONFIG_LOCALVERSION=""
174CONFIG_LOCALVERSION_AUTO=y
175CONFIG_SWAP=y
176CONFIG_SYSVIPC=y
177# CONFIG_IPC_NS is not set
178CONFIG_SYSVIPC_SYSCTL=y
179# CONFIG_POSIX_MQUEUE is not set
180# CONFIG_BSD_PROCESS_ACCT is not set
181# CONFIG_TASKSTATS is not set
182# CONFIG_UTS_NS is not set
183# CONFIG_AUDIT is not set
184# CONFIG_IKCONFIG is not set
185CONFIG_SYSFS_DEPRECATED=y
186CONFIG_RELAY=y
187# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
188CONFIG_SYSCTL=y
189CONFIG_EMBEDDED=y
190CONFIG_SYSCTL_SYSCALL=y
191CONFIG_KALLSYMS=y
192# CONFIG_KALLSYMS_EXTRA_PASS is not set
193CONFIG_HOTPLUG=y
194CONFIG_PRINTK=y
195CONFIG_BUG=y
196CONFIG_ELF_CORE=y
197CONFIG_BASE_FULL=y
198CONFIG_FUTEX=y
199CONFIG_EPOLL=y
200CONFIG_SHMEM=y
201CONFIG_SLAB=y
202CONFIG_VM_EVENT_COUNTERS=y
203CONFIG_RT_MUTEXES=y
204# CONFIG_TINY_SHMEM is not set
205CONFIG_BASE_SMALL=0
206# CONFIG_SLOB is not set
207
208#
209# Loadable module support
210#
211CONFIG_MODULES=y
212CONFIG_MODULE_UNLOAD=y
213# CONFIG_MODULE_FORCE_UNLOAD is not set
214CONFIG_MODVERSIONS=y
215CONFIG_MODULE_SRCVERSION_ALL=y
216CONFIG_KMOD=y
217
218#
219# Block layer
220#
221CONFIG_BLOCK=y
222# CONFIG_LBD is not set
223# CONFIG_BLK_DEV_IO_TRACE is not set
224# CONFIG_LSF is not set
225
226#
227# IO Schedulers
228#
229CONFIG_IOSCHED_NOOP=y
230CONFIG_IOSCHED_AS=y
231CONFIG_IOSCHED_DEADLINE=y
232CONFIG_IOSCHED_CFQ=y
233CONFIG_DEFAULT_AS=y
234# CONFIG_DEFAULT_DEADLINE is not set
235# CONFIG_DEFAULT_CFQ is not set
236# CONFIG_DEFAULT_NOOP is not set
237CONFIG_DEFAULT_IOSCHED="anticipatory"
238
239#
240# Bus options (PCI, PCMCIA, EISA, ISA, TC)
241#
242CONFIG_HW_HAS_PCI=y
243CONFIG_PCI=y
244CONFIG_MMU=y
245
246#
247# PCCARD (PCMCIA/CardBus) support
248#
249# CONFIG_PCCARD is not set
250
251#
252# PCI Hotplug Support
253#
254# CONFIG_HOTPLUG_PCI is not set
255
256#
257# Executable file formats
258#
259CONFIG_BINFMT_ELF=y
260# CONFIG_BINFMT_MISC is not set
261CONFIG_TRAD_SIGNALS=y
262
263#
264# Power management options
265#
266CONFIG_PM=y
267# CONFIG_PM_LEGACY is not set
268# CONFIG_PM_DEBUG is not set
269# CONFIG_PM_SYSFS_DEPRECATED is not set
270
271#
272# Networking
273#
274CONFIG_NET=y
275
276#
277# Networking options
278#
279# CONFIG_NETDEBUG is not set
280# CONFIG_PACKET is not set
281CONFIG_UNIX=y
282CONFIG_XFRM=y
283CONFIG_XFRM_USER=m
284# CONFIG_XFRM_SUB_POLICY is not set
285CONFIG_XFRM_MIGRATE=y
286CONFIG_NET_KEY=y
287CONFIG_NET_KEY_MIGRATE=y
288CONFIG_INET=y
289# CONFIG_IP_MULTICAST is not set
290# CONFIG_IP_ADVANCED_ROUTER is not set
291CONFIG_IP_FIB_HASH=y
292# CONFIG_IP_PNP is not set
293# CONFIG_NET_IPIP is not set
294# CONFIG_NET_IPGRE is not set
295# CONFIG_ARPD is not set
296# CONFIG_SYN_COOKIES is not set
297# CONFIG_INET_AH is not set
298# CONFIG_INET_ESP is not set
299# CONFIG_INET_IPCOMP is not set
300# CONFIG_INET_XFRM_TUNNEL is not set
301# CONFIG_INET_TUNNEL is not set
302CONFIG_INET_XFRM_MODE_TRANSPORT=m
303CONFIG_INET_XFRM_MODE_TUNNEL=m
304CONFIG_INET_XFRM_MODE_BEET=m
305CONFIG_INET_DIAG=y
306CONFIG_INET_TCP_DIAG=y
307# CONFIG_TCP_CONG_ADVANCED is not set
308CONFIG_TCP_CONG_CUBIC=y
309CONFIG_DEFAULT_TCP_CONG="cubic"
310CONFIG_TCP_MD5SIG=y
311# CONFIG_IPV6 is not set
312# CONFIG_INET6_XFRM_TUNNEL is not set
313# CONFIG_INET6_TUNNEL is not set
314CONFIG_NETWORK_SECMARK=y
315# CONFIG_NETFILTER is not set
316
317#
318# DCCP Configuration (EXPERIMENTAL)
319#
320# CONFIG_IP_DCCP is not set
321
322#
323# SCTP Configuration (EXPERIMENTAL)
324#
325# CONFIG_IP_SCTP is not set
326
327#
328# TIPC Configuration (EXPERIMENTAL)
329#
330# CONFIG_TIPC is not set
331# CONFIG_ATM is not set
332# CONFIG_BRIDGE is not set
333# CONFIG_VLAN_8021Q is not set
334# CONFIG_DECNET is not set
335# CONFIG_LLC2 is not set
336# CONFIG_IPX is not set
337# CONFIG_ATALK is not set
338# CONFIG_X25 is not set
339# CONFIG_LAPB is not set
340# CONFIG_ECONET is not set
341# CONFIG_WAN_ROUTER is not set
342
343#
344# QoS and/or fair queueing
345#
346# CONFIG_NET_SCHED is not set
347
348#
349# Network testing
350#
351# CONFIG_NET_PKTGEN is not set
352# CONFIG_HAMRADIO is not set
353# CONFIG_IRDA is not set
354# CONFIG_BT is not set
355CONFIG_IEEE80211=m
356# CONFIG_IEEE80211_DEBUG is not set
357CONFIG_IEEE80211_CRYPT_WEP=m
358CONFIG_IEEE80211_CRYPT_CCMP=m
359CONFIG_IEEE80211_SOFTMAC=m
360# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
361CONFIG_WIRELESS_EXT=y
362
363#
364# Device Drivers
365#
366
367#
368# Generic Driver Options
369#
370CONFIG_STANDALONE=y
371CONFIG_PREVENT_FIRMWARE_BUILD=y
372CONFIG_FW_LOADER=m
373# CONFIG_SYS_HYPERVISOR is not set
374
375#
376# Connector - unified userspace <-> kernelspace linker
377#
378CONFIG_CONNECTOR=m
379
380#
381# Memory Technology Devices (MTD)
382#
383CONFIG_MTD=y
384# CONFIG_MTD_DEBUG is not set
385# CONFIG_MTD_CONCAT is not set
386CONFIG_MTD_PARTITIONS=y
387# CONFIG_MTD_REDBOOT_PARTS is not set
388# CONFIG_MTD_CMDLINE_PARTS is not set
389
390#
391# User Modules And Translation Layers
392#
393CONFIG_MTD_CHAR=y
394CONFIG_MTD_BLKDEVS=y
395CONFIG_MTD_BLOCK=y
396# CONFIG_FTL is not set
397# CONFIG_NFTL is not set
398# CONFIG_INFTL is not set
399# CONFIG_RFD_FTL is not set
400# CONFIG_SSFDC is not set
401
402#
403# RAM/ROM/Flash chip drivers
404#
405CONFIG_MTD_CFI=y
406# CONFIG_MTD_JEDECPROBE is not set
407CONFIG_MTD_GEN_PROBE=y
408# CONFIG_MTD_CFI_ADV_OPTIONS is not set
409CONFIG_MTD_MAP_BANK_WIDTH_1=y
410CONFIG_MTD_MAP_BANK_WIDTH_2=y
411CONFIG_MTD_MAP_BANK_WIDTH_4=y
412# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
413# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
414# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
415CONFIG_MTD_CFI_I1=y
416CONFIG_MTD_CFI_I2=y
417# CONFIG_MTD_CFI_I4 is not set
418# CONFIG_MTD_CFI_I8 is not set
419# CONFIG_MTD_CFI_INTELEXT is not set
420CONFIG_MTD_CFI_AMDSTD=y
421# CONFIG_MTD_CFI_STAA is not set
422CONFIG_MTD_CFI_UTIL=y
423# CONFIG_MTD_RAM is not set
424# CONFIG_MTD_ROM is not set
425# CONFIG_MTD_ABSENT is not set
426# CONFIG_MTD_OBSOLETE_CHIPS is not set
427
428#
429# Mapping drivers for chip access
430#
431# CONFIG_MTD_COMPLEX_MAPPINGS is not set
432# CONFIG_MTD_PHYSMAP is not set
433CONFIG_MTD_LASAT=y
434# CONFIG_MTD_PLATRAM is not set
435
436#
437# Self-contained MTD device drivers
438#
439# CONFIG_MTD_PMC551 is not set
440# CONFIG_MTD_SLRAM is not set
441# CONFIG_MTD_PHRAM is not set
442# CONFIG_MTD_MTDRAM is not set
443# CONFIG_MTD_BLOCK2MTD is not set
444
445#
446# Disk-On-Chip Device Drivers
447#
448# CONFIG_MTD_DOC2000 is not set
449# CONFIG_MTD_DOC2001 is not set
450# CONFIG_MTD_DOC2001PLUS is not set
451
452#
453# NAND Flash Device Drivers
454#
455# CONFIG_MTD_NAND is not set
456
457#
458# OneNAND Flash Device Drivers
459#
460# CONFIG_MTD_ONENAND is not set
461
462#
463# Parallel port support
464#
465# CONFIG_PARPORT is not set
466
467#
468# Plug and Play support
469#
470# CONFIG_PNPACPI is not set
471
472#
473# Block devices
474#
475# CONFIG_BLK_CPQ_DA is not set
476# CONFIG_BLK_CPQ_CISS_DA is not set
477# CONFIG_BLK_DEV_DAC960 is not set
478# CONFIG_BLK_DEV_UMEM is not set
479# CONFIG_BLK_DEV_COW_COMMON is not set
480# CONFIG_BLK_DEV_LOOP is not set
481# CONFIG_BLK_DEV_NBD is not set
482# CONFIG_BLK_DEV_SX8 is not set
483# CONFIG_BLK_DEV_RAM is not set
484# CONFIG_BLK_DEV_INITRD is not set
485CONFIG_CDROM_PKTCDVD=m
486CONFIG_CDROM_PKTCDVD_BUFFERS=8
487# CONFIG_CDROM_PKTCDVD_WCACHE is not set
488CONFIG_ATA_OVER_ETH=m
489
490#
491# Misc devices
492#
493CONFIG_SGI_IOC4=m
494# CONFIG_TIFM_CORE is not set
495
496#
497# ATA/ATAPI/MFM/RLL support
498#
499CONFIG_IDE=y
500CONFIG_IDE_MAX_HWIFS=4
501CONFIG_BLK_DEV_IDE=y
502
503#
504# Please see Documentation/ide.txt for help/info on IDE drives
505#
506# CONFIG_BLK_DEV_IDE_SATA is not set
507CONFIG_BLK_DEV_IDEDISK=y
508CONFIG_IDEDISK_MULTI_MODE=y
509# CONFIG_BLK_DEV_IDECD is not set
510# CONFIG_BLK_DEV_IDETAPE is not set
511# CONFIG_BLK_DEV_IDEFLOPPY is not set
512# CONFIG_IDE_TASK_IOCTL is not set
513
514#
515# IDE chipset support/bugfixes
516#
517CONFIG_IDE_GENERIC=y
518CONFIG_BLK_DEV_IDEPCI=y
519# CONFIG_IDEPCI_SHARE_IRQ is not set
520# CONFIG_BLK_DEV_OFFBOARD is not set
521CONFIG_BLK_DEV_GENERIC=y
522# CONFIG_BLK_DEV_OPTI621 is not set
523CONFIG_BLK_DEV_IDEDMA_PCI=y
524# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
525CONFIG_IDEDMA_PCI_AUTO=y
526# CONFIG_IDEDMA_ONLYDISK is not set
527# CONFIG_BLK_DEV_AEC62XX is not set
528# CONFIG_BLK_DEV_ALI15X3 is not set
529# CONFIG_BLK_DEV_AMD74XX is not set
530CONFIG_BLK_DEV_CMD64X=y
531# CONFIG_BLK_DEV_TRIFLEX is not set
532# CONFIG_BLK_DEV_CY82C693 is not set
533# CONFIG_BLK_DEV_CS5520 is not set
534# CONFIG_BLK_DEV_CS5530 is not set
535# CONFIG_BLK_DEV_HPT34X is not set
536# CONFIG_BLK_DEV_HPT366 is not set
537# CONFIG_BLK_DEV_JMICRON is not set
538# CONFIG_BLK_DEV_SC1200 is not set
539# CONFIG_BLK_DEV_PIIX is not set
540CONFIG_BLK_DEV_IT8213=m
541# CONFIG_BLK_DEV_IT821X is not set
542# CONFIG_BLK_DEV_NS87415 is not set
543# CONFIG_BLK_DEV_PDC202XX_OLD is not set
544# CONFIG_BLK_DEV_PDC202XX_NEW is not set
545# CONFIG_BLK_DEV_SVWKS is not set
546# CONFIG_BLK_DEV_SIIMAGE is not set
547# CONFIG_BLK_DEV_SLC90E66 is not set
548# CONFIG_BLK_DEV_TRM290 is not set
549# CONFIG_BLK_DEV_VIA82CXXX is not set
550CONFIG_BLK_DEV_TC86C001=m
551# CONFIG_IDE_ARM is not set
552CONFIG_BLK_DEV_IDEDMA=y
553# CONFIG_IDEDMA_IVB is not set
554CONFIG_IDEDMA_AUTO=y
555# CONFIG_BLK_DEV_HD is not set
556
557#
558# SCSI device support
559#
560CONFIG_RAID_ATTRS=m
561# CONFIG_SCSI is not set
562# CONFIG_SCSI_NETLINK is not set
563
564#
565# Serial ATA (prod) and Parallel ATA (experimental) drivers
566#
567# CONFIG_ATA is not set
568
569#
570# Multi-device support (RAID and LVM)
571#
572# CONFIG_MD is not set
573
574#
575# Fusion MPT device support
576#
577# CONFIG_FUSION is not set
578
579#
580# IEEE 1394 (FireWire) support
581#
582# CONFIG_IEEE1394 is not set
583
584#
585# I2O device support
586#
587# CONFIG_I2O is not set
588
589#
590# Network device support
591#
592CONFIG_NETDEVICES=y
593# CONFIG_DUMMY is not set
594# CONFIG_BONDING is not set
595# CONFIG_EQUALIZER is not set
596# CONFIG_TUN is not set
597
598#
599# ARCnet devices
600#
601# CONFIG_ARCNET is not set
602
603#
604# PHY device support
605#
606CONFIG_PHYLIB=m
607
608#
609# MII PHY device drivers
610#
611CONFIG_MARVELL_PHY=m
612CONFIG_DAVICOM_PHY=m
613CONFIG_QSEMI_PHY=m
614CONFIG_LXT_PHY=m
615CONFIG_CICADA_PHY=m
616CONFIG_VITESSE_PHY=m
617CONFIG_SMSC_PHY=m
618# CONFIG_BROADCOM_PHY is not set
619# CONFIG_FIXED_PHY is not set
620
621#
622# Ethernet (10 or 100Mbit)
623#
624CONFIG_NET_ETHERNET=y
625# CONFIG_MII is not set
626# CONFIG_HAPPYMEAL is not set
627# CONFIG_SUNGEM is not set
628# CONFIG_CASSINI is not set
629# CONFIG_NET_VENDOR_3COM is not set
630# CONFIG_DM9000 is not set
631
632#
633# Tulip family network device support
634#
635# CONFIG_NET_TULIP is not set
636# CONFIG_HP100 is not set
637# CONFIG_NET_PCI is not set
638
639#
640# Ethernet (1000 Mbit)
641#
642# CONFIG_ACENIC is not set
643# CONFIG_DL2K is not set
644# CONFIG_E1000 is not set
645# CONFIG_NS83820 is not set
646# CONFIG_HAMACHI is not set
647# CONFIG_YELLOWFIN is not set
648# CONFIG_R8169 is not set
649# CONFIG_SIS190 is not set
650# CONFIG_SKGE is not set
651# CONFIG_SKY2 is not set
652# CONFIG_SK98LIN is not set
653# CONFIG_TIGON3 is not set
654# CONFIG_BNX2 is not set
655CONFIG_QLA3XXX=m
656# CONFIG_ATL1 is not set
657
658#
659# Ethernet (10000 Mbit)
660#
661# CONFIG_CHELSIO_T1 is not set
662CONFIG_CHELSIO_T3=m
663# CONFIG_IXGB is not set
664# CONFIG_S2IO is not set
665# CONFIG_MYRI10GE is not set
666CONFIG_NETXEN_NIC=m
667
668#
669# Token Ring devices
670#
671# CONFIG_TR is not set
672
673#
674# Wireless LAN (non-hamradio)
675#
676# CONFIG_NET_RADIO is not set
677
678#
679# Wan interfaces
680#
681# CONFIG_WAN is not set
682# CONFIG_FDDI is not set
683# CONFIG_HIPPI is not set
684# CONFIG_PPP is not set
685# CONFIG_SLIP is not set
686# CONFIG_SHAPER is not set
687# CONFIG_NETCONSOLE is not set
688# CONFIG_NETPOLL is not set
689# CONFIG_NET_POLL_CONTROLLER is not set
690
691#
692# ISDN subsystem
693#
694# CONFIG_ISDN is not set
695
696#
697# Telephony Support
698#
699# CONFIG_PHONE is not set
700
701#
702# Input device support
703#
704CONFIG_INPUT=y
705# CONFIG_INPUT_FF_MEMLESS is not set
706
707#
708# Userland interfaces
709#
710CONFIG_INPUT_MOUSEDEV=y
711CONFIG_INPUT_MOUSEDEV_PSAUX=y
712CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
713CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
714# CONFIG_INPUT_JOYDEV is not set
715# CONFIG_INPUT_TSDEV is not set
716# CONFIG_INPUT_EVDEV is not set
717# CONFIG_INPUT_EVBUG is not set
718
719#
720# Input Device Drivers
721#
722# CONFIG_INPUT_KEYBOARD is not set
723# CONFIG_INPUT_MOUSE is not set
724# CONFIG_INPUT_JOYSTICK is not set
725# CONFIG_INPUT_TOUCHSCREEN is not set
726# CONFIG_INPUT_MISC is not set
727
728#
729# Hardware I/O ports
730#
731CONFIG_SERIO=y
732CONFIG_SERIO_I8042=y
733CONFIG_SERIO_SERPORT=y
734# CONFIG_SERIO_PCIPS2 is not set
735# CONFIG_SERIO_LIBPS2 is not set
736CONFIG_SERIO_RAW=m
737# CONFIG_GAMEPORT is not set
738
739#
740# Character devices
741#
742CONFIG_VT=y
743CONFIG_VT_CONSOLE=y
744CONFIG_HW_CONSOLE=y
745CONFIG_VT_HW_CONSOLE_BINDING=y
746# CONFIG_SERIAL_NONSTANDARD is not set
747
748#
749# Serial drivers
750#
751CONFIG_SERIAL_8250=y
752CONFIG_SERIAL_8250_CONSOLE=y
753CONFIG_SERIAL_8250_PCI=y
754CONFIG_SERIAL_8250_NR_UARTS=4
755CONFIG_SERIAL_8250_RUNTIME_UARTS=4
756# CONFIG_SERIAL_8250_EXTENDED is not set
757
758#
759# Non-8250 serial port support
760#
761CONFIG_SERIAL_CORE=y
762CONFIG_SERIAL_CORE_CONSOLE=y
763# CONFIG_SERIAL_JSM is not set
764CONFIG_UNIX98_PTYS=y
765CONFIG_LEGACY_PTYS=y
766CONFIG_LEGACY_PTY_COUNT=256
767
768#
769# IPMI
770#
771# CONFIG_IPMI_HANDLER is not set
772
773#
774# Watchdog Cards
775#
776# CONFIG_WATCHDOG is not set
777# CONFIG_HW_RANDOM is not set
778# CONFIG_RTC is not set
779# CONFIG_GEN_RTC is not set
780# CONFIG_DTLK is not set
781# CONFIG_R3964 is not set
782# CONFIG_APPLICOM is not set
783# CONFIG_DRM is not set
784# CONFIG_RAW_DRIVER is not set
785
786#
787# TPM devices
788#
789# CONFIG_TCG_TPM is not set
790
791#
792# I2C support
793#
794# CONFIG_I2C is not set
795
796#
797# SPI support
798#
799# CONFIG_SPI is not set
800# CONFIG_SPI_MASTER is not set
801
802#
803# Dallas's 1-wire bus
804#
805# CONFIG_W1 is not set
806
807#
808# Hardware Monitoring support
809#
810# CONFIG_HWMON is not set
811# CONFIG_HWMON_VID is not set
812
813#
814# Multimedia devices
815#
816# CONFIG_VIDEO_DEV is not set
817
818#
819# Digital Video Broadcasting Devices
820#
821# CONFIG_DVB is not set
822
823#
824# Graphics support
825#
826# CONFIG_FIRMWARE_EDID is not set
827# CONFIG_FB is not set
828
829#
830# Console display driver support
831#
832# CONFIG_VGA_CONSOLE is not set
833CONFIG_DUMMY_CONSOLE=y
834# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
835
836#
837# Sound
838#
839# CONFIG_SOUND is not set
840
841#
842# HID Devices
843#
844# CONFIG_HID is not set
845
846#
847# USB support
848#
849CONFIG_USB_ARCH_HAS_HCD=y
850CONFIG_USB_ARCH_HAS_OHCI=y
851CONFIG_USB_ARCH_HAS_EHCI=y
852# CONFIG_USB is not set
853
854#
855# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
856#
857
858#
859# USB Gadget Support
860#
861# CONFIG_USB_GADGET is not set
862
863#
864# MMC/SD Card support
865#
866# CONFIG_MMC is not set
867
868#
869# LED devices
870#
871# CONFIG_NEW_LEDS is not set
872
873#
874# LED drivers
875#
876
877#
878# LED Triggers
879#
880
881#
882# InfiniBand support
883#
884# CONFIG_INFINIBAND is not set
885
886#
887# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
888#
889
890#
891# Real Time Clock
892#
893# CONFIG_RTC_CLASS is not set
894
895#
896# DMA Engine support
897#
898# CONFIG_DMA_ENGINE is not set
899
900#
901# DMA Clients
902#
903
904#
905# DMA Devices
906#
907
908#
909# Auxiliary Display support
910#
911
912#
913# Virtualization
914#
915
916#
917# File systems
918#
919CONFIG_EXT2_FS=y
920# CONFIG_EXT2_FS_XATTR is not set
921# CONFIG_EXT2_FS_XIP is not set
922CONFIG_EXT3_FS=y
923CONFIG_EXT3_FS_XATTR=y
924# CONFIG_EXT3_FS_POSIX_ACL is not set
925CONFIG_EXT3_FS_SECURITY=y
926# CONFIG_EXT4DEV_FS is not set
927CONFIG_JBD=y
928# CONFIG_JBD_DEBUG is not set
929CONFIG_FS_MBCACHE=y
930# CONFIG_REISERFS_FS is not set
931# CONFIG_JFS_FS is not set
932CONFIG_FS_POSIX_ACL=y
933# CONFIG_XFS_FS is not set
934# CONFIG_GFS2_FS is not set
935# CONFIG_OCFS2_FS is not set
936# CONFIG_MINIX_FS is not set
937# CONFIG_ROMFS_FS is not set
938CONFIG_INOTIFY=y
939CONFIG_INOTIFY_USER=y
940# CONFIG_QUOTA is not set
941CONFIG_DNOTIFY=y
942# CONFIG_AUTOFS_FS is not set
943# CONFIG_AUTOFS4_FS is not set
944CONFIG_FUSE_FS=m
945CONFIG_GENERIC_ACL=y
946
947#
948# CD-ROM/DVD Filesystems
949#
950# CONFIG_ISO9660_FS is not set
951# CONFIG_UDF_FS is not set
952
953#
954# DOS/FAT/NT Filesystems
955#
956# CONFIG_MSDOS_FS is not set
957# CONFIG_VFAT_FS is not set
958# CONFIG_NTFS_FS is not set
959
960#
961# Pseudo filesystems
962#
963CONFIG_PROC_FS=y
964CONFIG_PROC_KCORE=y
965CONFIG_PROC_SYSCTL=y
966CONFIG_SYSFS=y
967CONFIG_TMPFS=y
968CONFIG_TMPFS_POSIX_ACL=y
969# CONFIG_HUGETLB_PAGE is not set
970CONFIG_RAMFS=y
971CONFIG_CONFIGFS_FS=m
972
973#
974# Miscellaneous filesystems
975#
976# CONFIG_ADFS_FS is not set
977# CONFIG_AFFS_FS is not set
978# CONFIG_ECRYPT_FS is not set
979# CONFIG_HFS_FS is not set
980# CONFIG_HFSPLUS_FS is not set
981# CONFIG_BEFS_FS is not set
982# CONFIG_BFS_FS is not set
983# CONFIG_EFS_FS is not set
984# CONFIG_JFFS2_FS is not set
985# CONFIG_CRAMFS is not set
986# CONFIG_VXFS_FS is not set
987# CONFIG_HPFS_FS is not set
988# CONFIG_QNX4FS_FS is not set
989# CONFIG_SYSV_FS is not set
990# CONFIG_UFS_FS is not set
991
992#
993# Network File Systems
994#
995CONFIG_NFS_FS=y
996CONFIG_NFS_V3=y
997# CONFIG_NFS_V3_ACL is not set
998# CONFIG_NFS_V4 is not set
999# CONFIG_NFS_DIRECTIO is not set
1000# CONFIG_NFSD is not set
1001CONFIG_LOCKD=y
1002CONFIG_LOCKD_V4=y
1003CONFIG_NFS_COMMON=y
1004CONFIG_SUNRPC=y
1005# CONFIG_RPCSEC_GSS_KRB5 is not set
1006# CONFIG_RPCSEC_GSS_SPKM3 is not set
1007# CONFIG_SMB_FS is not set
1008# CONFIG_CIFS is not set
1009# CONFIG_NCP_FS is not set
1010# CONFIG_CODA_FS is not set
1011# CONFIG_AFS_FS is not set
1012# CONFIG_9P_FS is not set
1013
1014#
1015# Partition Types
1016#
1017# CONFIG_PARTITION_ADVANCED is not set
1018CONFIG_MSDOS_PARTITION=y
1019
1020#
1021# Native Language Support
1022#
1023# CONFIG_NLS is not set
1024
1025#
1026# Distributed Lock Manager
1027#
1028CONFIG_DLM=m
1029CONFIG_DLM_TCP=y
1030# CONFIG_DLM_SCTP is not set
1031# CONFIG_DLM_DEBUG is not set
1032
1033#
1034# Profiling support
1035#
1036# CONFIG_PROFILING is not set
1037
1038#
1039# Kernel hacking
1040#
1041CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1042# CONFIG_PRINTK_TIME is not set
1043CONFIG_ENABLE_MUST_CHECK=y
1044# CONFIG_MAGIC_SYSRQ is not set
1045# CONFIG_UNUSED_SYMBOLS is not set
1046# CONFIG_DEBUG_FS is not set
1047# CONFIG_HEADERS_CHECK is not set
1048# CONFIG_DEBUG_KERNEL is not set
1049CONFIG_LOG_BUF_SHIFT=14
1050CONFIG_CROSSCOMPILE=y
1051CONFIG_CMDLINE=""
1052
1053#
1054# Security options
1055#
1056CONFIG_KEYS=y
1057CONFIG_KEYS_DEBUG_PROC_KEYS=y
1058# CONFIG_SECURITY is not set
1059
1060#
1061# Cryptographic options
1062#
1063CONFIG_CRYPTO=y
1064CONFIG_CRYPTO_ALGAPI=y
1065CONFIG_CRYPTO_BLKCIPHER=m
1066CONFIG_CRYPTO_HASH=y
1067CONFIG_CRYPTO_MANAGER=y
1068CONFIG_CRYPTO_HMAC=y
1069CONFIG_CRYPTO_XCBC=m
1070CONFIG_CRYPTO_NULL=m
1071CONFIG_CRYPTO_MD4=m
1072CONFIG_CRYPTO_MD5=y
1073CONFIG_CRYPTO_SHA1=m
1074CONFIG_CRYPTO_SHA256=m
1075CONFIG_CRYPTO_SHA512=m
1076CONFIG_CRYPTO_WP512=m
1077CONFIG_CRYPTO_TGR192=m
1078CONFIG_CRYPTO_GF128MUL=m
1079CONFIG_CRYPTO_ECB=m
1080CONFIG_CRYPTO_CBC=m
1081CONFIG_CRYPTO_PCBC=m
1082CONFIG_CRYPTO_LRW=m
1083CONFIG_CRYPTO_DES=m
1084CONFIG_CRYPTO_FCRYPT=m
1085CONFIG_CRYPTO_BLOWFISH=m
1086CONFIG_CRYPTO_TWOFISH=m
1087CONFIG_CRYPTO_TWOFISH_COMMON=m
1088CONFIG_CRYPTO_SERPENT=m
1089CONFIG_CRYPTO_AES=m
1090CONFIG_CRYPTO_CAST5=m
1091CONFIG_CRYPTO_CAST6=m
1092CONFIG_CRYPTO_TEA=m
1093CONFIG_CRYPTO_ARC4=m
1094CONFIG_CRYPTO_KHAZAD=m
1095CONFIG_CRYPTO_ANUBIS=m
1096CONFIG_CRYPTO_DEFLATE=m
1097CONFIG_CRYPTO_MICHAEL_MIC=m
1098CONFIG_CRYPTO_CRC32C=m
1099CONFIG_CRYPTO_CAMELLIA=m
1100# CONFIG_CRYPTO_TEST is not set
1101
1102#
1103# Hardware crypto devices
1104#
1105
1106#
1107# Library routines
1108#
1109CONFIG_BITREVERSE=y
1110# CONFIG_CRC_CCITT is not set
1111CONFIG_CRC16=m
1112CONFIG_CRC32=y
1113CONFIG_LIBCRC32C=m
1114CONFIG_ZLIB_INFLATE=m
1115CONFIG_ZLIB_DEFLATE=m
1116CONFIG_PLIST=y
1117CONFIG_HAS_IOMEM=y
1118CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 1f64d7632a03..546cb243fd09 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32CONFIG_MIPS_MALTA=y 30CONFIG_MIPS_MALTA=y
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_MIPS_MALTA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index a2db5c201216..6abad6f88313 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35CONFIG_MIPS_SIM=y 33CONFIG_MIPS_SIM=y
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
@@ -496,36 +492,23 @@ CONFIG_NETDEVICES=y
496# CONFIG_BONDING is not set 492# CONFIG_BONDING is not set
497# CONFIG_EQUALIZER is not set 493# CONFIG_EQUALIZER is not set
498# CONFIG_TUN is not set 494# CONFIG_TUN is not set
499 495# CONFIG_PHYLIB is not set
500#
501# PHY device support
502#
503 496
504# 497#
505# Ethernet (10 or 100Mbit) 498# Ethernet (10 or 100Mbit)
506# 499#
507# CONFIG_NET_ETHERNET is not set 500CONFIG_NET_ETHERNET=y
508 501# CONFIG_MII is not set
509# 502CONFIG_MIPS_SIM_NET=y
510# Ethernet (1000 Mbit) 503# CONFIG_DM9000 is not set
511# 504# CONFIG_NETDEV_1000 is not set
512 505# CONFIG_NETDEV_10000 is not set
513#
514# Ethernet (10000 Mbit)
515#
516
517#
518# Token Ring devices
519#
520
521#
522# Wireless LAN (non-hamradio)
523#
524# CONFIG_NET_RADIO is not set
525 506
526# 507#
527# Wan interfaces 508# Wireless LAN
528# 509#
510# CONFIG_WLAN_PRE80211 is not set
511# CONFIG_WLAN_80211 is not set
529# CONFIG_WAN is not set 512# CONFIG_WAN is not set
530# CONFIG_PPP is not set 513# CONFIG_PPP is not set
531# CONFIG_SLIP is not set 514# CONFIG_SLIP is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index ad5c0bf87b2b..4981ce425d82 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/msp71xx_defconfig
index 28547313ce13..adca5f7ba533 100644
--- a/arch/mips/configs/ocelot_3_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20 3# Linux kernel version: 2.6.21-rc4
4# Tue Feb 20 21:47:35 2007 4# Thu Apr 26 18:11:29 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,14 +33,13 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38CONFIG_MOMENCO_OCELOT_3=y
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
43# CONFIG_PNX8550_STB810 is not set 39# CONFIG_PNX8550_STB810 is not set
44# CONFIG_DDB5477 is not set 40# CONFIG_DDB5477 is not set
45# CONFIG_MACH_VR41XX is not set 41# CONFIG_MACH_VR41XX is not set
42CONFIG_PMC_MSP=y
46# CONFIG_PMC_YOSEMITE is not set 43# CONFIG_PMC_YOSEMITE is not set
47# CONFIG_QEMU is not set 44# CONFIG_QEMU is not set
48# CONFIG_MARKEINS is not set 45# CONFIG_MARKEINS is not set
@@ -62,6 +59,16 @@ CONFIG_MOMENCO_OCELOT_3=y
62# CONFIG_TOSHIBA_JMR3927 is not set 59# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set 60# CONFIG_TOSHIBA_RBTX4927 is not set
64# CONFIG_TOSHIBA_RBTX4938 is not set 61# CONFIG_TOSHIBA_RBTX4938 is not set
62# CONFIG_PMC_MSP4200_EVAL is not set
63# CONFIG_PMC_MSP4200_GW is not set
64# CONFIG_PMC_MSP7120_EVAL is not set
65CONFIG_PMC_MSP7120_GW=y
66# CONFIG_PMC_MSP7120_FPGA is not set
67
68#
69# Options for PMC-Sierra MSP chipsets
70#
71CONFIG_PMC_MSP_EMBEDDED_ROOTFS=y
65CONFIG_RWSEM_GENERIC_SPINLOCK=y 72CONFIG_RWSEM_GENERIC_SPINLOCK=y
66# CONFIG_ARCH_HAS_ILOG2_U32 is not set 73# CONFIG_ARCH_HAS_ILOG2_U32 is not set
67# CONFIG_ARCH_HAS_ILOG2_U64 is not set 74# CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -71,24 +78,24 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
71CONFIG_GENERIC_TIME=y 78CONFIG_GENERIC_TIME=y
72CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 79CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
73# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set 80# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
81CONFIG_BOOT_RAW=y
74CONFIG_DMA_NONCOHERENT=y 82CONFIG_DMA_NONCOHERENT=y
75CONFIG_DMA_NEED_PCI_MAP_STATE=y 83CONFIG_DMA_NEED_PCI_MAP_STATE=y
84CONFIG_NO_EXCEPT_FILL=y
76CONFIG_CPU_BIG_ENDIAN=y 85CONFIG_CPU_BIG_ENDIAN=y
77# CONFIG_CPU_LITTLE_ENDIAN is not set 86# CONFIG_CPU_LITTLE_ENDIAN is not set
78CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 87CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
79CONFIG_IRQ_CPU=y 88CONFIG_IRQ_CPU=y
80CONFIG_IRQ_CPU_RM7K=y 89CONFIG_IRQ_MSP_CIC=y
81CONFIG_IRQ_MV64340=y 90CONFIG_MSP_USB=y
82CONFIG_PCI_MARVELL=y
83CONFIG_SWAP_IO_SPACE=y 91CONFIG_SWAP_IO_SPACE=y
84CONFIG_BOOT_ELF32=y
85CONFIG_MIPS_L1_CACHE_SHIFT=5 92CONFIG_MIPS_L1_CACHE_SHIFT=5
86 93
87# 94#
88# CPU selection 95# CPU selection
89# 96#
90# CONFIG_CPU_MIPS32_R1 is not set 97# CONFIG_CPU_MIPS32_R1 is not set
91# CONFIG_CPU_MIPS32_R2 is not set 98CONFIG_CPU_MIPS32_R2=y
92# CONFIG_CPU_MIPS64_R1 is not set 99# CONFIG_CPU_MIPS64_R1 is not set
93# CONFIG_CPU_MIPS64_R2 is not set 100# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set 101# CONFIG_CPU_R3000 is not set
@@ -104,14 +111,14 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
104# CONFIG_CPU_R8000 is not set 111# CONFIG_CPU_R8000 is not set
105# CONFIG_CPU_R10000 is not set 112# CONFIG_CPU_R10000 is not set
106# CONFIG_CPU_RM7000 is not set 113# CONFIG_CPU_RM7000 is not set
107CONFIG_CPU_RM9000=y 114# CONFIG_CPU_RM9000 is not set
108# CONFIG_CPU_SB1 is not set 115# CONFIG_CPU_SB1 is not set
109CONFIG_SYS_HAS_CPU_RM9000=y 116CONFIG_SYS_HAS_CPU_MIPS32_R1=y
110CONFIG_WEAK_ORDERING=y 117CONFIG_SYS_HAS_CPU_MIPS32_R2=y
118CONFIG_CPU_MIPS32=y
119CONFIG_CPU_MIPSR2=y
111CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 120CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
112CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
113CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 121CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
114CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
115 122
116# 123#
117# Kernel type 124# Kernel type
@@ -122,13 +129,12 @@ CONFIG_PAGE_SIZE_4KB=y
122# CONFIG_PAGE_SIZE_8KB is not set 129# CONFIG_PAGE_SIZE_8KB is not set
123# CONFIG_PAGE_SIZE_16KB is not set 130# CONFIG_PAGE_SIZE_16KB is not set
124# CONFIG_PAGE_SIZE_64KB is not set 131# CONFIG_PAGE_SIZE_64KB is not set
125CONFIG_BOARD_SCACHE=y
126CONFIG_RM7000_CPU_SCACHE=y
127CONFIG_CPU_HAS_PREFETCH=y 132CONFIG_CPU_HAS_PREFETCH=y
128CONFIG_MIPS_MT_DISABLED=y 133CONFIG_MIPS_MT_DISABLED=y
129# CONFIG_MIPS_MT_SMP is not set 134# CONFIG_MIPS_MT_SMP is not set
130# CONFIG_MIPS_MT_SMTC is not set 135# CONFIG_MIPS_MT_SMTC is not set
131# CONFIG_MIPS_VPE_LOADER is not set 136# CONFIG_MIPS_VPE_LOADER is not set
137CONFIG_SYS_SUPPORTS_MULTITHREADING=y
132# CONFIG_64BIT_PHYS_ADDR is not set 138# CONFIG_64BIT_PHYS_ADDR is not set
133CONFIG_CPU_HAS_LLSC=y 139CONFIG_CPU_HAS_LLSC=y
134CONFIG_CPU_HAS_SYNC=y 140CONFIG_CPU_HAS_SYNC=y
@@ -149,15 +155,16 @@ CONFIG_ZONE_DMA_FLAG=1
149# CONFIG_HZ_48 is not set 155# CONFIG_HZ_48 is not set
150# CONFIG_HZ_100 is not set 156# CONFIG_HZ_100 is not set
151# CONFIG_HZ_128 is not set 157# CONFIG_HZ_128 is not set
152# CONFIG_HZ_250 is not set 158CONFIG_HZ_250=y
153# CONFIG_HZ_256 is not set 159# CONFIG_HZ_256 is not set
154CONFIG_HZ_1000=y 160# CONFIG_HZ_1000 is not set
155# CONFIG_HZ_1024 is not set 161# CONFIG_HZ_1024 is not set
156CONFIG_SYS_SUPPORTS_ARBIT_HZ=y 162CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
157CONFIG_HZ=1000 163CONFIG_HZ=250
158CONFIG_PREEMPT_NONE=y 164# CONFIG_PREEMPT_NONE is not set
159# CONFIG_PREEMPT_VOLUNTARY is not set 165# CONFIG_PREEMPT_VOLUNTARY is not set
160# CONFIG_PREEMPT is not set 166CONFIG_PREEMPT=y
167# CONFIG_PREEMPT_BKL is not set
161# CONFIG_KEXEC is not set 168# CONFIG_KEXEC is not set
162CONFIG_LOCKDEP_SUPPORT=y 169CONFIG_LOCKDEP_SUPPORT=y
163CONFIG_STACKTRACE_SUPPORT=y 170CONFIG_STACKTRACE_SUPPORT=y
@@ -168,14 +175,15 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
168# 175#
169CONFIG_EXPERIMENTAL=y 176CONFIG_EXPERIMENTAL=y
170CONFIG_BROKEN_ON_SMP=y 177CONFIG_BROKEN_ON_SMP=y
178CONFIG_LOCK_KERNEL=y
171CONFIG_INIT_ENV_ARG_LIMIT=32 179CONFIG_INIT_ENV_ARG_LIMIT=32
172 180
173# 181#
174# General setup 182# General setup
175# 183#
176CONFIG_LOCALVERSION="" 184CONFIG_LOCALVERSION="-pmc"
177CONFIG_LOCALVERSION_AUTO=y 185CONFIG_LOCALVERSION_AUTO=y
178CONFIG_SWAP=y 186# CONFIG_SWAP is not set
179CONFIG_SYSVIPC=y 187CONFIG_SYSVIPC=y
180# CONFIG_IPC_NS is not set 188# CONFIG_IPC_NS is not set
181CONFIG_SYSVIPC_SYSCTL=y 189CONFIG_SYSVIPC_SYSCTL=y
@@ -184,15 +192,16 @@ CONFIG_SYSVIPC_SYSCTL=y
184# CONFIG_TASKSTATS is not set 192# CONFIG_TASKSTATS is not set
185# CONFIG_UTS_NS is not set 193# CONFIG_UTS_NS is not set
186# CONFIG_AUDIT is not set 194# CONFIG_AUDIT is not set
187CONFIG_IKCONFIG=y 195# CONFIG_IKCONFIG is not set
188CONFIG_IKCONFIG_PROC=y
189CONFIG_SYSFS_DEPRECATED=y 196CONFIG_SYSFS_DEPRECATED=y
190CONFIG_RELAY=y 197# CONFIG_RELAY is not set
198# CONFIG_BLK_DEV_INITRD is not set
191# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 199# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
192CONFIG_SYSCTL=y 200CONFIG_SYSCTL=y
193CONFIG_EMBEDDED=y 201CONFIG_EMBEDDED=y
194CONFIG_SYSCTL_SYSCALL=y 202CONFIG_SYSCTL_SYSCALL=y
195CONFIG_KALLSYMS=y 203CONFIG_KALLSYMS=y
204# CONFIG_KALLSYMS_ALL is not set
196# CONFIG_KALLSYMS_EXTRA_PASS is not set 205# CONFIG_KALLSYMS_EXTRA_PASS is not set
197CONFIG_HOTPLUG=y 206CONFIG_HOTPLUG=y
198CONFIG_PRINTK=y 207CONFIG_PRINTK=y
@@ -201,11 +210,11 @@ CONFIG_ELF_CORE=y
201CONFIG_BASE_FULL=y 210CONFIG_BASE_FULL=y
202CONFIG_FUTEX=y 211CONFIG_FUTEX=y
203CONFIG_EPOLL=y 212CONFIG_EPOLL=y
204CONFIG_SHMEM=y 213# CONFIG_SHMEM is not set
205CONFIG_SLAB=y 214CONFIG_SLAB=y
206CONFIG_VM_EVENT_COUNTERS=y 215CONFIG_VM_EVENT_COUNTERS=y
207CONFIG_RT_MUTEXES=y 216CONFIG_RT_MUTEXES=y
208# CONFIG_TINY_SHMEM is not set 217CONFIG_TINY_SHMEM=y
209CONFIG_BASE_SMALL=0 218CONFIG_BASE_SMALL=0
210# CONFIG_SLOB is not set 219# CONFIG_SLOB is not set
211 220
@@ -232,8 +241,8 @@ CONFIG_BLOCK=y
232# 241#
233CONFIG_IOSCHED_NOOP=y 242CONFIG_IOSCHED_NOOP=y
234CONFIG_IOSCHED_AS=y 243CONFIG_IOSCHED_AS=y
235CONFIG_IOSCHED_DEADLINE=y 244# CONFIG_IOSCHED_DEADLINE is not set
236CONFIG_IOSCHED_CFQ=y 245# CONFIG_IOSCHED_CFQ is not set
237CONFIG_DEFAULT_AS=y 246CONFIG_DEFAULT_AS=y
238# CONFIG_DEFAULT_DEADLINE is not set 247# CONFIG_DEFAULT_DEADLINE is not set
239# CONFIG_DEFAULT_CFQ is not set 248# CONFIG_DEFAULT_CFQ is not set
@@ -245,6 +254,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
245# 254#
246CONFIG_HW_HAS_PCI=y 255CONFIG_HW_HAS_PCI=y
247CONFIG_PCI=y 256CONFIG_PCI=y
257# CONFIG_PCI_DEBUG is not set
248CONFIG_MMU=y 258CONFIG_MMU=y
249 259
250# 260#
@@ -267,10 +277,7 @@ CONFIG_TRAD_SIGNALS=y
267# 277#
268# Power management options 278# Power management options
269# 279#
270CONFIG_PM=y 280# CONFIG_PM is not set
271# CONFIG_PM_LEGACY is not set
272# CONFIG_PM_DEBUG is not set
273# CONFIG_PM_SYSFS_DEPRECATED is not set
274 281
275# 282#
276# Networking 283# Networking
@@ -281,17 +288,16 @@ CONFIG_NET=y
281# Networking options 288# Networking options
282# 289#
283# CONFIG_NETDEBUG is not set 290# CONFIG_NETDEBUG is not set
284CONFIG_PACKET=y 291# CONFIG_PACKET is not set
285# CONFIG_PACKET_MMAP is not set
286CONFIG_UNIX=y 292CONFIG_UNIX=y
287CONFIG_XFRM=y 293CONFIG_XFRM=y
288# CONFIG_XFRM_USER is not set 294CONFIG_XFRM_USER=y
289# CONFIG_XFRM_SUB_POLICY is not set 295# CONFIG_XFRM_SUB_POLICY is not set
290CONFIG_XFRM_MIGRATE=y 296# CONFIG_XFRM_MIGRATE is not set
291CONFIG_NET_KEY=y 297CONFIG_NET_KEY=y
292CONFIG_NET_KEY_MIGRATE=y 298# CONFIG_NET_KEY_MIGRATE is not set
293CONFIG_INET=y 299CONFIG_INET=y
294# CONFIG_IP_MULTICAST is not set 300CONFIG_IP_MULTICAST=y
295# CONFIG_IP_ADVANCED_ROUTER is not set 301# CONFIG_IP_ADVANCED_ROUTER is not set
296CONFIG_IP_FIB_HASH=y 302CONFIG_IP_FIB_HASH=y
297CONFIG_IP_PNP=y 303CONFIG_IP_PNP=y
@@ -300,122 +306,92 @@ CONFIG_IP_PNP_BOOTP=y
300# CONFIG_IP_PNP_RARP is not set 306# CONFIG_IP_PNP_RARP is not set
301# CONFIG_NET_IPIP is not set 307# CONFIG_NET_IPIP is not set
302# CONFIG_NET_IPGRE is not set 308# CONFIG_NET_IPGRE is not set
309# CONFIG_IP_MROUTE is not set
303# CONFIG_ARPD is not set 310# CONFIG_ARPD is not set
304# CONFIG_SYN_COOKIES is not set 311# CONFIG_SYN_COOKIES is not set
305# CONFIG_INET_AH is not set 312CONFIG_INET_AH=y
306# CONFIG_INET_ESP is not set 313CONFIG_INET_ESP=y
307# CONFIG_INET_IPCOMP is not set 314CONFIG_INET_IPCOMP=y
308# CONFIG_INET_XFRM_TUNNEL is not set 315CONFIG_INET_XFRM_TUNNEL=y
309CONFIG_INET_TUNNEL=m 316CONFIG_INET_TUNNEL=y
310CONFIG_INET_XFRM_MODE_TRANSPORT=m 317CONFIG_INET_XFRM_MODE_TRANSPORT=y
311CONFIG_INET_XFRM_MODE_TUNNEL=m 318CONFIG_INET_XFRM_MODE_TUNNEL=y
312CONFIG_INET_XFRM_MODE_BEET=m 319CONFIG_INET_XFRM_MODE_BEET=y
313CONFIG_INET_DIAG=y 320CONFIG_INET_DIAG=y
314CONFIG_INET_TCP_DIAG=y 321CONFIG_INET_TCP_DIAG=y
315# CONFIG_TCP_CONG_ADVANCED is not set 322# CONFIG_TCP_CONG_ADVANCED is not set
316CONFIG_TCP_CONG_CUBIC=y 323CONFIG_TCP_CONG_CUBIC=y
317CONFIG_DEFAULT_TCP_CONG="cubic" 324CONFIG_DEFAULT_TCP_CONG="cubic"
318CONFIG_TCP_MD5SIG=y 325# CONFIG_TCP_MD5SIG is not set
319 326
320# 327#
321# IP: Virtual Server Configuration 328# IP: Virtual Server Configuration
322# 329#
323# CONFIG_IP_VS is not set 330# CONFIG_IP_VS is not set
324CONFIG_IPV6=m 331# CONFIG_IPV6 is not set
325# CONFIG_IPV6_PRIVACY is not set
326CONFIG_IPV6_ROUTER_PREF=y
327CONFIG_IPV6_ROUTE_INFO=y
328# CONFIG_INET6_AH is not set
329# CONFIG_INET6_ESP is not set
330# CONFIG_INET6_IPCOMP is not set
331CONFIG_IPV6_MIP6=y
332# CONFIG_INET6_XFRM_TUNNEL is not set 332# CONFIG_INET6_XFRM_TUNNEL is not set
333# CONFIG_INET6_TUNNEL is not set 333# CONFIG_INET6_TUNNEL is not set
334CONFIG_INET6_XFRM_MODE_TRANSPORT=m 334# CONFIG_NETWORK_SECMARK is not set
335CONFIG_INET6_XFRM_MODE_TUNNEL=m
336CONFIG_INET6_XFRM_MODE_BEET=m
337CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
338CONFIG_IPV6_SIT=m
339# CONFIG_IPV6_TUNNEL is not set
340CONFIG_IPV6_MULTIPLE_TABLES=y
341CONFIG_IPV6_SUBTREES=y
342CONFIG_NETWORK_SECMARK=y
343CONFIG_NETFILTER=y 335CONFIG_NETFILTER=y
344# CONFIG_NETFILTER_DEBUG is not set 336# CONFIG_NETFILTER_DEBUG is not set
337CONFIG_BRIDGE_NETFILTER=y
345 338
346# 339#
347# Core Netfilter Configuration 340# Core Netfilter Configuration
348# 341#
349CONFIG_NETFILTER_NETLINK=m 342# CONFIG_NETFILTER_NETLINK is not set
350CONFIG_NETFILTER_NETLINK_QUEUE=m 343# CONFIG_NF_CONNTRACK_ENABLED is not set
351CONFIG_NETFILTER_NETLINK_LOG=m 344CONFIG_NETFILTER_XTABLES=y
352CONFIG_NF_CONNTRACK_ENABLED=m 345# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
353CONFIG_NF_CONNTRACK_SUPPORT=y 346# CONFIG_NETFILTER_XT_TARGET_MARK is not set
354# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set 347# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
355CONFIG_NF_CONNTRACK=m 348# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
356CONFIG_NF_CT_ACCT=y 349# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
357CONFIG_NF_CONNTRACK_MARK=y 350# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
358CONFIG_NF_CONNTRACK_SECMARK=y 351# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
359CONFIG_NF_CONNTRACK_EVENTS=y 352# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
360CONFIG_NF_CT_PROTO_GRE=m 353# CONFIG_NETFILTER_XT_MATCH_ESP is not set
361CONFIG_NF_CT_PROTO_SCTP=m 354# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
362CONFIG_NF_CONNTRACK_AMANDA=m 355# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
363CONFIG_NF_CONNTRACK_FTP=m 356# CONFIG_NETFILTER_XT_MATCH_MAC is not set
364CONFIG_NF_CONNTRACK_H323=m 357# CONFIG_NETFILTER_XT_MATCH_MARK is not set
365CONFIG_NF_CONNTRACK_IRC=m 358# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
366# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set 359# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
367CONFIG_NF_CONNTRACK_PPTP=m 360# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
368CONFIG_NF_CONNTRACK_SANE=m 361# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
369CONFIG_NF_CONNTRACK_SIP=m 362# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
370CONFIG_NF_CONNTRACK_TFTP=m 363# CONFIG_NETFILTER_XT_MATCH_REALM is not set
371CONFIG_NF_CT_NETLINK=m 364# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
372CONFIG_NETFILTER_XTABLES=m 365# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
373CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m 366# CONFIG_NETFILTER_XT_MATCH_STRING is not set
374CONFIG_NETFILTER_XT_TARGET_MARK=m 367# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
375CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 368# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
376CONFIG_NETFILTER_XT_TARGET_NFLOG=m
377CONFIG_NETFILTER_XT_TARGET_SECMARK=m
378CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
379CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
380CONFIG_NETFILTER_XT_MATCH_COMMENT=m
381CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
382CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
383CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
384CONFIG_NETFILTER_XT_MATCH_DCCP=m
385CONFIG_NETFILTER_XT_MATCH_DSCP=m
386CONFIG_NETFILTER_XT_MATCH_ESP=m
387CONFIG_NETFILTER_XT_MATCH_HELPER=m
388CONFIG_NETFILTER_XT_MATCH_LENGTH=m
389CONFIG_NETFILTER_XT_MATCH_LIMIT=m
390CONFIG_NETFILTER_XT_MATCH_MAC=m
391CONFIG_NETFILTER_XT_MATCH_MARK=m
392CONFIG_NETFILTER_XT_MATCH_POLICY=m
393CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
394CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
395CONFIG_NETFILTER_XT_MATCH_QUOTA=m
396CONFIG_NETFILTER_XT_MATCH_REALM=m
397CONFIG_NETFILTER_XT_MATCH_SCTP=m
398CONFIG_NETFILTER_XT_MATCH_STATE=m
399CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
400CONFIG_NETFILTER_XT_MATCH_STRING=m
401CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
402CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
403 369
404# 370#
405# IP: Netfilter Configuration 371# IP: Netfilter Configuration
406# 372#
407CONFIG_NF_CONNTRACK_IPV4=m
408CONFIG_NF_CONNTRACK_PROC_COMPAT=y
409# CONFIG_IP_NF_QUEUE is not set 373# CONFIG_IP_NF_QUEUE is not set
410# CONFIG_IP_NF_IPTABLES is not set 374CONFIG_IP_NF_IPTABLES=y
375# CONFIG_IP_NF_MATCH_IPRANGE is not set
376# CONFIG_IP_NF_MATCH_TOS is not set
377# CONFIG_IP_NF_MATCH_RECENT is not set
378# CONFIG_IP_NF_MATCH_ECN is not set
379# CONFIG_IP_NF_MATCH_AH is not set
380# CONFIG_IP_NF_MATCH_TTL is not set
381# CONFIG_IP_NF_MATCH_OWNER is not set
382# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
383CONFIG_IP_NF_FILTER=y
384CONFIG_IP_NF_TARGET_REJECT=y
385# CONFIG_IP_NF_TARGET_LOG is not set
386# CONFIG_IP_NF_TARGET_ULOG is not set
387# CONFIG_IP_NF_MANGLE is not set
388# CONFIG_IP_NF_RAW is not set
411# CONFIG_IP_NF_ARPTABLES is not set 389# CONFIG_IP_NF_ARPTABLES is not set
412 390
413# 391#
414# IPv6: Netfilter Configuration (EXPERIMENTAL) 392# Bridge: Netfilter Configuration
415# 393#
416CONFIG_NF_CONNTRACK_IPV6=m 394# CONFIG_BRIDGE_NF_EBTABLES is not set
417# CONFIG_IP6_NF_QUEUE is not set
418# CONFIG_IP6_NF_IPTABLES is not set
419 395
420# 396#
421# DCCP Configuration (EXPERIMENTAL) 397# DCCP Configuration (EXPERIMENTAL)
@@ -432,9 +408,10 @@ CONFIG_NF_CONNTRACK_IPV6=m
432# 408#
433# CONFIG_TIPC is not set 409# CONFIG_TIPC is not set
434# CONFIG_ATM is not set 410# CONFIG_ATM is not set
435# CONFIG_BRIDGE is not set 411CONFIG_BRIDGE=y
436# CONFIG_VLAN_8021Q is not set 412# CONFIG_VLAN_8021Q is not set
437# CONFIG_DECNET is not set 413# CONFIG_DECNET is not set
414CONFIG_LLC=y
438# CONFIG_LLC2 is not set 415# CONFIG_LLC2 is not set
439# CONFIG_IPX is not set 416# CONFIG_IPX is not set
440# CONFIG_ATALK is not set 417# CONFIG_ATALK is not set
@@ -447,7 +424,6 @@ CONFIG_NF_CONNTRACK_IPV6=m
447# QoS and/or fair queueing 424# QoS and/or fair queueing
448# 425#
449# CONFIG_NET_SCHED is not set 426# CONFIG_NET_SCHED is not set
450CONFIG_NET_CLS_ROUTE=y
451 427
452# 428#
453# Network testing 429# Network testing
@@ -456,14 +432,8 @@ CONFIG_NET_CLS_ROUTE=y
456# CONFIG_HAMRADIO is not set 432# CONFIG_HAMRADIO is not set
457# CONFIG_IRDA is not set 433# CONFIG_IRDA is not set
458# CONFIG_BT is not set 434# CONFIG_BT is not set
459CONFIG_IEEE80211=m 435# CONFIG_IEEE80211 is not set
460# CONFIG_IEEE80211_DEBUG is not set
461CONFIG_IEEE80211_CRYPT_WEP=m
462CONFIG_IEEE80211_CRYPT_CCMP=m
463CONFIG_IEEE80211_SOFTMAC=m
464# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
465CONFIG_WIRELESS_EXT=y 436CONFIG_WIRELESS_EXT=y
466CONFIG_FIB_RULES=y
467 437
468# 438#
469# Device Drivers 439# Device Drivers
@@ -473,19 +443,101 @@ CONFIG_FIB_RULES=y
473# Generic Driver Options 443# Generic Driver Options
474# 444#
475CONFIG_STANDALONE=y 445CONFIG_STANDALONE=y
476CONFIG_PREVENT_FIRMWARE_BUILD=y 446# CONFIG_PREVENT_FIRMWARE_BUILD is not set
477CONFIG_FW_LOADER=m 447# CONFIG_FW_LOADER is not set
448# CONFIG_DEBUG_DRIVER is not set
449# CONFIG_DEBUG_DEVRES is not set
478# CONFIG_SYS_HYPERVISOR is not set 450# CONFIG_SYS_HYPERVISOR is not set
479 451
480# 452#
481# Connector - unified userspace <-> kernelspace linker 453# Connector - unified userspace <-> kernelspace linker
482# 454#
483CONFIG_CONNECTOR=m 455# CONFIG_CONNECTOR is not set
484 456
485# 457#
486# Memory Technology Devices (MTD) 458# Memory Technology Devices (MTD)
487# 459#
488# CONFIG_MTD is not set 460CONFIG_MTD=y
461# CONFIG_MTD_DEBUG is not set
462# CONFIG_MTD_CONCAT is not set
463CONFIG_MTD_PARTITIONS=y
464# CONFIG_MTD_REDBOOT_PARTS is not set
465# CONFIG_MTD_CMDLINE_PARTS is not set
466
467#
468# User Modules And Translation Layers
469#
470CONFIG_MTD_CHAR=y
471CONFIG_MTD_BLKDEVS=y
472CONFIG_MTD_BLOCK=y
473# CONFIG_FTL is not set
474# CONFIG_NFTL is not set
475# CONFIG_INFTL is not set
476# CONFIG_RFD_FTL is not set
477# CONFIG_SSFDC is not set
478
479#
480# RAM/ROM/Flash chip drivers
481#
482CONFIG_MTD_CFI=y
483# CONFIG_MTD_JEDECPROBE is not set
484CONFIG_MTD_GEN_PROBE=y
485# CONFIG_MTD_CFI_ADV_OPTIONS is not set
486CONFIG_MTD_MAP_BANK_WIDTH_1=y
487CONFIG_MTD_MAP_BANK_WIDTH_2=y
488CONFIG_MTD_MAP_BANK_WIDTH_4=y
489# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
490# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
491# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
492CONFIG_MTD_CFI_I1=y
493CONFIG_MTD_CFI_I2=y
494# CONFIG_MTD_CFI_I4 is not set
495# CONFIG_MTD_CFI_I8 is not set
496# CONFIG_MTD_CFI_INTELEXT is not set
497CONFIG_MTD_CFI_AMDSTD=y
498# CONFIG_MTD_CFI_STAA is not set
499CONFIG_MTD_CFI_UTIL=y
500CONFIG_MTD_RAM=y
501# CONFIG_MTD_ROM is not set
502# CONFIG_MTD_ABSENT is not set
503# CONFIG_MTD_OBSOLETE_CHIPS is not set
504
505#
506# Mapping drivers for chip access
507#
508# CONFIG_MTD_COMPLEX_MAPPINGS is not set
509# CONFIG_MTD_PHYSMAP is not set
510CONFIG_MTD_PMC_MSP_EVM=y
511CONFIG_MSP_FLASH_MAP_LIMIT_32M=y
512CONFIG_MSP_FLASH_MAP_LIMIT=0x02000000
513CONFIG_MTD_PMC_MSP_RAMROOT=y
514# CONFIG_MTD_PLATRAM is not set
515
516#
517# Self-contained MTD device drivers
518#
519# CONFIG_MTD_PMC551 is not set
520# CONFIG_MTD_SLRAM is not set
521# CONFIG_MTD_PHRAM is not set
522# CONFIG_MTD_MTDRAM is not set
523# CONFIG_MTD_BLOCK2MTD is not set
524
525#
526# Disk-On-Chip Device Drivers
527#
528# CONFIG_MTD_DOC2000 is not set
529# CONFIG_MTD_DOC2001 is not set
530# CONFIG_MTD_DOC2001PLUS is not set
531
532#
533# NAND Flash Device Drivers
534#
535# CONFIG_MTD_NAND is not set
536
537#
538# OneNAND Flash Device Drivers
539#
540# CONFIG_MTD_ONENAND is not set
489 541
490# 542#
491# Parallel port support 543# Parallel port support
@@ -505,19 +557,21 @@ CONFIG_CONNECTOR=m
505# CONFIG_BLK_DEV_DAC960 is not set 557# CONFIG_BLK_DEV_DAC960 is not set
506# CONFIG_BLK_DEV_UMEM is not set 558# CONFIG_BLK_DEV_UMEM is not set
507# CONFIG_BLK_DEV_COW_COMMON is not set 559# CONFIG_BLK_DEV_COW_COMMON is not set
508CONFIG_BLK_DEV_LOOP=y 560# CONFIG_BLK_DEV_LOOP is not set
509# CONFIG_BLK_DEV_CRYPTOLOOP is not set
510# CONFIG_BLK_DEV_NBD is not set 561# CONFIG_BLK_DEV_NBD is not set
511# CONFIG_BLK_DEV_SX8 is not set 562# CONFIG_BLK_DEV_SX8 is not set
512# CONFIG_BLK_DEV_RAM is not set 563# CONFIG_BLK_DEV_UB is not set
513# CONFIG_BLK_DEV_INITRD is not set 564CONFIG_BLK_DEV_RAM=y
565CONFIG_BLK_DEV_RAM_COUNT=16
566CONFIG_BLK_DEV_RAM_SIZE=4096
567CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
514# CONFIG_CDROM_PKTCDVD is not set 568# CONFIG_CDROM_PKTCDVD is not set
515CONFIG_ATA_OVER_ETH=m 569# CONFIG_ATA_OVER_ETH is not set
516 570
517# 571#
518# Misc devices 572# Misc devices
519# 573#
520CONFIG_SGI_IOC4=m 574# CONFIG_SGI_IOC4 is not set
521# CONFIG_TIFM_CORE is not set 575# CONFIG_TIFM_CORE is not set
522 576
523# 577#
@@ -528,16 +582,16 @@ CONFIG_SGI_IOC4=m
528# 582#
529# SCSI device support 583# SCSI device support
530# 584#
531CONFIG_RAID_ATTRS=m 585# CONFIG_RAID_ATTRS is not set
532CONFIG_SCSI=m 586CONFIG_SCSI=y
533CONFIG_SCSI_TGT=m 587# CONFIG_SCSI_TGT is not set
534CONFIG_SCSI_NETLINK=y 588# CONFIG_SCSI_NETLINK is not set
535CONFIG_SCSI_PROC_FS=y 589CONFIG_SCSI_PROC_FS=y
536 590
537# 591#
538# SCSI support type (disk, tape, CD-ROM) 592# SCSI support type (disk, tape, CD-ROM)
539# 593#
540# CONFIG_BLK_DEV_SD is not set 594CONFIG_BLK_DEV_SD=y
541# CONFIG_CHR_DEV_ST is not set 595# CONFIG_CHR_DEV_ST is not set
542# CONFIG_CHR_DEV_OSST is not set 596# CONFIG_CHR_DEV_OSST is not set
543# CONFIG_BLK_DEV_SR is not set 597# CONFIG_BLK_DEV_SR is not set
@@ -550,22 +604,21 @@ CONFIG_SCSI_PROC_FS=y
550# CONFIG_SCSI_MULTI_LUN is not set 604# CONFIG_SCSI_MULTI_LUN is not set
551# CONFIG_SCSI_CONSTANTS is not set 605# CONFIG_SCSI_CONSTANTS is not set
552# CONFIG_SCSI_LOGGING is not set 606# CONFIG_SCSI_LOGGING is not set
553CONFIG_SCSI_SCAN_ASYNC=y 607# CONFIG_SCSI_SCAN_ASYNC is not set
554 608
555# 609#
556# SCSI Transports 610# SCSI Transports
557# 611#
558# CONFIG_SCSI_SPI_ATTRS is not set 612# CONFIG_SCSI_SPI_ATTRS is not set
559CONFIG_SCSI_FC_ATTRS=m 613# CONFIG_SCSI_FC_ATTRS is not set
560CONFIG_SCSI_ISCSI_ATTRS=m 614# CONFIG_SCSI_ISCSI_ATTRS is not set
561CONFIG_SCSI_SAS_ATTRS=m 615# CONFIG_SCSI_SAS_ATTRS is not set
562CONFIG_SCSI_SAS_LIBSAS=m 616# CONFIG_SCSI_SAS_LIBSAS is not set
563# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
564 617
565# 618#
566# SCSI low-level drivers 619# SCSI low-level drivers
567# 620#
568CONFIG_ISCSI_TCP=m 621# CONFIG_ISCSI_TCP is not set
569# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 622# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
570# CONFIG_SCSI_3W_9XXX is not set 623# CONFIG_SCSI_3W_9XXX is not set
571# CONFIG_SCSI_ACARD is not set 624# CONFIG_SCSI_ACARD is not set
@@ -573,8 +626,7 @@ CONFIG_ISCSI_TCP=m
573# CONFIG_SCSI_AIC7XXX is not set 626# CONFIG_SCSI_AIC7XXX is not set
574# CONFIG_SCSI_AIC7XXX_OLD is not set 627# CONFIG_SCSI_AIC7XXX_OLD is not set
575# CONFIG_SCSI_AIC79XX is not set 628# CONFIG_SCSI_AIC79XX is not set
576CONFIG_SCSI_AIC94XX=m 629# CONFIG_SCSI_AIC94XX is not set
577# CONFIG_AIC94XX_DEBUG is not set
578# CONFIG_SCSI_DPT_I2O is not set 630# CONFIG_SCSI_DPT_I2O is not set
579# CONFIG_SCSI_ARCMSR is not set 631# CONFIG_SCSI_ARCMSR is not set
580# CONFIG_MEGARAID_NEWGEN is not set 632# CONFIG_MEGARAID_NEWGEN is not set
@@ -630,10 +682,10 @@ CONFIG_SCSI_AIC94XX=m
630# Network device support 682# Network device support
631# 683#
632CONFIG_NETDEVICES=y 684CONFIG_NETDEVICES=y
633# CONFIG_DUMMY is not set 685CONFIG_DUMMY=y
634# CONFIG_BONDING is not set 686# CONFIG_BONDING is not set
635# CONFIG_EQUALIZER is not set 687# CONFIG_EQUALIZER is not set
636CONFIG_TUN=m 688# CONFIG_TUN is not set
637 689
638# 690#
639# ARCnet devices 691# ARCnet devices
@@ -643,26 +695,16 @@ CONFIG_TUN=m
643# 695#
644# PHY device support 696# PHY device support
645# 697#
646CONFIG_PHYLIB=m 698# CONFIG_PHYLIB is not set
647
648#
649# MII PHY device drivers
650#
651CONFIG_MARVELL_PHY=m
652CONFIG_DAVICOM_PHY=m
653CONFIG_QSEMI_PHY=m
654CONFIG_LXT_PHY=m
655CONFIG_CICADA_PHY=m
656CONFIG_VITESSE_PHY=m
657CONFIG_SMSC_PHY=m
658# CONFIG_BROADCOM_PHY is not set
659# CONFIG_FIXED_PHY is not set
660 699
661# 700#
662# Ethernet (10 or 100Mbit) 701# Ethernet (10 or 100Mbit)
663# 702#
664CONFIG_NET_ETHERNET=y 703CONFIG_NET_ETHERNET=y
665CONFIG_MII=y 704CONFIG_MII=y
705CONFIG_MSPETH=y
706CONFIG_MSPETH_NAPI=y
707# CONFIG_MSPETH_SKB_RECYCLE is not set
666# CONFIG_HAPPYMEAL is not set 708# CONFIG_HAPPYMEAL is not set
667# CONFIG_SUNGEM is not set 709# CONFIG_SUNGEM is not set
668# CONFIG_CASSINI is not set 710# CONFIG_CASSINI is not set
@@ -674,26 +716,7 @@ CONFIG_MII=y
674# 716#
675# CONFIG_NET_TULIP is not set 717# CONFIG_NET_TULIP is not set
676# CONFIG_HP100 is not set 718# CONFIG_HP100 is not set
677CONFIG_NET_PCI=y 719# CONFIG_NET_PCI is not set
678# CONFIG_PCNET32 is not set
679# CONFIG_AMD8111_ETH is not set
680# CONFIG_ADAPTEC_STARFIRE is not set
681# CONFIG_B44 is not set
682# CONFIG_FORCEDETH is not set
683# CONFIG_DGRS is not set
684# CONFIG_EEPRO100 is not set
685CONFIG_E100=y
686# CONFIG_FEALNX is not set
687# CONFIG_NATSEMI is not set
688# CONFIG_NE2K_PCI is not set
689# CONFIG_8139CP is not set
690# CONFIG_8139TOO is not set
691# CONFIG_SIS900 is not set
692# CONFIG_EPIC100 is not set
693# CONFIG_SUNDANCE is not set
694# CONFIG_TLAN is not set
695# CONFIG_VIA_RHINE is not set
696# CONFIG_SC92031 is not set
697 720
698# 721#
699# Ethernet (1000 Mbit) 722# Ethernet (1000 Mbit)
@@ -709,22 +732,20 @@ CONFIG_E100=y
709# CONFIG_SKGE is not set 732# CONFIG_SKGE is not set
710# CONFIG_SKY2 is not set 733# CONFIG_SKY2 is not set
711# CONFIG_SK98LIN is not set 734# CONFIG_SK98LIN is not set
712# CONFIG_VIA_VELOCITY is not set
713# CONFIG_TIGON3 is not set 735# CONFIG_TIGON3 is not set
714# CONFIG_BNX2 is not set 736# CONFIG_BNX2 is not set
715CONFIG_MV643XX_ETH=y 737# CONFIG_QLA3XXX is not set
716CONFIG_QLA3XXX=m
717# CONFIG_ATL1 is not set 738# CONFIG_ATL1 is not set
718 739
719# 740#
720# Ethernet (10000 Mbit) 741# Ethernet (10000 Mbit)
721# 742#
722# CONFIG_CHELSIO_T1 is not set 743# CONFIG_CHELSIO_T1 is not set
723CONFIG_CHELSIO_T3=m 744# CONFIG_CHELSIO_T3 is not set
724# CONFIG_IXGB is not set 745# CONFIG_IXGB is not set
725# CONFIG_S2IO is not set 746# CONFIG_S2IO is not set
726# CONFIG_MYRI10GE is not set 747# CONFIG_MYRI10GE is not set
727CONFIG_NETXEN_NIC=m 748# CONFIG_NETXEN_NIC is not set
728 749
729# 750#
730# Token Ring devices 751# Token Ring devices
@@ -734,7 +755,29 @@ CONFIG_NETXEN_NIC=m
734# 755#
735# Wireless LAN (non-hamradio) 756# Wireless LAN (non-hamradio)
736# 757#
737# CONFIG_NET_RADIO is not set 758CONFIG_NET_RADIO=y
759# CONFIG_NET_WIRELESS_RTNETLINK is not set
760
761#
762# Obsolete Wireless cards support (pre-802.11)
763#
764# CONFIG_STRIP is not set
765
766#
767# Wireless 802.11b ISA/PCI cards support
768#
769# CONFIG_IPW2100 is not set
770# CONFIG_IPW2200 is not set
771# CONFIG_HERMES is not set
772# CONFIG_ATMEL is not set
773
774#
775# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
776#
777# CONFIG_PRISM54 is not set
778# CONFIG_USB_ZD1201 is not set
779# CONFIG_HOSTAP is not set
780CONFIG_NET_WIRELESS=y
738 781
739# 782#
740# Wan interfaces 783# Wan interfaces
@@ -742,17 +785,17 @@ CONFIG_NETXEN_NIC=m
742# CONFIG_WAN is not set 785# CONFIG_WAN is not set
743# CONFIG_FDDI is not set 786# CONFIG_FDDI is not set
744# CONFIG_HIPPI is not set 787# CONFIG_HIPPI is not set
745CONFIG_PPP=m 788CONFIG_PPP=y
746# CONFIG_PPP_MULTILINK is not set 789# CONFIG_PPP_MULTILINK is not set
747# CONFIG_PPP_FILTER is not set 790# CONFIG_PPP_FILTER is not set
748CONFIG_PPP_ASYNC=m 791# CONFIG_PPP_ASYNC is not set
749CONFIG_PPP_SYNC_TTY=m 792# CONFIG_PPP_SYNC_TTY is not set
750CONFIG_PPP_DEFLATE=m 793# CONFIG_PPP_DEFLATE is not set
751# CONFIG_PPP_BSDCOMP is not set 794# CONFIG_PPP_BSDCOMP is not set
752CONFIG_PPP_MPPE=m 795# CONFIG_PPP_MPPE is not set
753CONFIG_PPPOE=m 796# CONFIG_PPPOE is not set
754# CONFIG_SLIP is not set 797# CONFIG_SLIP is not set
755CONFIG_SLHC=m 798CONFIG_SLHC=y
756# CONFIG_NET_FC is not set 799# CONFIG_NET_FC is not set
757# CONFIG_SHAPER is not set 800# CONFIG_SHAPER is not set
758# CONFIG_NETCONSOLE is not set 801# CONFIG_NETCONSOLE is not set
@@ -796,31 +839,24 @@ CONFIG_INPUT=y
796# 839#
797# Hardware I/O ports 840# Hardware I/O ports
798# 841#
799CONFIG_SERIO=y 842# CONFIG_SERIO is not set
800# CONFIG_SERIO_I8042 is not set
801# CONFIG_SERIO_SERPORT is not set
802# CONFIG_SERIO_PCIPS2 is not set
803# CONFIG_SERIO_LIBPS2 is not set
804# CONFIG_SERIO_RAW is not set
805# CONFIG_GAMEPORT is not set 843# CONFIG_GAMEPORT is not set
806 844
807# 845#
808# Character devices 846# Character devices
809# 847#
810CONFIG_VT=y 848# CONFIG_VT is not set
811CONFIG_VT_CONSOLE=y
812CONFIG_HW_CONSOLE=y
813CONFIG_VT_HW_CONSOLE_BINDING=y
814# CONFIG_SERIAL_NONSTANDARD is not set 849# CONFIG_SERIAL_NONSTANDARD is not set
850CONFIG_PMCMSP_GPIO=y
815 851
816# 852#
817# Serial drivers 853# Serial drivers
818# 854#
819CONFIG_SERIAL_8250=y 855CONFIG_SERIAL_8250=y
820CONFIG_SERIAL_8250_CONSOLE=y 856CONFIG_SERIAL_8250_CONSOLE=y
821CONFIG_SERIAL_8250_PCI=y 857# CONFIG_SERIAL_8250_PCI is not set
822CONFIG_SERIAL_8250_NR_UARTS=4 858CONFIG_SERIAL_8250_NR_UARTS=2
823CONFIG_SERIAL_8250_RUNTIME_UARTS=4 859CONFIG_SERIAL_8250_RUNTIME_UARTS=2
824# CONFIG_SERIAL_8250_EXTENDED is not set 860# CONFIG_SERIAL_8250_EXTENDED is not set
825 861
826# 862#
@@ -830,8 +866,7 @@ CONFIG_SERIAL_CORE=y
830CONFIG_SERIAL_CORE_CONSOLE=y 866CONFIG_SERIAL_CORE_CONSOLE=y
831# CONFIG_SERIAL_JSM is not set 867# CONFIG_SERIAL_JSM is not set
832CONFIG_UNIX98_PTYS=y 868CONFIG_UNIX98_PTYS=y
833CONFIG_LEGACY_PTYS=y 869# CONFIG_LEGACY_PTYS is not set
834CONFIG_LEGACY_PTY_COUNT=256
835 870
836# 871#
837# IPMI 872# IPMI
@@ -843,7 +878,8 @@ CONFIG_LEGACY_PTY_COUNT=256
843# 878#
844# CONFIG_WATCHDOG is not set 879# CONFIG_WATCHDOG is not set
845# CONFIG_HW_RANDOM is not set 880# CONFIG_HW_RANDOM is not set
846CONFIG_RTC=y 881# CONFIG_RTC is not set
882# CONFIG_GEN_RTC is not set
847# CONFIG_DTLK is not set 883# CONFIG_DTLK is not set
848# CONFIG_R3964 is not set 884# CONFIG_R3964 is not set
849# CONFIG_APPLICOM is not set 885# CONFIG_APPLICOM is not set
@@ -858,7 +894,58 @@ CONFIG_RTC=y
858# 894#
859# I2C support 895# I2C support
860# 896#
861# CONFIG_I2C is not set 897CONFIG_I2C=y
898CONFIG_I2C_CHARDEV=y
899
900#
901# I2C Algorithms
902#
903# CONFIG_I2C_ALGOBIT is not set
904# CONFIG_I2C_ALGOPCF is not set
905# CONFIG_I2C_ALGOPCA is not set
906
907#
908# I2C Hardware Bus support
909#
910# CONFIG_I2C_ALI1535 is not set
911# CONFIG_I2C_ALI1563 is not set
912# CONFIG_I2C_ALI15X3 is not set
913# CONFIG_I2C_AMD756 is not set
914# CONFIG_I2C_AMD8111 is not set
915# CONFIG_I2C_I801 is not set
916# CONFIG_I2C_I810 is not set
917# CONFIG_I2C_PIIX4 is not set
918# CONFIG_I2C_NFORCE2 is not set
919# CONFIG_I2C_OCORES is not set
920# CONFIG_I2C_PARPORT_LIGHT is not set
921# CONFIG_I2C_PASEMI is not set
922# CONFIG_I2C_PROSAVAGE is not set
923# CONFIG_I2C_SAVAGE4 is not set
924# CONFIG_I2C_SIS5595 is not set
925# CONFIG_I2C_SIS630 is not set
926# CONFIG_I2C_SIS96X is not set
927# CONFIG_I2C_STUB is not set
928# CONFIG_I2C_VIA is not set
929# CONFIG_I2C_VIAPRO is not set
930# CONFIG_I2C_VOODOO3 is not set
931# CONFIG_I2C_PCA_ISA is not set
932CONFIG_I2C_PMCMSP=y
933
934#
935# Miscellaneous I2C Chip support
936#
937# CONFIG_SENSORS_DS1337 is not set
938# CONFIG_SENSORS_DS1374 is not set
939# CONFIG_SENSORS_EEPROM is not set
940# CONFIG_SENSORS_PCF8574 is not set
941CONFIG_PMCTWILED=y
942# CONFIG_SENSORS_PCA9539 is not set
943# CONFIG_SENSORS_PCF8591 is not set
944# CONFIG_SENSORS_MAX6875 is not set
945# CONFIG_I2C_DEBUG_CORE is not set
946# CONFIG_I2C_DEBUG_ALGO is not set
947# CONFIG_I2C_DEBUG_BUS is not set
948# CONFIG_I2C_DEBUG_CHIP is not set
862 949
863# 950#
864# SPI support 951# SPI support
@@ -874,8 +961,57 @@ CONFIG_RTC=y
874# 961#
875# Hardware Monitoring support 962# Hardware Monitoring support
876# 963#
877# CONFIG_HWMON is not set 964CONFIG_HWMON=y
878# CONFIG_HWMON_VID is not set 965# CONFIG_HWMON_VID is not set
966# CONFIG_SENSORS_ABITUGURU is not set
967# CONFIG_SENSORS_ADM1021 is not set
968# CONFIG_SENSORS_ADM1025 is not set
969# CONFIG_SENSORS_ADM1026 is not set
970# CONFIG_SENSORS_ADM1029 is not set
971# CONFIG_SENSORS_ADM1031 is not set
972# CONFIG_SENSORS_ADM9240 is not set
973# CONFIG_SENSORS_ASB100 is not set
974# CONFIG_SENSORS_ATXP1 is not set
975# CONFIG_SENSORS_DS1621 is not set
976# CONFIG_SENSORS_F71805F is not set
977# CONFIG_SENSORS_FSCHER is not set
978# CONFIG_SENSORS_FSCPOS is not set
979# CONFIG_SENSORS_GL518SM is not set
980# CONFIG_SENSORS_GL520SM is not set
981# CONFIG_SENSORS_IT87 is not set
982# CONFIG_SENSORS_LM63 is not set
983# CONFIG_SENSORS_LM75 is not set
984# CONFIG_SENSORS_LM77 is not set
985# CONFIG_SENSORS_LM78 is not set
986# CONFIG_SENSORS_LM80 is not set
987# CONFIG_SENSORS_LM83 is not set
988# CONFIG_SENSORS_LM85 is not set
989# CONFIG_SENSORS_LM87 is not set
990# CONFIG_SENSORS_LM90 is not set
991# CONFIG_SENSORS_LM92 is not set
992# CONFIG_SENSORS_MAX1619 is not set
993# CONFIG_SENSORS_PC87360 is not set
994# CONFIG_SENSORS_PC87427 is not set
995# CONFIG_SENSORS_SIS5595 is not set
996# CONFIG_SENSORS_SMSC47M1 is not set
997# CONFIG_SENSORS_SMSC47M192 is not set
998# CONFIG_SENSORS_SMSC47B397 is not set
999# CONFIG_SENSORS_VIA686A is not set
1000# CONFIG_SENSORS_VT1211 is not set
1001# CONFIG_SENSORS_VT8231 is not set
1002# CONFIG_SENSORS_W83781D is not set
1003# CONFIG_SENSORS_W83791D is not set
1004# CONFIG_SENSORS_W83792D is not set
1005# CONFIG_SENSORS_W83793 is not set
1006# CONFIG_SENSORS_W83L785TS is not set
1007# CONFIG_SENSORS_W83627HF is not set
1008# CONFIG_SENSORS_W83627EHF is not set
1009# CONFIG_HWMON_DEBUG_CHIP is not set
1010
1011#
1012# Multifunction device drivers
1013#
1014# CONFIG_MFD_SM501 is not set
879 1015
880# 1016#
881# Multimedia devices 1017# Multimedia devices
@@ -886,62 +1022,13 @@ CONFIG_RTC=y
886# Digital Video Broadcasting Devices 1022# Digital Video Broadcasting Devices
887# 1023#
888# CONFIG_DVB is not set 1024# CONFIG_DVB is not set
1025# CONFIG_USB_DABUSB is not set
889 1026
890# 1027#
891# Graphics support 1028# Graphics support
892# 1029#
893# CONFIG_FIRMWARE_EDID is not set
894CONFIG_FB=y
895# CONFIG_FB_CFB_FILLRECT is not set
896# CONFIG_FB_CFB_COPYAREA is not set
897# CONFIG_FB_CFB_IMAGEBLIT is not set
898# CONFIG_FB_SVGALIB is not set
899# CONFIG_FB_MACMODES is not set
900# CONFIG_FB_BACKLIGHT is not set
901CONFIG_FB_MODE_HELPERS=y
902# CONFIG_FB_TILEBLITTING is not set
903# CONFIG_FB_CIRRUS is not set
904# CONFIG_FB_PM2 is not set
905# CONFIG_FB_CYBER2000 is not set
906# CONFIG_FB_ASILIANT is not set
907# CONFIG_FB_IMSTT is not set
908# CONFIG_FB_S1D13XXX is not set
909# CONFIG_FB_NVIDIA is not set
910# CONFIG_FB_RIVA is not set
911# CONFIG_FB_MATROX is not set
912# CONFIG_FB_RADEON is not set
913# CONFIG_FB_ATY128 is not set
914# CONFIG_FB_ATY is not set
915# CONFIG_FB_S3 is not set
916# CONFIG_FB_SAVAGE is not set
917# CONFIG_FB_SIS is not set
918# CONFIG_FB_NEOMAGIC is not set
919# CONFIG_FB_KYRO is not set
920# CONFIG_FB_3DFX is not set
921# CONFIG_FB_VOODOO1 is not set
922# CONFIG_FB_SMIVGX is not set
923# CONFIG_FB_TRIDENT is not set
924# CONFIG_FB_VIRTUAL is not set
925
926#
927# Console display driver support
928#
929# CONFIG_VGA_CONSOLE is not set
930CONFIG_DUMMY_CONSOLE=y
931CONFIG_FRAMEBUFFER_CONSOLE=y
932# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
933# CONFIG_FONTS is not set
934CONFIG_FONT_8x8=y
935CONFIG_FONT_8x16=y
936
937#
938# Logo configuration
939#
940CONFIG_LOGO=y
941CONFIG_LOGO_LINUX_MONO=y
942CONFIG_LOGO_LINUX_VGA16=y
943CONFIG_LOGO_LINUX_CLUT224=y
944# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1030# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1031# CONFIG_FB is not set
945 1032
946# 1033#
947# Sound 1034# Sound
@@ -960,13 +1047,134 @@ CONFIG_HID=y
960CONFIG_USB_ARCH_HAS_HCD=y 1047CONFIG_USB_ARCH_HAS_HCD=y
961CONFIG_USB_ARCH_HAS_OHCI=y 1048CONFIG_USB_ARCH_HAS_OHCI=y
962CONFIG_USB_ARCH_HAS_EHCI=y 1049CONFIG_USB_ARCH_HAS_EHCI=y
963# CONFIG_USB is not set 1050CONFIG_USB=y
1051# CONFIG_USB_DEBUG is not set
1052
1053#
1054# Miscellaneous USB options
1055#
1056CONFIG_USB_DEVICEFS=y
1057# CONFIG_USB_DYNAMIC_MINORS is not set
1058# CONFIG_USB_OTG is not set
1059
1060#
1061# USB Host Controller Drivers
1062#
1063CONFIG_USB_EHCI_HCD=y
1064# CONFIG_USB_EHCI_SPLIT_ISO is not set
1065CONFIG_USB_EHCI_ROOT_HUB_TT=y
1066# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1067# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
1068# CONFIG_USB_ISP116X_HCD is not set
1069# CONFIG_USB_OHCI_HCD is not set
1070# CONFIG_USB_UHCI_HCD is not set
1071# CONFIG_USB_SL811_HCD is not set
1072
1073#
1074# USB Device Class drivers
1075#
1076# CONFIG_USB_ACM is not set
1077# CONFIG_USB_PRINTER is not set
964 1078
965# 1079#
966# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1080# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
967# 1081#
968 1082
969# 1083#
1084# may also be needed; see USB_STORAGE Help for more information
1085#
1086CONFIG_USB_STORAGE=y
1087# CONFIG_USB_STORAGE_DEBUG is not set
1088# CONFIG_USB_STORAGE_DATAFAB is not set
1089# CONFIG_USB_STORAGE_FREECOM is not set
1090# CONFIG_USB_STORAGE_DPCM is not set
1091# CONFIG_USB_STORAGE_USBAT is not set
1092# CONFIG_USB_STORAGE_SDDR09 is not set
1093# CONFIG_USB_STORAGE_SDDR55 is not set
1094# CONFIG_USB_STORAGE_JUMPSHOT is not set
1095# CONFIG_USB_STORAGE_ALAUDA is not set
1096# CONFIG_USB_STORAGE_KARMA is not set
1097# CONFIG_USB_LIBUSUAL is not set
1098
1099#
1100# USB Input Devices
1101#
1102# CONFIG_USB_HID is not set
1103
1104#
1105# USB HID Boot Protocol drivers
1106#
1107# CONFIG_USB_KBD is not set
1108# CONFIG_USB_MOUSE is not set
1109# CONFIG_USB_AIPTEK is not set
1110# CONFIG_USB_WACOM is not set
1111# CONFIG_USB_ACECAD is not set
1112# CONFIG_USB_KBTAB is not set
1113# CONFIG_USB_POWERMATE is not set
1114# CONFIG_USB_TOUCHSCREEN is not set
1115# CONFIG_USB_YEALINK is not set
1116# CONFIG_USB_XPAD is not set
1117# CONFIG_USB_ATI_REMOTE is not set
1118# CONFIG_USB_ATI_REMOTE2 is not set
1119# CONFIG_USB_KEYSPAN_REMOTE is not set
1120# CONFIG_USB_APPLETOUCH is not set
1121# CONFIG_USB_GTCO is not set
1122
1123#
1124# USB Imaging devices
1125#
1126# CONFIG_USB_MDC800 is not set
1127# CONFIG_USB_MICROTEK is not set
1128
1129#
1130# USB Network Adapters
1131#
1132# CONFIG_USB_CATC is not set
1133# CONFIG_USB_KAWETH is not set
1134# CONFIG_USB_PEGASUS is not set
1135# CONFIG_USB_RTL8150 is not set
1136# CONFIG_USB_USBNET_MII is not set
1137# CONFIG_USB_USBNET is not set
1138CONFIG_USB_MON=y
1139
1140#
1141# USB port drivers
1142#
1143
1144#
1145# USB Serial Converter support
1146#
1147# CONFIG_USB_SERIAL is not set
1148
1149#
1150# USB Miscellaneous drivers
1151#
1152# CONFIG_USB_EMI62 is not set
1153# CONFIG_USB_EMI26 is not set
1154# CONFIG_USB_ADUTUX is not set
1155# CONFIG_USB_AUERSWALD is not set
1156# CONFIG_USB_RIO500 is not set
1157# CONFIG_USB_LEGOTOWER is not set
1158# CONFIG_USB_LCD is not set
1159# CONFIG_USB_BERRY_CHARGE is not set
1160# CONFIG_USB_LED is not set
1161# CONFIG_USB_CYPRESS_CY7C63 is not set
1162# CONFIG_USB_CYTHERM is not set
1163# CONFIG_USB_PHIDGET is not set
1164# CONFIG_USB_IDMOUSE is not set
1165# CONFIG_USB_FTDI_ELAN is not set
1166# CONFIG_USB_APPLEDISPLAY is not set
1167# CONFIG_USB_SISUSBVGA is not set
1168# CONFIG_USB_LD is not set
1169# CONFIG_USB_TRANCEVIBRATOR is not set
1170# CONFIG_USB_IOWARRIOR is not set
1171# CONFIG_USB_TEST is not set
1172
1173#
1174# USB DSL modem support
1175#
1176
1177#
970# USB Gadget Support 1178# USB Gadget Support
971# 1179#
972# CONFIG_USB_GADGET is not set 1180# CONFIG_USB_GADGET is not set
@@ -1030,37 +1238,22 @@ CONFIG_USB_ARCH_HAS_EHCI=y
1030CONFIG_EXT2_FS=y 1238CONFIG_EXT2_FS=y
1031# CONFIG_EXT2_FS_XATTR is not set 1239# CONFIG_EXT2_FS_XATTR is not set
1032# CONFIG_EXT2_FS_XIP is not set 1240# CONFIG_EXT2_FS_XIP is not set
1033CONFIG_EXT3_FS=m 1241# CONFIG_EXT3_FS is not set
1034CONFIG_EXT3_FS_XATTR=y
1035# CONFIG_EXT3_FS_POSIX_ACL is not set
1036# CONFIG_EXT3_FS_SECURITY is not set
1037# CONFIG_EXT4DEV_FS is not set 1242# CONFIG_EXT4DEV_FS is not set
1038CONFIG_JBD=m 1243# CONFIG_REISERFS_FS is not set
1039# CONFIG_JBD_DEBUG is not set
1040CONFIG_FS_MBCACHE=y
1041CONFIG_REISERFS_FS=m
1042# CONFIG_REISERFS_CHECK is not set
1043# CONFIG_REISERFS_PROC_INFO is not set
1044# CONFIG_REISERFS_FS_XATTR is not set
1045# CONFIG_JFS_FS is not set 1244# CONFIG_JFS_FS is not set
1046CONFIG_FS_POSIX_ACL=y 1245# CONFIG_FS_POSIX_ACL is not set
1047CONFIG_XFS_FS=m 1246# CONFIG_XFS_FS is not set
1048# CONFIG_XFS_QUOTA is not set
1049# CONFIG_XFS_SECURITY is not set
1050# CONFIG_XFS_POSIX_ACL is not set
1051# CONFIG_XFS_RT is not set
1052# CONFIG_GFS2_FS is not set 1247# CONFIG_GFS2_FS is not set
1053# CONFIG_OCFS2_FS is not set 1248# CONFIG_OCFS2_FS is not set
1054# CONFIG_MINIX_FS is not set 1249# CONFIG_MINIX_FS is not set
1055# CONFIG_ROMFS_FS is not set 1250# CONFIG_ROMFS_FS is not set
1056CONFIG_INOTIFY=y 1251# CONFIG_INOTIFY is not set
1057CONFIG_INOTIFY_USER=y
1058# CONFIG_QUOTA is not set 1252# CONFIG_QUOTA is not set
1059CONFIG_DNOTIFY=y 1253# CONFIG_DNOTIFY is not set
1060CONFIG_AUTOFS_FS=y 1254# CONFIG_AUTOFS_FS is not set
1061CONFIG_AUTOFS4_FS=m 1255# CONFIG_AUTOFS4_FS is not set
1062CONFIG_FUSE_FS=m 1256# CONFIG_FUSE_FS is not set
1063CONFIG_GENERIC_ACL=y
1064 1257
1065# 1258#
1066# CD-ROM/DVD Filesystems 1259# CD-ROM/DVD Filesystems
@@ -1071,22 +1264,25 @@ CONFIG_GENERIC_ACL=y
1071# 1264#
1072# DOS/FAT/NT Filesystems 1265# DOS/FAT/NT Filesystems
1073# 1266#
1074# CONFIG_MSDOS_FS is not set 1267CONFIG_FAT_FS=y
1075# CONFIG_VFAT_FS is not set 1268CONFIG_MSDOS_FS=y
1269CONFIG_VFAT_FS=y
1270CONFIG_FAT_DEFAULT_CODEPAGE=437
1271CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1076# CONFIG_NTFS_FS is not set 1272# CONFIG_NTFS_FS is not set
1077 1273
1078# 1274#
1079# Pseudo filesystems 1275# Pseudo filesystems
1080# 1276#
1081CONFIG_PROC_FS=y 1277CONFIG_PROC_FS=y
1082CONFIG_PROC_KCORE=y 1278# CONFIG_PROC_KCORE is not set
1083CONFIG_PROC_SYSCTL=y 1279CONFIG_PROC_SYSCTL=y
1084CONFIG_SYSFS=y 1280CONFIG_SYSFS=y
1085CONFIG_TMPFS=y 1281CONFIG_TMPFS=y
1086CONFIG_TMPFS_POSIX_ACL=y 1282# CONFIG_TMPFS_POSIX_ACL is not set
1087# CONFIG_HUGETLB_PAGE is not set 1283# CONFIG_HUGETLB_PAGE is not set
1088CONFIG_RAMFS=y 1284CONFIG_RAMFS=y
1089CONFIG_CONFIGFS_FS=m 1285# CONFIG_CONFIGFS_FS is not set
1090 1286
1091# 1287#
1092# Miscellaneous filesystems 1288# Miscellaneous filesystems
@@ -1097,8 +1293,21 @@ CONFIG_CONFIGFS_FS=m
1097# CONFIG_HFSPLUS_FS is not set 1293# CONFIG_HFSPLUS_FS is not set
1098# CONFIG_BEFS_FS is not set 1294# CONFIG_BEFS_FS is not set
1099# CONFIG_BFS_FS is not set 1295# CONFIG_BFS_FS is not set
1100CONFIG_EFS_FS=y 1296# CONFIG_EFS_FS is not set
1101CONFIG_CRAMFS=y 1297CONFIG_JFFS2_FS=y
1298CONFIG_JFFS2_FS_DEBUG=0
1299CONFIG_JFFS2_FS_WRITEBUFFER=y
1300# CONFIG_JFFS2_SUMMARY is not set
1301# CONFIG_JFFS2_FS_XATTR is not set
1302# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1303CONFIG_JFFS2_ZLIB=y
1304CONFIG_JFFS2_RTIME=y
1305# CONFIG_JFFS2_RUBIN is not set
1306# CONFIG_CRAMFS is not set
1307CONFIG_SQUASHFS=y
1308CONFIG_SQUASHFS_EMBEDDED=y
1309CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
1310CONFIG_SQUASHFS_VMALLOC=y
1102# CONFIG_VXFS_FS is not set 1311# CONFIG_VXFS_FS is not set
1103# CONFIG_HPFS_FS is not set 1312# CONFIG_HPFS_FS is not set
1104# CONFIG_QNX4FS_FS is not set 1313# CONFIG_QNX4FS_FS is not set
@@ -1108,26 +1317,9 @@ CONFIG_CRAMFS=y
1108# 1317#
1109# Network File Systems 1318# Network File Systems
1110# 1319#
1111CONFIG_NFS_FS=y 1320# CONFIG_NFS_FS is not set
1112CONFIG_NFS_V3=y 1321# CONFIG_NFSD is not set
1113# CONFIG_NFS_V3_ACL is not set 1322# CONFIG_SMB_FS is not set
1114# CONFIG_NFS_V4 is not set
1115# CONFIG_NFS_DIRECTIO is not set
1116CONFIG_NFSD=y
1117CONFIG_NFSD_V3=y
1118# CONFIG_NFSD_V3_ACL is not set
1119# CONFIG_NFSD_V4 is not set
1120# CONFIG_NFSD_TCP is not set
1121CONFIG_ROOT_NFS=y
1122CONFIG_LOCKD=y
1123CONFIG_LOCKD_V4=y
1124CONFIG_EXPORTFS=y
1125CONFIG_NFS_COMMON=y
1126CONFIG_SUNRPC=y
1127# CONFIG_RPCSEC_GSS_KRB5 is not set
1128# CONFIG_RPCSEC_GSS_SPKM3 is not set
1129CONFIG_SMB_FS=m
1130# CONFIG_SMB_NLS_DEFAULT is not set
1131# CONFIG_CIFS is not set 1323# CONFIG_CIFS is not set
1132# CONFIG_NCP_FS is not set 1324# CONFIG_NCP_FS is not set
1133# CONFIG_CODA_FS is not set 1325# CONFIG_CODA_FS is not set
@@ -1143,9 +1335,9 @@ CONFIG_MSDOS_PARTITION=y
1143# 1335#
1144# Native Language Support 1336# Native Language Support
1145# 1337#
1146CONFIG_NLS=m 1338CONFIG_NLS=y
1147CONFIG_NLS_DEFAULT="iso8859-1" 1339CONFIG_NLS_DEFAULT="iso8859-1"
1148# CONFIG_NLS_CODEPAGE_437 is not set 1340CONFIG_NLS_CODEPAGE_437=y
1149# CONFIG_NLS_CODEPAGE_737 is not set 1341# CONFIG_NLS_CODEPAGE_737 is not set
1150# CONFIG_NLS_CODEPAGE_775 is not set 1342# CONFIG_NLS_CODEPAGE_775 is not set
1151# CONFIG_NLS_CODEPAGE_850 is not set 1343# CONFIG_NLS_CODEPAGE_850 is not set
@@ -1169,7 +1361,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
1169# CONFIG_NLS_CODEPAGE_1250 is not set 1361# CONFIG_NLS_CODEPAGE_1250 is not set
1170# CONFIG_NLS_CODEPAGE_1251 is not set 1362# CONFIG_NLS_CODEPAGE_1251 is not set
1171# CONFIG_NLS_ASCII is not set 1363# CONFIG_NLS_ASCII is not set
1172# CONFIG_NLS_ISO8859_1 is not set 1364CONFIG_NLS_ISO8859_1=y
1173# CONFIG_NLS_ISO8859_2 is not set 1365# CONFIG_NLS_ISO8859_2 is not set
1174# CONFIG_NLS_ISO8859_3 is not set 1366# CONFIG_NLS_ISO8859_3 is not set
1175# CONFIG_NLS_ISO8859_4 is not set 1367# CONFIG_NLS_ISO8859_4 is not set
@@ -1187,10 +1379,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
1187# 1379#
1188# Distributed Lock Manager 1380# Distributed Lock Manager
1189# 1381#
1190CONFIG_DLM=m 1382# CONFIG_DLM is not set
1191CONFIG_DLM_TCP=y
1192# CONFIG_DLM_SCTP is not set
1193# CONFIG_DLM_DEBUG is not set
1194 1383
1195# 1384#
1196# Profiling support 1385# Profiling support
@@ -1203,14 +1392,40 @@ CONFIG_DLM_TCP=y
1203CONFIG_TRACE_IRQFLAGS_SUPPORT=y 1392CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1204# CONFIG_PRINTK_TIME is not set 1393# CONFIG_PRINTK_TIME is not set
1205CONFIG_ENABLE_MUST_CHECK=y 1394CONFIG_ENABLE_MUST_CHECK=y
1206# CONFIG_MAGIC_SYSRQ is not set 1395CONFIG_MAGIC_SYSRQ=y
1207# CONFIG_UNUSED_SYMBOLS is not set 1396# CONFIG_UNUSED_SYMBOLS is not set
1208# CONFIG_DEBUG_FS is not set 1397# CONFIG_DEBUG_FS is not set
1209# CONFIG_HEADERS_CHECK is not set 1398# CONFIG_HEADERS_CHECK is not set
1210# CONFIG_DEBUG_KERNEL is not set 1399CONFIG_DEBUG_KERNEL=y
1400# CONFIG_DEBUG_SHIRQ is not set
1211CONFIG_LOG_BUF_SHIFT=14 1401CONFIG_LOG_BUF_SHIFT=14
1402CONFIG_DETECT_SOFTLOCKUP=y
1403# CONFIG_SCHEDSTATS is not set
1404# CONFIG_TIMER_STATS is not set
1405# CONFIG_DEBUG_SLAB is not set
1406CONFIG_DEBUG_PREEMPT=y
1407# CONFIG_DEBUG_RT_MUTEXES is not set
1408# CONFIG_RT_MUTEX_TESTER is not set
1409# CONFIG_DEBUG_SPINLOCK is not set
1410# CONFIG_DEBUG_MUTEXES is not set
1411# CONFIG_DEBUG_LOCK_ALLOC is not set
1412# CONFIG_PROVE_LOCKING is not set
1413# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1414# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1415# CONFIG_DEBUG_KOBJECT is not set
1416# CONFIG_DEBUG_INFO is not set
1417# CONFIG_DEBUG_VM is not set
1418# CONFIG_DEBUG_LIST is not set
1419CONFIG_FORCED_INLINING=y
1420# CONFIG_RCU_TORTURE_TEST is not set
1421# CONFIG_FAULT_INJECTION is not set
1212CONFIG_CROSSCOMPILE=y 1422CONFIG_CROSSCOMPILE=y
1213CONFIG_CMDLINE="ip=any root=nfs" 1423CONFIG_CMDLINE=""
1424# CONFIG_DEBUG_STACK_USAGE is not set
1425# CONFIG_KGDB is not set
1426CONFIG_SYS_SUPPORTS_KGDB=y
1427# CONFIG_RUNTIME_DEBUG is not set
1428# CONFIG_MIPS_UNCACHED is not set
1214 1429
1215# 1430#
1216# Security options 1431# Security options
@@ -1223,41 +1438,40 @@ CONFIG_CMDLINE="ip=any root=nfs"
1223# 1438#
1224CONFIG_CRYPTO=y 1439CONFIG_CRYPTO=y
1225CONFIG_CRYPTO_ALGAPI=y 1440CONFIG_CRYPTO_ALGAPI=y
1226CONFIG_CRYPTO_BLKCIPHER=m 1441CONFIG_CRYPTO_BLKCIPHER=y
1227CONFIG_CRYPTO_HASH=y 1442CONFIG_CRYPTO_HASH=y
1228CONFIG_CRYPTO_MANAGER=y 1443CONFIG_CRYPTO_MANAGER=y
1229CONFIG_CRYPTO_HMAC=y 1444CONFIG_CRYPTO_HMAC=y
1230CONFIG_CRYPTO_XCBC=m 1445# CONFIG_CRYPTO_XCBC is not set
1231CONFIG_CRYPTO_NULL=m 1446CONFIG_CRYPTO_NULL=y
1232CONFIG_CRYPTO_MD4=m 1447# CONFIG_CRYPTO_MD4 is not set
1233CONFIG_CRYPTO_MD5=y 1448CONFIG_CRYPTO_MD5=y
1234CONFIG_CRYPTO_SHA1=m 1449CONFIG_CRYPTO_SHA1=y
1235CONFIG_CRYPTO_SHA256=m 1450# CONFIG_CRYPTO_SHA256 is not set
1236CONFIG_CRYPTO_SHA512=m 1451# CONFIG_CRYPTO_SHA512 is not set
1237CONFIG_CRYPTO_WP512=m 1452# CONFIG_CRYPTO_WP512 is not set
1238CONFIG_CRYPTO_TGR192=m 1453# CONFIG_CRYPTO_TGR192 is not set
1239CONFIG_CRYPTO_GF128MUL=m 1454# CONFIG_CRYPTO_GF128MUL is not set
1240CONFIG_CRYPTO_ECB=m 1455# CONFIG_CRYPTO_ECB is not set
1241CONFIG_CRYPTO_CBC=m 1456CONFIG_CRYPTO_CBC=y
1242CONFIG_CRYPTO_PCBC=m 1457# CONFIG_CRYPTO_PCBC is not set
1243CONFIG_CRYPTO_LRW=m 1458# CONFIG_CRYPTO_LRW is not set
1244CONFIG_CRYPTO_DES=m 1459CONFIG_CRYPTO_DES=y
1245CONFIG_CRYPTO_FCRYPT=m 1460# CONFIG_CRYPTO_FCRYPT is not set
1246CONFIG_CRYPTO_BLOWFISH=m 1461# CONFIG_CRYPTO_BLOWFISH is not set
1247CONFIG_CRYPTO_TWOFISH=m 1462# CONFIG_CRYPTO_TWOFISH is not set
1248CONFIG_CRYPTO_TWOFISH_COMMON=m 1463# CONFIG_CRYPTO_SERPENT is not set
1249CONFIG_CRYPTO_SERPENT=m 1464CONFIG_CRYPTO_AES=y
1250CONFIG_CRYPTO_AES=m 1465# CONFIG_CRYPTO_CAST5 is not set
1251CONFIG_CRYPTO_CAST5=m 1466# CONFIG_CRYPTO_CAST6 is not set
1252CONFIG_CRYPTO_CAST6=m 1467# CONFIG_CRYPTO_TEA is not set
1253CONFIG_CRYPTO_TEA=m 1468# CONFIG_CRYPTO_ARC4 is not set
1254CONFIG_CRYPTO_ARC4=m 1469# CONFIG_CRYPTO_KHAZAD is not set
1255CONFIG_CRYPTO_KHAZAD=m 1470# CONFIG_CRYPTO_ANUBIS is not set
1256CONFIG_CRYPTO_ANUBIS=m 1471CONFIG_CRYPTO_DEFLATE=y
1257CONFIG_CRYPTO_DEFLATE=m 1472# CONFIG_CRYPTO_MICHAEL_MIC is not set
1258CONFIG_CRYPTO_MICHAEL_MIC=m 1473# CONFIG_CRYPTO_CRC32C is not set
1259CONFIG_CRYPTO_CRC32C=m 1474# CONFIG_CRYPTO_CAMELLIA is not set
1260CONFIG_CRYPTO_CAMELLIA=m
1261# CONFIG_CRYPTO_TEST is not set 1475# CONFIG_CRYPTO_TEST is not set
1262 1476
1263# 1477#
@@ -1268,16 +1482,12 @@ CONFIG_CRYPTO_CAMELLIA=m
1268# Library routines 1482# Library routines
1269# 1483#
1270CONFIG_BITREVERSE=y 1484CONFIG_BITREVERSE=y
1271CONFIG_CRC_CCITT=m 1485# CONFIG_CRC_CCITT is not set
1272CONFIG_CRC16=m 1486# CONFIG_CRC16 is not set
1273CONFIG_CRC32=y 1487CONFIG_CRC32=y
1274CONFIG_LIBCRC32C=m 1488# CONFIG_LIBCRC32C is not set
1275CONFIG_ZLIB_INFLATE=y 1489CONFIG_ZLIB_INFLATE=y
1276CONFIG_ZLIB_DEFLATE=m 1490CONFIG_ZLIB_DEFLATE=y
1277CONFIG_TEXTSEARCH=y
1278CONFIG_TEXTSEARCH_KMP=m
1279CONFIG_TEXTSEARCH_BM=m
1280CONFIG_TEXTSEARCH_FSM=m
1281CONFIG_PLIST=y 1491CONFIG_PLIST=y
1282CONFIG_HAS_IOMEM=y 1492CONFIG_HAS_IOMEM=y
1283CONFIG_HAS_IOPORT=y 1493CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig
deleted file mode 100644
index 82ff6fc0cd41..000000000000
--- a/arch/mips/configs/ocelot_c_defconfig
+++ /dev/null
@@ -1,982 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20
4# Tue Feb 20 21:47:36 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set
34# CONFIG_WR_PPMC is not set
35# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39CONFIG_MOMENCO_OCELOT_C=y
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set
43# CONFIG_PNX8550_STB810 is not set
44# CONFIG_DDB5477 is not set
45# CONFIG_MACH_VR41XX is not set
46# CONFIG_PMC_YOSEMITE is not set
47# CONFIG_QEMU is not set
48# CONFIG_MARKEINS is not set
49# CONFIG_SGI_IP22 is not set
50# CONFIG_SGI_IP27 is not set
51# CONFIG_SGI_IP32 is not set
52# CONFIG_SIBYTE_BIGSUR is not set
53# CONFIG_SIBYTE_SWARM is not set
54# CONFIG_SIBYTE_SENTOSA is not set
55# CONFIG_SIBYTE_RHONE is not set
56# CONFIG_SIBYTE_CARMEL is not set
57# CONFIG_SIBYTE_PTSWARM is not set
58# CONFIG_SIBYTE_LITTLESUR is not set
59# CONFIG_SIBYTE_CRHINE is not set
60# CONFIG_SIBYTE_CRHONE is not set
61# CONFIG_SNI_RM is not set
62# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set
64# CONFIG_TOSHIBA_RBTX4938 is not set
65CONFIG_RWSEM_GENERIC_SPINLOCK=y
66# CONFIG_ARCH_HAS_ILOG2_U32 is not set
67# CONFIG_ARCH_HAS_ILOG2_U64 is not set
68CONFIG_GENERIC_FIND_NEXT_BIT=y
69CONFIG_GENERIC_HWEIGHT=y
70CONFIG_GENERIC_CALIBRATE_DELAY=y
71CONFIG_GENERIC_TIME=y
72CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
73CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
74CONFIG_DMA_NONCOHERENT=y
75CONFIG_DMA_NEED_PCI_MAP_STATE=y
76CONFIG_CPU_BIG_ENDIAN=y
77# CONFIG_CPU_LITTLE_ENDIAN is not set
78CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
79CONFIG_IRQ_CPU=y
80CONFIG_IRQ_MV64340=y
81CONFIG_PCI_MARVELL=y
82CONFIG_SWAP_IO_SPACE=y
83CONFIG_MIPS_L1_CACHE_SHIFT=5
84
85#
86# CPU selection
87#
88# CONFIG_CPU_MIPS32_R1 is not set
89# CONFIG_CPU_MIPS32_R2 is not set
90# CONFIG_CPU_MIPS64_R1 is not set
91# CONFIG_CPU_MIPS64_R2 is not set
92# CONFIG_CPU_R3000 is not set
93# CONFIG_CPU_TX39XX is not set
94# CONFIG_CPU_VR41XX is not set
95# CONFIG_CPU_R4300 is not set
96# CONFIG_CPU_R4X00 is not set
97# CONFIG_CPU_TX49XX is not set
98# CONFIG_CPU_R5000 is not set
99# CONFIG_CPU_R5432 is not set
100# CONFIG_CPU_R6000 is not set
101# CONFIG_CPU_NEVADA is not set
102# CONFIG_CPU_R8000 is not set
103# CONFIG_CPU_R10000 is not set
104CONFIG_CPU_RM7000=y
105# CONFIG_CPU_RM9000 is not set
106# CONFIG_CPU_SB1 is not set
107CONFIG_SYS_HAS_CPU_RM7000=y
108CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
109CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
110CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
111CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
112
113#
114# Kernel type
115#
116# CONFIG_32BIT is not set
117CONFIG_64BIT=y
118CONFIG_PAGE_SIZE_4KB=y
119# CONFIG_PAGE_SIZE_8KB is not set
120# CONFIG_PAGE_SIZE_16KB is not set
121# CONFIG_PAGE_SIZE_64KB is not set
122CONFIG_BOARD_SCACHE=y
123CONFIG_RM7000_CPU_SCACHE=y
124CONFIG_CPU_HAS_PREFETCH=y
125CONFIG_MIPS_MT_DISABLED=y
126# CONFIG_MIPS_MT_SMP is not set
127# CONFIG_MIPS_MT_SMTC is not set
128# CONFIG_MIPS_VPE_LOADER is not set
129CONFIG_CPU_HAS_LLSC=y
130CONFIG_CPU_HAS_SYNC=y
131CONFIG_GENERIC_HARDIRQS=y
132CONFIG_GENERIC_IRQ_PROBE=y
133CONFIG_CPU_SUPPORTS_HIGHMEM=y
134CONFIG_ARCH_FLATMEM_ENABLE=y
135CONFIG_SELECT_MEMORY_MODEL=y
136CONFIG_FLATMEM_MANUAL=y
137# CONFIG_DISCONTIGMEM_MANUAL is not set
138# CONFIG_SPARSEMEM_MANUAL is not set
139CONFIG_FLATMEM=y
140CONFIG_FLAT_NODE_MEM_MAP=y
141# CONFIG_SPARSEMEM_STATIC is not set
142CONFIG_SPLIT_PTLOCK_CPUS=4
143CONFIG_RESOURCES_64BIT=y
144CONFIG_ZONE_DMA_FLAG=1
145# CONFIG_HZ_48 is not set
146# CONFIG_HZ_100 is not set
147# CONFIG_HZ_128 is not set
148# CONFIG_HZ_250 is not set
149# CONFIG_HZ_256 is not set
150CONFIG_HZ_1000=y
151# CONFIG_HZ_1024 is not set
152CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
153CONFIG_HZ=1000
154CONFIG_PREEMPT_NONE=y
155# CONFIG_PREEMPT_VOLUNTARY is not set
156# CONFIG_PREEMPT is not set
157# CONFIG_KEXEC is not set
158CONFIG_LOCKDEP_SUPPORT=y
159CONFIG_STACKTRACE_SUPPORT=y
160CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
161
162#
163# Code maturity level options
164#
165CONFIG_EXPERIMENTAL=y
166CONFIG_BROKEN_ON_SMP=y
167CONFIG_INIT_ENV_ARG_LIMIT=32
168
169#
170# General setup
171#
172CONFIG_LOCALVERSION=""
173CONFIG_LOCALVERSION_AUTO=y
174CONFIG_SWAP=y
175CONFIG_SYSVIPC=y
176# CONFIG_IPC_NS is not set
177CONFIG_SYSVIPC_SYSCTL=y
178# CONFIG_POSIX_MQUEUE is not set
179# CONFIG_BSD_PROCESS_ACCT is not set
180# CONFIG_TASKSTATS is not set
181# CONFIG_UTS_NS is not set
182# CONFIG_AUDIT is not set
183# CONFIG_IKCONFIG is not set
184CONFIG_SYSFS_DEPRECATED=y
185CONFIG_RELAY=y
186# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
187CONFIG_SYSCTL=y
188CONFIG_EMBEDDED=y
189CONFIG_SYSCTL_SYSCALL=y
190CONFIG_KALLSYMS=y
191# CONFIG_KALLSYMS_EXTRA_PASS is not set
192CONFIG_HOTPLUG=y
193CONFIG_PRINTK=y
194CONFIG_BUG=y
195CONFIG_ELF_CORE=y
196CONFIG_BASE_FULL=y
197CONFIG_FUTEX=y
198CONFIG_EPOLL=y
199CONFIG_SHMEM=y
200CONFIG_SLAB=y
201CONFIG_VM_EVENT_COUNTERS=y
202CONFIG_RT_MUTEXES=y
203# CONFIG_TINY_SHMEM is not set
204CONFIG_BASE_SMALL=0
205# CONFIG_SLOB is not set
206
207#
208# Loadable module support
209#
210# CONFIG_MODULES is not set
211
212#
213# Block layer
214#
215CONFIG_BLOCK=y
216# CONFIG_BLK_DEV_IO_TRACE is not set
217
218#
219# IO Schedulers
220#
221CONFIG_IOSCHED_NOOP=y
222CONFIG_IOSCHED_AS=y
223CONFIG_IOSCHED_DEADLINE=y
224CONFIG_IOSCHED_CFQ=y
225CONFIG_DEFAULT_AS=y
226# CONFIG_DEFAULT_DEADLINE is not set
227# CONFIG_DEFAULT_CFQ is not set
228# CONFIG_DEFAULT_NOOP is not set
229CONFIG_DEFAULT_IOSCHED="anticipatory"
230
231#
232# Bus options (PCI, PCMCIA, EISA, ISA, TC)
233#
234CONFIG_HW_HAS_PCI=y
235CONFIG_PCI=y
236CONFIG_MMU=y
237
238#
239# PCCARD (PCMCIA/CardBus) support
240#
241# CONFIG_PCCARD is not set
242
243#
244# PCI Hotplug Support
245#
246# CONFIG_HOTPLUG_PCI is not set
247
248#
249# Executable file formats
250#
251CONFIG_BINFMT_ELF=y
252# CONFIG_BINFMT_MISC is not set
253# CONFIG_BUILD_ELF64 is not set
254CONFIG_MIPS32_COMPAT=y
255CONFIG_COMPAT=y
256CONFIG_SYSVIPC_COMPAT=y
257CONFIG_MIPS32_O32=y
258CONFIG_MIPS32_N32=y
259CONFIG_BINFMT_ELF32=y
260
261#
262# Power management options
263#
264CONFIG_PM=y
265# CONFIG_PM_LEGACY is not set
266# CONFIG_PM_DEBUG is not set
267# CONFIG_PM_SYSFS_DEPRECATED is not set
268
269#
270# Networking
271#
272CONFIG_NET=y
273
274#
275# Networking options
276#
277# CONFIG_NETDEBUG is not set
278# CONFIG_PACKET is not set
279CONFIG_UNIX=y
280CONFIG_XFRM=y
281CONFIG_XFRM_USER=y
282# CONFIG_XFRM_SUB_POLICY is not set
283CONFIG_XFRM_MIGRATE=y
284CONFIG_NET_KEY=y
285CONFIG_NET_KEY_MIGRATE=y
286CONFIG_INET=y
287# CONFIG_IP_MULTICAST is not set
288# CONFIG_IP_ADVANCED_ROUTER is not set
289CONFIG_IP_FIB_HASH=y
290CONFIG_IP_PNP=y
291CONFIG_IP_PNP_DHCP=y
292# CONFIG_IP_PNP_BOOTP is not set
293# CONFIG_IP_PNP_RARP is not set
294# CONFIG_NET_IPIP is not set
295# CONFIG_NET_IPGRE is not set
296# CONFIG_ARPD is not set
297# CONFIG_SYN_COOKIES is not set
298# CONFIG_INET_AH is not set
299# CONFIG_INET_ESP is not set
300# CONFIG_INET_IPCOMP is not set
301# CONFIG_INET_XFRM_TUNNEL is not set
302# CONFIG_INET_TUNNEL is not set
303CONFIG_INET_XFRM_MODE_TRANSPORT=y
304CONFIG_INET_XFRM_MODE_TUNNEL=y
305CONFIG_INET_XFRM_MODE_BEET=y
306CONFIG_INET_DIAG=y
307CONFIG_INET_TCP_DIAG=y
308# CONFIG_TCP_CONG_ADVANCED is not set
309CONFIG_TCP_CONG_CUBIC=y
310CONFIG_DEFAULT_TCP_CONG="cubic"
311CONFIG_TCP_MD5SIG=y
312# CONFIG_IPV6 is not set
313# CONFIG_INET6_XFRM_TUNNEL is not set
314# CONFIG_INET6_TUNNEL is not set
315CONFIG_NETWORK_SECMARK=y
316# CONFIG_NETFILTER is not set
317
318#
319# DCCP Configuration (EXPERIMENTAL)
320#
321# CONFIG_IP_DCCP is not set
322
323#
324# SCTP Configuration (EXPERIMENTAL)
325#
326# CONFIG_IP_SCTP is not set
327
328#
329# TIPC Configuration (EXPERIMENTAL)
330#
331# CONFIG_TIPC is not set
332# CONFIG_ATM is not set
333# CONFIG_BRIDGE is not set
334# CONFIG_VLAN_8021Q is not set
335# CONFIG_DECNET is not set
336# CONFIG_LLC2 is not set
337# CONFIG_IPX is not set
338# CONFIG_ATALK is not set
339# CONFIG_X25 is not set
340# CONFIG_LAPB is not set
341# CONFIG_ECONET is not set
342# CONFIG_WAN_ROUTER is not set
343
344#
345# QoS and/or fair queueing
346#
347# CONFIG_NET_SCHED is not set
348
349#
350# Network testing
351#
352# CONFIG_NET_PKTGEN is not set
353# CONFIG_HAMRADIO is not set
354# CONFIG_IRDA is not set
355# CONFIG_BT is not set
356CONFIG_IEEE80211=y
357# CONFIG_IEEE80211_DEBUG is not set
358CONFIG_IEEE80211_CRYPT_WEP=y
359CONFIG_IEEE80211_CRYPT_CCMP=y
360CONFIG_IEEE80211_SOFTMAC=y
361# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
362CONFIG_WIRELESS_EXT=y
363
364#
365# Device Drivers
366#
367
368#
369# Generic Driver Options
370#
371CONFIG_STANDALONE=y
372CONFIG_PREVENT_FIRMWARE_BUILD=y
373CONFIG_FW_LOADER=y
374# CONFIG_SYS_HYPERVISOR is not set
375
376#
377# Connector - unified userspace <-> kernelspace linker
378#
379CONFIG_CONNECTOR=y
380CONFIG_PROC_EVENTS=y
381
382#
383# Memory Technology Devices (MTD)
384#
385# CONFIG_MTD is not set
386
387#
388# Parallel port support
389#
390# CONFIG_PARPORT is not set
391
392#
393# Plug and Play support
394#
395# CONFIG_PNPACPI is not set
396
397#
398# Block devices
399#
400# CONFIG_BLK_CPQ_DA is not set
401# CONFIG_BLK_CPQ_CISS_DA is not set
402# CONFIG_BLK_DEV_DAC960 is not set
403# CONFIG_BLK_DEV_UMEM is not set
404# CONFIG_BLK_DEV_COW_COMMON is not set
405# CONFIG_BLK_DEV_LOOP is not set
406# CONFIG_BLK_DEV_NBD is not set
407# CONFIG_BLK_DEV_SX8 is not set
408# CONFIG_BLK_DEV_RAM is not set
409# CONFIG_BLK_DEV_INITRD is not set
410CONFIG_CDROM_PKTCDVD=y
411CONFIG_CDROM_PKTCDVD_BUFFERS=8
412# CONFIG_CDROM_PKTCDVD_WCACHE is not set
413CONFIG_ATA_OVER_ETH=y
414
415#
416# Misc devices
417#
418CONFIG_SGI_IOC4=y
419# CONFIG_TIFM_CORE is not set
420
421#
422# ATA/ATAPI/MFM/RLL support
423#
424# CONFIG_IDE is not set
425
426#
427# SCSI device support
428#
429CONFIG_RAID_ATTRS=y
430# CONFIG_SCSI is not set
431# CONFIG_SCSI_NETLINK is not set
432
433#
434# Serial ATA (prod) and Parallel ATA (experimental) drivers
435#
436# CONFIG_ATA is not set
437
438#
439# Multi-device support (RAID and LVM)
440#
441# CONFIG_MD is not set
442
443#
444# Fusion MPT device support
445#
446# CONFIG_FUSION is not set
447
448#
449# IEEE 1394 (FireWire) support
450#
451# CONFIG_IEEE1394 is not set
452
453#
454# I2O device support
455#
456# CONFIG_I2O is not set
457
458#
459# Network device support
460#
461CONFIG_NETDEVICES=y
462# CONFIG_DUMMY is not set
463# CONFIG_BONDING is not set
464# CONFIG_EQUALIZER is not set
465# CONFIG_TUN is not set
466
467#
468# ARCnet devices
469#
470# CONFIG_ARCNET is not set
471
472#
473# PHY device support
474#
475CONFIG_PHYLIB=y
476
477#
478# MII PHY device drivers
479#
480CONFIG_MARVELL_PHY=y
481CONFIG_DAVICOM_PHY=y
482CONFIG_QSEMI_PHY=y
483CONFIG_LXT_PHY=y
484CONFIG_CICADA_PHY=y
485CONFIG_VITESSE_PHY=y
486CONFIG_SMSC_PHY=y
487# CONFIG_BROADCOM_PHY is not set
488# CONFIG_FIXED_PHY is not set
489
490#
491# Ethernet (10 or 100Mbit)
492#
493CONFIG_NET_ETHERNET=y
494# CONFIG_MII is not set
495# CONFIG_HAPPYMEAL is not set
496# CONFIG_SUNGEM is not set
497# CONFIG_CASSINI is not set
498# CONFIG_NET_VENDOR_3COM is not set
499# CONFIG_DM9000 is not set
500
501#
502# Tulip family network device support
503#
504# CONFIG_NET_TULIP is not set
505# CONFIG_HP100 is not set
506# CONFIG_NET_PCI is not set
507
508#
509# Ethernet (1000 Mbit)
510#
511# CONFIG_ACENIC is not set
512# CONFIG_DL2K is not set
513# CONFIG_E1000 is not set
514# CONFIG_NS83820 is not set
515# CONFIG_HAMACHI is not set
516# CONFIG_YELLOWFIN is not set
517# CONFIG_R8169 is not set
518# CONFIG_SIS190 is not set
519# CONFIG_SKGE is not set
520# CONFIG_SKY2 is not set
521# CONFIG_SK98LIN is not set
522# CONFIG_TIGON3 is not set
523# CONFIG_BNX2 is not set
524# CONFIG_MV643XX_ETH is not set
525CONFIG_QLA3XXX=y
526# CONFIG_ATL1 is not set
527
528#
529# Ethernet (10000 Mbit)
530#
531# CONFIG_CHELSIO_T1 is not set
532CONFIG_CHELSIO_T3=y
533# CONFIG_IXGB is not set
534# CONFIG_S2IO is not set
535# CONFIG_MYRI10GE is not set
536CONFIG_NETXEN_NIC=y
537
538#
539# Token Ring devices
540#
541# CONFIG_TR is not set
542
543#
544# Wireless LAN (non-hamradio)
545#
546# CONFIG_NET_RADIO is not set
547
548#
549# Wan interfaces
550#
551# CONFIG_WAN is not set
552# CONFIG_FDDI is not set
553# CONFIG_HIPPI is not set
554# CONFIG_PPP is not set
555# CONFIG_SLIP is not set
556# CONFIG_SHAPER is not set
557# CONFIG_NETCONSOLE is not set
558# CONFIG_NETPOLL is not set
559# CONFIG_NET_POLL_CONTROLLER is not set
560
561#
562# ISDN subsystem
563#
564# CONFIG_ISDN is not set
565
566#
567# Telephony Support
568#
569# CONFIG_PHONE is not set
570
571#
572# Input device support
573#
574CONFIG_INPUT=y
575# CONFIG_INPUT_FF_MEMLESS is not set
576
577#
578# Userland interfaces
579#
580CONFIG_INPUT_MOUSEDEV=y
581CONFIG_INPUT_MOUSEDEV_PSAUX=y
582CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
583CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
584# CONFIG_INPUT_JOYDEV is not set
585# CONFIG_INPUT_TSDEV is not set
586# CONFIG_INPUT_EVDEV is not set
587# CONFIG_INPUT_EVBUG is not set
588
589#
590# Input Device Drivers
591#
592# CONFIG_INPUT_KEYBOARD is not set
593# CONFIG_INPUT_MOUSE is not set
594# CONFIG_INPUT_JOYSTICK is not set
595# CONFIG_INPUT_TOUCHSCREEN is not set
596# CONFIG_INPUT_MISC is not set
597
598#
599# Hardware I/O ports
600#
601CONFIG_SERIO=y
602# CONFIG_SERIO_I8042 is not set
603CONFIG_SERIO_SERPORT=y
604# CONFIG_SERIO_PCIPS2 is not set
605# CONFIG_SERIO_LIBPS2 is not set
606CONFIG_SERIO_RAW=y
607# CONFIG_GAMEPORT is not set
608
609#
610# Character devices
611#
612CONFIG_VT=y
613CONFIG_VT_CONSOLE=y
614CONFIG_HW_CONSOLE=y
615CONFIG_VT_HW_CONSOLE_BINDING=y
616# CONFIG_SERIAL_NONSTANDARD is not set
617
618#
619# Serial drivers
620#
621CONFIG_SERIAL_8250=y
622CONFIG_SERIAL_8250_CONSOLE=y
623CONFIG_SERIAL_8250_PCI=y
624CONFIG_SERIAL_8250_NR_UARTS=4
625CONFIG_SERIAL_8250_RUNTIME_UARTS=4
626# CONFIG_SERIAL_8250_EXTENDED is not set
627
628#
629# Non-8250 serial port support
630#
631CONFIG_SERIAL_CORE=y
632CONFIG_SERIAL_CORE_CONSOLE=y
633# CONFIG_SERIAL_JSM is not set
634CONFIG_UNIX98_PTYS=y
635CONFIG_LEGACY_PTYS=y
636CONFIG_LEGACY_PTY_COUNT=256
637
638#
639# IPMI
640#
641# CONFIG_IPMI_HANDLER is not set
642
643#
644# Watchdog Cards
645#
646# CONFIG_WATCHDOG is not set
647# CONFIG_HW_RANDOM is not set
648# CONFIG_RTC is not set
649# CONFIG_GEN_RTC is not set
650# CONFIG_DTLK is not set
651# CONFIG_R3964 is not set
652# CONFIG_APPLICOM is not set
653# CONFIG_DRM is not set
654# CONFIG_RAW_DRIVER is not set
655
656#
657# TPM devices
658#
659# CONFIG_TCG_TPM is not set
660
661#
662# I2C support
663#
664# CONFIG_I2C is not set
665
666#
667# SPI support
668#
669# CONFIG_SPI is not set
670# CONFIG_SPI_MASTER is not set
671
672#
673# Dallas's 1-wire bus
674#
675# CONFIG_W1 is not set
676
677#
678# Hardware Monitoring support
679#
680# CONFIG_HWMON is not set
681# CONFIG_HWMON_VID is not set
682
683#
684# Multimedia devices
685#
686# CONFIG_VIDEO_DEV is not set
687
688#
689# Digital Video Broadcasting Devices
690#
691# CONFIG_DVB is not set
692
693#
694# Graphics support
695#
696# CONFIG_FIRMWARE_EDID is not set
697# CONFIG_FB is not set
698
699#
700# Console display driver support
701#
702# CONFIG_VGA_CONSOLE is not set
703CONFIG_DUMMY_CONSOLE=y
704# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
705
706#
707# Sound
708#
709# CONFIG_SOUND is not set
710
711#
712# HID Devices
713#
714# CONFIG_HID is not set
715
716#
717# USB support
718#
719CONFIG_USB_ARCH_HAS_HCD=y
720CONFIG_USB_ARCH_HAS_OHCI=y
721CONFIG_USB_ARCH_HAS_EHCI=y
722# CONFIG_USB is not set
723
724#
725# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
726#
727
728#
729# USB Gadget Support
730#
731# CONFIG_USB_GADGET is not set
732
733#
734# MMC/SD Card support
735#
736# CONFIG_MMC is not set
737
738#
739# LED devices
740#
741# CONFIG_NEW_LEDS is not set
742
743#
744# LED drivers
745#
746
747#
748# LED Triggers
749#
750
751#
752# InfiniBand support
753#
754# CONFIG_INFINIBAND is not set
755
756#
757# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
758#
759
760#
761# Real Time Clock
762#
763# CONFIG_RTC_CLASS is not set
764
765#
766# DMA Engine support
767#
768# CONFIG_DMA_ENGINE is not set
769
770#
771# DMA Clients
772#
773
774#
775# DMA Devices
776#
777
778#
779# Auxiliary Display support
780#
781
782#
783# Virtualization
784#
785
786#
787# File systems
788#
789CONFIG_EXT2_FS=y
790# CONFIG_EXT2_FS_XATTR is not set
791# CONFIG_EXT2_FS_XIP is not set
792# CONFIG_EXT3_FS is not set
793# CONFIG_EXT4DEV_FS is not set
794# CONFIG_REISERFS_FS is not set
795# CONFIG_JFS_FS is not set
796CONFIG_FS_POSIX_ACL=y
797# CONFIG_XFS_FS is not set
798# CONFIG_GFS2_FS is not set
799# CONFIG_OCFS2_FS is not set
800# CONFIG_MINIX_FS is not set
801# CONFIG_ROMFS_FS is not set
802CONFIG_INOTIFY=y
803CONFIG_INOTIFY_USER=y
804# CONFIG_QUOTA is not set
805CONFIG_DNOTIFY=y
806# CONFIG_AUTOFS_FS is not set
807# CONFIG_AUTOFS4_FS is not set
808CONFIG_FUSE_FS=y
809CONFIG_GENERIC_ACL=y
810
811#
812# CD-ROM/DVD Filesystems
813#
814# CONFIG_ISO9660_FS is not set
815# CONFIG_UDF_FS is not set
816
817#
818# DOS/FAT/NT Filesystems
819#
820# CONFIG_MSDOS_FS is not set
821# CONFIG_VFAT_FS is not set
822# CONFIG_NTFS_FS is not set
823
824#
825# Pseudo filesystems
826#
827CONFIG_PROC_FS=y
828CONFIG_PROC_KCORE=y
829CONFIG_PROC_SYSCTL=y
830CONFIG_SYSFS=y
831CONFIG_TMPFS=y
832CONFIG_TMPFS_POSIX_ACL=y
833# CONFIG_HUGETLB_PAGE is not set
834CONFIG_RAMFS=y
835CONFIG_CONFIGFS_FS=y
836
837#
838# Miscellaneous filesystems
839#
840# CONFIG_ADFS_FS is not set
841# CONFIG_AFFS_FS is not set
842# CONFIG_ECRYPT_FS is not set
843# CONFIG_HFS_FS is not set
844# CONFIG_HFSPLUS_FS is not set
845# CONFIG_BEFS_FS is not set
846# CONFIG_BFS_FS is not set
847# CONFIG_EFS_FS is not set
848# CONFIG_CRAMFS is not set
849# CONFIG_VXFS_FS is not set
850# CONFIG_HPFS_FS is not set
851# CONFIG_QNX4FS_FS is not set
852# CONFIG_SYSV_FS is not set
853# CONFIG_UFS_FS is not set
854
855#
856# Network File Systems
857#
858CONFIG_NFS_FS=y
859# CONFIG_NFS_V3 is not set
860# CONFIG_NFS_V4 is not set
861# CONFIG_NFS_DIRECTIO is not set
862CONFIG_NFSD=y
863# CONFIG_NFSD_V3 is not set
864# CONFIG_NFSD_TCP is not set
865CONFIG_ROOT_NFS=y
866CONFIG_LOCKD=y
867CONFIG_EXPORTFS=y
868CONFIG_NFS_COMMON=y
869CONFIG_SUNRPC=y
870# CONFIG_RPCSEC_GSS_KRB5 is not set
871# CONFIG_RPCSEC_GSS_SPKM3 is not set
872# CONFIG_SMB_FS is not set
873# CONFIG_CIFS is not set
874# CONFIG_NCP_FS is not set
875# CONFIG_CODA_FS is not set
876# CONFIG_AFS_FS is not set
877# CONFIG_9P_FS is not set
878
879#
880# Partition Types
881#
882# CONFIG_PARTITION_ADVANCED is not set
883CONFIG_MSDOS_PARTITION=y
884
885#
886# Native Language Support
887#
888# CONFIG_NLS is not set
889
890#
891# Distributed Lock Manager
892#
893CONFIG_DLM=y
894CONFIG_DLM_TCP=y
895# CONFIG_DLM_SCTP is not set
896# CONFIG_DLM_DEBUG is not set
897
898#
899# Profiling support
900#
901# CONFIG_PROFILING is not set
902
903#
904# Kernel hacking
905#
906CONFIG_TRACE_IRQFLAGS_SUPPORT=y
907# CONFIG_PRINTK_TIME is not set
908CONFIG_ENABLE_MUST_CHECK=y
909# CONFIG_MAGIC_SYSRQ is not set
910# CONFIG_UNUSED_SYMBOLS is not set
911# CONFIG_DEBUG_FS is not set
912# CONFIG_HEADERS_CHECK is not set
913# CONFIG_DEBUG_KERNEL is not set
914CONFIG_LOG_BUF_SHIFT=14
915CONFIG_CROSSCOMPILE=y
916CONFIG_CMDLINE=""
917
918#
919# Security options
920#
921CONFIG_KEYS=y
922CONFIG_KEYS_DEBUG_PROC_KEYS=y
923# CONFIG_SECURITY is not set
924
925#
926# Cryptographic options
927#
928CONFIG_CRYPTO=y
929CONFIG_CRYPTO_ALGAPI=y
930CONFIG_CRYPTO_BLKCIPHER=y
931CONFIG_CRYPTO_HASH=y
932CONFIG_CRYPTO_MANAGER=y
933CONFIG_CRYPTO_HMAC=y
934CONFIG_CRYPTO_XCBC=y
935CONFIG_CRYPTO_NULL=y
936CONFIG_CRYPTO_MD4=y
937CONFIG_CRYPTO_MD5=y
938CONFIG_CRYPTO_SHA1=y
939CONFIG_CRYPTO_SHA256=y
940CONFIG_CRYPTO_SHA512=y
941CONFIG_CRYPTO_WP512=y
942CONFIG_CRYPTO_TGR192=y
943CONFIG_CRYPTO_GF128MUL=y
944CONFIG_CRYPTO_ECB=y
945CONFIG_CRYPTO_CBC=y
946CONFIG_CRYPTO_PCBC=y
947CONFIG_CRYPTO_LRW=y
948CONFIG_CRYPTO_DES=y
949CONFIG_CRYPTO_FCRYPT=y
950CONFIG_CRYPTO_BLOWFISH=y
951CONFIG_CRYPTO_TWOFISH=y
952CONFIG_CRYPTO_TWOFISH_COMMON=y
953CONFIG_CRYPTO_SERPENT=y
954CONFIG_CRYPTO_AES=y
955CONFIG_CRYPTO_CAST5=y
956CONFIG_CRYPTO_CAST6=y
957CONFIG_CRYPTO_TEA=y
958CONFIG_CRYPTO_ARC4=y
959CONFIG_CRYPTO_KHAZAD=y
960CONFIG_CRYPTO_ANUBIS=y
961CONFIG_CRYPTO_DEFLATE=y
962CONFIG_CRYPTO_MICHAEL_MIC=y
963CONFIG_CRYPTO_CRC32C=y
964CONFIG_CRYPTO_CAMELLIA=y
965
966#
967# Hardware crypto devices
968#
969
970#
971# Library routines
972#
973CONFIG_BITREVERSE=y
974# CONFIG_CRC_CCITT is not set
975CONFIG_CRC16=y
976CONFIG_CRC32=y
977CONFIG_LIBCRC32C=y
978CONFIG_ZLIB_INFLATE=y
979CONFIG_ZLIB_DEFLATE=y
980CONFIG_PLIST=y
981CONFIG_HAS_IOMEM=y
982CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
index 15a027e00eec..e1db1fb80cd0 100644
--- a/arch/mips/configs/ocelot_defconfig
+++ b/arch/mips/configs/ocelot_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37CONFIG_MOMENCO_OCELOT=y 35CONFIG_MOMENCO_OCELOT=y
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 37d696c64541..0028aef0af9d 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -26,9 +26,7 @@ CONFIG_MIPS_PB1100=y
26# CONFIG_BASLER_EXCITE is not set 26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_MIPS_PB1100=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index b11f0e8b6059..8a1d5888739c 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -26,9 +26,7 @@ CONFIG_MIPS_PB1500=y
26# CONFIG_BASLER_EXCITE is not set 26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_MIPS_PB1500=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 2927f38f4907..5581ad2ca411 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -26,9 +26,7 @@ CONFIG_MIPS_PB1550=y
26# CONFIG_BASLER_EXCITE is not set 26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MIPS_EV64120 is not set
30# CONFIG_MACH_JAZZ is not set 29# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set 31# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set 32# CONFIG_MIPS_SEAD is not set
@@ -36,8 +34,6 @@ CONFIG_MIPS_PB1550=y
36# CONFIG_MIPS_SIM is not set 34# CONFIG_MIPS_SIM is not set
37# CONFIG_MOMENCO_JAGUAR_ATX is not set 35# CONFIG_MOMENCO_JAGUAR_ATX is not set
38# CONFIG_MOMENCO_OCELOT is not set 36# CONFIG_MOMENCO_OCELOT is not set
39# CONFIG_MOMENCO_OCELOT_3 is not set
40# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 37# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 38# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_JBS is not set 39# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index fae16c5ec521..821c1cee5639 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42CONFIG_PNX8550_JBS=y 38CONFIG_PNX8550_JBS=y
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index cd821e52181d..0e8bd92b38cf 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index 8e8d03157954..6cca105832ca 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig
index 35d64260917e..20a38526d483 100644
--- a/arch/mips/configs/rbhma4200_defconfig
+++ b/arch/mips/configs/rbhma4200_defconfig
@@ -24,17 +24,13 @@ CONFIG_MIPS=y
24# CONFIG_BASLER_EXCITE is not set 24# CONFIG_BASLER_EXCITE is not set
25# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
26# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
27# CONFIG_MIPS_EV64120 is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
29# CONFIG_LASAT is not set
30# CONFIG_MIPS_ATLAS is not set 28# CONFIG_MIPS_ATLAS is not set
31# CONFIG_MIPS_MALTA is not set 29# CONFIG_MIPS_MALTA is not set
32# CONFIG_MIPS_SEAD is not set 30# CONFIG_MIPS_SEAD is not set
33# CONFIG_WR_PPMC is not set 31# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set 32# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_OCELOT is not set 33# CONFIG_MOMENCO_OCELOT is not set
36# CONFIG_MOMENCO_OCELOT_3 is not set
37# CONFIG_MOMENCO_OCELOT_C is not set
38# CONFIG_MIPS_XXS1500 is not set 34# CONFIG_MIPS_XXS1500 is not set
39# CONFIG_PNX8550_JBS is not set 35# CONFIG_PNX8550_JBS is not set
40# CONFIG_PNX8550_STB810 is not set 36# CONFIG_PNX8550_STB810 is not set
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index 41011f770a67..5dbb250f71c7 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20 3# Linux kernel version: 2.6.22-rc5
4# Tue Feb 20 21:47:39 2007 4# Fri Jun 22 21:39:45 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -9,40 +9,23 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set 12# CONFIG_LEMOTE_FULONG is not set
13# CONFIG_MIPS_BOSPORUS is not set 13# CONFIG_MACH_ALCHEMY is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set 14# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 16# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 17# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 18# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 19# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 20# CONFIG_MIPS_SEAD is not set
34# CONFIG_WR_PPMC is not set 21# CONFIG_WR_PPMC is not set
35# CONFIG_MIPS_SIM is not set 22# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 23# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 24# CONFIG_PNX8550_JBS is not set
43# CONFIG_PNX8550_STB810 is not set 25# CONFIG_PNX8550_STB810 is not set
44# CONFIG_DDB5477 is not set 26# CONFIG_DDB5477 is not set
45# CONFIG_MACH_VR41XX is not set 27# CONFIG_MACH_VR41XX is not set
28# CONFIG_PMC_MSP is not set
46# CONFIG_PMC_YOSEMITE is not set 29# CONFIG_PMC_YOSEMITE is not set
47# CONFIG_QEMU is not set 30# CONFIG_QEMU is not set
48# CONFIG_MARKEINS is not set 31# CONFIG_MARKEINS is not set
@@ -82,6 +65,8 @@ CONFIG_DMA_NONCOHERENT=y
82CONFIG_DMA_NEED_PCI_MAP_STATE=y 65CONFIG_DMA_NEED_PCI_MAP_STATE=y
83CONFIG_GENERIC_ISA_DMA=y 66CONFIG_GENERIC_ISA_DMA=y
84CONFIG_I8259=y 67CONFIG_I8259=y
68# CONFIG_NO_IOPORT is not set
69CONFIG_GENERIC_GPIO=y
85# CONFIG_CPU_BIG_ENDIAN is not set 70# CONFIG_CPU_BIG_ENDIAN is not set
86CONFIG_CPU_LITTLE_ENDIAN=y 71CONFIG_CPU_LITTLE_ENDIAN=y
87CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 72CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
@@ -93,6 +78,7 @@ CONFIG_HAVE_STD_PC_SERIAL_PORT=y
93# 78#
94# CPU selection 79# CPU selection
95# 80#
81# CONFIG_CPU_LOONGSON2 is not set
96# CONFIG_CPU_MIPS32_R1 is not set 82# CONFIG_CPU_MIPS32_R1 is not set
97# CONFIG_CPU_MIPS32_R2 is not set 83# CONFIG_CPU_MIPS32_R2 is not set
98# CONFIG_CPU_MIPS64_R1 is not set 84# CONFIG_CPU_MIPS64_R1 is not set
@@ -149,12 +135,12 @@ CONFIG_ZONE_DMA_FLAG=1
149# CONFIG_HZ_48 is not set 135# CONFIG_HZ_48 is not set
150# CONFIG_HZ_100 is not set 136# CONFIG_HZ_100 is not set
151# CONFIG_HZ_128 is not set 137# CONFIG_HZ_128 is not set
152# CONFIG_HZ_250 is not set 138CONFIG_HZ_250=y
153# CONFIG_HZ_256 is not set 139# CONFIG_HZ_256 is not set
154CONFIG_HZ_1000=y 140# CONFIG_HZ_1000 is not set
155# CONFIG_HZ_1024 is not set 141# CONFIG_HZ_1024 is not set
156CONFIG_SYS_SUPPORTS_ARBIT_HZ=y 142CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
157CONFIG_HZ=1000 143CONFIG_HZ=250
158CONFIG_PREEMPT_NONE=y 144CONFIG_PREEMPT_NONE=y
159# CONFIG_PREEMPT_VOLUNTARY is not set 145# CONFIG_PREEMPT_VOLUNTARY is not set
160# CONFIG_PREEMPT is not set 146# CONFIG_PREEMPT is not set
@@ -186,28 +172,35 @@ CONFIG_SYSVIPC_SYSCTL=y
186# CONFIG_AUDIT is not set 172# CONFIG_AUDIT is not set
187CONFIG_IKCONFIG=y 173CONFIG_IKCONFIG=y
188CONFIG_IKCONFIG_PROC=y 174CONFIG_IKCONFIG_PROC=y
175CONFIG_LOG_BUF_SHIFT=14
189CONFIG_SYSFS_DEPRECATED=y 176CONFIG_SYSFS_DEPRECATED=y
190CONFIG_RELAY=y 177# CONFIG_RELAY is not set
178CONFIG_BLK_DEV_INITRD=y
191CONFIG_INITRAMFS_SOURCE="" 179CONFIG_INITRAMFS_SOURCE=""
192# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 180CONFIG_CC_OPTIMIZE_FOR_SIZE=y
193CONFIG_SYSCTL=y 181CONFIG_SYSCTL=y
194CONFIG_EMBEDDED=y 182CONFIG_EMBEDDED=y
195CONFIG_SYSCTL_SYSCALL=y 183CONFIG_SYSCTL_SYSCALL=y
196CONFIG_KALLSYMS=y 184CONFIG_KALLSYMS=y
197# CONFIG_KALLSYMS_EXTRA_PASS is not set 185# CONFIG_KALLSYMS_EXTRA_PASS is not set
198CONFIG_HOTPLUG=y 186# CONFIG_HOTPLUG is not set
199CONFIG_PRINTK=y 187CONFIG_PRINTK=y
200CONFIG_BUG=y 188CONFIG_BUG=y
201CONFIG_ELF_CORE=y 189CONFIG_ELF_CORE=y
202CONFIG_BASE_FULL=y 190CONFIG_BASE_FULL=y
203# CONFIG_FUTEX is not set 191# CONFIG_FUTEX is not set
192CONFIG_ANON_INODES=y
204# CONFIG_EPOLL is not set 193# CONFIG_EPOLL is not set
194CONFIG_SIGNALFD=y
195CONFIG_TIMERFD=y
196CONFIG_EVENTFD=y
205CONFIG_SHMEM=y 197CONFIG_SHMEM=y
206CONFIG_SLAB=y
207CONFIG_VM_EVENT_COUNTERS=y 198CONFIG_VM_EVENT_COUNTERS=y
199CONFIG_SLAB=y
200# CONFIG_SLUB is not set
201# CONFIG_SLOB is not set
208# CONFIG_TINY_SHMEM is not set 202# CONFIG_TINY_SHMEM is not set
209CONFIG_BASE_SMALL=0 203CONFIG_BASE_SMALL=0
210# CONFIG_SLOB is not set
211 204
212# 205#
213# Loadable module support 206# Loadable module support
@@ -244,17 +237,12 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
244# 237#
245CONFIG_HW_HAS_PCI=y 238CONFIG_HW_HAS_PCI=y
246CONFIG_PCI=y 239CONFIG_PCI=y
240# CONFIG_ARCH_SUPPORTS_MSI is not set
247CONFIG_MMU=y 241CONFIG_MMU=y
248 242
249# 243#
250# PCCARD (PCMCIA/CardBus) support 244# PCCARD (PCMCIA/CardBus) support
251# 245#
252# CONFIG_PCCARD is not set
253
254#
255# PCI Hotplug Support
256#
257# CONFIG_HOTPLUG_PCI is not set
258 246
259# 247#
260# Executable file formats 248# Executable file formats
@@ -266,10 +254,7 @@ CONFIG_TRAD_SIGNALS=y
266# 254#
267# Power management options 255# Power management options
268# 256#
269CONFIG_PM=y 257# CONFIG_PM is not set
270# CONFIG_PM_LEGACY is not set
271# CONFIG_PM_DEBUG is not set
272# CONFIG_PM_SYSFS_DEPRECATED is not set
273 258
274# 259#
275# Networking 260# Networking
@@ -279,14 +264,9 @@ CONFIG_NET=y
279# 264#
280# Networking options 265# Networking options
281# 266#
282# CONFIG_NETDEBUG is not set
283CONFIG_PACKET=y 267CONFIG_PACKET=y
284# CONFIG_PACKET_MMAP is not set 268# CONFIG_PACKET_MMAP is not set
285CONFIG_UNIX=y 269CONFIG_UNIX=y
286CONFIG_XFRM=y
287# CONFIG_XFRM_USER is not set
288# CONFIG_XFRM_SUB_POLICY is not set
289CONFIG_XFRM_MIGRATE=y
290# CONFIG_NET_KEY is not set 270# CONFIG_NET_KEY is not set
291CONFIG_INET=y 271CONFIG_INET=y
292CONFIG_IP_MULTICAST=y 272CONFIG_IP_MULTICAST=y
@@ -294,7 +274,7 @@ CONFIG_IP_MULTICAST=y
294CONFIG_IP_FIB_HASH=y 274CONFIG_IP_FIB_HASH=y
295CONFIG_IP_PNP=y 275CONFIG_IP_PNP=y
296# CONFIG_IP_PNP_DHCP is not set 276# CONFIG_IP_PNP_DHCP is not set
297CONFIG_IP_PNP_BOOTP=y 277# CONFIG_IP_PNP_BOOTP is not set
298# CONFIG_IP_PNP_RARP is not set 278# CONFIG_IP_PNP_RARP is not set
299# CONFIG_NET_IPIP is not set 279# CONFIG_NET_IPIP is not set
300# CONFIG_NET_IPGRE is not set 280# CONFIG_NET_IPGRE is not set
@@ -305,130 +285,23 @@ CONFIG_IP_PNP_BOOTP=y
305# CONFIG_INET_ESP is not set 285# CONFIG_INET_ESP is not set
306# CONFIG_INET_IPCOMP is not set 286# CONFIG_INET_IPCOMP is not set
307# CONFIG_INET_XFRM_TUNNEL is not set 287# CONFIG_INET_XFRM_TUNNEL is not set
308CONFIG_INET_TUNNEL=m 288# CONFIG_INET_TUNNEL is not set
309CONFIG_INET_XFRM_MODE_TRANSPORT=m 289# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
310CONFIG_INET_XFRM_MODE_TUNNEL=m 290# CONFIG_INET_XFRM_MODE_TUNNEL is not set
311CONFIG_INET_XFRM_MODE_BEET=m 291# CONFIG_INET_XFRM_MODE_BEET is not set
312CONFIG_INET_DIAG=y 292CONFIG_INET_DIAG=y
313CONFIG_INET_TCP_DIAG=y 293CONFIG_INET_TCP_DIAG=y
314# CONFIG_TCP_CONG_ADVANCED is not set 294# CONFIG_TCP_CONG_ADVANCED is not set
315CONFIG_TCP_CONG_CUBIC=y 295CONFIG_TCP_CONG_CUBIC=y
316CONFIG_DEFAULT_TCP_CONG="cubic" 296CONFIG_DEFAULT_TCP_CONG="cubic"
317CONFIG_TCP_MD5SIG=y 297# CONFIG_TCP_MD5SIG is not set
318 298# CONFIG_IPV6 is not set
319#
320# IP: Virtual Server Configuration
321#
322# CONFIG_IP_VS is not set
323CONFIG_IPV6=m
324# CONFIG_IPV6_PRIVACY is not set
325CONFIG_IPV6_ROUTER_PREF=y
326CONFIG_IPV6_ROUTE_INFO=y
327# CONFIG_INET6_AH is not set
328# CONFIG_INET6_ESP is not set
329# CONFIG_INET6_IPCOMP is not set
330CONFIG_IPV6_MIP6=y
331# CONFIG_INET6_XFRM_TUNNEL is not set 299# CONFIG_INET6_XFRM_TUNNEL is not set
332# CONFIG_INET6_TUNNEL is not set 300# CONFIG_INET6_TUNNEL is not set
333CONFIG_INET6_XFRM_MODE_TRANSPORT=m 301# CONFIG_NETWORK_SECMARK is not set
334CONFIG_INET6_XFRM_MODE_TUNNEL=m 302# CONFIG_NETFILTER is not set
335CONFIG_INET6_XFRM_MODE_BEET=m
336CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
337CONFIG_IPV6_SIT=m
338# CONFIG_IPV6_TUNNEL is not set
339CONFIG_IPV6_MULTIPLE_TABLES=y
340CONFIG_IPV6_SUBTREES=y
341CONFIG_NETWORK_SECMARK=y
342CONFIG_NETFILTER=y
343# CONFIG_NETFILTER_DEBUG is not set
344
345#
346# Core Netfilter Configuration
347#
348CONFIG_NETFILTER_NETLINK=m
349CONFIG_NETFILTER_NETLINK_QUEUE=m
350CONFIG_NETFILTER_NETLINK_LOG=m
351CONFIG_NF_CONNTRACK_ENABLED=m
352CONFIG_NF_CONNTRACK_SUPPORT=y
353# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
354CONFIG_NF_CONNTRACK=m
355CONFIG_NF_CT_ACCT=y
356CONFIG_NF_CONNTRACK_MARK=y
357CONFIG_NF_CONNTRACK_SECMARK=y
358CONFIG_NF_CONNTRACK_EVENTS=y
359CONFIG_NF_CT_PROTO_GRE=m
360CONFIG_NF_CT_PROTO_SCTP=m
361CONFIG_NF_CONNTRACK_AMANDA=m
362CONFIG_NF_CONNTRACK_FTP=m
363CONFIG_NF_CONNTRACK_H323=m
364CONFIG_NF_CONNTRACK_IRC=m
365# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
366CONFIG_NF_CONNTRACK_PPTP=m
367CONFIG_NF_CONNTRACK_SANE=m
368CONFIG_NF_CONNTRACK_SIP=m
369CONFIG_NF_CONNTRACK_TFTP=m
370CONFIG_NF_CT_NETLINK=m
371CONFIG_NETFILTER_XTABLES=m
372CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
373CONFIG_NETFILTER_XT_TARGET_MARK=m
374CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
375CONFIG_NETFILTER_XT_TARGET_NFLOG=m
376CONFIG_NETFILTER_XT_TARGET_SECMARK=m
377CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
378CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
379CONFIG_NETFILTER_XT_MATCH_COMMENT=m
380CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
381CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
382CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
383CONFIG_NETFILTER_XT_MATCH_DCCP=m
384CONFIG_NETFILTER_XT_MATCH_DSCP=m
385CONFIG_NETFILTER_XT_MATCH_ESP=m
386CONFIG_NETFILTER_XT_MATCH_HELPER=m
387CONFIG_NETFILTER_XT_MATCH_LENGTH=m
388CONFIG_NETFILTER_XT_MATCH_LIMIT=m
389CONFIG_NETFILTER_XT_MATCH_MAC=m
390CONFIG_NETFILTER_XT_MATCH_MARK=m
391# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
392CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
393CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
394CONFIG_NETFILTER_XT_MATCH_QUOTA=m
395CONFIG_NETFILTER_XT_MATCH_REALM=m
396CONFIG_NETFILTER_XT_MATCH_SCTP=m
397CONFIG_NETFILTER_XT_MATCH_STATE=m
398CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
399CONFIG_NETFILTER_XT_MATCH_STRING=m
400CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
401CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
402
403#
404# IP: Netfilter Configuration
405#
406CONFIG_NF_CONNTRACK_IPV4=m
407CONFIG_NF_CONNTRACK_PROC_COMPAT=y
408# CONFIG_IP_NF_QUEUE is not set
409# CONFIG_IP_NF_IPTABLES is not set
410# CONFIG_IP_NF_ARPTABLES is not set
411
412#
413# IPv6: Netfilter Configuration (EXPERIMENTAL)
414#
415CONFIG_NF_CONNTRACK_IPV6=m
416# CONFIG_IP6_NF_QUEUE is not set
417# CONFIG_IP6_NF_IPTABLES is not set
418
419#
420# DCCP Configuration (EXPERIMENTAL)
421#
422# CONFIG_IP_DCCP is not set 303# CONFIG_IP_DCCP is not set
423
424#
425# SCTP Configuration (EXPERIMENTAL)
426#
427# CONFIG_IP_SCTP is not set 304# CONFIG_IP_SCTP is not set
428
429#
430# TIPC Configuration (EXPERIMENTAL)
431#
432# CONFIG_TIPC is not set 305# CONFIG_TIPC is not set
433# CONFIG_ATM is not set 306# CONFIG_ATM is not set
434# CONFIG_BRIDGE is not set 307# CONFIG_BRIDGE is not set
@@ -446,7 +319,6 @@ CONFIG_NF_CONNTRACK_IPV6=m
446# QoS and/or fair queueing 319# QoS and/or fair queueing
447# 320#
448# CONFIG_NET_SCHED is not set 321# CONFIG_NET_SCHED is not set
449CONFIG_NET_CLS_ROUTE=y
450 322
451# 323#
452# Network testing 324# Network testing
@@ -455,15 +327,16 @@ CONFIG_NET_CLS_ROUTE=y
455# CONFIG_HAMRADIO is not set 327# CONFIG_HAMRADIO is not set
456# CONFIG_IRDA is not set 328# CONFIG_IRDA is not set
457# CONFIG_BT is not set 329# CONFIG_BT is not set
458CONFIG_IEEE80211=m 330# CONFIG_AF_RXRPC is not set
459# CONFIG_IEEE80211_DEBUG is not set 331
460CONFIG_IEEE80211_CRYPT_WEP=m 332#
461CONFIG_IEEE80211_CRYPT_CCMP=m 333# Wireless
462CONFIG_IEEE80211_CRYPT_TKIP=m 334#
463CONFIG_IEEE80211_SOFTMAC=m 335# CONFIG_CFG80211 is not set
464# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set 336# CONFIG_WIRELESS_EXT is not set
465CONFIG_WIRELESS_EXT=y 337# CONFIG_MAC80211 is not set
466CONFIG_FIB_RULES=y 338# CONFIG_IEEE80211 is not set
339# CONFIG_RFKILL is not set
467 340
468# 341#
469# Device Drivers 342# Device Drivers
@@ -474,94 +347,13 @@ CONFIG_FIB_RULES=y
474# 347#
475CONFIG_STANDALONE=y 348CONFIG_STANDALONE=y
476CONFIG_PREVENT_FIRMWARE_BUILD=y 349CONFIG_PREVENT_FIRMWARE_BUILD=y
477CONFIG_FW_LOADER=m
478# CONFIG_SYS_HYPERVISOR is not set 350# CONFIG_SYS_HYPERVISOR is not set
479 351
480# 352#
481# Connector - unified userspace <-> kernelspace linker 353# Connector - unified userspace <-> kernelspace linker
482# 354#
483CONFIG_CONNECTOR=m 355# CONFIG_CONNECTOR is not set
484 356# CONFIG_MTD is not set
485#
486# Memory Technology Devices (MTD)
487#
488CONFIG_MTD=y
489# CONFIG_MTD_DEBUG is not set
490# CONFIG_MTD_CONCAT is not set
491CONFIG_MTD_PARTITIONS=y
492# CONFIG_MTD_REDBOOT_PARTS is not set
493# CONFIG_MTD_CMDLINE_PARTS is not set
494
495#
496# User Modules And Translation Layers
497#
498CONFIG_MTD_CHAR=y
499CONFIG_MTD_BLKDEVS=y
500CONFIG_MTD_BLOCK=y
501# CONFIG_FTL is not set
502# CONFIG_NFTL is not set
503# CONFIG_INFTL is not set
504# CONFIG_RFD_FTL is not set
505# CONFIG_SSFDC is not set
506
507#
508# RAM/ROM/Flash chip drivers
509#
510CONFIG_MTD_CFI=y
511# CONFIG_MTD_JEDECPROBE is not set
512CONFIG_MTD_GEN_PROBE=y
513# CONFIG_MTD_CFI_ADV_OPTIONS is not set
514CONFIG_MTD_MAP_BANK_WIDTH_1=y
515CONFIG_MTD_MAP_BANK_WIDTH_2=y
516CONFIG_MTD_MAP_BANK_WIDTH_4=y
517# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
518# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
519# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
520CONFIG_MTD_CFI_I1=y
521CONFIG_MTD_CFI_I2=y
522# CONFIG_MTD_CFI_I4 is not set
523# CONFIG_MTD_CFI_I8 is not set
524CONFIG_MTD_CFI_INTELEXT=y
525CONFIG_MTD_CFI_AMDSTD=y
526# CONFIG_MTD_CFI_STAA is not set
527CONFIG_MTD_CFI_UTIL=y
528# CONFIG_MTD_RAM is not set
529# CONFIG_MTD_ROM is not set
530# CONFIG_MTD_ABSENT is not set
531# CONFIG_MTD_OBSOLETE_CHIPS is not set
532
533#
534# Mapping drivers for chip access
535#
536# CONFIG_MTD_COMPLEX_MAPPINGS is not set
537# CONFIG_MTD_PHYSMAP is not set
538# CONFIG_MTD_PLATRAM is not set
539
540#
541# Self-contained MTD device drivers
542#
543# CONFIG_MTD_PMC551 is not set
544# CONFIG_MTD_SLRAM is not set
545# CONFIG_MTD_PHRAM is not set
546# CONFIG_MTD_MTDRAM is not set
547# CONFIG_MTD_BLOCK2MTD is not set
548
549#
550# Disk-On-Chip Device Drivers
551#
552# CONFIG_MTD_DOC2000 is not set
553# CONFIG_MTD_DOC2001 is not set
554# CONFIG_MTD_DOC2001PLUS is not set
555
556#
557# NAND Flash Device Drivers
558#
559# CONFIG_MTD_NAND is not set
560
561#
562# OneNAND Flash Device Drivers
563#
564# CONFIG_MTD_ONENAND is not set
565 357
566# 358#
567# Parallel port support 359# Parallel port support
@@ -583,93 +375,30 @@ CONFIG_MTD_CFI_UTIL=y
583# CONFIG_BLK_DEV_COW_COMMON is not set 375# CONFIG_BLK_DEV_COW_COMMON is not set
584CONFIG_BLK_DEV_LOOP=y 376CONFIG_BLK_DEV_LOOP=y
585# CONFIG_BLK_DEV_CRYPTOLOOP is not set 377# CONFIG_BLK_DEV_CRYPTOLOOP is not set
586CONFIG_BLK_DEV_NBD=m 378# CONFIG_BLK_DEV_NBD is not set
587# CONFIG_BLK_DEV_SX8 is not set 379# CONFIG_BLK_DEV_SX8 is not set
588# CONFIG_BLK_DEV_UB is not set
589CONFIG_BLK_DEV_RAM=y 380CONFIG_BLK_DEV_RAM=y
590CONFIG_BLK_DEV_RAM_COUNT=16 381CONFIG_BLK_DEV_RAM_COUNT=16
591CONFIG_BLK_DEV_RAM_SIZE=8192 382CONFIG_BLK_DEV_RAM_SIZE=8192
592CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 383CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
593CONFIG_BLK_DEV_INITRD=y
594# CONFIG_CDROM_PKTCDVD is not set 384# CONFIG_CDROM_PKTCDVD is not set
595# CONFIG_ATA_OVER_ETH is not set 385# CONFIG_ATA_OVER_ETH is not set
596 386
597# 387#
598# Misc devices 388# Misc devices
599# 389#
600CONFIG_SGI_IOC4=m 390# CONFIG_PHANTOM is not set
391# CONFIG_SGI_IOC4 is not set
601# CONFIG_TIFM_CORE is not set 392# CONFIG_TIFM_CORE is not set
602 393# CONFIG_BLINK is not set
603# 394# CONFIG_IDE is not set
604# ATA/ATAPI/MFM/RLL support
605#
606CONFIG_IDE=y
607CONFIG_IDE_MAX_HWIFS=4
608CONFIG_BLK_DEV_IDE=y
609
610#
611# Please see Documentation/ide.txt for help/info on IDE drives
612#
613# CONFIG_BLK_DEV_IDE_SATA is not set
614CONFIG_BLK_DEV_IDEDISK=y
615# CONFIG_IDEDISK_MULTI_MODE is not set
616CONFIG_BLK_DEV_IDECD=y
617# CONFIG_BLK_DEV_IDETAPE is not set
618# CONFIG_BLK_DEV_IDEFLOPPY is not set
619# CONFIG_IDE_TASK_IOCTL is not set
620
621#
622# IDE chipset support/bugfixes
623#
624CONFIG_IDE_GENERIC=y
625CONFIG_BLK_DEV_IDEPCI=y
626CONFIG_IDEPCI_SHARE_IRQ=y
627# CONFIG_BLK_DEV_OFFBOARD is not set
628# CONFIG_BLK_DEV_GENERIC is not set
629# CONFIG_BLK_DEV_OPTI621 is not set
630CONFIG_BLK_DEV_IDEDMA_PCI=y
631# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
632# CONFIG_IDEDMA_PCI_AUTO is not set
633# CONFIG_BLK_DEV_AEC62XX is not set
634# CONFIG_BLK_DEV_ALI15X3 is not set
635# CONFIG_BLK_DEV_AMD74XX is not set
636# CONFIG_BLK_DEV_CMD64X is not set
637# CONFIG_BLK_DEV_TRIFLEX is not set
638# CONFIG_BLK_DEV_CY82C693 is not set
639# CONFIG_BLK_DEV_CS5520 is not set
640# CONFIG_BLK_DEV_CS5530 is not set
641# CONFIG_BLK_DEV_HPT34X is not set
642# CONFIG_BLK_DEV_HPT366 is not set
643# CONFIG_BLK_DEV_JMICRON is not set
644# CONFIG_BLK_DEV_SC1200 is not set
645# CONFIG_BLK_DEV_PIIX is not set
646CONFIG_BLK_DEV_IT8213=m
647# CONFIG_BLK_DEV_IT821X is not set
648# CONFIG_BLK_DEV_NS87415 is not set
649# CONFIG_BLK_DEV_PDC202XX_OLD is not set
650# CONFIG_BLK_DEV_PDC202XX_NEW is not set
651# CONFIG_BLK_DEV_SVWKS is not set
652# CONFIG_BLK_DEV_SIIMAGE is not set
653# CONFIG_BLK_DEV_SLC90E66 is not set
654# CONFIG_BLK_DEV_TRM290 is not set
655# CONFIG_BLK_DEV_VIA82CXXX is not set
656CONFIG_BLK_DEV_TC86C001=m
657# CONFIG_IDE_ARM is not set
658CONFIG_BLK_DEV_IDEDMA=y
659# CONFIG_IDEDMA_IVB is not set
660# CONFIG_IDEDMA_AUTO is not set
661# CONFIG_BLK_DEV_HD is not set
662 395
663# 396#
664# SCSI device support 397# SCSI device support
665# 398#
666CONFIG_RAID_ATTRS=m 399# CONFIG_RAID_ATTRS is not set
667# CONFIG_SCSI is not set 400# CONFIG_SCSI is not set
668# CONFIG_SCSI_NETLINK is not set 401# CONFIG_SCSI_NETLINK is not set
669
670#
671# Serial ATA (prod) and Parallel ATA (experimental) drivers
672#
673# CONFIG_ATA is not set 402# CONFIG_ATA is not set
674 403
675# 404#
@@ -685,6 +414,7 @@ CONFIG_RAID_ATTRS=m
685# 414#
686# IEEE 1394 (FireWire) support 415# IEEE 1394 (FireWire) support
687# 416#
417# CONFIG_FIREWIRE is not set
688# CONFIG_IEEE1394 is not set 418# CONFIG_IEEE1394 is not set
689 419
690# 420#
@@ -699,36 +429,15 @@ CONFIG_NETDEVICES=y
699# CONFIG_DUMMY is not set 429# CONFIG_DUMMY is not set
700# CONFIG_BONDING is not set 430# CONFIG_BONDING is not set
701# CONFIG_EQUALIZER is not set 431# CONFIG_EQUALIZER is not set
702CONFIG_TUN=m 432# CONFIG_TUN is not set
703
704#
705# ARCnet devices
706#
707# CONFIG_ARCNET is not set 433# CONFIG_ARCNET is not set
708 434# CONFIG_PHYLIB is not set
709#
710# PHY device support
711#
712CONFIG_PHYLIB=m
713
714#
715# MII PHY device drivers
716#
717CONFIG_MARVELL_PHY=m
718CONFIG_DAVICOM_PHY=m
719CONFIG_QSEMI_PHY=m
720CONFIG_LXT_PHY=m
721CONFIG_CICADA_PHY=m
722CONFIG_VITESSE_PHY=m
723CONFIG_SMSC_PHY=m
724# CONFIG_BROADCOM_PHY is not set
725# CONFIG_FIXED_PHY is not set
726 435
727# 436#
728# Ethernet (10 or 100Mbit) 437# Ethernet (10 or 100Mbit)
729# 438#
730CONFIG_NET_ETHERNET=y 439CONFIG_NET_ETHERNET=y
731# CONFIG_MII is not set 440CONFIG_MII=y
732# CONFIG_HAPPYMEAL is not set 441# CONFIG_HAPPYMEAL is not set
733# CONFIG_SUNGEM is not set 442# CONFIG_SUNGEM is not set
734# CONFIG_CASSINI is not set 443# CONFIG_CASSINI is not set
@@ -747,6 +456,7 @@ CONFIG_NET_PCI=y
747# CONFIG_ADAPTEC_STARFIRE is not set 456# CONFIG_ADAPTEC_STARFIRE is not set
748# CONFIG_B44 is not set 457# CONFIG_B44 is not set
749# CONFIG_FORCEDETH is not set 458# CONFIG_FORCEDETH is not set
459CONFIG_TC35815=y
750# CONFIG_DGRS is not set 460# CONFIG_DGRS is not set
751# CONFIG_EEPRO100 is not set 461# CONFIG_EEPRO100 is not set
752# CONFIG_E100 is not set 462# CONFIG_E100 is not set
@@ -761,91 +471,20 @@ CONFIG_NET_PCI=y
761# CONFIG_TLAN is not set 471# CONFIG_TLAN is not set
762# CONFIG_VIA_RHINE is not set 472# CONFIG_VIA_RHINE is not set
763# CONFIG_SC92031 is not set 473# CONFIG_SC92031 is not set
764 474# CONFIG_NETDEV_1000 is not set
765# 475# CONFIG_NETDEV_10000 is not set
766# Ethernet (1000 Mbit)
767#
768# CONFIG_ACENIC is not set
769# CONFIG_DL2K is not set
770# CONFIG_E1000 is not set
771# CONFIG_NS83820 is not set
772# CONFIG_HAMACHI is not set
773# CONFIG_YELLOWFIN is not set
774# CONFIG_R8169 is not set
775# CONFIG_SIS190 is not set
776# CONFIG_SKGE is not set
777# CONFIG_SKY2 is not set
778# CONFIG_SK98LIN is not set
779# CONFIG_VIA_VELOCITY is not set
780# CONFIG_TIGON3 is not set
781# CONFIG_BNX2 is not set
782CONFIG_QLA3XXX=m
783# CONFIG_ATL1 is not set
784
785#
786# Ethernet (10000 Mbit)
787#
788# CONFIG_CHELSIO_T1 is not set
789CONFIG_CHELSIO_T3=m
790# CONFIG_IXGB is not set
791# CONFIG_S2IO is not set
792# CONFIG_MYRI10GE is not set
793CONFIG_NETXEN_NIC=m
794
795#
796# Token Ring devices
797#
798# CONFIG_TR is not set 476# CONFIG_TR is not set
799 477
800# 478#
801# Wireless LAN (non-hamradio) 479# Wireless LAN
802#
803CONFIG_NET_RADIO=y
804# CONFIG_NET_WIRELESS_RTNETLINK is not set
805
806#
807# Obsolete Wireless cards support (pre-802.11)
808#
809# CONFIG_STRIP is not set
810
811#
812# Wireless 802.11b ISA/PCI cards support
813#
814# CONFIG_IPW2100 is not set
815CONFIG_IPW2200=m
816# CONFIG_IPW2200_MONITOR is not set
817# CONFIG_IPW2200_QOS is not set
818# CONFIG_IPW2200_DEBUG is not set
819# CONFIG_HERMES is not set
820# CONFIG_ATMEL is not set
821
822#
823# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
824#
825# CONFIG_PRISM54 is not set
826# CONFIG_USB_ZD1201 is not set
827# CONFIG_HOSTAP is not set
828# CONFIG_BCM43XX is not set
829# CONFIG_ZD1211RW is not set
830CONFIG_NET_WIRELESS=y
831
832#
833# Wan interfaces
834# 480#
481# CONFIG_WLAN_PRE80211 is not set
482# CONFIG_WLAN_80211 is not set
835# CONFIG_WAN is not set 483# CONFIG_WAN is not set
836# CONFIG_FDDI is not set 484# CONFIG_FDDI is not set
837# CONFIG_HIPPI is not set 485# CONFIG_HIPPI is not set
838CONFIG_PPP=m 486# CONFIG_PPP is not set
839CONFIG_PPP_MULTILINK=y
840# CONFIG_PPP_FILTER is not set
841CONFIG_PPP_ASYNC=m
842CONFIG_PPP_SYNC_TTY=m
843CONFIG_PPP_DEFLATE=m
844# CONFIG_PPP_BSDCOMP is not set
845CONFIG_PPP_MPPE=m
846CONFIG_PPPOE=m
847# CONFIG_SLIP is not set 487# CONFIG_SLIP is not set
848CONFIG_SLHC=m
849# CONFIG_SHAPER is not set 488# CONFIG_SHAPER is not set
850# CONFIG_NETCONSOLE is not set 489# CONFIG_NETCONSOLE is not set
851# CONFIG_NETPOLL is not set 490# CONFIG_NETPOLL is not set
@@ -864,57 +503,18 @@ CONFIG_SLHC=m
864# 503#
865# Input device support 504# Input device support
866# 505#
867CONFIG_INPUT=y 506# CONFIG_INPUT is not set
868# CONFIG_INPUT_FF_MEMLESS is not set
869
870#
871# Userland interfaces
872#
873CONFIG_INPUT_MOUSEDEV=y
874CONFIG_INPUT_MOUSEDEV_PSAUX=y
875CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
876CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
877# CONFIG_INPUT_JOYDEV is not set
878# CONFIG_INPUT_TSDEV is not set
879CONFIG_INPUT_EVDEV=y
880# CONFIG_INPUT_EVBUG is not set
881
882#
883# Input Device Drivers
884#
885CONFIG_INPUT_KEYBOARD=y
886CONFIG_KEYBOARD_ATKBD=y
887# CONFIG_KEYBOARD_SUNKBD is not set
888# CONFIG_KEYBOARD_LKKBD is not set
889# CONFIG_KEYBOARD_XTKBD is not set
890# CONFIG_KEYBOARD_NEWTON is not set
891# CONFIG_KEYBOARD_STOWAWAY is not set
892CONFIG_INPUT_MOUSE=y
893CONFIG_MOUSE_PS2=y
894# CONFIG_MOUSE_SERIAL is not set
895# CONFIG_MOUSE_VSXXXAA is not set
896# CONFIG_INPUT_JOYSTICK is not set
897# CONFIG_INPUT_TOUCHSCREEN is not set
898# CONFIG_INPUT_MISC is not set
899 507
900# 508#
901# Hardware I/O ports 509# Hardware I/O ports
902# 510#
903CONFIG_SERIO=y 511# CONFIG_SERIO is not set
904CONFIG_SERIO_I8042=y
905CONFIG_SERIO_SERPORT=y
906# CONFIG_SERIO_PCIPS2 is not set
907CONFIG_SERIO_LIBPS2=y
908# CONFIG_SERIO_RAW is not set
909# CONFIG_GAMEPORT is not set 512# CONFIG_GAMEPORT is not set
910 513
911# 514#
912# Character devices 515# Character devices
913# 516#
914CONFIG_VT=y 517# CONFIG_VT is not set
915CONFIG_VT_CONSOLE=y
916CONFIG_HW_CONSOLE=y
917CONFIG_VT_HW_CONSOLE_BINDING=y
918# CONFIG_SERIAL_NONSTANDARD is not set 518# CONFIG_SERIAL_NONSTANDARD is not set
919 519
920# 520#
@@ -926,11 +526,12 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
926# Non-8250 serial port support 526# Non-8250 serial port support
927# 527#
928CONFIG_SERIAL_CORE=y 528CONFIG_SERIAL_CORE=y
529CONFIG_SERIAL_CORE_CONSOLE=y
929CONFIG_SERIAL_TXX9=y 530CONFIG_SERIAL_TXX9=y
930CONFIG_HAS_TXX9_SERIAL=y 531CONFIG_HAS_TXX9_SERIAL=y
931CONFIG_SERIAL_TXX9_NR_UARTS=6 532CONFIG_SERIAL_TXX9_NR_UARTS=6
932# CONFIG_SERIAL_TXX9_CONSOLE is not set 533CONFIG_SERIAL_TXX9_CONSOLE=y
933# CONFIG_SERIAL_TXX9_STDSERIAL is not set 534CONFIG_SERIAL_TXX9_STDSERIAL=y
934# CONFIG_SERIAL_JSM is not set 535# CONFIG_SERIAL_JSM is not set
935CONFIG_UNIX98_PTYS=y 536CONFIG_UNIX98_PTYS=y
936CONFIG_LEGACY_PTYS=y 537CONFIG_LEGACY_PTYS=y
@@ -940,15 +541,10 @@ CONFIG_LEGACY_PTY_COUNT=256
940# IPMI 541# IPMI
941# 542#
942# CONFIG_IPMI_HANDLER is not set 543# CONFIG_IPMI_HANDLER is not set
943
944#
945# Watchdog Cards
946#
947# CONFIG_WATCHDOG is not set 544# CONFIG_WATCHDOG is not set
948# CONFIG_HW_RANDOM is not set 545# CONFIG_HW_RANDOM is not set
949# CONFIG_RTC is not set 546# CONFIG_RTC is not set
950# CONFIG_GEN_RTC is not set 547# CONFIG_GEN_RTC is not set
951# CONFIG_DTLK is not set
952# CONFIG_R3964 is not set 548# CONFIG_R3964 is not set
953# CONFIG_APPLICOM is not set 549# CONFIG_APPLICOM is not set
954# CONFIG_DRM is not set 550# CONFIG_DRM is not set
@@ -958,108 +554,61 @@ CONFIG_LEGACY_PTY_COUNT=256
958# TPM devices 554# TPM devices
959# 555#
960# CONFIG_TCG_TPM is not set 556# CONFIG_TCG_TPM is not set
557CONFIG_DEVPORT=y
558# CONFIG_I2C is not set
559
560#
561# SPI support
562#
563CONFIG_SPI=y
564CONFIG_SPI_MASTER=y
961 565
962# 566#
963# I2C support 567# SPI Master Controller Drivers
964# 568#
965# CONFIG_I2C is not set 569# CONFIG_SPI_BITBANG is not set
570CONFIG_SPI_TXX9=y
966 571
967# 572#
968# SPI support 573# SPI Protocol Masters
969# 574#
970# CONFIG_SPI is not set 575CONFIG_SPI_AT25=y
971# CONFIG_SPI_MASTER is not set 576# CONFIG_SPI_SPIDEV is not set
972 577
973# 578#
974# Dallas's 1-wire bus 579# Dallas's 1-wire bus
975# 580#
976# CONFIG_W1 is not set 581# CONFIG_W1 is not set
582# CONFIG_HWMON is not set
977 583
978# 584#
979# Hardware Monitoring support 585# Multifunction device drivers
980# 586#
981CONFIG_HWMON=y 587# CONFIG_MFD_SM501 is not set
982# CONFIG_HWMON_VID is not set
983# CONFIG_SENSORS_ABITUGURU is not set
984# CONFIG_SENSORS_F71805F is not set
985# CONFIG_SENSORS_PC87427 is not set
986# CONFIG_SENSORS_VT1211 is not set
987# CONFIG_HWMON_DEBUG_CHIP is not set
988 588
989# 589#
990# Multimedia devices 590# Multimedia devices
991# 591#
992# CONFIG_VIDEO_DEV is not set 592# CONFIG_VIDEO_DEV is not set
993 593# CONFIG_DVB_CORE is not set
994# 594# CONFIG_DAB is not set
995# Digital Video Broadcasting Devices
996#
997# CONFIG_DVB is not set
998# CONFIG_USB_DABUSB is not set
999 595
1000# 596#
1001# Graphics support 597# Graphics support
1002# 598#
1003# CONFIG_FIRMWARE_EDID is not set
1004CONFIG_FB=y
1005CONFIG_FB_CFB_FILLRECT=y
1006CONFIG_FB_CFB_COPYAREA=y
1007CONFIG_FB_CFB_IMAGEBLIT=y
1008# CONFIG_FB_SVGALIB is not set
1009# CONFIG_FB_MACMODES is not set
1010# CONFIG_FB_BACKLIGHT is not set
1011# CONFIG_FB_MODE_HELPERS is not set
1012# CONFIG_FB_TILEBLITTING is not set
1013# CONFIG_FB_CIRRUS is not set
1014# CONFIG_FB_PM2 is not set
1015# CONFIG_FB_CYBER2000 is not set
1016# CONFIG_FB_ASILIANT is not set
1017# CONFIG_FB_IMSTT is not set
1018# CONFIG_FB_S1D13XXX is not set
1019# CONFIG_FB_NVIDIA is not set
1020# CONFIG_FB_RIVA is not set
1021# CONFIG_FB_MATROX is not set
1022# CONFIG_FB_RADEON is not set
1023# CONFIG_FB_ATY128 is not set
1024CONFIG_FB_ATY=y
1025CONFIG_FB_ATY_CT=y
1026# CONFIG_FB_ATY_GENERIC_LCD is not set
1027# CONFIG_FB_ATY_GX is not set
1028# CONFIG_FB_S3 is not set
1029# CONFIG_FB_SAVAGE is not set
1030# CONFIG_FB_SIS is not set
1031# CONFIG_FB_NEOMAGIC is not set
1032# CONFIG_FB_KYRO is not set
1033# CONFIG_FB_3DFX is not set
1034# CONFIG_FB_VOODOO1 is not set
1035# CONFIG_FB_SMIVGX is not set
1036# CONFIG_FB_TRIDENT is not set
1037# CONFIG_FB_VIRTUAL is not set
1038
1039#
1040# Console display driver support
1041#
1042CONFIG_VGA_CONSOLE=y
1043# CONFIG_VGACON_SOFT_SCROLLBACK is not set
1044CONFIG_DUMMY_CONSOLE=y
1045# CONFIG_FRAMEBUFFER_CONSOLE is not set
1046
1047#
1048# Logo configuration
1049#
1050# CONFIG_LOGO is not set
1051# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 599# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1052 600
1053# 601#
1054# Sound 602# Display device support
1055# 603#
1056# CONFIG_SOUND is not set 604# CONFIG_DISPLAY_SUPPORT is not set
605# CONFIG_VGASTATE is not set
606# CONFIG_FB is not set
1057 607
1058# 608#
1059# HID Devices 609# Sound
1060# 610#
1061CONFIG_HID=y 611# CONFIG_SOUND is not set
1062# CONFIG_HID_DEBUG is not set
1063 612
1064# 613#
1065# USB support 614# USB support
@@ -1067,148 +616,80 @@ CONFIG_HID=y
1067CONFIG_USB_ARCH_HAS_HCD=y 616CONFIG_USB_ARCH_HAS_HCD=y
1068CONFIG_USB_ARCH_HAS_OHCI=y 617CONFIG_USB_ARCH_HAS_OHCI=y
1069CONFIG_USB_ARCH_HAS_EHCI=y 618CONFIG_USB_ARCH_HAS_EHCI=y
1070CONFIG_USB=y 619# CONFIG_USB is not set
1071# CONFIG_USB_DEBUG is not set
1072
1073#
1074# Miscellaneous USB options
1075#
1076# CONFIG_USB_DEVICEFS is not set
1077# CONFIG_USB_DYNAMIC_MINORS is not set
1078# CONFIG_USB_SUSPEND is not set
1079# CONFIG_USB_OTG is not set
1080
1081#
1082# USB Host Controller Drivers
1083#
1084# CONFIG_USB_EHCI_HCD is not set
1085# CONFIG_USB_ISP116X_HCD is not set
1086# CONFIG_USB_OHCI_HCD is not set
1087# CONFIG_USB_UHCI_HCD is not set
1088# CONFIG_USB_SL811_HCD is not set
1089
1090#
1091# USB Device Class drivers
1092#
1093# CONFIG_USB_ACM is not set
1094# CONFIG_USB_PRINTER is not set
1095 620
1096# 621#
1097# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 622# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1098# 623#
1099 624
1100# 625#
1101# may also be needed; see USB_STORAGE Help for more information 626# USB Gadget Support
1102#
1103# CONFIG_USB_LIBUSUAL is not set
1104
1105#
1106# USB Input Devices
1107#
1108CONFIG_USB_HID=y
1109# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1110# CONFIG_HID_FF is not set
1111CONFIG_USB_HIDDEV=y
1112# CONFIG_USB_AIPTEK is not set
1113# CONFIG_USB_WACOM is not set
1114# CONFIG_USB_ACECAD is not set
1115# CONFIG_USB_KBTAB is not set
1116# CONFIG_USB_POWERMATE is not set
1117# CONFIG_USB_TOUCHSCREEN is not set
1118CONFIG_USB_YEALINK=m
1119# CONFIG_USB_XPAD is not set
1120# CONFIG_USB_ATI_REMOTE is not set
1121# CONFIG_USB_ATI_REMOTE2 is not set
1122# CONFIG_USB_KEYSPAN_REMOTE is not set
1123# CONFIG_USB_APPLETOUCH is not set
1124# CONFIG_USB_GTCO is not set
1125
1126#
1127# USB Imaging devices
1128#
1129# CONFIG_USB_MDC800 is not set
1130
1131#
1132# USB Network Adapters
1133#
1134# CONFIG_USB_CATC is not set
1135# CONFIG_USB_KAWETH is not set
1136# CONFIG_USB_PEGASUS is not set
1137# CONFIG_USB_RTL8150 is not set
1138# CONFIG_USB_USBNET_MII is not set
1139# CONFIG_USB_USBNET is not set
1140CONFIG_USB_MON=y
1141
1142#
1143# USB port drivers
1144# 627#
628# CONFIG_USB_GADGET is not set
629# CONFIG_MMC is not set
1145 630
1146# 631#
1147# USB Serial Converter support 632# LED devices
1148# 633#
1149# CONFIG_USB_SERIAL is not set 634# CONFIG_NEW_LEDS is not set
1150 635
1151# 636#
1152# USB Miscellaneous drivers 637# LED drivers
1153# 638#
1154# CONFIG_USB_EMI62 is not set
1155# CONFIG_USB_EMI26 is not set
1156# CONFIG_USB_ADUTUX is not set
1157# CONFIG_USB_AUERSWALD is not set
1158# CONFIG_USB_RIO500 is not set
1159# CONFIG_USB_LEGOTOWER is not set
1160# CONFIG_USB_LCD is not set
1161# CONFIG_USB_BERRY_CHARGE is not set
1162# CONFIG_USB_LED is not set
1163# CONFIG_USB_CYPRESS_CY7C63 is not set
1164# CONFIG_USB_CYTHERM is not set
1165# CONFIG_USB_PHIDGET is not set
1166# CONFIG_USB_IDMOUSE is not set
1167# CONFIG_USB_FTDI_ELAN is not set
1168# CONFIG_USB_APPLEDISPLAY is not set
1169# CONFIG_USB_LD is not set
1170# CONFIG_USB_TRANCEVIBRATOR is not set
1171 639
1172# 640#
1173# USB DSL modem support 641# LED Triggers
1174# 642#
1175 643
1176# 644#
1177# USB Gadget Support 645# InfiniBand support
1178# 646#
1179# CONFIG_USB_GADGET is not set 647# CONFIG_INFINIBAND is not set
1180 648
1181# 649#
1182# MMC/SD Card support 650# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
1183# 651#
1184# CONFIG_MMC is not set
1185 652
1186# 653#
1187# LED devices 654# Real Time Clock
1188# 655#
1189# CONFIG_NEW_LEDS is not set 656CONFIG_RTC_LIB=y
657CONFIG_RTC_CLASS=y
658CONFIG_RTC_HCTOSYS=y
659CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
660# CONFIG_RTC_DEBUG is not set
1190 661
1191# 662#
1192# LED drivers 663# RTC interfaces
1193# 664#
665CONFIG_RTC_INTF_SYSFS=y
666CONFIG_RTC_INTF_PROC=y
667CONFIG_RTC_INTF_DEV=y
668CONFIG_RTC_INTF_DEV_UIE_EMUL=y
669# CONFIG_RTC_DRV_TEST is not set
1194 670
1195# 671#
1196# LED Triggers 672# I2C RTC drivers
1197# 673#
1198 674
1199# 675#
1200# InfiniBand support 676# SPI RTC drivers
1201# 677#
1202# CONFIG_INFINIBAND is not set 678CONFIG_RTC_DRV_RS5C348=y
679# CONFIG_RTC_DRV_MAX6902 is not set
1203 680
1204# 681#
1205# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) 682# Platform RTC drivers
1206# 683#
684# CONFIG_RTC_DRV_CMOS is not set
685# CONFIG_RTC_DRV_DS1553 is not set
686# CONFIG_RTC_DRV_DS1742 is not set
687# CONFIG_RTC_DRV_M48T86 is not set
688# CONFIG_RTC_DRV_V3020 is not set
1207 689
1208# 690#
1209# Real Time Clock 691# on-CPU RTC drivers
1210# 692#
1211# CONFIG_RTC_CLASS is not set
1212 693
1213# 694#
1214# DMA Engine support 695# DMA Engine support
@@ -1224,38 +705,15 @@ CONFIG_USB_MON=y
1224# 705#
1225 706
1226# 707#
1227# Auxiliary Display support
1228#
1229
1230#
1231# Virtualization
1232#
1233
1234#
1235# File systems 708# File systems
1236# 709#
1237CONFIG_EXT2_FS=y 710# CONFIG_EXT2_FS is not set
1238# CONFIG_EXT2_FS_XATTR is not set 711# CONFIG_EXT3_FS is not set
1239# CONFIG_EXT2_FS_XIP is not set
1240CONFIG_EXT3_FS=m
1241CONFIG_EXT3_FS_XATTR=y
1242# CONFIG_EXT3_FS_POSIX_ACL is not set
1243# CONFIG_EXT3_FS_SECURITY is not set
1244# CONFIG_EXT4DEV_FS is not set 712# CONFIG_EXT4DEV_FS is not set
1245CONFIG_JBD=m 713# CONFIG_REISERFS_FS is not set
1246# CONFIG_JBD_DEBUG is not set
1247CONFIG_FS_MBCACHE=y
1248CONFIG_REISERFS_FS=m
1249# CONFIG_REISERFS_CHECK is not set
1250# CONFIG_REISERFS_PROC_INFO is not set
1251# CONFIG_REISERFS_FS_XATTR is not set
1252# CONFIG_JFS_FS is not set 714# CONFIG_JFS_FS is not set
1253CONFIG_FS_POSIX_ACL=y 715CONFIG_FS_POSIX_ACL=y
1254CONFIG_XFS_FS=m 716# CONFIG_XFS_FS is not set
1255# CONFIG_XFS_QUOTA is not set
1256# CONFIG_XFS_SECURITY is not set
1257# CONFIG_XFS_POSIX_ACL is not set
1258# CONFIG_XFS_RT is not set
1259# CONFIG_GFS2_FS is not set 717# CONFIG_GFS2_FS is not set
1260# CONFIG_OCFS2_FS is not set 718# CONFIG_OCFS2_FS is not set
1261# CONFIG_MINIX_FS is not set 719# CONFIG_MINIX_FS is not set
@@ -1265,26 +723,21 @@ CONFIG_INOTIFY_USER=y
1265# CONFIG_QUOTA is not set 723# CONFIG_QUOTA is not set
1266# CONFIG_DNOTIFY is not set 724# CONFIG_DNOTIFY is not set
1267# CONFIG_AUTOFS_FS is not set 725# CONFIG_AUTOFS_FS is not set
1268CONFIG_AUTOFS4_FS=m 726# CONFIG_AUTOFS4_FS is not set
1269CONFIG_FUSE_FS=m 727# CONFIG_FUSE_FS is not set
1270CONFIG_GENERIC_ACL=y 728CONFIG_GENERIC_ACL=y
1271 729
1272# 730#
1273# CD-ROM/DVD Filesystems 731# CD-ROM/DVD Filesystems
1274# 732#
1275CONFIG_ISO9660_FS=y 733# CONFIG_ISO9660_FS is not set
1276# CONFIG_JOLIET is not set
1277# CONFIG_ZISOFS is not set
1278# CONFIG_UDF_FS is not set 734# CONFIG_UDF_FS is not set
1279 735
1280# 736#
1281# DOS/FAT/NT Filesystems 737# DOS/FAT/NT Filesystems
1282# 738#
1283CONFIG_FAT_FS=y
1284# CONFIG_MSDOS_FS is not set 739# CONFIG_MSDOS_FS is not set
1285CONFIG_VFAT_FS=y 740# CONFIG_VFAT_FS is not set
1286CONFIG_FAT_DEFAULT_CODEPAGE=437
1287CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1288# CONFIG_NTFS_FS is not set 741# CONFIG_NTFS_FS is not set
1289 742
1290# 743#
@@ -1298,7 +751,7 @@ CONFIG_TMPFS=y
1298CONFIG_TMPFS_POSIX_ACL=y 751CONFIG_TMPFS_POSIX_ACL=y
1299# CONFIG_HUGETLB_PAGE is not set 752# CONFIG_HUGETLB_PAGE is not set
1300CONFIG_RAMFS=y 753CONFIG_RAMFS=y
1301CONFIG_CONFIGFS_FS=m 754# CONFIG_CONFIGFS_FS is not set
1302 755
1303# 756#
1304# Miscellaneous filesystems 757# Miscellaneous filesystems
@@ -1310,16 +763,7 @@ CONFIG_CONFIGFS_FS=m
1310# CONFIG_BEFS_FS is not set 763# CONFIG_BEFS_FS is not set
1311# CONFIG_BFS_FS is not set 764# CONFIG_BFS_FS is not set
1312# CONFIG_EFS_FS is not set 765# CONFIG_EFS_FS is not set
1313CONFIG_JFFS2_FS=y 766# CONFIG_CRAMFS is not set
1314CONFIG_JFFS2_FS_DEBUG=0
1315CONFIG_JFFS2_FS_WRITEBUFFER=y
1316# CONFIG_JFFS2_SUMMARY is not set
1317# CONFIG_JFFS2_FS_XATTR is not set
1318# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1319CONFIG_JFFS2_ZLIB=y
1320CONFIG_JFFS2_RTIME=y
1321# CONFIG_JFFS2_RUBIN is not set
1322CONFIG_CRAMFS=y
1323# CONFIG_VXFS_FS is not set 767# CONFIG_VXFS_FS is not set
1324# CONFIG_HPFS_FS is not set 768# CONFIG_HPFS_FS is not set
1325# CONFIG_QNX4FS_FS is not set 769# CONFIG_QNX4FS_FS is not set
@@ -1334,19 +778,16 @@ CONFIG_NFS_V3=y
1334# CONFIG_NFS_V3_ACL is not set 778# CONFIG_NFS_V3_ACL is not set
1335# CONFIG_NFS_V4 is not set 779# CONFIG_NFS_V4 is not set
1336# CONFIG_NFS_DIRECTIO is not set 780# CONFIG_NFS_DIRECTIO is not set
1337CONFIG_NFSD=m 781# CONFIG_NFSD is not set
1338# CONFIG_NFSD_V3 is not set
1339# CONFIG_NFSD_TCP is not set
1340CONFIG_ROOT_NFS=y 782CONFIG_ROOT_NFS=y
1341CONFIG_LOCKD=y 783CONFIG_LOCKD=y
1342CONFIG_LOCKD_V4=y 784CONFIG_LOCKD_V4=y
1343CONFIG_EXPORTFS=m
1344CONFIG_NFS_COMMON=y 785CONFIG_NFS_COMMON=y
1345CONFIG_SUNRPC=y 786CONFIG_SUNRPC=y
787# CONFIG_SUNRPC_BIND34 is not set
1346# CONFIG_RPCSEC_GSS_KRB5 is not set 788# CONFIG_RPCSEC_GSS_KRB5 is not set
1347# CONFIG_RPCSEC_GSS_SPKM3 is not set 789# CONFIG_RPCSEC_GSS_SPKM3 is not set
1348CONFIG_SMB_FS=m 790# CONFIG_SMB_FS is not set
1349# CONFIG_SMB_NLS_DEFAULT is not set
1350# CONFIG_CIFS is not set 791# CONFIG_CIFS is not set
1351# CONFIG_NCP_FS is not set 792# CONFIG_NCP_FS is not set
1352# CONFIG_CODA_FS is not set 793# CONFIG_CODA_FS is not set
@@ -1362,54 +803,12 @@ CONFIG_MSDOS_PARTITION=y
1362# 803#
1363# Native Language Support 804# Native Language Support
1364# 805#
1365CONFIG_NLS=y 806# CONFIG_NLS is not set
1366CONFIG_NLS_DEFAULT="iso8859-1"
1367# CONFIG_NLS_CODEPAGE_437 is not set
1368# CONFIG_NLS_CODEPAGE_737 is not set
1369# CONFIG_NLS_CODEPAGE_775 is not set
1370# CONFIG_NLS_CODEPAGE_850 is not set
1371# CONFIG_NLS_CODEPAGE_852 is not set
1372# CONFIG_NLS_CODEPAGE_855 is not set
1373# CONFIG_NLS_CODEPAGE_857 is not set
1374# CONFIG_NLS_CODEPAGE_860 is not set
1375# CONFIG_NLS_CODEPAGE_861 is not set
1376# CONFIG_NLS_CODEPAGE_862 is not set
1377# CONFIG_NLS_CODEPAGE_863 is not set
1378# CONFIG_NLS_CODEPAGE_864 is not set
1379# CONFIG_NLS_CODEPAGE_865 is not set
1380# CONFIG_NLS_CODEPAGE_866 is not set
1381# CONFIG_NLS_CODEPAGE_869 is not set
1382# CONFIG_NLS_CODEPAGE_936 is not set
1383# CONFIG_NLS_CODEPAGE_950 is not set
1384# CONFIG_NLS_CODEPAGE_932 is not set
1385# CONFIG_NLS_CODEPAGE_949 is not set
1386# CONFIG_NLS_CODEPAGE_874 is not set
1387# CONFIG_NLS_ISO8859_8 is not set
1388# CONFIG_NLS_CODEPAGE_1250 is not set
1389# CONFIG_NLS_CODEPAGE_1251 is not set
1390# CONFIG_NLS_ASCII is not set
1391# CONFIG_NLS_ISO8859_1 is not set
1392# CONFIG_NLS_ISO8859_2 is not set
1393# CONFIG_NLS_ISO8859_3 is not set
1394# CONFIG_NLS_ISO8859_4 is not set
1395# CONFIG_NLS_ISO8859_5 is not set
1396# CONFIG_NLS_ISO8859_6 is not set
1397# CONFIG_NLS_ISO8859_7 is not set
1398# CONFIG_NLS_ISO8859_9 is not set
1399# CONFIG_NLS_ISO8859_13 is not set
1400# CONFIG_NLS_ISO8859_14 is not set
1401# CONFIG_NLS_ISO8859_15 is not set
1402# CONFIG_NLS_KOI8_R is not set
1403# CONFIG_NLS_KOI8_U is not set
1404# CONFIG_NLS_UTF8 is not set
1405 807
1406# 808#
1407# Distributed Lock Manager 809# Distributed Lock Manager
1408# 810#
1409CONFIG_DLM=m 811# CONFIG_DLM is not set
1410CONFIG_DLM_TCP=y
1411# CONFIG_DLM_SCTP is not set
1412# CONFIG_DLM_DEBUG is not set
1413 812
1414# 813#
1415# Profiling support 814# Profiling support
@@ -1427,7 +826,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1427# CONFIG_DEBUG_FS is not set 826# CONFIG_DEBUG_FS is not set
1428# CONFIG_HEADERS_CHECK is not set 827# CONFIG_HEADERS_CHECK is not set
1429# CONFIG_DEBUG_KERNEL is not set 828# CONFIG_DEBUG_KERNEL is not set
1430CONFIG_LOG_BUF_SHIFT=14
1431CONFIG_CROSSCOMPILE=y 829CONFIG_CROSSCOMPILE=y
1432CONFIG_CMDLINE="" 830CONFIG_CMDLINE=""
1433CONFIG_SYS_SUPPORTS_KGDB=y 831CONFIG_SYS_SUPPORTS_KGDB=y
@@ -1441,62 +839,17 @@ CONFIG_SYS_SUPPORTS_KGDB=y
1441# 839#
1442# Cryptographic options 840# Cryptographic options
1443# 841#
1444CONFIG_CRYPTO=y 842# CONFIG_CRYPTO is not set
1445CONFIG_CRYPTO_ALGAPI=y
1446CONFIG_CRYPTO_BLKCIPHER=m
1447CONFIG_CRYPTO_HASH=y
1448CONFIG_CRYPTO_MANAGER=y
1449CONFIG_CRYPTO_HMAC=y
1450CONFIG_CRYPTO_XCBC=m
1451CONFIG_CRYPTO_NULL=m
1452CONFIG_CRYPTO_MD4=m
1453CONFIG_CRYPTO_MD5=y
1454CONFIG_CRYPTO_SHA1=m
1455CONFIG_CRYPTO_SHA256=m
1456CONFIG_CRYPTO_SHA512=m
1457CONFIG_CRYPTO_WP512=m
1458CONFIG_CRYPTO_TGR192=m
1459CONFIG_CRYPTO_GF128MUL=m
1460CONFIG_CRYPTO_ECB=m
1461CONFIG_CRYPTO_CBC=m
1462CONFIG_CRYPTO_PCBC=m
1463CONFIG_CRYPTO_LRW=m
1464CONFIG_CRYPTO_DES=m
1465CONFIG_CRYPTO_FCRYPT=m
1466CONFIG_CRYPTO_BLOWFISH=m
1467CONFIG_CRYPTO_TWOFISH=m
1468CONFIG_CRYPTO_TWOFISH_COMMON=m
1469CONFIG_CRYPTO_SERPENT=m
1470CONFIG_CRYPTO_AES=m
1471CONFIG_CRYPTO_CAST5=m
1472CONFIG_CRYPTO_CAST6=m
1473CONFIG_CRYPTO_TEA=m
1474CONFIG_CRYPTO_ARC4=m
1475CONFIG_CRYPTO_KHAZAD=m
1476CONFIG_CRYPTO_ANUBIS=m
1477CONFIG_CRYPTO_DEFLATE=m
1478CONFIG_CRYPTO_MICHAEL_MIC=m
1479CONFIG_CRYPTO_CRC32C=m
1480CONFIG_CRYPTO_CAMELLIA=m
1481# CONFIG_CRYPTO_TEST is not set
1482
1483#
1484# Hardware crypto devices
1485#
1486 843
1487# 844#
1488# Library routines 845# Library routines
1489# 846#
1490CONFIG_BITREVERSE=y 847CONFIG_BITREVERSE=y
1491CONFIG_CRC_CCITT=m 848# CONFIG_CRC_CCITT is not set
1492CONFIG_CRC16=m 849# CONFIG_CRC16 is not set
850# CONFIG_CRC_ITU_T is not set
1493CONFIG_CRC32=y 851CONFIG_CRC32=y
1494CONFIG_LIBCRC32C=m 852# CONFIG_LIBCRC32C is not set
1495CONFIG_ZLIB_INFLATE=y
1496CONFIG_ZLIB_DEFLATE=y
1497CONFIG_TEXTSEARCH=y
1498CONFIG_TEXTSEARCH_KMP=m
1499CONFIG_TEXTSEARCH_BM=m
1500CONFIG_TEXTSEARCH_FSM=m
1501CONFIG_HAS_IOMEM=y 853CONFIG_HAS_IOMEM=y
1502CONFIG_HAS_IOPORT=y 854CONFIG_HAS_IOPORT=y
855CONFIG_HAS_DMA=y
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index 5593cde9f74c..1a67a85aabbb 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 6c4f09a381e2..98a914092258 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 988b9cdef01f..69c08b24c82a 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33CONFIG_MIPS_SEAD=y 31CONFIG_MIPS_SEAD=y
@@ -35,8 +33,6 @@ CONFIG_MIPS_SEAD=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index 8b1675c07ec4..5d4fc0e4f729 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index b5be8b74d896..1b92b48de051 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 8bb6be4342b6..5b77c7a5d83a 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index 8f019ffcc71b..94a4f94a8b24 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 52b48c0715d3..e38bd9b0eadc 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_WR_PPMC=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 6824606309e5..f1cdb12f7925 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/ddb5xxx/ddb5477/Makefile b/arch/mips/ddb5xxx/ddb5477/Makefile
index 23fd3b81fe1a..4864b8a659c7 100644
--- a/arch/mips/ddb5xxx/ddb5477/Makefile
+++ b/arch/mips/ddb5xxx/ddb5477/Makefile
@@ -2,7 +2,8 @@
2# Makefile for NEC DDB-Vrc5477 board 2# Makefile for NEC DDB-Vrc5477 board
3# 3#
4 4
5obj-y += irq.o irq_5477.o setup.o lcd44780.o 5obj-y += ddb5477-platform.o irq.o irq_5477.o setup.o \
6 lcd44780.o
6 7
7obj-$(CONFIG_RUNTIME_DEBUG) += debug.o 8obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
8obj-$(CONFIG_KGDB) += kgdb_io.o 9obj-$(CONFIG_KGDB) += kgdb_io.o
diff --git a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c b/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c
new file mode 100644
index 000000000000..c16020ad54c2
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c
@@ -0,0 +1,49 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/serial_8250.h>
11
12#include <asm/ddb5xxx/ddb5477.h>
13
14#define DDB_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
15
16#define DDB5477_PORT(base, int) \
17{ \
18 .mapbase = base, \
19 .irq = int, \
20 .uartclk = 1843200, \
21 .iotype = UPIO_MEM, \
22 .flags = DDB_UART_FLAGS, \
23 .regshift = 3, \
24}
25
26static struct plat_serial8250_port uart8250_data[] = {
27 DDB5477_PORT(0xbfa04200, VRC5477_IRQ_UART0),
28 DDB5477_PORT(0xbfa04240, VRC5477_IRQ_UART1),
29 { },
30};
31
32static struct platform_device uart8250_device = {
33 .name = "serial8250",
34 .id = PLAT8250_DEV_PLATFORM,
35 .dev = {
36 .platform_data = uart8250_data,
37 },
38};
39
40static int __init uart8250_init(void)
41{
42 return platform_device_register(&uart8250_device);
43}
44
45module_init(uart8250_init);
46
47MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
48MODULE_LICENSE("GPL");
49MODULE_DESCRIPTION("8250 UART probe driver for the NEC DDB5477");
diff --git a/arch/mips/dec/prom/console.c b/arch/mips/dec/prom/console.c
index 65419bf32441..078e1a12421d 100644
--- a/arch/mips/dec/prom/console.c
+++ b/arch/mips/dec/prom/console.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * DECstation PROM-based early console support. 4 * DECstation PROM-based early console support.
5 * 5 *
6 * Copyright (C) 2004 Maciej W. Rozycki 6 * Copyright (C) 2004, 2007 Maciej W. Rozycki
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License 9 * modify it under the terms of the GNU General Public License
@@ -13,15 +13,35 @@
13#include <linux/console.h> 13#include <linux/console.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/string.h>
16 17
17#include <asm/dec/prom.h> 18#include <asm/dec/prom.h>
18 19
19void prom_putchar(char c) 20static void __init prom_console_write(struct console *con, const char *s,
21 unsigned int c)
20{ 22{
21 char s[2]; 23 char buf[81];
24 unsigned int chunk = sizeof(buf) - 1;
22 25
23 s[0] = c; 26 while (c > 0) {
24 s[1] = '\0'; 27 if (chunk > c)
28 chunk = c;
29 memcpy(buf, s, chunk);
30 buf[chunk] = '\0';
31 prom_printf("%s", buf);
32 s += chunk;
33 c -= chunk;
34 }
35}
36
37static struct console promcons __initdata = {
38 .name = "prom",
39 .write = prom_console_write,
40 .flags = CON_BOOT | CON_PRINTBUFFER,
41 .index = -1,
42};
25 43
26 prom_printf( s); 44void __init register_prom_console(void)
45{
46 register_console(&promcons);
27} 47}
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index a217aafe59f6..808c182fd3fa 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -86,7 +86,7 @@ void __init which_prom(s32 magic, s32 *prom_vec)
86 86
87void __init prom_init(void) 87void __init prom_init(void)
88{ 88{
89 extern void ATTRIB_NORET dec_machine_halt(void); 89 extern void dec_machine_halt(void);
90 static char cpu_msg[] __initdata = 90 static char cpu_msg[] __initdata =
91 "Sorry, this kernel is compiled for a wrong CPU type!\n"; 91 "Sorry, this kernel is compiled for a wrong CPU type!\n";
92 s32 argc = fw_arg0; 92 s32 argc = fw_arg0;
@@ -103,6 +103,9 @@ void __init prom_init(void)
103 if (prom_is_rex(magic)) 103 if (prom_is_rex(magic))
104 rex_clear_cache(); 104 rex_clear_cache();
105 105
106 /* Register the early console. */
107 register_prom_console();
108
106 /* Were we compiled with the right CPU option? */ 109 /* Were we compiled with the right CPU option? */
107#if defined(CONFIG_CPU_R3000) 110#if defined(CONFIG_CPU_R3000)
108 if ((current_cpu_data.cputype == CPU_R4000SC) || 111 if ((current_cpu_data.cputype == CPU_R4000SC) ||
diff --git a/arch/mips/dec/reset.c b/arch/mips/dec/reset.c
index 56397227adb0..c15a879046e5 100644
--- a/arch/mips/dec/reset.c
+++ b/arch/mips/dec/reset.c
@@ -9,26 +9,26 @@
9 9
10#include <asm/addrspace.h> 10#include <asm/addrspace.h>
11 11
12typedef void ATTRIB_NORET (* noret_func_t)(void); 12typedef void __noreturn (* noret_func_t)(void);
13 13
14static inline void ATTRIB_NORET back_to_prom(void) 14static inline void __noreturn back_to_prom(void)
15{ 15{
16 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); 16 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000);
17 17
18 func(); 18 func();
19} 19}
20 20
21void ATTRIB_NORET dec_machine_restart(char *command) 21void __noreturn dec_machine_restart(char *command)
22{ 22{
23 back_to_prom(); 23 back_to_prom();
24} 24}
25 25
26void ATTRIB_NORET dec_machine_halt(void) 26void __noreturn dec_machine_halt(void)
27{ 27{
28 back_to_prom(); 28 back_to_prom();
29} 29}
30 30
31void ATTRIB_NORET dec_machine_power_off(void) 31void __noreturn dec_machine_power_off(void)
32{ 32{
33 /* DECstations don't have a software power switch */ 33 /* DECstations don't have a software power switch */
34 back_to_prom(); 34 back_to_prom();
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index 41211f8b7738..b3b6e58058f6 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -25,9 +25,7 @@ CONFIG_ZONE_DMA=y
25# CONFIG_BASLER_EXCITE is not set 25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MIPS_EV64120 is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
30# CONFIG_LASAT is not set
31# CONFIG_MIPS_ATLAS is not set 29# CONFIG_MIPS_ATLAS is not set
32# CONFIG_MIPS_MALTA is not set 30# CONFIG_MIPS_MALTA is not set
33# CONFIG_MIPS_SEAD is not set 31# CONFIG_MIPS_SEAD is not set
@@ -35,8 +33,6 @@ CONFIG_ZONE_DMA=y
35# CONFIG_MIPS_SIM is not set 33# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set 34# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set 35# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set 36# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set 37# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_JBS is not set 38# CONFIG_PNX8550_JBS is not set
diff --git a/arch/mips/gt64120/ev64120/Kconfig b/arch/mips/gt64120/ev64120/Kconfig
deleted file mode 100644
index d691762cb0f7..000000000000
--- a/arch/mips/gt64120/ev64120/Kconfig
+++ /dev/null
@@ -1,3 +0,0 @@
1config EVB_PCI1
2 bool "Enable Second PCI (PCI1)"
3 depends on MIPS_EV64120
diff --git a/arch/mips/gt64120/ev64120/Makefile b/arch/mips/gt64120/ev64120/Makefile
deleted file mode 100644
index 323b2cebc691..000000000000
--- a/arch/mips/gt64120/ev64120/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Copyright 2000 RidgeRun, Inc.
3# Author: RidgeRun, Inc.
4# glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5#
6# Makefile for the Galileo EV64120 board.
7#
8
9obj-y += irq.o promcon.o reset.o serialGT.o setup.o
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
deleted file mode 100644
index 64e4c80b6139..000000000000
--- a/arch/mips/gt64120/ev64120/irq.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Code to handle irqs on GT64120A boards
4 * Derived from mips/orion and Cort <cort@fsmlabs.com>
5 *
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: RidgeRun, Inc.
8 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/errno.h>
31#include <linux/init.h>
32#include <linux/kernel_stat.h>
33#include <linux/module.h>
34#include <linux/signal.h>
35#include <linux/sched.h>
36#include <linux/types.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/timex.h>
40#include <linux/slab.h>
41#include <linux/random.h>
42#include <linux/bitops.h>
43#include <asm/bootinfo.h>
44#include <asm/io.h>
45#include <asm/mipsregs.h>
46#include <asm/system.h>
47#include <asm/gt64120.h>
48
49asmlinkage void plat_irq_dispatch(void)
50{
51 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
52
53 if (pending & STATUSF_IP4) /* int2 hardware line (timer) */
54 do_IRQ(4);
55 else if (pending & STATUSF_IP2) /* int0 hardware line */
56 do_IRQ(GT_INTA);
57 else if (pending & STATUSF_IP5) /* int3 hardware line */
58 do_IRQ(GT_INTD);
59 else if (pending & STATUSF_IP6) /* int4 hardware line */
60 do_IRQ(6);
61 else if (pending & STATUSF_IP7) /* compare int */
62 do_IRQ(7);
63 else
64 spurious_interrupt();
65}
66
67static void disable_ev64120_irq(unsigned int irq_nr)
68{
69 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
70 clear_c0_status(9 << 10);
71 } else {
72 clear_c0_status(1 << (irq_nr + 8));
73 }
74}
75
76static void enable_ev64120_irq(unsigned int irq_nr)
77{
78 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
79 set_c0_status(9 << 10);
80 else
81 set_c0_status(1 << (irq_nr + 8));
82}
83
84static void end_ev64120_irq(unsigned int irq)
85{
86 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
87 enable_ev64120_irq(irq);
88}
89
90static struct irq_chip ev64120_irq_type = {
91 .name = "EV64120",
92 .ack = disable_ev64120_irq,
93 .mask = disable_ev64120_irq,
94 .mask_ack = disable_ev64120_irq,
95 .unmask = enable_ev64120_irq,
96 .end = end_ev64120_irq,
97};
98
99void gt64120_irq_setup(void)
100{
101 /*
102 * Clear all of the interrupts while we change the able around a bit.
103 */
104 clear_c0_status(ST0_IM);
105
106 /*
107 * Enable timer. Other interrupts will be enabled as they are
108 * registered.
109 */
110 set_c0_status(IE_IRQ2);
111}
112
113void __init arch_init_irq(void)
114{
115 gt64120_irq_setup();
116}
diff --git a/arch/mips/gt64120/ev64120/promcon.c b/arch/mips/gt64120/ev64120/promcon.c
deleted file mode 100644
index 6e0ecfed9640..000000000000
--- a/arch/mips/gt64120/ev64120/promcon.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * Wrap-around code for a console using the
3 * SGI PROM io-routines.
4 *
5 * Copyright (c) 1999 Ulf Carlsson
6 *
7 * Derived from DECstation promcon.c
8 * Copyright (c) 1998 Harald Koerfgen
9 */
10#include <linux/tty.h>
11#include <linux/init.h>
12#include <linux/console.h>
13
14static void prom_console_write(struct console *co, const char *s,
15 unsigned count)
16{
17 extern int CONSOLE_CHANNEL; // The default serial port
18 unsigned i;
19
20 for (i = 0; i < count; i++) {
21 if (*s == 10)
22 serial_putc(CONSOLE_CHANNEL, 13);
23 serial_putc(CONSOLE_CHANNEL, *s++);
24 }
25}
26
27static struct console sercons = {
28 .name = "ttyS",
29 .write = prom_console_write,
30 .flags = CON_PRINTBUFFER,
31 .index = -1,
32};
33
34/*
35 * Register console.
36 */
37
38static int gal_serial_console_init(void)
39{
40 // serial_init();
41 //serial_set(115200);
42
43 register_console(&sercons);
44
45 return 0;
46}
47
48console_initcall(gal_serial_console_init);
diff --git a/arch/mips/gt64120/ev64120/reset.c b/arch/mips/gt64120/ev64120/reset.c
deleted file mode 100644
index 7b9f5e5bf21f..000000000000
--- a/arch/mips/gt64120/ev64120/reset.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997 Ralf Baechle
7 */
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <asm/io.h>
11#include <asm/pgtable.h>
12#include <asm/processor.h>
13#include <asm/reboot.h>
14#include <asm/system.h>
15
16void galileo_machine_restart(char *command)
17{
18 *(volatile char *) 0xbc000000 = 0x0f;
19 /*
20 * Ouch, we're still alive ... This time we take the silver bullet ...
21 * ... and find that we leave the hardware in a state in which the
22 * kernel in the flush locks up somewhen during of after the PCI
23 * detection stuff.
24 */
25 set_c0_status(ST0_BEV | ST0_ERL);
26 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
27 flush_cache_all();
28 write_c0_wired(0);
29 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
30}
31
32void galileo_machine_halt(void)
33{
34 printk(KERN_NOTICE "You can safely turn off the power\n");
35 while (1)
36 __asm__(".set\tmips3\n\t"
37 "wait\n\t"
38 ".set\tmips0");
39
40}
41
42void galileo_machine_power_off(void)
43{
44 galileo_machine_halt();
45}
diff --git a/arch/mips/gt64120/ev64120/serialGT.c b/arch/mips/gt64120/ev64120/serialGT.c
deleted file mode 100644
index 8f0d835491ff..000000000000
--- a/arch/mips/gt64120/ev64120/serialGT.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 * serialGT.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Low Level Serial Port control for use
6 * with the Galileo EVB64120A MIPS eval board and
7 * its on board two channel 16552 Uart.
8 *
9 * Copyright (C) 2000 RidgeRun, Inc.
10 * Author: RidgeRun, Inc.
11 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 */
34
35// Note:
36// Serial CHANNELS - 0 is the bottom connector of evb64120A.
37// (The one that maps to the "B" channel of the
38// board's uart)
39// 1 is the top connector of evb64120A.
40// (The one that maps to the "A" channel of the
41// board's uart)
42int DEBUG_CHANNEL = 0; // See Note Above
43int CONSOLE_CHANNEL = 1; // See Note Above
44
45#define DUART 0xBD000000 /* Base address of Uart. */
46#define CHANNELOFFSET 0x20 /* DUART+CHANNELOFFSET gets you to the ChanA
47 register set of the 16552 Uart device.
48 DUART+0 gets you to the ChanB register set.
49 */
50#define DUART_DELTA 0x4
51#define FIFO_ENABLE 0x07
52#define INT_ENABLE 0x04 /* default interrupt mask */
53
54#define RBR 0x00
55#define THR 0x00
56#define DLL 0x00
57#define IER 0x01
58#define DLM 0x01
59#define IIR 0x02
60#define FCR 0x02
61#define LCR 0x03
62#define MCR 0x04
63#define LSR 0x05
64#define MSR 0x06
65#define SCR 0x07
66
67#define LCR_DLAB 0x80
68#define XTAL 1843200
69#define LSR_THRE 0x20
70#define LSR_BI 0x10
71#define LSR_DR 0x01
72#define MCR_LOOP 0x10
73#define ACCESS_DELAY 0x10000
74
75/******************************
76 Routine:
77 Description:
78 ******************************/
79int inreg(int channel, int reg)
80{
81 int val;
82 val =
83 *((volatile unsigned char *) DUART +
84 (channel * CHANNELOFFSET) + (reg * DUART_DELTA));
85 return val;
86}
87
88/******************************
89 Routine:
90 Description:
91 ******************************/
92void outreg(int channel, int reg, unsigned char val)
93{
94 *((volatile unsigned char *) DUART + (channel * CHANNELOFFSET)
95 + (reg * DUART_DELTA)) = val;
96}
97
98/******************************
99 Routine:
100 Description:
101 Initialize the device driver.
102 ******************************/
103void serial_init(int channel)
104{
105 /*
106 * Configure active port, (CHANNELOFFSET already set.)
107 *
108 * Set 8 bits, 1 stop bit, no parity.
109 *
110 * LCR<7> 0 divisor latch access bit
111 * LCR<6> 0 break control (1=send break)
112 * LCR<5> 0 stick parity (0=space, 1=mark)
113 * LCR<4> 0 parity even (0=odd, 1=even)
114 * LCR<3> 0 parity enable (1=enabled)
115 * LCR<2> 0 # stop bits (0=1, 1=1.5)
116 * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8)
117 */
118 outreg(channel, LCR, 0x3);
119
120 outreg(channel, FCR, FIFO_ENABLE); /* Enable the FIFO */
121
122 outreg(channel, IER, INT_ENABLE); /* Enable appropriate interrupts */
123}
124
125/******************************
126 Routine:
127 Description:
128 Set the baud rate.
129 ******************************/
130void serial_set(int channel, unsigned long baud)
131{
132 unsigned char sav_lcr;
133
134 /*
135 * Enable access to the divisor latches by setting DLAB in LCR.
136 *
137 */
138 sav_lcr = inreg(channel, LCR);
139
140#if 0
141 /*
142 * Set baud rate
143 */
144 outreg(channel, LCR, LCR_DLAB | sav_lcr);
145 // outreg(DLL,(XTAL/(16*2*(baud))-2));
146 outreg(channel, DLL, XTAL / (16 * baud));
147 // outreg(DLM,(XTAL/(16*2*(baud))-2)>>8);
148 outreg(channel, DLM, (XTAL / (16 * baud)) >> 8);
149#else
150 /*
151 * Note: Set baud rate, hardcoded here for rate of 115200
152 * since became unsure of above "baud rate" algorithm (??).
153 */
154 outreg(channel, LCR, 0x83);
155 outreg(channel, DLM, 0x00); // See note above
156 outreg(channel, DLL, 0x02); // See note above.
157 outreg(channel, LCR, 0x03);
158#endif
159
160 /*
161 * Restore line control register
162 */
163 outreg(channel, LCR, sav_lcr);
164}
165
166
167/******************************
168 Routine:
169 Description:
170 Transmit a character.
171 ******************************/
172void serial_putc(int channel, int c)
173{
174 while ((inreg(channel, LSR) & LSR_THRE) == 0);
175 outreg(channel, THR, c);
176}
177
178/******************************
179 Routine:
180 Description:
181 Read a received character if one is
182 available. Return -1 otherwise.
183 ******************************/
184int serial_getc(int channel)
185{
186 if (inreg(channel, LSR) & LSR_DR) {
187 return inreg(channel, RBR);
188 }
189 return -1;
190}
191
192/******************************
193 Routine:
194 Description:
195 Used by embedded gdb client. (example; gdb-stub.c)
196 ******************************/
197char getDebugChar()
198{
199 int val;
200 while ((val = serial_getc(DEBUG_CHANNEL)) == -1); // loop until we get a character in.
201 return (char) val;
202}
203
204/******************************
205 Routine:
206 Description:
207 Used by embedded gdb target. (example; gdb-stub.c)
208 ******************************/
209void putDebugChar(char c)
210{
211 serial_putc(DEBUG_CHANNEL, (int) c);
212}
diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c
deleted file mode 100644
index 477848c22a2c..000000000000
--- a/arch/mips/gt64120/ev64120/setup.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/types.h>
30#include <linux/mm.h>
31#include <linux/swap.h>
32#include <linux/ioport.h>
33#include <linux/sched.h>
34#include <linux/interrupt.h>
35#include <linux/pci.h>
36#include <linux/timex.h>
37#include <linux/pm.h>
38
39#include <asm/bootinfo.h>
40#include <asm/page.h>
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/pci.h>
44#include <asm/processor.h>
45#include <asm/time.h>
46#include <asm/reboot.h>
47#include <asm/traps.h>
48#include <linux/bootmem.h>
49
50unsigned long gt64120_base = KSEG1ADDR(0x14000000);
51
52/* These functions are used for rebooting or halting the machine*/
53extern void galileo_machine_restart(char *command);
54extern void galileo_machine_halt(void);
55extern void galileo_machine_power_off(void);
56/*
57 *This structure holds pointers to the pci configuration space accesses
58 *and interrupts allocating routine for device over the PCI
59 */
60extern struct pci_ops galileo_pci_ops;
61
62void __init prom_free_prom_memory(void)
63{
64}
65
66/*
67 * Initializes basic routines and structures pointers, memory size (as
68 * given by the bios and saves the command line.
69 */
70
71void __init plat_mem_setup(void)
72{
73 _machine_restart = galileo_machine_restart;
74 _machine_halt = galileo_machine_halt;
75 pm_power_off = galileo_machine_power_off;
76
77 set_io_port_base(KSEG1);
78}
79
80const char *get_system_type(void)
81{
82 return "Galileo EV64120A";
83}
84
85/*
86 * Kernel arguments passed by the firmware
87 *
88 * $a0 - nothing
89 * $a1 - holds a pointer to the eprom parameters
90 * $a2 - nothing
91 */
92
93void __init prom_init(void)
94{
95 mips_machgroup = MACH_GROUP_GALILEO;
96 mips_machtype = MACH_EV64120A;
97
98 add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
99}
diff --git a/arch/mips/gt64120/momenco_ocelot/Makefile b/arch/mips/gt64120/momenco_ocelot/Makefile
index 9f9a33fc76b9..1df5fe23c642 100644
--- a/arch/mips/gt64120/momenco_ocelot/Makefile
+++ b/arch/mips/gt64120/momenco_ocelot/Makefile
@@ -2,6 +2,6 @@
2# Makefile for Momentum's Ocelot board. 2# Makefile for Momentum's Ocelot board.
3# 3#
4 4
5obj-y += irq.o prom.o reset.o setup.o 5obj-y += irq.o ocelot-platform.o prom.o reset.o setup.o
6 6
7obj-$(CONFIG_KGDB) += dbg_io.o 7obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c b/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c
new file mode 100644
index 000000000000..81d9031a5a2a
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c
@@ -0,0 +1,46 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * A NS16552 DUART with a 20MHz crystal.
9 *
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/serial_8250.h>
14
15#define OCELOT_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
16
17static struct plat_serial8250_port uart8250_data[] = {
18 {
19 .mapbase = 0xe0001020,
20 .irq = 4,
21 .uartclk = 20000000,
22 .iotype = UPIO_MEM,
23 .flags = OCELOT_UART_FLAGS,
24 .regshift = 2,
25 },
26 { },
27};
28
29static struct platform_device uart8250_device = {
30 .name = "serial8250",
31 .id = PLAT8250_DEV_PLATFORM,
32 .dev = {
33 .platform_data = uart8250_data,
34 },
35};
36
37static int __init uart8250_init(void)
38{
39 return platform_device_register(&uart8250_device);
40}
41
42module_init(uart8250_init);
43
44MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
45MODULE_LICENSE("GPL");
46MODULE_DESCRIPTION("8250 UART probe driver for the Momenco Ocelot");
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c
index 121188d5ec4a..ea965529e5e0 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/gt64120/wrppmc/setup.c
@@ -158,8 +158,8 @@ const char *get_system_type(void)
158 */ 158 */
159void __init prom_init(void) 159void __init prom_init(void)
160{ 160{
161 mips_machgroup = MACH_GROUP_GALILEO; 161 mips_machgroup = MACH_GROUP_WINDRIVER;
162 mips_machtype = MACH_EV64120A; 162 mips_machtype = MACH_WRPPMC;
163 163
164 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); 164 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
165 add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA); 165 add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile
index dd9d99bfcf7a..ae4c402b5004 100644
--- a/arch/mips/jazz/Makefile
+++ b/arch/mips/jazz/Makefile
@@ -2,4 +2,4 @@
2# Makefile for the Jazz family specific parts of the kernel 2# Makefile for the Jazz family specific parts of the kernel
3# 3#
4 4
5obj-y := irq.o jazzdma.o reset.o setup.o 5obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o
diff --git a/arch/mips/jazz/jazz-platform.c b/arch/mips/jazz/jazz-platform.c
new file mode 100644
index 000000000000..fd736703eef2
--- /dev/null
+++ b/arch/mips/jazz/jazz-platform.c
@@ -0,0 +1,60 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/serial_8250.h>
11
12#include <asm/jazz.h>
13
14/*
15 * Confusion ... It seems the original Microsoft Jazz machine used to have a
16 * 4.096MHz clock for its UART while the MIPS Magnum and Millenium systems
17 * had 8MHz. The Olivetti M700-10 and the Acer PICA have 1.8432MHz like PCs.
18 */
19#ifdef CONFIG_OLIVETTI_M700
20#define JAZZ_BASE_BAUD 1843200
21#else
22#define JAZZ_BASE_BAUD 8000000 /* 3072000 */
23#endif
24
25#define JAZZ_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
26
27#define JAZZ_PORT(base, int) \
28{ \
29 .mapbase = base, \
30 .irq = int, \
31 .uartclk = JAZZ_BASE_BAUD, \
32 .iotype = UPIO_MEM, \
33 .flags = JAZZ_UART_FLAGS, \
34 .regshift = 0, \
35}
36
37static struct plat_serial8250_port uart8250_data[] = {
38 JAZZ_PORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ),
39 JAZZ_PORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ),
40 { },
41};
42
43static struct platform_device uart8250_device = {
44 .name = "serial8250",
45 .id = PLAT8250_DEV_PLATFORM,
46 .dev = {
47 .platform_data = uart8250_data,
48 },
49};
50
51static int __init uart8250_init(void)
52{
53 return platform_device_register(&uart8250_device);
54}
55
56module_init(uart8250_init);
57
58MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
59MODULE_LICENSE("GPL");
60MODULE_DESCRIPTION("8250 UART probe driver for the Jazz family");
diff --git a/arch/mips/kernel/8250-platform.c b/arch/mips/kernel/8250-platform.c
new file mode 100644
index 000000000000..cbf3fe20ad17
--- /dev/null
+++ b/arch/mips/kernel/8250-platform.c
@@ -0,0 +1,47 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/serial_8250.h>
11
12#define PORT(base, int) \
13{ \
14 .iobase = base, \
15 .irq = int, \
16 .uartclk = 1843200, \
17 .iotype = UPIO_PORT, \
18 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
19 .regshift = 0, \
20}
21
22static struct plat_serial8250_port uart8250_data[] = {
23 PORT(0x3F8, 4),
24 PORT(0x2F8, 3),
25 PORT(0x3E8, 4),
26 PORT(0x2E8, 3),
27 { },
28};
29
30static struct platform_device uart8250_device = {
31 .name = "serial8250",
32 .id = PLAT8250_DEV_PLATFORM,
33 .dev = {
34 .platform_data = uart8250_data,
35 },
36};
37
38static int __init uart8250_init(void)
39{
40 return platform_device_register(&uart8250_device);
41}
42
43module_init(uart8250_init);
44
45MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
46MODULE_LICENSE("GPL");
47MODULE_DESCRIPTION("Generic 8250 UART probe driver");
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 49246264cc7c..961594cb5214 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -14,14 +14,15 @@ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
14obj-$(CONFIG_STACKTRACE) += stacktrace.o 14obj-$(CONFIG_STACKTRACE) += stacktrace.o
15obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 15obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
16 16
17obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o
18obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
19obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
17obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o 20obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
18obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
19obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
20obj-$(CONFIG_CPU_R4000) += r4k_fpu.o r4k_switch.o 21obj-$(CONFIG_CPU_R4000) += r4k_fpu.o r4k_switch.o
21obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
22obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o 22obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o
23obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o 23obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o
24obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o 24obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o
25obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
25obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o 26obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o
26obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o 27obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o
27obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o 28obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o
@@ -29,13 +30,14 @@ obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o
29obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o 30obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o
30obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o 31obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o
31obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o 32obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
32obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o 33obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
33obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o 34obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
34obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o 35obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
35 36
36obj-$(CONFIG_SMP) += smp.o 37obj-$(CONFIG_SMP) += smp.o
37 38
38obj-$(CONFIG_MIPS_MT) += mips-mt.o 39obj-$(CONFIG_MIPS_MT) += mips-mt.o
40obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
39obj-$(CONFIG_MIPS_MT_SMTC) += smtc.o smtc-asm.o smtc-proc.o 41obj-$(CONFIG_MIPS_MT_SMTC) += smtc.o smtc-asm.o smtc-proc.o
40obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o 42obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o
41 43
@@ -47,7 +49,6 @@ obj-$(CONFIG_I8259) += i8259.o
47obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 49obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
48obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o 50obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
49obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o 51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
50obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o
51obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o 52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
52 53
53obj-$(CONFIG_32BIT) += scall32-o32.o 54obj-$(CONFIG_32BIT) += scall32-o32.o
@@ -68,3 +69,5 @@ obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
68obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 69obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
69 70
70CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) 71CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
72
73obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b12eeee0e974..c6b8b074a81a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -186,9 +186,29 @@ static inline void check_wait(void)
186 } 186 }
187} 187}
188 188
189static inline void check_errata(void)
190{
191 struct cpuinfo_mips *c = &current_cpu_data;
192
193 switch (c->cputype) {
194 case CPU_34K:
195 /*
196 * Erratum "RPS May Cause Incorrect Instruction Execution"
197 * This code only handles VPE0, any SMP/SMTC/RTOS code
198 * making use of VPE1 will be responsable for that VPE.
199 */
200 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
201 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
202 break;
203 default:
204 break;
205 }
206}
207
189void __init check_bugs32(void) 208void __init check_bugs32(void)
190{ 209{
191 check_wait(); 210 check_wait();
211 check_errata();
192} 212}
193 213
194/* 214/*
@@ -485,6 +505,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
485 MIPS_CPU_LLSC; 505 MIPS_CPU_LLSC;
486 c->tlbsize = 64; 506 c->tlbsize = 64;
487 break; 507 break;
508 case PRID_IMP_LOONGSON2:
509 c->cputype = CPU_LOONGSON2;
510 c->isa_level = MIPS_CPU_ISA_III;
511 c->options = R4K_OPTS |
512 MIPS_CPU_FPU | MIPS_CPU_LLSC |
513 MIPS_CPU_32FPR;
514 c->tlbsize = 64;
515 break;
488 } 516 }
489} 517}
490 518
@@ -588,6 +616,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
588 c->options |= MIPS_CPU_VEIC; 616 c->options |= MIPS_CPU_VEIC;
589 if (config3 & MIPS_CONF3_MT) 617 if (config3 & MIPS_CONF3_MT)
590 c->ases |= MIPS_ASE_MIPSMT; 618 c->ases |= MIPS_ASE_MIPSMT;
619 if (config3 & MIPS_CONF3_ULRI)
620 c->options |= MIPS_CPU_ULRI;
591 621
592 return config3 & MIPS_CONF_M; 622 return config3 & MIPS_CONF_M;
593} 623}
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 6f57ca44291f..f78538eceef7 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -16,6 +16,7 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/threads.h> 17#include <linux/threads.h>
18 18
19#include <asm/addrspace.h>
19#include <asm/asm.h> 20#include <asm/asm.h>
20#include <asm/asmmacro.h> 21#include <asm/asmmacro.h>
21#include <asm/irqflags.h> 22#include <asm/irqflags.h>
@@ -129,24 +130,25 @@
129#endif 130#endif
130 .endm 131 .endm
131 132
133#ifndef CONFIG_NO_EXCEPT_FILL
132 /* 134 /*
133 * Reserved space for exception handlers. 135 * Reserved space for exception handlers.
134 * Necessary for machines which link their kernels at KSEG0. 136 * Necessary for machines which link their kernels at KSEG0.
135 */ 137 */
136 .fill 0x400 138 .fill 0x400
139#endif
137 140
138EXPORT(stext) # used for profiling 141EXPORT(stext) # used for profiling
139EXPORT(_stext) 142EXPORT(_stext)
140 143
141#ifdef CONFIG_MIPS_SIM 144#ifdef CONFIG_BOOT_RAW
142 /* 145 /*
143 * Give us a fighting chance of running if execution beings at the 146 * Give us a fighting chance of running if execution beings at the
144 * kernel load address. This is needed because this platform does 147 * kernel load address. This is needed because this platform does
145 * not have a ELF loader yet. 148 * not have a ELF loader yet.
146 */ 149 */
147 j kernel_entry
148#endif
149 __INIT 150 __INIT
151#endif
150 152
151NESTED(kernel_entry, 16, sp) # kernel entry point 153NESTED(kernel_entry, 16, sp) # kernel entry point
152 154
@@ -197,9 +199,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
197 j start_kernel 199 j start_kernel
198 END(kernel_entry) 200 END(kernel_entry)
199 201
200#ifdef CONFIG_QEMU
201 __INIT 202 __INIT
202#endif
203 203
204#ifdef CONFIG_SMP 204#ifdef CONFIG_SMP
205/* 205/*
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
deleted file mode 100644
index 3dd561832e4c..000000000000
--- a/arch/mips/kernel/irq-mv6434x.c
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/kernel_stat.h>
15#include <linux/mv643xx.h>
16#include <linux/sched.h>
17
18#include <asm/io.h>
19#include <asm/irq.h>
20#include <asm/marvell.h>
21
22static unsigned int irq_base;
23
24static inline int ls1bit32(unsigned int x)
25{
26 int b = 31, s;
27
28 s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
29 s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
30 s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
31 s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
32 s = 1; if (x << 1 == 0) s = 0; b -= s;
33
34 return b;
35}
36
37/* mask off an interrupt -- 1 is enable, 0 is disable */
38static inline void mask_mv64340_irq(unsigned int irq)
39{
40 uint32_t value;
41
42 if (irq < (irq_base + 32)) {
43 value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
44 value &= ~(1 << (irq - irq_base));
45 MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
46 } else {
47 value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
48 value &= ~(1 << (irq - irq_base - 32));
49 MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
50 }
51}
52
53/* unmask an interrupt -- 1 is enable, 0 is disable */
54static inline void unmask_mv64340_irq(unsigned int irq)
55{
56 uint32_t value;
57
58 if (irq < (irq_base + 32)) {
59 value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
60 value |= 1 << (irq - irq_base);
61 MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
62 } else {
63 value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
64 value |= 1 << (irq - irq_base - 32);
65 MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
66 }
67}
68
69/*
70 * Interrupt handler for interrupts coming from the Marvell chip.
71 * It could be built in ethernet ports etc...
72 */
73void ll_mv64340_irq(void)
74{
75 unsigned int irq_src_low, irq_src_high;
76 unsigned int irq_mask_low, irq_mask_high;
77
78 /* read the interrupt status registers */
79 irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
80 irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
81 irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW);
82 irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH);
83
84 /* mask for just the interrupts we want */
85 irq_src_low &= irq_mask_low;
86 irq_src_high &= irq_mask_high;
87
88 if (irq_src_low)
89 do_IRQ(ls1bit32(irq_src_low) + irq_base);
90 else
91 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
92}
93
94struct irq_chip mv64340_irq_type = {
95 .name = "MV-64340",
96 .ack = mask_mv64340_irq,
97 .mask = mask_mv64340_irq,
98 .mask_ack = mask_mv64340_irq,
99 .unmask = unmask_mv64340_irq,
100};
101
102void __init mv64340_irq_init(unsigned int base)
103{
104 int i;
105
106 for (i = base; i < base + 64; i++)
107 set_irq_chip_and_handler(i, &mv64340_irq_type,
108 handle_level_irq);
109
110 irq_base = base;
111}
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
new file mode 100644
index 000000000000..ede5d73d652e
--- /dev/null
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -0,0 +1,176 @@
1/*
2 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
3 * Copyright (C) 2005 Mips Technologies, Inc
4 */
5#include <linux/cpu.h>
6#include <linux/cpumask.h>
7#include <linux/delay.h>
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/sched.h>
11#include <linux/security.h>
12#include <linux/types.h>
13#include <asm/uaccess.h>
14
15/*
16 * CPU mask used to set process affinity for MT VPEs/TCs with FPUs
17 */
18cpumask_t mt_fpu_cpumask;
19
20static int fpaff_threshold = -1;
21unsigned long mt_fpemul_threshold = 0;
22
23/*
24 * Replacement functions for the sys_sched_setaffinity() and
25 * sys_sched_getaffinity() system calls, so that we can integrate
26 * FPU affinity with the user's requested processor affinity.
27 * This code is 98% identical with the sys_sched_setaffinity()
28 * and sys_sched_getaffinity() system calls, and should be
29 * updated when kernel/sched.c changes.
30 */
31
32/*
33 * find_process_by_pid - find a process with a matching PID value.
34 * used in sys_sched_set/getaffinity() in kernel/sched.c, so
35 * cloned here.
36 */
37static inline struct task_struct *find_process_by_pid(pid_t pid)
38{
39 return pid ? find_task_by_pid(pid) : current;
40}
41
42
43/*
44 * mipsmt_sys_sched_setaffinity - set the cpu affinity of a process
45 */
46asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
47 unsigned long __user *user_mask_ptr)
48{
49 cpumask_t new_mask;
50 cpumask_t effective_mask;
51 int retval;
52 struct task_struct *p;
53
54 if (len < sizeof(new_mask))
55 return -EINVAL;
56
57 if (copy_from_user(&new_mask, user_mask_ptr, sizeof(new_mask)))
58 return -EFAULT;
59
60 lock_cpu_hotplug();
61 read_lock(&tasklist_lock);
62
63 p = find_process_by_pid(pid);
64 if (!p) {
65 read_unlock(&tasklist_lock);
66 unlock_cpu_hotplug();
67 return -ESRCH;
68 }
69
70 /*
71 * It is not safe to call set_cpus_allowed with the
72 * tasklist_lock held. We will bump the task_struct's
73 * usage count and drop tasklist_lock before invoking
74 * set_cpus_allowed.
75 */
76 get_task_struct(p);
77
78 retval = -EPERM;
79 if ((current->euid != p->euid) && (current->euid != p->uid) &&
80 !capable(CAP_SYS_NICE)) {
81 read_unlock(&tasklist_lock);
82 goto out_unlock;
83 }
84
85 retval = security_task_setscheduler(p, 0, NULL);
86 if (retval)
87 goto out_unlock;
88
89 /* Record new user-specified CPU set for future reference */
90 p->thread.user_cpus_allowed = new_mask;
91
92 /* Unlock the task list */
93 read_unlock(&tasklist_lock);
94
95 /* Compute new global allowed CPU set if necessary */
96 if ((p->thread.mflags & MF_FPUBOUND)
97 && cpus_intersects(new_mask, mt_fpu_cpumask)) {
98 cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
99 retval = set_cpus_allowed(p, effective_mask);
100 } else {
101 p->thread.mflags &= ~MF_FPUBOUND;
102 retval = set_cpus_allowed(p, new_mask);
103 }
104
105
106out_unlock:
107 put_task_struct(p);
108 unlock_cpu_hotplug();
109 return retval;
110}
111
112/*
113 * mipsmt_sys_sched_getaffinity - get the cpu affinity of a process
114 */
115asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
116 unsigned long __user *user_mask_ptr)
117{
118 unsigned int real_len;
119 cpumask_t mask;
120 int retval;
121 struct task_struct *p;
122
123 real_len = sizeof(mask);
124 if (len < real_len)
125 return -EINVAL;
126
127 lock_cpu_hotplug();
128 read_lock(&tasklist_lock);
129
130 retval = -ESRCH;
131 p = find_process_by_pid(pid);
132 if (!p)
133 goto out_unlock;
134 retval = security_task_getscheduler(p);
135 if (retval)
136 goto out_unlock;
137
138 cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map);
139
140out_unlock:
141 read_unlock(&tasklist_lock);
142 unlock_cpu_hotplug();
143 if (retval)
144 return retval;
145 if (copy_to_user(user_mask_ptr, &mask, real_len))
146 return -EFAULT;
147 return real_len;
148}
149
150
151static int __init fpaff_thresh(char *str)
152{
153 get_option(&str, &fpaff_threshold);
154 return 1;
155}
156__setup("fpaff=", fpaff_thresh);
157
158/*
159 * FPU Use Factor empirically derived from experiments on 34K
160 */
161#define FPUSEFACTOR 333
162
163static __init int mt_fp_affinity_init(void)
164{
165 if (fpaff_threshold >= 0) {
166 mt_fpemul_threshold = fpaff_threshold;
167 } else {
168 mt_fpemul_threshold =
169 (FPUSEFACTOR * (loops_per_jiffy/(500000/HZ))) / HZ;
170 }
171 printk(KERN_DEBUG "FPU Affinity set after %ld emulations\n",
172 mt_fpemul_threshold);
173
174 return 0;
175}
176arch_initcall(mt_fp_affinity_init);
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index ba01800b6018..1a7d89231299 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -6,7 +6,6 @@
6#include <linux/device.h> 6#include <linux/device.h>
7#include <linux/kernel.h> 7#include <linux/kernel.h>
8#include <linux/sched.h> 8#include <linux/sched.h>
9#include <linux/cpumask.h>
10#include <linux/module.h> 9#include <linux/module.h>
11#include <linux/interrupt.h> 10#include <linux/interrupt.h>
12#include <linux/security.h> 11#include <linux/security.h>
@@ -23,149 +22,6 @@
23#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
24 23
25/* 24/*
26 * CPU mask used to set process affinity for MT VPEs/TCs with FPUs
27 */
28
29cpumask_t mt_fpu_cpumask;
30
31#ifdef CONFIG_MIPS_MT_FPAFF
32
33#include <linux/cpu.h>
34#include <linux/delay.h>
35#include <asm/uaccess.h>
36
37unsigned long mt_fpemul_threshold = 0;
38
39/*
40 * Replacement functions for the sys_sched_setaffinity() and
41 * sys_sched_getaffinity() system calls, so that we can integrate
42 * FPU affinity with the user's requested processor affinity.
43 * This code is 98% identical with the sys_sched_setaffinity()
44 * and sys_sched_getaffinity() system calls, and should be
45 * updated when kernel/sched.c changes.
46 */
47
48/*
49 * find_process_by_pid - find a process with a matching PID value.
50 * used in sys_sched_set/getaffinity() in kernel/sched.c, so
51 * cloned here.
52 */
53static inline struct task_struct *find_process_by_pid(pid_t pid)
54{
55 return pid ? find_task_by_pid(pid) : current;
56}
57
58
59/*
60 * mipsmt_sys_sched_setaffinity - set the cpu affinity of a process
61 */
62asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
63 unsigned long __user *user_mask_ptr)
64{
65 cpumask_t new_mask;
66 cpumask_t effective_mask;
67 int retval;
68 struct task_struct *p;
69
70 if (len < sizeof(new_mask))
71 return -EINVAL;
72
73 if (copy_from_user(&new_mask, user_mask_ptr, sizeof(new_mask)))
74 return -EFAULT;
75
76 lock_cpu_hotplug();
77 read_lock(&tasklist_lock);
78
79 p = find_process_by_pid(pid);
80 if (!p) {
81 read_unlock(&tasklist_lock);
82 unlock_cpu_hotplug();
83 return -ESRCH;
84 }
85
86 /*
87 * It is not safe to call set_cpus_allowed with the
88 * tasklist_lock held. We will bump the task_struct's
89 * usage count and drop tasklist_lock before invoking
90 * set_cpus_allowed.
91 */
92 get_task_struct(p);
93
94 retval = -EPERM;
95 if ((current->euid != p->euid) && (current->euid != p->uid) &&
96 !capable(CAP_SYS_NICE)) {
97 read_unlock(&tasklist_lock);
98 goto out_unlock;
99 }
100
101 retval = security_task_setscheduler(p, 0, NULL);
102 if (retval)
103 goto out_unlock;
104
105 /* Record new user-specified CPU set for future reference */
106 p->thread.user_cpus_allowed = new_mask;
107
108 /* Unlock the task list */
109 read_unlock(&tasklist_lock);
110
111 /* Compute new global allowed CPU set if necessary */
112 if( (p->thread.mflags & MF_FPUBOUND)
113 && cpus_intersects(new_mask, mt_fpu_cpumask)) {
114 cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
115 retval = set_cpus_allowed(p, effective_mask);
116 } else {
117 p->thread.mflags &= ~MF_FPUBOUND;
118 retval = set_cpus_allowed(p, new_mask);
119 }
120
121
122out_unlock:
123 put_task_struct(p);
124 unlock_cpu_hotplug();
125 return retval;
126}
127
128/*
129 * mipsmt_sys_sched_getaffinity - get the cpu affinity of a process
130 */
131asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
132 unsigned long __user *user_mask_ptr)
133{
134 unsigned int real_len;
135 cpumask_t mask;
136 int retval;
137 struct task_struct *p;
138
139 real_len = sizeof(mask);
140 if (len < real_len)
141 return -EINVAL;
142
143 lock_cpu_hotplug();
144 read_lock(&tasklist_lock);
145
146 retval = -ESRCH;
147 p = find_process_by_pid(pid);
148 if (!p)
149 goto out_unlock;
150 retval = security_task_getscheduler(p);
151 if (retval)
152 goto out_unlock;
153
154 cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map);
155
156out_unlock:
157 read_unlock(&tasklist_lock);
158 unlock_cpu_hotplug();
159 if (retval)
160 return retval;
161 if (copy_to_user(user_mask_ptr, &mask, real_len))
162 return -EFAULT;
163 return real_len;
164}
165
166#endif /* CONFIG_MIPS_MT_FPAFF */
167
168/*
169 * Dump new MIPS MT state for the core. Does not leave TCs halted. 25 * Dump new MIPS MT state for the core. Does not leave TCs halted.
170 * Takes an argument which taken to be a pre-call MVPControl value. 26 * Takes an argument which taken to be a pre-call MVPControl value.
171 */ 27 */
@@ -195,27 +51,31 @@ void mips_mt_regdump(unsigned long mvpctl)
195 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 51 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
196 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 52 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
197 printk("-- per-VPE State --\n"); 53 printk("-- per-VPE State --\n");
198 for(i = 0; i < nvpe; i++) { 54 for (i = 0; i < nvpe; i++) {
199 for(tc = 0; tc < ntc; tc++) { 55 for (tc = 0; tc < ntc; tc++) {
200 settc(tc); 56 settc(tc);
201 if((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) { 57 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
202 printk(" VPE %d\n", i); 58 printk(" VPE %d\n", i);
203 printk(" VPEControl : %08lx\n", read_vpe_c0_vpecontrol()); 59 printk(" VPEControl : %08lx\n",
204 printk(" VPEConf0 : %08lx\n", read_vpe_c0_vpeconf0()); 60 read_vpe_c0_vpecontrol());
205 printk(" VPE%d.Status : %08lx\n", 61 printk(" VPEConf0 : %08lx\n",
206 i, read_vpe_c0_status()); 62 read_vpe_c0_vpeconf0());
207 printk(" VPE%d.EPC : %08lx\n", i, read_vpe_c0_epc()); 63 printk(" VPE%d.Status : %08lx\n",
208 printk(" VPE%d.Cause : %08lx\n", i, read_vpe_c0_cause()); 64 i, read_vpe_c0_status());
209 printk(" VPE%d.Config7 : %08lx\n", 65 printk(" VPE%d.EPC : %08lx\n",
210 i, read_vpe_c0_config7()); 66 i, read_vpe_c0_epc());
211 break; /* Next VPE */ 67 printk(" VPE%d.Cause : %08lx\n",
68 i, read_vpe_c0_cause());
69 printk(" VPE%d.Config7 : %08lx\n",
70 i, read_vpe_c0_config7());
71 break; /* Next VPE */
72 }
212 } 73 }
213 }
214 } 74 }
215 printk("-- per-TC State --\n"); 75 printk("-- per-TC State --\n");
216 for(tc = 0; tc < ntc; tc++) { 76 for (tc = 0; tc < ntc; tc++) {
217 settc(tc); 77 settc(tc);
218 if(read_tc_c0_tcbind() == read_c0_tcbind()) { 78 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
219 /* Are we dumping ourself? */ 79 /* Are we dumping ourself? */
220 haltval = 0; /* Then we're not halted, and mustn't be */ 80 haltval = 0; /* Then we're not halted, and mustn't be */
221 tcstatval = flags; /* And pre-dump TCStatus is flags */ 81 tcstatval = flags; /* And pre-dump TCStatus is flags */
@@ -310,17 +170,6 @@ static int __init ndflush(char *s)
310 return 1; 170 return 1;
311} 171}
312__setup("ndflush=", ndflush); 172__setup("ndflush=", ndflush);
313#ifdef CONFIG_MIPS_MT_FPAFF
314static int fpaff_threshold = -1;
315
316static int __init fpaff_thresh(char *str)
317{
318 get_option(&str, &fpaff_threshold);
319 return 1;
320}
321
322__setup("fpaff=", fpaff_thresh);
323#endif /* CONFIG_MIPS_MT_FPAFF */
324 173
325static unsigned int itc_base = 0; 174static unsigned int itc_base = 0;
326 175
@@ -376,20 +225,6 @@ void mips_mt_set_cpuoptions(void)
376 if (mt_n_dflushes != 1) 225 if (mt_n_dflushes != 1)
377 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes); 226 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
378 227
379#ifdef CONFIG_MIPS_MT_FPAFF
380 /* FPU Use Factor empirically derived from experiments on 34K */
381#define FPUSEFACTOR 333
382
383 if (fpaff_threshold >= 0) {
384 mt_fpemul_threshold = fpaff_threshold;
385 } else {
386 mt_fpemul_threshold =
387 (FPUSEFACTOR * (loops_per_jiffy/(500000/HZ))) / HZ;
388 }
389 printk("FPU Affinity set after %ld emulations\n",
390 mt_fpemul_threshold);
391#endif /* CONFIG_MIPS_MT_FPAFF */
392
393 if (itc_base != 0) { 228 if (itc_base != 0) {
394 /* 229 /*
395 * Configure ITC mapping. This code is very 230 * Configure ITC mapping. This code is very
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 5ddc2e9deecf..ec04f5a1a5ea 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -14,7 +14,6 @@
14#include <asm/cpu-features.h> 14#include <asm/cpu-features.h>
15#include <asm/mipsregs.h> 15#include <asm/mipsregs.h>
16#include <asm/processor.h> 16#include <asm/processor.h>
17#include <asm/watch.h>
18 17
19unsigned int vced_count, vcei_count; 18unsigned int vced_count, vcei_count;
20 19
@@ -84,6 +83,7 @@ static const char *cpu_name[] = {
84 [CPU_VR4181A] = "NEC VR4181A", 83 [CPU_VR4181A] = "NEC VR4181A",
85 [CPU_SR71000] = "Sandcraft SR71000", 84 [CPU_SR71000] = "Sandcraft SR71000",
86 [CPU_PR4450] = "Philips PR4450", 85 [CPU_PR4450] = "Philips PR4450",
86 [CPU_LOONGSON2] = "ICT Loongson-2",
87}; 87};
88 88
89 89
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 6bdfb5a9fa1a..8f4cf27c7157 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -46,7 +46,7 @@
46 * power and have a low exit latency (ie sit in a loop waiting for somebody to 46 * power and have a low exit latency (ie sit in a loop waiting for somebody to
47 * say that they'd like to reschedule) 47 * say that they'd like to reschedule)
48 */ 48 */
49ATTRIB_NORET void cpu_idle(void) 49void __noreturn cpu_idle(void)
50{ 50{
51 /* endless idle loop with no priority at all */ 51 /* endless idle loop with no priority at all */
52 while (1) { 52 while (1) {
@@ -213,7 +213,7 @@ int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr)
213/* 213/*
214 * Create a kernel thread 214 * Create a kernel thread
215 */ 215 */
216static ATTRIB_NORET void kernel_thread_helper(void *arg, int (*fn)(void *)) 216static void __noreturn kernel_thread_helper(void *arg, int (*fn)(void *))
217{ 217{
218 do_exit(fn(arg)); 218 do_exit(fn(arg));
219} 219}
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 4975da0bfb63..316685fca059 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -20,6 +20,7 @@
20#include <linux/highmem.h> 20#include <linux/highmem.h>
21#include <linux/console.h> 21#include <linux/console.h>
22#include <linux/pfn.h> 22#include <linux/pfn.h>
23#include <linux/debugfs.h>
23 24
24#include <asm/addrspace.h> 25#include <asm/addrspace.h>
25#include <asm/bootinfo.h> 26#include <asm/bootinfo.h>
@@ -574,3 +575,18 @@ __setup("nodsp", dsp_disable);
574 575
575unsigned long kernelsp[NR_CPUS]; 576unsigned long kernelsp[NR_CPUS];
576unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; 577unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
578
579#ifdef CONFIG_DEBUG_FS
580struct dentry *mips_debugfs_dir;
581static int __init debugfs_mips(void)
582{
583 struct dentry *d;
584
585 d = debugfs_create_dir("mips", NULL);
586 if (IS_ERR(d))
587 return PTR_ERR(d);
588 mips_debugfs_dir = d;
589 return 0;
590}
591arch_initcall(debugfs_mips);
592#endif
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index a1b017f2dbb3..be7362bc2c9a 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -52,7 +52,7 @@ EXPORT_SYMBOL(phys_cpu_present_map);
52EXPORT_SYMBOL(cpu_online_map); 52EXPORT_SYMBOL(cpu_online_map);
53 53
54extern void __init calibrate_delay(void); 54extern void __init calibrate_delay(void);
55extern ATTRIB_NORET void cpu_idle(void); 55extern void cpu_idle(void);
56 56
57/* 57/*
58 * First C code run on the secondary CPUs after being started up by 58 * First C code run on the secondary CPUs after being started up by
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 046b03b1705a..342d873b2ecc 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1104,7 +1104,7 @@ void smtc_idle_loop_hook(void)
1104 mtflags = dmt(); 1104 mtflags = dmt();
1105 pdb_msg = &id_ho_db_msg[0]; 1105 pdb_msg = &id_ho_db_msg[0];
1106 im = read_c0_status(); 1106 im = read_c0_status();
1107 vpe = cpu_data[smp_processor_id()].vpe_id; 1107 vpe = current_cpu_data.vpe_id;
1108 for (bit = 0; bit < 8; bit++) { 1108 for (bit = 0; bit < 8; bit++) {
1109 /* 1109 /*
1110 * In current prototype, I/O interrupts 1110 * In current prototype, I/O interrupts
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 9dd5a2df8eac..b947c61c0cc8 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -272,9 +272,8 @@ asmlinkage int sys_set_thread_area(unsigned long addr)
272 struct thread_info *ti = task_thread_info(current); 272 struct thread_info *ti = task_thread_info(current);
273 273
274 ti->tp_value = addr; 274 ti->tp_value = addr;
275 275 if (cpu_has_userlocal)
276 /* If some future MIPS implementation has this register in hardware, 276 write_c0_userlocal(addr);
277 * we will need to update it here (and in context switches). */
278 277
279 return 0; 278 return 0;
280} 279}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 3ea7863c4519..80ea4fa95bd9 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -39,7 +39,6 @@
39#include <asm/traps.h> 39#include <asm/traps.h>
40#include <asm/uaccess.h> 40#include <asm/uaccess.h>
41#include <asm/mmu_context.h> 41#include <asm/mmu_context.h>
42#include <asm/watch.h>
43#include <asm/types.h> 42#include <asm/types.h>
44#include <asm/stacktrace.h> 43#include <asm/stacktrace.h>
45 44
@@ -70,6 +69,7 @@ extern asmlinkage void handle_reserved(void);
70extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 69extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
71 struct mips_fpu_struct *ctx, int has_fpu); 70 struct mips_fpu_struct *ctx, int has_fpu);
72 71
72void (*board_watchpoint_handler)(struct pt_regs *regs);
73void (*board_be_init)(void); 73void (*board_be_init)(void);
74int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 74int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
75void (*board_nmi_handler_setup)(void); 75void (*board_nmi_handler_setup)(void);
@@ -311,7 +311,7 @@ void show_registers(struct pt_regs *regs)
311 311
312static DEFINE_SPINLOCK(die_lock); 312static DEFINE_SPINLOCK(die_lock);
313 313
314NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) 314void __noreturn die(const char * str, struct pt_regs * regs)
315{ 315{
316 static int die_counter; 316 static int die_counter;
317#ifdef CONFIG_MIPS_MT_SMTC 317#ifdef CONFIG_MIPS_MT_SMTC
@@ -753,6 +753,33 @@ asmlinkage void do_ri(struct pt_regs *regs)
753 force_sig(SIGILL, current); 753 force_sig(SIGILL, current);
754} 754}
755 755
756/*
757 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
758 * emulated more than some threshold number of instructions, force migration to
759 * a "CPU" that has FP support.
760 */
761static void mt_ase_fp_affinity(void)
762{
763#ifdef CONFIG_MIPS_MT_FPAFF
764 if (mt_fpemul_threshold > 0 &&
765 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
766 /*
767 * If there's no FPU present, or if the application has already
768 * restricted the allowed set to exclude any CPUs with FPUs,
769 * we'll skip the procedure.
770 */
771 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
772 cpumask_t tmask;
773
774 cpus_and(tmask, current->thread.user_cpus_allowed,
775 mt_fpu_cpumask);
776 set_cpus_allowed(current, tmask);
777 current->thread.mflags |= MF_FPUBOUND;
778 }
779 }
780#endif /* CONFIG_MIPS_MT_FPAFF */
781}
782
756asmlinkage void do_cpu(struct pt_regs *regs) 783asmlinkage void do_cpu(struct pt_regs *regs)
757{ 784{
758 unsigned int cpid; 785 unsigned int cpid;
@@ -786,36 +813,8 @@ asmlinkage void do_cpu(struct pt_regs *regs)
786 &current->thread.fpu, 0); 813 &current->thread.fpu, 0);
787 if (sig) 814 if (sig)
788 force_sig(sig, current); 815 force_sig(sig, current);
789#ifdef CONFIG_MIPS_MT_FPAFF 816 else
790 else { 817 mt_ase_fp_affinity();
791 /*
792 * MIPS MT processors may have fewer FPU contexts
793 * than CPU threads. If we've emulated more than
794 * some threshold number of instructions, force
795 * migration to a "CPU" that has FP support.
796 */
797 if(mt_fpemul_threshold > 0
798 && ((current->thread.emulated_fp++
799 > mt_fpemul_threshold))) {
800 /*
801 * If there's no FPU present, or if the
802 * application has already restricted
803 * the allowed set to exclude any CPUs
804 * with FPUs, we'll skip the procedure.
805 */
806 if (cpus_intersects(current->cpus_allowed,
807 mt_fpu_cpumask)) {
808 cpumask_t tmask;
809
810 cpus_and(tmask,
811 current->thread.user_cpus_allowed,
812 mt_fpu_cpumask);
813 set_cpus_allowed(current, tmask);
814 current->thread.mflags |= MF_FPUBOUND;
815 }
816 }
817 }
818#endif /* CONFIG_MIPS_MT_FPAFF */
819 } 818 }
820 819
821 return; 820 return;
@@ -835,6 +834,11 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
835 834
836asmlinkage void do_watch(struct pt_regs *regs) 835asmlinkage void do_watch(struct pt_regs *regs)
837{ 836{
837 if (board_watchpoint_handler) {
838 (*board_watchpoint_handler)(regs);
839 return;
840 }
841
838 /* 842 /*
839 * We use the watch exception where available to detect stack 843 * We use the watch exception where available to detect stack
840 * overflows. 844 * overflows.
@@ -1343,7 +1347,14 @@ void __init per_cpu_trap_init(void)
1343 set_c0_status(ST0_MX); 1347 set_c0_status(ST0_MX);
1344 1348
1345#ifdef CONFIG_CPU_MIPSR2 1349#ifdef CONFIG_CPU_MIPSR2
1346 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ 1350 if (cpu_has_mips_r2) {
1351 unsigned int enable = 0x0000000f;
1352
1353 if (cpu_has_userlocal)
1354 enable |= (1 << 29);
1355
1356 write_c0_hwrena(enable);
1357 }
1347#endif 1358#endif
1348 1359
1349#ifdef CONFIG_MIPS_MT_SMTC 1360#ifdef CONFIG_MIPS_MT_SMTC
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 18c4a3c45a31..8b9c34ffae18 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -77,6 +77,7 @@
77#include <linux/signal.h> 77#include <linux/signal.h>
78#include <linux/smp.h> 78#include <linux/smp.h>
79#include <linux/sched.h> 79#include <linux/sched.h>
80#include <linux/debugfs.h>
80#include <asm/asm.h> 81#include <asm/asm.h>
81#include <asm/branch.h> 82#include <asm/branch.h>
82#include <asm/byteorder.h> 83#include <asm/byteorder.h>
@@ -87,9 +88,18 @@
87#define STR(x) __STR(x) 88#define STR(x) __STR(x)
88#define __STR(x) #x 89#define __STR(x) #x
89 90
90#ifdef CONFIG_PROC_FS 91enum {
91unsigned long unaligned_instructions; 92 UNALIGNED_ACTION_QUIET,
93 UNALIGNED_ACTION_SIGNAL,
94 UNALIGNED_ACTION_SHOW,
95};
96#ifdef CONFIG_DEBUG_FS
97static u32 unaligned_instructions;
98static u32 unaligned_action;
99#else
100#define unaligned_action UNALIGNED_ACTION_QUIET
92#endif 101#endif
102extern void show_registers(struct pt_regs *regs);
93 103
94static inline int emulate_load_store_insn(struct pt_regs *regs, 104static inline int emulate_load_store_insn(struct pt_regs *regs,
95 void __user *addr, unsigned int __user *pc, 105 void __user *addr, unsigned int __user *pc,
@@ -459,7 +469,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
459 goto sigill; 469 goto sigill;
460 } 470 }
461 471
462#ifdef CONFIG_PROC_FS 472#ifdef CONFIG_DEBUG_FS
463 unaligned_instructions++; 473 unaligned_instructions++;
464#endif 474#endif
465 475
@@ -516,6 +526,10 @@ asmlinkage void do_ade(struct pt_regs *regs)
516 pc = (unsigned int __user *) exception_epc(regs); 526 pc = (unsigned int __user *) exception_epc(regs);
517 if (user_mode(regs) && (current->thread.mflags & MF_FIXADE) == 0) 527 if (user_mode(regs) && (current->thread.mflags & MF_FIXADE) == 0)
518 goto sigbus; 528 goto sigbus;
529 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
530 goto sigbus;
531 else if (unaligned_action == UNALIGNED_ACTION_SHOW)
532 show_registers(regs);
519 533
520 /* 534 /*
521 * Do branch emulation only if we didn't forward the exception. 535 * Do branch emulation only if we didn't forward the exception.
@@ -546,3 +560,24 @@ sigbus:
546 * XXX On return from the signal handler we should advance the epc 560 * XXX On return from the signal handler we should advance the epc
547 */ 561 */
548} 562}
563
564#ifdef CONFIG_DEBUG_FS
565extern struct dentry *mips_debugfs_dir;
566static int __init debugfs_unaligned(void)
567{
568 struct dentry *d;
569
570 if (!mips_debugfs_dir)
571 return -ENODEV;
572 d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
573 mips_debugfs_dir, &unaligned_instructions);
574 if (IS_ERR(d))
575 return PTR_ERR(d);
576 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
577 mips_debugfs_dir, &unaligned_action);
578 if (IS_ERR(d))
579 return PTR_ERR(d);
580 return 0;
581}
582__initcall(debugfs_unaligned);
583#endif
diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig
deleted file mode 100644
index 1d2ee8a9be13..000000000000
--- a/arch/mips/lasat/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
1config PICVUE
2 tristate "PICVUE LCD display driver"
3 depends on LASAT
4
5config PICVUE_PROC
6 tristate "PICVUE LCD display driver /proc interface"
7 depends on PICVUE
8
9config DS1603
10 bool "DS1603 RTC driver"
11 depends on LASAT
12
13config LASAT_SYSCTL
14 bool "LASAT sysctl interface"
15 depends on LASAT
diff --git a/arch/mips/lasat/Makefile b/arch/mips/lasat/Makefile
deleted file mode 100644
index 99f5046fdf49..000000000000
--- a/arch/mips/lasat/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
1#
2# Makefile for the LASAT specific kernel interface routines under Linux.
3#
4
5obj-y += reset.o setup.o prom.o lasat_board.o \
6 at93c.o interrupt.o
7
8obj-$(CONFIG_LASAT_SYSCTL) += sysctl.o
9obj-$(CONFIG_DS1603) += ds1603.o
10obj-$(CONFIG_PICVUE) += picvue.o
11obj-$(CONFIG_PICVUE_PROC) += picvue_proc.o
12
13clean:
14 make -C image clean
diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c
deleted file mode 100644
index ca26e554615e..000000000000
--- a/arch/mips/lasat/at93c.c
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Atmel AT93C46 serial eeprom driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/delay.h>
9#include <asm/lasat/lasat.h>
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "at93c.h"
14
15#define AT93C_ADDR_SHIFT 7
16#define AT93C_ADDR_MAX ((1 << AT93C_ADDR_SHIFT) - 1)
17#define AT93C_RCMD (0x6 << AT93C_ADDR_SHIFT)
18#define AT93C_WCMD (0x5 << AT93C_ADDR_SHIFT)
19#define AT93C_WENCMD 0x260
20#define AT93C_WDSCMD 0x200
21
22struct at93c_defs *at93c;
23
24static void at93c_reg_write(u32 val)
25{
26 *at93c->reg = val;
27}
28
29static u32 at93c_reg_read(void)
30{
31 u32 tmp = *at93c->reg;
32 return tmp;
33}
34
35static u32 at93c_datareg_read(void)
36{
37 u32 tmp = *at93c->rdata_reg;
38 return tmp;
39}
40
41static void at93c_cycle_clk(u32 data)
42{
43 at93c_reg_write(data | at93c->clk);
44 lasat_ndelay(250);
45 at93c_reg_write(data & ~at93c->clk);
46 lasat_ndelay(250);
47}
48
49static void at93c_write_databit(u8 bit)
50{
51 u32 data = at93c_reg_read();
52 if (bit)
53 data |= 1 << at93c->wdata_shift;
54 else
55 data &= ~(1 << at93c->wdata_shift);
56
57 at93c_reg_write(data);
58 lasat_ndelay(100);
59 at93c_cycle_clk(data);
60}
61
62static unsigned int at93c_read_databit(void)
63{
64 u32 data;
65
66 at93c_cycle_clk(at93c_reg_read());
67 data = (at93c_datareg_read() >> at93c->rdata_shift) & 1;
68 return data;
69}
70
71static u8 at93c_read_byte(void)
72{
73 int i;
74 u8 data = 0;
75
76 for (i = 0; i<=7; i++) {
77 data <<= 1;
78 data |= at93c_read_databit();
79 }
80 return data;
81}
82
83static void at93c_write_bits(u32 data, int size)
84{
85 int i;
86 int shift = size - 1;
87 u32 mask = (1 << shift);
88
89 for (i = 0; i < size; i++) {
90 at93c_write_databit((data & mask) >> shift);
91 data <<= 1;
92 }
93}
94
95static void at93c_init_op(void)
96{
97 at93c_reg_write((at93c_reg_read() | at93c->cs) & ~at93c->clk & ~(1 << at93c->rdata_shift));
98 lasat_ndelay(50);
99}
100
101static void at93c_end_op(void)
102{
103 at93c_reg_write(at93c_reg_read() & ~at93c->cs);
104 lasat_ndelay(250);
105}
106
107static void at93c_wait(void)
108{
109 at93c_init_op();
110 while (!at93c_read_databit())
111 ;
112 at93c_end_op();
113};
114
115static void at93c_disable_wp(void)
116{
117 at93c_init_op();
118 at93c_write_bits(AT93C_WENCMD, 10);
119 at93c_end_op();
120}
121
122static void at93c_enable_wp(void)
123{
124 at93c_init_op();
125 at93c_write_bits(AT93C_WDSCMD, 10);
126 at93c_end_op();
127}
128
129u8 at93c_read(u8 addr)
130{
131 u8 byte;
132 at93c_init_op();
133 at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_RCMD, 10);
134 byte = at93c_read_byte();
135 at93c_end_op();
136 return byte;
137}
138
139void at93c_write(u8 addr, u8 data)
140{
141 at93c_disable_wp();
142 at93c_init_op();
143 at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_WCMD, 10);
144 at93c_write_bits(data, 8);
145 at93c_end_op();
146 at93c_wait();
147 at93c_enable_wp();
148}
diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h
deleted file mode 100644
index cfe2f99b1d44..000000000000
--- a/arch/mips/lasat/at93c.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Atmel AT93C46 serial eeprom driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7
8extern struct at93c_defs {
9 volatile u32 *reg;
10 volatile u32 *rdata_reg;
11 int rdata_shift;
12 int wdata_shift;
13 u32 cs;
14 u32 clk;
15} *at93c;
16
17u8 at93c_read(u8 addr);
18void at93c_write(u8 addr, u8 data);
diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c
deleted file mode 100644
index 7dced67c55eb..000000000000
--- a/arch/mips/lasat/ds1603.c
+++ /dev/null
@@ -1,183 +0,0 @@
1/*
2 * Dallas Semiconductors 1603 RTC driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#include <linux/kernel.h>
8#include <asm/lasat/lasat.h>
9#include <linux/delay.h>
10#include <asm/lasat/ds1603.h>
11#include <asm/time.h>
12
13#include "ds1603.h"
14
15#define READ_TIME_CMD 0x81
16#define SET_TIME_CMD 0x80
17#define TRIMMER_SET_CMD 0xC0
18#define TRIMMER_VALUE_MASK 0x38
19#define TRIMMER_SHIFT 3
20
21struct ds_defs *ds1603 = NULL;
22
23/* HW specific register functions */
24static void rtc_reg_write(unsigned long val)
25{
26 *ds1603->reg = val;
27}
28
29static unsigned long rtc_reg_read(void)
30{
31 unsigned long tmp = *ds1603->reg;
32 return tmp;
33}
34
35static unsigned long rtc_datareg_read(void)
36{
37 unsigned long tmp = *ds1603->data_reg;
38 return tmp;
39}
40
41static void rtc_nrst_high(void)
42{
43 rtc_reg_write(rtc_reg_read() | ds1603->rst);
44}
45
46static void rtc_nrst_low(void)
47{
48 rtc_reg_write(rtc_reg_read() & ~ds1603->rst);
49}
50
51static void rtc_cycle_clock(unsigned long data)
52{
53 data |= ds1603->clk;
54 rtc_reg_write(data);
55 lasat_ndelay(250);
56 if (ds1603->data_reversed)
57 data &= ~ds1603->data;
58 else
59 data |= ds1603->data;
60 data &= ~ds1603->clk;
61 rtc_reg_write(data);
62 lasat_ndelay(250 + ds1603->huge_delay);
63}
64
65static void rtc_write_databit(unsigned int bit)
66{
67 unsigned long data = rtc_reg_read();
68 if (ds1603->data_reversed)
69 bit = !bit;
70 if (bit)
71 data |= ds1603->data;
72 else
73 data &= ~ds1603->data;
74
75 rtc_reg_write(data);
76 lasat_ndelay(50 + ds1603->huge_delay);
77 rtc_cycle_clock(data);
78}
79
80static unsigned int rtc_read_databit(void)
81{
82 unsigned int data;
83
84 data = (rtc_datareg_read() & (1 << ds1603->data_read_shift))
85 >> ds1603->data_read_shift;
86 rtc_cycle_clock(rtc_reg_read());
87 return data;
88}
89
90static void rtc_write_byte(unsigned int byte)
91{
92 int i;
93
94 for (i = 0; i<=7; i++) {
95 rtc_write_databit(byte & 1L);
96 byte >>= 1;
97 }
98}
99
100static void rtc_write_word(unsigned long word)
101{
102 int i;
103
104 for (i = 0; i<=31; i++) {
105 rtc_write_databit(word & 1L);
106 word >>= 1;
107 }
108}
109
110static unsigned long rtc_read_word(void)
111{
112 int i;
113 unsigned long word = 0;
114 unsigned long shift = 0;
115
116 for (i = 0; i<=31; i++) {
117 word |= rtc_read_databit() << shift;
118 shift++;
119 }
120 return word;
121}
122
123static void rtc_init_op(void)
124{
125 rtc_nrst_high();
126
127 rtc_reg_write(rtc_reg_read() & ~ds1603->clk);
128
129 lasat_ndelay(50);
130}
131
132static void rtc_end_op(void)
133{
134 rtc_nrst_low();
135 lasat_ndelay(1000);
136}
137
138/* interface */
139unsigned long ds1603_read(void)
140{
141 unsigned long word;
142 unsigned long flags;
143
144 spin_lock_irqsave(&rtc_lock, flags);
145 rtc_init_op();
146 rtc_write_byte(READ_TIME_CMD);
147 word = rtc_read_word();
148 rtc_end_op();
149 spin_unlock_irqrestore(&rtc_lock, flags);
150 return word;
151}
152
153int ds1603_set(unsigned long time)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&rtc_lock, flags);
158 rtc_init_op();
159 rtc_write_byte(SET_TIME_CMD);
160 rtc_write_word(time);
161 rtc_end_op();
162 spin_unlock_irqrestore(&rtc_lock, flags);
163
164 return 0;
165}
166
167void ds1603_set_trimmer(unsigned int trimval)
168{
169 rtc_init_op();
170 rtc_write_byte(((trimval << TRIMMER_SHIFT) & TRIMMER_VALUE_MASK)
171 | (TRIMMER_SET_CMD));
172 rtc_end_op();
173}
174
175void ds1603_disable(void)
176{
177 ds1603_set_trimmer(TRIMMER_DISABLE_RTC);
178}
179
180void ds1603_enable(void)
181{
182 ds1603_set_trimmer(TRIMMER_DEFAULT);
183}
diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h
deleted file mode 100644
index c2e5c76a379d..000000000000
--- a/arch/mips/lasat/ds1603.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Dallas Semiconductors 1603 RTC driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#ifndef __DS1603_H
8#define __DS1603_H
9
10struct ds_defs {
11 volatile u32 *reg;
12 volatile u32 *data_reg;
13 u32 rst;
14 u32 clk;
15 u32 data;
16 u32 data_read_shift;
17 char data_reversed;
18 u32 huge_delay;
19};
20
21extern struct ds_defs *ds1603;
22
23unsigned long ds1603_read(void);
24int ds1603_set(unsigned long);
25void ds1603_set_trimmer(unsigned int);
26void ds1603_enable(void);
27void ds1603_disable(void);
28void ds1603_init(struct ds_defs *);
29
30#define TRIMMER_DEFAULT 3
31#define TRIMMER_DISABLE_RTC 0
32
33#endif
diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile
deleted file mode 100644
index 35ecd6483ef6..000000000000
--- a/arch/mips/lasat/image/Makefile
+++ /dev/null
@@ -1,53 +0,0 @@
1#
2# MAKEFILE FOR THE MIPS LINUX BOOTLOADER AND ROM DEBUGGER
3#
4# i-data Networks
5#
6# Author: Thomas Horsten <thh@i-data.com>
7#
8
9ifndef Version
10 Version = "$(USER)-test"
11endif
12
13MKLASATIMG = mklasatimg
14MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200
15KERNEL_IMAGE = $(TOPDIR)/vmlinux
16KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ )
17KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ )
18
19LDSCRIPT= -L$(obj) -Tromscript.normal
20
21HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
22 -D_kernel_entry=0x$(KERNEL_ENTRY) \
23 -D VERSION="\"$(Version)\"" \
24 -D TIMESTAMP=$(shell date +%s)
25
26$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE)
27 $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $<
28
29OBJECTS = head.o kImage.o
30
31rom.sw: $(obj)/rom.sw
32
33$(obj)/rom.sw: $(obj)/rom.bin
34 $(MKLASATIMG) -o $@ -k $^ -m $(MKLASATIMG_ARCH)
35
36$(obj)/rom.bin: $(obj)/rom
37 $(OBJCOPY) -O binary -S $^ $@
38
39# Rule to make the bootloader
40$(obj)/rom: $(addprefix $(obj)/,$(OBJECTS))
41 $(LD) $(LDFLAGS) $(LDSCRIPT) -o $@ $^
42
43$(obj)/%.o: $(obj)/%.gz
44 $(LD) -r -o $@ -b binary $<
45
46$(obj)/%.gz: $(obj)/%.bin
47 gzip -cf -9 $< > $@
48
49$(obj)/kImage.bin: $(KERNEL_IMAGE)
50 $(OBJCOPY) -O binary -S $^ $@
51
52clean:
53 rm -f rom rom.bin rom.sw kImage.bin kImage.o
diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S
deleted file mode 100644
index efb95f2609c2..000000000000
--- a/arch/mips/lasat/image/head.S
+++ /dev/null
@@ -1,31 +0,0 @@
1#include <asm/lasat/head.h>
2
3 .text
4 .section .text.start, "ax"
5 .set noreorder
6 .set mips3
7
8 /* Magic words identifying a software image */
9 .word LASAT_K_MAGIC0_VAL
10 .word LASAT_K_MAGIC1_VAL
11
12 /* Image header version */
13 .word 0x00000002
14
15 /* image start and size */
16 .word _image_start
17 .word _image_size
18
19 /* start of kernel and entrypoint in uncompressed image */
20 .word _kernel_start
21 .word _kernel_entry
22
23 /* Here we have room for future flags */
24
25 .org 0x40
26reldate:
27 .word TIMESTAMP
28
29 .org 0x50
30release:
31 .string VERSION
diff --git a/arch/mips/lasat/image/romscript.normal b/arch/mips/lasat/image/romscript.normal
deleted file mode 100644
index 988f8ad189cb..000000000000
--- a/arch/mips/lasat/image/romscript.normal
+++ /dev/null
@@ -1,23 +0,0 @@
1OUTPUT_ARCH(mips)
2
3SECTIONS
4{
5 .text :
6 {
7 *(.text.start)
8 }
9
10 /* Data in ROM */
11
12 .data ALIGN(0x10) :
13 {
14 *(.data)
15 }
16 _image_start = ADDR(.data);
17 _image_size = SIZEOF(.data);
18
19 .other :
20 {
21 *(.*)
22 }
23}
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
deleted file mode 100644
index 9a622b9a1051..000000000000
--- a/arch/mips/lasat/interrupt.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines for generic manipulation of the interrupts found on the
19 * Lasat boards.
20 */
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/slab.h>
24#include <linux/interrupt.h>
25#include <linux/kernel_stat.h>
26
27#include <asm/bootinfo.h>
28#include <asm/irq.h>
29#include <asm/lasat/lasatint.h>
30#include <asm/time.h>
31#include <asm/gdb-stub.h>
32
33static volatile int *lasat_int_status = NULL;
34static volatile int *lasat_int_mask = NULL;
35static volatile int lasat_int_mask_shift;
36
37void disable_lasat_irq(unsigned int irq_nr)
38{
39 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
40}
41
42void enable_lasat_irq(unsigned int irq_nr)
43{
44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
45}
46
47static struct irq_chip lasat_irq_type = {
48 .name = "Lasat",
49 .ack = disable_lasat_irq,
50 .mask = disable_lasat_irq,
51 .mask_ack = disable_lasat_irq,
52 .unmask = enable_lasat_irq,
53};
54
55static inline int ls1bit32(unsigned int x)
56{
57 int b = 31, s;
58
59 s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
60 s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
61 s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
62 s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
63 s = 1; if (x << 1 == 0) s = 0; b -= s;
64
65 return b;
66}
67
68static unsigned long (* get_int_status)(void);
69
70static unsigned long get_int_status_100(void)
71{
72 return *lasat_int_status & *lasat_int_mask;
73}
74
75static unsigned long get_int_status_200(void)
76{
77 unsigned long int_status;
78
79 int_status = *lasat_int_status;
80 int_status &= (int_status >> LASATINT_MASK_SHIFT_200) & 0xffff;
81 return int_status;
82}
83
84asmlinkage void plat_irq_dispatch(void)
85{
86 unsigned long int_status;
87 unsigned int cause = read_c0_cause();
88 int irq;
89
90 if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
91 ll_timer_interrupt(7);
92 return;
93 }
94
95 int_status = get_int_status();
96
97 /* if int_status == 0, then the interrupt has already been cleared */
98 if (int_status) {
99 irq = ls1bit32(int_status);
100
101 do_IRQ(irq);
102 }
103}
104
105void __init arch_init_irq(void)
106{
107 int i;
108
109 switch (mips_machtype) {
110 case MACH_LASAT_100:
111 lasat_int_status = (void *)LASAT_INT_STATUS_REG_100;
112 lasat_int_mask = (void *)LASAT_INT_MASK_REG_100;
113 lasat_int_mask_shift = LASATINT_MASK_SHIFT_100;
114 get_int_status = get_int_status_100;
115 *lasat_int_mask = 0;
116 break;
117 case MACH_LASAT_200:
118 lasat_int_status = (void *)LASAT_INT_STATUS_REG_200;
119 lasat_int_mask = (void *)LASAT_INT_MASK_REG_200;
120 lasat_int_mask_shift = LASATINT_MASK_SHIFT_200;
121 get_int_status = get_int_status_200;
122 *lasat_int_mask &= 0xffff;
123 break;
124 default:
125 panic("arch_init_irq: mips_machtype incorrect");
126 }
127
128 for (i = 0; i <= LASATINT_END; i++)
129 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
130}
diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c
deleted file mode 100644
index fbe9a87bd0ad..000000000000
--- a/arch/mips/lasat/lasat_board.c
+++ /dev/null
@@ -1,279 +0,0 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines specific to the LASAT boards
19 */
20#include <linux/types.h>
21#include <linux/crc32.h>
22#include <asm/lasat/lasat.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/ctype.h>
26#include <asm/bootinfo.h>
27#include <asm/addrspace.h>
28#include "at93c.h"
29/* New model description table */
30#include "lasat_models.h"
31
32#define EEPROM_CRC(data, len) (~0 ^ crc32(~0, data, len))
33
34struct lasat_info lasat_board_info;
35
36void update_bcastaddr(void);
37
38int EEPROMRead(unsigned int pos, unsigned char *data, int len)
39{
40 int i;
41
42 for (i=0; i<len; i++)
43 *data++ = at93c_read(pos++);
44
45 return 0;
46}
47int EEPROMWrite(unsigned int pos, unsigned char *data, int len)
48{
49 int i;
50
51 for (i=0; i<len; i++)
52 at93c_write(pos++, *data++);
53
54 return 0;
55}
56
57static void init_flash_sizes(void)
58{
59 int i;
60 unsigned long *lb = lasat_board_info.li_flashpart_base;
61 unsigned long *ls = lasat_board_info.li_flashpart_size;
62
63 ls[LASAT_MTD_BOOTLOADER] = 0x40000;
64 ls[LASAT_MTD_SERVICE] = 0xC0000;
65 ls[LASAT_MTD_NORMAL] = 0x100000;
66
67 if (mips_machtype == MACH_LASAT_100) {
68 lasat_board_info.li_flash_base = 0x1e000000;
69
70 lb[LASAT_MTD_BOOTLOADER] = 0x1e400000;
71
72 if (lasat_board_info.li_flash_size > 0x200000) {
73 ls[LASAT_MTD_CONFIG] = 0x100000;
74 ls[LASAT_MTD_FS] = 0x500000;
75 }
76 } else {
77 lasat_board_info.li_flash_base = 0x10000000;
78
79 if (lasat_board_info.li_flash_size < 0x1000000) {
80 lb[LASAT_MTD_BOOTLOADER] = 0x10000000;
81 ls[LASAT_MTD_CONFIG] = 0x100000;
82 if (lasat_board_info.li_flash_size >= 0x400000) {
83 ls[LASAT_MTD_FS] = lasat_board_info.li_flash_size - 0x300000;
84 }
85 }
86 }
87
88 for (i = 1; i < LASAT_MTD_LAST; i++)
89 lb[i] = lb[i-1] + ls[i-1];
90}
91
92int lasat_init_board_info(void)
93{
94 int c;
95 unsigned long crc;
96 unsigned long cfg0, cfg1;
97 const product_info_t *ppi;
98 int i_n_base_models = N_BASE_MODELS;
99 const char * const * i_txt_base_models = txt_base_models;
100 int i_n_prids = N_PRIDS;
101
102 memset(&lasat_board_info, 0, sizeof(lasat_board_info));
103
104 /* First read the EEPROM info */
105 EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
106 sizeof(struct lasat_eeprom_struct));
107
108 /* Check the CRC */
109 crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info),
110 sizeof(struct lasat_eeprom_struct) - 4);
111
112 if (crc != lasat_board_info.li_eeprom_info.crc32) {
113 printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM CRC does "
114 "not match calculated, attempting to soldier on...\n");
115 }
116
117 if (lasat_board_info.li_eeprom_info.version != LASAT_EEPROM_VERSION) {
118 printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM version "
119 "%d, wanted version %d, attempting to soldier on...\n",
120 (unsigned int)lasat_board_info.li_eeprom_info.version,
121 LASAT_EEPROM_VERSION);
122 }
123
124 cfg0 = lasat_board_info.li_eeprom_info.cfg[0];
125 cfg1 = lasat_board_info.li_eeprom_info.cfg[1];
126
127 if ( LASAT_W0_DSCTYPE(cfg0) != 1) {
128 printk(KERN_WARNING "WARNING...\nWARNING...\n"
129 "Invalid configuration read from EEPROM, attempting to "
130 "soldier on...");
131 }
132 /* We have a valid configuration */
133
134 switch (LASAT_W0_SDRAMBANKSZ(cfg0)) {
135 case 0:
136 lasat_board_info.li_memsize = 0x0800000;
137 break;
138 case 1:
139 lasat_board_info.li_memsize = 0x1000000;
140 break;
141 case 2:
142 lasat_board_info.li_memsize = 0x2000000;
143 break;
144 case 3:
145 lasat_board_info.li_memsize = 0x4000000;
146 break;
147 case 4:
148 lasat_board_info.li_memsize = 0x8000000;
149 break;
150 default:
151 lasat_board_info.li_memsize = 0;
152 }
153
154 switch (LASAT_W0_SDRAMBANKS(cfg0)) {
155 case 0:
156 break;
157 case 1:
158 lasat_board_info.li_memsize *= 2;
159 break;
160 default:
161 break;
162 }
163
164 switch (LASAT_W0_BUSSPEED(cfg0)) {
165 case 0x0:
166 lasat_board_info.li_bus_hz = 60000000;
167 break;
168 case 0x1:
169 lasat_board_info.li_bus_hz = 66000000;
170 break;
171 case 0x2:
172 lasat_board_info.li_bus_hz = 66666667;
173 break;
174 case 0x3:
175 lasat_board_info.li_bus_hz = 80000000;
176 break;
177 case 0x4:
178 lasat_board_info.li_bus_hz = 83333333;
179 break;
180 case 0x5:
181 lasat_board_info.li_bus_hz = 100000000;
182 break;
183 }
184
185 switch (LASAT_W0_CPUCLK(cfg0)) {
186 case 0x0:
187 lasat_board_info.li_cpu_hz =
188 lasat_board_info.li_bus_hz;
189 break;
190 case 0x1:
191 lasat_board_info.li_cpu_hz =
192 lasat_board_info.li_bus_hz +
193 (lasat_board_info.li_bus_hz >> 1);
194 break;
195 case 0x2:
196 lasat_board_info.li_cpu_hz =
197 lasat_board_info.li_bus_hz +
198 lasat_board_info.li_bus_hz;
199 break;
200 case 0x3:
201 lasat_board_info.li_cpu_hz =
202 lasat_board_info.li_bus_hz +
203 lasat_board_info.li_bus_hz +
204 (lasat_board_info.li_bus_hz >> 1);
205 break;
206 case 0x4:
207 lasat_board_info.li_cpu_hz =
208 lasat_board_info.li_bus_hz +
209 lasat_board_info.li_bus_hz +
210 lasat_board_info.li_bus_hz;
211 break;
212 }
213
214 /* Flash size */
215 switch (LASAT_W1_FLASHSIZE(cfg1)) {
216 case 0:
217 lasat_board_info.li_flash_size = 0x200000;
218 break;
219 case 1:
220 lasat_board_info.li_flash_size = 0x400000;
221 break;
222 case 2:
223 lasat_board_info.li_flash_size = 0x800000;
224 break;
225 case 3:
226 lasat_board_info.li_flash_size = 0x1000000;
227 break;
228 case 4:
229 lasat_board_info.li_flash_size = 0x2000000;
230 break;
231 }
232
233 init_flash_sizes();
234
235 lasat_board_info.li_bmid = LASAT_W0_BMID(cfg0);
236 lasat_board_info.li_prid = lasat_board_info.li_eeprom_info.prid;
237 if (lasat_board_info.li_prid == 0xffff || lasat_board_info.li_prid == 0)
238 lasat_board_info.li_prid = lasat_board_info.li_bmid;
239
240 /* Base model stuff */
241 if (lasat_board_info.li_bmid > i_n_base_models)
242 lasat_board_info.li_bmid = i_n_base_models;
243 strcpy(lasat_board_info.li_bmstr, i_txt_base_models[lasat_board_info.li_bmid]);
244
245 /* Product ID dependent values */
246 c = lasat_board_info.li_prid;
247 if (c >= i_n_prids) {
248 strcpy(lasat_board_info.li_namestr, "Unknown Model");
249 strcpy(lasat_board_info.li_typestr, "Unknown Type");
250 } else {
251 ppi = &vendor_info_table[0].vi_product_info[c];
252 strcpy(lasat_board_info.li_namestr, ppi->pi_name);
253 if (ppi->pi_type)
254 strcpy(lasat_board_info.li_typestr, ppi->pi_type);
255 else
256 sprintf(lasat_board_info.li_typestr, "%d",10*c);
257 }
258
259#if defined(CONFIG_INET) && defined(CONFIG_SYSCTL)
260 update_bcastaddr();
261#endif
262
263 return 0;
264}
265
266void lasat_write_eeprom_info(void)
267{
268 unsigned long crc;
269
270 /* Generate the CRC */
271 crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info),
272 sizeof(struct lasat_eeprom_struct) - 4);
273 lasat_board_info.li_eeprom_info.crc32 = crc;
274
275 /* Write the EEPROM info */
276 EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
277 sizeof(struct lasat_eeprom_struct));
278}
279
diff --git a/arch/mips/lasat/lasat_models.h b/arch/mips/lasat/lasat_models.h
deleted file mode 100644
index ae0c5d0bd403..000000000000
--- a/arch/mips/lasat/lasat_models.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Model description tables
3 */
4
5typedef struct product_info_t {
6 const char *pi_name;
7 const char *pi_type;
8} product_info_t;
9
10typedef struct vendor_info_t {
11 const char *vi_name;
12 const product_info_t *vi_product_info;
13} vendor_info_t;
14
15/*
16 * Base models
17 */
18static const char * const txt_base_models[] = {
19 "MQ 2", "MQ Pro", "SP 25", "SP 50", "SP 100", "SP 5000", "SP 7000", "SP 1000", "Unknown"
20};
21#define N_BASE_MODELS (sizeof(txt_base_models)/sizeof(char*)-1)
22
23/*
24 * Eicon Networks
25 */
26static const char txt_en_mq[] = "Masquerade";
27static const char txt_en_sp[] = "Safepipe";
28
29static const product_info_t product_info_eicon[] = {
30 { txt_en_mq, "II" }, /* 0 */
31 { txt_en_mq, "Pro" }, /* 1 */
32 { txt_en_sp, "25" }, /* 2 */
33 { txt_en_sp, "50" }, /* 3 */
34 { txt_en_sp, "100" }, /* 4 */
35 { txt_en_sp, "5000" }, /* 5 */
36 { txt_en_sp, "7000" }, /* 6 */
37 { txt_en_sp, "30" }, /* 7 */
38 { txt_en_sp, "5100" }, /* 8 */
39 { txt_en_sp, "7100" }, /* 9 */
40 { txt_en_sp, "1110" }, /* 10 */
41 { txt_en_sp, "3020" }, /* 11 */
42 { txt_en_sp, "3030" }, /* 12 */
43 { txt_en_sp, "5020" }, /* 13 */
44 { txt_en_sp, "5030" }, /* 14 */
45 { txt_en_sp, "1120" }, /* 15 */
46 { txt_en_sp, "1130" }, /* 16 */
47 { txt_en_sp, "6010" }, /* 17 */
48 { txt_en_sp, "6110" }, /* 18 */
49 { txt_en_sp, "6210" }, /* 19 */
50 { txt_en_sp, "1020" }, /* 20 */
51 { txt_en_sp, "1040" }, /* 21 */
52 { txt_en_sp, "1050" }, /* 22 */
53 { txt_en_sp, "1060" }, /* 23 */
54};
55#define N_PRIDS (sizeof(product_info_eicon)/sizeof(product_info_t))
56
57/*
58 * The vendor table
59 */
60static vendor_info_t const vendor_info_table[] = {
61 { "Eicon Networks", product_info_eicon },
62};
63#define N_VENDORS (sizeof(vendor_info_table)/sizeof(vendor_info_t))
diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
deleted file mode 100644
index 9ae82c3ffb07..000000000000
--- a/arch/mips/lasat/picvue.c
+++ /dev/null
@@ -1,240 +0,0 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/delay.h>
9#include <asm/bootinfo.h>
10#include <asm/lasat/lasat.h>
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15
16#include "picvue.h"
17
18#define PVC_BUSY 0x80
19#define PVC_NLINES 2
20#define PVC_DISPMEM 80
21#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES
22
23struct pvc_defs *picvue = NULL;
24
25DECLARE_MUTEX(pvc_sem);
26
27static void pvc_reg_write(u32 val)
28{
29 *picvue->reg = val;
30}
31
32static u32 pvc_reg_read(void)
33{
34 u32 tmp = *picvue->reg;
35 return tmp;
36}
37
38static void pvc_write_byte(u32 data, u8 byte)
39{
40 data |= picvue->e;
41 pvc_reg_write(data);
42 data &= ~picvue->data_mask;
43 data |= byte << picvue->data_shift;
44 pvc_reg_write(data);
45 ndelay(220);
46 pvc_reg_write(data & ~picvue->e);
47 ndelay(220);
48}
49
50static u8 pvc_read_byte(u32 data)
51{
52 u8 byte;
53
54 data |= picvue->e;
55 pvc_reg_write(data);
56 ndelay(220);
57 byte = (pvc_reg_read() & picvue->data_mask) >> picvue->data_shift;
58 data &= ~picvue->e;
59 pvc_reg_write(data);
60 ndelay(220);
61 return byte;
62}
63
64static u8 pvc_read_data(void)
65{
66 u32 data = pvc_reg_read();
67 u8 byte;
68 data |= picvue->rw;
69 data &= ~picvue->rs;
70 pvc_reg_write(data);
71 ndelay(40);
72 byte = pvc_read_byte(data);
73 data |= picvue->rs;
74 pvc_reg_write(data);
75 return byte;
76}
77
78#define TIMEOUT 1000
79static int pvc_wait(void)
80{
81 int i = TIMEOUT;
82 int err = 0;
83
84 while ((pvc_read_data() & PVC_BUSY) && i)
85 i--;
86 if (i == 0)
87 err = -ETIME;
88
89 return err;
90}
91
92#define MODE_INST 0
93#define MODE_DATA 1
94static void pvc_write(u8 byte, int mode)
95{
96 u32 data = pvc_reg_read();
97 data &= ~picvue->rw;
98 if (mode == MODE_DATA)
99 data |= picvue->rs;
100 else
101 data &= ~picvue->rs;
102 pvc_reg_write(data);
103 ndelay(40);
104 pvc_write_byte(data, byte);
105 if (mode == MODE_DATA)
106 data &= ~picvue->rs;
107 else
108 data |= picvue->rs;
109 pvc_reg_write(data);
110 pvc_wait();
111}
112
113void pvc_write_string(const unsigned char *str, u8 addr, int line)
114{
115 int i = 0;
116
117 if (line > 0 && (PVC_NLINES > 1))
118 addr += 0x40 * line;
119 pvc_write(0x80 | addr, MODE_INST);
120
121 while (*str != 0 && i < PVC_LINELEN) {
122 pvc_write(*str++, MODE_DATA);
123 i++;
124 }
125}
126
127void pvc_write_string_centered(const unsigned char *str, int line)
128{
129 int len = strlen(str);
130 u8 addr;
131
132 if (len > PVC_VISIBLE_CHARS)
133 addr = 0;
134 else
135 addr = (PVC_VISIBLE_CHARS - strlen(str))/2;
136
137 pvc_write_string(str, addr, line);
138}
139
140void pvc_dump_string(const unsigned char *str)
141{
142 int len = strlen(str);
143
144 pvc_write_string(str, 0, 0);
145 if (len > PVC_VISIBLE_CHARS)
146 pvc_write_string(&str[PVC_VISIBLE_CHARS], 0, 1);
147}
148
149#define BM_SIZE 8
150#define MAX_PROGRAMMABLE_CHARS 8
151int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE])
152{
153 int i;
154 int addr;
155
156 if (charnum > MAX_PROGRAMMABLE_CHARS)
157 return -ENOENT;
158
159 addr = charnum * 8;
160 pvc_write(0x40 | addr, MODE_INST);
161
162 for (i=0; i<BM_SIZE; i++)
163 pvc_write(bitmap[i], MODE_DATA);
164 return 0;
165}
166
167#define FUNC_SET_CMD 0x20
168#define EIGHT_BYTE (1 << 4)
169#define FOUR_BYTE 0
170#define TWO_LINES (1 << 3)
171#define ONE_LINE 0
172#define LARGE_FONT (1 << 2)
173#define SMALL_FONT 0
174static void pvc_funcset(u8 cmd)
175{
176 pvc_write(FUNC_SET_CMD | (cmd & (EIGHT_BYTE|TWO_LINES|LARGE_FONT)), MODE_INST);
177}
178
179#define ENTRYMODE_CMD 0x4
180#define AUTO_INC (1 << 1)
181#define AUTO_DEC 0
182#define CURSOR_FOLLOWS_DISP (1 << 0)
183static void pvc_entrymode(u8 cmd)
184{
185 pvc_write(ENTRYMODE_CMD | (cmd & (AUTO_INC|CURSOR_FOLLOWS_DISP)), MODE_INST);
186}
187
188#define DISP_CNT_CMD 0x08
189#define DISP_OFF 0
190#define DISP_ON (1 << 2)
191#define CUR_ON (1 << 1)
192#define CUR_BLINK (1 << 0)
193void pvc_dispcnt(u8 cmd)
194{
195 pvc_write(DISP_CNT_CMD | (cmd & (DISP_ON|CUR_ON|CUR_BLINK)), MODE_INST);
196}
197
198#define MOVE_CMD 0x10
199#define DISPLAY (1 << 3)
200#define CURSOR 0
201#define RIGHT (1 << 2)
202#define LEFT 0
203void pvc_move(u8 cmd)
204{
205 pvc_write(MOVE_CMD | (cmd & (DISPLAY|RIGHT)), MODE_INST);
206}
207
208#define CLEAR_CMD 0x1
209void pvc_clear(void)
210{
211 pvc_write(CLEAR_CMD, MODE_INST);
212}
213
214#define HOME_CMD 0x2
215void pvc_home(void)
216{
217 pvc_write(HOME_CMD, MODE_INST);
218}
219
220int pvc_init(void)
221{
222 u8 cmd = EIGHT_BYTE;
223
224 if (PVC_NLINES == 2)
225 cmd |= (SMALL_FONT|TWO_LINES);
226 else
227 cmd |= (LARGE_FONT|ONE_LINE);
228 pvc_funcset(cmd);
229 pvc_dispcnt(DISP_ON);
230 pvc_entrymode(AUTO_INC);
231
232 pvc_clear();
233 pvc_write_string_centered("Display", 0);
234 pvc_write_string_centered("Initialized", 1);
235
236 return 0;
237}
238
239module_init(pvc_init);
240MODULE_LICENSE("GPL");
diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h
deleted file mode 100644
index 2a96bf971897..000000000000
--- a/arch/mips/lasat/picvue.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <asm/semaphore.h>
8
9struct pvc_defs {
10 volatile u32 *reg;
11 u32 data_shift;
12 u32 data_mask;
13 u32 e;
14 u32 rw;
15 u32 rs;
16};
17
18extern struct pvc_defs *picvue;
19
20#define PVC_NLINES 2
21#define PVC_DISPMEM 80
22#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES
23#define PVC_VISIBLE_CHARS 16
24
25void pvc_write_string(const unsigned char *str, u8 addr, int line);
26void pvc_write_string_centered(const unsigned char *str, int line);
27void pvc_dump_string(const unsigned char *str);
28
29#define BM_SIZE 8
30#define MAX_PROGRAMMABLE_CHARS 8
31int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]);
32
33void pvc_dispcnt(u8 cmd);
34#define DISP_OFF 0
35#define DISP_ON (1 << 2)
36#define CUR_ON (1 << 1)
37#define CUR_BLINK (1 << 0)
38
39void pvc_move(u8 cmd);
40#define DISPLAY (1 << 3)
41#define CURSOR 0
42#define RIGHT (1 << 2)
43#define LEFT 0
44
45void pvc_clear(void);
46void pvc_home(void);
47
48extern struct semaphore pvc_sem;
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
deleted file mode 100644
index cce7cddcdb08..000000000000
--- a/arch/mips/lasat/picvue_proc.c
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/errno.h>
11
12#include <linux/proc_fs.h>
13#include <linux/interrupt.h>
14
15#include <linux/timer.h>
16
17#include "picvue.h"
18
19static char pvc_lines[PVC_NLINES][PVC_LINELEN+1];
20static int pvc_linedata[PVC_NLINES];
21static struct proc_dir_entry *pvc_display_dir;
22static char *pvc_linename[PVC_NLINES] = {"line1", "line2"};
23#define DISPLAY_DIR_NAME "display"
24static int scroll_dir = 0, scroll_interval = 0;
25
26static struct timer_list timer;
27
28static void pvc_display(unsigned long data) {
29 int i;
30
31 pvc_clear();
32 for (i=0; i<PVC_NLINES; i++)
33 pvc_write_string(pvc_lines[i], 0, i);
34}
35
36static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0);
37
38static int pvc_proc_read_line(char *page, char **start,
39 off_t off, int count,
40 int *eof, void *data)
41{
42 char *origpage = page;
43 int lineno = *(int *)data;
44
45 if (lineno < 0 || lineno > PVC_NLINES) {
46 printk("proc_read_line: invalid lineno %d\n", lineno);
47 return 0;
48 }
49
50 down(&pvc_sem);
51 page += sprintf(page, "%s\n", pvc_lines[lineno]);
52 up(&pvc_sem);
53
54 return page - origpage;
55}
56
57static int pvc_proc_write_line(struct file *file, const char *buffer,
58 unsigned long count, void *data)
59{
60 int origcount = count;
61 int lineno = *(int *)data;
62
63 if (lineno < 0 || lineno > PVC_NLINES) {
64 printk("proc_write_line: invalid lineno %d\n", lineno);
65 return origcount;
66 }
67
68 if (count > PVC_LINELEN)
69 count = PVC_LINELEN;
70
71 if (buffer[count-1] == '\n')
72 count--;
73
74 down(&pvc_sem);
75 strncpy(pvc_lines[lineno], buffer, count);
76 pvc_lines[lineno][count] = '\0';
77 up(&pvc_sem);
78
79 tasklet_schedule(&pvc_display_tasklet);
80
81 return origcount;
82}
83
84static int pvc_proc_write_scroll(struct file *file, const char *buffer,
85 unsigned long count, void *data)
86{
87 int origcount = count;
88 int cmd = simple_strtol(buffer, NULL, 10);
89
90 down(&pvc_sem);
91 if (scroll_interval != 0)
92 del_timer(&timer);
93
94 if (cmd == 0) {
95 scroll_dir = 0;
96 scroll_interval = 0;
97 } else {
98 if (cmd < 0) {
99 scroll_dir = -1;
100 scroll_interval = -cmd;
101 } else {
102 scroll_dir = 1;
103 scroll_interval = cmd;
104 }
105 add_timer(&timer);
106 }
107 up(&pvc_sem);
108
109 return origcount;
110}
111
112static int pvc_proc_read_scroll(char *page, char **start,
113 off_t off, int count,
114 int *eof, void *data)
115{
116 char *origpage = page;
117
118 down(&pvc_sem);
119 page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
120 up(&pvc_sem);
121
122 return page - origpage;
123}
124
125
126void pvc_proc_timerfunc(unsigned long data)
127{
128 if (scroll_dir < 0)
129 pvc_move(DISPLAY|RIGHT);
130 else if (scroll_dir > 0)
131 pvc_move(DISPLAY|LEFT);
132
133 timer.expires = jiffies + scroll_interval;
134 add_timer(&timer);
135}
136
137static void pvc_proc_cleanup(void)
138{
139 int i;
140 for (i=0; i<PVC_NLINES; i++)
141 remove_proc_entry(pvc_linename[i], pvc_display_dir);
142 remove_proc_entry("scroll", pvc_display_dir);
143 remove_proc_entry(DISPLAY_DIR_NAME, NULL);
144
145 del_timer(&timer);
146}
147
148static int __init pvc_proc_init(void)
149{
150 struct proc_dir_entry *proc_entry;
151 int i;
152
153 pvc_display_dir = proc_mkdir(DISPLAY_DIR_NAME, NULL);
154 if (pvc_display_dir == NULL)
155 goto error;
156
157 for (i=0; i<PVC_NLINES; i++) {
158 strcpy(pvc_lines[i], "");
159 pvc_linedata[i] = i;
160 }
161 for (i=0; i<PVC_NLINES; i++) {
162 proc_entry = create_proc_entry(pvc_linename[i], 0644, pvc_display_dir);
163 if (proc_entry == NULL)
164 goto error;
165 proc_entry->read_proc = pvc_proc_read_line;
166 proc_entry->write_proc = pvc_proc_write_line;
167 proc_entry->data = &pvc_linedata[i];
168 }
169 proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir);
170 if (proc_entry == NULL)
171 goto error;
172 proc_entry->write_proc = pvc_proc_write_scroll;
173 proc_entry->read_proc = pvc_proc_read_scroll;
174
175 init_timer(&timer);
176 timer.function = pvc_proc_timerfunc;
177
178 return 0;
179error:
180 pvc_proc_cleanup();
181 return -ENOMEM;
182}
183
184module_init(pvc_proc_init);
185module_exit(pvc_proc_cleanup);
186MODULE_LICENSE("GPL");
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
deleted file mode 100644
index 812c6ac366be..000000000000
--- a/arch/mips/lasat/prom.c
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * PROM interface routines.
3 */
4#include <linux/types.h>
5#include <linux/init.h>
6#include <linux/string.h>
7#include <linux/ctype.h>
8#include <linux/kernel.h>
9#include <linux/mm.h>
10#include <linux/bootmem.h>
11#include <linux/ioport.h>
12#include <asm/bootinfo.h>
13#include <asm/lasat/lasat.h>
14#include <asm/cpu.h>
15
16#include "at93c.h"
17#include <asm/lasat/eeprom.h>
18#include "prom.h"
19
20#define RESET_VECTOR 0xbfc00000
21#define PROM_JUMP_TABLE_ENTRY(n) (*((u32 *)(RESET_VECTOR + 0x20) + n))
22#define PROM_DISPLAY_ADDR PROM_JUMP_TABLE_ENTRY(0)
23#define PROM_PUTC_ADDR PROM_JUMP_TABLE_ENTRY(1)
24#define PROM_MONITOR_ADDR PROM_JUMP_TABLE_ENTRY(2)
25
26static void null_prom_display(const char *string, int pos, int clear)
27{
28}
29
30static void null_prom_monitor(void)
31{
32}
33
34static void null_prom_putc(char c)
35{
36}
37
38/* these are functions provided by the bootloader */
39static void (* __prom_putc)(char c) = null_prom_putc;
40
41void prom_putchar(char c)
42{
43 __prom_putc(c);
44}
45
46void (* prom_display)(const char *string, int pos, int clear) =
47 null_prom_display;
48void (* prom_monitor)(void) = null_prom_monitor;
49
50unsigned int lasat_ndelay_divider;
51
52static void setup_prom_vectors(void)
53{
54 u32 version = *(u32 *)(RESET_VECTOR + 0x90);
55
56 if (version >= 307) {
57 prom_display = (void *)PROM_DISPLAY_ADDR;
58 __prom_putc = (void *)PROM_PUTC_ADDR;
59 prom_monitor = (void *)PROM_MONITOR_ADDR;
60 }
61 printk("prom vectors set up\n");
62}
63
64static struct at93c_defs at93c_defs[N_MACHTYPES] = {
65 {(void *)AT93C_REG_100, (void *)AT93C_RDATA_REG_100, AT93C_RDATA_SHIFT_100,
66 AT93C_WDATA_SHIFT_100, AT93C_CS_M_100, AT93C_CLK_M_100},
67 {(void *)AT93C_REG_200, (void *)AT93C_RDATA_REG_200, AT93C_RDATA_SHIFT_200,
68 AT93C_WDATA_SHIFT_200, AT93C_CS_M_200, AT93C_CLK_M_200},
69};
70
71void __init prom_init(void)
72{
73 int argc = fw_arg0;
74 char **argv = (char **) fw_arg1;
75
76 setup_prom_vectors();
77
78 if (current_cpu_data.cputype == CPU_R5000) {
79 printk("LASAT 200 board\n");
80 mips_machtype = MACH_LASAT_200;
81 lasat_ndelay_divider = LASAT_200_DIVIDER;
82 } else {
83 printk("LASAT 100 board\n");
84 mips_machtype = MACH_LASAT_100;
85 lasat_ndelay_divider = LASAT_100_DIVIDER;
86 }
87
88 at93c = &at93c_defs[mips_machtype];
89
90 lasat_init_board_info(); /* Read info from EEPROM */
91
92 mips_machgroup = MACH_GROUP_LASAT;
93
94 /* Get the command line */
95 if (argc > 0) {
96 strncpy(arcs_cmdline, argv[0], CL_SIZE-1);
97 arcs_cmdline[CL_SIZE-1] = '\0';
98 }
99
100 /* Set the I/O base address */
101 set_io_port_base(KSEG1);
102
103 /* Set memory regions */
104 ioport_resource.start = 0;
105 ioport_resource.end = 0xffffffff; /* Wrong, fixme. */
106
107 add_memory_region(0, lasat_board_info.li_memsize, BOOT_MEM_RAM);
108}
109
110void __init prom_free_prom_memory(void)
111{
112}
113
114const char *get_system_type(void)
115{
116 return lasat_board_info.li_bmstr;
117}
diff --git a/arch/mips/lasat/prom.h b/arch/mips/lasat/prom.h
deleted file mode 100644
index 019d45fbd268..000000000000
--- a/arch/mips/lasat/prom.h
+++ /dev/null
@@ -1,5 +0,0 @@
1#ifndef PROM_H
2#define PROM_H
3extern void (* prom_display)(const char *string, int pos, int clear);
4extern void (* prom_monitor)(void);
5#endif
diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c
deleted file mode 100644
index 9e22acf03083..000000000000
--- a/arch/mips/lasat/reset.c
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Reset the LASAT board.
19 */
20#include <linux/kernel.h>
21#include <linux/pm.h>
22
23#include <asm/reboot.h>
24#include <asm/system.h>
25#include <asm/lasat/lasat.h>
26
27#include "picvue.h"
28#include "prom.h"
29
30static void lasat_machine_restart(char *command);
31static void lasat_machine_halt(void);
32
33/* Used to set machine to boot in service mode via /proc interface */
34int lasat_boot_to_service = 0;
35
36static void lasat_machine_restart(char *command)
37{
38 local_irq_disable();
39
40 if (lasat_boot_to_service) {
41 printk("machine_restart: Rebooting to service mode\n");
42 *(volatile unsigned int *)0xa0000024 = 0xdeadbeef;
43 *(volatile unsigned int *)0xa00000fc = 0xfedeabba;
44 }
45 *lasat_misc->reset_reg = 0xbedead;
46 for (;;) ;
47}
48
49#define MESSAGE "System halted"
50static void lasat_machine_halt(void)
51{
52 local_irq_disable();
53
54 /* Disable interrupts and loop forever */
55 printk(KERN_NOTICE MESSAGE "\n");
56#ifdef CONFIG_PICVUE
57 pvc_clear();
58 pvc_write_string(MESSAGE, 0, 0);
59#endif
60 prom_monitor();
61 for (;;) ;
62}
63
64void lasat_reboot_setup(void)
65{
66 _machine_restart = lasat_machine_restart;
67 _machine_halt = lasat_machine_halt;
68 pm_power_off = lasat_machine_halt;
69}
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
deleted file mode 100644
index 488007f13988..000000000000
--- a/arch/mips/lasat/setup.c
+++ /dev/null
@@ -1,182 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
4 *
5 * Thomas Horsten <thh@lasat.com>
6 * Copyright (C) 2000 LASAT Networks A/S.
7 *
8 * Brian Murphy <brian@murphy.dk>
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * Lasat specific setup.
24 */
25#include <linux/init.h>
26#include <linux/sched.h>
27#include <linux/pci.h>
28#include <linux/interrupt.h>
29#include <linux/tty.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32
33#include <asm/time.h>
34#include <asm/cpu.h>
35#include <asm/bootinfo.h>
36#include <asm/irq.h>
37#include <asm/lasat/lasat.h>
38#include <asm/lasat/serial.h>
39
40#ifdef CONFIG_PICVUE
41#include <linux/notifier.h>
42#endif
43
44#include "ds1603.h"
45#include <asm/lasat/ds1603.h>
46#include <asm/lasat/picvue.h>
47#include <asm/lasat/eeprom.h>
48
49#include "prom.h"
50
51int lasat_command_line = 0;
52void lasatint_init(void);
53
54extern void lasat_reboot_setup(void);
55extern void pcisetup(void);
56extern void edhac_init(void *, void *, void *);
57extern void addrflt_init(void);
58
59struct lasat_misc lasat_misc_info[N_MACHTYPES] = {
60 {(void *)KSEG1ADDR(0x1c840000), (void *)KSEG1ADDR(0x1c800000), 2},
61 {(void *)KSEG1ADDR(0x11080000), (void *)KSEG1ADDR(0x11000000), 6}
62};
63
64struct lasat_misc *lasat_misc = NULL;
65
66#ifdef CONFIG_DS1603
67static struct ds_defs ds_defs[N_MACHTYPES] = {
68 { (void *)DS1603_REG_100, (void *)DS1603_REG_100,
69 DS1603_RST_100, DS1603_CLK_100, DS1603_DATA_100,
70 DS1603_DATA_SHIFT_100, 0, 0 },
71 { (void *)DS1603_REG_200, (void *)DS1603_DATA_REG_200,
72 DS1603_RST_200, DS1603_CLK_200, DS1603_DATA_200,
73 DS1603_DATA_READ_SHIFT_200, 1, 2000 }
74};
75#endif
76
77#ifdef CONFIG_PICVUE
78#include "picvue.h"
79static struct pvc_defs pvc_defs[N_MACHTYPES] = {
80 { (void *)PVC_REG_100, PVC_DATA_SHIFT_100, PVC_DATA_M_100,
81 PVC_E_100, PVC_RW_100, PVC_RS_100 },
82 { (void *)PVC_REG_200, PVC_DATA_SHIFT_200, PVC_DATA_M_200,
83 PVC_E_200, PVC_RW_200, PVC_RS_200 }
84};
85#endif
86
87static int lasat_panic_display(struct notifier_block *this,
88 unsigned long event, void *ptr)
89{
90#ifdef CONFIG_PICVUE
91 unsigned char *string = ptr;
92 if (string == NULL)
93 string = "Kernel Panic";
94 pvc_dump_string(string);
95#endif
96 return NOTIFY_DONE;
97}
98
99static int lasat_panic_prom_monitor(struct notifier_block *this,
100 unsigned long event, void *ptr)
101{
102 prom_monitor();
103 return NOTIFY_DONE;
104}
105
106static struct notifier_block lasat_panic_block[] =
107{
108 { lasat_panic_display, NULL, INT_MAX },
109 { lasat_panic_prom_monitor, NULL, INT_MIN }
110};
111
112static void lasat_time_init(void)
113{
114 mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2;
115}
116
117void __init plat_timer_setup(struct irqaction *irq)
118{
119 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
120}
121
122#define DYNAMIC_SERIAL_INIT
123#ifdef DYNAMIC_SERIAL_INIT
124void __init serial_init(void)
125{
126#ifdef CONFIG_SERIAL_8250
127 struct uart_port s;
128
129 memset(&s, 0, sizeof(s));
130
131 s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
132 s.iotype = UPIO_MEM;
133
134 if (mips_machtype == MACH_LASAT_100) {
135 s.uartclk = LASAT_BASE_BAUD_100 * 16;
136 s.irq = LASATINT_UART_100;
137 s.regshift = LASAT_UART_REGS_SHIFT_100;
138 s.membase = (char *)KSEG1ADDR(LASAT_UART_REGS_BASE_100);
139 } else {
140 s.uartclk = LASAT_BASE_BAUD_200 * 16;
141 s.irq = LASATINT_UART_200;
142 s.regshift = LASAT_UART_REGS_SHIFT_200;
143 s.membase = (char *)KSEG1ADDR(LASAT_UART_REGS_BASE_200);
144 }
145
146 if (early_serial_setup(&s) != 0)
147 printk(KERN_ERR "Serial setup failed!\n");
148#endif
149}
150#endif
151
152void __init plat_mem_setup(void)
153{
154 int i;
155 lasat_misc = &lasat_misc_info[mips_machtype];
156#ifdef CONFIG_PICVUE
157 picvue = &pvc_defs[mips_machtype];
158#endif
159
160 /* Set up panic notifier */
161 for (i = 0; i < sizeof(lasat_panic_block) / sizeof(struct notifier_block); i++)
162 atomic_notifier_chain_register(&panic_notifier_list,
163 &lasat_panic_block[i]);
164
165 lasat_reboot_setup();
166
167 board_time_init = lasat_time_init;
168
169#ifdef CONFIG_DS1603
170 ds1603 = &ds_defs[mips_machtype];
171 rtc_mips_get_time = ds1603_read;
172 rtc_mips_set_time = ds1603_set;
173#endif
174
175#ifdef DYNAMIC_SERIAL_INIT
176 serial_init();
177#endif
178 /* Switch from prom exception handler to normal mode */
179 change_c0_status(ST0_BEV,0);
180
181 pr_info("Lasat specific initialization complete\n");
182}
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
deleted file mode 100644
index 699ab1886ceb..000000000000
--- a/arch/mips/lasat/sysctl.c
+++ /dev/null
@@ -1,441 +0,0 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines specific to the LASAT boards
19 */
20#include <linux/types.h>
21#include <asm/lasat/lasat.h>
22
23#include <linux/module.h>
24#include <linux/sysctl.h>
25#include <linux/stddef.h>
26#include <linux/init.h>
27#include <linux/fs.h>
28#include <linux/ctype.h>
29#include <linux/string.h>
30#include <linux/net.h>
31#include <linux/inet.h>
32#include <linux/mutex.h>
33#include <asm/uaccess.h>
34
35#include "sysctl.h"
36#include "ds1603.h"
37
38static DEFINE_MUTEX(lasat_info_mutex);
39
40/* Strategy function to write EEPROM after changing string entry */
41int sysctl_lasatstring(ctl_table *table, int *name, int nlen,
42 void *oldval, size_t *oldlenp,
43 void *newval, size_t newlen)
44{
45 int r;
46 mutex_lock(&lasat_info_mutex);
47 r = sysctl_string(table, name,
48 nlen, oldval, oldlenp, newval, newlen);
49 if (r < 0) {
50 mutex_unlock(&lasat_info_mutex);
51 return r;
52 }
53 if (newval && newlen) {
54 lasat_write_eeprom_info();
55 }
56 mutex_unlock(&lasat_info_mutex);
57 return 1;
58}
59
60
61/* And the same for proc */
62int proc_dolasatstring(ctl_table *table, int write, struct file *filp,
63 void *buffer, size_t *lenp, loff_t *ppos)
64{
65 int r;
66 mutex_lock(&lasat_info_mutex);
67 r = proc_dostring(table, write, filp, buffer, lenp, ppos);
68 if ( (!write) || r) {
69 mutex_unlock(&lasat_info_mutex);
70 return r;
71 }
72 lasat_write_eeprom_info();
73 mutex_unlock(&lasat_info_mutex);
74 return 0;
75}
76
77/* proc function to write EEPROM after changing int entry */
78int proc_dolasatint(ctl_table *table, int write, struct file *filp,
79 void *buffer, size_t *lenp, loff_t *ppos)
80{
81 int r;
82 mutex_lock(&lasat_info_mutex);
83 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
84 if ( (!write) || r) {
85 mutex_unlock(&lasat_info_mutex);
86 return r;
87 }
88 lasat_write_eeprom_info();
89 mutex_unlock(&lasat_info_mutex);
90 return 0;
91}
92
93static int rtctmp;
94
95#ifdef CONFIG_DS1603
96/* proc function to read/write RealTime Clock */
97int proc_dolasatrtc(ctl_table *table, int write, struct file *filp,
98 void *buffer, size_t *lenp, loff_t *ppos)
99{
100 int r;
101 mutex_lock(&lasat_info_mutex);
102 if (!write) {
103 rtctmp = ds1603_read();
104 /* check for time < 0 and set to 0 */
105 if (rtctmp < 0)
106 rtctmp = 0;
107 }
108 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
109 if ( (!write) || r) {
110 mutex_unlock(&lasat_info_mutex);
111 return r;
112 }
113 ds1603_set(rtctmp);
114 mutex_unlock(&lasat_info_mutex);
115 return 0;
116}
117#endif
118
119/* Sysctl for setting the IP addresses */
120int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen,
121 void *oldval, size_t *oldlenp,
122 void *newval, size_t newlen)
123{
124 int r;
125 mutex_lock(&lasat_info_mutex);
126 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
127 if (r < 0) {
128 mutex_unlock(&lasat_info_mutex);
129 return r;
130 }
131 if (newval && newlen) {
132 lasat_write_eeprom_info();
133 }
134 mutex_unlock(&lasat_info_mutex);
135 return 1;
136}
137
138#ifdef CONFIG_DS1603
139/* Same for RTC */
140int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen,
141 void *oldval, size_t *oldlenp,
142 void *newval, size_t newlen)
143{
144 int r;
145 mutex_lock(&lasat_info_mutex);
146 rtctmp = ds1603_read();
147 if (rtctmp < 0)
148 rtctmp = 0;
149 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
150 if (r < 0) {
151 mutex_unlock(&lasat_info_mutex);
152 return r;
153 }
154 if (newval && newlen) {
155 ds1603_set(rtctmp);
156 }
157 mutex_unlock(&lasat_info_mutex);
158 return 1;
159}
160#endif
161
162#ifdef CONFIG_INET
163static char lasat_bcastaddr[16];
164
165void update_bcastaddr(void)
166{
167 unsigned int ip;
168
169 ip = (lasat_board_info.li_eeprom_info.ipaddr &
170 lasat_board_info.li_eeprom_info.netmask) |
171 ~lasat_board_info.li_eeprom_info.netmask;
172
173 sprintf(lasat_bcastaddr, "%d.%d.%d.%d",
174 (ip ) & 0xff,
175 (ip >> 8) & 0xff,
176 (ip >> 16) & 0xff,
177 (ip >> 24) & 0xff);
178}
179
180static char proc_lasat_ipbuf[32];
181/* Parsing of IP address */
182int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
183 void *buffer, size_t *lenp, loff_t *ppos)
184{
185 int len;
186 unsigned int ip;
187 char *p, c;
188
189 if (!table->data || !table->maxlen || !*lenp ||
190 (*ppos && !write)) {
191 *lenp = 0;
192 return 0;
193 }
194
195 mutex_lock(&lasat_info_mutex);
196 if (write) {
197 len = 0;
198 p = buffer;
199 while (len < *lenp) {
200 if(get_user(c, p++)) {
201 mutex_unlock(&lasat_info_mutex);
202 return -EFAULT;
203 }
204 if (c == 0 || c == '\n')
205 break;
206 len++;
207 }
208 if (len >= sizeof(proc_lasat_ipbuf)-1)
209 len = sizeof(proc_lasat_ipbuf) - 1;
210 if (copy_from_user(proc_lasat_ipbuf, buffer, len))
211 {
212 mutex_unlock(&lasat_info_mutex);
213 return -EFAULT;
214 }
215 proc_lasat_ipbuf[len] = 0;
216 *ppos += *lenp;
217 /* Now see if we can convert it to a valid IP */
218 ip = in_aton(proc_lasat_ipbuf);
219 *(unsigned int *)(table->data) = ip;
220 lasat_write_eeprom_info();
221 } else {
222 ip = *(unsigned int *)(table->data);
223 sprintf(proc_lasat_ipbuf, "%d.%d.%d.%d",
224 (ip ) & 0xff,
225 (ip >> 8) & 0xff,
226 (ip >> 16) & 0xff,
227 (ip >> 24) & 0xff);
228 len = strlen(proc_lasat_ipbuf);
229 if (len > *lenp)
230 len = *lenp;
231 if (len)
232 if(copy_to_user(buffer, proc_lasat_ipbuf, len)) {
233 mutex_unlock(&lasat_info_mutex);
234 return -EFAULT;
235 }
236 if (len < *lenp) {
237 if(put_user('\n', ((char *) buffer) + len)) {
238 mutex_unlock(&lasat_info_mutex);
239 return -EFAULT;
240 }
241 len++;
242 }
243 *lenp = len;
244 *ppos += len;
245 }
246 update_bcastaddr();
247 mutex_unlock(&lasat_info_mutex);
248 return 0;
249}
250#endif /* defined(CONFIG_INET) */
251
252static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
253 void *oldval, size_t *oldlenp,
254 void *newval, size_t newlen)
255{
256 int r;
257
258 mutex_lock(&lasat_info_mutex);
259 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
260 if (r < 0) {
261 mutex_unlock(&lasat_info_mutex);
262 return r;
263 }
264
265 if (newval && newlen)
266 {
267 if (name && *name == LASAT_PRID)
268 lasat_board_info.li_eeprom_info.prid = *(int*)newval;
269
270 lasat_write_eeprom_info();
271 lasat_init_board_info();
272 }
273 mutex_unlock(&lasat_info_mutex);
274
275 return 0;
276}
277
278int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp,
279 void *buffer, size_t *lenp, loff_t *ppos)
280{
281 int r;
282 mutex_lock(&lasat_info_mutex);
283 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
284 if ( (!write) || r) {
285 mutex_unlock(&lasat_info_mutex);
286 return r;
287 }
288 if (filp && filp->f_path.dentry)
289 {
290 if (!strcmp(filp->f_path.dentry->d_name.name, "prid"))
291 lasat_board_info.li_eeprom_info.prid = lasat_board_info.li_prid;
292 if (!strcmp(filp->f_path.dentry->d_name.name, "debugaccess"))
293 lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess;
294 }
295 lasat_write_eeprom_info();
296 mutex_unlock(&lasat_info_mutex);
297 return 0;
298}
299
300extern int lasat_boot_to_service;
301
302#ifdef CONFIG_SYSCTL
303
304static ctl_table lasat_table[] = {
305 {
306 .ctl_name = CTL_UNNUMBERED,
307 .procname = "cpu-hz",
308 .data = &lasat_board_info.li_cpu_hz,
309 .maxlen = sizeof(int),
310 .mode = 0444,
311 .proc_handler = &proc_dointvec,
312 .strategy = &sysctl_intvec
313 },
314 {
315 .ctl_name = CTL_UNNUMBERED,
316 .procname = "bus-hz",
317 .data = &lasat_board_info.li_bus_hz,
318 .maxlen = sizeof(int),
319 .mode = 0444,
320 .proc_handler = &proc_dointvec,
321 .strategy = &sysctl_intvec
322 },
323 {
324 .ctl_name = CTL_UNNUMBERED,
325 .procname = "bmid",
326 .data = &lasat_board_info.li_bmid,
327 .maxlen = sizeof(int),
328 .mode = 0444,
329 .proc_handler = &proc_dointvec,
330 .strategy = &sysctl_intvec
331 },
332 {
333 .ctl_name = CTL_UNNUMBERED,
334 .procname = "prid",
335 .data = &lasat_board_info.li_prid,
336 .maxlen = sizeof(int),
337 .mode = 0644,
338 .proc_handler = &proc_lasat_eeprom_value,
339 .strategy = &sysctl_lasat_eeprom_value
340 },
341#ifdef CONFIG_INET
342 {
343 .ctl_name = CTL_UNNUMBERED,
344 .procname = "ipaddr",
345 .data = &lasat_board_info.li_eeprom_info.ipaddr,
346 .maxlen = sizeof(int),
347 .mode = 0644,
348 .proc_handler = &proc_lasat_ip,
349 .strategy = &sysctl_lasat_intvec
350 },
351 {
352 .ctl_name = LASAT_NETMASK,
353 .procname = "netmask",
354 .data = &lasat_board_info.li_eeprom_info.netmask,
355 .maxlen = sizeof(int),
356 .mode = 0644,
357 .proc_handler = &proc_lasat_ip,
358 .strategy = &sysctl_lasat_intvec
359 },
360 {
361 .ctl_name = CTL_UNNUMBERED,
362 .procname = "bcastaddr",
363 .data = &lasat_bcastaddr,
364 .maxlen = sizeof(lasat_bcastaddr),
365 .mode = 0600,
366 .proc_handler = &proc_dostring,
367 .strategy = &sysctl_string
368 },
369#endif
370 {
371 .ctl_name = CTL_UNNUMBERED,
372 .procname = "passwd_hash",
373 .data = &lasat_board_info.li_eeprom_info.passwd_hash,
374 .maxlen = sizeof(lasat_board_info.li_eeprom_info.passwd_hash),
375 .mode = 0600,
376 .proc_handler = &proc_dolasatstring,
377 .strategy = &sysctl_lasatstring
378 },
379 {
380 .ctl_name = CTL_UNNUMBERED,
381 .procname = "boot-service",
382 .data = &lasat_boot_to_service,
383 .maxlen = sizeof(int),
384 .mode = 0644,
385 .proc_handler = &proc_dointvec,
386 .strategy = &sysctl_intvec
387 },
388#ifdef CONFIG_DS1603
389 {
390 .ctl_name = CTL_UNNUMBERED,
391 .procname = "rtc",
392 .data = &rtctmp,
393 .maxlen = sizeof(int),
394 .mode = 0644,
395 .proc_handler = &proc_dolasatrtc,
396 .strategy = &sysctl_lasat_rtc
397 },
398#endif
399 {
400 .ctl_name = CTL_UNNUMBERED,
401 .procname = "namestr",
402 .data = &lasat_board_info.li_namestr,
403 .maxlen = sizeof(lasat_board_info.li_namestr),
404 .mode = 0444,
405 .proc_handler = &proc_dostring,
406 .strategy = &sysctl_string
407 },
408 {
409 .ctl_name = CTL_UNNUMBERED,
410 .procname = "typestr",
411 .data = &lasat_board_info.li_typestr,
412 .maxlen = sizeof(lasat_board_info.li_typestr),
413 .mode = 0444,
414 .proc_handler = &proc_dostring,
415 .strategy = &sysctl_string
416 },
417 {}
418};
419
420static ctl_table lasat_root_table[] = {
421 {
422 .ctl_name = CTL_UNNUMBERED,
423 .procname = "lasat",
424 .mode = 0555,
425 .child = lasat_table
426 },
427 {}
428};
429
430static int __init lasat_register_sysctl(void)
431{
432 struct ctl_table_header *lasat_table_header;
433
434 lasat_table_header =
435 register_sysctl_table(lasat_root_table);
436
437 return 0;
438}
439
440__initcall(lasat_register_sysctl);
441#endif /* CONFIG_SYSCTL */
diff --git a/arch/mips/lasat/sysctl.h b/arch/mips/lasat/sysctl.h
deleted file mode 100644
index 4d139d2adbdf..000000000000
--- a/arch/mips/lasat/sysctl.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * LASAT sysctl values
3 */
4
5#ifndef _LASAT_SYSCTL_H
6#define _LASAT_SYSCTL_H
7
8/* /proc/sys/lasat */
9enum {
10 LASAT_CPU_HZ=1,
11 LASAT_BUS_HZ,
12 LASAT_MODEL,
13 LASAT_PRID,
14 LASAT_IPADDR,
15 LASAT_NETMASK,
16 LASAT_BCAST,
17 LASAT_PASSWORD,
18 LASAT_SBOOT,
19 LASAT_RTC,
20 LASAT_NAMESTR,
21 LASAT_TYPESTR,
22};
23
24#endif /* _LASAT_SYSCTL_H */
diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile
new file mode 100644
index 000000000000..fb1b48c48cb3
--- /dev/null
+++ b/arch/mips/lemote/lm2e/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for Lemote Fulong mini-PC board.
3#
4
5obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o
6EXTRA_AFLAGS := $(CFLAGS)
7
diff --git a/arch/mips/lemote/lm2e/bonito-irq.c b/arch/mips/lemote/lm2e/bonito-irq.c
new file mode 100644
index 000000000000..8fc3bce7075b
--- /dev/null
+++ b/arch/mips/lemote/lm2e/bonito-irq.c
@@ -0,0 +1,74 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
5 *
6 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
7 * Author: Fuxin Zhang, zhangfx@lemote.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 */
30#include <linux/errno.h>
31#include <linux/init.h>
32#include <linux/io.h>
33#include <linux/types.h>
34#include <linux/interrupt.h>
35#include <linux/irq.h>
36
37#include <asm/mips-boards/bonito64.h>
38
39
40static inline void bonito_irq_enable(unsigned int irq)
41{
42 BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE));
43 mmiowb();
44}
45
46static inline void bonito_irq_disable(unsigned int irq)
47{
48 BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE));
49 mmiowb();
50}
51
52static struct irq_chip bonito_irq_type = {
53 .name = "bonito_irq",
54 .ack = bonito_irq_disable,
55 .mask = bonito_irq_disable,
56 .mask_ack = bonito_irq_disable,
57 .unmask = bonito_irq_enable,
58};
59
60static struct irqaction dma_timeout_irqaction = {
61 .handler = no_action,
62 .name = "dma_timeout",
63};
64
65void bonito_irq_init(void)
66{
67 u32 i;
68
69 for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) {
70 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
71 }
72
73 setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction);
74}
diff --git a/arch/mips/lemote/lm2e/dbg_io.c b/arch/mips/lemote/lm2e/dbg_io.c
new file mode 100644
index 000000000000..6c95da3ca76f
--- /dev/null
+++ b/arch/mips/lemote/lm2e/dbg_io.c
@@ -0,0 +1,146 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
5 *
6 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
7 * Author: Fuxin Zhang, zhangfx@lemote.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 */
30
31#include <linux/io.h>
32#include <linux/init.h>
33#include <linux/types.h>
34
35#include <asm/serial.h>
36
37#define UART16550_BAUD_2400 2400
38#define UART16550_BAUD_4800 4800
39#define UART16550_BAUD_9600 9600
40#define UART16550_BAUD_19200 19200
41#define UART16550_BAUD_38400 38400
42#define UART16550_BAUD_57600 57600
43#define UART16550_BAUD_115200 115200
44
45#define UART16550_PARITY_NONE 0
46#define UART16550_PARITY_ODD 0x08
47#define UART16550_PARITY_EVEN 0x18
48#define UART16550_PARITY_MARK 0x28
49#define UART16550_PARITY_SPACE 0x38
50
51#define UART16550_DATA_5BIT 0x0
52#define UART16550_DATA_6BIT 0x1
53#define UART16550_DATA_7BIT 0x2
54#define UART16550_DATA_8BIT 0x3
55
56#define UART16550_STOP_1BIT 0x0
57#define UART16550_STOP_2BIT 0x4
58
59/* ----------------------------------------------------- */
60
61/* === CONFIG === */
62#ifdef CONFIG_64BIT
63#define BASE (0xffffffffbfd003f8)
64#else
65#define BASE (0xbfd003f8)
66#endif
67
68#define MAX_BAUD BASE_BAUD
69/* === END OF CONFIG === */
70
71#define REG_OFFSET 1
72
73/* register offset */
74#define OFS_RCV_BUFFER 0
75#define OFS_TRANS_HOLD 0
76#define OFS_SEND_BUFFER 0
77#define OFS_INTR_ENABLE (1*REG_OFFSET)
78#define OFS_INTR_ID (2*REG_OFFSET)
79#define OFS_DATA_FORMAT (3*REG_OFFSET)
80#define OFS_LINE_CONTROL (3*REG_OFFSET)
81#define OFS_MODEM_CONTROL (4*REG_OFFSET)
82#define OFS_RS232_OUTPUT (4*REG_OFFSET)
83#define OFS_LINE_STATUS (5*REG_OFFSET)
84#define OFS_MODEM_STATUS (6*REG_OFFSET)
85#define OFS_RS232_INPUT (6*REG_OFFSET)
86#define OFS_SCRATCH_PAD (7*REG_OFFSET)
87
88#define OFS_DIVISOR_LSB (0*REG_OFFSET)
89#define OFS_DIVISOR_MSB (1*REG_OFFSET)
90
91/* memory-mapped read/write of the port */
92#define UART16550_READ(y) readb((char *)BASE + (y))
93#define UART16550_WRITE(y, z) writeb(z, (char *)BASE + (y))
94
95void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
96{
97 u32 divisor;
98
99 /* disable interrupts */
100 UART16550_WRITE(OFS_INTR_ENABLE, 0);
101
102 /* set up buad rate */
103 /* set DIAB bit */
104 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
105
106 /* set divisor */
107 divisor = MAX_BAUD / baud;
108 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
109 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
110
111 /* clear DIAB bit */
112 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
113
114 /* set data format */
115 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
116}
117
118static int remoteDebugInitialized;
119
120u8 getDebugChar(void)
121{
122 if (!remoteDebugInitialized) {
123 remoteDebugInitialized = 1;
124 debugInit(UART16550_BAUD_115200,
125 UART16550_DATA_8BIT,
126 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
127 }
128
129 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0) ;
130 return UART16550_READ(OFS_RCV_BUFFER);
131}
132
133int putDebugChar(u8 byte)
134{
135 if (!remoteDebugInitialized) {
136 remoteDebugInitialized = 1;
137 /*
138 debugInit(UART16550_BAUD_115200,
139 UART16550_DATA_8BIT,
140 UART16550_PARITY_NONE, UART16550_STOP_1BIT); */
141 }
142
143 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0) ;
144 UART16550_WRITE(OFS_SEND_BUFFER, byte);
145 return 1;
146}
diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c
new file mode 100644
index 000000000000..05693bceaeaf
--- /dev/null
+++ b/arch/mips/lemote/lm2e/irq.c
@@ -0,0 +1,145 @@
1/*
2 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 */
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/irq.h>
32
33#include <asm/irq_cpu.h>
34#include <asm/i8259.h>
35#include <asm/mipsregs.h>
36#include <asm/mips-boards/bonito64.h>
37
38
39/*
40 * the first level int-handler will jump here if it is a bonito irq
41 */
42static void bonito_irqdispatch(void)
43{
44 u32 int_status;
45 int i;
46
47 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
48 int_status = BONITO_INTISR;
49 if (int_status & (1 << 10)) {
50 while (int_status & (1 << 10)) {
51 udelay(1);
52 int_status = BONITO_INTISR;
53 }
54 }
55
56 /* Get pending sources, masked by current enables */
57 int_status = BONITO_INTISR & BONITO_INTEN;
58
59 if (int_status != 0) {
60 i = __ffs(int_status);
61 int_status &= ~(1 << i);
62 do_IRQ(BONITO_IRQ_BASE + i);
63 }
64}
65
66static void i8259_irqdispatch(void)
67{
68 int irq;
69
70 irq = i8259_irq();
71 if (irq >= 0) {
72 do_IRQ(irq);
73 } else {
74 spurious_interrupt();
75 }
76
77}
78
79asmlinkage void plat_irq_dispatch(void)
80{
81 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
82
83 if (pending & CAUSEF_IP7) {
84 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
85 } else if (pending & CAUSEF_IP5) {
86 i8259_irqdispatch();
87 } else if (pending & CAUSEF_IP2) {
88 bonito_irqdispatch();
89 } else {
90 spurious_interrupt();
91 }
92}
93
94static struct irqaction cascade_irqaction = {
95 .handler = no_action,
96 .mask = CPU_MASK_NONE,
97 .name = "cascade",
98};
99
100void __init arch_init_irq(void)
101{
102 extern void bonito_irq_init(void);
103
104 /*
105 * Clear all of the interrupts while we change the able around a bit.
106 * int-handler is not on bootstrap
107 */
108 clear_c0_status(ST0_IM | ST0_BEV);
109 local_irq_disable();
110
111 /* most bonito irq should be level triggered */
112 BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
113 BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
114 BONITO_INTSTEER = 0;
115
116 /*
117 * Mask out all interrupt by writing "1" to all bit position in
118 * the interrupt reset reg.
119 */
120 BONITO_INTENCLR = ~0;
121
122 /* init all controller
123 * 0-15 ------> i8259 interrupt
124 * 16-23 ------> mips cpu interrupt
125 * 32-63 ------> bonito irq
126 */
127
128 /* Sets the first-level interrupt dispatcher. */
129 mips_cpu_irq_init();
130 init_i8259_irqs();
131 bonito_irq_init();
132
133 /*
134 printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE);
135 printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n",
136 BONITO_INTEN, BONITO_INTENSET,
137 BONITO_INTENCLR, BONITO_INTISR);
138 */
139
140 /* bonito irq at IP2 */
141 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
142 /* 8259 irq at IP5 */
143 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
144
145}
diff --git a/arch/mips/lemote/lm2e/mem.c b/arch/mips/lemote/lm2e/mem.c
new file mode 100644
index 000000000000..16cd21587d34
--- /dev/null
+++ b/arch/mips/lemote/lm2e/mem.c
@@ -0,0 +1,23 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 */
7#include <linux/fs.h>
8#include <linux/fcntl.h>
9#include <linux/mm.h>
10
11/* override of arch/mips/mm/cache.c: __uncached_access */
12int __uncached_access(struct file *file, unsigned long addr)
13{
14 if (file->f_flags & O_SYNC)
15 return 1;
16
17 /*
18 * On the Lemote Loongson 2e system, the peripheral registers
19 * reside between 0x1000:0000 and 0x2000:0000.
20 */
21 return addr >= __pa(high_memory) ||
22 ((addr >= 0x10000000) && (addr < 0x20000000));
23}
diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c
new file mode 100644
index 000000000000..1ade1cef3899
--- /dev/null
+++ b/arch/mips/lemote/lm2e/pci.c
@@ -0,0 +1,93 @@
1/*
2 * pci.c
3 *
4 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
5 * Author: Fuxin Zhang, zhangfx@lemote.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 */
28#include <linux/types.h>
29#include <linux/pci.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <asm/mips-boards/bonito64.h>
33
34extern struct pci_ops bonito64_pci_ops;
35
36static struct resource loongson2e_pci_mem_resource = {
37 .name = "LOONGSON2E PCI MEM",
38 .start = 0x14000000UL,
39 .end = 0x1fffffffUL,
40 .flags = IORESOURCE_MEM,
41};
42
43static struct resource loongson2e_pci_io_resource = {
44 .name = "LOONGSON2E PCI IO MEM",
45 .start = 0x00004000UL,
46 .end = IO_SPACE_LIMIT,
47 .flags = IORESOURCE_IO,
48};
49
50static struct pci_controller loongson2e_pci_controller = {
51 .pci_ops = &bonito64_pci_ops,
52 .io_resource = &loongson2e_pci_io_resource,
53 .mem_resource = &loongson2e_pci_mem_resource,
54 .mem_offset = 0x00000000UL,
55 .io_offset = 0x00000000UL,
56};
57
58static void __init ict_pcimap(void)
59{
60 /*
61 * local to PCI mapping: [256M,512M] -> [256M,512M]; differ from PMON
62 *
63 * CPU address space [256M,448M] is window for accessing pci space
64 * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M]
65 * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0
66 */
67 /* 1,00 0110 ,0001 01,00 0000 */
68 BONITO_PCIMAP = 0x46140;
69
70 /* 1, 00 0010, 0000,01, 00 0000 */
71 /* BONITO_PCIMAP = 0x42040; */
72
73 /*
74 * PCI to local mapping: [2G,2G+256M] -> [0,256M]
75 */
76 BONITO_PCIBASE0 = 0x80000000;
77 BONITO_PCIBASE1 = 0x00800000;
78 BONITO_PCIBASE2 = 0x90000000;
79
80}
81
82static int __init pcibios_init(void)
83{
84 extern int pci_probe_only;
85 pci_probe_only = 0;
86
87 ict_pcimap();
88 register_pci_controller(&loongson2e_pci_controller);
89
90 return 0;
91}
92
93arch_initcall(pcibios_init);
diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c
new file mode 100644
index 000000000000..67312d7acf2a
--- /dev/null
+++ b/arch/mips/lemote/lm2e/prom.c
@@ -0,0 +1,104 @@
1/*
2 * Based on Ocelot Linux port, which is
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright 2003 ICT CAS
7 * Author: Michael Guo <guoyi@ict.ac.cn>
8 *
9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
10 * Author: Fuxin Zhang, zhangfx@lemote.com
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/init.h>
18#include <linux/mm.h>
19#include <linux/sched.h>
20#include <linux/bootmem.h>
21
22#include <asm/addrspace.h>
23#include <asm/bootinfo.h>
24
25extern unsigned long bus_clock;
26extern unsigned long cpu_clock;
27extern unsigned int memsize, highmemsize;
28extern int putDebugChar(unsigned char byte);
29
30static int argc;
31/* pmon passes arguments in 32bit pointers */
32static int *arg;
33static int *env;
34
35const char *get_system_type(void)
36{
37 return "lemote-fulong";
38}
39
40void __init prom_init_cmdline(void)
41{
42 int i;
43 long l;
44
45 /* arg[0] is "g", the rest is boot parameters */
46 arcs_cmdline[0] = '\0';
47 for (i = 1; i < argc; i++) {
48 l = (long)arg[i];
49 if (strlen(arcs_cmdline) + strlen(((char *)l) + 1)
50 >= sizeof(arcs_cmdline))
51 break;
52 strcat(arcs_cmdline, ((char *)l));
53 strcat(arcs_cmdline, " ");
54 }
55}
56
57void __init prom_init(void)
58{
59 long l;
60 argc = fw_arg0;
61 arg = (int *)fw_arg1;
62 env = (int *)fw_arg2;
63
64 mips_machgroup = MACH_GROUP_LEMOTE;
65 mips_machtype = MACH_LEMOTE_FULONG;
66
67 prom_init_cmdline();
68
69 if ((strstr(arcs_cmdline, "console=")) == NULL)
70 strcat(arcs_cmdline, " console=ttyS0,115200");
71 if ((strstr(arcs_cmdline, "root=")) == NULL)
72 strcat(arcs_cmdline, " root=/dev/hda1");
73
74#define parse_even_earlier(res, option, p) \
75do { \
76 if (strncmp(option, (char *)p, strlen(option)) == 0) \
77 res = simple_strtol((char *)p + strlen(option"="), \
78 NULL, 10); \
79} while (0)
80
81 l = (long)*env;
82 while (l != 0) {
83 parse_even_earlier(bus_clock, "busclock", l);
84 parse_even_earlier(cpu_clock, "cpuclock", l);
85 parse_even_earlier(memsize, "memsize", l);
86 parse_even_earlier(highmemsize, "highmemsize", l);
87 env++;
88 l = (long)*env;
89 }
90 if (memsize == 0)
91 memsize = 256;
92
93 pr_info("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n",
94 bus_clock, cpu_clock, memsize, highmemsize);
95}
96
97void __init prom_free_prom_memory(void)
98{
99}
100
101void prom_putchar(char c)
102{
103 putDebugChar(c);
104}
diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c
new file mode 100644
index 000000000000..099387a3827a
--- /dev/null
+++ b/arch/mips/lemote/lm2e/reset.c
@@ -0,0 +1,41 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
8 * Author: Fuxin Zhang, zhangfx@lemote.com
9 */
10#include <linux/pm.h>
11
12#include <asm/reboot.h>
13
14static void loongson2e_restart(char *command)
15{
16#ifdef CONFIG_32BIT
17 *(unsigned long *)0xbfe00104 &= ~(1 << 2);
18 *(unsigned long *)0xbfe00104 |= (1 << 2);
19#else
20 *(unsigned long *)0xffffffffbfe00104 &= ~(1 << 2);
21 *(unsigned long *)0xffffffffbfe00104 |= (1 << 2);
22#endif
23 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
24}
25
26static void loongson2e_halt(void)
27{
28 while (1) ;
29}
30
31static void loongson2e_power_off(void)
32{
33 loongson2e_halt();
34}
35
36void mips_reboot_setup(void)
37{
38 _machine_restart = loongson2e_restart;
39 _machine_halt = loongson2e_halt;
40 pm_power_off = loongson2e_power_off;
41}
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c
new file mode 100644
index 000000000000..0e4d1fa572b5
--- /dev/null
+++ b/arch/mips/lemote/lm2e/setup.c
@@ -0,0 +1,134 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * setup.c - board dependent boot routines
4 *
5 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
6 * Author: Fuxin Zhang, zhangfx@lemote.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 */
29#include <linux/bootmem.h>
30#include <linux/init.h>
31#include <linux/io.h>
32#include <linux/ioport.h>
33#include <linux/interrupt.h>
34#include <linux/irq.h>
35#include <linux/kernel.h>
36#include <linux/mc146818rtc.h>
37#include <linux/mm.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/tty.h>
41#include <linux/types.h>
42
43#include <asm/bootinfo.h>
44#include <asm/mc146818-time.h>
45#include <asm/time.h>
46#include <asm/wbflush.h>
47
48#ifdef CONFIG_VT
49#include <linux/console.h>
50#include <linux/screen_info.h>
51#endif
52
53extern void mips_reboot_setup(void);
54
55#ifdef CONFIG_64BIT
56#define PTR_PAD(p) ((0xffffffff00000000)|((unsigned long long)(p)))
57#else
58#define PTR_PAD(p) (p)
59#endif
60
61unsigned long cpu_clock;
62unsigned long bus_clock;
63unsigned int memsize;
64unsigned int highmemsize = 0;
65
66void __init plat_timer_setup(struct irqaction *irq)
67{
68 setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
69}
70
71static void __init loongson2e_time_init(void)
72{
73 /* setup mips r4k timer */
74 mips_hpt_frequency = cpu_clock / 2;
75}
76
77static unsigned long __init mips_rtc_get_time(void)
78{
79 return mc146818_get_cmos_time();
80}
81
82void (*__wbflush)(void);
83EXPORT_SYMBOL(__wbflush);
84
85static void wbflush_loongson2e(void)
86{
87 asm(".set\tpush\n\t"
88 ".set\tnoreorder\n\t"
89 ".set mips3\n\t"
90 "sync\n\t"
91 "nop\n\t"
92 ".set\tpop\n\t"
93 ".set mips0\n\t");
94}
95
96void __init plat_mem_setup(void)
97{
98 set_io_port_base(PTR_PAD(0xbfd00000));
99
100 mips_reboot_setup();
101
102 board_time_init = loongson2e_time_init;
103 rtc_mips_get_time = mips_rtc_get_time;
104
105 __wbflush = wbflush_loongson2e;
106
107 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
108#ifdef CONFIG_64BIT
109 if (highmemsize > 0) {
110 add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM);
111 }
112#endif
113
114#ifdef CONFIG_VT
115#if defined(CONFIG_VGA_CONSOLE)
116 conswitchp = &vga_con;
117
118 screen_info = (struct screen_info) {
119 0, 25, /* orig-x, orig-y */
120 0, /* unused */
121 0, /* orig-video-page */
122 0, /* orig-video-mode */
123 80, /* orig-video-cols */
124 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
125 25, /* orig-video-lines */
126 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
127 16 /* orig-video-points */
128 };
129#elif defined(CONFIG_DUMMY_CONSOLE)
130 conswitchp = &dummy_con;
131#endif
132#endif
133
134}
diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile
deleted file mode 100644
index 8b94d4cc5a30..000000000000
--- a/arch/mips/lib-32/Makefile
+++ /dev/null
@@ -1,23 +0,0 @@
1#
2# Makefile for MIPS-specific library files..
3#
4
5lib-y += watch.o
6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
9obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
10obj-$(CONFIG_CPU_R10000) += dump_tlb.o
11obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
12obj-$(CONFIG_CPU_R4300) += dump_tlb.o
13obj-$(CONFIG_CPU_R4X00) += dump_tlb.o
14obj-$(CONFIG_CPU_R5000) += dump_tlb.o
15obj-$(CONFIG_CPU_R5432) += dump_tlb.o
16obj-$(CONFIG_CPU_R6000) +=
17obj-$(CONFIG_CPU_R8000) +=
18obj-$(CONFIG_CPU_RM7000) += dump_tlb.o
19obj-$(CONFIG_CPU_RM9000) += dump_tlb.o
20obj-$(CONFIG_CPU_SB1) += dump_tlb.o
21obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
22obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
23obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
diff --git a/arch/mips/lib-32/dump_tlb.c b/arch/mips/lib-32/dump_tlb.c
deleted file mode 100644
index 6a68deb51aae..000000000000
--- a/arch/mips/lib-32/dump_tlb.c
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * Dump R4x00 TLB for debugging purposes.
3 *
4 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
5 * Copyright (C) 1999 by Silicon Graphics, Inc.
6 */
7#include <linux/kernel.h>
8#include <linux/mm.h>
9#include <linux/sched.h>
10#include <linux/string.h>
11
12#include <asm/bootinfo.h>
13#include <asm/cachectl.h>
14#include <asm/cpu.h>
15#include <asm/mipsregs.h>
16#include <asm/page.h>
17#include <asm/pgtable.h>
18
19static inline const char *msk2str(unsigned int mask)
20{
21 switch (mask) {
22 case PM_4K:
23 return "4kb";
24 case PM_16K:
25 return "16kb";
26 case PM_64K:
27 return "64kb";
28 case PM_256K:
29 return "256kb";
30#ifndef CONFIG_CPU_VR41XX
31 case PM_1M:
32 return "1Mb";
33 case PM_4M:
34 return "4Mb";
35 case PM_16M:
36 return "16Mb";
37 case PM_64M:
38 return "64Mb";
39 case PM_256M:
40 return "256Mb";
41#endif
42 }
43
44 return "unknown";
45}
46
47#define BARRIER() \
48 __asm__ __volatile__( \
49 ".set\tnoreorder\n\t" \
50 "nop;nop;nop;nop;nop;nop;nop\n\t" \
51 ".set\treorder");
52
53void dump_tlb(int first, int last)
54{
55 unsigned int pagemask, c0, c1, asid;
56 unsigned long long entrylo0, entrylo1;
57 unsigned long entryhi;
58 int i;
59
60 asid = read_c0_entryhi() & 0xff;
61
62 printk("\n");
63 for (i = first; i <= last; i++) {
64 write_c0_index(i);
65 BARRIER();
66 tlb_read();
67 BARRIER();
68 pagemask = read_c0_pagemask();
69 entryhi = read_c0_entryhi();
70 entrylo0 = read_c0_entrylo0();
71 entrylo1 = read_c0_entrylo1();
72
73 /* Unused entries have a virtual address in KSEG0. */
74 if ((entryhi & 0xf0000000) != 0x80000000
75 && (entryhi & 0xff) == asid) {
76 /*
77 * Only print entries in use
78 */
79 printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
80
81 c0 = (entrylo0 >> 3) & 7;
82 c1 = (entrylo1 >> 3) & 7;
83
84 printk("va=%08lx asid=%02lx\n",
85 (entryhi & 0xffffe000), (entryhi & 0xff));
86 printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n",
87 (entrylo0 << 6) & PAGE_MASK, c0,
88 (entrylo0 & 4) ? 1 : 0,
89 (entrylo0 & 2) ? 1 : 0, (entrylo0 & 1));
90 printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n",
91 (entrylo1 << 6) & PAGE_MASK, c1,
92 (entrylo1 & 4) ? 1 : 0,
93 (entrylo1 & 2) ? 1 : 0, (entrylo1 & 1));
94 printk("\n");
95 }
96 }
97
98 write_c0_entryhi(asid);
99}
100
101void dump_tlb_all(void)
102{
103 dump_tlb(0, current_cpu_data.tlbsize - 1);
104}
105
106void dump_tlb_wired(void)
107{
108 int wired;
109
110 wired = read_c0_wired();
111 printk("Wired: %d", wired);
112 dump_tlb(0, read_c0_wired());
113}
114
115void dump_tlb_addr(unsigned long addr)
116{
117 unsigned int flags, oldpid;
118 int index;
119
120 local_irq_save(flags);
121 oldpid = read_c0_entryhi() & 0xff;
122 BARRIER();
123 write_c0_entryhi((addr & PAGE_MASK) | oldpid);
124 BARRIER();
125 tlb_probe();
126 BARRIER();
127 index = read_c0_index();
128 write_c0_entryhi(oldpid);
129 local_irq_restore(flags);
130
131 if (index < 0) {
132 printk("No entry for address 0x%08lx in TLB\n", addr);
133 return;
134 }
135
136 printk("Entry %d maps address 0x%08lx\n", index, addr);
137 dump_tlb(index, index);
138}
139
140void dump_tlb_nonwired(void)
141{
142 dump_tlb(read_c0_wired(), current_cpu_data.tlbsize - 1);
143}
144
145void dump_list_process(struct task_struct *t, void *address)
146{
147 pgd_t *page_dir, *pgd;
148 pud_t *pud;
149 pmd_t *pmd;
150 pte_t *pte, page;
151 unsigned long addr, val;
152
153 addr = (unsigned long) address;
154
155 printk("Addr == %08lx\n", addr);
156 printk("task == %8p\n", t);
157 printk("task->mm == %8p\n", t->mm);
158 //printk("tasks->mm.pgd == %08x\n", (unsigned int) t->mm->pgd);
159
160 if (addr > KSEG0) {
161 page_dir = pgd_offset_k(0);
162 pgd = pgd_offset_k(addr);
163 } else if (t->mm) {
164 page_dir = pgd_offset(t->mm, 0);
165 pgd = pgd_offset(t->mm, addr);
166 } else {
167 printk("Current thread has no mm\n");
168 return;
169 }
170 printk("page_dir == %08x\n", (unsigned int) page_dir);
171 printk("pgd == %08x, ", (unsigned int) pgd);
172 pud = pud_offset(pgd, addr);
173 printk("pud == %08x, ", (unsigned int) pud);
174
175 pmd = pmd_offset(pud, addr);
176 printk("pmd == %08x, ", (unsigned int) pmd);
177
178 pte = pte_offset(pmd, addr);
179 printk("pte == %08x, ", (unsigned int) pte);
180
181 page = *pte;
182#ifdef CONFIG_64BIT_PHYS_ADDR
183 printk("page == %08Lx\n", pte_val(page));
184#else
185 printk("page == %08lx\n", pte_val(page));
186#endif
187
188 val = pte_val(page);
189 if (val & _PAGE_PRESENT)
190 printk("present ");
191 if (val & _PAGE_READ)
192 printk("read ");
193 if (val & _PAGE_WRITE)
194 printk("write ");
195 if (val & _PAGE_ACCESSED)
196 printk("accessed ");
197 if (val & _PAGE_MODIFIED)
198 printk("modified ");
199 if (val & _PAGE_R4KBUG)
200 printk("r4kbug ");
201 if (val & _PAGE_GLOBAL)
202 printk("global ");
203 if (val & _PAGE_VALID)
204 printk("valid ");
205 printk("\n");
206}
207
208void dump_list_current(void *address)
209{
210 dump_list_process(current, address);
211}
212
213unsigned int vtop(void *address)
214{
215 pgd_t *pgd;
216 pud_t *pud;
217 pmd_t *pmd;
218 pte_t *pte;
219 unsigned int addr, paddr;
220
221 addr = (unsigned long) address;
222 pgd = pgd_offset(current->mm, addr);
223 pud = pud_offset(pgd, addr);
224 pmd = pmd_offset(pud, addr);
225 pte = pte_offset(pmd, addr);
226 paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
227 paddr |= (addr & ~PAGE_MASK);
228
229 return paddr;
230}
231
232void dump16(unsigned long *p)
233{
234 int i;
235
236 for (i = 0; i < 8; i++) {
237 printk("*%08lx == %08lx, ", (unsigned long) p, *p);
238 p++;
239 printk("*%08lx == %08lx\n", (unsigned long) p, *p);
240 p++;
241 }
242}
diff --git a/arch/mips/lib-32/r3k_dump_tlb.c b/arch/mips/lib-32/r3k_dump_tlb.c
deleted file mode 100644
index 4f2cb74f0766..000000000000
--- a/arch/mips/lib-32/r3k_dump_tlb.c
+++ /dev/null
@@ -1,182 +0,0 @@
1/*
2 * Dump R3000 TLB for debugging purposes.
3 *
4 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
5 * Copyright (C) 1999 by Silicon Graphics, Inc.
6 * Copyright (C) 1999 by Harald Koerfgen
7 */
8#include <linux/kernel.h>
9#include <linux/mm.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12
13#include <asm/bootinfo.h>
14#include <asm/cachectl.h>
15#include <asm/cpu.h>
16#include <asm/mipsregs.h>
17#include <asm/page.h>
18#include <asm/pgtable.h>
19
20extern int r3k_have_wired_reg; /* defined in tlb-r3k.c */
21
22void dump_tlb(int first, int last)
23{
24 int i;
25 unsigned int asid;
26 unsigned long entryhi, entrylo0;
27
28 asid = read_c0_entryhi() & 0xfc0;
29
30 for (i = first; i <= last; i++) {
31 write_c0_index(i<<8);
32 __asm__ __volatile__(
33 ".set\tnoreorder\n\t"
34 "tlbr\n\t"
35 "nop\n\t"
36 ".set\treorder");
37 entryhi = read_c0_entryhi();
38 entrylo0 = read_c0_entrylo0();
39
40 /* Unused entries have a virtual address of KSEG0. */
41 if ((entryhi & 0xffffe000) != 0x80000000
42 && (entryhi & 0xfc0) == asid) {
43 /*
44 * Only print entries in use
45 */
46 printk("Index: %2d ", i);
47
48 printk("va=%08lx asid=%08lx"
49 " [pa=%06lx n=%d d=%d v=%d g=%d]",
50 (entryhi & 0xffffe000),
51 entryhi & 0xfc0,
52 entrylo0 & PAGE_MASK,
53 (entrylo0 & (1 << 11)) ? 1 : 0,
54 (entrylo0 & (1 << 10)) ? 1 : 0,
55 (entrylo0 & (1 << 9)) ? 1 : 0,
56 (entrylo0 & (1 << 8)) ? 1 : 0);
57 }
58 }
59 printk("\n");
60
61 write_c0_entryhi(asid);
62}
63
64void dump_tlb_all(void)
65{
66 dump_tlb(0, current_cpu_data.tlbsize - 1);
67}
68
69void dump_tlb_wired(void)
70{
71 int wired = r3k_have_wired_reg ? read_c0_wired() : 8;
72
73 printk("Wired: %d", wired);
74 dump_tlb(0, wired - 1);
75}
76
77void dump_tlb_addr(unsigned long addr)
78{
79 unsigned long flags, oldpid;
80 int index;
81
82 local_irq_save(flags);
83 oldpid = read_c0_entryhi() & 0xff;
84 write_c0_entryhi((addr & PAGE_MASK) | oldpid);
85 tlb_probe();
86 index = read_c0_index();
87 write_c0_entryhi(oldpid);
88 local_irq_restore(flags);
89
90 if (index < 0) {
91 printk("No entry for address 0x%08lx in TLB\n", addr);
92 return;
93 }
94
95 printk("Entry %d maps address 0x%08lx\n", index, addr);
96 dump_tlb(index, index);
97}
98
99void dump_tlb_nonwired(void)
100{
101 int wired = r3k_have_wired_reg ? read_c0_wired() : 8;
102 dump_tlb(wired, current_cpu_data.tlbsize - 1);
103}
104
105void dump_list_process(struct task_struct *t, void *address)
106{
107 pgd_t *page_dir, *pgd;
108 pud_t *pud;
109 pmd_t *pmd;
110 pte_t *pte, page;
111 unsigned int addr;
112 unsigned long val;
113
114 addr = (unsigned int) address;
115
116 printk("Addr == %08x\n", addr);
117 printk("tasks->mm.pgd == %08x\n", (unsigned int) t->mm->pgd);
118
119 page_dir = pgd_offset(t->mm, 0);
120 printk("page_dir == %08x\n", (unsigned int) page_dir);
121
122 pgd = pgd_offset(t->mm, addr);
123 printk("pgd == %08x, ", (unsigned int) pgd);
124
125 pud = pud_offset(pgd, addr);
126 printk("pud == %08x, ", (unsigned int) pud);
127
128 pmd = pmd_offset(pud, addr);
129 printk("pmd == %08x, ", (unsigned int) pmd);
130
131 pte = pte_offset(pmd, addr);
132 printk("pte == %08x, ", (unsigned int) pte);
133
134 page = *pte;
135 printk("page == %08x\n", (unsigned int) pte_val(page));
136
137 val = pte_val(page);
138 if (val & _PAGE_PRESENT) printk("present ");
139 if (val & _PAGE_READ) printk("read ");
140 if (val & _PAGE_WRITE) printk("write ");
141 if (val & _PAGE_ACCESSED) printk("accessed ");
142 if (val & _PAGE_MODIFIED) printk("modified ");
143 if (val & _PAGE_GLOBAL) printk("global ");
144 if (val & _PAGE_VALID) printk("valid ");
145 printk("\n");
146}
147
148void dump_list_current(void *address)
149{
150 dump_list_process(current, address);
151}
152
153unsigned int vtop(void *address)
154{
155 pgd_t *pgd;
156 pud_t *pud;
157 pmd_t *pmd;
158 pte_t *pte;
159 unsigned int addr, paddr;
160
161 addr = (unsigned long) address;
162 pgd = pgd_offset(current->mm, addr);
163 pud = pud_offset(pgd, addr);
164 pmd = pmd_offset(pud, addr);
165 pte = pte_offset(pmd, addr);
166 paddr = (KSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
167 paddr |= (addr & ~PAGE_MASK);
168
169 return paddr;
170}
171
172void dump16(unsigned long *p)
173{
174 int i;
175
176 for (i = 0; i < 8; i++) {
177 printk("*%08lx == %08lx, ", (unsigned long)p, *p);
178 p++;
179 printk("*%08lx == %08lx\n", (unsigned long)p, *p);
180 p++;
181 }
182}
diff --git a/arch/mips/lib-32/watch.S b/arch/mips/lib-32/watch.S
deleted file mode 100644
index 808b3af1a605..000000000000
--- a/arch/mips/lib-32/watch.S
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Kernel debug stuff to use the Watch registers.
7 * Useful to find stack overflows, dangling pointers etc.
8 *
9 * Copyright (C) 1995, 1996, 1999 by Ralf Baechle
10 */
11#include <asm/asm.h>
12#include <asm/mipsregs.h>
13#include <asm/regdef.h>
14
15 .set noreorder
16/*
17 * Parameter: a0 - logic address to watch
18 * Currently only KSEG0 addresses are allowed!
19 * a1 - set bit #1 to trap on load references
20 * bit #0 to trap on store references
21 * Results : none
22 */
23 LEAF(__watch_set)
24 li t0, 0x80000000
25 subu a0, t0
26 ori a0, 7
27 xori a0, 7
28 or a0, a1
29 mtc0 a0, CP0_WATCHLO
30 sw a0, watch_savelo
31
32 jr ra
33 mtc0 zero, CP0_WATCHHI
34 END(__watch_set)
35
36/*
37 * Parameter: none
38 * Results : none
39 */
40 LEAF(__watch_clear)
41 jr ra
42 mtc0 zero, CP0_WATCHLO
43 END(__watch_clear)
44
45/*
46 * Parameter: none
47 * Results : none
48 */
49 LEAF(__watch_reenable)
50 lw t0, watch_savelo
51 jr ra
52 mtc0 t0, CP0_WATCHLO
53 END(__watch_reenable)
54
55/*
56 * Saved value of the c0_watchlo register for watch_reenable()
57 */
58 .data
59watch_savelo: .word 0
60 .text
diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile
deleted file mode 100644
index 8b94d4cc5a30..000000000000
--- a/arch/mips/lib-64/Makefile
+++ /dev/null
@@ -1,23 +0,0 @@
1#
2# Makefile for MIPS-specific library files..
3#
4
5lib-y += watch.o
6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
9obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
10obj-$(CONFIG_CPU_R10000) += dump_tlb.o
11obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
12obj-$(CONFIG_CPU_R4300) += dump_tlb.o
13obj-$(CONFIG_CPU_R4X00) += dump_tlb.o
14obj-$(CONFIG_CPU_R5000) += dump_tlb.o
15obj-$(CONFIG_CPU_R5432) += dump_tlb.o
16obj-$(CONFIG_CPU_R6000) +=
17obj-$(CONFIG_CPU_R8000) +=
18obj-$(CONFIG_CPU_RM7000) += dump_tlb.o
19obj-$(CONFIG_CPU_RM9000) += dump_tlb.o
20obj-$(CONFIG_CPU_SB1) += dump_tlb.o
21obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
22obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
23obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
diff --git a/arch/mips/lib-64/dump_tlb.c b/arch/mips/lib-64/dump_tlb.c
deleted file mode 100644
index 594df1a05ecc..000000000000
--- a/arch/mips/lib-64/dump_tlb.c
+++ /dev/null
@@ -1,216 +0,0 @@
1/*
2 * Dump R4x00 TLB for debugging purposes.
3 *
4 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
5 * Copyright (C) 1999 by Silicon Graphics, Inc.
6 */
7#include <linux/kernel.h>
8#include <linux/mm.h>
9#include <linux/sched.h>
10#include <linux/string.h>
11
12#include <asm/bootinfo.h>
13#include <asm/cachectl.h>
14#include <asm/cpu.h>
15#include <asm/mipsregs.h>
16#include <asm/page.h>
17#include <asm/pgtable.h>
18
19static inline const char *msk2str(unsigned int mask)
20{
21 switch (mask) {
22 case PM_4K: return "4kb";
23 case PM_16K: return "16kb";
24 case PM_64K: return "64kb";
25 case PM_256K: return "256kb";
26#ifndef CONFIG_CPU_VR41XX
27 case PM_1M: return "1Mb";
28 case PM_4M: return "4Mb";
29 case PM_16M: return "16Mb";
30 case PM_64M: return "64Mb";
31 case PM_256M: return "256Mb";
32#endif
33 }
34
35 return "unknown";
36}
37
38#define BARRIER() \
39 __asm__ __volatile__( \
40 ".set\tnoreorder\n\t" \
41 "nop;nop;nop;nop;nop;nop;nop\n\t" \
42 ".set\treorder");
43
44void dump_tlb(int first, int last)
45{
46 unsigned long s_entryhi, entryhi, entrylo0, entrylo1, asid;
47 unsigned int s_index, pagemask, c0, c1, i;
48
49 s_entryhi = read_c0_entryhi();
50 s_index = read_c0_index();
51 asid = s_entryhi & 0xff;
52
53 for (i = first; i <= last; i++) {
54 write_c0_index(i);
55 BARRIER();
56 tlb_read();
57 BARRIER();
58 pagemask = read_c0_pagemask();
59 entryhi = read_c0_entryhi();
60 entrylo0 = read_c0_entrylo0();
61 entrylo1 = read_c0_entrylo1();
62
63 /* Unused entries have a virtual address of CKSEG0. */
64 if ((entryhi & ~0x1ffffUL) != CKSEG0
65 && (entryhi & 0xff) == asid) {
66 /*
67 * Only print entries in use
68 */
69 printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
70
71 c0 = (entrylo0 >> 3) & 7;
72 c1 = (entrylo1 >> 3) & 7;
73
74 printk("va=%011lx asid=%02lx\n",
75 (entryhi & ~0x1fffUL),
76 entryhi & 0xff);
77 printk("\t[pa=%011lx c=%d d=%d v=%d g=%ld] ",
78 (entrylo0 << 6) & PAGE_MASK, c0,
79 (entrylo0 & 4) ? 1 : 0,
80 (entrylo0 & 2) ? 1 : 0,
81 (entrylo0 & 1));
82 printk("[pa=%011lx c=%d d=%d v=%d g=%ld]\n",
83 (entrylo1 << 6) & PAGE_MASK, c1,
84 (entrylo1 & 4) ? 1 : 0,
85 (entrylo1 & 2) ? 1 : 0,
86 (entrylo1 & 1));
87 }
88 }
89 printk("\n");
90
91 write_c0_entryhi(s_entryhi);
92 write_c0_index(s_index);
93}
94
95void dump_tlb_all(void)
96{
97 dump_tlb(0, current_cpu_data.tlbsize - 1);
98}
99
100void dump_tlb_wired(void)
101{
102 int wired;
103
104 wired = read_c0_wired();
105 printk("Wired: %d", wired);
106 dump_tlb(0, read_c0_wired());
107}
108
109void dump_tlb_addr(unsigned long addr)
110{
111 unsigned int flags, oldpid;
112 int index;
113
114 local_irq_save(flags);
115 oldpid = read_c0_entryhi() & 0xff;
116 BARRIER();
117 write_c0_entryhi((addr & PAGE_MASK) | oldpid);
118 BARRIER();
119 tlb_probe();
120 BARRIER();
121 index = read_c0_index();
122 write_c0_entryhi(oldpid);
123 local_irq_restore(flags);
124
125 if (index < 0) {
126 printk("No entry for address 0x%08lx in TLB\n", addr);
127 return;
128 }
129
130 printk("Entry %d maps address 0x%08lx\n", index, addr);
131 dump_tlb(index, index);
132}
133
134void dump_tlb_nonwired(void)
135{
136 dump_tlb(read_c0_wired(), current_cpu_data.tlbsize - 1);
137}
138
139void dump_list_process(struct task_struct *t, void *address)
140{
141 pgd_t *page_dir, *pgd;
142 pud_t *pud;
143 pmd_t *pmd;
144 pte_t *pte, page;
145 unsigned long addr, val;
146
147 addr = (unsigned long) address;
148
149 printk("Addr == %08lx\n", addr);
150 printk("tasks->mm.pgd == %08lx\n", (unsigned long) t->mm->pgd);
151
152 page_dir = pgd_offset(t->mm, 0UL);
153 printk("page_dir == %016lx\n", (unsigned long) page_dir);
154
155 pgd = pgd_offset(t->mm, addr);
156 printk("pgd == %016lx\n", (unsigned long) pgd);
157
158 pud = pud_offset(pgd, addr);
159 printk("pud == %016lx\n", (unsigned long) pud);
160
161 pmd = pmd_offset(pud, addr);
162 printk("pmd == %016lx\n", (unsigned long) pmd);
163
164 pte = pte_offset(pmd, addr);
165 printk("pte == %016lx\n", (unsigned long) pte);
166
167 page = *pte;
168 printk("page == %08lx\n", pte_val(page));
169
170 val = pte_val(page);
171 if (val & _PAGE_PRESENT) printk("present ");
172 if (val & _PAGE_READ) printk("read ");
173 if (val & _PAGE_WRITE) printk("write ");
174 if (val & _PAGE_ACCESSED) printk("accessed ");
175 if (val & _PAGE_MODIFIED) printk("modified ");
176 if (val & _PAGE_R4KBUG) printk("r4kbug ");
177 if (val & _PAGE_GLOBAL) printk("global ");
178 if (val & _PAGE_VALID) printk("valid ");
179 printk("\n");
180}
181
182void dump_list_current(void *address)
183{
184 dump_list_process(current, address);
185}
186
187unsigned long vtop(void *address)
188{
189 pgd_t *pgd;
190 pud_t *pud;
191 pmd_t *pmd;
192 pte_t *pte;
193 unsigned long addr, paddr;
194
195 addr = (unsigned long) address;
196 pgd = pgd_offset(current->mm, addr);
197 pud = pud_offset(pgd, addr);
198 pmd = pmd_offset(pud, addr);
199 pte = pte_offset(pmd, addr);
200 paddr = (CKSEG1 | (unsigned int) pte_val(*pte)) & PAGE_MASK;
201 paddr |= (addr & ~PAGE_MASK);
202
203 return paddr;
204}
205
206void dump16(unsigned long *p)
207{
208 int i;
209
210 for (i = 0; i < 8; i++) {
211 printk("*%08lx == %08lx, ", (unsigned long)p, *p);
212 p++;
213 printk("*%08lx == %08lx\n", (unsigned long)p, *p);
214 p++;
215 }
216}
diff --git a/arch/mips/lib-64/watch.S b/arch/mips/lib-64/watch.S
deleted file mode 100644
index f91434013695..000000000000
--- a/arch/mips/lib-64/watch.S
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Kernel debug stuff to use the Watch registers.
7 * Useful to find stack overflows, dangling pointers etc.
8 *
9 * Copyright (C) 1995, 1996, 1999, 2001 by Ralf Baechle
10 */
11#include <asm/asm.h>
12#include <asm/mipsregs.h>
13#include <asm/regdef.h>
14
15 .set noreorder
16/*
17 * Parameter: a0 - physical address to watch
18 * a1 - set bit #1 to trap on load references
19 * bit #0 to trap on store references
20 * Results : none
21 */
22 LEAF(__watch_set)
23 ori a0, 7
24 xori a0, 7
25 or a0, a1
26 mtc0 a0, CP0_WATCHLO
27 sd a0, watch_savelo
28 dsrl32 a0, a0, 0
29
30 jr ra
31 mtc0 zero, CP0_WATCHHI
32 END(__watch_set)
33
34/*
35 * Parameter: none
36 * Results : none
37 */
38 LEAF(__watch_clear)
39 jr ra
40 mtc0 zero, CP0_WATCHLO
41 END(__watch_clear)
42
43/*
44 * Parameter: none
45 * Results : none
46 */
47 LEAF(__watch_reenable)
48 ld t0, watch_savelo
49 jr ra
50 mtc0 t0, CP0_WATCHLO
51 END(__watch_reenable)
52
53/*
54 * Saved value of the c0_watchlo register for watch_reenable()
55 */
56 .local watch_savelo
57 .comm watch_savelo, 8, 8
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 1c1aa9f92f6c..91ed1eb33102 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -8,5 +8,24 @@ lib-y += csum_partial.o memcpy.o memcpy-inatomic.o memset.o strlen_user.o \
8obj-y += iomap.o 8obj-y += iomap.o
9obj-$(CONFIG_PCI) += iomap-pci.o 9obj-$(CONFIG_PCI) += iomap-pci.o
10 10
11obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o
12obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
13obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
14obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
15obj-$(CONFIG_CPU_R10000) += dump_tlb.o
16obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
17obj-$(CONFIG_CPU_R4300) += dump_tlb.o
18obj-$(CONFIG_CPU_R4X00) += dump_tlb.o
19obj-$(CONFIG_CPU_R5000) += dump_tlb.o
20obj-$(CONFIG_CPU_R5432) += dump_tlb.o
21obj-$(CONFIG_CPU_R6000) +=
22obj-$(CONFIG_CPU_R8000) +=
23obj-$(CONFIG_CPU_RM7000) += dump_tlb.o
24obj-$(CONFIG_CPU_RM9000) += dump_tlb.o
25obj-$(CONFIG_CPU_SB1) += dump_tlb.o
26obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
27obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
28obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
29
11# libgcc-style stuff needed in the kernel 30# libgcc-style stuff needed in the kernel
12obj-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o 31obj-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
new file mode 100644
index 000000000000..1a4db7dc77cb
--- /dev/null
+++ b/arch/mips/lib/dump_tlb.c
@@ -0,0 +1,100 @@
1/*
2 * Dump R4x00 TLB for debugging purposes.
3 *
4 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
5 * Copyright (C) 1999 by Silicon Graphics, Inc.
6 */
7#include <linux/kernel.h>
8#include <linux/mm.h>
9
10#include <asm/mipsregs.h>
11#include <asm/page.h>
12#include <asm/pgtable.h>
13
14static inline const char *msk2str(unsigned int mask)
15{
16 switch (mask) {
17 case PM_4K: return "4kb";
18 case PM_16K: return "16kb";
19 case PM_64K: return "64kb";
20 case PM_256K: return "256kb";
21#ifndef CONFIG_CPU_VR41XX
22 case PM_1M: return "1Mb";
23 case PM_4M: return "4Mb";
24 case PM_16M: return "16Mb";
25 case PM_64M: return "64Mb";
26 case PM_256M: return "256Mb";
27#endif
28 }
29 return "";
30}
31
32#define BARRIER() \
33 __asm__ __volatile__( \
34 ".set\tnoreorder\n\t" \
35 "nop;nop;nop;nop;nop;nop;nop\n\t" \
36 ".set\treorder");
37
38static void dump_tlb(int first, int last)
39{
40 unsigned long s_entryhi, entryhi, asid;
41 unsigned long long entrylo0, entrylo1;
42 unsigned int s_index, pagemask, c0, c1, i;
43
44 s_entryhi = read_c0_entryhi();
45 s_index = read_c0_index();
46 asid = s_entryhi & 0xff;
47
48 for (i = first; i <= last; i++) {
49 write_c0_index(i);
50 BARRIER();
51 tlb_read();
52 BARRIER();
53 pagemask = read_c0_pagemask();
54 entryhi = read_c0_entryhi();
55 entrylo0 = read_c0_entrylo0();
56 entrylo1 = read_c0_entrylo1();
57
58 /* Unused entries have a virtual address of CKSEG0. */
59 if ((entryhi & ~0x1ffffUL) != CKSEG0
60 && (entryhi & 0xff) == asid) {
61#ifdef CONFIG_32BIT
62 int width = 8;
63#else
64 int width = 11;
65#endif
66 /*
67 * Only print entries in use
68 */
69 printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
70
71 c0 = (entrylo0 >> 3) & 7;
72 c1 = (entrylo1 >> 3) & 7;
73
74 printk("va=%0*lx asid=%02lx\n",
75 width, (entryhi & ~0x1fffUL),
76 entryhi & 0xff);
77 printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
78 width,
79 (entrylo0 << 6) & PAGE_MASK, c0,
80 (entrylo0 & 4) ? 1 : 0,
81 (entrylo0 & 2) ? 1 : 0,
82 (entrylo0 & 1) ? 1 : 0);
83 printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
84 width,
85 (entrylo1 << 6) & PAGE_MASK, c1,
86 (entrylo1 & 4) ? 1 : 0,
87 (entrylo1 & 2) ? 1 : 0,
88 (entrylo1 & 1) ? 1 : 0);
89 }
90 }
91 printk("\n");
92
93 write_c0_entryhi(s_entryhi);
94 write_c0_index(s_index);
95}
96
97void dump_tlb_all(void)
98{
99 dump_tlb(0, current_cpu_data.tlbsize - 1);
100}
diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c
new file mode 100644
index 000000000000..52f87795ecc3
--- /dev/null
+++ b/arch/mips/lib/r3k_dump_tlb.c
@@ -0,0 +1,62 @@
1/*
2 * Dump R3000 TLB for debugging purposes.
3 *
4 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
5 * Copyright (C) 1999 by Silicon Graphics, Inc.
6 * Copyright (C) 1999 by Harald Koerfgen
7 */
8#include <linux/kernel.h>
9#include <linux/mm.h>
10
11#include <asm/mipsregs.h>
12#include <asm/page.h>
13#include <asm/pgtable.h>
14
15extern int r3k_have_wired_reg; /* defined in tlb-r3k.c */
16
17static void dump_tlb(int first, int last)
18{
19 int i;
20 unsigned int asid;
21 unsigned long entryhi, entrylo0;
22
23 asid = read_c0_entryhi() & 0xfc0;
24
25 for (i = first; i <= last; i++) {
26 write_c0_index(i<<8);
27 __asm__ __volatile__(
28 ".set\tnoreorder\n\t"
29 "tlbr\n\t"
30 "nop\n\t"
31 ".set\treorder");
32 entryhi = read_c0_entryhi();
33 entrylo0 = read_c0_entrylo0();
34
35 /* Unused entries have a virtual address of KSEG0. */
36 if ((entryhi & 0xffffe000) != 0x80000000
37 && (entryhi & 0xfc0) == asid) {
38 /*
39 * Only print entries in use
40 */
41 printk("Index: %2d ", i);
42
43 printk("va=%08lx asid=%08lx"
44 " [pa=%06lx n=%d d=%d v=%d g=%d]",
45 (entryhi & 0xffffe000),
46 entryhi & 0xfc0,
47 entrylo0 & PAGE_MASK,
48 (entrylo0 & (1 << 11)) ? 1 : 0,
49 (entrylo0 & (1 << 10)) ? 1 : 0,
50 (entrylo0 & (1 << 9)) ? 1 : 0,
51 (entrylo0 & (1 << 8)) ? 1 : 0);
52 }
53 }
54 printk("\n");
55
56 write_c0_entryhi(asid);
57}
58
59void dump_tlb_all(void)
60{
61 dump_tlb(0, current_cpu_data.tlbsize - 1);
62}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 80531b35cd61..d7f05b0abe17 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -35,6 +35,7 @@
35 * better performance by compiling with -msoft-float! 35 * better performance by compiling with -msoft-float!
36 */ 36 */
37#include <linux/sched.h> 37#include <linux/sched.h>
38#include <linux/debugfs.h>
38 39
39#include <asm/inst.h> 40#include <asm/inst.h>
40#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
@@ -1277,3 +1278,36 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1277 1278
1278 return sig; 1279 return sig;
1279} 1280}
1281
1282#ifdef CONFIG_DEBUG_FS
1283extern struct dentry *mips_debugfs_dir;
1284static int __init debugfs_fpuemu(void)
1285{
1286 struct dentry *d, *dir;
1287 int i;
1288 static struct {
1289 const char *name;
1290 unsigned int *v;
1291 } vars[] __initdata = {
1292 { "emulated", &fpuemustats.emulated },
1293 { "loads", &fpuemustats.loads },
1294 { "stores", &fpuemustats.stores },
1295 { "cp1ops", &fpuemustats.cp1ops },
1296 { "cp1xops", &fpuemustats.cp1xops },
1297 { "errors", &fpuemustats.errors },
1298 };
1299
1300 if (!mips_debugfs_dir)
1301 return -ENODEV;
1302 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1303 if (IS_ERR(dir))
1304 return PTR_ERR(dir);
1305 for (i = 0; i < ARRAY_SIZE(vars); i++) {
1306 d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
1307 if (IS_ERR(d))
1308 return PTR_ERR(d);
1309 }
1310 return 0;
1311}
1312__initcall(debugfs_fpuemu);
1313#endif
diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile
index 377d9e8f250a..a242b0fc377d 100644
--- a/arch/mips/mips-boards/malta/Makefile
+++ b/arch/mips/mips-boards/malta/Makefile
@@ -19,6 +19,7 @@
19# under Linux. 19# under Linux.
20# 20#
21 21
22obj-y := malta_int.o malta_setup.o 22obj-y := malta_int.o malta_platform.o malta_setup.o
23
23obj-$(CONFIG_MTD) += malta_mtd.o 24obj-$(CONFIG_MTD) += malta_mtd.o
24obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o 25obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o
diff --git a/arch/mips/mips-boards/malta/malta_platform.c b/arch/mips/mips-boards/malta/malta_platform.c
new file mode 100644
index 000000000000..83b9bab3cd3f
--- /dev/null
+++ b/arch/mips/mips-boards/malta/malta_platform.c
@@ -0,0 +1,65 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 MIPS Technologies, Inc.
7 * written by Ralf Baechle (ralf@linux-mips.org)
8 *
9 * Probe driver for the Malta's UART ports:
10 *
11 * o 2 ports in the SMC SuperIO
12 * o 1 port in the CBUS UART, a discrete 16550 which normally is only used
13 * for bringups.
14 *
15 * We don't use 8250_platform.c on Malta as it would result in the CBUS
16 * UART becoming ttyS0.
17 */
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/serial_8250.h>
21
22#define SMC_PORT(base, int) \
23{ \
24 .iobase = base, \
25 .irq = int, \
26 .uartclk = 1843200, \
27 .iotype = UPIO_PORT, \
28 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
29 .regshift = 0, \
30}
31
32#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
33
34static struct plat_serial8250_port uart8250_data[] = {
35 SMC_PORT(0x3F8, 4),
36 SMC_PORT(0x2F8, 3),
37 {
38 .mapbase = 0x1f000900, /* The CBUS UART */
39 .irq = MIPS_CPU_IRQ_BASE + 2,
40 .uartclk = 3686400, /* Twice the usual clk! */
41 .iotype = UPIO_MEM32,
42 .flags = CBUS_UART_FLAGS,
43 .regshift = 3,
44 },
45 { },
46};
47
48static struct platform_device uart8250_device = {
49 .name = "serial8250",
50 .id = PLAT8250_DEV_PLATFORM2,
51 .dev = {
52 .platform_data = uart8250_data,
53 },
54};
55
56static int __init uart8250_init(void)
57{
58 return platform_device_register(&uart8250_device);
59}
60
61module_init(uart8250_init);
62
63MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
64MODULE_LICENSE("GPL");
65MODULE_DESCRIPTION("8250 UART probe driver for the Malta CBUS UART");
diff --git a/arch/mips/mips-boards/sim/Makefile b/arch/mips/mipssim/Makefile
index dc0bfda11427..dc0bfda11427 100644
--- a/arch/mips/mips-boards/sim/Makefile
+++ b/arch/mips/mipssim/Makefile
diff --git a/arch/mips/mips-boards/sim/sim_cmdline.c b/arch/mips/mipssim/sim_cmdline.c
index c63021a5dc6c..c63021a5dc6c 100644
--- a/arch/mips/mips-boards/sim/sim_cmdline.c
+++ b/arch/mips/mipssim/sim_cmdline.c
diff --git a/arch/mips/mips-boards/sim/sim_console.c b/arch/mips/mipssim/sim_console.c
index de595a9ccb27..a2f41672cd5d 100644
--- a/arch/mips/mips-boards/sim/sim_console.c
+++ b/arch/mips/mipssim/sim_console.c
@@ -18,8 +18,8 @@
18 * written by Ralf Baechle 18 * written by Ralf Baechle
19 */ 19 */
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/io.h>
21#include <linux/serial_reg.h> 22#include <linux/serial_reg.h>
22#include <asm/io.h>
23 23
24static inline unsigned int serial_in(int offset) 24static inline unsigned int serial_in(int offset)
25{ 25{
diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c
new file mode 100644
index 000000000000..d86b37235cf6
--- /dev/null
+++ b/arch/mips/mipssim/sim_int.c
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 */
18#include <linux/init.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/interrupt.h>
22#include <linux/kernel_stat.h>
23#include <asm/mips-boards/simint.h>
24#include <asm/irq_cpu.h>
25
26static inline int clz(unsigned long x)
27{
28 __asm__ (
29 " .set push \n"
30 " .set mips32 \n"
31 " clz %0, %1 \n"
32 " .set pop \n"
33 : "=r" (x)
34 : "r" (x));
35
36 return x;
37}
38
39/*
40 * Version of ffs that only looks at bits 12..15.
41 */
42static inline unsigned int irq_ffs(unsigned int pending)
43{
44#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
45 return -clz(pending) + 31 - CAUSEB_IP;
46#else
47 unsigned int a0 = 7;
48 unsigned int t0;
49
50 t0 = s0 & 0xf000;
51 t0 = t0 < 1;
52 t0 = t0 << 2;
53 a0 = a0 - t0;
54 s0 = s0 << t0;
55
56 t0 = s0 & 0xc000;
57 t0 = t0 < 1;
58 t0 = t0 << 1;
59 a0 = a0 - t0;
60 s0 = s0 << t0;
61
62 t0 = s0 & 0x8000;
63 t0 = t0 < 1;
64 /* t0 = t0 << 2; */
65 a0 = a0 - t0;
66 /* s0 = s0 << t0; */
67
68 return a0;
69#endif
70}
71
72asmlinkage void plat_irq_dispatch(void)
73{
74 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
75 int irq;
76
77 irq = irq_ffs(pending);
78
79 if (irq > 0)
80 do_IRQ(MIPSCPU_INT_BASE + irq);
81 else
82 spurious_interrupt();
83}
84
85void __init arch_init_irq(void)
86{
87 mips_cpu_irq_init();
88}
diff --git a/arch/mips/mips-boards/sim/sim_mem.c b/arch/mips/mipssim/sim_mem.c
index e408ef0bcd6e..2312483eb838 100644
--- a/arch/mips/mips-boards/sim/sim_mem.c
+++ b/arch/mips/mipssim/sim_mem.c
@@ -95,7 +95,7 @@ void __init prom_meminit(void)
95 size = p->size; 95 size = p->size;
96 96
97 add_memory_region(base, size, type); 97 add_memory_region(base, size, type);
98 p++; 98 p++;
99 } 99 }
100} 100}
101 101
diff --git a/arch/mips/mips-boards/sim/sim_platform.c b/arch/mips/mipssim/sim_platform.c
index 53210a8c5dec..53210a8c5dec 100644
--- a/arch/mips/mips-boards/sim/sim_platform.c
+++ b/arch/mips/mipssim/sim_platform.c
diff --git a/arch/mips/mips-boards/sim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index b705f09e57c3..3643582bdade 100644
--- a/arch/mips/mips-boards/sim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -19,18 +19,18 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/string.h> 20#include <linux/string.h>
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/irq.h>
22#include <linux/ioport.h> 24#include <linux/ioport.h>
25#include <linux/serial.h>
23#include <linux/tty.h> 26#include <linux/tty.h>
24#include <linux/serial.h> 27#include <linux/serial.h>
25#include <linux/serial_core.h> 28#include <linux/serial_core.h>
26 29
27#include <asm/cpu.h> 30#include <asm/cpu.h>
28#include <asm/bootinfo.h> 31#include <asm/bootinfo.h>
29#include <asm/irq.h>
30#include <asm/mips-boards/generic.h> 32#include <asm/mips-boards/generic.h>
31#include <asm/mips-boards/prom.h> 33#include <asm/mips-boards/prom.h>
32#include <asm/serial.h>
33#include <asm/io.h>
34#include <asm/time.h> 34#include <asm/time.h>
35#include <asm/mips-boards/sim.h> 35#include <asm/mips-boards/sim.h>
36#include <asm/mips-boards/simint.h> 36#include <asm/mips-boards/simint.h>
@@ -62,7 +62,7 @@ void __init plat_mem_setup(void)
62#endif 62#endif
63} 63}
64 64
65void prom_init(void) 65void __init prom_init(void)
66{ 66{
67 set_io_port_base(0xbfd00000); 67 set_io_port_base(0xbfd00000);
68 68
diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mipssim/sim_smp.c
index cb47863ecf10..38fa807b99f9 100644
--- a/arch/mips/mips-boards/sim/sim_smp.c
+++ b/arch/mips/mipssim/sim_smp.c
@@ -22,13 +22,13 @@
22#include <linux/sched.h> 22#include <linux/sched.h>
23#include <linux/cpumask.h> 23#include <linux/cpumask.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/smp.h>
26
25#include <asm/atomic.h> 27#include <asm/atomic.h>
26#include <asm/cpu.h> 28#include <asm/cpu.h>
27#include <asm/processor.h> 29#include <asm/processor.h>
28#include <asm/system.h> 30#include <asm/system.h>
29#include <asm/hardirq.h>
30#include <asm/mmu_context.h> 31#include <asm/mmu_context.h>
31#include <asm/smp.h>
32#ifdef CONFIG_MIPS_MT_SMTC 32#ifdef CONFIG_MIPS_MT_SMTC
33#include <asm/smtc_ipi.h> 33#include <asm/smtc_ipi.h>
34#endif /* CONFIG_MIPS_MT_SMTC */ 34#endif /* CONFIG_MIPS_MT_SMTC */
@@ -73,11 +73,19 @@ void prom_init_secondary(void)
73#endif /* CONFIG_MIPS_MT_SMTC */ 73#endif /* CONFIG_MIPS_MT_SMTC */
74} 74}
75 75
76void plat_smp_setup(void)
77{
78#ifdef CONFIG_MIPS_MT_SMTC
79 if (read_c0_config3() & (1 << 2))
80 mipsmt_build_cpu_map(0);
81#endif /* CONFIG_MIPS_MT_SMTC */
82}
83
76/* 84/*
77 * Platform SMP pre-initialization 85 * Platform SMP pre-initialization
78 */ 86 */
79 87
80void prom_prepare_cpus(unsigned int max_cpus) 88void plat_prepare_cpus(unsigned int max_cpus)
81{ 89{
82#ifdef CONFIG_MIPS_MT_SMTC 90#ifdef CONFIG_MIPS_MT_SMTC
83 /* 91 /*
@@ -85,8 +93,8 @@ void prom_prepare_cpus(unsigned int max_cpus)
85 * but it may be multithreaded. 93 * but it may be multithreaded.
86 */ 94 */
87 95
88 if (read_c0_config3() & (1<<2)) { 96 if (read_c0_config3() & (1 << 2)) {
89 mipsmt_prepare_cpus(max_cpus); 97 mipsmt_prepare_cpus();
90 } 98 }
91#endif /* CONFIG_MIPS_MT_SMTC */ 99#endif /* CONFIG_MIPS_MT_SMTC */
92} 100}
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mipssim/sim_time.c
index 7224ffe31d36..874a18e8ac24 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -5,10 +5,10 @@
5#include <linux/spinlock.h> 5#include <linux/spinlock.h>
6#include <linux/interrupt.h> 6#include <linux/interrupt.h>
7#include <linux/mc146818rtc.h> 7#include <linux/mc146818rtc.h>
8#include <linux/mipsregs.h>
9#include <linux/smp.h>
8#include <linux/timex.h> 10#include <linux/timex.h>
9 11
10#include <asm/mipsregs.h>
11#include <asm/ptrace.h>
12#include <asm/hardirq.h> 12#include <asm/hardirq.h>
13#include <asm/div64.h> 13#include <asm/div64.h>
14#include <asm/cpu.h> 14#include <asm/cpu.h>
@@ -16,7 +16,6 @@
16#include <asm/irq.h> 16#include <asm/irq.h>
17#include <asm/mc146818-time.h> 17#include <asm/mc146818-time.h>
18#include <asm/msc01_ic.h> 18#include <asm/msc01_ic.h>
19#include <asm/smp.h>
20 19
21#include <asm/mips-boards/generic.h> 20#include <asm/mips-boards/generic.h>
22#include <asm/mips-boards/prom.h> 21#include <asm/mips-boards/prom.h>
@@ -37,8 +36,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
37#ifndef CONFIG_MIPS_MT_SMTC 36#ifndef CONFIG_MIPS_MT_SMTC
38 if (cpu == 0) { 37 if (cpu == 0) {
39 timer_interrupt(irq, dev_id); 38 timer_interrupt(irq, dev_id);
40 } 39 } else {
41 else {
42 /* Everyone else needs to reset the timer int here as 40 /* Everyone else needs to reset the timer int here as
43 ll_local_timer_interrupt doesn't */ 41 ll_local_timer_interrupt doesn't */
44 /* 42 /*
@@ -76,8 +74,10 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
76 irq_enable_hazard(); 74 irq_enable_hazard();
77 evpe(vpflags); 75 evpe(vpflags);
78 76
79 if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id); 77 if (cpu_data[cpu].vpe_id == 0)
80 else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ)); 78 timer_interrupt(irq, dev_id);
79 else
80 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
81 smtc_timer_broadcast(cpu_data[cpu].vpe_id); 81 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
82 82
83#endif /* CONFIG_MIPS_MT_SMTC */ 83#endif /* CONFIG_MIPS_MT_SMTC */
@@ -85,7 +85,8 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
85 /* 85 /*
86 * every CPU should do profiling and process accounting 86 * every CPU should do profiling and process accounting
87 */ 87 */
88 local_timer_interrupt (irq, dev_id); 88 local_timer_interrupt (irq, dev_id);
89
89 return IRQ_HANDLED; 90 return IRQ_HANDLED;
90#else 91#else
91 return timer_interrupt (irq, dev_id); 92 return timer_interrupt (irq, dev_id);
@@ -152,17 +153,15 @@ void __init sim_time_init(void)
152 153
153 local_irq_save(flags); 154 local_irq_save(flags);
154 155
155 156 /* Set Data mode - binary. */
156 /* Set Data mode - binary. */
157 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 157 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
158 158
159
160 est_freq = estimate_cpu_frequency (); 159 est_freq = estimate_cpu_frequency ();
161 160
162 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 161 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
163 (est_freq%1000000)*100/1000000); 162 (est_freq % 1000000) * 100 / 1000000);
164 163
165 cpu_khz = est_freq / 1000; 164 cpu_khz = est_freq / 1000;
166 165
167 local_irq_restore(flags); 166 local_irq_restore(flags);
168} 167}
@@ -180,8 +179,7 @@ void __init plat_timer_setup(struct irqaction *irq)
180 if (cpu_has_veic) { 179 if (cpu_has_veic) {
181 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); 180 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
182 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 181 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
183 } 182 } else {
184 else {
185 if (cpu_has_vint) 183 if (cpu_has_vint)
186 set_vi_handler(cp0_compare_irq, mips_timer_dispatch); 184 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
187 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 185 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 293697b15603..19a0e544c4e9 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
9obj-$(CONFIG_64BIT) += pgtable-64.o 9obj-$(CONFIG_64BIT) += pgtable-64.o
10obj-$(CONFIG_HIGHMEM) += highmem.o 10obj-$(CONFIG_HIGHMEM) += highmem.o
11 11
12obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
12obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 13obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
13obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 14obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
14obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 15obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index df04a315d830..be96231dccb6 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -335,6 +335,10 @@ static void r4k_flush_cache_all(void)
335 335
336static inline void local_r4k___flush_cache_all(void * args) 336static inline void local_r4k___flush_cache_all(void * args)
337{ 337{
338#if defined(CONFIG_CPU_LOONGSON2)
339 r4k_blast_scache();
340 return;
341#endif
338 r4k_blast_dcache(); 342 r4k_blast_dcache();
339 r4k_blast_icache(); 343 r4k_blast_icache();
340 344
@@ -848,6 +852,24 @@ static void __init probe_pcache(void)
848 c->options |= MIPS_CPU_PREFETCH; 852 c->options |= MIPS_CPU_PREFETCH;
849 break; 853 break;
850 854
855 case CPU_LOONGSON2:
856 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
857 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
858 if (prid & 0x3)
859 c->icache.ways = 4;
860 else
861 c->icache.ways = 2;
862 c->icache.waybit = 0;
863
864 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
865 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
866 if (prid & 0x3)
867 c->dcache.ways = 4;
868 else
869 c->dcache.ways = 2;
870 c->dcache.waybit = 0;
871 break;
872
851 default: 873 default:
852 if (!(config & MIPS_CONF_M)) 874 if (!(config & MIPS_CONF_M))
853 panic("Don't know how to probe P-caches on this cpu."); 875 panic("Don't know how to probe P-caches on this cpu.");
@@ -963,6 +985,14 @@ static void __init probe_pcache(void)
963 break; 985 break;
964 } 986 }
965 987
988#ifdef CONFIG_CPU_LOONGSON2
989 /*
990 * LOONGSON2 has 4 way icache, but when using indexed cache op,
991 * one op will act on all 4 ways
992 */
993 c->icache.ways = 1;
994#endif
995
966 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 996 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
967 icache_size >> 10, 997 icache_size >> 10,
968 cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", 998 cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
@@ -1036,6 +1066,24 @@ static int __init probe_scache(void)
1036 return 1; 1066 return 1;
1037} 1067}
1038 1068
1069#if defined(CONFIG_CPU_LOONGSON2)
1070static void __init loongson2_sc_init(void)
1071{
1072 struct cpuinfo_mips *c = &current_cpu_data;
1073
1074 scache_size = 512*1024;
1075 c->scache.linesz = 32;
1076 c->scache.ways = 4;
1077 c->scache.waybit = 0;
1078 c->scache.waysize = scache_size / (c->scache.ways);
1079 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1080 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1081 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1082
1083 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1084}
1085#endif
1086
1039extern int r5k_sc_init(void); 1087extern int r5k_sc_init(void);
1040extern int rm7k_sc_init(void); 1088extern int rm7k_sc_init(void);
1041extern int mips_sc_init(void); 1089extern int mips_sc_init(void);
@@ -1085,6 +1133,12 @@ static void __init setup_scache(void)
1085#endif 1133#endif
1086 return; 1134 return;
1087 1135
1136#if defined(CONFIG_CPU_LOONGSON2)
1137 case CPU_LOONGSON2:
1138 loongson2_sc_init();
1139 return;
1140#endif
1141
1088 default: 1142 default:
1089 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1143 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1090 c->isa_level == MIPS_CPU_ISA_M32R2 || 1144 c->isa_level == MIPS_CPU_ISA_M32R2 ||
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index 9ea460b16bda..6f9bd7fbd481 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -476,7 +476,7 @@ static __init void probe_cache_sizes(void)
476 * memory management function pointers, as well as initialize 476 * memory management function pointers, as well as initialize
477 * the caches and tlbs 477 * the caches and tlbs
478 */ 478 */
479void sb1_cache_init(void) 479void __init sb1_cache_init(void)
480{ 480{
481 extern char except_vec2_sb1; 481 extern char except_vec2_sb1;
482 482
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index abf99b1eba13..81f925a9a731 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -6,6 +6,8 @@
6 * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 MIPS Technologies, Inc. 7 * Copyright (C) 2007 MIPS Technologies, Inc.
8 */ 8 */
9#include <linux/fs.h>
10#include <linux/fcntl.h>
9#include <linux/init.h> 11#include <linux/init.h>
10#include <linux/kernel.h> 12#include <linux/kernel.h>
11#include <linux/module.h> 13#include <linux/module.h>
@@ -164,3 +166,11 @@ void __init cpu_cache_init(void)
164 166
165 panic(cache_panic); 167 panic(cache_panic);
166} 168}
169
170int __weak __uncached_access(struct file *file, unsigned long addr)
171{
172 if (file->f_flags & O_SYNC)
173 return 1;
174
175 return addr >= __pa(high_memory);
176}
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 65160d4984d9..dcd6913dc1ff 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -48,6 +48,22 @@ extern void build_tlb_refill_handler(void);
48 48
49#endif /* CONFIG_MIPS_MT_SMTC */ 49#endif /* CONFIG_MIPS_MT_SMTC */
50 50
51#if defined(CONFIG_CPU_LOONGSON2)
52/*
53 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
54 * unfortrunately, itlb is not totally transparent to software.
55 */
56#define FLUSH_ITLB write_c0_diag(4);
57
58#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
59
60#else
61
62#define FLUSH_ITLB
63#define FLUSH_ITLB_VM(vma)
64
65#endif
66
51void local_flush_tlb_all(void) 67void local_flush_tlb_all(void)
52{ 68{
53 unsigned long flags; 69 unsigned long flags;
@@ -73,6 +89,7 @@ void local_flush_tlb_all(void)
73 } 89 }
74 tlbw_use_hazard(); 90 tlbw_use_hazard();
75 write_c0_entryhi(old_ctx); 91 write_c0_entryhi(old_ctx);
92 FLUSH_ITLB;
76 EXIT_CRITICAL(flags); 93 EXIT_CRITICAL(flags);
77} 94}
78 95
@@ -136,6 +153,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
136 } else { 153 } else {
137 drop_mmu_context(mm, cpu); 154 drop_mmu_context(mm, cpu);
138 } 155 }
156 FLUSH_ITLB;
139 EXIT_CRITICAL(flags); 157 EXIT_CRITICAL(flags);
140 } 158 }
141} 159}
@@ -178,6 +196,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
178 } else { 196 } else {
179 local_flush_tlb_all(); 197 local_flush_tlb_all();
180 } 198 }
199 FLUSH_ITLB;
181 EXIT_CRITICAL(flags); 200 EXIT_CRITICAL(flags);
182} 201}
183 202
@@ -210,6 +229,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
210 229
211 finish: 230 finish:
212 write_c0_entryhi(oldpid); 231 write_c0_entryhi(oldpid);
232 FLUSH_ITLB_VM(vma);
213 EXIT_CRITICAL(flags); 233 EXIT_CRITICAL(flags);
214 } 234 }
215} 235}
@@ -241,7 +261,7 @@ void local_flush_tlb_one(unsigned long page)
241 tlbw_use_hazard(); 261 tlbw_use_hazard();
242 } 262 }
243 write_c0_entryhi(oldpid); 263 write_c0_entryhi(oldpid);
244 264 FLUSH_ITLB;
245 EXIT_CRITICAL(flags); 265 EXIT_CRITICAL(flags);
246} 266}
247 267
@@ -293,6 +313,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
293 else 313 else
294 tlb_write_indexed(); 314 tlb_write_indexed();
295 tlbw_use_hazard(); 315 tlbw_use_hazard();
316 FLUSH_ITLB_VM(vma);
296 EXIT_CRITICAL(flags); 317 EXIT_CRITICAL(flags);
297} 318}
298 319
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index e7149290d1cb..4ec0964b8394 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -893,6 +893,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
893 case CPU_4KSC: 893 case CPU_4KSC:
894 case CPU_20KC: 894 case CPU_20KC:
895 case CPU_25KF: 895 case CPU_25KF:
896 case CPU_LOONGSON2:
896 tlbw(p); 897 tlbw(p);
897 break; 898 break;
898 899
@@ -1276,7 +1277,8 @@ static void __init build_r4000_tlb_refill_handler(void)
1276 * need three, with the second nop'ed and the third being 1277 * need three, with the second nop'ed and the third being
1277 * unused. 1278 * unused.
1278 */ 1279 */
1279#ifdef CONFIG_32BIT 1280 /* Loongson2 ebase is different than r4k, we have more space */
1281#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1280 if ((p - tlb_handler) > 64) 1282 if ((p - tlb_handler) > 64)
1281 panic("TLB refill handler space exceeded"); 1283 panic("TLB refill handler space exceeded");
1282#else 1284#else
@@ -1289,7 +1291,7 @@ static void __init build_r4000_tlb_refill_handler(void)
1289 /* 1291 /*
1290 * Now fold the handler in the TLB refill handler space. 1292 * Now fold the handler in the TLB refill handler space.
1291 */ 1293 */
1292#ifdef CONFIG_32BIT 1294#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1293 f = final_handler; 1295 f = final_handler;
1294 /* Simplest case, just copy the handler. */ 1296 /* Simplest case, just copy the handler. */
1295 copy_handler(relocs, labels, tlb_handler, p, f); 1297 copy_handler(relocs, labels, tlb_handler, p, f);
@@ -1336,7 +1338,7 @@ static void __init build_r4000_tlb_refill_handler(void)
1336 final_len); 1338 final_len);
1337 1339
1338 f = final_handler; 1340 f = final_handler;
1339#ifdef CONFIG_64BIT 1341#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2)
1340 if (final_len > 32) 1342 if (final_len > 32)
1341 final_len = 64; 1343 final_len = 64;
1342 else 1344 else
diff --git a/arch/mips/momentum/ocelot_3/Makefile b/arch/mips/momentum/ocelot_3/Makefile
deleted file mode 100644
index d5a090a85a15..000000000000
--- a/arch/mips/momentum/ocelot_3/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for Momentum Computer's Ocelot-3 board.
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8obj-y += irq.o platform.o prom.o reset.o setup.o
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c
deleted file mode 100644
index 3862d1d1add4..000000000000
--- a/arch/mips/momentum/ocelot_3/irq.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
9 *
10 * Copyright 2004 PMC-Sierra
11 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 * Copyright (C) 2004 MontaVista Software Inc.
34 * Author: Manish Lachwani, mlachwani@mvista.com
35 *
36 */
37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/kernel_stat.h>
40#include <linux/module.h>
41#include <linux/signal.h>
42#include <linux/sched.h>
43#include <linux/types.h>
44#include <linux/interrupt.h>
45#include <linux/ioport.h>
46#include <linux/timex.h>
47#include <linux/slab.h>
48#include <linux/random.h>
49#include <asm/bitops.h>
50#include <asm/bootinfo.h>
51#include <asm/io.h>
52#include <asm/irq.h>
53#include <asm/mipsregs.h>
54#include <asm/system.h>
55
56static struct irqaction cascade_mv64340 = {
57 no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
58};
59
60void __init arch_init_irq(void)
61{
62 /*
63 * Clear all of the interrupts while we change the able around a bit.
64 * int-handler is not on bootstrap
65 */
66 clear_c0_status(ST0_IM | ST0_BEV);
67
68 rm7k_cpu_irq_init();
69
70 /* set up the cascading interrupts */
71 setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */
72 mv64340_irq_init(16);
73
74 set_c0_status(ST0_IM); /* IE in the status register */
75
76}
77
78asmlinkage void plat_irq_dispatch(void)
79{
80 unsigned int pending = read_c0_cause() & read_c0_status();
81
82 if (pending & STATUSF_IP0)
83 do_IRQ(0);
84 else if (pending & STATUSF_IP1)
85 do_IRQ(1);
86 else if (pending & STATUSF_IP2)
87 do_IRQ(2);
88 else if (pending & STATUSF_IP3)
89 do_IRQ(3);
90 else if (pending & STATUSF_IP4)
91 do_IRQ(4);
92 else if (pending & STATUSF_IP5)
93 do_IRQ(5);
94 else if (pending & STATUSF_IP6)
95 do_IRQ(6);
96 else if (pending & STATUSF_IP7)
97 do_IRQ(7);
98 else {
99 /*
100 * Now look at the extended interrupts
101 */
102 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
103
104 if (pending & STATUSF_IP8)
105 ll_mv64340_irq();
106 else
107 spurious_interrupt();
108 }
109}
diff --git a/arch/mips/momentum/ocelot_3/platform.c b/arch/mips/momentum/ocelot_3/platform.c
deleted file mode 100644
index 44e4c3fc7403..000000000000
--- a/arch/mips/momentum/ocelot_3/platform.c
+++ /dev/null
@@ -1,208 +0,0 @@
1#include <linux/delay.h>
2#include <linux/if_ether.h>
3#include <linux/ioport.h>
4#include <linux/mv643xx.h>
5#include <linux/platform_device.h>
6
7#include "ocelot_3_fpga.h"
8
9#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
11static struct resource mv643xx_eth_shared_resources[] = {
12 [0] = {
13 .name = "ethernet shared base",
14 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16 MV643XX_ETH_SHARED_REGS_SIZE - 1,
17 .flags = IORESOURCE_MEM,
18 },
19};
20
21static struct platform_device mv643xx_eth_shared_device = {
22 .name = MV643XX_ETH_SHARED_NAME,
23 .id = 0,
24 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25 .resource = mv643xx_eth_shared_resources,
26};
27
28#define MV_SRAM_BASE 0xfe000000UL
29#define MV_SRAM_SIZE (256 * 1024)
30
31#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
34#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
37#define MV64x60_IRQ_ETH_0 48
38#define MV64x60_IRQ_ETH_1 49
39#define MV64x60_IRQ_ETH_2 50
40
41static struct resource mv64x60_eth0_resources[] = {
42 [0] = {
43 .name = "eth0 irq",
44 .start = MV64x60_IRQ_ETH_0,
45 .end = MV64x60_IRQ_ETH_0,
46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50static struct mv643xx_eth_platform_data eth0_pd = {
51 .port_number = 0,
52
53 .tx_sram_addr = MV_SRAM_BASE_ETH0,
54 .tx_sram_size = MV_SRAM_TXRING_SIZE,
55 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
56
57 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
58 .rx_sram_size = MV_SRAM_RXRING_SIZE,
59 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
60};
61
62static struct platform_device eth0_device = {
63 .name = MV643XX_ETH_NAME,
64 .id = 0,
65 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
66 .resource = mv64x60_eth0_resources,
67 .dev = {
68 .platform_data = &eth0_pd,
69 },
70};
71
72static struct resource mv64x60_eth1_resources[] = {
73 [0] = {
74 .name = "eth1 irq",
75 .start = MV64x60_IRQ_ETH_1,
76 .end = MV64x60_IRQ_ETH_1,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct mv643xx_eth_platform_data eth1_pd = {
82 .port_number = 1,
83
84 .tx_sram_addr = MV_SRAM_BASE_ETH1,
85 .tx_sram_size = MV_SRAM_TXRING_SIZE,
86 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
87
88 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
89 .rx_sram_size = MV_SRAM_RXRING_SIZE,
90 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
91};
92
93static struct platform_device eth1_device = {
94 .name = MV643XX_ETH_NAME,
95 .id = 1,
96 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
97 .resource = mv64x60_eth1_resources,
98 .dev = {
99 .platform_data = &eth1_pd,
100 },
101};
102
103static struct resource mv64x60_eth2_resources[] = {
104 [0] = {
105 .name = "eth2 irq",
106 .start = MV64x60_IRQ_ETH_2,
107 .end = MV64x60_IRQ_ETH_2,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112static struct mv643xx_eth_platform_data eth2_pd = {
113 .port_number = 2,
114};
115
116static struct platform_device eth2_device = {
117 .name = MV643XX_ETH_NAME,
118 .id = 2,
119 .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
120 .resource = mv64x60_eth2_resources,
121 .dev = {
122 .platform_data = &eth2_pd,
123 },
124};
125
126static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
127 &mv643xx_eth_shared_device,
128 &eth0_device,
129 &eth1_device,
130 &eth2_device,
131};
132
133static u8 __init exchange_bit(u8 val, u8 cs)
134{
135 /* place the data */
136 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
137 udelay(1);
138
139 /* turn the clock on */
140 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
141 udelay(1);
142
143 /* turn the clock off and read-strobe */
144 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
145
146 /* return the data */
147 return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
148}
149
150static void __init get_mac(char dest[6])
151{
152 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
153 int i,j;
154
155 for (i = 0; i < 12; i++)
156 exchange_bit(read_opcode[i], 1);
157
158 for (j = 0; j < 6; j++) {
159 dest[j] = 0;
160 for (i = 0; i < 8; i++) {
161 dest[j] <<= 1;
162 dest[j] |= exchange_bit(0, 1);
163 }
164 }
165
166 /* turn off CS */
167 exchange_bit(0,0);
168}
169
170/*
171 * Copy and increment ethernet MAC address by a small value.
172 *
173 * This is useful for systems where the only one MAC address is stored in
174 * non-volatile memory for multiple ports.
175 */
176static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
177 unsigned int add)
178{
179 int i;
180
181 BUG_ON(add >= 256);
182
183 for (i = ETH_ALEN; i >= 0; i--) {
184 dst[i] = src[i] + add;
185 add = dst[i] < src[i]; /* compute carry */
186 }
187
188 WARN_ON(add);
189}
190
191static int __init mv643xx_eth_add_pds(void)
192{
193 unsigned char mac[ETH_ALEN];
194 int ret;
195
196 get_mac(mac);
197 eth_mac_add(eth0_pd.mac_addr, mac, 0);
198 eth_mac_add(eth1_pd.mac_addr, mac, 1);
199 eth_mac_add(eth2_pd.mac_addr, mac, 2);
200 ret = platform_add_devices(mv643xx_eth_pd_devs,
201 ARRAY_SIZE(mv643xx_eth_pd_devs));
202
203 return ret;
204}
205
206device_initcall(mv643xx_eth_add_pds);
207
208#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c
deleted file mode 100644
index 8e02df63578a..000000000000
--- a/arch/mips/momentum/ocelot_3/prom.c
+++ /dev/null
@@ -1,189 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Copyright 2004 PMC-Sierra
9 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Based on Ocelot Linux port, which is
12 * Copyright 2001 MontaVista Software Inc.
13 * Author: jsun@mvista.com or jsun@junsun.net
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Copyright (C) 2004 MontaVista Software Inc.
21 * Author: Manish Lachwani, mlachwani@mvista.com
22 *
23 */
24#include <linux/init.h>
25#include <linux/bootmem.h>
26#include <linux/mv643xx.h>
27
28#include <asm/addrspace.h>
29#include <asm/bootinfo.h>
30#include <asm/pmon.h>
31#include "ocelot_3_fpga.h"
32
33struct callvectors* debug_vectors;
34extern unsigned long marvell_base;
35extern unsigned long cpu_clock;
36
37const char *get_system_type(void)
38{
39 return "Momentum Ocelot-3";
40}
41
42#ifdef CONFIG_64BIT
43
44unsigned long signext(unsigned long addr)
45{
46 addr &= 0xffffffff;
47 return (unsigned long)((int)addr);
48}
49
50void *get_arg(unsigned long args, int arc)
51{
52 unsigned long ul;
53 unsigned char *puc, uc;
54
55 args += (arc * 4);
56 ul = (unsigned long)signext(args);
57 puc = (unsigned char *)ul;
58 if (puc == 0)
59 return (void *)0;
60
61#ifdef CONFIG_CPU_LITTLE_ENDIAN
62 uc = *puc++;
63 ul = (unsigned long)uc;
64 uc = *puc++;
65 ul |= (((unsigned long)uc) << 8);
66 uc = *puc++;
67 ul |= (((unsigned long)uc) << 16);
68 uc = *puc++;
69 ul |= (((unsigned long)uc) << 24);
70#else /* CONFIG_CPU_LITTLE_ENDIAN */
71 uc = *puc++;
72 ul = ((unsigned long)uc) << 24;
73 uc = *puc++;
74 ul |= (((unsigned long)uc) << 16);
75 uc = *puc++;
76 ul |= (((unsigned long)uc) << 8);
77 uc = *puc++;
78 ul |= ((unsigned long)uc);
79#endif /* CONFIG_CPU_LITTLE_ENDIAN */
80 ul = signext(ul);
81 return (void *)ul;
82}
83
84char *arg64(unsigned long addrin, int arg_index)
85{
86 unsigned long args;
87 char *p;
88
89 args = signext(addrin);
90 p = (char *)get_arg(args, arg_index);
91
92 return p;
93}
94#endif /* CONFIG_64BIT */
95
96void __init prom_init(void)
97{
98 int argc = fw_arg0;
99 char **arg = (char **) fw_arg1;
100 char **env = (char **) fw_arg2;
101 struct callvectors *cv = (struct callvectors *) fw_arg3;
102 int i;
103
104#ifdef CONFIG_64BIT
105 char *ptr;
106 printk("prom_init - MIPS64\n");
107
108 /* save the PROM vectors for debugging use */
109 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
110
111 /* arg[0] is "g", the rest is boot parameters */
112 arcs_cmdline[0] = '\0';
113
114 for (i = 1; i < argc; i++) {
115 ptr = (char *)arg64((unsigned long)arg, i);
116 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
117 sizeof(arcs_cmdline))
118 break;
119 strcat(arcs_cmdline, ptr);
120 strcat(arcs_cmdline, " ");
121 }
122 i = 0;
123
124 while (1) {
125 ptr = (char *)arg64((unsigned long)env, i);
126 if (! ptr)
127 break;
128
129 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
130 marvell_base = simple_strtol(ptr + strlen("gtbase="),
131 NULL, 16);
132
133 if ((marvell_base & 0xffffffff00000000) == 0)
134 marvell_base |= 0xffffffff00000000;
135
136 printk("marvell_base set to 0x%016lx\n", marvell_base);
137 }
138 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
139 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
140 NULL, 10);
141 printk("cpu_clock set to %d\n", cpu_clock);
142 }
143 i++;
144 }
145 printk("arcs_cmdline: %s\n", arcs_cmdline);
146
147#else /* CONFIG_64BIT */
148
149 /* save the PROM vectors for debugging use */
150 debug_vectors = cv;
151
152 /* arg[0] is "g", the rest is boot parameters */
153 arcs_cmdline[0] = '\0';
154 for (i = 1; i < argc; i++) {
155 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
156 >= sizeof(arcs_cmdline))
157 break;
158 strcat(arcs_cmdline, arg[i]);
159 strcat(arcs_cmdline, " ");
160 }
161
162 while (*env) {
163 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
164 marvell_base = simple_strtol(*env + strlen("gtbase="),
165 NULL, 16);
166 }
167 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
168 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
169 NULL, 10);
170 }
171 env++;
172 }
173#endif /* CONFIG_64BIT */
174
175 mips_machgroup = MACH_GROUP_MOMENCO;
176 mips_machtype = MACH_MOMENCO_OCELOT_3;
177
178#ifndef CONFIG_64BIT
179 debug_vectors->printf("Booting Linux kernel...\n");
180#endif
181}
182
183void __init prom_free_prom_memory(void)
184{
185}
186
187void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
188{
189}
diff --git a/arch/mips/momentum/ocelot_3/reset.c b/arch/mips/momentum/ocelot_3/reset.c
deleted file mode 100644
index 9d86d2468376..000000000000
--- a/arch/mips/momentum/ocelot_3/reset.c
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 01, 05 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 *
17 * Copyright 2004 PMC-Sierra
18 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
19 *
20 * Copyright (C) 2004 MontaVista Software Inc.
21 * Author: Manish Lachwani, mlachwani@mvista.com
22 */
23#include <linux/sched.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <asm/io.h>
27#include <asm/pgtable.h>
28#include <asm/processor.h>
29#include <asm/reboot.h>
30#include <asm/system.h>
31
32void momenco_ocelot_restart(char *command)
33{
34 /* base address of timekeeper portion of part */
35 void *nvram = (void *) 0xfc807000L;
36
37 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
38 writeb(0x84, nvram + 0xff7);
39
40 /* wait for the watchdog to go off */
41 mdelay(100+(1000/16));
42
43 /* if the watchdog fails for some reason, let people know */
44 printk(KERN_NOTICE "Watchdog reset failed\n");
45}
46
47void momenco_ocelot_halt(void)
48{
49 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
50 while (1)
51 __asm__(".set\tmips3\n\t"
52 "wait\n\t"
53 ".set\tmips0");
54}
55
56void momenco_ocelot_power_off(void)
57{
58 momenco_ocelot_halt();
59}
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
deleted file mode 100644
index ff0829f81116..000000000000
--- a/arch/mips/momentum/ocelot_3/setup.c
+++ /dev/null
@@ -1,398 +0,0 @@
1/*
2 * setup.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot-3 board dependent boot routines
6 *
7 * Copyright (C) 1996, 1997, 01, 05 - 06 Ralf Baechle
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer
11 *
12 * Author: Matthew Dharm, Momentum Computer
13 * mdharm@momenco.com
14 *
15 * Louis Hamilton, Red Hat, Inc.
16 * hamilton@redhat.com [MIPS64 modifications]
17 *
18 * Author: RidgeRun, Inc.
19 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
20 *
21 * Copyright 2001 MontaVista Software Inc.
22 * Author: jsun@mvista.com or jsun@junsun.net
23 *
24 * Copyright 2004 PMC-Sierra
25 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
26 *
27 * Copyright (C) 2004 MontaVista Software Inc.
28 * Author: Manish Lachwani, mlachwani@mvista.com
29 *
30 * This program is free software; you can redistribute it and/or modify it
31 * under the terms of the GNU General Public License as published by the
32 * Free Software Foundation; either version 2 of the License, or (at your
33 * option) any later version.
34 *
35 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
36 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
37 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
38 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
40 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
41 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
42 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
44 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 * You should have received a copy of the GNU General Public License along
47 * with this program; if not, write to the Free Software Foundation, Inc.,
48 * 675 Mass Ave, Cambridge, MA 02139, USA.
49 */
50#include <linux/init.h>
51#include <linux/kernel.h>
52#include <linux/types.h>
53#include <linux/mc146818rtc.h>
54#include <linux/ioport.h>
55#include <linux/interrupt.h>
56#include <linux/pci.h>
57#include <linux/timex.h>
58#include <linux/bootmem.h>
59#include <linux/mv643xx.h>
60#include <linux/pm.h>
61#include <linux/bcd.h>
62
63#include <asm/time.h>
64#include <asm/page.h>
65#include <asm/bootinfo.h>
66#include <asm/io.h>
67#include <asm/irq.h>
68#include <asm/pci.h>
69#include <asm/processor.h>
70#include <asm/reboot.h>
71#include <asm/mc146818rtc.h>
72#include <asm/tlbflush.h>
73#include "ocelot_3_fpga.h"
74
75/* Marvell Discovery Register Base */
76unsigned long marvell_base = (signed)0xf4000000;
77
78/* CPU clock */
79unsigned long cpu_clock;
80
81/* RTC/NVRAM */
82unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000;
83
84/* FPGA Base */
85unsigned long ocelot_fpga_base = (signed)0xfc000000;
86
87/* Serial base */
88unsigned long uart_base = (signed)0xfd000000;
89
90/*
91 * Marvell Discovery SRAM. This is one place where Ethernet
92 * Tx and Rx descriptors can be placed to improve performance
93 */
94extern unsigned long mv64340_sram_base;
95
96/* These functions are used for rebooting or halting the machine*/
97extern void momenco_ocelot_restart(char *command);
98extern void momenco_ocelot_halt(void);
99extern void momenco_ocelot_power_off(void);
100
101void momenco_time_init(void);
102static char reset_reason;
103
104void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
105 unsigned long entryhi, unsigned long pagemask);
106
107static inline unsigned long ENTRYLO(unsigned long paddr)
108{
109 return ((paddr & PAGE_MASK) |
110 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
111 _CACHE_UNCACHED)) >> 6;
112}
113
114void __init bus_error_init(void)
115{
116 /* nothing */
117}
118
119/*
120 * setup code for a handoff from a version 2 PMON 2000 PROM
121 */
122void setup_wired_tlb_entries(void)
123{
124 write_c0_wired(0);
125 local_flush_tlb_all();
126
127 /* marvell and extra space */
128 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K);
129
130 /* fpga, rtc, and uart */
131 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
132}
133
134unsigned long m48t37y_get_time(void)
135{
136 unsigned int year, month, day, hour, min, sec;
137 unsigned long flags;
138
139 spin_lock_irqsave(&rtc_lock, flags);
140 /* stop the update */
141 rtc_base[0x7ff8] = 0x40;
142
143 year = BCD2BIN(rtc_base[0x7fff]);
144 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
145
146 month = BCD2BIN(rtc_base[0x7ffe]);
147
148 day = BCD2BIN(rtc_base[0x7ffd]);
149
150 hour = BCD2BIN(rtc_base[0x7ffb]);
151 min = BCD2BIN(rtc_base[0x7ffa]);
152 sec = BCD2BIN(rtc_base[0x7ff9]);
153
154 /* start the update */
155 rtc_base[0x7ff8] = 0x00;
156 spin_unlock_irqrestore(&rtc_lock, flags);
157
158 return mktime(year, month, day, hour, min, sec);
159}
160
161int m48t37y_set_time(unsigned long sec)
162{
163 struct rtc_time tm;
164 unsigned long flags;
165
166 /* convert to a more useful format -- note months count from 0 */
167 to_tm(sec, &tm);
168 tm.tm_mon += 1;
169
170 spin_lock_irqsave(&rtc_lock, flags);
171 /* enable writing */
172 rtc_base[0x7ff8] = 0x80;
173
174 /* year */
175 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
176 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
177
178 /* month */
179 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
180
181 /* day */
182 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
183
184 /* hour/min/sec */
185 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
186 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
187 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
188
189 /* day of week -- not really used, but let's keep it up-to-date */
190 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
191
192 /* disable writing */
193 rtc_base[0x7ff8] = 0x00;
194 spin_unlock_irqrestore(&rtc_lock, flags);
195
196 return 0;
197}
198
199void __init plat_timer_setup(struct irqaction *irq)
200{
201 setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */
202}
203
204void momenco_time_init(void)
205{
206 setup_wired_tlb_entries();
207
208 /*
209 * Ocelot-3 board has been built with both
210 * the Rm7900 and the Rm7065C
211 */
212 mips_hpt_frequency = cpu_clock / 2;
213
214 rtc_mips_get_time = m48t37y_get_time;
215 rtc_mips_set_time = m48t37y_set_time;
216}
217
218/*
219 * PCI Support for Ocelot-3
220 */
221
222/* Bus #0 IO and MEM space */
223#define OCELOT_3_PCI_IO_0_START 0xe0000000
224#define OCELOT_3_PCI_IO_0_SIZE 0x08000000
225#define OCELOT_3_PCI_MEM_0_START 0xc0000000
226#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000
227
228/* Bus #1 IO and MEM space */
229#define OCELOT_3_PCI_IO_1_START 0xe8000000
230#define OCELOT_3_PCI_IO_1_SIZE 0x08000000
231#define OCELOT_3_PCI_MEM_1_START 0xd0000000
232#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000
233
234static struct resource mv_pci_io_mem0_resource = {
235 .name = "MV64340 PCI0 IO MEM",
236 .start = OCELOT_3_PCI_IO_0_START,
237 .end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1,
238 .flags = IORESOURCE_IO,
239};
240
241static struct resource mv_pci_io_mem1_resource = {
242 .name = "MV64340 PCI1 IO MEM",
243 .start = OCELOT_3_PCI_IO_1_START,
244 .end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1,
245 .flags = IORESOURCE_IO,
246};
247
248static struct resource mv_pci_mem0_resource = {
249 .name = "MV64340 PCI0 MEM",
250 .start = OCELOT_3_PCI_MEM_0_START,
251 .end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1,
252 .flags = IORESOURCE_MEM,
253};
254
255static struct resource mv_pci_mem1_resource = {
256 .name = "MV64340 PCI1 MEM",
257 .start = OCELOT_3_PCI_MEM_1_START,
258 .end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1,
259 .flags = IORESOURCE_MEM,
260};
261
262static struct mv_pci_controller mv_bus0_controller = {
263 .pcic = {
264 .pci_ops = &mv_pci_ops,
265 .mem_resource = &mv_pci_mem0_resource,
266 .io_resource = &mv_pci_io_mem0_resource,
267 },
268 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
269 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
270};
271
272static struct mv_pci_controller mv_bus1_controller = {
273 .pcic = {
274 .pci_ops = &mv_pci_ops,
275 .mem_resource = &mv_pci_mem1_resource,
276 .io_resource = &mv_pci_io_mem1_resource,
277 },
278 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
279 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
280};
281
282static __init int __init ja_pci_init(void)
283{
284 uint32_t enable;
285 extern int pci_probe_only;
286
287 /* PMON will assign PCI resources */
288 pci_probe_only = 1;
289
290 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
291 /*
292 * We require at least one enabled I/O or PCI memory window or we
293 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
294 */
295 if (enable & (0x01 << 9) || enable & (0x01 << 10))
296 register_pci_controller(&mv_bus0_controller.pcic);
297
298 if (enable & (0x01 << 14) || enable & (0x01 << 15))
299 register_pci_controller(&mv_bus1_controller.pcic);
300
301 ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE +
302 OCELOT_3_PCI_IO_1_SIZE - 1;
303
304 iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE +
305 OCELOT_3_PCI_MEM_1_SIZE - 1;
306
307 set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */
308
309 return 0;
310}
311
312arch_initcall(ja_pci_init);
313
314void __init plat_mem_setup(void)
315{
316 unsigned int tmpword;
317
318 board_time_init = momenco_time_init;
319
320 _machine_restart = momenco_ocelot_restart;
321 _machine_halt = momenco_ocelot_halt;
322 pm_power_off = momenco_ocelot_power_off;
323
324 /* Wired TLB entries */
325 setup_wired_tlb_entries();
326
327 /* shut down ethernet ports, just to be sure our memory doesn't get
328 * corrupted by random ethernet traffic.
329 */
330 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
331 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
332 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
333 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
334 do {}
335 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
336 do {}
337 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
338 do {}
339 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
340 do {}
341 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
342 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
343 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
344 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
345 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
346
347 /* Turn off the Bit-Error LED */
348 OCELOT_FPGA_WRITE(0x80, CLR);
349
350 tmpword = OCELOT_FPGA_READ(BOARDREV);
351 if (tmpword < 26)
352 printk("Momenco Ocelot-3: Board Assembly Rev. %c\n",
353 'A'+tmpword);
354 else
355 printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n",
356 tmpword);
357
358 tmpword = OCELOT_FPGA_READ(FPGA_REV);
359 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
360 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
361 printk("Reset reason: 0x%x\n", tmpword);
362 switch (tmpword) {
363 case 0x1:
364 printk(" - Power-up reset\n");
365 break;
366 case 0x2:
367 printk(" - Push-button reset\n");
368 break;
369 case 0x4:
370 printk(" - cPCI bus reset\n");
371 break;
372 case 0x8:
373 printk(" - Watchdog reset\n");
374 break;
375 case 0x10:
376 printk(" - Software reset\n");
377 break;
378 default:
379 printk(" - Unknown reset cause\n");
380 }
381 reset_reason = tmpword;
382 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
383
384 tmpword = OCELOT_FPGA_READ(CPCI_ID);
385 printk("cPCI ID register: 0x%02x\n", tmpword);
386 printk(" - Slot number: %d\n", tmpword & 0x1f);
387 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
388 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
389
390 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
391 printk("Board Status register: 0x%02x\n", tmpword);
392 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
393 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
394 printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1);
395
396 /* Support for 128 MB memory */
397 add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
398}
diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile
deleted file mode 100644
index d69161aa1675..000000000000
--- a/arch/mips/momentum/ocelot_c/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for Momentum Computer's Ocelot-C and -CS boards.
3#
4
5obj-y += cpci-irq.o irq.o platform.o prom.o reset.o \
6 setup.o uart-irq.o
7
8obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
deleted file mode 100644
index 186a140fd2a9..000000000000
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/cpci-irq.c
6 * Interrupt routines for cpci. Interrupt numbers are assigned from
7 * CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources).
8 *
9 * Note that the high-level software will need to be careful about using
10 * these interrupts. If this board is asserting a cPCI interrupt, it will
11 * also see the asserted interrupt. Care must be taken to avoid an
12 * interrupt flood.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/kernel.h>
24#include <linux/sched.h>
25#include <linux/kernel_stat.h>
26#include <asm/io.h>
27#include "ocelot_c_fpga.h"
28
29#define CPCI_IRQ_BASE 8
30
31static inline int ls1bit8(unsigned int x)
32{
33 int b = 7, s;
34
35 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
36 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
37 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
38
39 return b;
40}
41
42/* mask off an interrupt -- 0 is enable, 1 is disable */
43static inline void mask_cpci_irq(unsigned int irq)
44{
45 uint32_t value;
46
47 value = OCELOT_FPGA_READ(INTMASK);
48 value |= 1 << (irq - CPCI_IRQ_BASE);
49 OCELOT_FPGA_WRITE(value, INTMASK);
50
51 /* read the value back to assure that it's really been written */
52 value = OCELOT_FPGA_READ(INTMASK);
53}
54
55/* unmask an interrupt -- 0 is enable, 1 is disable */
56static inline void unmask_cpci_irq(unsigned int irq)
57{
58 uint32_t value;
59
60 value = OCELOT_FPGA_READ(INTMASK);
61 value &= ~(1 << (irq - CPCI_IRQ_BASE));
62 OCELOT_FPGA_WRITE(value, INTMASK);
63
64 /* read the value back to assure that it's really been written */
65 value = OCELOT_FPGA_READ(INTMASK);
66}
67
68/*
69 * Interrupt handler for interrupts coming from the FPGA chip.
70 * It could be built in ethernet ports etc...
71 */
72void ll_cpci_irq(void)
73{
74 unsigned int irq_src, irq_mask;
75
76 /* read the interrupt status registers */
77 irq_src = OCELOT_FPGA_READ(INTSTAT);
78 irq_mask = OCELOT_FPGA_READ(INTMASK);
79
80 /* mask for just the interrupts we want */
81 irq_src &= ~irq_mask;
82
83 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
84}
85
86struct irq_chip cpci_irq_type = {
87 .name = "CPCI/FPGA",
88 .ack = mask_cpci_irq,
89 .mask = mask_cpci_irq,
90 .mask_ack = mask_cpci_irq,
91 .unmask = unmask_cpci_irq,
92};
93
94void cpci_irq_init(void)
95{
96 int i;
97
98 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
99 set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
100}
diff --git a/arch/mips/momentum/ocelot_c/dbg_io.c b/arch/mips/momentum/ocelot_c/dbg_io.c
deleted file mode 100644
index 32d6fb4ee679..000000000000
--- a/arch/mips/momentum/ocelot_c/dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
1
2#include <asm/serial.h> /* For the serial port location and base baud */
3
4/* --- CONFIG --- */
5
6typedef unsigned char uint8;
7typedef unsigned int uint32;
8
9/* --- END OF CONFIG --- */
10
11#define UART16550_BAUD_2400 2400
12#define UART16550_BAUD_4800 4800
13#define UART16550_BAUD_9600 9600
14#define UART16550_BAUD_19200 19200
15#define UART16550_BAUD_38400 38400
16#define UART16550_BAUD_57600 57600
17#define UART16550_BAUD_115200 115200
18
19#define UART16550_PARITY_NONE 0
20#define UART16550_PARITY_ODD 0x08
21#define UART16550_PARITY_EVEN 0x18
22#define UART16550_PARITY_MARK 0x28
23#define UART16550_PARITY_SPACE 0x38
24
25#define UART16550_DATA_5BIT 0x0
26#define UART16550_DATA_6BIT 0x1
27#define UART16550_DATA_7BIT 0x2
28#define UART16550_DATA_8BIT 0x3
29
30#define UART16550_STOP_1BIT 0x0
31#define UART16550_STOP_2BIT 0x4
32
33/* ----------------------------------------------------- */
34
35/* === CONFIG === */
36
37/* [jsun] we use the second serial port for kdb */
38#define BASE OCELOT_SERIAL1_BASE
39#define MAX_BAUD OCELOT_BASE_BAUD
40
41/* === END OF CONFIG === */
42
43#define REG_OFFSET 4
44
45/* register offset */
46#define OFS_RCV_BUFFER 0
47#define OFS_TRANS_HOLD 0
48#define OFS_SEND_BUFFER 0
49#define OFS_INTR_ENABLE (1*REG_OFFSET)
50#define OFS_INTR_ID (2*REG_OFFSET)
51#define OFS_DATA_FORMAT (3*REG_OFFSET)
52#define OFS_LINE_CONTROL (3*REG_OFFSET)
53#define OFS_MODEM_CONTROL (4*REG_OFFSET)
54#define OFS_RS232_OUTPUT (4*REG_OFFSET)
55#define OFS_LINE_STATUS (5*REG_OFFSET)
56#define OFS_MODEM_STATUS (6*REG_OFFSET)
57#define OFS_RS232_INPUT (6*REG_OFFSET)
58#define OFS_SCRATCH_PAD (7*REG_OFFSET)
59
60#define OFS_DIVISOR_LSB (0*REG_OFFSET)
61#define OFS_DIVISOR_MSB (1*REG_OFFSET)
62
63
64/* memory-mapped read/write of the port */
65#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
66#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
67
68void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
69{
70 /* disable interrupts */
71 UART16550_WRITE(OFS_INTR_ENABLE, 0);
72
73 /* set up baud rate */
74 {
75 uint32 divisor;
76
77 /* set DIAB bit */
78 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
79
80 /* set divisor */
81 divisor = MAX_BAUD / baud;
82 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
83 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
84
85 /* clear DIAB bit */
86 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
87 }
88
89 /* set data format */
90 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
91}
92
93static int remoteDebugInitialized = 0;
94
95uint8 getDebugChar(void)
96{
97 if (!remoteDebugInitialized) {
98 remoteDebugInitialized = 1;
99 debugInit(UART16550_BAUD_38400,
100 UART16550_DATA_8BIT,
101 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
102 }
103
104 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
105 return UART16550_READ(OFS_RCV_BUFFER);
106}
107
108
109int putDebugChar(uint8 byte)
110{
111 if (!remoteDebugInitialized) {
112 remoteDebugInitialized = 1;
113 debugInit(UART16550_BAUD_38400,
114 UART16550_DATA_8BIT,
115 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
116 }
117
118 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
119 UART16550_WRITE(OFS_SEND_BUFFER, byte);
120 return 1;
121}
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
deleted file mode 100644
index 844d566c9de3..000000000000
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <linux/mv643xx.h>
45#include <asm/bootinfo.h>
46#include <asm/io.h>
47#include <asm/irq_cpu.h>
48#include <asm/mipsregs.h>
49#include <asm/system.h>
50
51extern void uart_irq_init(void);
52extern void cpci_irq_init(void);
53
54static struct irqaction cascade_fpga = {
55 no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
56};
57
58static struct irqaction cascade_mv64340 = {
59 no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
60};
61
62extern void ll_uart_irq(void);
63extern void ll_cpci_irq(void);
64
65asmlinkage void plat_irq_dispatch(void)
66{
67 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
68
69 if (pending & STATUSF_IP0)
70 do_IRQ(0);
71 else if (pending & STATUSF_IP1)
72 do_IRQ(1);
73 else if (pending & STATUSF_IP2)
74 do_IRQ(2);
75 else if (pending & STATUSF_IP3)
76 ll_uart_irq();
77 else if (pending & STATUSF_IP4)
78 do_IRQ(4);
79 else if (pending & STATUSF_IP5)
80 ll_cpci_irq();
81 else if (pending & STATUSF_IP6)
82 ll_mv64340_irq();
83 else if (pending & STATUSF_IP7)
84 do_IRQ(7);
85 else
86 spurious_interrupt();
87}
88
89void __init arch_init_irq(void)
90{
91 /*
92 * Clear all of the interrupts while we change the able around a bit.
93 * int-handler is not on bootstrap
94 */
95 clear_c0_status(ST0_IM);
96
97 mips_cpu_irq_init();
98
99 /* set up the cascading interrupts */
100 setup_irq(3, &cascade_fpga);
101 setup_irq(5, &cascade_fpga);
102 setup_irq(6, &cascade_mv64340);
103
104 mv64340_irq_init(16);
105 uart_irq_init();
106 cpci_irq_init();
107}
diff --git a/arch/mips/momentum/ocelot_c/platform.c b/arch/mips/momentum/ocelot_c/platform.c
deleted file mode 100644
index 7780aa0c6555..000000000000
--- a/arch/mips/momentum/ocelot_c/platform.c
+++ /dev/null
@@ -1,183 +0,0 @@
1#include <linux/delay.h>
2#include <linux/if_ether.h>
3#include <linux/ioport.h>
4#include <linux/mv643xx.h>
5#include <linux/platform_device.h>
6
7#include "ocelot_c_fpga.h"
8
9#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
11static struct resource mv643xx_eth_shared_resources[] = {
12 [0] = {
13 .name = "ethernet shared base",
14 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16 MV643XX_ETH_SHARED_REGS_SIZE - 1,
17 .flags = IORESOURCE_MEM,
18 },
19};
20
21static struct platform_device mv643xx_eth_shared_device = {
22 .name = MV643XX_ETH_SHARED_NAME,
23 .id = 0,
24 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25 .resource = mv643xx_eth_shared_resources,
26};
27
28#define MV_SRAM_BASE 0xfe000000UL
29#define MV_SRAM_SIZE (256 * 1024)
30
31#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
34#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
37#define MV64x60_IRQ_ETH_0 48
38#define MV64x60_IRQ_ETH_1 49
39
40static struct resource mv64x60_eth0_resources[] = {
41 [0] = {
42 .name = "eth0 irq",
43 .start = MV64x60_IRQ_ETH_0,
44 .end = MV64x60_IRQ_ETH_0,
45 .flags = IORESOURCE_IRQ,
46 },
47};
48
49static struct mv643xx_eth_platform_data eth0_pd = {
50 .port_number = 0,
51
52 .tx_sram_addr = MV_SRAM_BASE_ETH0,
53 .tx_sram_size = MV_SRAM_TXRING_SIZE,
54 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
55
56 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
57 .rx_sram_size = MV_SRAM_RXRING_SIZE,
58 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
59};
60
61static struct platform_device eth0_device = {
62 .name = MV643XX_ETH_NAME,
63 .id = 0,
64 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
65 .resource = mv64x60_eth0_resources,
66 .dev = {
67 .platform_data = &eth0_pd,
68 },
69};
70
71static struct resource mv64x60_eth1_resources[] = {
72 [0] = {
73 .name = "eth1 irq",
74 .start = MV64x60_IRQ_ETH_1,
75 .end = MV64x60_IRQ_ETH_1,
76 .flags = IORESOURCE_IRQ,
77 },
78};
79
80static struct mv643xx_eth_platform_data eth1_pd = {
81 .port_number = 1,
82
83 .tx_sram_addr = MV_SRAM_BASE_ETH1,
84 .tx_sram_size = MV_SRAM_TXRING_SIZE,
85 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
86
87 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
88 .rx_sram_size = MV_SRAM_RXRING_SIZE,
89 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
90};
91
92static struct platform_device eth1_device = {
93 .name = MV643XX_ETH_NAME,
94 .id = 1,
95 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
96 .resource = mv64x60_eth1_resources,
97 .dev = {
98 .platform_data = &eth1_pd,
99 },
100};
101
102static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
103 &mv643xx_eth_shared_device,
104 &eth0_device,
105 &eth1_device,
106 /* The third port is not wired up on the Ocelot C */
107};
108
109static u8 __init exchange_bit(u8 val, u8 cs)
110{
111 /* place the data */
112 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
113 udelay(1);
114
115 /* turn the clock on */
116 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
117 udelay(1);
118
119 /* turn the clock off and read-strobe */
120 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
121
122 /* return the data */
123 return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
124}
125
126static void __init get_mac(char dest[6])
127{
128 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
129 int i,j;
130
131 for (i = 0; i < 12; i++)
132 exchange_bit(read_opcode[i], 1);
133
134 for (j = 0; j < 6; j++) {
135 dest[j] = 0;
136 for (i = 0; i < 8; i++) {
137 dest[j] <<= 1;
138 dest[j] |= exchange_bit(0, 1);
139 }
140 }
141
142 /* turn off CS */
143 exchange_bit(0,0);
144}
145
146/*
147 * Copy and increment ethernet MAC address by a small value.
148 *
149 * This is useful for systems where the only one MAC address is stored in
150 * non-volatile memory for multiple ports.
151 */
152static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
153 unsigned int add)
154{
155 int i;
156
157 BUG_ON(add >= 256);
158
159 for (i = ETH_ALEN; i >= 0; i--) {
160 dst[i] = src[i] + add;
161 add = dst[i] < src[i]; /* compute carry */
162 }
163
164 WARN_ON(add);
165}
166
167static int __init mv643xx_eth_add_pds(void)
168{
169 unsigned char mac[ETH_ALEN];
170 int ret;
171
172 get_mac(mac);
173 eth_mac_add(eth0_pd.mac_addr, mac, 0);
174 eth_mac_add(eth1_pd.mac_addr, mac, 1);
175 ret = platform_add_devices(mv643xx_eth_pd_devs,
176 ARRAY_SIZE(mv643xx_eth_pd_devs));
177
178 return ret;
179}
180
181device_initcall(mv643xx_eth_add_pds);
182
183#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c
deleted file mode 100644
index b689ceea8cfb..000000000000
--- a/arch/mips/momentum/ocelot_c/prom.c
+++ /dev/null
@@ -1,183 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Louis Hamilton, Red Hat, Inc.
6 * hamilton@redhat.com [MIPS64 modifications]
7 *
8 * Based on Ocelot Linux port, which is
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/init.h>
18#include <linux/mm.h>
19#include <linux/sched.h>
20#include <linux/bootmem.h>
21#include <linux/mv643xx.h>
22
23#include <asm/addrspace.h>
24#include <asm/bootinfo.h>
25#include <asm/pmon.h>
26
27#include "ocelot_c_fpga.h"
28
29struct callvectors* debug_vectors;
30
31extern unsigned long marvell_base;
32extern unsigned int cpu_clock;
33
34const char *get_system_type(void)
35{
36#ifdef CONFIG_CPU_SR71000
37 return "Momentum Ocelot-CS";
38#else
39 return "Momentum Ocelot-C";
40#endif
41}
42
43#ifdef CONFIG_64BIT
44
45unsigned long signext(unsigned long addr)
46{
47 addr &= 0xffffffff;
48 return (unsigned long)((int)addr);
49}
50
51void *get_arg(unsigned long args, int arc)
52{
53 unsigned long ul;
54 unsigned char *puc, uc;
55
56 args += (arc * 4);
57 ul = (unsigned long)signext(args);
58 puc = (unsigned char *)ul;
59 if (puc == 0)
60 return (void *)0;
61
62#ifdef CONFIG_CPU_LITTLE_ENDIAN
63 uc = *puc++;
64 ul = (unsigned long)uc;
65 uc = *puc++;
66 ul |= (((unsigned long)uc) << 8);
67 uc = *puc++;
68 ul |= (((unsigned long)uc) << 16);
69 uc = *puc++;
70 ul |= (((unsigned long)uc) << 24);
71#else /* CONFIG_CPU_LITTLE_ENDIAN */
72 uc = *puc++;
73 ul = ((unsigned long)uc) << 24;
74 uc = *puc++;
75 ul |= (((unsigned long)uc) << 16);
76 uc = *puc++;
77 ul |= (((unsigned long)uc) << 8);
78 uc = *puc++;
79 ul |= ((unsigned long)uc);
80#endif /* CONFIG_CPU_LITTLE_ENDIAN */
81 ul = signext(ul);
82 return (void *)ul;
83}
84
85char *arg64(unsigned long addrin, int arg_index)
86{
87 unsigned long args;
88 char *p;
89 args = signext(addrin);
90 p = (char *)get_arg(args, arg_index);
91 return p;
92}
93#endif /* CONFIG_64BIT */
94
95
96void __init prom_init(void)
97{
98 int argc = fw_arg0;
99 char **arg = (char **) fw_arg1;
100 char **env = (char **) fw_arg2;
101 struct callvectors *cv = (struct callvectors *) fw_arg3;
102 int i;
103
104#ifdef CONFIG_64BIT
105 char *ptr;
106
107 printk("prom_init - MIPS64\n");
108 /* save the PROM vectors for debugging use */
109 debug_vectors = (struct callvectors *)signext((unsigned long)cv);
110
111 /* arg[0] is "g", the rest is boot parameters */
112 arcs_cmdline[0] = '\0';
113
114 for (i = 1; i < argc; i++) {
115 ptr = (char *)arg64((unsigned long)arg, i);
116 if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
117 sizeof(arcs_cmdline))
118 break;
119 strcat(arcs_cmdline, ptr);
120 strcat(arcs_cmdline, " ");
121 }
122 i = 0;
123 while (1) {
124 ptr = (char *)arg64((unsigned long)env, i);
125 if (! ptr)
126 break;
127
128 if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
129 marvell_base = simple_strtol(ptr + strlen("gtbase="),
130 NULL, 16);
131
132 if ((marvell_base & 0xffffffff00000000) == 0)
133 marvell_base |= 0xffffffff00000000;
134
135 printk("marvell_base set to 0x%016lx\n", marvell_base);
136 }
137 if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
138 cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
139 NULL, 10);
140 printk("cpu_clock set to %d\n", cpu_clock);
141 }
142 i++;
143 }
144 printk("arcs_cmdline: %s\n", arcs_cmdline);
145
146#else /* CONFIG_64BIT */
147 /* save the PROM vectors for debugging use */
148 debug_vectors = cv;
149
150 /* arg[0] is "g", the rest is boot parameters */
151 arcs_cmdline[0] = '\0';
152 for (i = 1; i < argc; i++) {
153 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
154 >= sizeof(arcs_cmdline))
155 break;
156 strcat(arcs_cmdline, arg[i]);
157 strcat(arcs_cmdline, " ");
158 }
159
160 while (*env) {
161 if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
162 marvell_base = simple_strtol(*env + strlen("gtbase="),
163 NULL, 16);
164 }
165 if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
166 cpu_clock = simple_strtol(*env + strlen("cpuclock="),
167 NULL, 10);
168 }
169 env++;
170 }
171#endif /* CONFIG_64BIT */
172
173 mips_machgroup = MACH_GROUP_MOMENCO;
174 mips_machtype = MACH_MOMENCO_OCELOT_C;
175
176#ifndef CONFIG_64BIT
177 debug_vectors->printf("Booting Linux kernel...\n");
178#endif
179}
180
181void __init prom_free_prom_memory(void)
182{
183}
diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c
deleted file mode 100644
index 3fdcb64ff1e6..000000000000
--- a/arch/mips/momentum/ocelot_c/reset.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 * Copyright (C) 2002 Momentum Computer Inc.
12 * Author: Matthew Dharm <mdharm@momenco.com>
13 *
14 * Louis Hamilton, Red Hat, Inc.
15 * hamilton@redhat.com [MIPS64 modifications]
16 */
17#include <linux/sched.h>
18#include <linux/mm.h>
19#include <asm/io.h>
20#include <asm/pgtable.h>
21#include <asm/processor.h>
22#include <asm/reboot.h>
23#include <asm/system.h>
24#include <linux/delay.h>
25
26void momenco_ocelot_restart(char *command)
27{
28 /* base address of timekeeper portion of part */
29 void *nvram = (void *)
30#ifdef CONFIG_64BIT
31 0xfffffffffc807000;
32#else
33 0xfc807000;
34#endif
35
36 /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
37 writeb(0x84, nvram + 0xff7);
38
39 /* wait for the watchdog to go off */
40 mdelay(100+(1000/16));
41
42 /* if the watchdog fails for some reason, let people know */
43 printk(KERN_NOTICE "Watchdog reset failed\n");
44}
45
46void momenco_ocelot_halt(void)
47{
48 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
49 while (1)
50 __asm__(".set\tmips3\n\t"
51 "wait\n\t"
52 ".set\tmips0");
53}
54
55void momenco_ocelot_power_off(void)
56{
57 momenco_ocelot_halt();
58}
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
deleted file mode 100644
index 0b6b2338cfb4..000000000000
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ /dev/null
@@ -1,362 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-C and -CS board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 *
42 */
43#include <linux/bcd.h>
44#include <linux/init.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/mm.h>
48#include <linux/swap.h>
49#include <linux/ioport.h>
50#include <linux/sched.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/pm.h>
54#include <linux/timex.h>
55#include <linux/vmalloc.h>
56#include <linux/mv643xx.h>
57
58#include <asm/time.h>
59#include <asm/bootinfo.h>
60#include <asm/page.h>
61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/pci.h>
64#include <asm/processor.h>
65#include <asm/reboot.h>
66#include <asm/marvell.h>
67#include <linux/bootmem.h>
68#include <linux/blkdev.h>
69#include "ocelot_c_fpga.h"
70
71unsigned long marvell_base;
72unsigned int cpu_clock;
73
74/* These functions are used for rebooting or halting the machine*/
75extern void momenco_ocelot_restart(char *command);
76extern void momenco_ocelot_halt(void);
77extern void momenco_ocelot_power_off(void);
78
79void momenco_time_init(void);
80
81static char reset_reason;
82
83void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
84
85static unsigned long ENTRYLO(unsigned long paddr)
86{
87 return ((paddr & PAGE_MASK) |
88 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
89 _CACHE_UNCACHED)) >> 6;
90}
91
92/* setup code for a handoff from a version 2 PMON 2000 PROM */
93void PMON_v2_setup(void)
94{
95 /* Some wired TLB entries for the MV64340 and perhiperals. The
96 MV64340 is going to be hit on every IRQ anyway - there's
97 absolutely no point in letting it be a random TLB entry, as
98 it'll just cause needless churning of the TLB. And we use
99 the other half for the serial port, which is just a PITA
100 otherwise :)
101
102 Device Physical Virtual
103 MV64340 Internal Regs 0xf4000000 0xf4000000
104 Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
105 NVRAM (CS1) 0xfc800000 0xfc800000
106 UARTs (CS2) 0xfd000000 0xfd000000
107 Internal SRAM 0xfe000000 0xfe000000
108 M-Systems DOC (CS3) 0xff000000 0xff000000
109 */
110 printk("PMON_v2_setup\n");
111
112#ifdef CONFIG_64BIT
113 /* marvell and extra space */
114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
115 /* fpga, rtc, and uart */
116 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
117 /* m-sys and internal SRAM */
118 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
119
120 marvell_base = 0xfffffffff4000000;
121#else
122 /* marvell and extra space */
123 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
124 /* fpga, rtc, and uart */
125 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
126 /* m-sys and internal SRAM */
127 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
128
129 marvell_base = 0xf4000000;
130#endif
131}
132
133unsigned long m48t37y_get_time(void)
134{
135#ifdef CONFIG_64BIT
136 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
137#else
138 unsigned char* rtc_base = (unsigned char*)0xfc800000;
139#endif
140 unsigned int year, month, day, hour, min, sec;
141 unsigned long flags;
142
143 spin_lock_irqsave(&rtc_lock, flags);
144 /* stop the update */
145 rtc_base[0x7ff8] = 0x40;
146
147 year = BCD2BIN(rtc_base[0x7fff]);
148 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
149
150 month = BCD2BIN(rtc_base[0x7ffe]);
151
152 day = BCD2BIN(rtc_base[0x7ffd]);
153
154 hour = BCD2BIN(rtc_base[0x7ffb]);
155 min = BCD2BIN(rtc_base[0x7ffa]);
156 sec = BCD2BIN(rtc_base[0x7ff9]);
157
158 /* start the update */
159 rtc_base[0x7ff8] = 0x00;
160 spin_unlock_irqrestore(&rtc_lock, flags);
161
162 return mktime(year, month, day, hour, min, sec);
163}
164
165int m48t37y_set_time(unsigned long sec)
166{
167#ifdef CONFIG_64BIT
168 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
169#else
170 unsigned char* rtc_base = (unsigned char*)0xfc800000;
171#endif
172 struct rtc_time tm;
173 unsigned long flags;
174
175 /* convert to a more useful format -- note months count from 0 */
176 to_tm(sec, &tm);
177 tm.tm_mon += 1;
178
179 spin_lock_irqsave(&rtc_lock, flags);
180 /* enable writing */
181 rtc_base[0x7ff8] = 0x80;
182
183 /* year */
184 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
185 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
186
187 /* month */
188 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
189
190 /* day */
191 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
192
193 /* hour/min/sec */
194 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
195 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
196 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
197
198 /* day of week -- not really used, but let's keep it up-to-date */
199 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
200
201 /* disable writing */
202 rtc_base[0x7ff8] = 0x00;
203 spin_unlock_irqrestore(&rtc_lock, flags);
204
205 return 0;
206}
207
208void __init plat_timer_setup(struct irqaction *irq)
209{
210 setup_irq(7, irq);
211}
212
213void momenco_time_init(void)
214{
215#ifdef CONFIG_CPU_SR71000
216 mips_hpt_frequency = cpu_clock;
217#elif defined(CONFIG_CPU_RM7000)
218 mips_hpt_frequency = cpu_clock / 2;
219#else
220#error Unknown CPU for this board
221#endif
222 printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
223
224 rtc_mips_get_time = m48t37y_get_time;
225 rtc_mips_set_time = m48t37y_set_time;
226}
227
228void __init plat_mem_setup(void)
229{
230 unsigned int tmpword;
231
232 board_time_init = momenco_time_init;
233
234 _machine_restart = momenco_ocelot_restart;
235 _machine_halt = momenco_ocelot_halt;
236 pm_power_off = momenco_ocelot_power_off;
237
238 /*
239 * initrd_start = (unsigned long)ocelot_initrd_start;
240 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
241 * initrd_below_start_ok = 1;
242 */
243
244 /* do handoff reconfiguration */
245 PMON_v2_setup();
246
247 /* shut down ethernet ports, just to be sure our memory doesn't get
248 * corrupted by random ethernet traffic.
249 */
250 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
251 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
252 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
253 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
254 do {}
255 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
256 do {}
257 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
258 do {}
259 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
260 do {}
261 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
262 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
263 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
264 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
265 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
266
267 /* Turn off the Bit-Error LED */
268 OCELOT_FPGA_WRITE(0x80, CLR);
269
270 tmpword = OCELOT_FPGA_READ(BOARDREV);
271#ifdef CONFIG_CPU_SR71000
272 if (tmpword < 26)
273 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
274 'A'+tmpword);
275 else
276 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
277 tmpword);
278#else
279 if (tmpword < 26)
280 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
281 'A'+tmpword);
282 else
283 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
284 tmpword);
285#endif
286
287 tmpword = OCELOT_FPGA_READ(FPGA_REV);
288 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
289 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
290 printk("Reset reason: 0x%x\n", tmpword);
291 switch (tmpword) {
292 case 0x1:
293 printk(" - Power-up reset\n");
294 break;
295 case 0x2:
296 printk(" - Push-button reset\n");
297 break;
298 case 0x4:
299 printk(" - cPCI bus reset\n");
300 break;
301 case 0x8:
302 printk(" - Watchdog reset\n");
303 break;
304 case 0x10:
305 printk(" - Software reset\n");
306 break;
307 default:
308 printk(" - Unknown reset cause\n");
309 }
310 reset_reason = tmpword;
311 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
312
313 tmpword = OCELOT_FPGA_READ(CPCI_ID);
314 printk("cPCI ID register: 0x%02x\n", tmpword);
315 printk(" - Slot number: %d\n", tmpword & 0x1f);
316 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
317 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
318
319 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
320 printk("Board Status register: 0x%02x\n", tmpword);
321 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
322 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
323 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
324 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
325
326 switch(tmpword &3) {
327 case 3:
328 /* 512MiB */
329 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
330 break;
331 case 2:
332 /* 256MiB */
333 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
334 break;
335 case 1:
336 /* 128MiB */
337 add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
338 break;
339 case 0:
340 /* 1GiB -- needs CONFIG_HIGHMEM */
341 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
342 break;
343 }
344}
345
346/*
347 * This needs to be one of the first initcalls, because no I/O port access
348 * can work before this
349 */
350static int io_base_ioremap(void)
351{
352 void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
353
354 if (!io_remap_range)
355 panic("Could not ioremap I/O port range");
356
357 set_io_port_base((unsigned long) io_remap_range);
358
359 return 0;
360}
361
362module_init(io_base_ioremap);
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
deleted file mode 100644
index de1a31ee52f3..000000000000
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/uart-irq.c
6 * Interrupt routines for UARTs. Interrupt numbers are assigned from
7 * 80 to 81 (2 interrupt sources).
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/kernel_stat.h>
21#include <asm/io.h>
22#include <asm/irq.h>
23#include "ocelot_c_fpga.h"
24
25static inline int ls1bit8(unsigned int x)
26{
27 int b = 7, s;
28
29 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
30 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
31 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
32
33 return b;
34}
35
36/* mask off an interrupt -- 0 is enable, 1 is disable */
37static inline void mask_uart_irq(unsigned int irq)
38{
39 uint8_t value;
40
41 value = OCELOT_FPGA_READ(UART_INTMASK);
42 value |= 1 << (irq - 74);
43 OCELOT_FPGA_WRITE(value, UART_INTMASK);
44
45 /* read the value back to assure that it's really been written */
46 value = OCELOT_FPGA_READ(UART_INTMASK);
47}
48
49/* unmask an interrupt -- 0 is enable, 1 is disable */
50static inline void unmask_uart_irq(unsigned int irq)
51{
52 uint8_t value;
53
54 value = OCELOT_FPGA_READ(UART_INTMASK);
55 value &= ~(1 << (irq - 74));
56 OCELOT_FPGA_WRITE(value, UART_INTMASK);
57
58 /* read the value back to assure that it's really been written */
59 value = OCELOT_FPGA_READ(UART_INTMASK);
60}
61
62/*
63 * Interrupt handler for interrupts coming from the FPGA chip.
64 */
65void ll_uart_irq(void)
66{
67 unsigned int irq_src, irq_mask;
68
69 /* read the interrupt status registers */
70 irq_src = OCELOT_FPGA_READ(UART_INTSTAT);
71 irq_mask = OCELOT_FPGA_READ(UART_INTMASK);
72
73 /* mask for just the interrupts we want */
74 irq_src &= ~irq_mask;
75
76 do_IRQ(ls1bit8(irq_src) + 74);
77}
78
79struct irq_chip uart_irq_type = {
80 .name = "UART/FPGA",
81 .ack = mask_uart_irq,
82 .mask = mask_uart_irq,
83 .mask_ack = mask_uart_irq,
84 .unmask = unmask_uart_irq,
85};
86
87void uart_irq_init(void)
88{
89 set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq);
90 set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq);
91}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index aba3dbf47eda..f26ede001a0b 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -9,9 +9,7 @@ obj-y += pci.o pci-dac.o
9# 9#
10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o 10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
11obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o 11obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
12obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o
13obj-$(CONFIG_MIPS_MSC) += ops-msc.o 12obj-$(CONFIG_MIPS_MSC) += ops-msc.o
14obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
15obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o 13obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
16obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o 14obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
17obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o 15obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
@@ -22,17 +20,17 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
22# 20#
23obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o 21obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
24obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o 22obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
25obj-$(CONFIG_LASAT) += pci-lasat.o
26obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 23obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
27obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 24obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
28obj-$(CONFIG_MIPS_EV64120) += pci-ev64120.o
29obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 25obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
30obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 26obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
31obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 27obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
28obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 29obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
33obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o 30obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
34obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o 31obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
35obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o 32obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
33obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
36obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ 34obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
37 pci-yosemite.o 35 pci-yosemite.o
38obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o 36obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o
diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c
index c6cd6e9cdfbc..45224fd2c7ba 100644
--- a/arch/mips/pci/fixup-atlas.c
+++ b/arch/mips/pci/fixup-atlas.c
@@ -58,7 +58,7 @@ static char irq_tab[][5] __initdata = {
58 {0, 0, 0, 0, 0 } /* 21: Unused */ 58 {0, 0, 0, 0, 0 } /* 21: Unused */
59}; 59};
60 60
61int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 61int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
62{ 62{
63 return irq_tab[slot][pin]; 63 return irq_tab[slot][pin];
64} 64}
diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c
index c2f8304fe55b..ca0276c8070a 100644
--- a/arch/mips/pci/fixup-au1000.c
+++ b/arch/mips/pci/fixup-au1000.c
@@ -35,7 +35,7 @@
35 35
36extern char irq_tab_alchemy[][5]; 36extern char irq_tab_alchemy[][5];
37 37
38int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 38int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
39{ 39{
40 return irq_tab_alchemy[slot][pin]; 40 return irq_tab_alchemy[slot][pin];
41} 41}
diff --git a/arch/mips/pci/fixup-capcella.c b/arch/mips/pci/fixup-capcella.c
index 1e530751936c..1416bca6d1a3 100644
--- a/arch/mips/pci/fixup-capcella.c
+++ b/arch/mips/pci/fixup-capcella.c
@@ -38,7 +38,7 @@ static char irq_tab_capcella[][5] __initdata = {
38 [14] = { -1, INTA, INTB, INTC, INTD } 38 [14] = { -1, INTA, INTB, INTC, INTD }
39}; 39};
40 40
41int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 41int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
42{ 42{
43 return irq_tab_capcella[slot][pin]; 43 return irq_tab_capcella[slot][pin];
44} 44}
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index d57ffd7242ca..7fc475f7eae5 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -161,7 +161,7 @@ static char irq_tab_raq2[] __initdata = {
161 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 161 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ
162}; 162};
163 163
164int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 164int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
165{ 165{
166 if (cobalt_board_id < COBALT_BRD_ID_QUBE2) 166 if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
167 return irq_tab_qube1[slot]; 167 return irq_tab_qube1[slot];
diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c
index 7abcfd175d43..a2705895561d 100644
--- a/arch/mips/pci/fixup-emma2rh.c
+++ b/arch/mips/pci/fixup-emma2rh.c
@@ -89,7 +89,7 @@ static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev)
89DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH, 89DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,
90 emma2rh_pci_host_fixup); 90 emma2rh_pci_host_fixup);
91 91
92int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 92int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
93{ 93{
94 return irq_map[slot][pin]; 94 return irq_map[slot][pin];
95} 95}
diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c
index 1da696d43f00..cd64d9f177c4 100644
--- a/arch/mips/pci/fixup-excite.c
+++ b/arch/mips/pci/fixup-excite.c
@@ -21,7 +21,7 @@
21#include <linux/pci.h> 21#include <linux/pci.h>
22#include <excite.h> 22#include <excite.h>
23 23
24int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 24int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
25{ 25{
26 if (pin == 0) 26 if (pin == 0)
27 return -1; 27 return -1;
diff --git a/arch/mips/pci/fixup-ip32.c b/arch/mips/pci/fixup-ip32.c
index 3e66b0aa63ca..190fffd08d3e 100644
--- a/arch/mips/pci/fixup-ip32.c
+++ b/arch/mips/pci/fixup-ip32.c
@@ -39,7 +39,7 @@ static char irq_tab_mace[][5] __initdata = {
39 * irqs. I suppose a device without a pin A will thank us for doing it 39 * irqs. I suppose a device without a pin A will thank us for doing it
40 * right if there exists such a broken piece of crap. 40 * right if there exists such a broken piece of crap.
41 */ 41 */
42int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 42int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
43{ 43{
44 return irq_tab_mace[slot][pin]; 44 return irq_tab_mace[slot][pin];
45} 45}
diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c
index 73d18503517c..e974394be7bc 100644
--- a/arch/mips/pci/fixup-jmr3927.c
+++ b/arch/mips/pci/fixup-jmr3927.c
@@ -33,7 +33,7 @@
33 33
34#include <asm/jmr3927/jmr3927.h> 34#include <asm/jmr3927/jmr3927.h>
35 35
36int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 36int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
37{ 37{
38 unsigned char irq = pin; 38 unsigned char irq = pin;
39 39
diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c
new file mode 100644
index 000000000000..e18ae4f574c1
--- /dev/null
+++ b/arch/mips/pci/fixup-lm2e.c
@@ -0,0 +1,242 @@
1/*
2 * fixup-lm2e.c
3 *
4 * Copyright (C) 2004 ICT CAS
5 * Author: Li xiaoyu, ICT CAS
6 * lixy@ict.ac.cn
7 *
8 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
9 * Author: Fuxin Zhang, zhangfx@lemote.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <asm/mips-boards/bonito64.h>
35
36/* South bridge slot number is set by the pci probe process */
37static u8 sb_slot = 5;
38
39int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
40{
41 int irq = 0;
42
43 if (slot == sb_slot) {
44 switch (PCI_FUNC(dev->devfn)) {
45 case 2:
46 irq = 10;
47 break;
48 case 3:
49 irq = 11;
50 break;
51 case 5:
52 irq = 9;
53 break;
54 }
55 } else {
56 irq = BONITO_IRQ_BASE + 25 + pin;
57 }
58 return irq;
59
60}
61
62/* Do platform specific device initialization at pci_enable_device() time */
63int pcibios_plat_dev_init(struct pci_dev *dev)
64{
65 return 0;
66}
67
68static void __init loongson2e_nec_fixup(struct pci_dev *pdev)
69{
70 unsigned int val;
71
72 /* Configues port 1, 2, 3, 4 to be validate*/
73 pci_read_config_dword(pdev, 0xe0, &val);
74 pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4);
75
76 /* System clock is 48-MHz Oscillator. */
77 pci_write_config_dword(pdev, 0xe4, 1 << 5);
78}
79
80static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
81{
82 unsigned char c;
83
84 sb_slot = PCI_SLOT(pdev->devfn);
85
86 printk(KERN_INFO "via686b fix: ISA bridge\n");
87
88 /* Enable I/O Recovery time */
89 pci_write_config_byte(pdev, 0x40, 0x08);
90
91 /* Enable ISA refresh */
92 pci_write_config_byte(pdev, 0x41, 0x01);
93
94 /* disable ISA line buffer */
95 pci_write_config_byte(pdev, 0x45, 0x00);
96
97 /* Gate INTR, and flush line buffer */
98 pci_write_config_byte(pdev, 0x46, 0xe0);
99
100 /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */
101 /* pci_write_config_byte(pdev, 0x47, 0x20); */
102
103 /*
104 * enable PCI Delay Transaction, Enable EISA ports 4D0/4D1.
105 * enable time-out timer
106 */
107 pci_write_config_byte(pdev, 0x47, 0xe6);
108
109 /*
110 * enable level trigger on pci irqs: 9,10,11,13
111 * important! without this PCI interrupts won't work
112 */
113 outb(0x2e, 0x4d1);
114
115 /* 512 K PCI Decode */
116 pci_write_config_byte(pdev, 0x48, 0x01);
117
118 /* Wait for PGNT before grant to ISA Master/DMA */
119 pci_write_config_byte(pdev, 0x4a, 0x84);
120
121 /*
122 * Plug'n'Play
123 *
124 * Parallel DRQ 3, Floppy DRQ 2 (default)
125 */
126 pci_write_config_byte(pdev, 0x50, 0x0e);
127
128 /*
129 * IRQ Routing for Floppy and Parallel port
130 *
131 * IRQ 6 for floppy, IRQ 7 for parallel port
132 */
133 pci_write_config_byte(pdev, 0x51, 0x76);
134
135 /* IRQ Routing for serial ports (take IRQ 3 and 4) */
136 pci_write_config_byte(pdev, 0x52, 0x34);
137
138 /* All IRQ's level triggered. */
139 pci_write_config_byte(pdev, 0x54, 0x00);
140
141 /* route PIRQA-D irq */
142 pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */
143 pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; */
144 /* 3-0, PIRQB */
145 pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */
146
147 /* enable function 5/6, audio/modem */
148 pci_read_config_byte(pdev, 0x85, &c);
149 c &= ~(0x3 << 2);
150 pci_write_config_byte(pdev, 0x85, c);
151
152 printk(KERN_INFO"via686b fix: ISA bridge done\n");
153}
154
155static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
156{
157 printk(KERN_INFO"via686b fix: IDE\n");
158
159 /* Modify IDE controller setup */
160 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48);
161 pci_write_config_byte(pdev, PCI_COMMAND,
162 PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
163 PCI_COMMAND_MASTER);
164 pci_write_config_byte(pdev, 0x40, 0x0b);
165 /* legacy mode */
166 pci_write_config_byte(pdev, 0x42, 0x09);
167
168#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */
169 /* disable read prefetch/write post buffers */
170 pci_write_config_byte(pdev, 0x41, 0x02);
171
172 /* use 3/4 as fifo thresh hold */
173 pci_write_config_byte(pdev, 0x43, 0x0a);
174 pci_write_config_byte(pdev, 0x44, 0x00);
175
176 pci_write_config_byte(pdev, 0x45, 0x00);
177#else
178 pci_write_config_byte(pdev, 0x41, 0xc2);
179 pci_write_config_byte(pdev, 0x43, 0x35);
180 pci_write_config_byte(pdev, 0x44, 0x1c);
181
182 pci_write_config_byte(pdev, 0x45, 0x10);
183#endif
184
185 printk(KERN_INFO"via686b fix: IDE done\n");
186}
187
188static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev)
189{
190 /* irq routing */
191 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
192}
193
194static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev)
195{
196 /* irq routing */
197 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
198}
199
200static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev)
201{
202 unsigned int val;
203 unsigned char c;
204
205 /* enable IO */
206 pci_write_config_byte(pdev, PCI_COMMAND,
207 PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
208 PCI_COMMAND_MASTER);
209 pci_read_config_dword(pdev, 0x4, &val);
210 pci_write_config_dword(pdev, 0x4, val | 1);
211
212 /* route ac97 IRQ */
213 pci_write_config_byte(pdev, 0x3c, 9);
214
215 pci_read_config_byte(pdev, 0x8, &c);
216
217 /* link control: enable link & SGD PCM output */
218 pci_write_config_byte(pdev, 0x41, 0xcc);
219
220 /* disable game port, FM, midi, sb, enable write to reg2c-2f */
221 pci_write_config_byte(pdev, 0x42, 0x20);
222
223 /* we are using Avance logic codec */
224 pci_write_config_word(pdev, 0x2c, 0x1005);
225 pci_write_config_word(pdev, 0x2e, 0x4710);
226 pci_read_config_dword(pdev, 0x2c, &val);
227
228 pci_write_config_byte(pdev, 0x42, 0x0);
229}
230
231DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
232 loongson2e_686b_func0_fixup);
233DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
234 loongson2e_686b_func1_fixup);
235DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2,
236 loongson2e_686b_func2_fixup);
237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3,
238 loongson2e_686b_func3_fixup);
239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5,
240 loongson2e_686b_func5_fixup);
241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
242 loongson2e_nec_fixup);
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index bf2c41d1e9c5..0f48498bc231 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -36,7 +36,7 @@ static char irq_tab[][5] __initdata = {
36 {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */ 36 {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
37}; 37};
38 38
39int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 39int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
40{ 40{
41 int virq; 41 int virq;
42 virq = irq_tab[slot][pin]; 42 virq = irq_tab[slot][pin];
diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c
index 3c9ae41f7517..591159625722 100644
--- a/arch/mips/pci/fixup-mpc30x.c
+++ b/arch/mips/pci/fixup-mpc30x.c
@@ -34,7 +34,7 @@ static const int irq_tab_mpc30x[] __initdata = {
34 [29] = MQ200_IRQ, 34 [29] = MQ200_IRQ,
35}; 35};
36 36
37int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 37int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
38{ 38{
39 if (slot == 30) 39 if (slot == 30)
40 return internal_func_irqs[PCI_FUNC(dev->devfn)]; 40 return internal_func_irqs[PCI_FUNC(dev->devfn)];
diff --git a/arch/mips/pci/fixup-ocelot-c.c b/arch/mips/pci/fixup-ocelot-c.c
deleted file mode 100644
index d45494807a33..000000000000
--- a/arch/mips/pci/fixup-ocelot-c.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * Copyright 2002 Momentum Computer Inc.
3 * Author: Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on work for the Linux port to the Ocelot board, which is
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 *
9 * arch/mips/momentum/ocelot_g/pci.c
10 * Board-specific PCI routines for mv64340 controller.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/types.h>
18#include <linux/pci.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21
22int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
23{
24 int bus = dev->bus->number;
25
26 if (bus == 0 && slot == 1)
27 return 2; /* PCI-X A */
28 if (bus == 1 && slot == 1)
29 return 12; /* PCI-X B */
30 if (bus == 1 && slot == 2)
31 return 4; /* PCI B */
32
33return 0;
34 panic("Whooops in pcibios_map_irq");
35}
36
37/* Do platform specific device initialization at pci_enable_device() time */
38int pcibios_plat_dev_init(struct pci_dev *dev)
39{
40 return 0;
41}
diff --git a/arch/mips/pci/fixup-ocelot3.c b/arch/mips/pci/fixup-ocelot3.c
deleted file mode 100644
index ececc03ec620..000000000000
--- a/arch/mips/pci/fixup-ocelot3.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Montavista Software Inc.
7 * Author: Manish Lachwani (mlachwani@mvista.com)
8 *
9 * Looking at the schematics for the Ocelot-3 board, there are
10 * two PCI busses and each bus has two PCI slots.
11 */
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <asm/mipsregs.h>
16
17/*
18 * Do platform specific device initialization at
19 * pci_enable_device() time
20 */
21int pcibios_plat_dev_init(struct pci_dev *dev)
22{
23 return 0;
24}
25
26int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
27{
28 int bus = dev->bus->number;
29
30 if (bus == 0 && slot == 1)
31 return 2; /* PCI-X A */
32 if (bus == 0 && slot == 2)
33 return 3; /* PCI-X B */
34 if (bus == 1 && slot == 1)
35 return 4; /* PCI A */
36 if (bus == 1 && slot == 2)
37 return 5; /* PCI B */
38
39return 0;
40 panic("Whooops in pcibios_map_irq");
41}
diff --git a/arch/mips/pci/fixup-pmcmsp.c b/arch/mips/pci/fixup-pmcmsp.c
new file mode 100644
index 000000000000..00261211dbfa
--- /dev/null
+++ b/arch/mips/pci/fixup-pmcmsp.c
@@ -0,0 +1,216 @@
1/*
2 * PMC-Sierra MSP board specific pci fixups.
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Copyright 2005-2007 PMC-Sierra, Inc
6 *
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#ifdef CONFIG_PCI
32
33#include <linux/types.h>
34#include <linux/pci.h>
35#include <linux/kernel.h>
36#include <linux/init.h>
37
38#include <asm/byteorder.h>
39
40#include <msp_pci.h>
41#include <msp_cic_int.h>
42
43/* PCI interrupt pins */
44#define IRQ4 MSP_INT_EXT4
45#define IRQ5 MSP_INT_EXT5
46#define IRQ6 MSP_INT_EXT6
47
48#if defined(CONFIG_PMC_MSP7120_GW)
49/* Garibaldi Board IRQ wiring to PCI slots */
50static char irq_tab[][5] __initdata = {
51 /* INTA INTB INTC INTD */
52 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
53 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
54 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
55 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
56 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
57 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
58 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
59 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
60 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
61 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
62 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
63 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
64 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
65 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
66 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
67 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
68 {0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
69 {0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
70 {0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
71 {0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
72 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
73 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
74 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
75 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
76 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
77 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
78 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
79 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
80 {0, IRQ4, IRQ4, 0, 0 }, /* 18 (AD[28]): slot 0 */
81 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
82 {0, IRQ5, IRQ5, 0, 0 }, /* 20 (AD[30]): slot 1 */
83 {0, IRQ6, IRQ6, 0, 0 } /* 21 (AD[31]): slot 2 */
84};
85
86#elif defined(CONFIG_PMC_MSP7120_EVAL)
87
88/* MSP7120 Eval Board IRQ wiring to PCI slots */
89static char irq_tab[][5] __initdata = {
90 /* INTA INTB INTC INTD */
91 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
92 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
93 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
94 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
95 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
96 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
97 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
98 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
99 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
100 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
101 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
102 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
103 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
104 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
105 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
106 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
107 {0, IRQ6, IRQ6, 0, 0 }, /* 6 (AD[16]): slot 3 (mini) */
108 {0, IRQ5, IRQ5, 0, 0 }, /* 7 (AD[17]): slot 2 (mini) */
109 {0, IRQ4, IRQ4, IRQ4, IRQ4}, /* 8 (AD[18]): slot 0 (PCI) */
110 {0, IRQ5, IRQ5, IRQ5, IRQ5}, /* 9 (AD[19]): slot 1 (PCI) */
111 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
112 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
113 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
114 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
115 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
116 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
117 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
118 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
119 {0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
120 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
121 {0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
122 {0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
123};
124
125#else
126
127/* Unknown board -- don't assign any IRQs */
128static char irq_tab[][5] __initdata = {
129 /* INTA INTB INTC INTD */
130 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
131 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
132 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
133 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
134 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
135 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
136 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
137 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
138 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
139 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
140 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
141 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
142 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
143 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
144 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
145 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
146 {0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
147 {0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
148 {0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
149 {0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
150 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
151 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
152 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
153 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
154 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
155 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
156 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
157 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
158 {0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
159 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
160 {0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
161 {0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
162};
163#endif
164
165/*****************************************************************************
166 *
167 * FUNCTION: pcibios_plat_dev_init
168 * _________________________________________________________________________
169 *
170 * DESCRIPTION: Perform platform specific device initialization at
171 * pci_enable_device() time.
172 * None are needed for the MSP7120 PCI Controller.
173 *
174 * INPUTS: dev - structure describing the PCI device
175 *
176 * OUTPUTS: none
177 *
178 * RETURNS: PCIBIOS_SUCCESSFUL
179 *
180 ****************************************************************************/
181int pcibios_plat_dev_init(struct pci_dev *dev)
182{
183 return PCIBIOS_SUCCESSFUL;
184}
185
186/*****************************************************************************
187 *
188 * FUNCTION: pcibios_map_irq
189 * _________________________________________________________________________
190 *
191 * DESCRIPTION: Perform board supplied PCI IRQ mapping routine.
192 *
193 * INPUTS: dev - unused
194 * slot - PCI slot. Identified by which bit of the AD[] bus
195 * drives the IDSEL line. AD[10] is 0, AD[31] is
196 * slot 21.
197 * pin - numbered using the scheme of the PCI_INTERRUPT_PIN
198 * field of the config header.
199 *
200 * OUTPUTS: none
201 *
202 * RETURNS: IRQ number
203 *
204 ****************************************************************************/
205int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
206{
207#if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL)
208 printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n");
209#endif
210 printk(KERN_WARNING "PCI: irq_tab returned %d for slot=%d pin=%d\n",
211 irq_tab[slot][pin], slot, pin);
212
213 return irq_tab[slot][pin];
214}
215
216#endif /* CONFIG_PCI */
diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c
index 50546dab6689..96857ac63bf5 100644
--- a/arch/mips/pci/fixup-pnx8550.c
+++ b/arch/mips/pci/fixup-pnx8550.c
@@ -45,7 +45,7 @@ void __init pcibios_fixup(void)
45 /* nothing to do here */ 45 /* nothing to do here */
46} 46}
47 47
48int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 48int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
49{ 49{
50 return pnx8550_irq_tab[slot][pin]; 50 return pnx8550_irq_tab[slot][pin];
51} 51}
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index ceeb1860895a..3cdbecb8e714 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -119,7 +119,7 @@ int pci_get_irq(struct pci_dev *dev, int pin)
119 return irq; 119 return irq;
120} 120}
121 121
122int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 122int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
123{ 123{
124 unsigned char irq; 124 unsigned char irq;
125 125
diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c
index 36e5fb1b3786..a45bedd17233 100644
--- a/arch/mips/pci/fixup-sni.c
+++ b/arch/mips/pci/fixup-sni.c
@@ -120,7 +120,7 @@ static inline int is_rm300_revd(void)
120 return (csmsr & 0xa0) == 0x20; 120 return (csmsr & 0xa0) == 0x20;
121} 121}
122 122
123int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 123int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
124{ 124{
125 switch (sni_brd_type) { 125 switch (sni_brd_type) {
126 case SNI_BRD_PCI_TOWER: 126 case SNI_BRD_PCI_TOWER:
diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c
index 734f2b71e164..720a2b720c5c 100644
--- a/arch/mips/pci/fixup-tb0219.c
+++ b/arch/mips/pci/fixup-tb0219.c
@@ -23,7 +23,7 @@
23 23
24#include <asm/vr41xx/tb0219.h> 24#include <asm/vr41xx/tb0219.h>
25 25
26int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 26int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
27{ 27{
28 int irq = -1; 28 int irq = -1;
29 29
diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c
index c9e7cb4361a1..e3eedf4bf9bd 100644
--- a/arch/mips/pci/fixup-tb0226.c
+++ b/arch/mips/pci/fixup-tb0226.c
@@ -23,7 +23,7 @@
23#include <asm/vr41xx/giu.h> 23#include <asm/vr41xx/giu.h>
24#include <asm/vr41xx/tb0226.h> 24#include <asm/vr41xx/tb0226.h>
25 25
26int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 26int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
27{ 27{
28 int irq = -1; 28 int irq = -1;
29 29
diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c
index fbe6bcb28199..267ab3dc3d42 100644
--- a/arch/mips/pci/fixup-tb0287.c
+++ b/arch/mips/pci/fixup-tb0287.c
@@ -22,7 +22,7 @@
22 22
23#include <asm/vr41xx/tb0287.h> 23#include <asm/vr41xx/tb0287.h>
24 24
25int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 25int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
26{ 26{
27 unsigned char bus; 27 unsigned char bus;
28 int irq = -1; 28 int irq = -1;
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c
index f455520ada88..2485f47dfe6f 100644
--- a/arch/mips/pci/fixup-tx4938.c
+++ b/arch/mips/pci/fixup-tx4938.c
@@ -69,7 +69,7 @@ int pci_get_irq(struct pci_dev *dev, int pin)
69 return irq; 69 return irq;
70} 70}
71 71
72int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 72int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
73{ 73{
74 unsigned char irq = 0; 74 unsigned char irq = 0;
75 75
diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c
index a8d9d22b13df..de5e5f6bbf4c 100644
--- a/arch/mips/pci/fixup-vr4133.c
+++ b/arch/mips/pci/fixup-vr4133.c
@@ -169,7 +169,7 @@ void i8259_init(void)
169} 169}
170#endif 170#endif
171 171
172int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 172int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
173{ 173{
174 extern int pci_probe_only; 174 extern int pci_probe_only;
175 pci_probe_only = 1; 175 pci_probe_only = 1;
diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c
index 3357c1300bb1..3d277549d5df 100644
--- a/arch/mips/pci/fixup-wrppmc.c
+++ b/arch/mips/pci/fixup-wrppmc.c
@@ -25,7 +25,7 @@ static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
25 [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0}, 25 [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
26}; 26};
27 27
28int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 28int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
29{ 29{
30 return pci_irq_tab[slot][pin]; 30 return pci_irq_tab[slot][pin];
31} 31}
diff --git a/arch/mips/pci/fixup-yosemite.c b/arch/mips/pci/fixup-yosemite.c
index 81d77a587a51..fdafb13a793b 100644
--- a/arch/mips/pci/fixup-yosemite.c
+++ b/arch/mips/pci/fixup-yosemite.c
@@ -26,7 +26,7 @@
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/pci.h> 27#include <linux/pci.h>
28 28
29int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 29int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
30{ 30{
31 if (pin == 0) 31 if (pin == 0)
32 return -1; 32 return -1;
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index dc35270b65a2..f742c51acf0d 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -29,83 +29,60 @@
29#define PCI_ACCESS_READ 0 29#define PCI_ACCESS_READ 0
30#define PCI_ACCESS_WRITE 1 30#define PCI_ACCESS_WRITE 1
31 31
32/* 32#ifdef CONFIG_LEMOTE_FULONG
33 * PCI configuration cycle AD bus definition 33#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
34 */ 34#define ID_SEL_BEGIN 11
35/* Type 0 */ 35#else
36#define PCI_CFG_TYPE0_REG_SHF 0 36#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
37#define PCI_CFG_TYPE0_FUNC_SHF 8 37#define ID_SEL_BEGIN 10
38#endif
39#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
38 40
39/* Type 1 */
40#define PCI_CFG_TYPE1_REG_SHF 0
41#define PCI_CFG_TYPE1_FUNC_SHF 8
42#define PCI_CFG_TYPE1_DEV_SHF 11
43#define PCI_CFG_TYPE1_BUS_SHF 16
44 41
45static int bonito64_pcibios_config_access(unsigned char access_type, 42static int bonito64_pcibios_config_access(unsigned char access_type,
46 struct pci_bus *bus, 43 struct pci_bus *bus,
47 unsigned int devfn, int where, 44 unsigned int devfn, int where,
48 u32 * data) 45 u32 * data)
49{ 46{
50 unsigned char busnum = bus->number; 47 u32 busnum = bus->number;
48 u32 addr, type;
51 u32 dummy; 49 u32 dummy;
52 u64 pci_addr; 50 void *addrp;
53 51 int device = PCI_SLOT(devfn);
54 /* Algorithmics Bonito64 system controller. */ 52 int function = PCI_FUNC(devfn);
53 int reg = where & ~3;
55 54
56 if ((busnum == 0) && (PCI_SLOT(devfn) > 21)) {
57 /* We number bus 0 devices from 0..21 */
58 return -1;
59 }
60
61 /* Clear cause register bits */
62 BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
63 BONITO_PCICMD_MTABORT_CLR);
64
65 /*
66 * Setup pattern to be used as PCI "address" for
67 * Type 0 cycle
68 */
69 if (busnum == 0) { 55 if (busnum == 0) {
70 /* IDSEL */ 56 /* Type 0 configuration for onboard PCI bus */
71 pci_addr = (u64) 1 << (PCI_SLOT(devfn) + 10); 57 if (device > MAX_DEV_NUM)
72 } else { 58 return -1;
73 /* Bus number */
74 pci_addr = busnum << PCI_CFG_TYPE1_BUS_SHF;
75
76 /* Device number */
77 pci_addr |=
78 PCI_SLOT(devfn) << PCI_CFG_TYPE1_DEV_SHF;
79 }
80
81 /* Function (same for Type 0/1) */
82 pci_addr |= PCI_FUNC(devfn) << PCI_CFG_TYPE0_FUNC_SHF;
83
84 /* Register number (same for Type 0/1) */
85 pci_addr |= (where & ~0x3) << PCI_CFG_TYPE0_REG_SHF;
86 59
87 if (busnum == 0) { 60 addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
88 /* Type 0 */ 61 type = 0;
89 BONITO_PCIMAP_CFG = pci_addr >> 16;
90 } else { 62 } else {
91 /* Type 1 */ 63 /* Type 1 configuration for offboard PCI bus */
92 BONITO_PCIMAP_CFG = (pci_addr >> 16) | 0x10000; 64 addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
65 type = 0x10000;
93 } 66 }
94 67
95 pci_addr &= 0xffff; 68 /* Clear aborts */
69 BONITO_PCICMD |= BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR;
70
71 BONITO_PCIMAP_CFG = (addr >> 16) | type;
96 72
97 /* Flush Bonito register block */ 73 /* Flush Bonito register block */
98 dummy = BONITO_PCIMAP_CFG; 74 dummy = BONITO_PCIMAP_CFG;
99 iob(); /* sync */ 75 mmiowb();
100 76
101 /* Perform access */ 77 addrp = CFG_SPACE_REG(addr & 0xffff);
102 if (access_type == PCI_ACCESS_WRITE) { 78 if (access_type == PCI_ACCESS_WRITE) {
103 *(volatile u32 *) (_pcictrl_bonito_pcicfg + (u32)pci_addr) = *(u32 *) data; 79 writel(cpu_to_le32(*data), addrp);
104 80#ifndef CONFIG_LEMOTE_FULONG
105 /* Wait till done */ 81 /* Wait till done */
106 while (BONITO_PCIMSTAT & 0xF); 82 while (BONITO_PCIMSTAT & 0xF);
83#endif
107 } else { 84 } else {
108 *(u32 *) data = *(volatile u32 *) (_pcictrl_bonito_pcicfg + (u32)pci_addr); 85 *data = le32_to_cpu(readl(addrp));
109 } 86 }
110 87
111 /* Detect Master/Target abort */ 88 /* Detect Master/Target abort */
@@ -121,6 +98,7 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
121 } 98 }
122 99
123 return 0; 100 return 0;
101
124} 102}
125 103
126 104
diff --git a/arch/mips/pci/ops-marvell.c b/arch/mips/pci/ops-marvell.c
deleted file mode 100644
index 1ac5c59199d1..000000000000
--- a/arch/mips/pci/ops-marvell.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/pci.h>
11
12#include <asm/marvell.h>
13
14static int mv_read_config(struct pci_bus *bus, unsigned int devfn,
15 int where, int size, u32 * val)
16{
17 struct mv_pci_controller *mvbc = bus->sysdata;
18 unsigned long address_reg, data_reg;
19 u32 address;
20
21 address_reg = mvbc->config_addr;
22 data_reg = mvbc->config_vreg;
23
24 /* Accessing device 31 crashes those Marvells. Since years.
25 Will they ever make sane controllers ... */
26 if (PCI_SLOT(devfn) == 31)
27 return PCIBIOS_DEVICE_NOT_FOUND;
28
29 address = (bus->number << 16) | (devfn << 8) |
30 (where & 0xfc) | 0x80000000;
31
32 /* start the configuration cycle */
33 MV_WRITE(address_reg, address);
34
35 switch (size) {
36 case 1:
37 *val = MV_READ_8(data_reg + (where & 0x3));
38 break;
39
40 case 2:
41 *val = MV_READ_16(data_reg + (where & 0x3));
42 break;
43
44 case 4:
45 *val = MV_READ(data_reg);
46 break;
47 }
48
49 return PCIBIOS_SUCCESSFUL;
50}
51
52static int mv_write_config(struct pci_bus *bus, unsigned int devfn,
53 int where, int size, u32 val)
54{
55 struct mv_pci_controller *mvbc = bus->sysdata;
56 unsigned long address_reg, data_reg;
57 u32 address;
58
59 address_reg = mvbc->config_addr;
60 data_reg = mvbc->config_vreg;
61
62 /* Accessing device 31 crashes those Marvells. Since years.
63 Will they ever make sane controllers ... */
64 if (PCI_SLOT(devfn) == 31)
65 return PCIBIOS_DEVICE_NOT_FOUND;
66
67 address = (bus->number << 16) | (devfn << 8) |
68 (where & 0xfc) | 0x80000000;
69
70 /* start the configuration cycle */
71 MV_WRITE(address_reg, address);
72
73 switch (size) {
74 case 1:
75 MV_WRITE_8(data_reg + (where & 0x3), val);
76 break;
77
78 case 2:
79 MV_WRITE_16(data_reg + (where & 0x3), val);
80 break;
81
82 case 4:
83 MV_WRITE(data_reg, val);
84 break;
85 }
86
87 return PCIBIOS_SUCCESSFUL;
88}
89
90struct pci_ops mv_pci_ops = {
91 .read = mv_read_config,
92 .write = mv_write_config
93};
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
deleted file mode 100644
index a8d38dc8c504..000000000000
--- a/arch/mips/pci/ops-nile4.c
+++ /dev/null
@@ -1,147 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/pci.h>
4#include <asm/bootinfo.h>
5
6#include <asm/lasat/lasat.h>
7#include <asm/gt64120.h>
8#include <asm/nile4.h>
9
10#define PCI_ACCESS_READ 0
11#define PCI_ACCESS_WRITE 1
12
13#define LO(reg) (reg / 4)
14#define HI(reg) (reg / 4 + 1)
15
16volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
17
18static DEFINE_SPINLOCK(nile4_pci_lock);
19
20static int nile4_pcibios_config_access(unsigned char access_type,
21 struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
22{
23 unsigned char busnum = bus->number;
24 u32 adr, mask, err;
25
26 if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
27 /* The addressing scheme chosen leaves room for just
28 * 8 devices on the first busnum (besides the PCI
29 * controller itself) */
30 return PCIBIOS_DEVICE_NOT_FOUND;
31
32 if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
33 /* Access controller registers directly */
34 if (access_type == PCI_ACCESS_WRITE) {
35 vrc_pciregs[(0x200 + where) >> 2] = *val;
36 } else {
37 *val = vrc_pciregs[(0x200 + where) >> 2];
38 }
39 return PCIBIOS_SUCCESSFUL;
40 }
41
42 /* Temporarily map PCI Window 1 to config space */
43 mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
44 vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
45
46 /* Clear PCI Error register. This also clears the Error Type
47 * bits in the Control register */
48 vrc_pciregs[LO(NILE4_PCIERR)] = 0;
49 vrc_pciregs[HI(NILE4_PCIERR)] = 0;
50
51 /* Setup address */
52 if (busnum == 0)
53 adr =
54 KSEG1ADDR(PCI_WINDOW1) +
55 ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
56 | (where & ~3));
57 else
58 adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |
59 (where & ~3);
60
61 if (access_type == PCI_ACCESS_WRITE)
62 *(u32 *) adr = *val;
63 else
64 *val = *(u32 *) adr;
65
66 /* Check for master or target abort */
67 err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
68
69 /* Restore PCI Window 1 */
70 vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
71
72 if (err)
73 return PCIBIOS_DEVICE_NOT_FOUND;
74
75 return PCIBIOS_SUCCESSFUL;
76}
77
78static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
79 int where, int size, u32 * val)
80{
81 unsigned long flags;
82 u32 data = 0;
83 int err;
84
85 if ((size == 2) && (where & 1))
86 return PCIBIOS_BAD_REGISTER_NUMBER;
87 else if ((size == 4) && (where & 3))
88 return PCIBIOS_BAD_REGISTER_NUMBER;
89
90 spin_lock_irqsave(&nile4_pci_lock, flags);
91 err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
92 &data);
93 spin_unlock_irqrestore(&nile4_pci_lock, flags);
94
95 if (err)
96 return err;
97
98 if (size == 1)
99 *val = (data >> ((where & 3) << 3)) & 0xff;
100 else if (size == 2)
101 *val = (data >> ((where & 3) << 3)) & 0xffff;
102 else
103 *val = data;
104
105 return PCIBIOS_SUCCESSFUL;
106}
107
108static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
109 int where, int size, u32 val)
110{
111 unsigned long flags;
112 u32 data = 0;
113 int err;
114
115 if ((size == 2) && (where & 1))
116 return PCIBIOS_BAD_REGISTER_NUMBER;
117 else if ((size == 4) && (where & 3))
118 return PCIBIOS_BAD_REGISTER_NUMBER;
119
120 spin_lock_irqsave(&nile4_pci_lock, flags);
121 err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
122 &data);
123 spin_unlock_irqrestore(&nile4_pci_lock, flags);
124
125 if (err)
126 return err;
127
128 if (size == 1)
129 data = (data & ~(0xff << ((where & 3) << 3))) |
130 (val << ((where & 3) << 3));
131 else if (size == 2)
132 data = (data & ~(0xffff << ((where & 3) << 3))) |
133 (val << ((where & 3) << 3));
134 else
135 data = val;
136
137 if (nile4_pcibios_config_access
138 (PCI_ACCESS_WRITE, bus, devfn, where, &data))
139 return -1;
140
141 return PCIBIOS_SUCCESSFUL;
142}
143
144struct pci_ops nile4_pci_ops = {
145 .read = nile4_pcibios_read,
146 .write = nile4_pcibios_write,
147};
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
new file mode 100644
index 000000000000..09fa007c1d1b
--- /dev/null
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -0,0 +1,994 @@
1/*
2 * PMC-Sierra MSP board specific pci_ops
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Copyright 2005-2007 PMC-Sierra, Inc
6 *
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 *
9 * Much of the code is derived from the original DDB5074 port by
10 * Geert Uytterhoeven <geert@sonycom.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18
19#define PCI_COUNTERS 1
20
21#include <linux/types.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24
25#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
26#include <linux/proc_fs.h>
27#include <linux/seq_file.h>
28#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
29
30#include <linux/kernel.h>
31#include <linux/init.h>
32
33#include <asm/byteorder.h>
34#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
35#include <asm/mipsmtregs.h>
36#endif
37
38#include <msp_prom.h>
39#include <msp_cic_int.h>
40#include <msp_pci.h>
41#include <msp_regs.h>
42#include <msp_regops.h>
43
44#define PCI_ACCESS_READ 0
45#define PCI_ACCESS_WRITE 1
46
47#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
48static char proc_init;
49extern struct proc_dir_entry *proc_bus_pci_dir;
50unsigned int pci_int_count[32];
51
52static void pci_proc_init(void);
53
54/*****************************************************************************
55 *
56 * FUNCTION: read_msp_pci_counts
57 * _________________________________________________________________________
58 *
59 * DESCRIPTION: Prints the count of how many times each PCI
60 * interrupt has asserted. Can be invoked by the
61 * /proc filesystem.
62 *
63 * INPUTS: page - part of STDOUT calculation
64 * off - part of STDOUT calculation
65 * count - part of STDOUT calculation
66 * data - unused
67 *
68 * OUTPUTS: start - new start location
69 * eof - end of file pointer
70 *
71 * RETURNS: len - STDOUT length
72 *
73 ****************************************************************************/
74static int read_msp_pci_counts(char *page, char **start, off_t off,
75 int count, int *eof, void *data)
76{
77 int i;
78 int len = 0;
79 unsigned int intcount, total = 0;
80
81 for (i = 0; i < 32; ++i) {
82 intcount = pci_int_count[i];
83 if (intcount != 0) {
84 len += sprintf(page + len, "[%d] = %u\n", i, intcount);
85 total += intcount;
86 }
87 }
88
89 len += sprintf(page + len, "total = %u\n", total);
90 if (len <= off+count)
91 *eof = 1;
92
93 *start = page + off;
94 len -= off;
95 if (len > count)
96 len = count;
97 if (len < 0)
98 len = 0;
99
100 return len;
101}
102
103/*****************************************************************************
104 *
105 * FUNCTION: gen_pci_cfg_wr
106 * _________________________________________________________________________
107 *
108 * DESCRIPTION: Generates a configuration write cycle for debug purposes.
109 * The IDSEL line asserted and location and data written are
110 * immaterial. Just want to be able to prove that a
111 * configuration write can be correctly generated on the
112 * PCI bus. Intent is that this function by invocable from
113 * the /proc filesystem.
114 *
115 * INPUTS: page - part of STDOUT calculation
116 * off - part of STDOUT calculation
117 * count - part of STDOUT calculation
118 * data - unused
119 *
120 * OUTPUTS: start - new start location
121 * eof - end of file pointer
122 *
123 * RETURNS: len - STDOUT length
124 *
125 ****************************************************************************/
126static int gen_pci_cfg_wr(char *page, char **start, off_t off,
127 int count, int *eof, void *data)
128{
129 unsigned char where = 0; /* Write to static Device/Vendor ID */
130 unsigned char bus_num = 0; /* Bus 0 */
131 unsigned char dev_fn = 0xF; /* Arbitrary device number */
132 u32 wr_data = 0xFF00AA00; /* Arbitrary data */
133 struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
134 int len = 0;
135 unsigned long value;
136 int intr;
137
138 len += sprintf(page + len, "PMC MSP PCI: Beginning\n");
139
140 if (proc_init == 0) {
141 pci_proc_init();
142 proc_init = ~0;
143 }
144
145 len += sprintf(page + len, "PMC MSP PCI: Before Cfg Wr\n");
146
147 /*
148 * Generate PCI Configuration Write Cycle
149 */
150
151 /* Clear cause register bits */
152 preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
153
154 /* Setup address that is to appear on PCI bus */
155 preg->config_addr = BPCI_CFGADDR_ENABLE |
156 (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
157 (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
158 (where & 0xFC);
159
160 value = cpu_to_le32(wr_data);
161
162 /* Launch the PCI configuration write cycle */
163 *PCI_CONFIG_SPACE_REG = value;
164
165 /*
166 * Check if the PCI configuration cycle (rd or wr) succeeded, by
167 * checking the status bits for errors like master or target abort.
168 */
169 intr = preg->if_status;
170
171 len += sprintf(page + len, "PMC MSP PCI: After Cfg Wr\n");
172
173 /* Handle STDOUT calculations */
174 if (len <= off+count)
175 *eof = 1;
176 *start = page + off;
177 len -= off;
178 if (len > count)
179 len = count;
180 if (len < 0)
181 len = 0;
182
183 return len;
184}
185
186/*****************************************************************************
187 *
188 * FUNCTION: pci_proc_init
189 * _________________________________________________________________________
190 *
191 * DESCRIPTION: Create entries in the /proc filesystem for debug access.
192 *
193 * INPUTS: none
194 *
195 * OUTPUTS: none
196 *
197 * RETURNS: none
198 *
199 ****************************************************************************/
200static void pci_proc_init(void)
201{
202 create_proc_read_entry("pmc_msp_pci_rd_cnt", 0, NULL,
203 read_msp_pci_counts, NULL);
204 create_proc_read_entry("pmc_msp_pci_cfg_wr", 0, NULL,
205 gen_pci_cfg_wr, NULL);
206}
207#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
208
209spinlock_t bpci_lock = SPIN_LOCK_UNLOCKED;
210
211/*****************************************************************************
212 *
213 * STRUCT: pci_io_resource
214 * _________________________________________________________________________
215 *
216 * DESCRIPTION: Defines the address range that pciauto() will use to
217 * assign to the I/O BARs of PCI devices.
218 *
219 * Use the start and end addresses of the MSP7120 PCI Host
220 * Controller I/O space, in the form that they appear on the
221 * PCI bus AFTER MSP7120 has performed address translation.
222 *
223 * For I/O accesses, MSP7120 ignores OATRAN and maps I/O
224 * accesses into the bottom 0xFFF region of address space,
225 * so that is the range to put into the pci_io_resource
226 * struct.
227 *
228 * In MSP4200, the start address was 0x04 instead of the
229 * expected 0x00. Will just assume there was a good reason
230 * for this!
231 *
232 * NOTES: Linux, by default, will assign I/O space to the lowest
233 * region of address space. Since MSP7120 and Linux,
234 * by default, have no offset in between how they map, the
235 * io_offset element of pci_controller struct should be set
236 * to zero.
237 * ELEMENTS:
238 * name - String used for a meaningful name.
239 *
240 * start - Start address of MSP7120's I/O space, as MSP7120 presents
241 * the address on the PCI bus.
242 *
243 * end - End address of MSP7120's I/O space, as MSP7120 presents
244 * the address on the PCI bus.
245 *
246 * flags - Attributes indicating the type of resource. In this case,
247 * indicate I/O space.
248 *
249 ****************************************************************************/
250static struct resource pci_io_resource = {
251 .name = "pci IO space",
252 .start = 0x04,
253 .end = 0x0FFF,
254 .flags = IORESOURCE_IO /* I/O space */
255};
256
257/*****************************************************************************
258 *
259 * STRUCT: pci_mem_resource
260 * _________________________________________________________________________
261 *
262 * DESCRIPTION: Defines the address range that pciauto() will use to
263 * assign to the memory BARs of PCI devices.
264 *
265 * The .start and .end values are dependent upon how address
266 * translation is performed by the OATRAN regiser.
267 *
268 * The values to use for .start and .end are the values
269 * in the form they appear on the PCI bus AFTER MSP7120 has
270 * performed OATRAN address translation.
271 *
272 * ELEMENTS:
273 * name - String used for a meaningful name.
274 *
275 * start - Start address of MSP7120's memory space, as MSP7120 presents
276 * the address on the PCI bus.
277 *
278 * end - End address of MSP7120's memory space, as MSP7120 presents
279 * the address on the PCI bus.
280 *
281 * flags - Attributes indicating the type of resource. In this case,
282 * indicate memory space.
283 *
284 ****************************************************************************/
285static struct resource pci_mem_resource = {
286 .name = "pci memory space",
287 .start = MSP_PCI_SPACE_BASE,
288 .end = MSP_PCI_SPACE_END,
289 .flags = IORESOURCE_MEM /* memory space */
290};
291
292/*****************************************************************************
293 *
294 * FUNCTION: bpci_interrupt
295 * _________________________________________________________________________
296 *
297 * DESCRIPTION: PCI status interrupt handler. Updates the count of how
298 * many times each status bit has been set, then clears
299 * the status bits. If the appropriate macros are defined,
300 * these counts can be viewed via the /proc filesystem.
301 *
302 * INPUTS: irq - unused
303 * dev_id - unused
304 * pt_regs - unused
305 *
306 * OUTPUTS: none
307 *
308 * RETURNS: PCIBIOS_SUCCESSFUL - success
309 *
310 ****************************************************************************/
311static int bpci_interrupt(int irq, void *dev_id)
312{
313 struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
314 unsigned int stat = preg->if_status;
315
316#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
317 int i;
318 for (i = 0; i < 32; ++i) {
319 if ((1 << i) & stat)
320 ++pci_int_count[i];
321 }
322#endif /* PROC_FS && PCI_COUNTERS */
323
324 /* printk("PCI ISR: Status=%08X\n", stat); */
325
326 /* write to clear all asserted interrupts */
327 preg->if_status = stat;
328
329 return PCIBIOS_SUCCESSFUL;
330}
331
332/*****************************************************************************
333 *
334 * FUNCTION: msp_pcibios_config_access
335 * _________________________________________________________________________
336 *
337 * DESCRIPTION: Performs a PCI configuration access (rd or wr), then
338 * checks that the access succeeded by querying MSP7120's
339 * PCI status bits.
340 *
341 * INPUTS:
342 * access_type - kind of PCI configuration cycle to perform
343 * (read or write). Legal values are
344 * PCI_ACCESS_WRITE and PCI_ACCESS_READ.
345 *
346 * bus - pointer to the bus number of the device to
347 * be targetted for the configuration cycle.
348 * The only element of the pci_bus structure
349 * used is bus->number. This argument determines
350 * if the configuration access will be Type 0 or
351 * Type 1. Since MSP7120 assumes itself to be the
352 * PCI Host, any non-zero bus->number generates
353 * a Type 1 access.
354 *
355 * devfn - this is an 8-bit field. The lower three bits
356 * specify the function number of the device to
357 * be targetted for the configuration cycle, with
358 * all three-bit combinations being legal. The
359 * upper five bits specify the device number,
360 * with legal values being 10 to 31.
361 *
362 * where - address within the Configuration Header
363 * space to access.
364 *
365 * data - for write accesses, contains the data to
366 * write.
367 *
368 * OUTPUTS:
369 * data - for read accesses, contains the value read.
370 *
371 * RETURNS: PCIBIOS_SUCCESSFUL - success
372 * -1 - access failure
373 *
374 ****************************************************************************/
375int msp_pcibios_config_access(unsigned char access_type,
376 struct pci_bus *bus,
377 unsigned int devfn,
378 unsigned char where,
379 u32 *data)
380{
381 struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
382 unsigned char bus_num = bus->number;
383 unsigned char dev_fn = (unsigned char)devfn;
384 unsigned long flags;
385 unsigned long intr;
386 unsigned long value;
387 static char pciirqflag;
388#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
389 unsigned int vpe_status;
390#endif
391
392#if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
393 if (proc_init == 0) {
394 pci_proc_init();
395 proc_init = ~0;
396 }
397#endif /* CONFIG_PROC_FS && PCI_COUNTERS */
398
399 /*
400 * Just the first time this function invokes, allocate
401 * an interrupt line for PCI host status interrupts. The
402 * allocation assigns an interrupt handler to the interrupt.
403 */
404 if (pciirqflag == 0) {
405 request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
406 bpci_interrupt,
407 SA_SHIRQ | SA_INTERRUPT,
408 "PMC MSP PCI Host",
409 preg);
410 pciirqflag = ~0;
411 }
412
413#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
414 local_irq_save(flags);
415 vpe_status = dvpe();
416#else
417 spin_lock_irqsave(&bpci_lock, flags);
418#endif
419
420 /*
421 * Clear PCI cause register bits.
422 *
423 * In Polo, the PCI Host had a dedicated DMA called the
424 * Block Copy (not to be confused with the general purpose Block
425 * Copy Engine block). There appear to have been special interrupts
426 * for this Block Copy, called Block Copy 0 Fault (BC0F) and
427 * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
428 * dedicated Block Copy block, so these two interrupts are now
429 * marked reserved. In case the Block Copy is resurrected in a
430 * future design, maintain the code that treats these two interrupts
431 * specially.
432 *
433 * Write to clear all interrupts in the PCI status register, aside
434 * from BC0F and BC1F.
435 */
436 preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
437
438 /* Setup address that is to appear on PCI bus */
439 preg->config_addr = BPCI_CFGADDR_ENABLE |
440 (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
441 (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
442 (where & 0xFC);
443
444 /* IF access is a PCI configuration write */
445 if (access_type == PCI_ACCESS_WRITE) {
446 value = cpu_to_le32(*data);
447 *PCI_CONFIG_SPACE_REG = value;
448 } else {
449 /* ELSE access is a PCI configuration read */
450 value = le32_to_cpu(*PCI_CONFIG_SPACE_REG);
451 *data = value;
452 }
453
454 /*
455 * Check if the PCI configuration cycle (rd or wr) succeeded, by
456 * checking the status bits for errors like master or target abort.
457 */
458 intr = preg->if_status;
459
460 /* Clear config access */
461 preg->config_addr = 0;
462
463 /* IF error occurred */
464 if (intr & ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F)) {
465 /* Clear status bits */
466 preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
467
468#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
469 evpe(vpe_status);
470 local_irq_restore(flags);
471#else
472 spin_unlock_irqrestore(&bpci_lock, flags);
473#endif
474
475 return -1;
476 }
477
478#if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
479 evpe(vpe_status);
480 local_irq_restore(flags);
481#else
482 spin_unlock_irqrestore(&bpci_lock, flags);
483#endif
484
485 return PCIBIOS_SUCCESSFUL;
486}
487
488/*****************************************************************************
489 *
490 * FUNCTION: msp_pcibios_read_config_byte
491 * _________________________________________________________________________
492 *
493 * DESCRIPTION: Read a byte from PCI configuration address spac
494 * Since the hardware can't address 8 bit chunks
495 * directly, read a 32-bit chunk, then mask off extraneous
496 * bits.
497 *
498 * INPUTS bus - structure containing attributes for the PCI bus
499 * that the read is destined for.
500 * devfn - device/function combination that the read is
501 * destined for.
502 * where - register within the Configuration Header space
503 * to access.
504 *
505 * OUTPUTS val - read data
506 *
507 * RETURNS: PCIBIOS_SUCCESSFUL - success
508 * -1 - read access failure
509 *
510 ****************************************************************************/
511static int
512msp_pcibios_read_config_byte(struct pci_bus *bus,
513 unsigned int devfn,
514 int where,
515 u32 *val)
516{
517 u32 data = 0;
518
519 /*
520 * If the config access did not complete normally (e.g., underwent
521 * master abort) do the PCI compliant thing, which is to supply an
522 * all ones value.
523 */
524 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
525 where, &data)) {
526 *val = 0xFFFFFFFF;
527 return -1;
528 }
529
530 *val = (data >> ((where & 3) << 3)) & 0x0ff;
531
532 return PCIBIOS_SUCCESSFUL;
533}
534
535/*****************************************************************************
536 *
537 * FUNCTION: msp_pcibios_read_config_word
538 * _________________________________________________________________________
539 *
540 * DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
541 * Since the hardware can't address 16 bit chunks
542 * directly, read a 32-bit chunk, then mask off extraneous
543 * bits.
544 *
545 * INPUTS bus - structure containing attributes for the PCI bus
546 * that the read is destined for.
547 * devfn - device/function combination that the read is
548 * destined for.
549 * where - register within the Configuration Header space
550 * to access.
551 *
552 * OUTPUTS val - read data
553 *
554 * RETURNS: PCIBIOS_SUCCESSFUL - success
555 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
556 * -1 - read access failure
557 *
558 ****************************************************************************/
559static int
560msp_pcibios_read_config_word(struct pci_bus *bus,
561 unsigned int devfn,
562 int where,
563 u32 *val)
564{
565 u32 data = 0;
566
567 /* if (where & 1) */ /* Commented out non-compliant code.
568 * Should allow word access to configuration
569 * registers, with only exception being when
570 * the word access would wrap around into
571 * the next dword.
572 */
573 if ((where & 3) == 3) {
574 *val = 0xFFFFFFFF;
575 return PCIBIOS_BAD_REGISTER_NUMBER;
576 }
577
578 /*
579 * If the config access did not complete normally (e.g., underwent
580 * master abort) do the PCI compliant thing, which is to supply an
581 * all ones value.
582 */
583 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
584 where, &data)) {
585 *val = 0xFFFFFFFF;
586 return -1;
587 }
588
589 *val = (data >> ((where & 3) << 3)) & 0x0ffff;
590
591 return PCIBIOS_SUCCESSFUL;
592}
593
594/*****************************************************************************
595 *
596 * FUNCTION: msp_pcibios_read_config_dword
597 * _________________________________________________________________________
598 *
599 * DESCRIPTION: Read a double word (32 bits) from PCI configuration
600 * address space.
601 *
602 * INPUTS bus - structure containing attributes for the PCI bus
603 * that the read is destined for.
604 * devfn - device/function combination that the read is
605 * destined for.
606 * where - register within the Configuration Header space
607 * to access.
608 *
609 * OUTPUTS val - read data
610 *
611 * RETURNS: PCIBIOS_SUCCESSFUL - success
612 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
613 * -1 - read access failure
614 *
615 ****************************************************************************/
616static int
617msp_pcibios_read_config_dword(struct pci_bus *bus,
618 unsigned int devfn,
619 int where,
620 u32 *val)
621{
622 u32 data = 0;
623
624 /* Address must be dword aligned. */
625 if (where & 3) {
626 *val = 0xFFFFFFFF;
627 return PCIBIOS_BAD_REGISTER_NUMBER;
628 }
629
630 /*
631 * If the config access did not complete normally (e.g., underwent
632 * master abort) do the PCI compliant thing, which is to supply an
633 * all ones value.
634 */
635 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
636 where, &data)) {
637 *val = 0xFFFFFFFF;
638 return -1;
639 }
640
641 *val = data;
642
643 return PCIBIOS_SUCCESSFUL;
644}
645
646/*****************************************************************************
647 *
648 * FUNCTION: msp_pcibios_write_config_byte
649 * _________________________________________________________________________
650 *
651 * DESCRIPTION: Write a byte to PCI configuration address space.
652 * Since the hardware can't address 8 bit chunks
653 * directly, a read-modify-write is performed.
654 *
655 * INPUTS bus - structure containing attributes for the PCI bus
656 * that the write is destined for.
657 * devfn - device/function combination that the write is
658 * destined for.
659 * where - register within the Configuration Header space
660 * to access.
661 * val - value to write
662 *
663 * OUTPUTS none
664 *
665 * RETURNS: PCIBIOS_SUCCESSFUL - success
666 * -1 - write access failure
667 *
668 ****************************************************************************/
669static int
670msp_pcibios_write_config_byte(struct pci_bus *bus,
671 unsigned int devfn,
672 int where,
673 u8 val)
674{
675 u32 data = 0;
676
677 /* read config space */
678 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
679 where, &data))
680 return -1;
681
682 /* modify the byte within the dword */
683 data = (data & ~(0xff << ((where & 3) << 3))) |
684 (val << ((where & 3) << 3));
685
686 /* write back the full dword */
687 if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
688 where, &data))
689 return -1;
690
691 return PCIBIOS_SUCCESSFUL;
692}
693
694/*****************************************************************************
695 *
696 * FUNCTION: msp_pcibios_write_config_word
697 * _________________________________________________________________________
698 *
699 * DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
700 * Since the hardware can't address 16 bit chunks
701 * directly, a read-modify-write is performed.
702 *
703 * INPUTS bus - structure containing attributes for the PCI bus
704 * that the write is destined for.
705 * devfn - device/function combination that the write is
706 * destined for.
707 * where - register within the Configuration Header space
708 * to access.
709 * val - value to write
710 *
711 * OUTPUTS none
712 *
713 * RETURNS: PCIBIOS_SUCCESSFUL - success
714 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
715 * -1 - write access failure
716 *
717 ****************************************************************************/
718static int
719msp_pcibios_write_config_word(struct pci_bus *bus,
720 unsigned int devfn,
721 int where,
722 u16 val)
723{
724 u32 data = 0;
725
726 /* Fixed non-compliance: if (where & 1) */
727 if ((where & 3) == 3)
728 return PCIBIOS_BAD_REGISTER_NUMBER;
729
730 /* read config space */
731 if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
732 where, &data))
733 return -1;
734
735 /* modify the word within the dword */
736 data = (data & ~(0xffff << ((where & 3) << 3))) |
737 (val << ((where & 3) << 3));
738
739 /* write back the full dword */
740 if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
741 where, &data))
742 return -1;
743
744 return PCIBIOS_SUCCESSFUL;
745}
746
747/*****************************************************************************
748 *
749 * FUNCTION: msp_pcibios_write_config_dword
750 * _________________________________________________________________________
751 *
752 * DESCRIPTION: Write a double word (32-bits) to PCI configuration address
753 * space.
754 *
755 * INPUTS bus - structure containing attributes for the PCI bus
756 * that the write is destined for.
757 * devfn - device/function combination that the write is
758 * destined for.
759 * where - register within the Configuration Header space
760 * to access.
761 * val - value to write
762 *
763 * OUTPUTS none
764 *
765 * RETURNS: PCIBIOS_SUCCESSFUL - success
766 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
767 * -1 - write access failure
768 *
769 ****************************************************************************/
770static int
771msp_pcibios_write_config_dword(struct pci_bus *bus,
772 unsigned int devfn,
773 int where,
774 u32 val)
775{
776 /* check that address is dword aligned */
777 if (where & 3)
778 return PCIBIOS_BAD_REGISTER_NUMBER;
779
780 /* perform write */
781 if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
782 where, &val))
783 return -1;
784
785 return PCIBIOS_SUCCESSFUL;
786}
787
788/*****************************************************************************
789 *
790 * FUNCTION: msp_pcibios_read_config
791 * _________________________________________________________________________
792 *
793 * DESCRIPTION: Interface the PCI configuration read request with
794 * the appropriate function, based on how many bytes
795 * the read request is.
796 *
797 * INPUTS bus - structure containing attributes for the PCI bus
798 * that the write is destined for.
799 * devfn - device/function combination that the write is
800 * destined for.
801 * where - register within the Configuration Header space
802 * to access.
803 * size - in units of bytes, should be 1, 2, or 4.
804 *
805 * OUTPUTS val - value read, with any extraneous bytes masked
806 * to zero.
807 *
808 * RETURNS: PCIBIOS_SUCCESSFUL - success
809 * -1 - failure
810 *
811 ****************************************************************************/
812int
813msp_pcibios_read_config(struct pci_bus *bus,
814 unsigned int devfn,
815 int where,
816 int size,
817 u32 *val)
818{
819 if (size == 1) {
820 if (msp_pcibios_read_config_byte(bus, devfn, where, val)) {
821 return -1;
822 }
823 } else if (size == 2) {
824 if (msp_pcibios_read_config_word(bus, devfn, where, val)) {
825 return -1;
826 }
827 } else if (size == 4) {
828 if (msp_pcibios_read_config_dword(bus, devfn, where, val)) {
829 return -1;
830 }
831 } else {
832 *val = 0xFFFFFFFF;
833 return -1;
834 }
835
836 return PCIBIOS_SUCCESSFUL;
837}
838
839/*****************************************************************************
840 *
841 * FUNCTION: msp_pcibios_write_config
842 * _________________________________________________________________________
843 *
844 * DESCRIPTION: Interface the PCI configuration write request with
845 * the appropriate function, based on how many bytes
846 * the read request is.
847 *
848 * INPUTS bus - structure containing attributes for the PCI bus
849 * that the write is destined for.
850 * devfn - device/function combination that the write is
851 * destined for.
852 * where - register within the Configuration Header space
853 * to access.
854 * size - in units of bytes, should be 1, 2, or 4.
855 * val - value to write
856 *
857 * OUTPUTS: none
858 *
859 * RETURNS: PCIBIOS_SUCCESSFUL - success
860 * -1 - failure
861 *
862 ****************************************************************************/
863int
864msp_pcibios_write_config(struct pci_bus *bus,
865 unsigned int devfn,
866 int where,
867 int size,
868 u32 val)
869{
870 if (size == 1) {
871 if (msp_pcibios_write_config_byte(bus, devfn,
872 where, (u8)(0xFF & val))) {
873 return -1;
874 }
875 } else if (size == 2) {
876 if (msp_pcibios_write_config_word(bus, devfn,
877 where, (u16)(0xFFFF & val))) {
878 return -1;
879 }
880 } else if (size == 4) {
881 if (msp_pcibios_write_config_dword(bus, devfn, where, val)) {
882 return -1;
883 }
884 } else {
885 return -1;
886 }
887
888 return PCIBIOS_SUCCESSFUL;
889}
890
891/*****************************************************************************
892 *
893 * STRUCTURE: msp_pci_ops
894 * _________________________________________________________________________
895 *
896 * DESCRIPTION: structure to abstract the hardware specific PCI
897 * configuration accesses.
898 *
899 * ELEMENTS:
900 * read - function for Linux to generate PCI Configuration reads.
901 * write - function for Linux to generate PCI Configuration writes.
902 *
903 ****************************************************************************/
904struct pci_ops msp_pci_ops = {
905 .read = msp_pcibios_read_config,
906 .write = msp_pcibios_write_config
907};
908
909/*****************************************************************************
910 *
911 * STRUCTURE: msp_pci_controller
912 * _________________________________________________________________________
913 *
914 * Describes the attributes of the MSP7120 PCI Host Controller
915 *
916 * ELEMENTS:
917 * pci_ops - abstracts the hardware specific PCI configuration
918 * accesses.
919 *
920 * mem_resource - address range pciauto() uses to assign to PCI device
921 * memory BARs.
922 *
923 * mem_offset - offset between how MSP7120 outbound PCI memory
924 * transaction addresses appear on the PCI bus and how Linux
925 * wants to configure memory BARs of the PCI devices.
926 * MSP7120 does nothing funky, so just set to zero.
927 *
928 * io_resource - address range pciauto() uses to assign to PCI device
929 * I/O BARs.
930 *
931 * io_offset - offset between how MSP7120 outbound PCI I/O
932 * transaction addresses appear on the PCI bus and how
933 * Linux defaults to configure I/O BARs of the PCI devices.
934 * MSP7120 maps outbound I/O accesses into the bottom
935 * bottom 4K of PCI address space (and ignores OATRAN).
936 * Since the Linux default is to configure I/O BARs to the
937 * bottom 4K, no special offset is needed. Just set to zero.
938 *
939 ****************************************************************************/
940static struct pci_controller msp_pci_controller = {
941 .pci_ops = &msp_pci_ops,
942 .mem_resource = &pci_mem_resource,
943 .mem_offset = 0,
944 .io_resource = &pci_io_resource,
945 .io_offset = 0
946};
947
948/*****************************************************************************
949 *
950 * FUNCTION: msp_pci_init
951 * _________________________________________________________________________
952 *
953 * DESCRIPTION: Initialize the PCI Host Controller and register it with
954 * Linux so Linux can seize control of the PCI bus.
955 *
956 ****************************************************************************/
957void __init msp_pci_init(void)
958{
959 struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
960 u32 id;
961
962 /* Extract Device ID */
963 id = read_reg32(PCI_JTAG_DEVID_REG, 0xFFFF) >> 12;
964
965 /* Check if JTAG ID identifies MSP7120 */
966 if (!MSP_HAS_PCI(id)) {
967 printk(KERN_WARNING "PCI: No PCI; id reads as %x\n", id);
968 goto no_pci;
969 }
970
971 /*
972 * Enable flushing of the PCI-SDRAM queue upon a read
973 * of the SDRAM's Memory Configuration Register.
974 */
975 *(unsigned long *)QFLUSH_REG_1 = 3;
976
977 /* Configure PCI Host Controller. */
978 preg->if_status = ~0; /* Clear cause register bits */
979 preg->config_addr = 0; /* Clear config access */
980 preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */
981 preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */
982
983 /* configure so inb(), outb(), and family are functional */
984 set_io_port_base(MSP_PCI_IOSPACE_BASE);
985
986 /* Tell Linux the details of the MSP7120 PCI Host Controller */
987 register_pci_controller(&msp_pci_controller);
988
989 return;
990
991no_pci:
992 /* Disable PCI channel */
993 printk(KERN_WARNING "PCI: no host PCI bus detected\n");
994}
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c
index 445007084515..a450c4062031 100644
--- a/arch/mips/pci/ops-tx4938.c
+++ b/arch/mips/pci/ops-tx4938.c
@@ -46,50 +46,63 @@ struct resource tx4938_pcic1_pci_mem_resource = {
46 .flags = IORESOURCE_MEM 46 .flags = IORESOURCE_MEM
47}; 47};
48 48
49static int mkaddr(int bus, int dev_fn, int where, int *flagsp) 49static int mkaddr(int bus, int dev_fn, int where,
50 struct tx4938_pcic_reg *pcicptr)
50{ 51{
51 if (bus > 0) { 52 if (bus > 0) {
52 /* Type 1 configuration */ 53 /* Type 1 configuration */
53 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | 54 pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
54 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; 55 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
55 } else { 56 } else {
56 if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0)) 57 if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
57 return -1; 58 return -1;
58 59
59 /* Type 0 configuration */ 60 /* Type 0 configuration */
60 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | 61 pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
61 ((dev_fn & 0xff) << 0x08) | (where & 0xfc); 62 ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
62 } 63 }
63 /* clear M_ABORT and Disable M_ABORT Int. */ 64 /* clear M_ABORT and Disable M_ABORT Int. */
64 tx4938_pcicptr->pcistatus = 65 pcicptr->pcistatus =
65 (tx4938_pcicptr->pcistatus & 0x0000ffff) | 66 (pcicptr->pcistatus & 0x0000ffff) |
66 (PCI_STATUS_REC_MASTER_ABORT << 16); 67 (PCI_STATUS_REC_MASTER_ABORT << 16);
67 tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; 68 pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
68 69
69 return 0; 70 return 0;
70} 71}
71 72
72static int check_abort(int flags) 73static int check_abort(struct tx4938_pcic_reg *pcicptr)
73{ 74{
74 int code = PCIBIOS_SUCCESSFUL; 75 int code = PCIBIOS_SUCCESSFUL;
75 /* wait write cycle completion before checking error status */ 76 /* wait write cycle completion before checking error status */
76 while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) 77 while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
77 ; 78 ;
78 if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { 79 if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
79 tx4938_pcicptr->pcistatus = 80 pcicptr->pcistatus =
80 (tx4938_pcicptr-> 81 (pcicptr->
81 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT 82 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
82 << 16); 83 << 16);
83 tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; 84 pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
84 code = PCIBIOS_DEVICE_NOT_FOUND; 85 code = PCIBIOS_DEVICE_NOT_FOUND;
85 } 86 }
86 return code; 87 return code;
87} 88}
88 89
90extern struct pci_controller tx4938_pci_controller[];
91extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch);
92
93static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus)
94{
95 struct pci_controller *channel = bus->sysdata;
96 return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]);
97}
98
89static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, 99static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
90 int where, int size, u32 * val) 100 int where, int size, u32 * val)
91{ 101{
92 int flags, retval, dev, busno, func; 102 int retval, dev, busno, func;
103 struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
104 void __iomem *cfgdata =
105 (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
93 106
94 dev = PCI_SLOT(devfn); 107 dev = PCI_SLOT(devfn);
95 func = PCI_FUNC(devfn); 108 func = PCI_FUNC(devfn);
@@ -101,32 +114,32 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
101 busno = 0; 114 busno = 0;
102 } 115 }
103 116
104 if (mkaddr(busno, devfn, where, &flags)) 117 if (mkaddr(busno, devfn, where, pcicptr))
105 return -1; 118 return -1;
106 119
107 switch (size) { 120 switch (size) {
108 case 1: 121 case 1:
109 *val = *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
110#ifdef __BIG_ENDIAN 122#ifdef __BIG_ENDIAN
111 ((where & 3) ^ 3)); 123 cfgdata += (where & 3) ^ 3;
112#else 124#else
113 (where & 3)); 125 cfgdata += where & 3;
114#endif 126#endif
127 *val = __raw_readb(cfgdata);
115 break; 128 break;
116 case 2: 129 case 2:
117 *val = *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
118#ifdef __BIG_ENDIAN 130#ifdef __BIG_ENDIAN
119 ((where & 3) ^ 2)); 131 cfgdata += (where & 2) ^ 2;
120#else 132#else
121 (where & 3)); 133 cfgdata += where & 2;
122#endif 134#endif
135 *val = __raw_readw(cfgdata);
123 break; 136 break;
124 case 4: 137 case 4:
125 *val = tx4938_pcicptr->g2pcfgdata; 138 *val = __raw_readl(cfgdata);
126 break; 139 break;
127 } 140 }
128 141
129 retval = check_abort(flags); 142 retval = check_abort(pcicptr);
130 if (retval == PCIBIOS_DEVICE_NOT_FOUND) 143 if (retval == PCIBIOS_DEVICE_NOT_FOUND)
131 *val = 0xffffffff; 144 *val = 0xffffffff;
132 145
@@ -136,7 +149,10 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
136static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, 149static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
137 int size, u32 val) 150 int size, u32 val)
138{ 151{
139 int flags, dev, busno, func; 152 int dev, busno, func;
153 struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
154 void __iomem *cfgdata =
155 (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
140 156
141 busno = bus->number; 157 busno = bus->number;
142 dev = PCI_SLOT(devfn); 158 dev = PCI_SLOT(devfn);
@@ -149,32 +165,32 @@ static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn,
149 busno = 0; 165 busno = 0;
150 } 166 }
151 167
152 if (mkaddr(busno, devfn, where, &flags)) 168 if (mkaddr(busno, devfn, where, pcicptr))
153 return -1; 169 return -1;
154 170
155 switch (size) { 171 switch (size) {
156 case 1: 172 case 1:
157 *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
158#ifdef __BIG_ENDIAN 173#ifdef __BIG_ENDIAN
159 ((where & 3) ^ 3)) = val; 174 cfgdata += (where & 3) ^ 3;
160#else 175#else
161 (where & 3)) = val; 176 cfgdata += where & 3;
162#endif 177#endif
178 __raw_writeb(val, cfgdata);
163 break; 179 break;
164 case 2: 180 case 2:
165 *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata |
166#ifdef __BIG_ENDIAN 181#ifdef __BIG_ENDIAN
167 ((where & 0x3) ^ 0x2)) = val; 182 cfgdata += (where & 2) ^ 2;
168#else 183#else
169 (where & 3)) = val; 184 cfgdata += where & 2;
170#endif 185#endif
186 __raw_writew(val, cfgdata);
171 break; 187 break;
172 case 4: 188 case 4:
173 tx4938_pcicptr->g2pcfgdata = val; 189 __raw_writel(val, cfgdata);
174 break; 190 break;
175 } 191 }
176 192
177 return check_abort(flags); 193 return check_abort(pcicptr);
178} 194}
179 195
180struct pci_ops tx4938_pci_ops = { 196struct pci_ops tx4938_pci_ops = {
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index d7b9e1349f6d..2b4e30c7d105 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -74,8 +74,9 @@ static inline void WRITECFG32(u32 addr, u32 data)
74 *(u32 *)(cfg_space + (addr & ~3)) = data; 74 *(u32 *)(cfg_space + (addr & ~3)) = data;
75} 75}
76 76
77int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 77int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
78{ 78{
79 This is b0rked.
79 return dev->irq; 80 return dev->irq;
80} 81}
81 82
diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c
index d071bc375b11..7363e1877842 100644
--- a/arch/mips/pci/pci-ddb5477.c
+++ b/arch/mips/pci/pci-ddb5477.c
@@ -131,7 +131,7 @@ static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
131 /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ 131 /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
132}; 132};
133 133
134int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 134int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
135{ 135{
136 int slot_num; 136 int slot_num;
137 unsigned char *slot_irq_map; 137 unsigned char *slot_irq_map;
diff --git a/arch/mips/pci/pci-ev64120.c b/arch/mips/pci/pci-ev64120.c
deleted file mode 100644
index a84f594b5a18..000000000000
--- a/arch/mips/pci/pci-ev64120.c
+++ /dev/null
@@ -1,22 +0,0 @@
1#include <linux/pci.h>
2#include <asm/irq.h>
3
4int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
5{
6 int irq;
7
8 if (!pin)
9 return 0;
10
11 irq = allocate_irqno();
12 if (irq < 0)
13 return 0;
14
15 return irq;
16}
17
18/* Do platform specific device initialization at pci_enable_device() time */
19int pcibios_plat_dev_init(struct pci_dev *dev)
20{
21 return 0;
22}
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 405ce0152739..a322543ac34e 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -134,7 +134,7 @@ int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
134 * A given PCI device, in general, should be able to intr any of the cpus 134 * A given PCI device, in general, should be able to intr any of the cpus
135 * on any one of the hubs connected to its xbow. 135 * on any one of the hubs connected to its xbow.
136 */ 136 */
137int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 137int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
138{ 138{
139 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 139 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
140 int irq = bc->pci_int[slot]; 140 int irq = bc->pci_int[slot];
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
deleted file mode 100644
index 985784a3e6f8..000000000000
--- a/arch/mips/pci/pci-lasat.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 2001, 04 Keith M Wesolowski
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/types.h>
12#include <asm/bootinfo.h>
13
14extern struct pci_ops nile4_pci_ops;
15extern struct pci_ops gt64xxx_pci0_ops;
16static struct resource lasat_pci_mem_resource = {
17 .name = "LASAT PCI MEM",
18 .start = 0x18000000,
19 .end = 0x19ffffff,
20 .flags = IORESOURCE_MEM,
21};
22
23static struct resource lasat_pci_io_resource = {
24 .name = "LASAT PCI IO",
25 .start = 0x1a000000,
26 .end = 0x1bffffff,
27 .flags = IORESOURCE_IO,
28};
29
30static struct pci_controller lasat_pci_controller = {
31 .mem_resource = &lasat_pci_mem_resource,
32 .io_resource = &lasat_pci_io_resource,
33};
34
35static int __init lasat_pci_setup(void)
36{
37 printk("PCI: starting\n");
38
39 switch (mips_machtype) {
40 case MACH_LASAT_100:
41 lasat_pci_controller.pci_ops = &gt64xxx_pci0_ops;
42 break;
43 case MACH_LASAT_200:
44 lasat_pci_controller.pci_ops = &nile4_pci_ops;
45 break;
46 default:
47 panic("pcibios_init: mips_machtype incorrect");
48 }
49
50 register_pci_controller(&lasat_pci_controller);
51
52 return 0;
53}
54
55arch_initcall(lasat_pci_setup);
56
57#define LASATINT_ETH1 0
58#define LASATINT_ETH0 1
59#define LASATINT_HDC 2
60#define LASATINT_COMP 3
61#define LASATINT_HDLC 4
62#define LASATINT_PCIA 5
63#define LASATINT_PCIB 6
64#define LASATINT_PCIC 7
65#define LASATINT_PCID 8
66
67int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
68{
69 switch (slot) {
70 case 1:
71 case 2:
72 case 3:
73 return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4);
74 case 4:
75 return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
76 case 5:
77 return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
78 case 6:
79 return LASATINT_HDC; /* IDE controller */
80 default:
81 return 0xff; /* Illegal */
82 }
83
84 return -1;
85}
86
87/* Do platform specific device initialization at pci_enable_device() time */
88int pcibios_plat_dev_init(struct pci_dev *dev)
89{
90 return 0;
91}
diff --git a/arch/mips/pci/pci-ocelot-c.c b/arch/mips/pci/pci-ocelot-c.c
deleted file mode 100644
index 027759f7c904..000000000000
--- a/arch/mips/pci/pci-ocelot-c.c
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org)
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/mv643xx.h>
12
13#include <linux/init.h>
14
15#include <asm/marvell.h>
16
17/*
18 * We assume the address ranges have already been setup appropriately by
19 * the firmware. PMON in case of the Ocelot C does that.
20 */
21static struct resource mv_pci_io_mem0_resource = {
22 .name = "MV64340 PCI0 IO MEM",
23 .flags = IORESOURCE_IO
24};
25
26static struct resource mv_pci_mem0_resource = {
27 .name = "MV64340 PCI0 MEM",
28 .flags = IORESOURCE_MEM
29};
30
31static struct mv_pci_controller mv_bus0_controller = {
32 .pcic = {
33 .pci_ops = &mv_pci_ops,
34 .mem_resource = &mv_pci_mem0_resource,
35 .io_resource = &mv_pci_io_mem0_resource,
36 },
37 .config_addr = MV64340_PCI_0_CONFIG_ADDR,
38 .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
39};
40
41static uint32_t mv_io_base, mv_io_size;
42
43static void mv64340_pci0_init(void)
44{
45 uint32_t mem0_base, mem0_size;
46 uint32_t io_base, io_size;
47
48 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
49 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
50 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
51 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
52
53 mv_pci_io_mem0_resource.start = 0;
54 mv_pci_io_mem0_resource.end = io_size - 1;
55 mv_pci_mem0_resource.start = mem0_base;
56 mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
57 mv_bus0_controller.pcic.mem_offset = mem0_base;
58 mv_bus0_controller.pcic.io_offset = 0;
59
60 ioport_resource.end = io_size - 1;
61
62 register_pci_controller(&mv_bus0_controller.pcic);
63
64 mv_io_base = io_base;
65 mv_io_size = io_size;
66}
67
68static struct resource mv_pci_io_mem1_resource = {
69 .name = "MV64340 PCI1 IO MEM",
70 .flags = IORESOURCE_IO
71};
72
73static struct resource mv_pci_mem1_resource = {
74 .name = "MV64340 PCI1 MEM",
75 .flags = IORESOURCE_MEM
76};
77
78static struct mv_pci_controller mv_bus1_controller = {
79 .pcic = {
80 .pci_ops = &mv_pci_ops,
81 .mem_resource = &mv_pci_mem1_resource,
82 .io_resource = &mv_pci_io_mem1_resource,
83 },
84 .config_addr = MV64340_PCI_1_CONFIG_ADDR,
85 .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
86};
87
88static __init void mv64340_pci1_init(void)
89{
90 uint32_t mem0_base, mem0_size;
91 uint32_t io_base, io_size;
92
93 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
94 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
95 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
96 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
97
98 /*
99 * Here we assume the I/O window of second bus to be contiguous with
100 * the first. A gap is no problem but would waste address space for
101 * remapping the port space.
102 */
103 mv_pci_io_mem1_resource.start = mv_io_size;
104 mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
105 mv_pci_mem1_resource.start = mem0_base;
106 mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
107 mv_bus1_controller.pcic.mem_offset = mem0_base;
108 mv_bus1_controller.pcic.io_offset = 0;
109
110 ioport_resource.end = io_base + io_size -mv_io_base - 1;
111
112 register_pci_controller(&mv_bus1_controller.pcic);
113
114 mv_io_size = io_base + io_size - mv_io_base;
115}
116
117static __init int __init ocelot_c_pci_init(void)
118{
119 unsigned long io_v_base;
120 uint32_t enable;
121
122 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
123
124 /*
125 * We require at least one enabled I/O or PCI memory window or we
126 * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
127 */
128 if (enable & (0x01 << 9) || enable & (0x01 << 10))
129 mv64340_pci0_init();
130
131 if (enable & (0x01 << 14) || enable & (0x01 << 15))
132 mv64340_pci1_init();
133
134 if (mv_io_size) {
135 io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
136 if (!io_v_base)
137 panic("Could not ioremap I/O port range");
138
139 set_io_port_base(io_v_base);
140 }
141
142 return 0;
143}
144
145arch_initcall(ocelot_c_pci_init);
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 75c1246ced5f..c1ac6493155e 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -84,7 +84,7 @@ static inline void WRITECFG32(u32 addr, u32 data)
84 *(u32 *) (cfg_space + (addr & ~3)) = data; 84 *(u32 *) (cfg_space + (addr & ~3)) = data;
85} 85}
86 86
87int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 87int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
88{ 88{
89 return dev->irq; 89 return dev->irq;
90} 90}
diff --git a/arch/mips/philips/pnx8550/common/platform.c b/arch/mips/philips/pnx8550/common/platform.c
index d43f56e2cd78..c839436bd012 100644
--- a/arch/mips/philips/pnx8550/common/platform.c
+++ b/arch/mips/philips/pnx8550/common/platform.c
@@ -123,7 +123,7 @@ static struct platform_device *pnx8550_platform_devices[] __initdata = {
123 &pnx8550_uart_device, 123 &pnx8550_uart_device,
124}; 124};
125 125
126int pnx8550_platform_init(void) 126static int __init pnx8550_platform_init(void)
127{ 127{
128 return platform_add_devices(pnx8550_platform_devices, 128 return platform_add_devices(pnx8550_platform_devices,
129 ARRAY_SIZE(pnx8550_platform_devices)); 129 ARRAY_SIZE(pnx8550_platform_devices));
diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c
index 3f097558ef13..92311e95b700 100644
--- a/arch/mips/philips/pnx8550/common/proc.c
+++ b/arch/mips/philips/pnx8550/common/proc.c
@@ -78,29 +78,33 @@ static int pnx8550_proc_init( void )
78{ 78{
79 79
80 // Create /proc/pnx8550 80 // Create /proc/pnx8550
81 pnx8550_dir = create_proc_entry("pnx8550", S_IFDIR|S_IRUGO, NULL); 81 pnx8550_dir = proc_mkdir("pnx8550", NULL);
82 if (!pnx8550_dir) { 82 if (!pnx8550_dir) {
83 printk(KERN_ERR "Can't create pnx8550 proc dir\n"); 83 printk(KERN_ERR "Can't create pnx8550 proc dir\n");
84 return -1; 84 return -1;
85 } 85 }
86 86
87 // Create /proc/pnx8550/timers 87 // Create /proc/pnx8550/timers
88 pnx8550_timers = create_proc_entry("timers", S_IFREG|S_IRUGO, pnx8550_dir ); 88 pnx8550_timers = create_proc_read_entry(
89 if (pnx8550_timers){ 89 "timers",
90 pnx8550_timers->read_proc = pnx8550_timers_read; 90 0,
91 } 91 pnx8550_dir,
92 else { 92 pnx8550_timers_read,
93 NULL);
94
95 if (!pnx8550_timers)
93 printk(KERN_ERR "Can't create pnx8550 timers proc file\n"); 96 printk(KERN_ERR "Can't create pnx8550 timers proc file\n");
94 }
95 97
96 // Create /proc/pnx8550/registers 98 // Create /proc/pnx8550/registers
97 pnx8550_registers = create_proc_entry("registers", S_IFREG|S_IRUGO, pnx8550_dir ); 99 pnx8550_registers = create_proc_read_entry(
98 if (pnx8550_registers){ 100 "registers",
99 pnx8550_registers->read_proc = pnx8550_registers_read; 101 0,
100 } 102 pnx8550_dir,
101 else { 103 pnx8550_registers_read,
104 NULL);
105
106 if (!pnx8550_registers)
102 printk(KERN_ERR "Can't create pnx8550 registers proc file\n"); 107 printk(KERN_ERR "Can't create pnx8550 registers proc file\n");
103 }
104 108
105 return 0; 109 return 0;
106} 110}
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
index 24d514c9dff9..abbd0bbfabd7 100644
--- a/arch/mips/pmc-sierra/Kconfig
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -1,3 +1,49 @@
1choice
2 prompt "PMC-Sierra MSP SOC type"
3 depends on PMC_MSP
4
5config PMC_MSP4200_EVAL
6 bool "PMC-Sierra MSP4200 Eval Board"
7 select IRQ_MSP_SLP
8 select HW_HAS_PCI
9
10config PMC_MSP4200_GW
11 bool "PMC-Sierra MSP4200 VoIP Gateway"
12 select IRQ_MSP_SLP
13 select HW_HAS_PCI
14
15config PMC_MSP7120_EVAL
16 bool "PMC-Sierra MSP7120 Eval Board"
17 select SYS_SUPPORTS_MULTITHREADING
18 select IRQ_MSP_CIC
19 select HW_HAS_PCI
20
21config PMC_MSP7120_GW
22 bool "PMC-Sierra MSP7120 Residential Gateway"
23 select SYS_SUPPORTS_MULTITHREADING
24 select IRQ_MSP_CIC
25 select HW_HAS_PCI
26
27config PMC_MSP7120_FPGA
28 bool "PMC-Sierra MSP7120 FPGA"
29 select SYS_SUPPORTS_MULTITHREADING
30 select IRQ_MSP_CIC
31 select HW_HAS_PCI
32
33endchoice
34
35menu "Options for PMC-Sierra MSP chipsets"
36 depends on PMC_MSP
37
38config PMC_MSP_EMBEDDED_ROOTFS
39 bool "Root filesystem embedded in kernel image"
40 select MTD
41 select MTD_BLOCK
42 select MTD_PMC_MSP_RAMROOT
43 select MTD_RAM
44
45endmenu
46
1config HYPERTRANSPORT 47config HYPERTRANSPORT
2 bool "Hypertransport Support for PMC-Sierra Yosemite" 48 bool "Hypertransport Support for PMC-Sierra Yosemite"
3 depends on PMC_YOSEMITE 49 depends on PMC_YOSEMITE
diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile
new file mode 100644
index 000000000000..4bba79c1cc79
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the PMC-Sierra MSP SOCs
3#
4obj-y += msp_prom.o msp_setup.o msp_irq.o \
5 msp_time.o msp_serial.o msp_elb.o
6obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
7obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
8obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o
9obj-$(CONFIG_PCI) += msp_pci.o
10obj-$(CONFIG_MSPETH) += msp_eth.o
11obj-$(CONFIG_USB_MSP71XX) += msp_usb.o
diff --git a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h b/arch/mips/pmc-sierra/msp71xx/msp_elb.c
index f0f5581dcb50..3e9641007216 100644
--- a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
+++ b/arch/mips/pmc-sierra/msp71xx/msp_elb.c
@@ -1,7 +1,9 @@
1/* 1/*
2 * Ocelot-C Board Register Definitions 2 * Sets up the proper Chip Select configuration registers. It is assumed that
3 * PMON sets up the ADDR and MASK registers properly.
3 * 4 *
4 * (C) 2002 Momentum Computer Inc. 5 * Copyright 2005-2006 PMC-Sierra, Inc.
6 * Author: Marc St-Jean, Marc_St-Jean@pmc-sierra.com
5 * 7 *
6 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -22,40 +24,23 @@
22 * You should have received a copy of the GNU General Public License along 24 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc., 25 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Louis Hamilton, Red Hat, Inc.
27 * hamilton@redhat.com [MIPS64 modifications]
28 */ 27 */
29 28
30#ifndef __OCELOT_C_FPGA_H__ 29#include <linux/kernel.h>
31#define __OCELOT_C_FPGA_H__ 30#include <linux/init.h>
32 31#include <msp_regs.h>
33 32
34#ifdef CONFIG_64BIT 33static int __init msp_elb_setup(void)
35#define OCELOT_C_CS0_ADDR (0xfffffffffc000000) 34{
36#else 35#if defined(CONFIG_PMC_MSP7120_GW) \
37#define OCELOT_C_CS0_ADDR (0xfc000000) 36 || defined(CONFIG_PMC_MSP7120_EVAL)
37 /*
38 * Force all CNFG to be identical and equal to CS0,
39 * according to OPS doc
40 */
41 *CS1_CNFG_REG = *CS2_CNFG_REG = *CS3_CNFG_REG = *CS0_CNFG_REG;
38#endif 42#endif
43 return 0;
44}
39 45
40#define OCELOT_C_REG_BOARDREV 0x0 46subsys_initcall(msp_elb_setup);
41#define OCELOT_C_REG_FPGA_REV 0x1
42#define OCELOT_C_REG_FPGA_TYPE 0x2
43#define OCELOT_C_REG_RESET_STATUS 0x3
44#define OCELOT_C_REG_BOARD_STATUS 0x4
45#define OCELOT_C_REG_CPCI_ID 0x5
46#define OCELOT_C_REG_SET 0x6
47#define OCELOT_C_REG_CLR 0x7
48#define OCELOT_C_REG_EEPROM_MODE 0x9
49#define OCELOT_C_REG_INTMASK 0xa
50#define OCELOT_C_REG_INTSTAT 0xb
51#define OCELOT_C_REG_UART_INTMASK 0xc
52#define OCELOT_C_REG_UART_INTSTAT 0xd
53#define OCELOT_C_REG_INTSET 0xe
54#define OCELOT_C_REG_INTCLR 0xf
55
56#define __FPGA_REG_TO_ADDR(reg) \
57 ((void *) OCELOT_C_CS0_ADDR + OCELOT_C_REG_##reg)
58#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
59#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
60
61#endif
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
new file mode 100644
index 000000000000..6fa85728158b
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -0,0 +1,179 @@
1/*
2 * Sets up interrupt handlers for various hardware switches which are
3 * connected to interrupt lines.
4 *
5 * Copyright 2005-2207 PMC-Sierra, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/kernel.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31
32#include <msp_int.h>
33#include <msp_regs.h>
34#include <msp_regops.h>
35#ifdef CONFIG_PMCTWILED
36#include <msp_led_macros.h>
37#endif
38
39/* For hwbutton_interrupt->initial_state */
40#define HWBUTTON_HI 0x1
41#define HWBUTTON_LO 0x2
42
43/*
44 * This struct describes a hardware button
45 */
46struct hwbutton_interrupt {
47 char *name; /* Name of button */
48 int irq; /* Actual LINUX IRQ */
49 int eirq; /* Extended IRQ number (0-7) */
50 int initial_state; /* The "normal" state of the switch */
51 void (*handle_hi)(void *); /* Handler: switch input has gone HI */
52 void (*handle_lo)(void *); /* Handler: switch input has gone LO */
53 void *data; /* Optional data to pass to handler */
54};
55
56#ifdef CONFIG_PMC_MSP7120_GW
57extern void msp_restart(char *);
58
59static void softreset_push(void *data)
60{
61 printk(KERN_WARNING "SOFTRESET switch was pushed\n");
62
63 /*
64 * In the future you could move this to the release handler,
65 * timing the difference between the 'push' and 'release', and only
66 * doing this ungraceful restart if the button has been down for
67 * a certain amount of time; otherwise doing a graceful restart.
68 */
69
70 msp_restart(NULL);
71}
72
73static void softreset_release(void *data)
74{
75 printk(KERN_WARNING "SOFTRESET switch was released\n");
76
77 /* Do nothing */
78}
79
80static void standby_on(void *data)
81{
82 printk(KERN_WARNING "STANDBY switch was set to ON (not implemented)\n");
83
84 /* TODO: Put board in standby mode */
85#ifdef CONFIG_PMCTWILED
86 msp_led_turn_off(MSP_LED_PWRSTANDBY_GREEN);
87 msp_led_turn_on(MSP_LED_PWRSTANDBY_RED);
88#endif
89}
90
91static void standby_off(void *data)
92{
93 printk(KERN_WARNING
94 "STANDBY switch was set to OFF (not implemented)\n");
95
96 /* TODO: Take out of standby mode */
97#ifdef CONFIG_PMCTWILED
98 msp_led_turn_on(MSP_LED_PWRSTANDBY_GREEN);
99 msp_led_turn_off(MSP_LED_PWRSTANDBY_RED);
100#endif
101}
102
103static struct hwbutton_interrupt softreset_sw = {
104 .name = "Softreset button",
105 .irq = MSP_INT_EXT0,
106 .eirq = 0,
107 .initial_state = HWBUTTON_HI,
108 .handle_hi = softreset_release,
109 .handle_lo = softreset_push,
110 .data = NULL,
111};
112
113static struct hwbutton_interrupt standby_sw = {
114 .name = "Standby switch",
115 .irq = MSP_INT_EXT1,
116 .eirq = 1,
117 .initial_state = HWBUTTON_HI,
118 .handle_hi = standby_off,
119 .handle_lo = standby_on,
120 .data = NULL,
121};
122#endif /* CONFIG_PMC_MSP7120_GW */
123
124static irqreturn_t hwbutton_handler(int irq, void *data)
125{
126 struct hwbutton_interrupt *hirq = data;
127 unsigned long cic_ext = *CIC_EXT_CFG_REG;
128
129 if (irq != hirq->irq)
130 return IRQ_NONE;
131
132 if (CIC_EXT_IS_ACTIVE_HI(cic_ext, hirq->eirq)) {
133 /* Interrupt: pin is now HI */
134 CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
135 hirq->handle_hi(hirq->data);
136 } else {
137 /* Interrupt: pin is now LO */
138 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
139 hirq->handle_lo(hirq->data);
140 }
141
142 /*
143 * Invert the POLARITY of this level interrupt to ack the interrupt
144 * Thus next state change will invoke the opposite message
145 */
146 *CIC_EXT_CFG_REG = cic_ext;
147
148 return IRQ_HANDLED;
149}
150
151static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
152{
153 unsigned long cic_ext;
154
155 if (hirq->handle_hi == NULL || hirq->handle_lo == NULL)
156 return -EINVAL;
157
158 cic_ext = *CIC_EXT_CFG_REG;
159 CIC_EXT_SET_TRIGGER_LEVEL(cic_ext, hirq->eirq);
160 if (hirq->initial_state == HWBUTTON_HI)
161 CIC_EXT_SET_ACTIVE_LO(cic_ext, hirq->eirq);
162 else
163 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
164 *CIC_EXT_CFG_REG = cic_ext;
165
166 return request_irq(hirq->irq, hwbutton_handler, SA_INTERRUPT,
167 hirq->name, (void *)hirq);
168}
169
170static int __init msp_hwbutton_setup(void)
171{
172#ifdef CONFIG_PMC_MSP7120_GW
173 msp_hwbutton_register(&softreset_sw);
174 msp_hwbutton_register(&standby_sw);
175#endif
176 return 0;
177}
178
179subsys_initcall(msp_hwbutton_setup);
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
new file mode 100644
index 000000000000..734d598a2e3a
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
@@ -0,0 +1,124 @@
1/*
2 * IRQ vector handles
3 *
4 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/ptrace.h>
16#include <linux/time.h>
17
18#include <asm/irq_cpu.h>
19
20#include <msp_int.h>
21
22extern void msp_int_handle(void);
23
24/* SLP bases systems */
25extern void msp_slp_irq_init(void);
26extern void msp_slp_irq_dispatch(void);
27
28/* CIC based systems */
29extern void msp_cic_irq_init(void);
30extern void msp_cic_irq_dispatch(void);
31
32/*
33 * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
34 * hierarchical system. The first level are the direct MIPS interrupts
35 * and are assigned the interrupt range 0-7. The second level is the SLM
36 * interrupt controller and is assigned the range 8-39. The third level
37 * comprises the Peripherial block, the PCI block, the PCI MSI block and
38 * the SLP. The PCI interrupts and the SLP errors are handled by the
39 * relevant subsystems so the core interrupt code needs only concern
40 * itself with the Peripheral block. These are assigned interrupts in
41 * the range 40-71.
42 */
43
44asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
45{
46 u32 pending;
47
48 pending = read_c0_status() & read_c0_cause();
49
50 /*
51 * jump to the correct interrupt routine
52 * These are arranged in priority order and the timer
53 * comes first!
54 */
55
56#ifdef CONFIG_IRQ_MSP_CIC /* break out the CIC stuff for now */
57 if (pending & C_IRQ4) /* do the peripherals first, that's the timer */
58 msp_cic_irq_dispatch();
59
60 else if (pending & C_IRQ0)
61 do_IRQ(MSP_INT_MAC0);
62
63 else if (pending & C_IRQ1)
64 do_IRQ(MSP_INT_MAC1);
65
66 else if (pending & C_IRQ2)
67 do_IRQ(MSP_INT_USB);
68
69 else if (pending & C_IRQ3)
70 do_IRQ(MSP_INT_SAR);
71
72 else if (pending & C_IRQ5)
73 do_IRQ(MSP_INT_SEC);
74
75#else
76 if (pending & C_IRQ5)
77 do_IRQ(MSP_INT_TIMER);
78
79 else if (pending & C_IRQ0)
80 do_IRQ(MSP_INT_MAC0);
81
82 else if (pending & C_IRQ1)
83 do_IRQ(MSP_INT_MAC1);
84
85 else if (pending & C_IRQ3)
86 do_IRQ(MSP_INT_VE);
87
88 else if (pending & C_IRQ4)
89 msp_slp_irq_dispatch();
90#endif
91
92 else if (pending & C_SW0) /* do software after hardware */
93 do_IRQ(MSP_INT_SW0);
94
95 else if (pending & C_SW1)
96 do_IRQ(MSP_INT_SW1);
97}
98
99static struct irqaction cascade_msp = {
100 .handler = no_action,
101 .name = "MSP cascade"
102};
103
104
105void __init arch_init_irq(void)
106{
107 /* initialize the 1st-level CPU based interrupt controller */
108 mips_cpu_irq_init();
109
110#ifdef CONFIG_IRQ_MSP_CIC
111 msp_cic_irq_init();
112
113 /* setup the cascaded interrupts */
114 setup_irq(MSP_INT_CIC, &cascade_msp);
115 setup_irq(MSP_INT_PER, &cascade_msp);
116#else
117 /* setup the 2nd-level SLP register based interrupt controller */
118 msp_slp_irq_init();
119
120 /* setup the cascaded SLP/PER interrupts */
121 setup_irq(MSP_INT_SLP, &cascade_msp);
122 setup_irq(MSP_INT_PER, &cascade_msp);
123#endif
124}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
new file mode 100644
index 000000000000..5175357d0a25
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
@@ -0,0 +1,134 @@
1/*
2 * This file define the irq handler for MSP SLM subsystem interrupts.
3 *
4 * Copyright 2005-2007 PMC-Sierra, Inc, derived from irq_cpu.c
5 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/bitops.h>
17
18#include <asm/system.h>
19
20#include <msp_cic_int.h>
21#include <msp_regs.h>
22
23/*
24 * NOTE: We are only enabling support for VPE0 right now.
25 */
26
27static inline void unmask_msp_cic_irq(unsigned int irq)
28{
29
30 /* check for PER interrupt range */
31 if (irq < MSP_PER_INTBASE)
32 *CIC_VPE0_MSK_REG |= (1 << (irq - MSP_CIC_INTBASE));
33 else
34 *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
35}
36
37static inline void mask_msp_cic_irq(unsigned int irq)
38{
39 /* check for PER interrupt range */
40 if (irq < MSP_PER_INTBASE)
41 *CIC_VPE0_MSK_REG &= ~(1 << (irq - MSP_CIC_INTBASE));
42 else
43 *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
44}
45
46/*
47 * While we ack the interrupt interrupts are disabled and thus we don't need
48 * to deal with concurrency issues. Same for msp_cic_irq_end.
49 */
50static inline void ack_msp_cic_irq(unsigned int irq)
51{
52 mask_msp_cic_irq(irq);
53
54 /*
55 * only really necessary for 18, 16-14 and sometimes 3:0 (since
56 * these can be edge sensitive) but it doesn't hurt for the others.
57 */
58
59 /* check for PER interrupt range */
60 if (irq < MSP_PER_INTBASE)
61 *CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE));
62 else
63 *PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
64}
65
66static struct irq_chip msp_cic_irq_controller = {
67 .name = "MSP_CIC",
68 .ack = ack_msp_cic_irq,
69 .mask = ack_msp_cic_irq,
70 .mask_ack = ack_msp_cic_irq,
71 .unmask = unmask_msp_cic_irq,
72};
73
74
75void __init msp_cic_irq_init(void)
76{
77 int i;
78
79 /* Mask/clear interrupts. */
80 *CIC_VPE0_MSK_REG = 0x00000000;
81 *PER_INT_MSK_REG = 0x00000000;
82 *CIC_STS_REG = 0xFFFFFFFF;
83 *PER_INT_STS_REG = 0xFFFFFFFF;
84
85#if defined(CONFIG_PMC_MSP7120_GW) || \
86 defined(CONFIG_PMC_MSP7120_EVAL)
87 /*
88 * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
89 * These inputs map to EXT_INT_POL[6:4] inside the CIC.
90 * They are to be active low, level sensitive.
91 */
92 *CIC_EXT_CFG_REG &= 0xFFFF8F8F;
93#endif
94
95 /* initialize all the IRQ descriptors */
96 for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++)
97 set_irq_chip_and_handler(i, &msp_cic_irq_controller,
98 handle_level_irq);
99}
100
101void msp_cic_irq_dispatch(void)
102{
103 u32 pending;
104 int intbase;
105
106 intbase = MSP_CIC_INTBASE;
107 pending = *CIC_STS_REG & *CIC_VPE0_MSK_REG;
108
109 /* check for PER interrupt */
110 if (pending == (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
111 intbase = MSP_PER_INTBASE;
112 pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
113 }
114
115 /* check for spurious interrupt */
116 if (pending == 0x00000000) {
117 printk(KERN_ERR
118 "Spurious %s interrupt? status %08x, mask %08x\n",
119 (intbase == MSP_CIC_INTBASE) ? "CIC" : "PER",
120 (intbase == MSP_CIC_INTBASE) ?
121 *CIC_STS_REG : *PER_INT_STS_REG,
122 (intbase == MSP_CIC_INTBASE) ?
123 *CIC_VPE0_MSK_REG : *PER_INT_MSK_REG);
124 return;
125 }
126
127 /* check for the timer and dispatch it first */
128 if ((intbase == MSP_CIC_INTBASE) &&
129 (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))))
130 do_IRQ(MSP_INT_VPE0_TIMER);
131 else
132 do_IRQ(ffs(pending) + intbase - 1);
133}
134
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
new file mode 100644
index 000000000000..f5f1b8d2bb9a
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
@@ -0,0 +1,109 @@
1/*
2 * This file define the irq handler for MSP SLM subsystem interrupts.
3 *
4 * Copyright 2005-2006 PMC-Sierra, Inc, derived from irq_cpu.c
5 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/bitops.h>
17
18#include <asm/mipsregs.h>
19#include <asm/system.h>
20
21#include <msp_slp_int.h>
22#include <msp_regs.h>
23
24static inline void unmask_msp_slp_irq(unsigned int irq)
25{
26 /* check for PER interrupt range */
27 if (irq < MSP_PER_INTBASE)
28 *SLP_INT_MSK_REG |= (1 << (irq - MSP_SLP_INTBASE));
29 else
30 *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
31}
32
33static inline void mask_msp_slp_irq(unsigned int irq)
34{
35 /* check for PER interrupt range */
36 if (irq < MSP_PER_INTBASE)
37 *SLP_INT_MSK_REG &= ~(1 << (irq - MSP_SLP_INTBASE));
38 else
39 *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
40}
41
42/*
43 * While we ack the interrupt interrupts are disabled and thus we don't need
44 * to deal with concurrency issues. Same for msp_slp_irq_end.
45 */
46static inline void ack_msp_slp_irq(unsigned int irq)
47{
48 mask_slp_irq(irq);
49
50 /*
51 * only really necessary for 18, 16-14 and sometimes 3:0 (since
52 * these can be edge sensitive) but it doesn't hurt for the others.
53 */
54
55 /* check for PER interrupt range */
56 if (irq < MSP_PER_INTBASE)
57 *SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE));
58 else
59 *PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
60}
61
62static struct irq_chip msp_slp_irq_controller = {
63 .name = "MSP_SLP",
64 .ack = ack_msp_slp_irq,
65 .mask = ack_msp_slp_irq,
66 .mask_ack = ack_msp_slp_irq,
67 .unmask = unmask_msp_slp_irq,
68};
69
70void __init msp_slp_irq_init(void)
71{
72 int i;
73
74 /* Mask/clear interrupts. */
75 *SLP_INT_MSK_REG = 0x00000000;
76 *PER_INT_MSK_REG = 0x00000000;
77 *SLP_INT_STS_REG = 0xFFFFFFFF;
78 *PER_INT_STS_REG = 0xFFFFFFFF;
79
80 /* initialize all the IRQ descriptors */
81 for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++)
82 set_irq_chip_and_handler(i, &msp_slp_irq_controller
83 handle_level_irq);
84}
85
86void msp_slp_irq_dispatch(void)
87{
88 u32 pending;
89 int intbase;
90
91 intbase = MSP_SLP_INTBASE;
92 pending = *SLP_INT_STS_REG & *SLP_INT_MSK_REG;
93
94 /* check for PER interrupt */
95 if (pending == (1 << (MSP_INT_PER - MSP_SLP_INTBASE))) {
96 intbase = MSP_PER_INTBASE;
97 pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
98 }
99
100 /* check for spurious interrupt */
101 if (pending == 0x00000000) {
102 printk(KERN_ERR "Spurious %s interrupt?\n",
103 (intbase == MSP_SLP_INTBASE) ? "SLP" : "PER");
104 return;
105 }
106
107 /* dispatch the irq */
108 do_IRQ(ffs(pending) + intbase - 1);
109}
diff --git a/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h b/arch/mips/pmc-sierra/msp71xx/msp_pci.c
index 5710a9029f1c..f764fe7748d6 100644
--- a/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
+++ b/arch/mips/pmc-sierra/msp71xx/msp_pci.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Ocelot-3 Board Register Definitions 2 * The setup file for PCI related hardware on PMC-Sierra MSP processors.
3 * 3 *
4 * (C) 2002 Momentum Computer Inc. 4 * Copyright 2005-2006 PMC-Sierra, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -22,38 +22,29 @@
22 * You should have received a copy of the GNU General Public License along 22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc., 23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Louis Hamilton, Red Hat, Inc.
27 * hamilton@redhat.com [MIPS64 modifications]
28 *
29 * Copyright (C) 2004 MontaVista Software Inc.
30 * Author: Manish Lachwani, mlachwani@mvista.com
31 */ 25 */
32 26
33#ifndef __OCELOT_3_FPGA_H__ 27#include <linux/init.h>
34#define __OCELOT_3_FPGA_H__ 28
35 29#include <msp_prom.h>
36#define OCELOT_3_REG_BOARDREV 0x0 30#include <msp_regs.h>
37#define OCELOT_3_REG_FPGA_REV 0x1 31
38#define OCELOT_3_REG_FPGA_TYPE 0x2 32extern void msp_pci_init(void);
39#define OCELOT_3_REG_RESET_STATUS 0x3
40#define OCELOT_3_REG_BOARD_STATUS 0x4
41#define OCELOT_3_REG_CPCI_ID 0x5
42#define OCELOT_3_REG_SET 0x6
43#define OCELOT_3_REG_CLR 0x7
44#define OCELOT_3_REG_EEPROM_MODE 0x9
45#define OCELOT_3_REG_INTMASK 0xa
46#define OCELOT_3_REG_INTSTAT 0xb
47#define OCELOT_3_REG_UART_INTMASK 0xc
48#define OCELOT_3_REG_UART_INTSTAT 0xd
49#define OCELOT_3_REG_INTSET 0xe
50#define OCELOT_3_REG_INTCLR 0xf
51
52extern unsigned long ocelot_fpga_base;
53
54#define __FPGA_REG_TO_ADDR(reg) \
55 ((void *) ocelot_fpga_base + OCELOT_3_REG_##reg)
56#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
57#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
58 33
34static int __init msp_pci_setup(void)
35{
36#if 0 /* Linux 2.6 initialization code to be completed */
37 if (getdeviceid() & DEV_ID_SINGLE_PC) {
38 /* If single card mode */
39 slmRegs *sreg = (slmRegs *) SREG_BASE;
40
41 sreg->single_pc_enable = SINGLE_PCCARD;
42 }
59#endif 43#endif
44
45 msp_pci_init();
46
47 return 0;
48}
49
50subsys_initcall(msp_pci_setup);
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
new file mode 100644
index 000000000000..e5bd5481d8db
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
@@ -0,0 +1,566 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * PROM library initialisation code, assuming a version of
4 * pmon is the boot code.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This file was derived from Carsten Langgaard's
11 * arch/mips/mips-boards/xx files.
12 *
13 * Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36
37#include <linux/module.h>
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/string.h>
41#include <linux/interrupt.h>
42#include <linux/mm.h>
43#ifdef CONFIG_CRAMFS
44#include <linux/cramfs_fs.h>
45#endif
46#ifdef CONFIG_SQUASHFS
47#include <linux/squashfs_fs.h>
48#endif
49
50#include <asm/addrspace.h>
51#include <asm/bootinfo.h>
52#include <asm-generic/sections.h>
53#include <asm/page.h>
54
55#include <msp_prom.h>
56#include <msp_regs.h>
57
58/* global PROM environment variables and pointers */
59int prom_argc;
60char **prom_argv, **prom_envp;
61int *prom_vec;
62
63/* debug flag */
64int init_debug = 1;
65
66/* memory blocks */
67struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
68
69/* default feature sets */
70static char msp_default_features[] =
71#if defined(CONFIG_PMC_MSP4200_EVAL) \
72 || defined(CONFIG_PMC_MSP4200_GW)
73 "ERER";
74#elif defined(CONFIG_PMC_MSP7120_EVAL) \
75 || defined(CONFIG_PMC_MSP7120_GW)
76 "EMEMSP";
77#elif defined(CONFIG_PMC_MSP7120_FPGA)
78 "EMEM";
79#endif
80
81/* conversion functions */
82static inline unsigned char str2hexnum(unsigned char c)
83{
84 if (c >= '0' && c <= '9')
85 return c - '0';
86 if (c >= 'a' && c <= 'f')
87 return c - 'a' + 10;
88 return 0; /* foo */
89}
90
91static inline int str2eaddr(unsigned char *ea, unsigned char *str)
92{
93 int index = 0;
94 unsigned char num = 0;
95
96 while (*str != '\0') {
97 if ((*str == '.') || (*str == ':')) {
98 ea[index++] = num;
99 num = 0;
100 str++;
101 } else {
102 num = num << 4;
103 num |= str2hexnum(*str++);
104 }
105 }
106
107 if (index == 5) {
108 ea[index++] = num;
109 return 0;
110 } else
111 return -1;
112}
113EXPORT_SYMBOL(str2eaddr);
114
115static inline unsigned long str2hex(unsigned char *str)
116{
117 int value = 0;
118
119 while (*str) {
120 value = value << 4;
121 value |= str2hexnum(*str++);
122 }
123
124 return value;
125}
126
127/* function to query the system information */
128const char *get_system_type(void)
129{
130#if defined(CONFIG_PMC_MSP4200_EVAL)
131 return "PMC-Sierra MSP4200 Eval Board";
132#elif defined(CONFIG_PMC_MSP4200_GW)
133 return "PMC-Sierra MSP4200 VoIP Gateway";
134#elif defined(CONFIG_PMC_MSP7120_EVAL)
135 return "PMC-Sierra MSP7120 Eval Board";
136#elif defined(CONFIG_PMC_MSP7120_GW)
137 return "PMC-Sierra MSP7120 Residential Gateway";
138#elif defined(CONFIG_PMC_MSP7120_FPGA)
139 return "PMC-Sierra MSP7120 FPGA";
140#else
141 #error "What is the type of *your* MSP?"
142#endif
143}
144
145int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr)
146{
147 char *ethaddr_str;
148
149 ethaddr_str = prom_getenv(ethaddr_name);
150 if (!ethaddr_str) {
151 printk(KERN_WARNING "%s not set in boot prom\n", ethaddr_name);
152 return -1;
153 }
154
155 if (str2eaddr(ethernet_addr, ethaddr_str) == -1) {
156 printk(KERN_WARNING "%s badly formatted-<%s>\n",
157 ethaddr_name, ethaddr_str);
158 return -1;
159 }
160
161 if (init_debug > 1) {
162 int i;
163 printk(KERN_DEBUG "get_ethernet_addr: for %s ", ethaddr_name);
164 for (i = 0; i < 5; i++)
165 printk(KERN_DEBUG "%02x:",
166 (unsigned char)*(ethernet_addr+i));
167 printk(KERN_DEBUG "%02x\n", *(ethernet_addr+i));
168 }
169
170 return 0;
171}
172EXPORT_SYMBOL(get_ethernet_addr);
173
174static char *get_features(void)
175{
176 char *feature = prom_getenv(FEATURES);
177
178 if (feature == NULL) {
179 /* default features based on MACHINE_TYPE */
180 feature = msp_default_features;
181 }
182
183 return feature;
184}
185
186static char test_feature(char c)
187{
188 char *feature = get_features();
189
190 while (*feature) {
191 if (*feature++ == c)
192 return *feature;
193 feature++;
194 }
195
196 return FEATURE_NOEXIST;
197}
198
199unsigned long get_deviceid(void)
200{
201 char *deviceid = prom_getenv(DEVICEID);
202
203 if (deviceid == NULL)
204 return *DEV_ID_REG;
205 else
206 return str2hex(deviceid);
207}
208
209char identify_pci(void)
210{
211 return test_feature(PCI_KEY);
212}
213EXPORT_SYMBOL(identify_pci);
214
215char identify_pcimux(void)
216{
217 return test_feature(PCIMUX_KEY);
218}
219
220char identify_sec(void)
221{
222 return test_feature(SEC_KEY);
223}
224EXPORT_SYMBOL(identify_sec);
225
226char identify_spad(void)
227{
228 return test_feature(SPAD_KEY);
229}
230EXPORT_SYMBOL(identify_spad);
231
232char identify_tdm(void)
233{
234 return test_feature(TDM_KEY);
235}
236EXPORT_SYMBOL(identify_tdm);
237
238char identify_zsp(void)
239{
240 return test_feature(ZSP_KEY);
241}
242EXPORT_SYMBOL(identify_zsp);
243
244static char identify_enetfeature(char key, unsigned long interface_num)
245{
246 char *feature = get_features();
247
248 while (*feature) {
249 if (*feature++ == key && interface_num-- == 0)
250 return *feature;
251 feature++;
252 }
253
254 return FEATURE_NOEXIST;
255}
256
257char identify_enet(unsigned long interface_num)
258{
259 return identify_enetfeature(ENET_KEY, interface_num);
260}
261EXPORT_SYMBOL(identify_enet);
262
263char identify_enetTxD(unsigned long interface_num)
264{
265 return identify_enetfeature(ENETTXD_KEY, interface_num);
266}
267EXPORT_SYMBOL(identify_enetTxD);
268
269unsigned long identify_family(void)
270{
271 unsigned long deviceid;
272
273 deviceid = get_deviceid();
274
275 return deviceid & CPU_DEVID_FAMILY;
276}
277EXPORT_SYMBOL(identify_family);
278
279unsigned long identify_revision(void)
280{
281 unsigned long deviceid;
282
283 deviceid = get_deviceid();
284
285 return deviceid & CPU_DEVID_REVISION;
286}
287EXPORT_SYMBOL(identify_revision);
288
289/* PROM environment functions */
290char *prom_getenv(char *env_name)
291{
292 /*
293 * Return a pointer to the given environment variable. prom_envp
294 * points to a null terminated array of pointers to variables.
295 * Environment variables are stored in the form of "memsize=64"
296 */
297
298 char **var = prom_envp;
299 int i = strlen(env_name);
300
301 while (*var) {
302 if (strncmp(env_name, *var, i) == 0) {
303 return (*var + strlen(env_name) + 1);
304 }
305 var++;
306 }
307
308 return NULL;
309}
310
311/* PROM commandline functions */
312char *prom_getcmdline(void)
313{
314 return &(arcs_cmdline[0]);
315}
316EXPORT_SYMBOL(prom_getcmdline);
317
318void __init prom_init_cmdline(void)
319{
320 char *cp;
321 int actr;
322
323 actr = 1; /* Always ignore argv[0] */
324
325 cp = &(arcs_cmdline[0]);
326 while (actr < prom_argc) {
327 strcpy(cp, prom_argv[actr]);
328 cp += strlen(prom_argv[actr]);
329 *cp++ = ' ';
330 actr++;
331 }
332 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
333 --cp;
334 *cp = '\0';
335}
336
337/* memory allocation functions */
338static int __init prom_memtype_classify(unsigned int type)
339{
340 switch (type) {
341 case yamon_free:
342 return BOOT_MEM_RAM;
343 case yamon_prom:
344 return BOOT_MEM_ROM_DATA;
345 default:
346 return BOOT_MEM_RESERVED;
347 }
348}
349
350void __init prom_meminit(void)
351{
352 struct prom_pmemblock *p;
353
354 p = prom_getmdesc();
355
356 while (p->size) {
357 long type;
358 unsigned long base, size;
359
360 type = prom_memtype_classify(p->type);
361 base = p->base;
362 size = p->size;
363
364 add_memory_region(base, size, type);
365 p++;
366 }
367}
368
369void __init prom_free_prom_memory(void)
370{
371 int argc;
372 char **argv;
373 char **envp;
374 char *ptr;
375 int len = 0;
376 int i;
377 unsigned long addr;
378
379 /*
380 * preserve environment variables and command line from pmon/bbload
381 * first preserve the command line
382 */
383 for (argc = 0; argc < prom_argc; argc++) {
384 len += sizeof(char *); /* length of pointer */
385 len += strlen(prom_argv[argc]) + 1; /* length of string */
386 }
387 len += sizeof(char *); /* plus length of null pointer */
388
389 argv = kmalloc(len, GFP_KERNEL);
390 ptr = (char *) &argv[prom_argc + 1]; /* strings follow array */
391
392 for (argc = 0; argc < prom_argc; argc++) {
393 argv[argc] = ptr;
394 strcpy(ptr, prom_argv[argc]);
395 ptr += strlen(prom_argv[argc]) + 1;
396 }
397 argv[prom_argc] = NULL; /* end array with null pointer */
398 prom_argv = argv;
399
400 /* next preserve the environment variables */
401 len = 0;
402 i = 0;
403 for (envp = prom_envp; *envp != NULL; envp++) {
404 i++; /* count number of environment variables */
405 len += sizeof(char *); /* length of pointer */
406 len += strlen(*envp) + 1; /* length of string */
407 }
408 len += sizeof(char *); /* plus length of null pointer */
409
410 envp = kmalloc(len, GFP_KERNEL);
411 ptr = (char *) &envp[i+1];
412
413 for (argc = 0; argc < i; argc++) {
414 envp[argc] = ptr;
415 strcpy(ptr, prom_envp[argc]);
416 ptr += strlen(prom_envp[argc]) + 1;
417 }
418 envp[i] = NULL; /* end array with null pointer */
419 prom_envp = envp;
420
421 for (i = 0; i < boot_mem_map.nr_map; i++) {
422 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
423 continue;
424
425 addr = boot_mem_map.map[i].addr;
426 free_init_pages("prom memory",
427 addr, addr + boot_mem_map.map[i].size);
428 }
429}
430
431struct prom_pmemblock *__init prom_getmdesc(void)
432{
433 static char memsz_env[] __initdata = "memsize";
434 static char heaptop_env[] __initdata = "heaptop";
435 char *str;
436 unsigned int memsize;
437 unsigned int heaptop;
438#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
439 void *ramroot_start;
440 unsigned long ramroot_size;
441#endif
442 int i;
443
444 str = prom_getenv(memsz_env);
445 if (!str) {
446 ppfinit("memsize not set in boot prom, "
447 "set to default (32Mb)\n");
448 memsize = 0x02000000;
449 } else {
450 memsize = simple_strtol(str, NULL, 0);
451
452 if (memsize == 0) {
453 /* if memsize is a bad size, use reasonable default */
454 memsize = 0x02000000;
455 }
456
457 /* convert to physical address (removing caching bits, etc) */
458 memsize = CPHYSADDR(memsize);
459 }
460
461 str = prom_getenv(heaptop_env);
462 if (!str) {
463 heaptop = CPHYSADDR((u32)&_text);
464 ppfinit("heaptop not set in boot prom, "
465 "set to default 0x%08x\n", heaptop);
466 } else {
467 heaptop = simple_strtol(str, NULL, 16);
468 if (heaptop == 0) {
469 /* heaptop conversion bad, might have 0xValue */
470 heaptop = simple_strtol(str, NULL, 0);
471
472 if (heaptop == 0) {
473 /* heaptop still bad, use reasonable default */
474 heaptop = CPHYSADDR((u32)&_text);
475 }
476 }
477
478 /* convert to physical address (removing caching bits, etc) */
479 heaptop = CPHYSADDR((u32)heaptop);
480 }
481
482 /* the base region */
483 i = 0;
484 mdesc[i].type = BOOT_MEM_RESERVED;
485 mdesc[i].base = 0x00000000;
486 mdesc[i].size = PAGE_ALIGN(0x300 + 0x80);
487 /* jtag interrupt vector + sizeof vector */
488
489 /* PMON data */
490 if (heaptop > mdesc[i].base + mdesc[i].size) {
491 i++; /* 1 */
492 mdesc[i].type = BOOT_MEM_ROM_DATA;
493 mdesc[i].base = mdesc[i-1].base + mdesc[i-1].size;
494 mdesc[i].size = heaptop - mdesc[i].base;
495 }
496
497 /* end of PMON data to start of kernel -- probably zero .. */
498 if (heaptop != CPHYSADDR((u32)_text)) {
499 i++; /* 2 */
500 mdesc[i].type = BOOT_MEM_RAM;
501 mdesc[i].base = heaptop;
502 mdesc[i].size = CPHYSADDR((u32)_text) - mdesc[i].base;
503 }
504
505 /* kernel proper */
506 i++; /* 3 */
507 mdesc[i].type = BOOT_MEM_RESERVED;
508 mdesc[i].base = CPHYSADDR((u32)_text);
509#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
510 if (get_ramroot(&ramroot_start, &ramroot_size)) {
511 /*
512 * Rootfs in RAM -- follows kernel
513 * Combine rootfs image with kernel block so a
514 * page (4k) isn't wasted between memory blocks
515 */
516 mdesc[i].size = CPHYSADDR(PAGE_ALIGN(
517 (u32)ramroot_start + ramroot_size)) - mdesc[i].base;
518 } else
519#endif
520 mdesc[i].size = CPHYSADDR(PAGE_ALIGN(
521 (u32)_end)) - mdesc[i].base;
522
523 /* Remainder of RAM -- under memsize */
524 i++; /* 5 */
525 mdesc[i].type = yamon_free;
526 mdesc[i].base = mdesc[i-1].base + mdesc[i-1].size;
527 mdesc[i].size = memsize - mdesc[i].base;
528
529 return &mdesc[0];
530}
531
532/* rootfs functions */
533#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
534bool get_ramroot(void **start, unsigned long *size)
535{
536 extern char _end[];
537
538 /* Check for start following the end of the kernel */
539 void *check_start = (void *)_end;
540
541 /* Check for supported rootfs types */
542#ifdef CONFIG_CRAMFS
543 if (*(__u32 *)check_start == CRAMFS_MAGIC) {
544 /* Get CRAMFS size */
545 *start = check_start;
546 *size = PAGE_ALIGN(((struct cramfs_super *)
547 check_start)->size);
548
549 return true;
550 }
551#endif
552#ifdef CONFIG_SQUASHFS
553 if (*((unsigned int *)check_start) == SQUASHFS_MAGIC) {
554 /* Get SQUASHFS size */
555 *start = check_start;
556 *size = PAGE_ALIGN(((struct squashfs_super_block *)
557 check_start)->bytes_used);
558
559 return true;
560 }
561#endif
562
563 return false;
564}
565EXPORT_SYMBOL(get_ramroot);
566#endif
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
new file mode 100644
index 000000000000..8f69b789be90
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -0,0 +1,256 @@
1/*
2 * The generic setup file for PMC-Sierra MSP processors
3 *
4 * Copyright 2005-2007 PMC-Sierra, Inc,
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <asm/bootinfo.h>
14#include <asm/cacheflush.h>
15#include <asm/r4kcache.h>
16#include <asm/reboot.h>
17#include <asm/time.h>
18
19#include <msp_prom.h>
20#include <msp_regs.h>
21
22#if defined(CONFIG_PMC_MSP7120_GW)
23#include <msp_regops.h>
24#include <msp_gpio.h>
25#define MSP_BOARD_RESET_GPIO 9
26#endif
27
28extern void msp_timer_init(void);
29extern void msp_serial_setup(void);
30extern void pmctwiled_setup(void);
31
32#if defined(CONFIG_PMC_MSP7120_EVAL) || \
33 defined(CONFIG_PMC_MSP7120_GW) || \
34 defined(CONFIG_PMC_MSP7120_FPGA)
35/*
36 * Performs the reset for MSP7120-based boards
37 */
38void msp7120_reset(void)
39{
40 void *start, *end, *iptr;
41 register int i;
42
43 /* Diasble all interrupts */
44 local_irq_disable();
45#ifdef CONFIG_SYS_SUPPORTS_MULTITHREADING
46 dvpe();
47#endif
48
49 /* Cache the reset code of this function */
50 __asm__ __volatile__ (
51 " .set push \n"
52 " .set mips3 \n"
53 " la %0,startpoint \n"
54 " la %1,endpoint \n"
55 " .set pop \n"
56 : "=r" (start), "=r" (end)
57 :
58 );
59
60 for (iptr = (void *)((unsigned int)start & ~(L1_CACHE_BYTES - 1));
61 iptr < end; iptr += L1_CACHE_BYTES)
62 cache_op(Fill, iptr);
63
64 __asm__ __volatile__ (
65 "startpoint: \n"
66 );
67
68 /* Put the DDRC into self-refresh mode */
69 DDRC_INDIRECT_WRITE(DDRC_CTL(10), 0xb, 1 << 16);
70
71 /*
72 * IMPORTANT!
73 * DO NOT do anything from here on out that might even
74 * think about fetching from RAM - i.e., don't call any
75 * non-inlined functions, and be VERY sure that any inline
76 * functions you do call do NOT access any sort of RAM
77 * anywhere!
78 */
79
80 /* Wait a bit for the DDRC to settle */
81 for (i = 0; i < 100000000; i++);
82
83#if defined(CONFIG_PMC_MSP7120_GW)
84 /*
85 * Set GPIO 9 HI, (tied to board reset logic)
86 * GPIO 9 is the 4th GPIO of register 3
87 *
88 * NOTE: We cannot use the higher-level msp_gpio_mode()/out()
89 * as GPIO char driver may not be enabled and it would look up
90 * data inRAM!
91 */
92 set_value_reg32(GPIO_CFG3_REG,
93 basic_mode_mask(MSP_BOARD_RESET_GPIO),
94 basic_mode(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO));
95 set_reg32(GPIO_DATA3_REG,
96 basic_data_mask(MSP_BOARD_RESET_GPIO));
97
98 /*
99 * In case GPIO9 doesn't reset the board (jumper configurable!)
100 * fallback to device reset below.
101 */
102#endif
103 /* Set bit 1 of the MSP7120 reset register */
104 *RST_SET_REG = 0x00000001;
105
106 __asm__ __volatile__ (
107 "endpoint: \n"
108 );
109}
110#endif
111
112void msp_restart(char *command)
113{
114 printk(KERN_WARNING "Now rebooting .......\n");
115
116#if defined(CONFIG_PMC_MSP7120_EVAL) || \
117 defined(CONFIG_PMC_MSP7120_GW) || \
118 defined(CONFIG_PMC_MSP7120_FPGA)
119 msp7120_reset();
120#else
121 /* No chip-specific reset code, just jump to the ROM reset vector */
122 set_c0_status(ST0_BEV | ST0_ERL);
123 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
124 flush_cache_all();
125 write_c0_wired(0);
126
127 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
128#endif
129}
130
131void msp_halt(void)
132{
133 printk(KERN_WARNING "\n** You can safely turn off the power\n");
134 while (1)
135 /* If possible call official function to get CPU WARs */
136 if (cpu_wait)
137 (*cpu_wait)();
138 else
139 __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
140}
141
142void msp_power_off(void)
143{
144 msp_halt();
145}
146
147void __init plat_mem_setup(void)
148{
149 _machine_restart = msp_restart;
150 _machine_halt = msp_halt;
151 pm_power_off = msp_power_off;
152
153 board_time_init = msp_timer_init;
154}
155
156void __init prom_init(void)
157{
158 unsigned long family;
159 unsigned long revision;
160
161 prom_argc = fw_arg0;
162 prom_argv = (char **)fw_arg1;
163 prom_envp = (char **)fw_arg2;
164
165 /*
166 * Someday we can use this with PMON2000 to get a
167 * platform call prom routines for output etc. without
168 * having to use grody hacks. For now it's unused.
169 *
170 * struct callvectors *cv = (struct callvectors *) fw_arg3;
171 */
172 family = identify_family();
173 revision = identify_revision();
174
175 switch (family) {
176 case FAMILY_FPGA:
177 if (FPGA_IS_MSP4200(revision)) {
178 /* Old-style revision ID */
179 mips_machgroup = MACH_GROUP_MSP;
180 mips_machtype = MACH_MSP4200_FPGA;
181 } else {
182 mips_machgroup = MACH_GROUP_MSP;
183 mips_machtype = MACH_MSP_OTHER;
184 }
185 break;
186
187 case FAMILY_MSP4200:
188 mips_machgroup = MACH_GROUP_MSP;
189#if defined(CONFIG_PMC_MSP4200_EVAL)
190 mips_machtype = MACH_MSP4200_EVAL;
191#elif defined(CONFIG_PMC_MSP4200_GW)
192 mips_machtype = MACH_MSP4200_GW;
193#else
194 mips_machtype = MACH_MSP_OTHER;
195#endif
196 break;
197
198 case FAMILY_MSP4200_FPGA:
199 mips_machgroup = MACH_GROUP_MSP;
200 mips_machtype = MACH_MSP4200_FPGA;
201 break;
202
203 case FAMILY_MSP7100:
204 mips_machgroup = MACH_GROUP_MSP;
205#if defined(CONFIG_PMC_MSP7120_EVAL)
206 mips_machtype = MACH_MSP7120_EVAL;
207#elif defined(CONFIG_PMC_MSP7120_GW)
208 mips_machtype = MACH_MSP7120_GW;
209#else
210 mips_machtype = MACH_MSP_OTHER;
211#endif
212 break;
213
214 case FAMILY_MSP7100_FPGA:
215 mips_machgroup = MACH_GROUP_MSP;
216 mips_machtype = MACH_MSP7120_FPGA;
217 break;
218
219 default:
220 /* we don't recognize the machine */
221 mips_machgroup = MACH_GROUP_UNKNOWN;
222 mips_machtype = MACH_UNKNOWN;
223 break;
224 }
225
226 /* make sure we have the right initialization routine - sanity */
227 if (mips_machgroup != MACH_GROUP_MSP) {
228 ppfinit("Unknown machine group in a "
229 "MSP initialization routine\n");
230 panic("***Bogosity factor five***, exiting\n");
231 }
232
233 prom_init_cmdline();
234
235 prom_meminit();
236
237 /*
238 * Sub-system setup follows.
239 * Setup functions can either be called here or using the
240 * subsys_initcall mechanism (i.e. see msp_pci_setup). The
241 * order in which they are called can be changed by using the
242 * link order in arch/mips/pmc-sierra/msp71xx/Makefile.
243 *
244 * NOTE: Please keep sub-system specific initialization code
245 * in separate specific files.
246 */
247 msp_serial_setup();
248
249#ifdef CONFIG_PMCTWILED
250 /*
251 * Setup LED states before the subsys_initcall loads other
252 * dependant drivers/modules.
253 */
254 pmctwiled_setup();
255#endif
256}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c
new file mode 100644
index 000000000000..2a2beac5a4f8
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c
@@ -0,0 +1,94 @@
1/*
2 * Setting up the clock on MSP SOCs. No RTC typically.
3 *
4 * Carsten Langgaard, carstenl@mips.com
5 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#include <linux/init.h>
26#include <linux/kernel_stat.h>
27#include <linux/sched.h>
28#include <linux/spinlock.h>
29#include <linux/module.h>
30#include <linux/ptrace.h>
31
32#include <asm/mipsregs.h>
33#include <asm/time.h>
34
35#include <msp_prom.h>
36#include <msp_int.h>
37#include <msp_regs.h>
38
39void __init msp_timer_init(void)
40{
41 char *endp, *s;
42 unsigned long cpu_rate = 0;
43
44 if (cpu_rate == 0) {
45 s = prom_getenv("clkfreqhz");
46 cpu_rate = simple_strtoul(s, &endp, 10);
47 if (endp != NULL && *endp != 0) {
48 printk(KERN_ERR
49 "Clock rate in Hz parse error: %s\n", s);
50 cpu_rate = 0;
51 }
52 }
53
54 if (cpu_rate == 0) {
55 s = prom_getenv("clkfreq");
56 cpu_rate = 1000 * simple_strtoul(s, &endp, 10);
57 if (endp != NULL && *endp != 0) {
58 printk(KERN_ERR
59 "Clock rate in MHz parse error: %s\n", s);
60 cpu_rate = 0;
61 }
62 }
63
64 if (cpu_rate == 0) {
65#if defined(CONFIG_PMC_MSP7120_EVAL) \
66 || defined(CONFIG_PMC_MSP7120_GW)
67 cpu_rate = 400000000;
68#elif defined(CONFIG_PMC_MSP7120_FPGA)
69 cpu_rate = 25000000;
70#else
71 cpu_rate = 150000000;
72#endif
73 printk(KERN_ERR
74 "Failed to determine CPU clock rate, "
75 "assuming %ld hz ...\n", cpu_rate);
76 }
77
78 printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate);
79
80 /* timer frequency is 1/2 clock rate */
81 mips_hpt_frequency = cpu_rate/2;
82}
83
84
85void __init plat_timer_setup(struct irqaction *irq)
86{
87#ifdef CONFIG_IRQ_MSP_CIC
88 /* we are using the vpe0 counter for timer interrupts */
89 setup_irq(MSP_INT_VPE0_TIMER, irq);
90#else
91 /* we are using the mips counter for timer interrupts */
92 setup_irq(MSP_INT_TIMER, irq);
93#endif
94}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
new file mode 100644
index 000000000000..21f9c70b6923
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
@@ -0,0 +1,150 @@
1/*
2 * The setup file for USB related hardware on PMC-Sierra MSP processors.
3 *
4 * Copyright 2006-2007 PMC-Sierra, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/dma-mapping.h>
28#include <linux/init.h>
29#include <linux/ioport.h>
30#include <linux/platform_device.h>
31
32#include <asm/mipsregs.h>
33
34#include <msp_regs.h>
35#include <msp_int.h>
36#include <msp_prom.h>
37
38#if defined(CONFIG_USB_EHCI_HCD)
39static struct resource msp_usbhost_resources [] = {
40 [0] = {
41 .start = MSP_USB_BASE_START,
42 .end = MSP_USB_BASE_END,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = MSP_INT_USB,
47 .end = MSP_INT_USB,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52static u64 msp_usbhost_dma_mask = DMA_32BIT_MASK;
53
54static struct platform_device msp_usbhost_device = {
55 .name = "pmcmsp-ehci",
56 .id = 0,
57 .dev = {
58 .dma_mask = &msp_usbhost_dma_mask,
59 .coherent_dma_mask = DMA_32BIT_MASK,
60 },
61 .num_resources = ARRAY_SIZE (msp_usbhost_resources),
62 .resource = msp_usbhost_resources,
63};
64#endif /* CONFIG_USB_EHCI_HCD */
65
66#if defined(CONFIG_USB_GADGET)
67static struct resource msp_usbdev_resources [] = {
68 [0] = {
69 .start = MSP_USB_BASE,
70 .end = MSP_USB_BASE_END,
71 .flags = IORESOURCE_MEM,
72 },
73 [1] = {
74 .start = MSP_INT_USB,
75 .end = MSP_INT_USB,
76 .flags = IORESOURCE_IRQ,
77 },
78};
79
80static u64 msp_usbdev_dma_mask = DMA_32BIT_MASK;
81
82static struct platform_device msp_usbdev_device = {
83 .name = "msp71xx_udc",
84 .id = 0,
85 .dev = {
86 .dma_mask = &msp_usbdev_dma_mask,
87 .coherent_dma_mask = DMA_32BIT_MASK,
88 },
89 .num_resources = ARRAY_SIZE (msp_usbdev_resources),
90 .resource = msp_usbdev_resources,
91};
92#endif /* CONFIG_USB_GADGET */
93
94#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET)
95static struct platform_device *msp_devs[1];
96#endif
97
98
99static int __init msp_usb_setup(void)
100{
101#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET)
102 char *strp;
103 char envstr[32];
104 unsigned int val = 0;
105 int result = 0;
106
107 /*
108 * construct environment name usbmode
109 * set usbmode <host/device> as pmon environment var
110 */
111 snprintf((char *)&envstr[0], sizeof(envstr), "usbmode");
112
113#if defined(CONFIG_USB_EHCI_HCD)
114 /* default to host mode */
115 val = 1;
116#endif
117
118 /* get environment string */
119 strp = prom_getenv((char *)&envstr[0]);
120 if (strp) {
121 if (!strcmp(strp, "device"))
122 val = 0;
123 }
124
125 if (val) {
126#if defined(CONFIG_USB_EHCI_HCD)
127 /* get host mode device */
128 msp_devs[0] = &msp_usbhost_device;
129 ppfinit("platform add USB HOST done %s.\n",
130 msp_devs[0]->name);
131
132 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs));
133#endif /* CONFIG_USB_EHCI_HCD */
134 }
135#if defined(CONFIG_USB_GADGET)
136 else {
137 /* get device mode structure */
138 msp_devs[0] = &msp_usbdev_device;
139 ppfinit("platform add USB DEVICE done %s.\n",
140 msp_devs[0]->name);
141
142 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs));
143 }
144#endif /* CONFIG_USB_GADGET */
145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */
146
147 return result;
148}
149
150subsys_initcall(msp_usb_setup);
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index 305491e74dbe..d83c4ada14f3 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -77,7 +77,7 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
77 * stack so the first thing we do is throw away that stuff and load useful 77 * stack so the first thing we do is throw away that stuff and load useful
78 * values into the registers ... 78 * values into the registers ...
79 */ 79 */
80void prom_boot_secondary(int cpu, struct task_struct *idle) 80void __init prom_boot_secondary(int cpu, struct task_struct *idle)
81{ 81{
82 unsigned long gp = (unsigned long) task_thread_info(idle); 82 unsigned long gp = (unsigned long) task_thread_info(idle);
83 unsigned long sp = __KSTK_TOS(idle); 83 unsigned long sp = __KSTK_TOS(idle);
diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c
index 66df5ac8f089..63afd7e44428 100644
--- a/arch/mips/sgi-ip22/ip22-reset.c
+++ b/arch/mips/sgi-ip22/ip22-reset.c
@@ -46,7 +46,7 @@ static struct timer_list power_timer, blink_timer, debounce_timer, volume_timer;
46 46
47static int machine_state; 47static int machine_state;
48 48
49static void ATTRIB_NORET sgi_machine_power_off(void) 49static void __noreturn sgi_machine_power_off(void)
50{ 50{
51 unsigned int tmp; 51 unsigned int tmp;
52 52
@@ -68,7 +68,7 @@ static void ATTRIB_NORET sgi_machine_power_off(void)
68 } 68 }
69} 69}
70 70
71static void ATTRIB_NORET sgi_machine_restart(char *command) 71static void __noreturn sgi_machine_restart(char *command)
72{ 72{
73 if (machine_state & MACHINE_SHUTTING_DOWN) 73 if (machine_state & MACHINE_SHUTTING_DOWN)
74 sgi_machine_power_off(); 74 sgi_machine_power_off();
@@ -76,7 +76,7 @@ static void ATTRIB_NORET sgi_machine_restart(char *command)
76 while (1); 76 while (1);
77} 77}
78 78
79static void ATTRIB_NORET sgi_machine_halt(void) 79static void __noreturn sgi_machine_halt(void)
80{ 80{
81 if (machine_state & MACHINE_SHUTTING_DOWN) 81 if (machine_state & MACHINE_SHUTTING_DOWN)
82 sgi_machine_power_off(); 82 sgi_machine_power_off();
diff --git a/arch/mips/sgi-ip27/ip27-berr.c b/arch/mips/sgi-ip27/ip27-berr.c
index ce907eda221b..123141ab21a2 100644
--- a/arch/mips/sgi-ip27/ip27-berr.c
+++ b/arch/mips/sgi-ip27/ip27-berr.c
@@ -21,7 +21,6 @@
21#include <asm/traps.h> 21#include <asm/traps.h>
22#include <asm/uaccess.h> 22#include <asm/uaccess.h>
23 23
24extern void dump_tlb_addr(unsigned long addr);
25extern void dump_tlb_all(void); 24extern void dump_tlb_all(void);
26 25
27static void dump_hub_information(unsigned long errst0, unsigned long errst1) 26static void dump_hub_information(unsigned long errst0, unsigned long errst1)
diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c
index 120b15932caf..ba3697ee7ff6 100644
--- a/arch/mips/sgi-ip32/ip32-platform.c
+++ b/arch/mips/sgi-ip32/ip32-platform.c
@@ -1,5 +1,53 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/module.h>
1#include <linux/init.h> 9#include <linux/init.h>
2#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/serial_8250.h>
12
13#include <asm/ip32/mace.h>
14#include <asm/ip32/ip32_ints.h>
15
16/*
17 * .iobase isn't a constant (in the sense of C) so we fill it in at runtime.
18 */
19#define MACE_PORT(int) \
20{ \
21 .irq = int, \
22 .uartclk = 1843200, \
23 .iotype = UPIO_MEM, \
24 .flags = UPF_SKIP_TEST, \
25 .regshift = 8, \
26}
27
28static struct plat_serial8250_port uart8250_data[] = {
29 MACE_PORT(MACEISA_SERIAL1_IRQ),
30 MACE_PORT(MACEISA_SERIAL2_IRQ),
31 { },
32};
33
34static struct platform_device uart8250_device = {
35 .name = "serial8250",
36 .id = PLAT8250_DEV_PLATFORM,
37 .dev = {
38 .platform_data = uart8250_data,
39 },
40};
41
42static int __init uart8250_init(void)
43{
44 uart8250_data[0].iobase = (unsigned long) &mace->isa.serial1;
45 uart8250_data[1].iobase = (unsigned long) &mace->isa.serial1;
46
47 return platform_device_register(&uart8250_device);
48}
49
50device_initcall(uart8250_init);
3 51
4static __init int meth_devinit(void) 52static __init int meth_devinit(void)
5{ 53{
@@ -18,3 +66,7 @@ static __init int meth_devinit(void)
18} 66}
19 67
20device_initcall(meth_devinit); 68device_initcall(meth_devinit);
69
70MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
71MODULE_LICENSE("GPL");
72MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2");
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index 57708fe28bd7..bbba066cb405 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -62,12 +62,6 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
62} 62}
63#endif 63#endif
64 64
65#ifdef CONFIG_SERIAL_8250
66#include <linux/tty.h>
67#include <linux/serial.h>
68#include <linux/serial_core.h>
69#endif /* CONFIG_SERIAL_8250 */
70
71/* An arbitrary time; this can be decreased if reliability looks good */ 65/* An arbitrary time; this can be decreased if reliability looks good */
72#define WAIT_MS 10 66#define WAIT_MS 10
73 67
@@ -96,36 +90,6 @@ void __init plat_mem_setup(void)
96 90
97 board_time_init = ip32_time_init; 91 board_time_init = ip32_time_init;
98 92
99#ifdef CONFIG_SERIAL_8250
100 {
101 static struct uart_port o2_serial[2];
102
103 memset(o2_serial, 0, sizeof(o2_serial));
104 o2_serial[0].type = PORT_16550A;
105 o2_serial[0].line = 0;
106 o2_serial[0].irq = MACEISA_SERIAL1_IRQ;
107 o2_serial[0].flags = UPF_SKIP_TEST;
108 o2_serial[0].uartclk = 1843200;
109 o2_serial[0].iotype = UPIO_MEM;
110 o2_serial[0].membase = (char *)&mace->isa.serial1;
111 o2_serial[0].fifosize = 14;
112 /* How much to shift register offset by. Each UART register
113 * is replicated over 256 byte space */
114 o2_serial[0].regshift = 8;
115 o2_serial[1].type = PORT_16550A;
116 o2_serial[1].line = 1;
117 o2_serial[1].irq = MACEISA_SERIAL2_IRQ;
118 o2_serial[1].flags = UPF_SKIP_TEST;
119 o2_serial[1].uartclk = 1843200;
120 o2_serial[1].iotype = UPIO_MEM;
121 o2_serial[1].membase = (char *)&mace->isa.serial2;
122 o2_serial[1].fifosize = 14;
123 o2_serial[1].regshift = 8;
124
125 early_serial_setup(&o2_serial[0]);
126 early_serial_setup(&o2_serial[1]);
127 }
128#endif
129#ifdef CONFIG_SGI_O2MACE_ETH 93#ifdef CONFIG_SGI_O2MACE_ETH
130 { 94 {
131 char *mac = ArcGetEnvironmentVariable("eaddr"); 95 char *mac = ArcGetEnvironmentVariable("eaddr");
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index ae4a92c3e529..51898dd1304a 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -62,7 +62,7 @@ extern unsigned long initrd_start, initrd_end;
62extern int kgdb_port; 62extern int kgdb_port;
63#endif 63#endif
64 64
65static void ATTRIB_NORET cfe_linux_exit(void *arg) 65static void __noreturn cfe_linux_exit(void *arg)
66{ 66{
67 int warm = *(int *)arg; 67 int warm = *(int *)arg;
68 68
@@ -83,14 +83,14 @@ static void ATTRIB_NORET cfe_linux_exit(void *arg)
83 while (1); 83 while (1);
84} 84}
85 85
86static void ATTRIB_NORET cfe_linux_restart(char *command) 86static void __noreturn cfe_linux_restart(char *command)
87{ 87{
88 static const int zero; 88 static const int zero;
89 89
90 cfe_linux_exit((void *)&zero); 90 cfe_linux_exit((void *)&zero);
91} 91}
92 92
93static void ATTRIB_NORET cfe_linux_halt(void) 93static void __noreturn cfe_linux_halt(void)
94{ 94{
95 static const int one = 1; 95 static const int one = 1;
96 96
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index e5777b7e2bc9..471418e4f446 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -2,5 +2,5 @@
2# Makefile for the SNI specific part of the kernel 2# Makefile for the SNI specific part of the kernel
3# 3#
4 4
5obj-y += irq.o reset.o setup.o ds1216.o a20r.o rm200.o pcimt.o pcit.o time.o 5obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o
6obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o 6obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 31ab80f1befa..6850a29defcd 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -15,7 +15,6 @@
15 15
16#include <asm/sni.h> 16#include <asm/sni.h>
17#include <asm/time.h> 17#include <asm/time.h>
18#include <asm/ds1216.h>
19 18
20#define PORT(_base,_irq) \ 19#define PORT(_base,_irq) \
21 { \ 20 { \
@@ -40,20 +39,34 @@ static struct platform_device a20r_serial8250_device = {
40 }, 39 },
41}; 40};
42 41
42static struct resource a20r_ds1216_rsrc[] = {
43 {
44 .start = 0x1c081ffc,
45 .end = 0x1c081fff,
46 .flags = IORESOURCE_MEM
47 }
48};
49
50static struct platform_device a20r_ds1216_device = {
51 .name = "rtc-ds1216",
52 .num_resources = ARRAY_SIZE(a20r_ds1216_rsrc),
53 .resource = a20r_ds1216_rsrc
54};
55
43static struct resource snirm_82596_rsrc[] = { 56static struct resource snirm_82596_rsrc[] = {
44 { 57 {
45 .start = 0xb8000000, 58 .start = 0x18000000,
46 .end = 0xb8000004, 59 .end = 0x18000004,
47 .flags = IORESOURCE_MEM 60 .flags = IORESOURCE_MEM
48 }, 61 },
49 { 62 {
50 .start = 0xb8010000, 63 .start = 0x18010000,
51 .end = 0xb8010004, 64 .end = 0x18010004,
52 .flags = IORESOURCE_MEM 65 .flags = IORESOURCE_MEM
53 }, 66 },
54 { 67 {
55 .start = 0xbff00000, 68 .start = 0x1ff00000,
56 .end = 0xbff00020, 69 .end = 0x1ff00020,
57 .flags = IORESOURCE_MEM 70 .flags = IORESOURCE_MEM
58 }, 71 },
59 { 72 {
@@ -205,8 +218,7 @@ void __init sni_a20r_irq_init(void)
205 218
206void sni_a20r_init(void) 219void sni_a20r_init(void)
207{ 220{
208 ds1216_base = (volatile unsigned char *) SNI_DS1216_A20R_BASE; 221 /* FIXME, remove if not needed */
209 rtc_mips_get_time = ds1216_get_cmos_time;
210} 222}
211 223
212static int __init snirm_a20r_setup_devinit(void) 224static int __init snirm_a20r_setup_devinit(void)
@@ -218,6 +230,7 @@ static int __init snirm_a20r_setup_devinit(void)
218 platform_device_register(&snirm_53c710_pdev); 230 platform_device_register(&snirm_53c710_pdev);
219 platform_device_register(&sc26xx_pdev); 231 platform_device_register(&sc26xx_pdev);
220 platform_device_register(&a20r_serial8250_device); 232 platform_device_register(&a20r_serial8250_device);
233 platform_device_register(&a20r_ds1216_device);
221 break; 234 break;
222 } 235 }
223 236
diff --git a/arch/mips/sni/ds1216.c b/arch/mips/sni/ds1216.c
deleted file mode 100644
index 1d92732c14f1..000000000000
--- a/arch/mips/sni/ds1216.c
+++ /dev/null
@@ -1,81 +0,0 @@
1
2#include <linux/bcd.h>
3#include <linux/time.h>
4
5#include <asm/ds1216.h>
6
7volatile unsigned char *ds1216_base;
8
9/*
10 * Read the 64 bit we'd like to have - It a series
11 * of 64 bits showing up in the LSB of the base register.
12 *
13 */
14static unsigned char *ds1216_read(void)
15{
16 static unsigned char rdbuf[8];
17 unsigned char c;
18 int i, j;
19
20 for (i = 0; i < 8; i++) {
21 c = 0x0;
22 for (j = 0; j < 8; j++) {
23 c |= (*ds1216_base & 0x1) << j;
24 }
25 rdbuf[i] = c;
26 }
27
28 return rdbuf;
29}
30
31static void ds1216_switch_ds_to_clock(void)
32{
33 unsigned char magic[] = {
34 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
35 };
36 int i,j,c;
37
38 /* Reset magic pointer */
39 c = *ds1216_base;
40
41 /* Write 64 bit magic to DS1216 */
42 for (i = 0; i < 8; i++) {
43 c = magic[i];
44 for (j = 0; j < 8; j++) {
45 *ds1216_base = c;
46 c = c >> 1;
47 }
48 }
49}
50
51unsigned long ds1216_get_cmos_time(void)
52{
53 unsigned char *rdbuf;
54 unsigned int year, month, date, hour, min, sec;
55
56 ds1216_switch_ds_to_clock();
57 rdbuf = ds1216_read();
58
59 sec = BCD2BIN(DS1216_SEC(rdbuf));
60 min = BCD2BIN(DS1216_MIN(rdbuf));
61 hour = BCD2BIN(DS1216_HOUR(rdbuf));
62 date = BCD2BIN(DS1216_DATE(rdbuf));
63 month = BCD2BIN(DS1216_MONTH(rdbuf));
64 year = BCD2BIN(DS1216_YEAR(rdbuf));
65
66 if (DS1216_1224(rdbuf) && DS1216_AMPM(rdbuf))
67 hour+=12;
68
69 if (year < 70)
70 year += 2000;
71 else
72 year += 1900;
73
74 return mktime(year, month, date, hour, min, sec);
75}
76
77int ds1216_set_rtc_mmss(unsigned long nowtime)
78{
79 printk("ds1216_set_rtc_mmss called but not implemented\n");
80 return -1;
81}
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 97b234361b4d..44b1ae62aa4a 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -14,7 +14,6 @@
14#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16 16
17#include <asm/mc146818-time.h>
18#include <asm/sni.h> 17#include <asm/sni.h>
19#include <asm/time.h> 18#include <asm/time.h>
20#include <asm/i8259.h> 19#include <asm/i8259.h>
@@ -90,6 +89,26 @@ static struct platform_device pcimt_serial8250_device = {
90 }, 89 },
91}; 90};
92 91
92static struct resource pcimt_cmos_rsrc[] = {
93 {
94 .start = 0x70,
95 .end = 0x71,
96 .flags = IORESOURCE_IO
97 },
98 {
99 .start = 8,
100 .end = 8,
101 .flags = IORESOURCE_IRQ
102 }
103};
104
105static struct platform_device pcimt_cmos_device = {
106 .name = "rtc_cmos",
107 .num_resources = ARRAY_SIZE(pcimt_cmos_rsrc),
108 .resource = pcimt_cmos_rsrc
109};
110
111
93static struct resource sni_io_resource = { 112static struct resource sni_io_resource = {
94 .start = 0x00000000UL, 113 .start = 0x00000000UL,
95 .end = 0x03bfffffUL, 114 .end = 0x03bfffffUL,
@@ -290,12 +309,10 @@ void __init sni_pcimt_irq_init(void)
290 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); 309 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
291} 310}
292 311
293void sni_pcimt_init(void) 312void __init sni_pcimt_init(void)
294{ 313{
295 sni_pcimt_detect(); 314 sni_pcimt_detect();
296 sni_pcimt_sc_init(); 315 sni_pcimt_sc_init();
297 rtc_mips_get_time = mc146818_get_cmos_time;
298 rtc_mips_set_time = mc146818_set_rtc_mmss;
299 board_time_init = sni_cpu_time_init; 316 board_time_init = sni_cpu_time_init;
300 ioport_resource.end = sni_io_resource.end; 317 ioport_resource.end = sni_io_resource.end;
301#ifdef CONFIG_PCI 318#ifdef CONFIG_PCI
@@ -312,6 +329,7 @@ static int __init snirm_pcimt_setup_devinit(void)
312 case SNI_BRD_PCI_DESKTOP: 329 case SNI_BRD_PCI_DESKTOP:
313 case SNI_BRD_PCI_MTOWER_CPLUS: 330 case SNI_BRD_PCI_MTOWER_CPLUS:
314 platform_device_register(&pcimt_serial8250_device); 331 platform_device_register(&pcimt_serial8250_device);
332 platform_device_register(&pcimt_cmos_device);
315 break; 333 break;
316 } 334 }
317 335
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 00d151f4d121..2480c478dcbd 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -13,7 +13,6 @@
13#include <linux/pci.h> 13#include <linux/pci.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15 15
16#include <asm/mc146818-time.h>
17#include <asm/sni.h> 16#include <asm/sni.h>
18#include <asm/time.h> 17#include <asm/time.h>
19#include <asm/irq_cpu.h> 18#include <asm/irq_cpu.h>
@@ -58,6 +57,25 @@ static struct platform_device pcit_cplus_serial8250_device = {
58 }, 57 },
59}; 58};
60 59
60static struct resource pcit_cmos_rsrc[] = {
61 {
62 .start = 0x70,
63 .end = 0x71,
64 .flags = IORESOURCE_IO
65 },
66 {
67 .start = 8,
68 .end = 8,
69 .flags = IORESOURCE_IRQ
70 }
71};
72
73static struct platform_device pcit_cmos_device = {
74 .name = "rtc_cmos",
75 .num_resources = ARRAY_SIZE(pcit_cmos_rsrc),
76 .resource = pcit_cmos_rsrc
77};
78
61static struct resource sni_io_resource = { 79static struct resource sni_io_resource = {
62 .start = 0x00000000UL, 80 .start = 0x00000000UL,
63 .end = 0x03bfffffUL, 81 .end = 0x03bfffffUL,
@@ -243,10 +261,8 @@ void __init sni_pcit_cplus_irq_init(void)
243 setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); 261 setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
244} 262}
245 263
246void sni_pcit_init(void) 264void __init sni_pcit_init(void)
247{ 265{
248 rtc_mips_get_time = mc146818_get_cmos_time;
249 rtc_mips_set_time = mc146818_set_rtc_mmss;
250 board_time_init = sni_cpu_time_init; 266 board_time_init = sni_cpu_time_init;
251 ioport_resource.end = sni_io_resource.end; 267 ioport_resource.end = sni_io_resource.end;
252#ifdef CONFIG_PCI 268#ifdef CONFIG_PCI
@@ -261,10 +277,12 @@ static int __init snirm_pcit_setup_devinit(void)
261 switch (sni_brd_type) { 277 switch (sni_brd_type) {
262 case SNI_BRD_PCI_TOWER: 278 case SNI_BRD_PCI_TOWER:
263 platform_device_register(&pcit_serial8250_device); 279 platform_device_register(&pcit_serial8250_device);
280 platform_device_register(&pcit_cmos_device);
264 break; 281 break;
265 282
266 case SNI_BRD_PCI_TOWER_CPLUS: 283 case SNI_BRD_PCI_TOWER_CPLUS:
267 platform_device_register(&pcit_cplus_serial8250_device); 284 platform_device_register(&pcit_cplus_serial8250_device);
285 platform_device_register(&pcit_cmos_device);
268 break; 286 break;
269 } 287 }
270 return 0; 288 return 0;
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index b82ff129f5ea..4bfda020fdc7 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -15,7 +15,6 @@
15 15
16#include <asm/sni.h> 16#include <asm/sni.h>
17#include <asm/time.h> 17#include <asm/time.h>
18#include <asm/ds1216.h>
19#include <asm/irq_cpu.h> 18#include <asm/irq_cpu.h>
20 19
21#define PORT(_base,_irq) \ 20#define PORT(_base,_irq) \
@@ -41,20 +40,34 @@ static struct platform_device rm200_serial8250_device = {
41 }, 40 },
42}; 41};
43 42
43static struct resource rm200_ds1216_rsrc[] = {
44 {
45 .start = 0x1cd41ffc,
46 .end = 0x1cd41fff,
47 .flags = IORESOURCE_MEM
48 }
49};
50
51static struct platform_device rm200_ds1216_device = {
52 .name = "rtc-ds1216",
53 .num_resources = ARRAY_SIZE(rm200_ds1216_rsrc),
54 .resource = rm200_ds1216_rsrc
55};
56
44static struct resource snirm_82596_rm200_rsrc[] = { 57static struct resource snirm_82596_rm200_rsrc[] = {
45 { 58 {
46 .start = 0xb8000000, 59 .start = 0x18000000,
47 .end = 0xb80fffff, 60 .end = 0x180fffff,
48 .flags = IORESOURCE_MEM 61 .flags = IORESOURCE_MEM
49 }, 62 },
50 { 63 {
51 .start = 0xbb000000, 64 .start = 0x1b000000,
52 .end = 0xbb000004, 65 .end = 0x1b000004,
53 .flags = IORESOURCE_MEM 66 .flags = IORESOURCE_MEM
54 }, 67 },
55 { 68 {
56 .start = 0xbff00000, 69 .start = 0x1ff00000,
57 .end = 0xbff00020, 70 .end = 0x1ff00020,
58 .flags = IORESOURCE_MEM 71 .flags = IORESOURCE_MEM
59 }, 72 },
60 { 73 {
@@ -96,6 +109,7 @@ static int __init snirm_setup_devinit(void)
96{ 109{
97 if (sni_brd_type == SNI_BRD_RM200) { 110 if (sni_brd_type == SNI_BRD_RM200) {
98 platform_device_register(&rm200_serial8250_device); 111 platform_device_register(&rm200_serial8250_device);
112 platform_device_register(&rm200_ds1216_device);
99 platform_device_register(&snirm_82596_rm200_pdev); 113 platform_device_register(&snirm_82596_rm200_pdev);
100 platform_device_register(&snirm_53c710_rm200_pdev); 114 platform_device_register(&snirm_53c710_rm200_pdev);
101 } 115 }
@@ -176,11 +190,9 @@ void __init sni_rm200_irq_init(void)
176 setup_irq (SNI_RM200_INT_START + 0, &sni_isa_irq); 190 setup_irq (SNI_RM200_INT_START + 0, &sni_isa_irq);
177} 191}
178 192
179void sni_rm200_init(void) 193void __init sni_rm200_init(void)
180{ 194{
181 set_io_port_base(SNI_PORT_BASE + 0x02000000); 195 set_io_port_base(SNI_PORT_BASE + 0x02000000);
182 ioport_resource.end += 0x02000000; 196 ioport_resource.end += 0x02000000;
183 ds1216_base = (volatile unsigned char *) SNI_DS1216_RM200_BASE;
184 rtc_mips_get_time = ds1216_get_cmos_time;
185 board_time_init = sni_cpu_time_init; 197 board_time_init = sni_cpu_time_init;
186} 198}
diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c
index 643366eb854a..00a03a6e8f58 100644
--- a/arch/mips/sni/sniprom.c
+++ b/arch/mips/sni/sniprom.c
@@ -146,7 +146,10 @@ static void __init sni_console_setup(void)
146 } 146 }
147 if (baud) 147 if (baud)
148 strcpy(options, baud); 148 strcpy(options, baud);
149 add_preferred_console("ttyS", port, baud ? options : NULL); 149 if (strncmp (cdev, "tty552", 6) == 0)
150 add_preferred_console("ttyS", port, baud ? options : NULL);
151 else
152 add_preferred_console("ttySC", port, baud ? options : NULL);
150 } 153 }
151} 154}
152 155
diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile
index 2033ae77f632..83cda518f204 100644
--- a/arch/mips/tx4938/common/Makefile
+++ b/arch/mips/tx4938/common/Makefile
@@ -6,6 +6,6 @@
6# unless it's something special (ie not a .c file). 6# unless it's something special (ie not a .c file).
7# 7#
8 8
9obj-y += prom.o setup.o irq.o rtc_rx5c348.o 9obj-y += prom.o setup.o irq.o
10obj-$(CONFIG_KGDB) += dbgio.o 10obj-$(CONFIG_KGDB) += dbgio.o
11 11
diff --git a/arch/mips/tx4938/common/rtc_rx5c348.c b/arch/mips/tx4938/common/rtc_rx5c348.c
deleted file mode 100644
index 07f782fc0725..000000000000
--- a/arch/mips/tx4938/common/rtc_rx5c348.c
+++ /dev/null
@@ -1,192 +0,0 @@
1/*
2 * RTC routines for RICOH Rx5C348 SPI chip.
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/rtc.h>
16#include <linux/time.h>
17#include <linux/bcd.h>
18#include <asm/time.h>
19#include <asm/tx4938/spi.h>
20
21#define EPOCH 2000
22
23/* registers */
24#define Rx5C348_REG_SECOND 0
25#define Rx5C348_REG_MINUTE 1
26#define Rx5C348_REG_HOUR 2
27#define Rx5C348_REG_WEEK 3
28#define Rx5C348_REG_DAY 4
29#define Rx5C348_REG_MONTH 5
30#define Rx5C348_REG_YEAR 6
31#define Rx5C348_REG_ADJUST 7
32#define Rx5C348_REG_ALARM_W_MIN 8
33#define Rx5C348_REG_ALARM_W_HOUR 9
34#define Rx5C348_REG_ALARM_W_WEEK 10
35#define Rx5C348_REG_ALARM_D_MIN 11
36#define Rx5C348_REG_ALARM_D_HOUR 12
37#define Rx5C348_REG_CTL1 14
38#define Rx5C348_REG_CTL2 15
39
40/* register bits */
41#define Rx5C348_BIT_PM 0x20 /* REG_HOUR */
42#define Rx5C348_BIT_Y2K 0x80 /* REG_MONTH */
43#define Rx5C348_BIT_24H 0x20 /* REG_CTL1 */
44#define Rx5C348_BIT_XSTP 0x10 /* REG_CTL2 */
45
46/* commands */
47#define Rx5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
48#define Rx5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
49#define Rx5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
50#define Rx5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
51
52static struct spi_dev_desc srtc_dev_desc = {
53 .baud = 1000000, /* 1.0Mbps @ Vdd 2.0V */
54 .tcss = 31,
55 .tcsh = 1,
56 .tcsr = 62,
57 /* 31us for Tcss (62us for Tcsr) is required for carry operation) */
58 .byteorder = 1, /* MSB-First */
59 .polarity = 0, /* High-Active */
60 .phase = 1, /* Shift-Then-Sample */
61
62};
63static int srtc_chipid;
64static int srtc_24h;
65
66static inline int
67spi_rtc_io(unsigned char *inbuf, unsigned char *outbuf, unsigned int count)
68{
69 unsigned char *inbufs[1], *outbufs[1];
70 unsigned int incounts[2], outcounts[2];
71 inbufs[0] = inbuf;
72 incounts[0] = count;
73 incounts[1] = 0;
74 outbufs[0] = outbuf;
75 outcounts[0] = count;
76 outcounts[1] = 0;
77 return txx9_spi_io(srtc_chipid, &srtc_dev_desc,
78 inbufs, incounts, outbufs, outcounts, 0);
79}
80
81/* RTC-dependent code for time.c */
82
83static int
84rtc_rx5c348_set_time(unsigned long t)
85{
86 unsigned char inbuf[8];
87 struct rtc_time tm;
88 u8 year, month, day, hour, minute, second, century;
89
90 /* convert */
91 to_tm(t, &tm);
92
93 year = tm.tm_year % 100;
94 month = tm.tm_mon+1; /* tm_mon starts from 0 to 11 */
95 day = tm.tm_mday;
96 hour = tm.tm_hour;
97 minute = tm.tm_min;
98 second = tm.tm_sec;
99 century = tm.tm_year / 100;
100
101 inbuf[0] = Rx5C348_CMD_MW(Rx5C348_REG_SECOND);
102 BIN_TO_BCD(second);
103 inbuf[1] = second;
104 BIN_TO_BCD(minute);
105 inbuf[2] = minute;
106
107 if (srtc_24h) {
108 BIN_TO_BCD(hour);
109 inbuf[3] = hour;
110 } else {
111 /* hour 0 is AM12, noon is PM12 */
112 inbuf[3] = 0;
113 if (hour >= 12)
114 inbuf[3] = Rx5C348_BIT_PM;
115 hour = (hour + 11) % 12 + 1;
116 BIN_TO_BCD(hour);
117 inbuf[3] |= hour;
118 }
119 inbuf[4] = 0; /* ignore week */
120 BIN_TO_BCD(day);
121 inbuf[5] = day;
122 BIN_TO_BCD(month);
123 inbuf[6] = month;
124 if (century >= 20)
125 inbuf[6] |= Rx5C348_BIT_Y2K;
126 BIN_TO_BCD(year);
127 inbuf[7] = year;
128 /* write in one transfer to avoid data inconsistency */
129 return spi_rtc_io(inbuf, NULL, 8);
130}
131
132static unsigned long
133rtc_rx5c348_get_time(void)
134{
135 unsigned char inbuf[8], outbuf[8];
136 unsigned int year, month, day, hour, minute, second;
137
138 inbuf[0] = Rx5C348_CMD_MR(Rx5C348_REG_SECOND);
139 memset(inbuf + 1, 0, 7);
140 /* read in one transfer to avoid data inconsistency */
141 if (spi_rtc_io(inbuf, outbuf, 8))
142 return 0;
143 second = outbuf[1];
144 BCD_TO_BIN(second);
145 minute = outbuf[2];
146 BCD_TO_BIN(minute);
147 if (srtc_24h) {
148 hour = outbuf[3];
149 BCD_TO_BIN(hour);
150 } else {
151 hour = outbuf[3] & ~Rx5C348_BIT_PM;
152 BCD_TO_BIN(hour);
153 hour %= 12;
154 if (outbuf[3] & Rx5C348_BIT_PM)
155 hour += 12;
156 }
157 day = outbuf[5];
158 BCD_TO_BIN(day);
159 month = outbuf[6] & ~Rx5C348_BIT_Y2K;
160 BCD_TO_BIN(month);
161 year = outbuf[7];
162 BCD_TO_BIN(year);
163 year += EPOCH;
164
165 return mktime(year, month, day, hour, minute, second);
166}
167
168void __init
169rtc_rx5c348_init(int chipid)
170{
171 unsigned char inbuf[2], outbuf[2];
172 srtc_chipid = chipid;
173 /* turn on RTC if it is not on */
174 inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL2);
175 inbuf[1] = 0;
176 spi_rtc_io(inbuf, outbuf, 2);
177 if (outbuf[1] & Rx5C348_BIT_XSTP) {
178 inbuf[0] = Rx5C348_CMD_W(Rx5C348_REG_CTL2);
179 inbuf[1] = 0;
180 spi_rtc_io(inbuf, NULL, 2);
181 }
182
183 inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL1);
184 inbuf[1] = 0;
185 spi_rtc_io(inbuf, outbuf, 2);
186 if (outbuf[1] & Rx5C348_BIT_24H)
187 srtc_24h = 1;
188
189 /* set the function pointers */
190 rtc_mips_get_time = rtc_rx5c348_get_time;
191 rtc_mips_set_time = rtc_rx5c348_set_time;
192}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/Makefile b/arch/mips/tx4938/toshiba_rbtx4938/Makefile
index 226941279d75..10c94e62bf5b 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/Makefile
+++ b/arch/mips/tx4938/toshiba_rbtx4938/Makefile
@@ -6,4 +6,4 @@
6# unless it's something special (ie not a .c file). 6# unless it's something special (ie not a .c file).
7# 7#
8 8
9obj-y += prom.o setup.o irq.o spi_eeprom.o spi_txx9.o 9obj-y += prom.o setup.o irq.o spi_eeprom.o
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 2e96dbb248b1..91aea7aff515 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -165,8 +165,6 @@ toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
165 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 165 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
166} 166}
167 167
168extern void __init txx9_spi_irqinit(int irc_irq);
169
170void __init arch_init_irq(void) 168void __init arch_init_irq(void)
171{ 169{
172 extern void tx4938_irq_init(void); 170 extern void tx4938_irq_init(void);
@@ -185,9 +183,5 @@ void __init arch_init_irq(void)
185 /* Onboard 10M Ether: High Active */ 183 /* Onboard 10M Ether: High Active */
186 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040); 184 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040);
187 185
188 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_SPI_SEL) {
189 txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI);
190 }
191
192 wbflush(); 186 wbflush();
193} 187}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index f5d1ce739fcc..6ed39a5aea72 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -14,13 +14,13 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/types.h> 15#include <linux/types.h>
16#include <linux/ioport.h> 16#include <linux/ioport.h>
17#include <linux/proc_fs.h>
18#include <linux/delay.h> 17#include <linux/delay.h>
19#include <linux/interrupt.h> 18#include <linux/interrupt.h>
20#include <linux/console.h> 19#include <linux/console.h>
21#include <linux/pci.h> 20#include <linux/pci.h>
22#include <linux/pm.h> 21#include <linux/pm.h>
23#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/clk.h>
24 24
25#include <asm/wbflush.h> 25#include <asm/wbflush.h>
26#include <asm/reboot.h> 26#include <asm/reboot.h>
@@ -35,6 +35,9 @@
35#include <linux/serial.h> 35#include <linux/serial.h>
36#include <linux/serial_core.h> 36#include <linux/serial_core.h>
37#endif 37#endif
38#include <linux/spi/spi.h>
39#include <asm/tx4938/spi.h>
40#include <asm/gpio.h>
38 41
39extern void rbtx4938_time_init(void) __init; 42extern void rbtx4938_time_init(void) __init;
40extern char * __init prom_getcmdline(void); 43extern char * __init prom_getcmdline(void);
@@ -349,7 +352,7 @@ static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
349 static struct pci_dev dev; 352 static struct pci_dev dev;
350 static struct pci_bus bus; 353 static struct pci_bus bus;
351 354
352 dev.sysdata = (void *)hose; 355 dev.sysdata = bus.sysdata = hose;
353 dev.devfn = devfn; 356 dev.devfn = devfn;
354 bus.number = busnr; 357 bus.number = busnr;
355 bus.ops = hose->pci_ops; 358 bus.ops = hose->pci_ops;
@@ -382,8 +385,10 @@ int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bu
382 printk("PCI: Checking 66MHz capabilities...\n"); 385 printk("PCI: Checking 66MHz capabilities...\n");
383 386
384 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) { 387 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
385 early_read_config_word(hose, top_bus, current_bus, pci_devfn, 388 if (early_read_config_word(hose, top_bus, current_bus,
386 PCI_VENDOR_ID, &vid); 389 pci_devfn, PCI_VENDOR_ID,
390 &vid) != PCIBIOS_SUCCESSFUL)
391 continue;
387 392
388 if (vid == 0xffff) continue; 393 if (vid == 0xffff) continue;
389 394
@@ -460,7 +465,6 @@ static int __init tx4938_pcibios_init(void)
460 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); 465 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
461 466
462 PCIBIOS_MIN_IO = 0x00001000UL; 467 PCIBIOS_MIN_IO = 0x00001000UL;
463 PCIBIOS_MIN_MEM = 0x01000000UL;
464 468
465 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]); 469 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
466 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]); 470 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
@@ -574,82 +578,43 @@ arch_initcall(tx4938_pcibios_init);
574#define SEEPROM3_CS 1 /* IOC */ 578#define SEEPROM3_CS 1 /* IOC */
575#define SRTC_CS 2 /* IOC */ 579#define SRTC_CS 2 /* IOC */
576 580
577static int rbtx4938_spi_cs_func(int chipid, int on)
578{
579 unsigned char bit;
580 switch (chipid) {
581 case RBTX4938_SEEPROM1_CHIPID:
582 if (on)
583 tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS);
584 else
585 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
586 return 0;
587 break;
588 case RBTX4938_SEEPROM2_CHIPID:
589 bit = (1 << SEEPROM2_CS);
590 break;
591 case RBTX4938_SEEPROM3_CHIPID:
592 bit = (1 << SEEPROM3_CS);
593 break;
594 case RBTX4938_SRTC_CHIPID:
595 bit = (1 << SRTC_CS);
596 break;
597 default:
598 return -ENODEV;
599 }
600 /* bit1,2,4 are low active, bit3 is high active */
601 *rbtx4938_spics_ptr =
602 (*rbtx4938_spics_ptr & ~bit) |
603 ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit);
604 return 0;
605}
606
607#ifdef CONFIG_PCI 581#ifdef CONFIG_PCI
608extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); 582static int __init rbtx4938_ethaddr_init(void)
609
610int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
611{ 583{
612 struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata; 584 unsigned char dat[17];
613 static unsigned char dat[17]; 585 unsigned char sum;
614 static int read_dat = 0; 586 int i;
615 int ch = 0;
616 587
617 if (channel != &tx4938_pci_controller[1]) 588 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
618 return -ENODEV; 589 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
619 /* TX4938 PCIC1 */ 590 printk(KERN_ERR "seeprom: read error.\n");
620 switch (PCI_SLOT(dev->devfn)) {
621 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
622 ch = 0;
623 break;
624 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
625 ch = 1;
626 break;
627 default:
628 return -ENODEV; 591 return -ENODEV;
592 } else {
593 if (strcmp(dat, "MAC") != 0)
594 printk(KERN_WARNING "seeprom: bad signature.\n");
595 for (i = 0, sum = 0; i < sizeof(dat); i++)
596 sum += dat[i];
597 if (sum)
598 printk(KERN_WARNING "seeprom: bad checksum.\n");
629 } 599 }
630 if (!read_dat) { 600 for (i = 0; i < 2; i++) {
631 unsigned char sum; 601 unsigned int slot = TX4938_PCIC_IDSEL_AD_TO_SLOT(31 - i);
632 int i; 602 unsigned int id = (1 << 8) | PCI_DEVFN(slot, 0); /* bus 1 */
633 read_dat = 1; 603 struct platform_device *pdev;
634 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */ 604 if (!(tx4938_ccfgptr->pcfg &
635 if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID, 605 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
636 0, dat, sizeof(dat))) { 606 continue;
637 printk(KERN_ERR "seeprom: read error.\n"); 607 pdev = platform_device_alloc("tc35815-mac", id);
638 } else { 608 if (!pdev ||
639 if (strcmp(dat, "MAC") != 0) 609 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
640 printk(KERN_WARNING "seeprom: bad signature.\n"); 610 platform_device_add(pdev))
641 for (i = 0, sum = 0; i < sizeof(dat); i++) 611 platform_device_put(pdev);
642 sum += dat[i];
643 if (sum)
644 printk(KERN_WARNING "seeprom: bad checksum.\n");
645 }
646 } 612 }
647 memcpy(addr, &dat[4 + 6 * ch], 6);
648 return 0; 613 return 0;
649} 614}
615device_initcall(rbtx4938_ethaddr_init);
650#endif /* CONFIG_PCI */ 616#endif /* CONFIG_PCI */
651 617
652extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on));
653static void __init rbtx4938_spi_setup(void) 618static void __init rbtx4938_spi_setup(void)
654{ 619{
655 /* set SPI_SEL */ 620 /* set SPI_SEL */
@@ -657,7 +622,6 @@ static void __init rbtx4938_spi_setup(void)
657 /* chip selects for SPI devices */ 622 /* chip selects for SPI devices */
658 tx4938_pioptr->dout |= (1 << SEEPROM1_CS); 623 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
659 tx4938_pioptr->dir |= (1 << SEEPROM1_CS); 624 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
660 txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func);
661} 625}
662 626
663static struct resource rbtx4938_fpga_resource; 627static struct resource rbtx4938_fpga_resource;
@@ -896,10 +860,8 @@ void tx4938_report_pcic_status(void)
896/* We use onchip r4k counter or TMR timer as our system wide timer 860/* We use onchip r4k counter or TMR timer as our system wide timer
897 * interrupt running at 100HZ. */ 861 * interrupt running at 100HZ. */
898 862
899extern void __init rtc_rx5c348_init(int chipid);
900void __init rbtx4938_time_init(void) 863void __init rbtx4938_time_init(void)
901{ 864{
902 rtc_rx5c348_init(RBTX4938_SRTC_CHIPID);
903 mips_hpt_frequency = txx9_cpu_clock / 2; 865 mips_hpt_frequency = txx9_cpu_clock / 2;
904} 866}
905 867
@@ -1016,29 +978,6 @@ void __init toshiba_rbtx4938_setup(void)
1016 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr); 978 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
1017} 979}
1018 980
1019#ifdef CONFIG_PROC_FS
1020extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid);
1021static int __init tx4938_spi_proc_setup(void)
1022{
1023 struct proc_dir_entry *tx4938_spi_eeprom_dir;
1024
1025 tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0);
1026
1027 if (!tx4938_spi_eeprom_dir)
1028 return -ENOMEM;
1029
1030 /* don't allow user access to RBTX4938_SEEPROM1_CHIPID
1031 * as it contains eth0 and eth1 MAC addresses
1032 */
1033 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID);
1034 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID);
1035
1036 return 0;
1037}
1038
1039__initcall(tx4938_spi_proc_setup);
1040#endif
1041
1042static int __init rbtx4938_ne_init(void) 981static int __init rbtx4938_ne_init(void)
1043{ 982{
1044 struct resource res[] = { 983 struct resource res[] = {
@@ -1057,3 +996,176 @@ static int __init rbtx4938_ne_init(void)
1057 return IS_ERR(dev) ? PTR_ERR(dev) : 0; 996 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1058} 997}
1059device_initcall(rbtx4938_ne_init); 998device_initcall(rbtx4938_ne_init);
999
1000/* GPIO support */
1001
1002static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
1003
1004static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
1005{
1006 u8 val;
1007 unsigned long flags;
1008 gpio -= 16;
1009 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
1010 val = *rbtx4938_spics_ptr;
1011 if (value)
1012 val |= 1 << gpio;
1013 else
1014 val &= ~(1 << gpio);
1015 *rbtx4938_spics_ptr = val;
1016 mmiowb();
1017 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1018}
1019
1020static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
1021{
1022 rbtx4938_spi_gpio_set(gpio, value);
1023 return 0;
1024}
1025
1026static DEFINE_SPINLOCK(tx4938_gpio_lock);
1027
1028static int tx4938_gpio_get(unsigned gpio)
1029{
1030 return tx4938_pioptr->din & (1 << gpio);
1031}
1032
1033static void tx4938_gpio_set_raw(unsigned gpio, int value)
1034{
1035 u32 val;
1036 val = tx4938_pioptr->dout;
1037 if (value)
1038 val |= 1 << gpio;
1039 else
1040 val &= ~(1 << gpio);
1041 tx4938_pioptr->dout = val;
1042}
1043
1044static void tx4938_gpio_set(unsigned gpio, int value)
1045{
1046 unsigned long flags;
1047 spin_lock_irqsave(&tx4938_gpio_lock, flags);
1048 tx4938_gpio_set_raw(gpio, value);
1049 mmiowb();
1050 spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
1051}
1052
1053static int tx4938_gpio_dir_in(unsigned gpio)
1054{
1055 spin_lock_irq(&tx4938_gpio_lock);
1056 tx4938_pioptr->dir &= ~(1 << gpio);
1057 mmiowb();
1058 spin_unlock_irq(&tx4938_gpio_lock);
1059 return 0;
1060}
1061
1062static int tx4938_gpio_dir_out(unsigned int gpio, int value)
1063{
1064 spin_lock_irq(&tx4938_gpio_lock);
1065 tx4938_gpio_set_raw(gpio, value);
1066 tx4938_pioptr->dir |= 1 << gpio;
1067 mmiowb();
1068 spin_unlock_irq(&tx4938_gpio_lock);
1069 return 0;
1070}
1071
1072int gpio_direction_input(unsigned gpio)
1073{
1074 if (gpio < 16)
1075 return tx4938_gpio_dir_in(gpio);
1076 return -EINVAL;
1077}
1078
1079int gpio_direction_output(unsigned gpio, int value)
1080{
1081 if (gpio < 16)
1082 return tx4938_gpio_dir_out(gpio, value);
1083 if (gpio < 16 + 3)
1084 return rbtx4938_spi_gpio_dir_out(gpio, value);
1085 return -EINVAL;
1086}
1087
1088int gpio_get_value(unsigned gpio)
1089{
1090 if (gpio < 16)
1091 return tx4938_gpio_get(gpio);
1092 return 0;
1093}
1094
1095void gpio_set_value(unsigned gpio, int value)
1096{
1097 if (gpio < 16)
1098 tx4938_gpio_set(gpio, value);
1099 else
1100 rbtx4938_spi_gpio_set(gpio, value);
1101}
1102
1103/* SPI support */
1104
1105static void __init txx9_spi_init(unsigned long base, int irq)
1106{
1107 struct resource res[] = {
1108 {
1109 .start = base,
1110 .end = base + 0x20 - 1,
1111 .flags = IORESOURCE_MEM,
1112 .parent = &tx4938_reg_resource,
1113 }, {
1114 .start = irq,
1115 .flags = IORESOURCE_IRQ,
1116 },
1117 };
1118 platform_device_register_simple("txx9spi", 0,
1119 res, ARRAY_SIZE(res));
1120}
1121
1122static int __init rbtx4938_spi_init(void)
1123{
1124 struct spi_board_info srtc_info = {
1125 .modalias = "rs5c348",
1126 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
1127 .bus_num = 0,
1128 .chip_select = 16 + SRTC_CS,
1129 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
1130 .mode = SPI_MODE_1 | SPI_CS_HIGH,
1131 };
1132 spi_register_board_info(&srtc_info, 1);
1133 spi_eeprom_register(SEEPROM1_CS);
1134 spi_eeprom_register(16 + SEEPROM2_CS);
1135 spi_eeprom_register(16 + SEEPROM3_CS);
1136 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
1137 return 0;
1138}
1139arch_initcall(rbtx4938_spi_init);
1140
1141/* Minimum CLK support */
1142
1143struct clk *clk_get(struct device *dev, const char *id)
1144{
1145 if (!strcmp(id, "spi-baseclk"))
1146 return (struct clk *)(txx9_gbus_clock / 2 / 4);
1147 return ERR_PTR(-ENOENT);
1148}
1149EXPORT_SYMBOL(clk_get);
1150
1151int clk_enable(struct clk *clk)
1152{
1153 return 0;
1154}
1155EXPORT_SYMBOL(clk_enable);
1156
1157void clk_disable(struct clk *clk)
1158{
1159}
1160EXPORT_SYMBOL(clk_disable);
1161
1162unsigned long clk_get_rate(struct clk *clk)
1163{
1164 return (unsigned long)clk;
1165}
1166EXPORT_SYMBOL(clk_get_rate);
1167
1168void clk_put(struct clk *clk)
1169{
1170}
1171EXPORT_SYMBOL(clk_put);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
index 89596e62f909..4d6b4ade5e8c 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
@@ -10,209 +10,90 @@
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/delay.h> 13#include <linux/device.h>
14#include <linux/proc_fs.h> 14#include <linux/spi/spi.h>
15#include <linux/spinlock.h> 15#include <linux/spi/eeprom.h>
16#include <asm/tx4938/spi.h> 16#include <asm/tx4938/spi.h>
17#include <asm/tx4938/tx4938.h>
18 17
19/* ATMEL 250x0 instructions */ 18#define AT250X0_PAGE_SIZE 8
20#define ATMEL_WREN 0x06
21#define ATMEL_WRDI 0x04
22#define ATMEL_RDSR 0x05
23#define ATMEL_WRSR 0x01
24#define ATMEL_READ 0x03
25#define ATMEL_WRITE 0x02
26 19
27#define ATMEL_SR_BSY 0x01 20/* register board information for at25 driver */
28#define ATMEL_SR_WEN 0x02 21int __init spi_eeprom_register(int chipid)
29#define ATMEL_SR_BP0 0x04
30#define ATMEL_SR_BP1 0x08
31
32DEFINE_SPINLOCK(spi_eeprom_lock);
33
34static struct spi_dev_desc seeprom_dev_desc = {
35 .baud = 1500000, /* 1.5Mbps */
36 .tcss = 1,
37 .tcsh = 1,
38 .tcsr = 1,
39 .byteorder = 1, /* MSB-First */
40 .polarity = 0, /* High-Active */
41 .phase = 0, /* Sample-Then-Shift */
42
43};
44static inline int
45spi_eeprom_io(int chipid,
46 unsigned char **inbufs, unsigned int *incounts,
47 unsigned char **outbufs, unsigned int *outcounts)
48{
49 return txx9_spi_io(chipid, &seeprom_dev_desc,
50 inbufs, incounts, outbufs, outcounts, 0);
51}
52
53int spi_eeprom_write_enable(int chipid, int enable)
54{ 22{
55 unsigned char inbuf[1]; 23 static struct spi_eeprom eeprom = {
56 unsigned char *inbufs[1]; 24 .name = "at250x0",
57 unsigned int incounts[2]; 25 .byte_len = 128,
58 unsigned long flags; 26 .page_size = AT250X0_PAGE_SIZE,
59 int stat; 27 .flags = EE_ADDR1,
60 inbuf[0] = enable ? ATMEL_WREN : ATMEL_WRDI; 28 };
61 inbufs[0] = inbuf; 29 struct spi_board_info info = {
62 incounts[0] = sizeof(inbuf); 30 .modalias = "at25",
63 incounts[1] = 0; 31 .max_speed_hz = 1500000, /* 1.5Mbps */
64 spin_lock_irqsave(&spi_eeprom_lock, flags); 32 .bus_num = 0,
65 stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL); 33 .chip_select = chipid,
66 spin_unlock_irqrestore(&spi_eeprom_lock, flags); 34 .platform_data = &eeprom,
67 return stat; 35 /* Mode 0: High-Active, Sample-Then-Shift */
68} 36 };
69 37
70static int spi_eeprom_read_status_nolock(int chipid) 38 return spi_register_board_info(&info, 1);
71{
72 unsigned char inbuf[2], outbuf[2];
73 unsigned char *inbufs[1], *outbufs[1];
74 unsigned int incounts[2], outcounts[2];
75 int stat;
76 inbuf[0] = ATMEL_RDSR;
77 inbuf[1] = 0;
78 inbufs[0] = inbuf;
79 incounts[0] = sizeof(inbuf);
80 incounts[1] = 0;
81 outbufs[0] = outbuf;
82 outcounts[0] = sizeof(outbuf);
83 outcounts[1] = 0;
84 stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
85 if (stat < 0)
86 return stat;
87 return outbuf[1];
88} 39}
89 40
90int spi_eeprom_read_status(int chipid) 41/* simple temporary spi driver to provide early access to seeprom. */
91{
92 unsigned long flags;
93 int stat;
94 spin_lock_irqsave(&spi_eeprom_lock, flags);
95 stat = spi_eeprom_read_status_nolock(chipid);
96 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
97 return stat;
98}
99 42
100int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len) 43static struct read_param {
101{ 44 int chipid;
102 unsigned char inbuf[2]; 45 int address;
103 unsigned char *inbufs[2], *outbufs[2]; 46 unsigned char *buf;
104 unsigned int incounts[2], outcounts[3]; 47 int len;
105 unsigned long flags; 48} *read_param;
106 int stat;
107 inbuf[0] = ATMEL_READ;
108 inbuf[1] = address;
109 inbufs[0] = inbuf;
110 inbufs[1] = NULL;
111 incounts[0] = sizeof(inbuf);
112 incounts[1] = 0;
113 outbufs[0] = NULL;
114 outbufs[1] = buf;
115 outcounts[0] = 2;
116 outcounts[1] = len;
117 outcounts[2] = 0;
118 spin_lock_irqsave(&spi_eeprom_lock, flags);
119 stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
120 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
121 return stat;
122}
123 49
124int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len) 50static int __init early_seeprom_probe(struct spi_device *spi)
125{ 51{
126 unsigned char inbuf[2]; 52 int stat = 0;
127 unsigned char *inbufs[2]; 53 u8 cmd[2];
128 unsigned int incounts[3]; 54 int len = read_param->len;
129 unsigned long flags; 55 char *buf = read_param->buf;
130 int i, stat; 56 int address = read_param->address;
131 57
132 if (address / 8 != (address + len - 1) / 8) 58 dev_info(&spi->dev, "spiclk %u KHz.\n",
133 return -EINVAL; 59 (spi->max_speed_hz + 500) / 1000);
134 stat = spi_eeprom_write_enable(chipid, 1); 60 if (read_param->chipid != spi->chip_select)
135 if (stat < 0) 61 return -ENODEV;
136 return stat; 62 while (len > 0) {
137 stat = spi_eeprom_read_status(chipid); 63 /* spi_write_then_read can only work with small chunk */
138 if (stat < 0) 64 int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE;
139 return stat; 65 cmd[0] = 0x03; /* AT25_READ */
140 if (!(stat & ATMEL_SR_WEN)) 66 cmd[1] = address;
141 return -EPERM; 67 stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c);
142 68 buf += c;
143 inbuf[0] = ATMEL_WRITE; 69 len -= c;
144 inbuf[1] = address; 70 address += c;
145 inbufs[0] = inbuf;
146 inbufs[1] = buf;
147 incounts[0] = sizeof(inbuf);
148 incounts[1] = len;
149 incounts[2] = 0;
150 spin_lock_irqsave(&spi_eeprom_lock, flags);
151 stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
152 if (stat < 0)
153 goto unlock_return;
154
155 /* write start. max 10ms */
156 for (i = 10; i > 0; i--) {
157 int stat = spi_eeprom_read_status_nolock(chipid);
158 if (stat < 0)
159 goto unlock_return;
160 if (!(stat & ATMEL_SR_BSY))
161 break;
162 mdelay(1);
163 } 71 }
164 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
165 if (i == 0)
166 return -EIO;
167 return len;
168 unlock_return:
169 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
170 return stat; 72 return stat;
171} 73}
172 74
173#ifdef CONFIG_PROC_FS 75static struct spi_driver early_seeprom_driver __initdata = {
174#define MAX_SIZE 0x80 /* for ATMEL 25010 */ 76 .driver = {
175static int spi_eeprom_read_proc(char *page, char **start, off_t off, 77 .name = "at25",
176 int count, int *eof, void *data) 78 .owner = THIS_MODULE,
177{ 79 },
178 unsigned int size = MAX_SIZE; 80 .probe = early_seeprom_probe,
179 if (spi_eeprom_read((int)data, 0, (unsigned char *)page, size) < 0) 81};
180 size = 0;
181 return size;
182}
183
184static int spi_eeprom_write_proc(struct file *file, const char *buffer,
185 unsigned long count, void *data)
186{
187 unsigned int size = MAX_SIZE;
188 int i;
189 if (file->f_pos >= size)
190 return -EIO;
191 if (file->f_pos + count > size)
192 count = size - file->f_pos;
193 for (i = 0; i < count; i += 8) {
194 int len = count - i < 8 ? count - i : 8;
195 if (spi_eeprom_write((int)data, file->f_pos,
196 (unsigned char *)buffer, len) < 0) {
197 count = -EIO;
198 break;
199 }
200 buffer += len;
201 file->f_pos += len;
202 }
203 return count;
204}
205 82
206__init void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) 83int __init spi_eeprom_read(int chipid, int address,
84 unsigned char *buf, int len)
207{ 85{
208 struct proc_dir_entry *entry; 86 int ret;
209 char name[128]; 87 struct read_param param = {
210 sprintf(name, "seeprom-%d", chipid); 88 .chipid = chipid,
211 entry = create_proc_entry(name, 0600, dir); 89 .address = address,
212 if (entry) { 90 .buf = buf,
213 entry->read_proc = spi_eeprom_read_proc; 91 .len = len
214 entry->write_proc = spi_eeprom_write_proc; 92 };
215 entry->data = (void *)chipid; 93
216 } 94 read_param = &param;
95 ret = spi_register_driver(&early_seeprom_driver);
96 if (!ret)
97 spi_unregister_driver(&early_seeprom_driver);
98 return ret;
217} 99}
218#endif /* CONFIG_PROC_FS */
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
deleted file mode 100644
index 08b20cdfd7b3..000000000000
--- a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/errno.h>
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/spinlock.h>
19#include <linux/wait.h>
20#include <asm/tx4938/spi.h>
21#include <asm/tx4938/tx4938.h>
22
23static int (*txx9_spi_cs_func)(int chipid, int on);
24static DEFINE_SPINLOCK(txx9_spi_lock);
25
26extern unsigned int txx9_gbus_clock;
27
28#define SPI_FIFO_SIZE 4
29
30void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on))
31{
32 txx9_spi_cs_func = cs_func;
33 /* enter config mode */
34 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
35}
36
37static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
38
39static irqreturn_t txx9_spi_interrupt(int irq, void *dev_id)
40{
41 /* disable rx intr */
42 tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
43 wake_up(&txx9_spi_wait);
44
45 return IRQ_HANDLED;
46}
47
48static struct irqaction txx9_spi_action = {
49 .handler = txx9_spi_interrupt,
50 .name = "spi",
51};
52
53void __init txx9_spi_irqinit(int irc_irq)
54{
55 setup_irq(irc_irq, &txx9_spi_action);
56}
57
58int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
59 unsigned char **inbufs, unsigned int *incounts,
60 unsigned char **outbufs, unsigned int *outcounts,
61 int cansleep)
62{
63 unsigned int incount, outcount;
64 unsigned char *inp, *outp;
65 int ret;
66 unsigned long flags;
67
68 spin_lock_irqsave(&txx9_spi_lock, flags);
69 if ((tx4938_spiptr->mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE) {
70 spin_unlock_irqrestore(&txx9_spi_lock, flags);
71 return -EBUSY;
72 }
73 /* enter config mode */
74 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
75 tx4938_spiptr->cr0 =
76 (desc->byteorder ? TXx9_SPCR0_SBOS : 0) |
77 (desc->polarity ? TXx9_SPCR0_SPOL : 0) |
78 (desc->phase ? TXx9_SPCR0_SPHA : 0) |
79 0x08;
80 tx4938_spiptr->cr1 =
81 (((TXX9_IMCLK + desc->baud) / (2 * desc->baud) - 1) << 8) |
82 0x08 /* 8 bit only */;
83 /* enter active mode */
84 tx4938_spiptr->mcr = TXx9_SPMCR_ACTIVE;
85 spin_unlock_irqrestore(&txx9_spi_lock, flags);
86
87 /* CS ON */
88 if ((ret = txx9_spi_cs_func(chipid, 1)) < 0) {
89 spin_unlock_irqrestore(&txx9_spi_lock, flags);
90 return ret;
91 }
92 udelay(desc->tcss);
93
94 /* do scatter IO */
95 inp = inbufs ? *inbufs : NULL;
96 outp = outbufs ? *outbufs : NULL;
97 incount = 0;
98 outcount = 0;
99 while (1) {
100 unsigned char data;
101 unsigned int count;
102 int i;
103 if (!incount) {
104 incount = incounts ? *incounts++ : 0;
105 inp = (incount && inbufs) ? *inbufs++ : NULL;
106 }
107 if (!outcount) {
108 outcount = outcounts ? *outcounts++ : 0;
109 outp = (outcount && outbufs) ? *outbufs++ : NULL;
110 }
111 if (!inp && !outp)
112 break;
113 count = SPI_FIFO_SIZE;
114 if (incount)
115 count = min(count, incount);
116 if (outcount)
117 count = min(count, outcount);
118
119 /* now tx must be idle... */
120 while (!(tx4938_spiptr->sr & TXx9_SPSR_SIDLE))
121 ;
122
123 tx4938_spiptr->cr0 =
124 (tx4938_spiptr->cr0 & ~TXx9_SPCR0_RXIFL_MASK) |
125 ((count - 1) << 12);
126 if (cansleep) {
127 /* enable rx intr */
128 tx4938_spiptr->cr0 |= TXx9_SPCR0_RBSIE;
129 }
130 /* send */
131 for (i = 0; i < count; i++)
132 tx4938_spiptr->dr = inp ? *inp++ : 0;
133 /* wait all rx data */
134 if (cansleep) {
135 wait_event(txx9_spi_wait,
136 tx4938_spiptr->sr & TXx9_SPSR_SRRDY);
137 } else {
138 while (!(tx4938_spiptr->sr & TXx9_SPSR_RBSI))
139 ;
140 }
141 /* receive */
142 for (i = 0; i < count; i++) {
143 data = tx4938_spiptr->dr;
144 if (outp)
145 *outp++ = data;
146 }
147 if (incount)
148 incount -= count;
149 if (outcount)
150 outcount -= count;
151 }
152
153 /* CS OFF */
154 udelay(desc->tcsh);
155 txx9_spi_cs_func(chipid, 0);
156 udelay(desc->tcsr);
157
158 spin_lock_irqsave(&txx9_spi_lock, flags);
159 /* enter config mode */
160 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
161 spin_unlock_irqrestore(&txx9_spi_lock, flags);
162
163 return 0;
164}
diff --git a/drivers/char/mem.c b/drivers/char/mem.c
index d2e4cfd79f27..bbee97ff355f 100644
--- a/drivers/char/mem.c
+++ b/drivers/char/mem.c
@@ -75,6 +75,13 @@ static inline int uncached_access(struct file *file, unsigned long addr)
75 * On ia64, we ignore O_SYNC because we cannot tolerate memory attribute aliases. 75 * On ia64, we ignore O_SYNC because we cannot tolerate memory attribute aliases.
76 */ 76 */
77 return !(efi_mem_attributes(addr) & EFI_MEMORY_WB); 77 return !(efi_mem_attributes(addr) & EFI_MEMORY_WB);
78#elif defined(CONFIG_MIPS)
79 {
80 extern int __uncached_access(struct file *file,
81 unsigned long addr);
82
83 return __uncached_access(file, addr);
84 }
78#else 85#else
79 /* 86 /*
80 * Accessing memory above the top the kernel knows about or through a file pointer 87 * Accessing memory above the top the kernel knows about or through a file pointer
diff --git a/drivers/mtd/devices/docprobe.c b/drivers/mtd/devices/docprobe.c
index 78872c3f3760..b96ac8e119dc 100644
--- a/drivers/mtd/devices/docprobe.c
+++ b/drivers/mtd/devices/docprobe.c
@@ -84,7 +84,7 @@ static unsigned long __initdata doc_locations[] = {
84#elif defined(CONFIG_MOMENCO_OCELOT) 84#elif defined(CONFIG_MOMENCO_OCELOT)
85 0x2f000000, 85 0x2f000000,
86 0xff000000, 86 0xff000000,
87#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) 87#elif defined(CONFIG_MOMENCO_OCELOT_G)
88 0xff000000, 88 0xff000000,
89##else 89##else
90#warning Unknown architecture for DiskOnChip. No default probe locations defined 90#warning Unknown architecture for DiskOnChip. No default probe locations defined
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index b665e4ac2208..f88ebc5b685e 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -258,12 +258,6 @@ config MTD_TSUNAMI
258 help 258 help
259 Support for the flash chip on Tsunami TIG bus. 259 Support for the flash chip on Tsunami TIG bus.
260 260
261config MTD_LASAT
262 tristate "LASAT flash device"
263 depends on LASAT && MTD_CFI
264 help
265 Support for the flash chips on the Lasat 100 and 200 boards.
266
267config MTD_NETtel 261config MTD_NETtel
268 tristate "CFI flash device on SnapGear/SecureEdge" 262 tristate "CFI flash device on SnapGear/SecureEdge"
269 depends on X86 && MTD_PARTITIONS && MTD_JEDECPROBE 263 depends on X86 && MTD_PARTITIONS && MTD_JEDECPROBE
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 3acbb5d01ca4..970b189271a2 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -47,7 +47,6 @@ obj-$(CONFIG_MTD_OCELOT) += ocelot.o
47obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o 47obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
48obj-$(CONFIG_MTD_PCI) += pci.o 48obj-$(CONFIG_MTD_PCI) += pci.o
49obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o 49obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o
50obj-$(CONFIG_MTD_LASAT) += lasat.o
51obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o 50obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o
52obj-$(CONFIG_MTD_EDB7312) += edb7312.o 51obj-$(CONFIG_MTD_EDB7312) += edb7312.o
53obj-$(CONFIG_MTD_IMPA7) += impa7.o 52obj-$(CONFIG_MTD_IMPA7) += impa7.o
diff --git a/drivers/mtd/maps/lasat.c b/drivers/mtd/maps/lasat.c
deleted file mode 100644
index e34376321050..000000000000
--- a/drivers/mtd/maps/lasat.c
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * Flash device on Lasat 100 and 200 boards
3 *
4 * (C) 2002 Brian Murphy <brian@murphy.dk>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * $Id: lasat.c,v 1.9 2004/11/04 13:24:15 gleixner Exp $
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <asm/io.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/map.h>
21#include <linux/mtd/partitions.h>
22#include <asm/lasat/lasat.h>
23
24static struct mtd_info *lasat_mtd;
25
26static struct mtd_partition partition_info[LASAT_MTD_LAST];
27static char *lasat_mtd_partnames[] = {"Bootloader", "Service", "Normal", "Filesystem", "Config"};
28
29static void lasat_set_vpp(struct map_info *map, int vpp)
30{
31 if (vpp)
32 *lasat_misc->flash_wp_reg |= 1 << lasat_misc->flash_wp_bit;
33 else
34 *lasat_misc->flash_wp_reg &= ~(1 << lasat_misc->flash_wp_bit);
35}
36
37static struct map_info lasat_map = {
38 .name = "LASAT flash",
39 .bankwidth = 4,
40 .set_vpp = lasat_set_vpp
41};
42
43static int __init init_lasat(void)
44{
45 int i;
46 /* since we use AMD chips and set_vpp is not implimented
47 * for these (yet) we still have to permanently enable flash write */
48 printk(KERN_NOTICE "Unprotecting flash\n");
49 ENABLE_VPP((&lasat_map));
50
51 lasat_map.phys = lasat_flash_partition_start(LASAT_MTD_BOOTLOADER);
52 lasat_map.virt = ioremap_nocache(
53 lasat_map.phys, lasat_board_info.li_flash_size);
54 lasat_map.size = lasat_board_info.li_flash_size;
55
56 simple_map_init(&lasat_map);
57
58 for (i=0; i < LASAT_MTD_LAST; i++)
59 partition_info[i].name = lasat_mtd_partnames[i];
60
61 lasat_mtd = do_map_probe("cfi_probe", &lasat_map);
62
63 if (!lasat_mtd)
64 lasat_mtd = do_map_probe("jedec_probe", &lasat_map);
65
66 if (lasat_mtd) {
67 u32 size, offset = 0;
68
69 lasat_mtd->owner = THIS_MODULE;
70
71 for (i=0; i < LASAT_MTD_LAST; i++) {
72 size = lasat_flash_partition_size(i);
73 partition_info[i].size = size;
74 partition_info[i].offset = offset;
75 offset += size;
76 }
77
78 add_mtd_partitions( lasat_mtd, partition_info, LASAT_MTD_LAST );
79 return 0;
80 }
81
82 iounmap(lasat_map.virt);
83 return -ENXIO;
84}
85
86static void __exit cleanup_lasat(void)
87{
88 if (lasat_mtd) {
89 del_mtd_partitions(lasat_mtd);
90 map_destroy(lasat_mtd);
91 }
92 if (lasat_map.virt) {
93 iounmap(lasat_map.virt);
94 lasat_map.virt = 0;
95 }
96}
97
98module_init(init_lasat);
99module_exit(cleanup_lasat);
100
101MODULE_LICENSE("GPL");
102MODULE_AUTHOR("Brian Murphy <brian@murphy.dk>");
103MODULE_DESCRIPTION("Lasat Safepipe/Masquerade MTD map driver");
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c
index 595208f965a5..17c868034aad 100644
--- a/drivers/mtd/nand/diskonchip.c
+++ b/drivers/mtd/nand/diskonchip.c
@@ -59,7 +59,7 @@ static unsigned long __initdata doc_locations[] = {
59#elif defined(CONFIG_MOMENCO_OCELOT) 59#elif defined(CONFIG_MOMENCO_OCELOT)
60 0x2f000000, 60 0x2f000000,
61 0xff000000, 61 0xff000000,
62#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) 62#elif defined(CONFIG_MOMENCO_OCELOT_G)
63 0xff000000, 63 0xff000000,
64#else 64#else
65#warning Unknown architecture for DiskOnChip. No default probe locations defined 65#warning Unknown architecture for DiskOnChip. No default probe locations defined
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 5cc3d517e39b..627316db3744 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2307,7 +2307,7 @@ config UGETH_TX_ON_DEMAND
2307 2307
2308config MV643XX_ETH 2308config MV643XX_ETH
2309 tristate "MV-643XX Ethernet support" 2309 tristate "MV-643XX Ethernet support"
2310 depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MV64X60 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32) 2310 depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32)
2311 select MII 2311 select MII
2312 help 2312 help
2313 This driver supports the gigabit Ethernet on the Marvell MV643XX 2313 This driver supports the gigabit Ethernet on the Marvell MV643XX
diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c
index 463d600ed83d..75655add3f34 100644
--- a/drivers/net/tc35815.c
+++ b/drivers/net/tc35815.c
@@ -23,9 +23,9 @@
23 */ 23 */
24 24
25#ifdef TC35815_NAPI 25#ifdef TC35815_NAPI
26#define DRV_VERSION "1.35-NAPI" 26#define DRV_VERSION "1.36-NAPI"
27#else 27#else
28#define DRV_VERSION "1.35" 28#define DRV_VERSION "1.36"
29#endif 29#endif
30static const char *version = "tc35815.c:v" DRV_VERSION "\n"; 30static const char *version = "tc35815.c:v" DRV_VERSION "\n";
31#define MODNAME "tc35815" 31#define MODNAME "tc35815"
@@ -49,6 +49,7 @@ static const char *version = "tc35815.c:v" DRV_VERSION "\n";
49#include <linux/pci.h> 49#include <linux/pci.h>
50#include <linux/mii.h> 50#include <linux/mii.h>
51#include <linux/ethtool.h> 51#include <linux/ethtool.h>
52#include <linux/platform_device.h>
52#include <asm/io.h> 53#include <asm/io.h>
53#include <asm/byteorder.h> 54#include <asm/byteorder.h>
54 55
@@ -597,13 +598,46 @@ static int tc_mdio_read(struct net_device *dev, int phy_id, int location);
597static void tc_mdio_write(struct net_device *dev, int phy_id, int location, 598static void tc_mdio_write(struct net_device *dev, int phy_id, int location,
598 int val); 599 int val);
599 600
600static void __devinit tc35815_init_dev_addr (struct net_device *dev) 601#ifdef CONFIG_CPU_TX49XX
602/*
603 * Find a platform_device providing a MAC address. The platform code
604 * should provide a "tc35815-mac" device with a MAC address in its
605 * platform_data.
606 */
607static int __devinit tc35815_mac_match(struct device *dev, void *data)
608{
609 struct platform_device *plat_dev = to_platform_device(dev);
610 struct pci_dev *pci_dev = data;
611 unsigned int id = (pci_dev->bus->number << 8) | pci_dev->devfn;
612 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
613}
614
615static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
616{
617 struct tc35815_local *lp = dev->priv;
618 struct device *pd = bus_find_device(&platform_bus_type, NULL,
619 lp->pci_dev, tc35815_mac_match);
620 if (pd) {
621 if (pd->platform_data)
622 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
623 put_device(pd);
624 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
625 }
626 return -ENODEV;
627}
628#else
629static int __devinit tc35815_read_plat_dev_addr(struct device *dev)
630{
631 return -ENODEV;
632}
633#endif
634
635static int __devinit tc35815_init_dev_addr (struct net_device *dev)
601{ 636{
602 struct tc35815_regs __iomem *tr = 637 struct tc35815_regs __iomem *tr =
603 (struct tc35815_regs __iomem *)dev->base_addr; 638 (struct tc35815_regs __iomem *)dev->base_addr;
604 int i; 639 int i;
605 640
606 /* dev_addr will be overwritten on NETDEV_REGISTER event */
607 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) 641 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
608 ; 642 ;
609 for (i = 0; i < 6; i += 2) { 643 for (i = 0; i < 6; i += 2) {
@@ -615,6 +649,9 @@ static void __devinit tc35815_init_dev_addr (struct net_device *dev)
615 dev->dev_addr[i] = data & 0xff; 649 dev->dev_addr[i] = data & 0xff;
616 dev->dev_addr[i+1] = data >> 8; 650 dev->dev_addr[i+1] = data >> 8;
617 } 651 }
652 if (!is_valid_ether_addr(dev->dev_addr))
653 return tc35815_read_plat_dev_addr(dev);
654 return 0;
618} 655}
619 656
620static int __devinit tc35815_init_one (struct pci_dev *pdev, 657static int __devinit tc35815_init_one (struct pci_dev *pdev,
@@ -724,7 +761,10 @@ static int __devinit tc35815_init_one (struct pci_dev *pdev,
724 tc35815_chip_reset(dev); 761 tc35815_chip_reset(dev);
725 762
726 /* Retrieve the ethernet address. */ 763 /* Retrieve the ethernet address. */
727 tc35815_init_dev_addr(dev); 764 if (tc35815_init_dev_addr(dev)) {
765 dev_warn(&pdev->dev, "not valid ether addr\n");
766 random_ether_addr(dev->dev_addr);
767 }
728 768
729 rc = register_netdev (dev); 769 rc = register_netdev (dev);
730 if (rc) 770 if (rc)
diff --git a/drivers/tc/zs.c b/drivers/tc/zs.c
index 61de78a9f6ee..4fff61b32dcb 100644
--- a/drivers/tc/zs.c
+++ b/drivers/tc/zs.c
@@ -143,7 +143,7 @@ static struct console sercons;
143static unsigned long break_pressed; /* break, really ... */ 143static unsigned long break_pressed; /* break, really ... */
144#endif 144#endif
145 145
146static unsigned char zs_init_regs[16] __initdata = { 146static unsigned char zs_init_regs[16] = {
147 0, /* write 0 */ 147 0, /* write 0 */
148 0, /* write 1 */ 148 0, /* write 1 */
149 0, /* write 2 */ 149 0, /* write 2 */
@@ -1581,7 +1581,7 @@ static void __init show_serial_version(void)
1581/* Initialize Z8530s zs_channels 1581/* Initialize Z8530s zs_channels
1582 */ 1582 */
1583 1583
1584static void __init probe_sccs(void) 1584static void probe_sccs(void)
1585{ 1585{
1586 struct dec_serial **pp; 1586 struct dec_serial **pp;
1587 int i, n, n_chips = 0, n_channels, chip, channel; 1587 int i, n, n_chips = 0, n_channels, chip, channel;
@@ -1923,7 +1923,7 @@ static struct tty_driver *serial_console_device(struct console *c, int *index)
1923 * - initialize the serial port 1923 * - initialize the serial port
1924 * Return non-zero if we didn't find a serial port. 1924 * Return non-zero if we didn't find a serial port.
1925 */ 1925 */
1926static int __init serial_console_setup(struct console *co, char *options) 1926static int serial_console_setup(struct console *co, char *options)
1927{ 1927{
1928 struct dec_serial *info; 1928 struct dec_serial *info;
1929 int baud = 9600; 1929 int baud = 9600;
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 964c5eddc21b..0b3ff9c48409 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -129,29 +129,12 @@
129#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ 129#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \
130 ((cm)<<59) | (a)) 130 ((cm)<<59) | (a))
131 131
132#if defined (CONFIG_CPU_R4300) \ 132/*
133 || defined (CONFIG_CPU_R4X00) \ 133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
134 || defined (CONFIG_CPU_R5000) \ 134 * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
135 || defined (CONFIG_CPU_RM7000) \ 135 * R8000 implements most with its 48-bit physical address space.
136 || defined (CONFIG_CPU_RM9000) \ 136 */
137 || defined (CONFIG_CPU_NEVADA) \ 137#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
138 || defined (CONFIG_CPU_TX49XX) \
139 || defined (CONFIG_CPU_MIPS64)
140#define TO_PHYS_MASK _CONST64_(0x0000000fffffffff) /* 2^^36 - 1 */
141#endif
142
143#if defined (CONFIG_CPU_R8000)
144/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
145#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */
146#endif
147
148#if defined (CONFIG_CPU_R10000)
149#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */
150#endif
151
152#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
153#define TO_PHYS_MASK _CONST64_(0x00000fffffffffff) /* 2^^44 - 1 */
154#endif
155 138
156#ifndef CONFIG_CPU_R8000 139#ifndef CONFIG_CPU_R8000
157 140
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b0c329783ac5..087126a5faf9 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -109,18 +109,12 @@
109#define MACH_COSINE_ORION 0 109#define MACH_COSINE_ORION 0
110 110
111/* 111/*
112 * Valid machtype for group GALILEO
113 */
114#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */
115#define MACH_EV64120A 0 /* EV64120A */
116
117/*
118 * Valid machtype for group MOMENCO 112 * Valid machtype for group MOMENCO
119 */ 113 */
120#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ 114#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */
121#define MACH_MOMENCO_OCELOT 0 115#define MACH_MOMENCO_OCELOT 0
122#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ 116#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */
123#define MACH_MOMENCO_OCELOT_C 2 117#define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */
124#define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */ 118#define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */
125#define MACH_MOMENCO_OCELOT_3 4 119#define MACH_MOMENCO_OCELOT_3 4
126 120
@@ -194,13 +188,6 @@
194#define MACH_HP_LASERJET 1 188#define MACH_HP_LASERJET 1
195 189
196/* 190/*
197 * Valid machtype for group LASAT
198 */
199#define MACH_GROUP_LASAT 21
200#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
201#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
202
203/*
204 * Valid machtype for group TITAN 191 * Valid machtype for group TITAN
205 */ 192 */
206#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ 193#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
@@ -213,6 +200,27 @@
213#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ 200#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
214#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ 201#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
215 202
203/*
204 * Valid machtype for group LEMOTE
205 */
206#define MACH_GROUP_LEMOTE 27
207#define MACH_LEMOTE_FULONG 0
208
209/*
210 * Valid machtype for group PMC-MSP
211 */
212#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */
213#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
214#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */
215#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */
216#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */
217#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */
218#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
219#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
220
221#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */
222#define MACH_WRPPMC 1
223
216#define CL_SIZE COMMAND_LINE_SIZE 224#define CL_SIZE COMMAND_LINE_SIZE
217 225
218const char *get_system_type(void); 226const char *get_system_type(void);
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index c4a1ec31ff6a..df7f2deb3b56 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -20,7 +20,11 @@
20#define Index_Load_Tag_D 0x05 20#define Index_Load_Tag_D 0x05
21#define Index_Store_Tag_I 0x08 21#define Index_Store_Tag_I 0x08
22#define Index_Store_Tag_D 0x09 22#define Index_Store_Tag_D 0x09
23#if defined(CONFIG_CPU_LOONGSON2)
24#define Hit_Invalidate_I 0x00
25#else
23#define Hit_Invalidate_I 0x10 26#define Hit_Invalidate_I 0x10
27#endif
24#define Hit_Invalidate_D 0x11 28#define Hit_Invalidate_D 0x11
25#define Hit_Writeback_Inv_D 0x15 29#define Hit_Writeback_Inv_D 0x15
26 30
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 5e4bed123b48..d95a83e3e1d7 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -150,6 +150,10 @@
150#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 150#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
151#endif 151#endif
152 152
153#ifndef cpu_has_userlocal
154#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
155#endif
156
153#ifdef CONFIG_32BIT 157#ifdef CONFIG_32BIT
154# ifndef cpu_has_nofpuex 158# ifndef cpu_has_nofpuex
155# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 159# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 2924069075e0..3857358fb6de 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -89,6 +89,8 @@
89#define PRID_IMP_34K 0x9500 89#define PRID_IMP_34K 0x9500
90#define PRID_IMP_24KE 0x9600 90#define PRID_IMP_24KE 0x9600
91#define PRID_IMP_74K 0x9700 91#define PRID_IMP_74K 0x9700
92#define PRID_IMP_LOONGSON1 0x4200
93#define PRID_IMP_LOONGSON2 0x6300
92 94
93/* 95/*
94 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 96 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -107,6 +109,7 @@
107 * Definitions for 7:0 on legacy processors 109 * Definitions for 7:0 on legacy processors
108 */ 110 */
109 111
112#define PRID_REV_MASK 0x00ff
110 113
111#define PRID_REV_TX4927 0x0022 114#define PRID_REV_TX4927 0x0022
112#define PRID_REV_TX4937 0x0030 115#define PRID_REV_TX4937 0x0030
@@ -123,6 +126,7 @@
123#define PRID_REV_VR4122 0x0070 126#define PRID_REV_VR4122 0x0070
124#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 127#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
125#define PRID_REV_VR4130 0x0080 128#define PRID_REV_VR4130 0x0080
129#define PRID_REV_34K_V1_0_2 0x0022
126 130
127/* 131/*
128 * Older processors used to encode processor version and revision in two 132 * Older processors used to encode processor version and revision in two
@@ -211,7 +215,10 @@
211#define CPU_SB1A 62 215#define CPU_SB1A 62
212#define CPU_74K 63 216#define CPU_74K 63
213#define CPU_R14000 64 217#define CPU_R14000 64
214#define CPU_LAST 64 218#define CPU_LOONGSON1 65
219#define CPU_LOONGSON2 66
220
221#define CPU_LAST 66
215 222
216/* 223/*
217 * ISA Level encodings 224 * ISA Level encodings
@@ -257,6 +264,7 @@
257#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ 264#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */
258#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ 265#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */
259#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ 266#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
267#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */
260 268
261/* 269/*
262 * CPU ASE encodings 270 * CPU ASE encodings
diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h
index 66189f5f6399..716371bd0980 100644
--- a/include/asm-mips/div64.h
+++ b/include/asm-mips/div64.h
@@ -20,7 +20,7 @@
20 */ 20 */
21 21
22#define do_div64_32(res, high, low, base) ({ \ 22#define do_div64_32(res, high, low, base) ({ \
23 unsigned long __quot, __mod; \ 23 unsigned long __quot32, __mod32; \
24 unsigned long __cf, __tmp, __tmp2, __i; \ 24 unsigned long __cf, __tmp, __tmp2, __i; \
25 \ 25 \
26 __asm__(".set push\n\t" \ 26 __asm__(".set push\n\t" \
@@ -48,12 +48,13 @@
48 "bnez %4, 0b\n\t" \ 48 "bnez %4, 0b\n\t" \
49 " srl %5, %1, 0x1f\n\t" \ 49 " srl %5, %1, 0x1f\n\t" \
50 ".set pop" \ 50 ".set pop" \
51 : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \ 51 : "=&r" (__mod32), "=&r" (__tmp), \
52 "=&r" (__quot32), "=&r" (__cf), \
52 "=&r" (__i), "=&r" (__tmp2) \ 53 "=&r" (__i), "=&r" (__tmp2) \
53 : "Jr" (base), "0" (high), "1" (low)); \ 54 : "Jr" (base), "0" (high), "1" (low)); \
54 \ 55 \
55 (res) = __quot; \ 56 (res) = __quot32; \
56 __mod; }) 57 __mod32; })
57 58
58#define do_div(n, base) ({ \ 59#define do_div(n, base) ({ \
59 unsigned long long __quot; \ 60 unsigned long long __quot; \
diff --git a/include/asm-mips/gpio.h b/include/asm-mips/gpio.h
new file mode 100644
index 000000000000..06e46faf862d
--- /dev/null
+++ b/include/asm-mips/gpio.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_MIPS_GPIO_H
2#define __ASM_MIPS_GPIO_H
3
4#include <gpio.h>
5
6#endif /* __ASM_MIPS_GPIO_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 92ec2618560c..12bcc1f9fba9 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -178,6 +178,11 @@ extern void __iounmap(const volatile void __iomem *addr);
178static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, 178static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
179 unsigned long flags) 179 unsigned long flags)
180{ 180{
181 void __iomem *addr = plat_ioremap(offset, size, flags);
182
183 if (addr)
184 return addr;
185
181#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) 186#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
182 187
183 if (cpu_has_64bit_addresses) { 188 if (cpu_has_64bit_addresses) {
@@ -282,6 +287,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
282 287
283static inline void iounmap(const volatile void __iomem *addr) 288static inline void iounmap(const volatile void __iomem *addr)
284{ 289{
290 if (plat_iounmap(addr))
291 return;
292
285#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) 293#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
286 294
287 if (cpu_has_64bit_addresses || 295 if (cpu_has_64bit_addresses ||
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h
deleted file mode 100644
index edcd7544b358..000000000000
--- a/include/asm-mips/lasat/ds1603.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#include <asm/addrspace.h>
2
3/* Lasat 100 */
4#define DS1603_REG_100 (KSEG1ADDR(0x1c810000))
5#define DS1603_RST_100 (1 << 2)
6#define DS1603_CLK_100 (1 << 0)
7#define DS1603_DATA_SHIFT_100 1
8#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100)
9
10/* Lasat 200 */
11#define DS1603_REG_200 (KSEG1ADDR(0x11000000))
12#define DS1603_RST_200 (1 << 3)
13#define DS1603_CLK_200 (1 << 4)
14#define DS1603_DATA_200 (1 << 5)
15
16#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000)
17#define DS1603_DATA_READ_SHIFT_200 9
18#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h
deleted file mode 100644
index 7b53edd5cd5f..000000000000
--- a/include/asm-mips/lasat/eeprom.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#include <asm/addrspace.h>
2
3/* lasat 100 */
4#define AT93C_REG_100 KSEG1ADDR(0x1c810000)
5#define AT93C_RDATA_REG_100 AT93C_REG_100
6#define AT93C_RDATA_SHIFT_100 4
7#define AT93C_WDATA_SHIFT_100 4
8#define AT93C_CS_M_100 ( 1 << 5 )
9#define AT93C_CLK_M_100 ( 1 << 3 )
10
11/* lasat 200 */
12#define AT93C_REG_200 KSEG1ADDR(0x11000000)
13#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000)
14#define AT93C_RDATA_SHIFT_200 8
15#define AT93C_WDATA_SHIFT_200 2
16#define AT93C_CS_M_200 ( 1 << 0 )
17#define AT93C_CLK_M_200 ( 1 << 1 )
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h
deleted file mode 100644
index f5589f31a197..000000000000
--- a/include/asm-mips/lasat/head.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Image header stuff
3 */
4#ifndef _HEAD_H
5#define _HEAD_H
6
7#define LASAT_K_MAGIC0_VAL 0xfedeabba
8#define LASAT_K_MAGIC1_VAL 0x00bedead
9
10#ifndef _LANGUAGE_ASSEMBLY
11#include <linux/types.h>
12struct bootloader_header {
13 u32 magic[2];
14 u32 version;
15 u32 image_start;
16 u32 image_size;
17 u32 kernel_start;
18 u32 kernel_entry;
19};
20#endif
21
22#endif /* _HEAD_H */
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
deleted file mode 100644
index 42077e367a5b..000000000000
--- a/include/asm-mips/lasat/lasat.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * lasat.h
3 *
4 * Thomas Horsten <thh@lasat.com>
5 * Copyright (C) 2000 LASAT Networks A/S.
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * Configuration for LASAT boards, loads the appropriate include files.
21 */
22#ifndef _LASAT_H
23#define _LASAT_H
24
25#ifndef _LANGUAGE_ASSEMBLY
26
27extern struct lasat_misc {
28 volatile u32 *reset_reg;
29 volatile u32 *flash_wp_reg;
30 u32 flash_wp_bit;
31} *lasat_misc;
32
33enum lasat_mtdparts {
34 LASAT_MTD_BOOTLOADER,
35 LASAT_MTD_SERVICE,
36 LASAT_MTD_NORMAL,
37 LASAT_MTD_CONFIG,
38 LASAT_MTD_FS,
39 LASAT_MTD_LAST
40};
41
42/*
43 * The format of the data record in the EEPROM.
44 * See Documentation/LASAT/eeprom.txt for a detailed description
45 * of the fields in this struct, and the LASAT Hardware Configuration
46 * field specification for a detailed description of the config
47 * field.
48 */
49#include <linux/types.h>
50
51#define LASAT_EEPROM_VERSION 7
52struct lasat_eeprom_struct {
53 unsigned int version;
54 unsigned int cfg[3];
55 unsigned char hwaddr[6];
56 unsigned char print_partno[12];
57 unsigned char term0;
58 unsigned char print_serial[14];
59 unsigned char term1;
60 unsigned char prod_partno[12];
61 unsigned char term2;
62 unsigned char prod_serial[14];
63 unsigned char term3;
64 unsigned char passwd_hash[16];
65 unsigned char pwdnull;
66 unsigned char vendid;
67 unsigned char ts_ref;
68 unsigned char ts_signoff;
69 unsigned char reserved[11];
70 unsigned char debugaccess;
71 unsigned short prid;
72 unsigned int serviceflag;
73 unsigned int ipaddr;
74 unsigned int netmask;
75 unsigned int crc32;
76};
77
78struct lasat_eeprom_struct_pre7 {
79 unsigned int version;
80 unsigned int flags[3];
81 unsigned char hwaddr0[6];
82 unsigned char hwaddr1[6];
83 unsigned char print_partno[9];
84 unsigned char term0;
85 unsigned char print_serial[14];
86 unsigned char term1;
87 unsigned char prod_partno[9];
88 unsigned char term2;
89 unsigned char prod_serial[14];
90 unsigned char term3;
91 unsigned char passwd_hash[24];
92 unsigned char pwdnull;
93 unsigned char vendor;
94 unsigned char ts_ref;
95 unsigned char ts_signoff;
96 unsigned char reserved[6];
97 unsigned int writecount;
98 unsigned int ipaddr;
99 unsigned int netmask;
100 unsigned int crc32;
101};
102
103/* Configuration descriptor encoding - see the doc for details */
104
105#define LASAT_W0_DSCTYPE(v) ( ( (v) ) & 0xf )
106#define LASAT_W0_BMID(v) ( ( (v) >> 0x04 ) & 0xf )
107#define LASAT_W0_CPUTYPE(v) ( ( (v) >> 0x08 ) & 0xf )
108#define LASAT_W0_BUSSPEED(v) ( ( (v) >> 0x0c ) & 0xf )
109#define LASAT_W0_CPUCLK(v) ( ( (v) >> 0x10 ) & 0xf )
110#define LASAT_W0_SDRAMBANKSZ(v) ( ( (v) >> 0x14 ) & 0xf )
111#define LASAT_W0_SDRAMBANKS(v) ( ( (v) >> 0x18 ) & 0xf )
112#define LASAT_W0_L2CACHE(v) ( ( (v) >> 0x1c ) & 0xf )
113
114#define LASAT_W1_EDHAC(v) ( ( (v) ) & 0xf )
115#define LASAT_W1_HIFN(v) ( ( (v) >> 0x04 ) & 0x1 )
116#define LASAT_W1_ISDN(v) ( ( (v) >> 0x05 ) & 0x1 )
117#define LASAT_W1_IDE(v) ( ( (v) >> 0x06 ) & 0x1 )
118#define LASAT_W1_HDLC(v) ( ( (v) >> 0x07 ) & 0x1 )
119#define LASAT_W1_USVERSION(v) ( ( (v) >> 0x08 ) & 0x1 )
120#define LASAT_W1_4MACS(v) ( ( (v) >> 0x09 ) & 0x1 )
121#define LASAT_W1_EXTSERIAL(v) ( ( (v) >> 0x0a ) & 0x1 )
122#define LASAT_W1_FLASHSIZE(v) ( ( (v) >> 0x0c ) & 0xf )
123#define LASAT_W1_PCISLOTS(v) ( ( (v) >> 0x10 ) & 0xf )
124#define LASAT_W1_PCI1OPT(v) ( ( (v) >> 0x14 ) & 0xf )
125#define LASAT_W1_PCI2OPT(v) ( ( (v) >> 0x18 ) & 0xf )
126#define LASAT_W1_PCI3OPT(v) ( ( (v) >> 0x1c ) & 0xf )
127
128/* Routines specific to LASAT boards */
129
130#define LASAT_BMID_MASQUERADE2 0
131#define LASAT_BMID_MASQUERADEPRO 1
132#define LASAT_BMID_SAFEPIPE25 2
133#define LASAT_BMID_SAFEPIPE50 3
134#define LASAT_BMID_SAFEPIPE100 4
135#define LASAT_BMID_SAFEPIPE5000 5
136#define LASAT_BMID_SAFEPIPE7000 6
137#define LASAT_BMID_SAFEPIPE1000 7
138//#define LASAT_BMID_SAFEPIPE30 7
139//#define LASAT_BMID_SAFEPIPE5100 8
140//#define LASAT_BMID_SAFEPIPE7100 9
141#define LASAT_BMID_UNKNOWN 0xf
142#define LASAT_MAX_BMID_NAMES 9 // no larger than 15!
143
144#define LASAT_HAS_EDHAC ( 1 << 0 )
145#define LASAT_EDHAC_FAST ( 1 << 1 )
146#define LASAT_HAS_EADI ( 1 << 2 )
147#define LASAT_HAS_HIFN ( 1 << 3 )
148#define LASAT_HAS_ISDN ( 1 << 4 )
149#define LASAT_HAS_LEASEDLINE_IF ( 1 << 5 )
150#define LASAT_HAS_HDC ( 1 << 6 )
151
152#define LASAT_PRID_MASQUERADE2 0
153#define LASAT_PRID_MASQUERADEPRO 1
154#define LASAT_PRID_SAFEPIPE25 2
155#define LASAT_PRID_SAFEPIPE50 3
156#define LASAT_PRID_SAFEPIPE100 4
157#define LASAT_PRID_SAFEPIPE5000 5
158#define LASAT_PRID_SAFEPIPE7000 6
159#define LASAT_PRID_SAFEPIPE30 7
160#define LASAT_PRID_SAFEPIPE5100 8
161#define LASAT_PRID_SAFEPIPE7100 9
162
163#define LASAT_PRID_SAFEPIPE1110 10
164#define LASAT_PRID_SAFEPIPE3020 11
165#define LASAT_PRID_SAFEPIPE3030 12
166#define LASAT_PRID_SAFEPIPE5020 13
167#define LASAT_PRID_SAFEPIPE5030 14
168#define LASAT_PRID_SAFEPIPE1120 15
169#define LASAT_PRID_SAFEPIPE1130 16
170#define LASAT_PRID_SAFEPIPE6010 17
171#define LASAT_PRID_SAFEPIPE6110 18
172#define LASAT_PRID_SAFEPIPE6210 19
173#define LASAT_PRID_SAFEPIPE1020 20
174#define LASAT_PRID_SAFEPIPE1040 21
175#define LASAT_PRID_SAFEPIPE1060 22
176
177struct lasat_info {
178 unsigned int li_cpu_hz;
179 unsigned int li_bus_hz;
180 unsigned int li_bmid;
181 unsigned int li_memsize;
182 unsigned int li_flash_size;
183 unsigned int li_prid;
184 unsigned char li_bmstr[16];
185 unsigned char li_namestr[32];
186 unsigned char li_typestr[16];
187 /* Info on the Flash layout */
188 unsigned int li_flash_base;
189 unsigned long li_flashpart_base[LASAT_MTD_LAST];
190 unsigned long li_flashpart_size[LASAT_MTD_LAST];
191 struct lasat_eeprom_struct li_eeprom_info;
192 unsigned int li_eeprom_upgrade_version;
193 unsigned int li_debugaccess;
194};
195
196extern struct lasat_info lasat_board_info;
197
198static inline unsigned long lasat_flash_partition_start(int partno)
199{
200 if (partno < 0 || partno >= LASAT_MTD_LAST)
201 return 0;
202
203 return lasat_board_info.li_flashpart_base[partno];
204}
205
206static inline unsigned long lasat_flash_partition_size(int partno)
207{
208 if (partno < 0 || partno >= LASAT_MTD_LAST)
209 return 0;
210
211 return lasat_board_info.li_flashpart_size[partno];
212}
213
214/* Called from setup() to initialize the global board_info struct */
215extern int lasat_init_board_info(void);
216
217/* Write the modified EEPROM info struct */
218extern void lasat_write_eeprom_info(void);
219
220#define N_MACHTYPES 2
221/* for calibration of delays */
222
223/* the lasat_ndelay function is necessary because it is used at an
224 * early stage of the boot process where ndelay is not calibrated.
225 * It is used for the bit-banging rtc and eeprom drivers */
226
227#include <asm/delay.h>
228/* calculating with the slowest board with 100 MHz clock */
229#define LASAT_100_DIVIDER 20
230/* All 200's run at 250 MHz clock */
231#define LASAT_200_DIVIDER 8
232
233extern unsigned int lasat_ndelay_divider;
234
235static inline void lasat_ndelay(unsigned int ns)
236{
237 __delay(ns / lasat_ndelay_divider);
238}
239
240#endif /* !defined (_LANGUAGE_ASSEMBLY) */
241
242#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
243#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba
244
245/* Lasat 100 boards */
246#define LASAT_GT_BASE (KSEG1ADDR(0x14000000))
247
248/* Lasat 200 boards */
249#define Vrc5074_PHYS_BASE 0x1fa00000
250#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE))
251#define PCI_WINDOW1 0x1a000000
252
253#endif /* _LASAT_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
deleted file mode 100644
index 065474feeccc..000000000000
--- a/include/asm-mips/lasat/lasatint.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#define LASATINT_END 16
2
3/* lasat 100 */
4#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
5#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
6#define LASATINT_MASK_SHIFT_100 0
7
8/* lasat 200 */
9#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c))
10#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c))
11#define LASATINT_MASK_SHIFT_200 16
12
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h
deleted file mode 100644
index 42a492edc40e..000000000000
--- a/include/asm-mips/lasat/picvue.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* Lasat 100 */
2#define PVC_REG_100 KSEG1ADDR(0x1c820000)
3#define PVC_DATA_SHIFT_100 0
4#define PVC_DATA_M_100 0xFF
5#define PVC_E_100 (1 << 8)
6#define PVC_RW_100 (1 << 9)
7#define PVC_RS_100 (1 << 10)
8
9/* Lasat 200 */
10#define PVC_REG_200 KSEG1ADDR(0x11000000)
11#define PVC_DATA_SHIFT_200 24
12#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200)
13#define PVC_E_200 (1 << 16)
14#define PVC_RW_200 (1 << 17)
15#define PVC_RS_200 (1 << 18)
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
deleted file mode 100644
index 9e88c7669c7a..000000000000
--- a/include/asm-mips/lasat/serial.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#include <asm/lasat/lasat.h>
2
3/* Lasat 100 boards serial configuration */
4#define LASAT_BASE_BAUD_100 ( 7372800 / 16 )
5#define LASAT_UART_REGS_BASE_100 0x1c8b0000
6#define LASAT_UART_REGS_SHIFT_100 2
7#define LASATINT_UART_100 8
8
9/* * LASAT 200 boards serial configuration */
10#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
11#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
12#define LASAT_UART_REGS_SHIFT_200 3
13#define LASATINT_UART_200 13
diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
deleted file mode 100644
index 27911e054ffc..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_gpio.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __AU1XXX_GPIO_H
2#define __AU1XXX_GPIO_H
3
4void au1xxx_gpio1_set_inputs(void);
5void au1xxx_gpio_tristate(int signal);
6void au1xxx_gpio_write(int signal, int value);
7int au1xxx_gpio_read(int signal);
8
9typedef volatile struct
10{
11 u32 dir;
12 u32 reserved;
13 u32 output;
14 u32 pinstate;
15 u32 inten;
16 u32 enable;
17
18} AU1X00_GPIO2;
19
20#endif //__AU1XXX_GPIO_H
diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h
new file mode 100644
index 000000000000..2dc61e009a08
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/gpio.h
@@ -0,0 +1,69 @@
1#ifndef _AU1XXX_GPIO_H_
2#define _AU1XXX_GPIO_H_
3
4#include <linux/types.h>
5
6#define AU1XXX_GPIO_BASE 200
7
8struct au1x00_gpio2 {
9 u32 dir;
10 u32 reserved;
11 u32 output;
12 u32 pinstate;
13 u32 inten;
14 u32 enable;
15};
16
17extern int au1xxx_gpio_get_value(unsigned gpio);
18extern void au1xxx_gpio_set_value(unsigned gpio, int value);
19extern int au1xxx_gpio_direction_input(unsigned gpio);
20extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
21
22
23/* Wrappers for the arch-neutral GPIO API */
24
25static inline int gpio_request(unsigned gpio, const char *label)
26{
27 /* Not yet implemented */
28 return 0;
29}
30
31static inline void gpio_free(unsigned gpio)
32{
33 /* Not yet implemented */
34}
35
36static inline int gpio_direction_input(unsigned gpio)
37{
38 return au1xxx_gpio_direction_input(gpio);
39}
40
41static inline int gpio_direction_output(unsigned gpio, int value)
42{
43 return au1xxx_gpio_direction_output(gpio, value);
44}
45
46static inline int gpio_get_value(unsigned gpio)
47{
48 return au1xxx_gpio_get_value(gpio);
49}
50
51static inline void gpio_set_value(unsigned gpio, int value)
52{
53 au1xxx_gpio_set_value(gpio, value);
54}
55
56static inline int gpio_to_irq(unsigned gpio)
57{
58 return gpio;
59}
60
61static inline int irq_to_gpio(unsigned irq)
62{
63 return irq;
64}
65
66/* For cansleep */
67#include <asm-generic/gpio.h>
68
69#endif /* _AU1XXX_GPIO_H_ */
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
index 098fca4289bb..364cea2dc71f 100644
--- a/include/asm-mips/mach-au1x00/ioremap.h
+++ b/include/asm-mips/mach-au1x00/ioremap.h
@@ -28,4 +28,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
28 return __fixup_bigphys_addr(phys_addr, size); 28 return __fixup_bigphys_addr(phys_addr, size);
29} 29}
30 30
31static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
32 unsigned long flags)
33{
34 return NULL;
35}
36
37static inline int plat_iounmap(const volatile void __iomem *addr)
38{
39 return 0;
40}
41
31#endif /* __ASM_MACH_AU1X00_IOREMAP_H */ 42#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index 684a501c04cf..9c9d2b998ca4 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -30,7 +30,6 @@
30#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE 30#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
31 31
32#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) 32#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
33#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
34#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) 33#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
35#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) 34#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
36#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) 35#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
@@ -71,10 +70,6 @@
71 70
72extern int cobalt_board_id; 71extern int cobalt_board_id;
73 72
74#define PCI_CFG_SET(devfn,where) \
75 GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) | \
76 (PCI_FUNC (devfn) << 8) | (where)))
77
78#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) 73#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
79# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ 74# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
80# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ 75# define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */
diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h
deleted file mode 100644
index 7e272ce57ea3..000000000000
--- a/include/asm-mips/mach-ev64120/mach-gt64120.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H
9#define __ASM_GALILEO_BOARDS_MIPS_EV64120_H
10
11/*
12 * GT64120 config space base address
13 */
14extern unsigned long gt64120_base;
15
16#define GT64120_BASE (gt64120_base)
17
18/*
19 * PCI Bus allocation
20 */
21#define GT_PCI_MEM_BASE 0x12000000UL
22#define GT_PCI_MEM_SIZE 0x02000000UL
23#define GT_PCI_IO_BASE 0x10000000UL
24#define GT_PCI_IO_SIZE 0x02000000UL
25#define GT_ISA_IO_BASE PCI_IO_BASE
26
27/*
28 * Duart I/O ports.
29 */
30#define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20)
31#define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00)
32
33
34/*
35 * EV64120 interrupt controller register base.
36 */
37#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
38
39/*
40 * EV64120 UART register base.
41 */
42#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
43#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
44#define EV64120_BASE_BAUD ( 3686400 / 16 )
45#define EV64120_UART_IRQ 6
46
47/*
48 * PCI interrupts will come in on either the INTA or INTD interrups lines,
49 * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
50 * boards, they all either come in on IntD or they all come in on IntA, they
51 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
52 * "requested" interrupt numbers and go through the list whenever we get an
53 * IntA/D.
54 *
55 * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
56 * INTD is 11.
57 */
58#define GT_TIMER 4
59#define GT_INTA 2
60#define GT_INTD 5
61
62#endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */
diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h
new file mode 100644
index 000000000000..6eaf5efedf3a
--- /dev/null
+++ b/include/asm-mips/mach-generic/gpio.h
@@ -0,0 +1,15 @@
1#ifndef __ASM_MACH_GENERIC_GPIO_H
2#define __ASM_MACH_GENERIC_GPIO_H
3
4int gpio_request(unsigned gpio, const char *label);
5void gpio_free(unsigned gpio);
6int gpio_direction_input(unsigned gpio);
7int gpio_direction_output(unsigned gpio, int value);
8int gpio_get_value(unsigned gpio);
9void gpio_set_value(unsigned gpio, int value);
10int gpio_to_irq(unsigned gpio);
11int irq_to_gpio(unsigned irq);
12
13#include <asm-generic/gpio.h> /* cansleep wrappers */
14
15#endif /* __ASM_MACH_GENERIC_GPIO_H */
diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h
index 9b64ff6e485d..b379938d47f0 100644
--- a/include/asm-mips/mach-generic/ioremap.h
+++ b/include/asm-mips/mach-generic/ioremap.h
@@ -20,4 +20,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
20 return phys_addr; 20 return phys_addr;
21} 21}
22 22
23static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
24 unsigned long flags)
25{
26 return NULL;
27}
28
29static inline int plat_iounmap(const volatile void __iomem *addr)
30{
31 return 0;
32}
33
23#endif /* __ASM_MACH_GENERIC_IOREMAP_H */ 34#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 0ae9997bc9a8..c9fa4b14968d 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -10,38 +10,54 @@
10#ifndef _ASM_MACH_GENERIC_SPACES_H 10#ifndef _ASM_MACH_GENERIC_SPACES_H
11#define _ASM_MACH_GENERIC_SPACES_H 11#define _ASM_MACH_GENERIC_SPACES_H
12 12
13#include <linux/const.h>
14
15/*
16 * This gives the physical RAM offset.
17 */
18#ifndef PHYS_OFFSET
19#define PHYS_OFFSET _AC(0, UL)
20#endif
13 21
14#ifdef CONFIG_32BIT 22#ifdef CONFIG_32BIT
15 23
16#define CAC_BASE 0x80000000 24#define CAC_BASE _AC(0x80000000, UL)
17#define IO_BASE 0xa0000000 25#define IO_BASE _AC(0xa0000000, UL)
18#define UNCAC_BASE 0xa0000000 26#define UNCAC_BASE _AC(0xa0000000, UL)
19#define MAP_BASE 0xc0000000
20 27
21/* 28#ifndef MAP_BASE
22 * This handles the memory map. 29#define MAP_BASE _AC(0xc0000000, UL)
23 * We handle pages at KSEG0 for kernels with 32 bit address space. 30#endif
24 */
25#define PAGE_OFFSET 0x80000000UL
26 31
27/* 32/*
28 * Memory above this physical address will be considered highmem. 33 * Memory above this physical address will be considered highmem.
29 */ 34 */
30#ifndef HIGHMEM_START 35#ifndef HIGHMEM_START
31#define HIGHMEM_START 0x20000000UL 36#define HIGHMEM_START _AC(0x20000000, UL)
32#endif 37#endif
33 38
34#endif /* CONFIG_32BIT */ 39#endif /* CONFIG_32BIT */
35 40
36#ifdef CONFIG_64BIT 41#ifdef CONFIG_64BIT
37 42
38/* 43#ifndef CAC_BASE
39 * This handles the memory map.
40 */
41#ifdef CONFIG_DMA_NONCOHERENT 44#ifdef CONFIG_DMA_NONCOHERENT
42#define PAGE_OFFSET 0x9800000000000000UL 45#define CAC_BASE _AC(0x9800000000000000, UL)
43#else 46#else
44#define PAGE_OFFSET 0xa800000000000000UL 47#define CAC_BASE _AC(0xa800000000000000, UL)
48#endif
49#endif
50
51#ifndef IO_BASE
52#define IO_BASE _AC(0x9000000000000000, UL)
53#endif
54
55#ifndef UNCAC_BASE
56#define UNCAC_BASE _AC(0x9000000000000000, UL)
57#endif
58
59#ifndef MAP_BASE
60#define MAP_BASE _AC(0xc000000000000000, UL)
45#endif 61#endif
46 62
47/* 63/*
@@ -50,22 +66,20 @@
50 * in the distant future. Nobody will care for a few years :-) 66 * in the distant future. Nobody will care for a few years :-)
51 */ 67 */
52#ifndef HIGHMEM_START 68#ifndef HIGHMEM_START
53#define HIGHMEM_START (1UL << 59UL) 69#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL))
54#endif 70#endif
55 71
56#ifdef CONFIG_DMA_NONCOHERENT
57#define CAC_BASE 0x9800000000000000UL
58#else
59#define CAC_BASE 0xa800000000000000UL
60#endif
61#define IO_BASE 0x9000000000000000UL
62#define UNCAC_BASE 0x9000000000000000UL
63#define MAP_BASE 0xc000000000000000UL
64
65#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) 72#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
66#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) 73#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
67#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) 74#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
68 75
69#endif /* CONFIG_64BIT */ 76#endif /* CONFIG_64BIT */
70 77
78/*
79 * This handles the memory map.
80 */
81#ifndef PAGE_OFFSET
82#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET)
83#endif
84
71#endif /* __ASM_MACH_GENERIC_SPACES_H */ 85#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
index ab20c026fd19..7f9fa6f66059 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -11,44 +11,17 @@
11#define _ASM_MACH_IP22_SPACES_H 11#define _ASM_MACH_IP22_SPACES_H
12 12
13 13
14#ifdef CONFIG_32BIT
15
16#define CAC_BASE 0x80000000
17#define IO_BASE 0xa0000000
18#define UNCAC_BASE 0xa0000000
19#define MAP_BASE 0xc0000000
20
21/*
22 * This handles the memory map.
23 * We handle pages at KSEG0 for kernels with 32 bit address space.
24 */
25#define PAGE_OFFSET 0x80000000UL
26
27/*
28 * Memory above this physical address will be considered highmem.
29 */
30#ifndef HIGHMEM_START
31#define HIGHMEM_START 0x20000000UL
32#endif
33
34#endif /* CONFIG_32BIT */
35
36#ifdef CONFIG_64BIT 14#ifdef CONFIG_64BIT
37#define PAGE_OFFSET 0xffffffff80000000UL
38 15
39#ifndef HIGHMEM_START 16#define PAGE_OFFSET 0xffffffff80000000UL
40#define HIGHMEM_START (1UL << 59UL)
41#endif
42 17
43#define CAC_BASE 0xffffffff80000000 18#define CAC_BASE 0xffffffff80000000
44#define IO_BASE 0xffffffffa0000000 19#define IO_BASE 0xffffffffa0000000
45#define UNCAC_BASE 0xffffffffa0000000 20#define UNCAC_BASE 0xffffffffa0000000
46#define MAP_BASE 0xc000000000000000 21#define MAP_BASE 0xc000000000000000
47 22
48#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
49#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
50#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
51
52#endif /* CONFIG_64BIT */ 23#endif /* CONFIG_64BIT */
53 24
25#include <asm/mach-generic/spaces.h>
26
54#endif /* __ASM_MACH_IP22_SPACES_H */ 27#endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
index 45e61785ef42..b18802a0b17e 100644
--- a/include/asm-mips/mach-ip27/spaces.h
+++ b/include/asm-mips/mach-ip27/spaces.h
@@ -14,22 +14,17 @@
14 * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects 14 * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects
15 * uncached memory addressing. 15 * uncached memory addressing.
16 */ 16 */
17#define CAC_BASE 0xa800000000000000
18 17
19#define HSPEC_BASE 0x9000000000000000 18#define HSPEC_BASE 0x9000000000000000
20#define IO_BASE 0x9200000000000000 19#define IO_BASE 0x9200000000000000
21#define MSPEC_BASE 0x9400000000000000 20#define MSPEC_BASE 0x9400000000000000
22#define UNCAC_BASE 0x9600000000000000 21#define UNCAC_BASE 0x9600000000000000
23#define MAP_BASE 0xc000000000000000
24 22
25#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
26#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
27#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
28#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) 23#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK))
29#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) 24#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK))
30 25
31#define PAGE_OFFSET CAC_BASE
32
33#define HIGHMEM_START (~0UL) 26#define HIGHMEM_START (~0UL)
34 27
28#include <asm/mach-generic/spaces.h>
29
35#endif /* _ASM_MACH_IP27_SPACES_H */ 30#endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h
deleted file mode 100644
index 44abe5c02389..000000000000
--- a/include/asm-mips/mach-ip32/spaces.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 03, 04, 05 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2000, 2002 Maciej W. Rozycki
8 * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
9 */
10#ifndef _ASM_MACH_IP32_SPACES_H
11#define _ASM_MACH_IP32_SPACES_H
12
13/*
14 * Memory above this physical address will be considered highmem.
15 * Fixme: 59 bits is a fictive number and makes assumptions about processors
16 * in the distant future. Nobody will care for a few years :-)
17 */
18#ifndef HIGHMEM_START
19#define HIGHMEM_START (1UL << 59UL)
20#endif
21
22#define CAC_BASE 0x9800000000000000UL
23#define IO_BASE 0x9000000000000000UL
24#define UNCAC_BASE 0x9000000000000000UL
25#define MAP_BASE 0xc000000000000000UL
26
27#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
28#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
29#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
30
31/*
32 * This handles the memory map.
33 */
34#define PAGE_OFFSET CAC_BASE
35
36#endif /* __ASM_MACH_IP32_SPACES_H */
diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-jmr3927/ioremap.h
new file mode 100644
index 000000000000..aa131ad7f717
--- /dev/null
+++ b/include/asm-mips/mach-jmr3927/ioremap.h
@@ -0,0 +1,38 @@
1/*
2 * include/asm-mips/mach-jmr3927/ioremap.h
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef __ASM_MACH_JMR3927_IOREMAP_H
10#define __ASM_MACH_JMR3927_IOREMAP_H
11
12#include <linux/types.h>
13
14/*
15 * Allow physical addresses to be fixed up to help peripherals located
16 * outside the low 32-bit range -- generic pass-through version.
17 */
18static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
19{
20 return phys_addr;
21}
22
23static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
24 unsigned long flags)
25{
26#define TXX9_DIRECTMAP_BASE 0xff000000ul
27 if (offset >= TXX9_DIRECTMAP_BASE &&
28 offset < TXX9_DIRECTMAP_BASE + 0xf0000)
29 return (void __iomem *)offset;
30 return NULL;
31}
32
33static inline int plat_iounmap(const volatile void __iomem *addr)
34{
35 return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
36}
37
38#endif /* __ASM_MACH_JMR3927_IOREMAP_H */
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h
deleted file mode 100644
index 1a9ad45cc135..000000000000
--- a/include/asm-mips/mach-lasat/mach-gt64120.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
9#define _ASM_GT64120_LASAT_GT64120_DEP_H
10
11/*
12 * GT64120 config space base address on Lasat 100
13 */
14#define GT64120_BASE (KSEG1ADDR(0x14000000))
15
16/*
17 * PCI Bus allocation
18 *
19 * (Guessing ...)
20 */
21#define GT_PCI_MEM_BASE 0x12000000UL
22#define GT_PCI_MEM_SIZE 0x02000000UL
23#define GT_PCI_IO_BASE 0x10000000UL
24#define GT_PCI_IO_SIZE 0x02000000UL
25#define GT_ISA_IO_BASE PCI_IO_BASE
26
27#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h
new file mode 100644
index 000000000000..7e914777ebc4
--- /dev/null
+++ b/include/asm-mips/mach-lemote/dma-coherence.h
@@ -0,0 +1,42 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006, 07 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
8 * Author: Fuxin Zhang, zhangfx@lemote.com
9 *
10 */
11#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H
12#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H
13
14struct device;
15
16static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
17 size_t size)
18{
19 return virt_to_phys(addr) | 0x80000000;
20}
21
22static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
23 struct page *page)
24{
25 return page_to_phys(page) | 0x80000000;
26}
27
28static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
29{
30 return dma_addr & 0x7fffffff;
31}
32
33static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
34{
35}
36
37static inline int plat_device_is_coherent(struct device *dev)
38{
39 return 0;
40}
41
42#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h
new file mode 100644
index 000000000000..ed5147e11085
--- /dev/null
+++ b/include/asm-mips/mach-lemote/mc146818rtc.h
@@ -0,0 +1,36 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org)
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H
11#define __ASM_MACH_LEMOTE_MC146818RTC_H
12
13#include <linux/io.h>
14
15#define RTC_PORT(x) (0x70 + (x))
16#define RTC_IRQ 8
17
18static inline unsigned char CMOS_READ(unsigned long addr)
19{
20 outb_p(addr, RTC_PORT(0));
21 return inb_p(RTC_PORT(1));
22}
23
24static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
25{
26 outb_p(addr, RTC_PORT(0));
27 outb_p(data, RTC_PORT(1));
28}
29
30#define RTC_ALWAYS_BCD 0
31
32#ifndef mc146818_decode_year
33#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
34#endif
35
36#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */
diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-mips/kernel-entry-init.h
new file mode 100644
index 000000000000..0b793e7bf67e
--- /dev/null
+++ b/include/asm-mips/mach-mips/kernel-entry-init.h
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Chris Dearman (chris@mips.com)
7 * Copyright (C) 2007 Mips Technologies, Inc.
8 */
9#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
10#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
11
12 .macro kernel_entry_setup
13#ifdef CONFIG_MIPS_MT_SMTC
14 mfc0 t0, CP0_CONFIG
15 bgez t0, 9f
16 mfc0 t0, CP0_CONFIG, 1
17 bgez t0, 9f
18 mfc0 t0, CP0_CONFIG, 2
19 bgez t0, 9f
20 mfc0 t0, CP0_CONFIG, 3
21 and t0, 1<<2
22 bnez t0, 0f
239:
24 /* Assume we came from YAMON... */
25 PTR_LA v0, 0x9fc00534 /* YAMON print */
26 lw v0, (v0)
27 move a0, zero
28 PTR_LA a1, nonmt_processor
29 jal v0
30
31 PTR_LA v0, 0x9fc00520 /* YAMON exit */
32 lw v0, (v0)
33 li a0, 1
34 jal v0
35
361: b 1b
37
38 __INITDATA
39nonmt_processor:
40 .asciz "SMTC kernel requires the MT ASE to run\n"
41 __FINIT
420:
43#endif
44 .endm
45
46/*
47 * Do SMP slave processor setup necessary before we can safely execute C code.
48 */
49 .macro smp_slave_setup
50 .endm
51
52#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
index 779b02205737..779b02205737 100644
--- a/include/asm-mips/mach-sim/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
deleted file mode 100644
index 57a12ded0613..000000000000
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 MontaVista Software Inc.
7 * Author: Manish Lachwani, mlachwani@mvista.com
8 * Copyright (C) 2004 Ralf Baechle
9 */
10#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
11#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
12
13/*
14 * Momentum Ocelot-3 is based on Rm7900 processor which
15 * is based on the E9000 core.
16 */
17#define cpu_has_watch 1
18#define cpu_has_mips16 0
19#define cpu_has_divec 0
20#define cpu_has_vce 0
21#define cpu_has_cache_cdex_p 0
22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
24#define cpu_has_mcheck 0
25#define cpu_has_ejtag 0
26
27#define cpu_has_llsc 1
28#define cpu_has_vtag_icache 0
29#define cpu_has_dc_aliases 0
30#define cpu_has_ic_fills_f_dc 0
31#define cpu_has_dsp 0
32#define cpu_icache_snoops_remote_store 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_inclusive_pcaches 0
38
39#define cpu_dcache_line_size() 32
40#define cpu_icache_line_size() 32
41#define cpu_scache_line_size() 32
42
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47
48#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/include/asm-mips/mach-tx49xx/ioremap.h
new file mode 100644
index 000000000000..88cf546719b8
--- /dev/null
+++ b/include/asm-mips/mach-tx49xx/ioremap.h
@@ -0,0 +1,42 @@
1/*
2 * include/asm-mips/mach-tx49xx/ioremap.h
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef __ASM_MACH_TX49XX_IOREMAP_H
10#define __ASM_MACH_TX49XX_IOREMAP_H
11
12#include <linux/types.h>
13
14/*
15 * Allow physical addresses to be fixed up to help peripherals located
16 * outside the low 32-bit range -- generic pass-through version.
17 */
18static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
19{
20 return phys_addr;
21}
22
23static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
24 unsigned long flags)
25{
26#ifdef CONFIG_64BIT
27#define TXX9_DIRECTMAP_BASE 0xfff000000ul
28#else
29#define TXX9_DIRECTMAP_BASE 0xff000000ul
30#endif
31 if (offset >= TXX9_DIRECTMAP_BASE &&
32 offset < TXX9_DIRECTMAP_BASE + 0x400000)
33 return (void __iomem *)(unsigned long)(int)offset;
34 return NULL;
35}
36
37static inline int plat_iounmap(const volatile void __iomem *addr)
38{
39 return (unsigned long)addr >= (unsigned long)(int)TXX9_DIRECTMAP_BASE;
40}
41
42#endif /* __ASM_MACH_TX49XX_IOREMAP_H */
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
index cd7125610100..dc3fc32eedd8 100644
--- a/include/asm-mips/mips-boards/bonito64.h
+++ b/include/asm-mips/mips-boards/bonito64.h
@@ -26,7 +26,12 @@
26/* offsets from base register */ 26/* offsets from base register */
27#define BONITO(x) (x) 27#define BONITO(x) (x)
28 28
29#else /* !__ASSEMBLY__ */ 29#elif defined(CONFIG_LEMOTE_FULONG)
30
31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32#define BONITO_IRQ_BASE 32
33
34#else
30 35
31/* 36/*
32 * Algorithmics Bonito64 system controller register base. 37 * Algorithmics Bonito64 system controller register base.
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 89c81922d47c..706b3691f57e 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -7,7 +7,7 @@
7 * Copyright (C) 2000 Silicon Graphics, Inc. 7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */ 12 */
13#ifndef _ASM_MIPSREGS_H 13#ifndef _ASM_MIPSREGS_H
@@ -15,6 +15,7 @@
15 15
16#include <linux/linkage.h> 16#include <linux/linkage.h>
17#include <asm/hazards.h> 17#include <asm/hazards.h>
18#include <asm/war.h>
18 19
19/* 20/*
20 * The following macros are especially useful for __asm__ 21 * The following macros are especially useful for __asm__
@@ -533,9 +534,13 @@
533#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 534#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
534#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 535#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
535#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 536#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
537#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
536 538
537#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 539#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
538 540
541#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
542
543
539/* 544/*
540 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 545 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
541 */ 546 */
@@ -772,6 +777,9 @@ do { \
772#define read_c0_context() __read_ulong_c0_register($4, 0) 777#define read_c0_context() __read_ulong_c0_register($4, 0)
773#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 778#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
774 779
780#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
781#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
782
775#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 783#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
776#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 784#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
777 785
@@ -1294,10 +1302,39 @@ static inline void tlb_probe(void)
1294 1302
1295static inline void tlb_read(void) 1303static inline void tlb_read(void)
1296{ 1304{
1305#if MIPS34K_MISSED_ITLB_WAR
1306 int res = 0;
1307
1308 __asm__ __volatile__(
1309 " .set push \n"
1310 " .set noreorder \n"
1311 " .set noat \n"
1312 " .set mips32r2 \n"
1313 " .word 0x41610001 # dvpe $1 \n"
1314 " move %0, $1 \n"
1315 " ehb \n"
1316 " .set pop \n"
1317 : "=r" (res));
1318
1319 instruction_hazard();
1320#endif
1321
1297 __asm__ __volatile__( 1322 __asm__ __volatile__(
1298 ".set noreorder\n\t" 1323 ".set noreorder\n\t"
1299 "tlbr\n\t" 1324 "tlbr\n\t"
1300 ".set reorder"); 1325 ".set reorder");
1326
1327#if MIPS34K_MISSED_ITLB_WAR
1328 if ((res & _ULCAST_(1)))
1329 __asm__ __volatile__(
1330 " .set push \n"
1331 " .set noreorder \n"
1332 " .set noat \n"
1333 " .set mips32r2 \n"
1334 " .word 0x41600021 # evpe \n"
1335 " ehb \n"
1336 " .set pop \n");
1337#endif
1301} 1338}
1302 1339
1303static inline void tlb_write_indexed(void) 1340static inline void tlb_write_indexed(void)
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index c5ef324fd69f..de6d09ebbd80 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr)
112#define MODULE_PROC_FAMILY "RM9000 " 112#define MODULE_PROC_FAMILY "RM9000 "
113#elif defined CONFIG_CPU_SB1 113#elif defined CONFIG_CPU_SB1
114#define MODULE_PROC_FAMILY "SB1 " 114#define MODULE_PROC_FAMILY "SB1 "
115#elif defined CONFIG_CPU_LOONGSON2
116#define MODULE_PROC_FAMILY "LOONGSON2 "
115#else 117#else
116#error MODULE_PROC_FAMILY undefined for your processor configuration 118#error MODULE_PROC_FAMILY undefined for your processor configuration
117#endif 119#endif
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h
deleted file mode 100644
index c3ca959aa4d9..000000000000
--- a/include/asm-mips/nile4.h
+++ /dev/null
@@ -1,310 +0,0 @@
1/*
2 * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 *
7 * This file is based on the following documentation:
8 *
9 * NEC Vrc 5074 System Controller Data Sheet, June 1998
10 */
11
12#ifndef _ASM_NILE4_H
13#define _ASM_NILE4_H
14
15#define NILE4_BASE 0xbfa00000
16#define NILE4_SIZE 0x00200000 /* 2 MB */
17
18
19 /*
20 * Physical Device Address Registers (PDARs)
21 */
22
23#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
24#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
25#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
26#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
27#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
28#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
29#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
30#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
31#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
32#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
33#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
34#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */
35 /* [R/W] */
36#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
37
38
39 /*
40 * CPU Interface Registers
41 */
42
43#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */
44#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */
45#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
46#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
47 /* Enable [R/W] */
48#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
49#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
50
51
52 /*
53 * Memory-Interface Registers
54 */
55
56#define NILE4_MEMCTRL 0x00C0 /* Memory Control */
57#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
58#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */
59
60
61 /*
62 * PCI-Bus Registers
63 */
64
65#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */
66#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
67#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
68#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
69#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */
70
71
72 /*
73 * Local-Bus Registers
74 */
75
76#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
77#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
78#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
79#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
80#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
81#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
82#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
83#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
84#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
85 /* Enables [R/W] */
86#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
87#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
88
89
90 /*
91 * DMA Registers
92 */
93
94#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
95#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
96#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
97#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
98#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
99#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
100
101
102 /*
103 * Timer Registers
104 */
105
106#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
107#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
108#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
109#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
110#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
111#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
112#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
113#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
114
115
116 /*
117 * PCI Configuration Space Registers
118 */
119
120#define NILE4_PCI_BASE 0x0200
121
122#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */
123#define NILE4_DID 0x0202 /* PCI Device ID [R] */
124#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */
125#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */
126#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */
127#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */
128#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
129#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */
130#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */
131#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */
132#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
133#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
134#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
135#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
136 /* (unimplemented) */
137#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
138#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */
139#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */
140 /* (unimplemented) */
141#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
142#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */
143#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
144#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
145#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
146#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
147#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
148#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
149#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
150#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
151#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
152#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
153
154
155 /*
156 * Serial-Port Registers
157 */
158
159#define NILE4_UART_BASE 0x0300
160
161#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */
162#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */
163#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */
164#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */
165#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */
166#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */
167#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */
168#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */
169#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */
170#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */
171#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */
172#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */
173
174#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */
175
176
177 /*
178 * Interrupt Lines
179 */
180
181#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */
182#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */
183#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */
184#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */
185#define NILE4_INT_UART 4 /* UART Interrupt */
186#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */
187#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */
188#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */
189#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */
190#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */
191#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */
192#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */
193#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */
194#define NILE4_INT_RESV 13 /* Reserved */
195#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */
196#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */
197
198
199 /*
200 * Nile 4 Register Access
201 */
202
203static inline void nile4_sync(void)
204{
205 volatile u32 *p = (volatile u32 *)0xbfc00000;
206 (void)(*p);
207}
208
209static inline void nile4_out32(u32 offset, u32 val)
210{
211 *(volatile u32 *)(NILE4_BASE+offset) = val;
212 nile4_sync();
213}
214
215static inline u32 nile4_in32(u32 offset)
216{
217 u32 val = *(volatile u32 *)(NILE4_BASE+offset);
218 nile4_sync();
219 return val;
220}
221
222static inline void nile4_out16(u32 offset, u16 val)
223{
224 *(volatile u16 *)(NILE4_BASE+offset) = val;
225 nile4_sync();
226}
227
228static inline u16 nile4_in16(u32 offset)
229{
230 u16 val = *(volatile u16 *)(NILE4_BASE+offset);
231 nile4_sync();
232 return val;
233}
234
235static inline void nile4_out8(u32 offset, u8 val)
236{
237 *(volatile u8 *)(NILE4_BASE+offset) = val;
238 nile4_sync();
239}
240
241static inline u8 nile4_in8(u32 offset)
242{
243 u8 val = *(volatile u8 *)(NILE4_BASE+offset);
244 nile4_sync();
245 return val;
246}
247
248
249 /*
250 * Physical Device Address Registers
251 */
252
253extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
254 int on_memory_bus, int visible);
255
256
257 /*
258 * PCI Master Registers
259 */
260
261#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
262#define NILE4_PCICMD_IO 1 /* PCI I/O Space */
263#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */
264#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */
265
266
267 /*
268 * PCI Address Spaces
269 *
270 * Note that these are multiplexed using PCIINIT[01]!
271 */
272
273#define NILE4_PCI_IO_BASE 0xa6000000
274#define NILE4_PCI_MEM_BASE 0xa8000000
275#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
276#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE
277
278
279extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
280
281
282 /*
283 * Interrupt Programming
284 */
285
286#define NUM_I8259_INTERRUPTS 16
287#define NUM_NILE4_INTERRUPTS 16
288
289#define IRQ_I8259_CASCADE NILE4_INT_INTE
290#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS)
291#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS)
292#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS)
293
294extern void nile4_map_irq(int nile4_irq, int cpu_irq);
295extern void nile4_map_irq_all(int cpu_irq);
296extern void nile4_enable_irq(unsigned int nile4_irq);
297extern void nile4_disable_irq(unsigned int nile4_irq);
298extern void nile4_disable_irq_all(void);
299extern u16 nile4_get_irq_stat(int cpu_irq);
300extern void nile4_enable_irq_output(int cpu_irq);
301extern void nile4_disable_irq_output(int cpu_irq);
302extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
303extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
304extern void nile4_clear_irq(int nile4_irq);
305extern void nile4_clear_irq_mask(u32 mask);
306extern u8 nile4_i8259_iack(void);
307extern void nile4_dump_irq_status(void); /* Debug */
308
309#endif
310
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 5c3239dad0f2..b92dd8c760da 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,12 +34,8 @@
34 34
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36 36
37/* 37#include <linux/pfn.h>
38 * This gives the physical RAM offset. 38#include <asm/io.h>
39 */
40#ifndef PHYS_OFFSET
41#define PHYS_OFFSET 0UL
42#endif
43 39
44/* 40/*
45 * It's normally defined only for FLATMEM config but it's 41 * It's normally defined only for FLATMEM config but it's
@@ -48,9 +44,6 @@
48 */ 44 */
49#define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) 45#define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET)
50 46
51#include <linux/pfn.h>
52#include <asm/io.h>
53
54extern void clear_page(void * page); 47extern void clear_page(void * page);
55extern void copy_page(void * to, void * from); 48extern void copy_page(void * to, void * from);
56 49
@@ -150,11 +143,15 @@ typedef struct { unsigned long pgprot; } pgprot_t;
150 * __pa()/__va() should be used only during mem init. 143 * __pa()/__va() should be used only during mem init.
151 */ 144 */
152#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) 145#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
153#define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0) 146#define __pa(x) \
147({ \
148 unsigned long __x = (unsigned long)(x); \
149 __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x); \
150})
154#else 151#else
155#define __pa_page_offset(x) PAGE_OFFSET 152#define __pa(x) \
153 ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
156#endif 154#endif
157#define __pa(x) ((unsigned long)(x) - __pa_page_offset(x) + PHYS_OFFSET)
158#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) 155#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
159#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) 156#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0))
160 157
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 3eea3ba0fca5..a59d54749eef 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -56,7 +56,7 @@ extern void register_pci_controller(struct pci_controller *hose);
56/* 56/*
57 * board supplied pci irq fixup routine 57 * board supplied pci irq fixup routine
58 */ 58 */
59extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin); 59extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
60 60
61 61
62/* Can be used to override the logic in pci_scan_bus for skipping 62/* Can be used to override the logic in pci_scan_bus for skipping
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
new file mode 100644
index 000000000000..c84bcf9570b1
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
@@ -0,0 +1,151 @@
1/*
2 * Defines for the MSP interrupt controller.
3 *
4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_CIC_INT_H
26#define _MSP_CIC_INT_H
27
28/*
29 * The PMC-Sierra CIC interrupts are all centrally managed by the
30 * CIC sub-system.
31 * We attempt to keep the interrupt numbers as consistent as possible
32 * across all of the MSP devices, but some differences will creep in ...
33 * The interrupts which are directly forwarded to the MIPS core interrupts
34 * are assigned interrupts in the range 0-7, interrupts cascaded through
35 * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
36 * (MSP_INT_CIC). Currently we don't really distinguish between VPE1
37 * and VPE0 (or thread contexts for that matter). Will have to fix.
38 * The PER interrupts are assigned interrupts in the range 40-71.
39*/
40
41
42/*
43 * IRQs directly forwarded to the CPU
44 */
45#define MSP_MIPS_INTBASE 0
46#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
47#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
48#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
49#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
50#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */
51#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */
52#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */
53#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
54
55/*
56 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
57 * These defines should be tied to the register definitions for the CIC
58 * interrupt routine. For now, just use hard-coded values.
59 */
60#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8)
61#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0)
62 /* External interrupt 0 */
63#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1)
64 /* External interrupt 1 */
65#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2)
66 /* External interrupt 2 */
67#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3)
68 /* External interrupt 3 */
69#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4)
70 /* CPU interface interrupt */
71#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5)
72 /* External interrupt 4 */
73#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6)
74 /* Cascaded IRQ for USB */
75#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7)
76 /* Sec engine mailbox IRQ */
77#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8)
78 /* External interrupt 5 */
79#define MSP_INT_TDM (MSP_CIC_INTBASE + 9)
80 /* TDM interrupt */
81#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10)
82 /* Cascaded IRQ for MAC 0 */
83#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11)
84 /* Cascaded IRQ for MAC 1 */
85#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12)
86 /* Cascaded IRQ for sec engine */
87#define MSP_INT_PER (MSP_CIC_INTBASE + 13)
88 /* Peripheral interrupt */
89#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14)
90 /* SLP timer 0 */
91#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15)
92 /* SLP timer 1 */
93#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16)
94 /* SLP timer 2 */
95#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17)
96 /* VPE0 MIPS timer */
97#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18)
98 /* Block Copy */
99#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19)
100 /* UART 0 */
101#define MSP_INT_PCI (MSP_CIC_INTBASE + 20)
102 /* PCI subsystem */
103#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21)
104 /* External interrupt 5 */
105#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22)
106 /* PCI Message Signal */
107#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23)
108 /* Cascaded ADSL2+ SAR IRQ */
109#define MSP_INT_DSL (MSP_CIC_INTBASE + 24)
110 /* ADSL2+ IRQ */
111#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25)
112 /* SLP error condition */
113#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26)
114 /* VPE1 MIPS timer */
115#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27)
116 /* VPE0 Performance counter */
117#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28)
118 /* VPE1 Performance counter */
119#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29)
120 /* External interrupt 5 */
121#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30)
122 /* VPE0 Software interrupt */
123#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31)
124 /* VPE0 Software interrupt */
125
126/*
127 * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
128 */
129#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32)
130/* Reserved 0-1 */
131#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
132 /* UART 1 */
133/* Reserved 3-5 */
134#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
135 /* 2-wire */
136#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
137 /* Peripheral timer block out 0 */
138#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
139 /* Peripheral timer block out 1 */
140/* Reserved 9 */
141#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
142 /* SPI RX complete */
143#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
144 /* SPI TX complete */
145#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
146 /* GPIO */
147#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
148 /* Peripheral error */
149/* Reserved 14-31 */
150
151#endif /* !_MSP_CIC_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
new file mode 100644
index 000000000000..1d9f05474820
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
@@ -0,0 +1,43 @@
1/*
2 * Defines for the MSP interrupt handlers.
3 *
4 * Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved.
5 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_INT_H
26#define _MSP_INT_H
27
28/*
29 * The PMC-Sierra MSP product line has at least two different interrupt
30 * controllers, the SLP register based scheme and the CIC interrupt
31 * controller block mechanism. This file distinguishes between them
32 * so that devices see a uniform interface.
33 */
34
35#if defined(CONFIG_IRQ_MSP_SLP)
36 #include "msp_slp_int.h"
37#elif defined(CONFIG_IRQ_MSP_CIC)
38 #include "msp_cic_int.h"
39#else
40 #error "What sort of interrupt controller does *your* MSP have?"
41#endif
42
43#endif /* !_MSP_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
new file mode 100644
index 000000000000..415606903617
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
@@ -0,0 +1,205 @@
1/*
2 * Copyright (c) 2000-2006 PMC-Sierra INC.
3 *
4 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General
6 * Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be
11 * useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public
17 * License along with this program; if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
19 * 02139, USA.
20 *
21 * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
22 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
23 * SOFTWARE.
24 */
25
26#ifndef _MSP_PCI_H_
27#define _MSP_PCI_H_
28
29#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
30
31/*
32 * It is convenient to program the OATRAN register so that
33 * Athena virtual address space and PCI address space are
34 * the same. This is not a requirement, just a convenience.
35 *
36 * The only hard restrictions on the value of OATRAN is that
37 * OATRAN must not be programmed to allow translated memory
38 * addresses to fall within the lowest 512MB of
39 * PCI address space. This region is hardcoded
40 * for use as Athena PCI Host Controller target
41 * access memory space to the Athena's SDRAM.
42 *
43 * Note that OATRAN applies only to memory accesses, not
44 * to I/O accesses.
45 *
46 * To program OATRAN to make Athena virtual address space
47 * and PCI address space have the same values, OATRAN
48 * is to be programmed to 0xB8000000. The top seven
49 * bits of the value mimic the seven bits clipped off
50 * by the PCI Host controller.
51 *
52 * With OATRAN at the said value, when the CPU does
53 * an access to its virtual address at, say 0xB900_5000,
54 * the address appearing on the PCI bus will be
55 * 0xB900_5000.
56 * - Michael Penner
57 */
58#define MSP_PCI_OATRAN 0xB8000000UL
59
60#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL)
61#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000)
62#define MSP_PCI_SPACE_END \
63 (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
64#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL)
65#define MSP_PCI_IOSPACE_SIZE 0x1000
66#define MSP_PCI_IOSPACE_END \
67 (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
68
69/* IRQ for PCI status interrupts */
70#define PCI_STAT_IRQ 20
71
72#define QFLUSH_REG_1 0xB7F40000
73
74typedef volatile unsigned int pcireg;
75typedef void * volatile ppcireg;
76
77struct pci_block_copy
78{
79 pcireg unused1; /* +0x00 */
80 pcireg unused2; /* +0x04 */
81 ppcireg unused3; /* +0x08 */
82 ppcireg unused4; /* +0x0C */
83 pcireg unused5; /* +0x10 */
84 pcireg unused6; /* +0x14 */
85 pcireg unused7; /* +0x18 */
86 ppcireg unused8; /* +0x1C */
87 ppcireg unused9; /* +0x20 */
88 pcireg unusedA; /* +0x24 */
89 ppcireg unusedB; /* +0x28 */
90 ppcireg unusedC; /* +0x2C */
91};
92
93enum
94{
95 config_device_vendor, /* 0 */
96 config_status_command, /* 1 */
97 config_class_revision, /* 2 */
98 config_BIST_header_latency_cache, /* 3 */
99 config_BAR0, /* 4 */
100 config_BAR1, /* 5 */
101 config_BAR2, /* 6 */
102 config_not_used7, /* 7 */
103 config_not_used8, /* 8 */
104 config_not_used9, /* 9 */
105 config_CIS, /* 10 */
106 config_subsystem, /* 11 */
107 config_not_used12, /* 12 */
108 config_capabilities, /* 13 */
109 config_not_used14, /* 14 */
110 config_lat_grant_irq, /* 15 */
111 config_message_control,/* 16 */
112 config_message_addr, /* 17 */
113 config_message_data, /* 18 */
114 config_VPD_addr, /* 19 */
115 config_VPD_data, /* 20 */
116 config_maxregs /* 21 - number of registers */
117};
118
119struct msp_pci_regs
120{
121 pcireg hop_unused_00; /* +0x00 */
122 pcireg hop_unused_04; /* +0x04 */
123 pcireg hop_unused_08; /* +0x08 */
124 pcireg hop_unused_0C; /* +0x0C */
125 pcireg hop_unused_10; /* +0x10 */
126 pcireg hop_unused_14; /* +0x14 */
127 pcireg hop_unused_18; /* +0x18 */
128 pcireg hop_unused_1C; /* +0x1C */
129 pcireg hop_unused_20; /* +0x20 */
130 pcireg hop_unused_24; /* +0x24 */
131 pcireg hop_unused_28; /* +0x28 */
132 pcireg hop_unused_2C; /* +0x2C */
133 pcireg hop_unused_30; /* +0x30 */
134 pcireg hop_unused_34; /* +0x34 */
135 pcireg if_control; /* +0x38 */
136 pcireg oatran; /* +0x3C */
137 pcireg reset_ctl; /* +0x40 */
138 pcireg config_addr; /* +0x44 */
139 pcireg hop_unused_48; /* +0x48 */
140 pcireg msg_signaled_int_status; /* +0x4C */
141 pcireg msg_signaled_int_mask; /* +0x50 */
142 pcireg if_status; /* +0x54 */
143 pcireg if_mask; /* +0x58 */
144 pcireg hop_unused_5C; /* +0x5C */
145 pcireg hop_unused_60; /* +0x60 */
146 pcireg hop_unused_64; /* +0x64 */
147 pcireg hop_unused_68; /* +0x68 */
148 pcireg hop_unused_6C; /* +0x6C */
149 pcireg hop_unused_70; /* +0x70 */
150
151 struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
152
153 pcireg error_hdr1; /* +0xE0 */
154 pcireg error_hdr2; /* +0xE4 */
155
156 pcireg config[config_maxregs] __attribute__((aligned(256)));
157
158};
159
160#define BPCI_CFGADDR_BUSNUM_SHF 16
161#define BPCI_CFGADDR_FUNCTNUM_SHF 8
162#define BPCI_CFGADDR_REGNUM_SHF 2
163#define BPCI_CFGADDR_ENABLE (1<<31)
164
165#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
166#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
167#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */
168#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */
169#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
170#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */
171#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */
172
173#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */
174#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */
175#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */
176#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
177#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
178#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
179#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
180#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
181#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */
182#define BPCI_IFSTATUS_SER (1<<19) /* System error */
183#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */
184#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */
185#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */
186#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */
187#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */
188#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */
189#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */
190#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */
191#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */
192
193#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */
194#define BPCI_RESETCTL_RT (1<<4) /* Release time */
195#define BPCI_RESETCTL_CT (1<<8) /* Config time */
196#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */
197#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */
198#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */
199
200extern struct msp_pci_regs msp_pci_regs
201 __attribute__((section(".register")));
202extern unsigned long msp_pci_config_space
203 __attribute__((section(".register")));
204
205#endif /* !_MSP_PCI_H_ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
new file mode 100644
index 000000000000..14ca7dc382a8
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
@@ -0,0 +1,176 @@
1/*
2 * MIPS boards bootprom interface for the Linux kernel.
3 *
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _ASM_MSP_PROM_H
26#define _ASM_MSP_PROM_H
27
28#include <linux/types.h>
29
30#define DEVICEID "deviceid"
31#define FEATURES "features"
32#define PROM_ENV "prom_env"
33#define PROM_ENV_FILE "/proc/"PROM_ENV
34#define PROM_ENV_SIZE 256
35
36#define CPU_DEVID_FAMILY 0x0000ff00
37#define CPU_DEVID_REVISION 0x000000ff
38
39#define FPGA_IS_POLO(revision) \
40 (((revision >= 0xb0) && (revision < 0xd0)))
41#define FPGA_IS_5000(revision) \
42 ((revision >= 0x80) && (revision <= 0x90))
43#define FPGA_IS_ZEUS(revision) ((revision < 0x7f))
44#define FPGA_IS_DUET(revision) \
45 (((revision >= 0xa0) && (revision < 0xb0)))
46#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0))
47#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0))
48
49#define MACHINE_TYPE_POLO "POLO"
50#define MACHINE_TYPE_DUET "DUET"
51#define MACHINE_TYPE_ZEUS "ZEUS"
52#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB"
53#define MACHINE_TYPE_MSP5000 "MSP5000"
54#define MACHINE_TYPE_MSP4200 "MSP4200"
55#define MACHINE_TYPE_MSP7120 "MSP7120"
56#define MACHINE_TYPE_MSP7130 "MSP7130"
57#define MACHINE_TYPE_OTHER "OTHER"
58
59#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA"
60#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA"
61#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA"
62#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA"
63#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA"
64#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA"
65#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA"
66#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA"
67
68/* Device Family definitions */
69#define FAMILY_FPGA 0x0000
70#define FAMILY_ZEUS 0x1000
71#define FAMILY_POLO 0x2000
72#define FAMILY_DUET 0x4000
73#define FAMILY_TRIAD 0x5000
74#define FAMILY_MSP4200 0x4200
75#define FAMILY_MSP4200_FPGA 0x4f00
76#define FAMILY_MSP7100 0x7100
77#define FAMILY_MSP7100_FPGA 0x7f00
78
79/* Device Type definitions */
80#define TYPE_MSP7120 0x7120
81#define TYPE_MSP7130 0x7130
82
83#define ENET_KEY 'E'
84#define ENETTXD_KEY 'e'
85#define PCI_KEY 'P'
86#define PCIMUX_KEY 'p'
87#define SEC_KEY 'S'
88#define SPAD_KEY 'D'
89#define TDM_KEY 'T'
90#define ZSP_KEY 'Z'
91
92#define FEATURE_NOEXIST '-'
93#define FEATURE_EXIST '+'
94
95#define ENET_MII 'M'
96#define ENET_RMII 'R'
97
98#define ENETTXD_FALLING 'F'
99#define ENETTXD_RISING 'R'
100
101#define PCI_HOST 'H'
102#define PCI_PERIPHERAL 'P'
103
104#define PCIMUX_FULL 'F'
105#define PCIMUX_SINGLE 'S'
106
107#define SEC_DUET 'D'
108#define SEC_POLO 'P'
109#define SEC_SLOW 'S'
110#define SEC_TRIAD 'T'
111
112#define SPAD_POLO 'P'
113
114#define TDM_DUET 'D' /* DUET TDMs might exist */
115#define TDM_POLO 'P' /* POLO TDMs might exist */
116#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */
117
118#define ZSP_DUET 'D' /* one DUET zsp engine */
119#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
120
121extern char *prom_getcmdline(void);
122extern char *prom_getenv(char *name);
123extern void prom_init_cmdline(void);
124extern void prom_meminit(void);
125extern void prom_fixup_mem_map(unsigned long start_mem,
126 unsigned long end_mem);
127
128#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
129extern bool get_ramroot(void **start, unsigned long *size);
130#endif
131
132extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
133extern unsigned long get_deviceid(void);
134extern char identify_enet(unsigned long interface_num);
135extern char identify_enetTxD(unsigned long interface_num);
136extern char identify_pci(void);
137extern char identify_sec(void);
138extern char identify_spad(void);
139extern char identify_sec(void);
140extern char identify_tdm(void);
141extern char identify_zsp(void);
142extern unsigned long identify_family(void);
143extern unsigned long identify_revision(void);
144
145/*
146 * The following macro calls prom_printf and puts the format string
147 * into an init section so it can be reclaimed.
148 */
149#define ppfinit(f, x...) \
150 do { \
151 static char _f[] __initdata = KERN_INFO f; \
152 printk(_f, ## x); \
153 } while (0)
154
155/* Memory descriptor management. */
156#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */
157
158enum yamon_memtypes {
159 yamon_dontuse,
160 yamon_prom,
161 yamon_free,
162};
163
164struct prom_pmemblock {
165 unsigned long base; /* Within KSEG0. */
166 unsigned int size; /* In bytes. */
167 unsigned int type; /* free or prom memory */
168};
169
170extern int prom_argc;
171extern char **prom_argv;
172extern char **prom_envp;
173extern int *prom_vec;
174extern struct prom_pmemblock *prom_getmdesc(void);
175
176#endif /* !_ASM_MSP_PROM_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
new file mode 100644
index 000000000000..60a5a38dd5b2
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
@@ -0,0 +1,236 @@
1/*
2 * SMP/VPE-safe functions to access "registers" (see note).
3 *
4 * NOTES:
5* - These macros use ll/sc instructions, so it is your responsibility to
6 * ensure these are available on your platform before including this file.
7 * - The MIPS32 spec states that ll/sc results are undefined for uncached
8 * accesses. This means they can't be used on HW registers accessed
9 * through kseg1. Code which requires these macros for this purpose must
10 * front-end the registers with cached memory "registers" and have a single
11 * thread update the actual HW registers.
12 * - A maximum of 2k of code can be inserted between ll and sc. Every
13 * memory accesses between the instructions will increase the chance of
14 * sc failing and having to loop.
15 * - When using custom_read_reg32/custom_write_reg32 only perform the
16 * necessary logical operations on the register value in between these
17 * two calls. All other logic should be performed before the first call.
18 * - There is a bug on the R10000 chips which has a workaround. If you
19 * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
20 * to be non-zero. If you are using this header from within linux, you may
21 * include <asm/war.h> before including this file to have this defined
22 * appropriately for you.
23 *
24 * Copyright 2005-2007 PMC-Sierra, Inc.
25 *
26 * This program is free software; you can redistribute it and/or modify it
27 * under the terms of the GNU General Public License as published by the
28 * Free Software Foundation; either version 2 of the License, or (at your
29 * option) any later version.
30 *
31 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
32 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
33 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
34 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * You should have received a copy of the GNU General Public License along
43 * with this program; if not, write to the Free Software Foundation, Inc., 675
44 * Mass Ave, Cambridge, MA 02139, USA.
45 */
46
47#ifndef __ASM_REGOPS_H__
48#define __ASM_REGOPS_H__
49
50#include <linux/types.h>
51
52#include <asm/war.h>
53
54#ifndef R10000_LLSC_WAR
55#define R10000_LLSC_WAR 0
56#endif
57
58#if R10000_LLSC_WAR == 1
59#define __beqz "beqzl "
60#else
61#define __beqz "beqz "
62#endif
63
64#ifndef _LINUX_TYPES_H
65typedef unsigned int u32;
66#endif
67
68/*
69 * Sets all the masked bits to the corresponding value bits
70 */
71static inline void set_value_reg32(volatile u32 *const addr,
72 u32 const mask,
73 u32 const value)
74{
75 u32 temp;
76
77 __asm__ __volatile__(
78 " .set push \n"
79 " .set mips3 \n"
80 "1: ll %0, %1 # set_value_reg32 \n"
81 " and %0, %2 \n"
82 " or %0, %3 \n"
83 " sc %0, %1 \n"
84 " "__beqz"%0, 1b \n"
85 " nop \n"
86 " .set pop \n"
87 : "=&r" (temp), "=m" (*addr)
88 : "ir" (~mask), "ir" (value), "m" (*addr));
89}
90
91/*
92 * Sets all the masked bits to '1'
93 */
94static inline void set_reg32(volatile u32 *const addr,
95 u32 const mask)
96{
97 u32 temp;
98
99 __asm__ __volatile__(
100 " .set push \n"
101 " .set mips3 \n"
102 "1: ll %0, %1 # set_reg32 \n"
103 " or %0, %2 \n"
104 " sc %0, %1 \n"
105 " "__beqz"%0, 1b \n"
106 " nop \n"
107 " .set pop \n"
108 : "=&r" (temp), "=m" (*addr)
109 : "ir" (mask), "m" (*addr));
110}
111
112/*
113 * Sets all the masked bits to '0'
114 */
115static inline void clear_reg32(volatile u32 *const addr,
116 u32 const mask)
117{
118 u32 temp;
119
120 __asm__ __volatile__(
121 " .set push \n"
122 " .set mips3 \n"
123 "1: ll %0, %1 # clear_reg32 \n"
124 " and %0, %2 \n"
125 " sc %0, %1 \n"
126 " "__beqz"%0, 1b \n"
127 " nop \n"
128 " .set pop \n"
129 : "=&r" (temp), "=m" (*addr)
130 : "ir" (~mask), "m" (*addr));
131}
132
133/*
134 * Toggles all masked bits from '0' to '1' and '1' to '0'
135 */
136static inline void toggle_reg32(volatile u32 *const addr,
137 u32 const mask)
138{
139 u32 temp;
140
141 __asm__ __volatile__(
142 " .set push \n"
143 " .set mips3 \n"
144 "1: ll %0, %1 # toggle_reg32 \n"
145 " xor %0, %2 \n"
146 " sc %0, %1 \n"
147 " "__beqz"%0, 1b \n"
148 " nop \n"
149 " .set pop \n"
150 : "=&r" (temp), "=m" (*addr)
151 : "ir" (mask), "m" (*addr));
152}
153
154/*
155 * Read all masked bits others are returned as '0'
156 */
157static inline u32 read_reg32(volatile u32 *const addr,
158 u32 const mask)
159{
160 u32 temp;
161
162 __asm__ __volatile__(
163 " .set push \n"
164 " .set noreorder \n"
165 " lw %0, %1 # read \n"
166 " and %0, %2 # mask \n"
167 " .set pop \n"
168 : "=&r" (temp)
169 : "m" (*addr), "ir" (mask));
170
171 return temp;
172}
173
174/*
175 * blocking_read_reg32 - Read address with blocking load
176 *
177 * Uncached writes need to be read back to ensure they reach RAM.
178 * The returned value must be 'used' to prevent from becoming a
179 * non-blocking load.
180 */
181static inline u32 blocking_read_reg32(volatile u32 *const addr)
182{
183 u32 temp;
184
185 __asm__ __volatile__(
186 " .set push \n"
187 " .set noreorder \n"
188 " lw %0, %1 # read \n"
189 " move %0, %0 # block \n"
190 " .set pop \n"
191 : "=&r" (temp)
192 : "m" (*addr));
193
194 return temp;
195}
196
197/*
198 * For special strange cases only:
199 *
200 * If you need custom processing within a ll/sc loop, use the following macros
201 * VERY CAREFULLY:
202 *
203 * u32 tmp; <-- Define a variable to hold the data
204 *
205 * custom_read_reg32(address, tmp); <-- Reads the address and put the value
206 * in the 'tmp' variable given
207 *
208 * From here on out, you are (basicly) atomic, so don't do anything too
209 * fancy!
210 * Also, this code may loop if the end of this block fails to write
211 * everything back safely due do the other CPU, so do NOT do anything
212 * with side-effects!
213 *
214 * custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely.
215 */
216#define custom_read_reg32(address, tmp) \
217 __asm__ __volatile__( \
218 " .set push \n" \
219 " .set mips3 \n" \
220 "1: ll %0, %1 #custom_read_reg32 \n" \
221 " .set pop \n" \
222 : "=r" (tmp), "=m" (*address) \
223 : "m" (*address))
224
225#define custom_write_reg32(address, tmp) \
226 __asm__ __volatile__( \
227 " .set push \n" \
228 " .set mips3 \n" \
229 " sc %0, %1 #custom_write_reg32 \n" \
230 " "__beqz"%0, 1b \n" \
231 " nop \n" \
232 " .set pop \n" \
233 : "=&r" (tmp), "=m" (*address) \
234 : "0" (tmp), "m" (*address))
235
236#endif /* __ASM_REGOPS_H__ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
new file mode 100644
index 000000000000..0b56f55206c6
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
@@ -0,0 +1,667 @@
1/*
2 * Defines for the address space, registers and register configuration
3 * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
4 * This file contains addess maps for all the devices in the line of
5 * products but only has register definitions and configuration masks for
6 * registers which aren't definitely associated with any device. Things
7 * like clock settings, reset access, the ELB etc. Individual device
8 * drivers will reference the appropriate XXX_BASE value defined here
9 * and have individual registers offset from that.
10 *
11 * Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved.
12 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
13 *
14 * ########################################################################
15 *
16 * This program is free software; you can distribute it and/or modify it
17 * under the terms of the GNU General Public License (Version 2) as
18 * published by the Free Software Foundation.
19 *
20 * This program is distributed in the hope it will be useful, but WITHOUT
21 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 * for more details.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
28 *
29 * ########################################################################
30 */
31
32#include <asm/addrspace.h>
33#include <linux/types.h>
34
35#ifndef _ASM_MSP_REGS_H
36#define _ASM_MSP_REGS_H
37
38/*
39 ########################################################################
40 # Address space and device base definitions #
41 ########################################################################
42 */
43
44/*
45 ***************************************************************************
46 * System Logic and Peripherals (ELB, UART0, etc) device address space *
47 ***************************************************************************
48 */
49#define MSP_SLP_BASE 0x1c000000
50 /* System Logic and Peripherals */
51#define MSP_RST_BASE (MSP_SLP_BASE + 0x10)
52 /* System reset register base */
53#define MSP_RST_SIZE 0x0C /* System reset register space */
54
55#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)
56 /* watchdog timer base */
57#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)
58 /* internal timer base */
59#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
60 /* UART0 controller base */
61#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
62 /* Block Copy controller base */
63#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)
64 /* Block Copy descriptor base */
65
66/*
67 ***************************************************************************
68 * PCI address space *
69 ***************************************************************************
70 */
71#define MSP_PCI_BASE 0x19000000
72
73/*
74 ***************************************************************************
75 * MSbus device address space *
76 ***************************************************************************
77 */
78#define MSP_MSB_BASE 0x18000000
79 /* MSbus address start */
80#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000)
81 /* Peripheral device registers */
82#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)
83 /* MAC A device registers */
84#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)
85 /* MAC B device registers */
86#define MSP_MAC_SIZE 0xE0 /* MAC register space */
87
88#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)
89 /* Security Engine registers */
90#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)
91 /* MAC C device registers */
92#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
93 /* ADSL2 device registers */
94#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000)
95 /* USB device registers */
96#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100)
97 /* USB device registers */
98#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF)
99 /* USB device registers */
100#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
101 /* CPU interface registers */
102
103/* Devices within the MSbus peripheral block */
104#define MSP_UART1_BASE (MSP_PER_BASE + 0x030)
105 /* UART1 controller base */
106#define MSP_SPI_BASE (MSP_PER_BASE + 0x058)
107 /* SPI/MPI control registers */
108#define MSP_TWI_BASE (MSP_PER_BASE + 0x090)
109 /* Two-wire control registers */
110#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)
111 /* Programmable timer control */
112
113/*
114 ***************************************************************************
115 * Physical Memory configuration address space *
116 ***************************************************************************
117 */
118#define MSP_MEM_CFG_BASE 0x17f00000
119
120#define MSP_MEM_INDIRECT_CTL_10 0x10
121
122/*
123 * Notes:
124 * 1) The SPI registers are split into two blocks, one offset from the
125 * MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
126 * 0x68. The SPI driver definitions for the register must be aware
127 * of this.
128 * 2) The block copy engine register are divided into two regions, one
129 * for the control/configuration of the engine proper and one for the
130 * values of the descriptors used in the copy process. These have
131 * different base defines (CTRL_BASE vs DESC_BASE)
132 * 3) These constants are for physical addresses which means that they
133 * work correctly with "ioremap" and friends. This means that device
134 * drivers will need to remap these addresses using ioremap and perhaps
135 * the readw/writew macros. Or they could use the regptr() macro
136 * defined below, but the readw/writew calls are the correct thing.
137 * 4) The UARTs have an additional status register offset from the base
138 * address. This register isn't used in the standard 8250 driver but
139 * may be used in other software. Consult the hardware datasheet for
140 * offset details.
141 * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers
142 * start at an offset of 0x84 from the base address but the block of
143 * registers before this is reserved for the security engine. The
144 * driver will have to be aware of this but it makes the register
145 * definitions line up better with the documentation.
146 */
147
148/*
149 ########################################################################
150 # System register definitions. Not associated with a specific device #
151 ########################################################################
152 */
153
154/*
155 * This macro maps the physical register number into uncached space
156 * and (for C code) casts it into a u32 pointer so it can be dereferenced
157 * Normally these would be accessed with ioremap and readX/writeX, but
158 * these are convenient for a lot of internal kernel code.
159 */
160#ifdef __ASSEMBLER__
161 #define regptr(addr) (KSEG1ADDR(addr))
162#else
163 #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
164#endif
165
166/*
167 ***************************************************************************
168 * System Logic and Peripherals (RESET, ELB, etc) registers *
169 ***************************************************************************
170 */
171
172/* System Control register definitions */
173#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)
174 /* Device-ID RO */
175#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)
176 /* Firmware-ID Register RW */
177#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)
178 /* System-ID Register-0 RW */
179#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)
180 /* System-ID Register-1 RW */
181
182/* System Reset register definitions */
183#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)
184 /* System Reset Status RO */
185#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)
186 /* System Set Reset WO */
187#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)
188 /* System Clear Reset WO */
189
190/* System Clock Registers */
191#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)
192 /* PCI clock generator RW */
193#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)
194 /* UART clock generator RW */
195/* reserved (MSP_SLP_BASE + 0x24) */
196/* reserved (MSP_SLP_BASE + 0x28) */
197#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)
198 /* PLL1 clock generator RW */
199#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)
200 /* PLL0 clock generator RW */
201#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)
202 /* MIPS clock generator RW */
203#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)
204 /* Voice Eng clock generator RW */
205/* reserved (MSP_SLP_BASE + 0x3C) */
206#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)
207 /* MS-Bus clock generator RW */
208#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)
209 /* Sec & MAC clock generator RW */
210#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)
211 /* Per & TDM clock generator RW */
212
213/* Interrupt Controller Registers */
214#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
215 /* Interrupt status register RW */
216#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
217 /* Interrupt enable/mask RW */
218#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)
219 /* Security Engine mailbox RW */
220#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)
221 /* Voice Engine mailbox RW */
222
223/* ELB Controller Registers */
224#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)
225 /* ELB CS0 Configuration Reg */
226#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)
227 /* ELB CS0 Base Address Reg */
228#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)
229 /* ELB CS0 Mask Register */
230#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
231 /* ELB CS0 access register */
232
233#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)
234 /* ELB CS1 Configuration Reg */
235#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)
236 /* ELB CS1 Base Address Reg */
237#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)
238 /* ELB CS1 Mask Register */
239#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
240 /* ELB CS1 access register */
241
242#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)
243 /* ELB CS2 Configuration Reg */
244#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)
245 /* ELB CS2 Base Address Reg */
246#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)
247 /* ELB CS2 Mask Register */
248#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
249 /* ELB CS2 access register */
250
251#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)
252 /* ELB CS3 Configuration Reg */
253#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)
254 /* ELB CS3 Base Address Reg */
255#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)
256 /* ELB CS3 Mask Register */
257#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
258 /* ELB CS3 access register */
259
260#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)
261 /* ELB CS4 Configuration Reg */
262#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)
263 /* ELB CS4 Base Address Reg */
264#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)
265 /* ELB CS4 Mask Register */
266#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
267 /* ELB CS4 access register */
268
269#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)
270 /* ELB CS5 Configuration Reg */
271#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)
272 /* ELB CS5 Base Address Reg */
273#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)
274 /* ELB CS5 Mask Register */
275#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
276 /* ELB CS5 access register */
277
278/* reserved 0xE0 - 0xE8 */
279#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
280 /* ELB single PC card detect */
281
282/* reserved 0xF0 - 0xF8 */
283#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
284 /* SDRAM read/ELB timing Reg */
285
286/* Extended UART status registers */
287#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)
288 /* UART Status Register 0 */
289#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)
290 /* UART Status Register 1 */
291
292/* Performance monitoring registers */
293#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)
294 /* Performance monitor control */
295#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)
296 /* Performance monitor clear */
297#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)
298 /* Perf monitor counter high */
299#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)
300 /* Perf monitor counter low */
301
302/* System control registers */
303#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)
304 /* System control register */
305#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)
306 /* System Error status 1 */
307#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)
308 /* System Error status 2 */
309#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)
310 /* System Interrupt config */
311
312/* Voice Engine Memory configuration */
313#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)
314 /* Voice engine memory config */
315
316/* CPU/SLP Error Status registers */
317#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)
318 /* CPU/SLP Error status 1 */
319#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
320 /* CPU/SLP Error status 1 */
321
322#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188)
323 /* Extended GPIO register */
324
325/* System Error registers */
326#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
327 /* Int status for SLP errors */
328#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)
329 /* Int mask for SLP errors */
330#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)
331 /* External ELB reset */
332#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)
333 /* Boot Status */
334
335/* Extended ELB addressing */
336#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)
337 /* CS0 Extended address */
338#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)
339 /* CS1 Extended address */
340#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)
341 /* CS2 Extended address */
342#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)
343 /* CS3 Extended address */
344/* reserved 0x1B0 */
345#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)
346 /* CS5 Extended address */
347
348/* PLL Adjustment registers */
349#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)
350 /* PLL0 lock status */
351#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)
352 /* PLL Analog reset status */
353#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)
354 /* PLL0 Adjustment value */
355#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)
356 /* PLL1 Adjustment value */
357
358/*
359 ***************************************************************************
360 * Peripheral Register definitions *
361 ***************************************************************************
362 */
363
364/* Peripheral status */
365#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)
366 /* Peripheral control register */
367#define PER_STS_REG regptr(MSP_PER_BASE + 0x54)
368 /* Peripheral status register */
369
370/* SPI/MPI Registers */
371#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)
372 /* SPI/MPI Tx Size register */
373#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)
374 /* SPI/MPI Rx Size register */
375#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)
376 /* SPI/MPI Control register */
377#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)
378 /* SPI/MPI Chip Select reg */
379#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)
380 /* SPI/MPI Core Data reg */
381#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)
382 /* SPI/MPI Core Control reg */
383#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)
384 /* SPI/MPI Core Status reg */
385#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)
386 /* SPI/MPI Core Ssel reg */
387#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)
388 /* SPI/MPI Data FIFO reg */
389
390/* Peripheral Block Error Registers */
391#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)
392 /* Error Bit Status Register */
393#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)
394 /* Error Bit Mask Register */
395#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)
396 /* Error Header 1 Register */
397#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)
398 /* Error Header 2 Register */
399
400/* Peripheral Block Interrupt Registers */
401#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)
402 /* Interrupt status register */
403#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)
404 /* Interrupt Mask Register */
405#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)
406 /* GPIO interrupt status reg */
407#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)
408 /* GPIO interrupt MASK Reg */
409
410/* POLO GPIO registers */
411#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)
412 /* Polo GPIO[8:0] data reg */
413#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)
414 /* Polo GPIO[7:0] config reg */
415#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)
416 /* Polo GPIO[15:8] config reg */
417#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)
418 /* Polo GPIO[31:0] output drive */
419#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)
420 /* Polo GPIO[23:16] config reg */
421#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)
422 /* Polo GPIO[15:9] data reg */
423#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)
424 /* Polo GPIO[23:16] data reg */
425#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)
426 /* Polo GPIO[31:24] data reg */
427#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)
428 /* Polo GPIO[39:32] data reg */
429#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)
430 /* Polo GPIO[47:40] data reg */
431#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)
432 /* Polo GPIO[54:48] data reg */
433#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
434 /* Polo GPIO[31:24] config reg */
435#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)
436 /* Polo GPIO[39:32] config reg */
437#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)
438 /* Polo GPIO[47:40] config reg */
439#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)
440 /* Polo GPIO[54:48] config reg */
441#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)
442 /* Polo GPIO[54:32] output drive */
443
444/* Generic GPIO registers */
445#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)
446 /* GPIO[1:0] data register */
447#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)
448 /* GPIO[5:2] data register */
449#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)
450 /* GPIO[9:6] data register */
451#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)
452 /* GPIO[15:10] data register */
453#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)
454 /* GPIO[1:0] config register */
455#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)
456 /* GPIO[5:2] config register */
457#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)
458 /* GPIO[9:6] config register */
459#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
460 /* GPIO[15:10] config register */
461#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)
462 /* GPIO[15:0] output drive */
463
464/*
465 ***************************************************************************
466 * CPU Interface register definitions *
467 ***************************************************************************
468 */
469#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)
470 /* PCI-SDRAM queue flush trigger */
471#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)
472 /* OCP Error Attribute 1 */
473#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)
474 /* OCP Error Attribute 2 */
475#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)
476 /* OCP Error Status */
477#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)
478 /* CPU policy configuration */
479#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)
480 /* Misc configuration options */
481
482/* Central Interrupt Controller Registers */
483#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)
484 /* Central Interrupt registers */
485#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)
486 /* External interrupt config */
487#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)
488 /* CIC Interrupt Status */
489#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)
490 /* VPE0 Interrupt Mask */
491#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)
492 /* VPE1 Interrupt Mask */
493#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)
494 /* Thread Context 0 Int Mask */
495#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)
496 /* Thread Context 1 Int Mask */
497#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)
498 /* Thread Context 2 Int Mask */
499#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)
500 /* Thread Context 3 Int Mask */
501#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)
502 /* Thread Context 4 Int Mask */
503#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)
504#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)
505#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)
506#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)
507
508
509/*
510 ***************************************************************************
511 * Memory controller registers *
512 ***************************************************************************
513 */
514#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)
515#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)
516#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)
517#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)
518
519/*
520 ***************************************************************************
521 * PCI controller registers *
522 ***************************************************************************
523 */
524#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)
525#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)
526#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)
527
528/*
529 ########################################################################
530 # Register content & macro definitions #
531 ########################################################################
532 */
533
534/*
535 ***************************************************************************
536 * DEV_ID defines *
537 ***************************************************************************
538 */
539#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */
540#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */
541#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */
542#define DEV_ID_FAMILY (0xff << 8) /* family ID code */
543#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */
544
545#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */
546#define MSP5000_ID (0x50 << 8)
547#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */
548#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */
549#define MSP4200_ID (0x42 << 8)
550#define MSP4000_ID (0x40 << 8)
551#define MSP2XXX_ID (0x20 << 8)
552#define MSPZEUS_ID (0x10 << 8)
553
554#define MSP2004_SUB_ID (0x0 << 16)
555#define MSP2005_SUB_ID (0x1 << 16)
556#define MSP2006_SUB_ID (0x1 << 16)
557#define MSP2007_SUB_ID (0x2 << 16)
558#define MSP2010_SUB_ID (0x3 << 16)
559#define MSP2015_SUB_ID (0x4 << 16)
560#define MSP2020_SUB_ID (0x5 << 16)
561#define MSP2100_SUB_ID (0x6 << 16)
562
563/*
564 ***************************************************************************
565 * RESET defines *
566 ***************************************************************************
567 */
568#define MSP_GR_RST (0x01 << 0) /* Global reset bit */
569#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */
570#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */
571#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */
572/* reserved */
573#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */
574#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */
575#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */
576#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */
577#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */
578#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */
579#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */
580#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */
581#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */
582
583/*
584 ***************************************************************************
585 * UART defines *
586 ***************************************************************************
587 */
588#ifndef CONFIG_MSP_FPGA
589#define MSP_BASE_BAUD 25000000
590#else
591#define MSP_BASE_BAUD 6000000
592#endif
593#define MSP_UART_REG_LEN 0x20
594
595/*
596 ***************************************************************************
597 * ELB defines *
598 ***************************************************************************
599 */
600#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */
601#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */
602
603/*
604 ***************************************************************************
605 * CIC defines *
606 ***************************************************************************
607 */
608
609/* CIC_EXT_CFG_REG */
610#define EXT_INT_POL(eirq) (1 << (eirq + 8))
611#define EXT_INT_EDGE(eirq) (1 << eirq)
612
613#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq))
614#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq))
615#define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq))
616#define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq))
617#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI
618#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO
619
620#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
621 ((reg & EXT_INT_EDGE(eirq)) == 0)
622#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq))
623#define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq))
624#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
625 ((reg & EXT_INT_POL(eirq)) == 0)
626#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI
627#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO
628
629/*
630 ***************************************************************************
631 * Memory Controller defines *
632 ***************************************************************************
633 */
634
635/* Indirect memory controller registers */
636#define DDRC_CFG(n) (n)
637#define DDRC_DEBUG(n) (0x04 + n)
638#define DDRC_CTL(n) (0x40 + n)
639
640/* Macro to perform DDRC indirect write */
641#define DDRC_INDIRECT_WRITE(reg, mask, value) \
642({ \
643 *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
644 *MEM_SS_DATA = (value); \
645 *MEM_SS_WRITE = 1; \
646})
647
648/*
649 ***************************************************************************
650 * SPI/MPI Mode *
651 ***************************************************************************
652 */
653#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */
654#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */
655#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */
656#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */
657
658/*
659 ***************************************************************************
660 * SPI/MPI Control Register *
661 ***************************************************************************
662 */
663#define SPI_MPI_RX_START 0x00000004 /* Start receive command */
664#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */
665#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */
666
667#endif /* !_ASM_MSP_REGS_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
new file mode 100644
index 000000000000..96d4c8ce8c83
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
@@ -0,0 +1,141 @@
1/*
2 * Defines for the MSP interrupt controller.
3 *
4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_SLP_INT_H
26#define _MSP_SLP_INT_H
27
28/*
29 * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
30 * hierarchical system. The first level are the direct MIPS interrupts
31 * and are assigned the interrupt range 0-7. The second level is the SLM
32 * interrupt controller and is assigned the range 8-39. The third level
33 * comprises the Peripherial block, the PCI block, the PCI MSI block and
34 * the SLP. The PCI interrupts and the SLP errors are handled by the
35 * relevant subsystems so the core interrupt code needs only concern
36 * itself with the Peripheral block. These are assigned interrupts in
37 * the range 40-71.
38 */
39
40/*
41 * IRQs directly connected to CPU
42 */
43#define MSP_MIPS_INTBASE 0
44#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
45#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
46#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
47#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
48#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
49#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
50#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
51#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
52
53/*
54 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
55 * These defines should be tied to the register definition for the SLM
56 * interrupt routine. For now, just use hard-coded values.
57 */
58#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
59#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
60 /* External interrupt 0 */
61#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
62 /* External interrupt 1 */
63#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
64 /* External interrupt 2 */
65#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
66 /* External interrupt 3 */
67/* Reserved 4-7 */
68
69/*
70 *************************************************************************
71 * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
72 * Some MSP produces have this interrupt labelled as Voice and some are *
73 * SEC mbox ... *
74 *************************************************************************
75 */
76#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
77 /* Cascaded IRQ for Voice Engine*/
78#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
79 /* TDM interrupt */
80#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
81 /* Cascaded IRQ for MAC 0 */
82#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
83 /* Cascaded IRQ for MAC 1 */
84#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
85 /* IRQ for security engine */
86#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
87 /* Peripheral interrupt */
88#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
89 /* SLP timer 0 */
90#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
91 /* SLP timer 1 */
92#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
93 /* SLP timer 2 */
94#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
95 /* Cascaded MIPS timer */
96#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
97 /* Block Copy */
98#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
99 /* UART 0 */
100#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
101 /* PCI subsystem */
102#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
103 /* PCI doorbell */
104#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
105 /* PCI Message Signal */
106#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
107 /* PCI Block Copy 0 */
108#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
109 /* PCI Block Copy 1 */
110#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
111 /* SLP error condition */
112#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
113 /* IRQ for MAC2 */
114/* Reserved 26-31 */
115
116/*
117 * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
118 */
119#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
120/* Reserved 0-1 */
121#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
122 /* UART 1 */
123/* Reserved 3-5 */
124#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
125 /* 2-wire */
126#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
127 /* Peripheral timer block out 0 */
128#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
129 /* Peripheral timer block out 1 */
130/* Reserved 9 */
131#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
132 /* SPI RX complete */
133#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
134 /* SPI TX complete */
135#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
136 /* GPIO */
137#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
138 /* Peripheral error */
139/* Reserved 14-31 */
140
141#endif /* !_MSP_SLP_INT_H */
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 5f80ba71ab92..1d8b9a8ae324 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -82,10 +82,6 @@ struct mips_fpu_struct {
82 unsigned int fcr31; 82 unsigned int fcr31;
83}; 83};
84 84
85#define INIT_FPU { \
86 {0,} \
87}
88
89#define NUM_DSP_REGS 6 85#define NUM_DSP_REGS 6
90 86
91typedef __u32 dspreg_t; 87typedef __u32 dspreg_t;
@@ -95,8 +91,6 @@ struct mips_dsp_state {
95 unsigned int dspcontrol; 91 unsigned int dspcontrol;
96}; 92};
97 93
98#define INIT_DSP {{0,},}
99
100#define INIT_CPUMASK { \ 94#define INIT_CPUMASK { \
101 {0,} \ 95 {0,} \
102} 96}
@@ -155,41 +149,63 @@ struct thread_struct {
155#define MF_N64 0 149#define MF_N64 0
156 150
157#ifdef CONFIG_MIPS_MT_FPAFF 151#ifdef CONFIG_MIPS_MT_FPAFF
158#define FPAFF_INIT 0, INIT_CPUMASK, 152#define FPAFF_INIT \
153 .emulated_fp = 0, \
154 .user_cpus_allowed = INIT_CPUMASK,
159#else 155#else
160#define FPAFF_INIT 156#define FPAFF_INIT
161#endif /* CONFIG_MIPS_MT_FPAFF */ 157#endif /* CONFIG_MIPS_MT_FPAFF */
162 158
163#define INIT_THREAD { \ 159#define INIT_THREAD { \
164 /* \ 160 /* \
165 * saved main processor registers \ 161 * Saved main processor registers \
166 */ \ 162 */ \
167 0, 0, 0, 0, 0, 0, 0, 0, \ 163 .reg16 = 0, \
168 0, 0, 0, \ 164 .reg17 = 0, \
169 /* \ 165 .reg18 = 0, \
170 * saved cp0 stuff \ 166 .reg19 = 0, \
171 */ \ 167 .reg20 = 0, \
172 0, \ 168 .reg21 = 0, \
173 /* \ 169 .reg22 = 0, \
174 * saved fpu/fpu emulator stuff \ 170 .reg23 = 0, \
175 */ \ 171 .reg29 = 0, \
176 INIT_FPU, \ 172 .reg30 = 0, \
177 /* \ 173 .reg31 = 0, \
178 * fpu affinity state (null if not FPAFF) \ 174 /* \
179 */ \ 175 * Saved cp0 stuff \
180 FPAFF_INIT \ 176 */ \
181 /* \ 177 .cp0_status = 0, \
182 * saved dsp/dsp emulator stuff \ 178 /* \
183 */ \ 179 * Saved FPU/FPU emulator stuff \
184 INIT_DSP, \ 180 */ \
185 /* \ 181 .fpu = { \
186 * Other stuff associated with the process \ 182 .fpr = {0,}, \
187 */ \ 183 .fcr31 = 0, \
188 0, 0, 0, 0, \ 184 }, \
189 /* \ 185 /* \
190 * For now the default is to fix address errors \ 186 * FPU affinity state (null if not FPAFF) \
191 */ \ 187 */ \
192 MF_FIXADE, 0, 0 \ 188 FPAFF_INIT \
189 /* \
190 * Saved DSP stuff \
191 */ \
192 .dsp = { \
193 .dspr = {0, }, \
194 .dspcontrol = 0, \
195 }, \
196 /* \
197 * Other stuff associated with the process \
198 */ \
199 .cp0_badvaddr = 0, \
200 .cp0_baduaddr = 0, \
201 .error_code = 0, \
202 .trap_no = 0, \
203 /* \
204 * For now the default is to fix address errors \
205 */ \
206 .mflags = MF_FIXADE, \
207 .irix_trampoline = 0, \
208 .irix_oldctx = 0, \
193} 209}
194 210
195struct task_struct; 211struct task_struct;
@@ -237,7 +253,7 @@ unsigned long get_wchan(struct task_struct *p);
237 253
238#define ARCH_HAS_PREFETCH 254#define ARCH_HAS_PREFETCH
239 255
240extern inline void prefetch(const void *addr) 256static inline void prefetch(const void *addr)
241{ 257{
242 __asm__ __volatile__( 258 __asm__ __volatile__(
243 " .set mips4 \n" 259 " .set mips4 \n"
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index ce51213d84f9..c07ebd8eb9e7 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -19,159 +19,4 @@
19 */ 19 */
20#define BASE_BAUD (1843200 / 16) 20#define BASE_BAUD (1843200 / 16)
21 21
22/* Standard COM flags (except for COM4, because of the 8514 problem) */
23#ifdef CONFIG_SERIAL_DETECT_IRQ
24#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
25#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
26#else
27#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
28#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
29#endif
30
31#ifdef CONFIG_MACH_JAZZ
32#include <asm/jazz.h>
33
34#ifndef CONFIG_OLIVETTI_M700
35 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
36 exactly which ones ... XXX */
37#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
38#else
39/* but the M700 isn't such a strange beast */
40#define JAZZ_BASE_BAUD BASE_BAUD
41#endif
42
43#define _JAZZ_SERIAL_INIT(int, base) \
44 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
45 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
46 .io_type = SERIAL_IO_MEM }
47#define JAZZ_SERIAL_PORT_DEFNS \
48 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
49 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
50#else
51#define JAZZ_SERIAL_PORT_DEFNS
52#endif
53
54/*
55 * Galileo EV64120 evaluation board
56 */
57#ifdef CONFIG_MIPS_EV64120
58#include <mach-gt64120.h>
59#define EV64120_SERIAL_PORT_DEFNS \
60 { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
61 .flags = STD_COM_FLAGS, \
62 .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \
63 .io_type = SERIAL_IO_MEM }, \
64 { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
65 .flags = STD_COM_FLAGS, \
66 .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \
67 .io_type = SERIAL_IO_MEM },
68#else
69#define EV64120_SERIAL_PORT_DEFNS
70#endif
71
72#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
73#define STD_SERIAL_PORT_DEFNS \
74 /* UART CLK PORT IRQ FLAGS */ \
75 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
76 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
77 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
78 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
79
80#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
81#define STD_SERIAL_PORT_DEFNS
82#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
83
84#ifdef CONFIG_MOMENCO_OCELOT_3
85#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
86#define OCELOT_3_SERIAL_IRQ 6
87#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
88
89#define _OCELOT_3_SERIAL_INIT(int, base) \
90 { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
91 .flags = STD_COM_FLAGS, \
92 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
93 io_type: SERIAL_IO_MEM }
94
95#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
96 _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
97#else
98#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
99#endif
100
101#ifdef CONFIG_MOMENCO_OCELOT
102/* Ordinary NS16552 duart with a 20MHz crystal. */
103#define OCELOT_BASE_BAUD ( 20000000 / 16 )
104
105#define OCELOT_SERIAL1_IRQ 4
106#define OCELOT_SERIAL1_BASE 0xe0001020
107
108#define _OCELOT_SERIAL_INIT(int, base) \
109 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
110 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
111 .io_type = SERIAL_IO_MEM }
112#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
113 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
114#else
115#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
116#endif
117
118#ifdef CONFIG_MOMENCO_OCELOT_C
119/* Ordinary NS16552 duart with a 20MHz crystal. */
120#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
121
122#define OCELOT_C_SERIAL1_IRQ 80
123#define OCELOT_C_SERIAL1_BASE 0xfd000020
124
125#define OCELOT_C_SERIAL2_IRQ 81
126#define OCELOT_C_SERIAL2_BASE 0xfd000000
127
128#define _OCELOT_C_SERIAL_INIT(int, base) \
129 { .baud_base = OCELOT_C_BASE_BAUD, \
130 .irq = (int), \
131 .flags = STD_COM_FLAGS, \
132 .iomem_base = (u8 *) base, \
133 .iomem_reg_shift = 2, \
134 .io_type = SERIAL_IO_MEM \
135 }
136#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
137 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
138 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
139#else
140#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
141#endif
142
143#ifdef CONFIG_DDB5477
144#include <asm/ddb5xxx/ddb5477.h>
145#define DDB5477_SERIAL_PORT_DEFNS \
146 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
147 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
148 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
149 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
150 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
151 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
152#else
153#define DDB5477_SERIAL_PORT_DEFNS
154#endif
155
156#ifdef CONFIG_SGI_IP32
157/*
158 * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
159 * They are initialized in ip32_setup
160 */
161#define IP32_SERIAL_PORT_DEFNS \
162 {},{},
163#else
164#define IP32_SERIAL_PORT_DEFNS
165#endif /* CONFIG_SGI_IP32 */
166
167#define SERIAL_PORT_DFNS \
168 DDB5477_SERIAL_PORT_DEFNS \
169 EV64120_SERIAL_PORT_DEFNS \
170 IP32_SERIAL_PORT_DEFNS \
171 JAZZ_SERIAL_PORT_DEFNS \
172 STD_SERIAL_PORT_DEFNS \
173 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
174 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
175 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
176
177#endif /* _ASM_SERIAL_H */ 22#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 1608fd71d6f7..13aef6af422c 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -49,13 +49,6 @@ extern struct call_data_struct *call_data;
49extern cpumask_t phys_cpu_present_map; 49extern cpumask_t phys_cpu_present_map;
50#define cpu_possible_map phys_cpu_present_map 50#define cpu_possible_map phys_cpu_present_map
51 51
52extern cpumask_t cpu_callout_map;
53/* We don't mark CPUs online until __cpu_up(), so we need another measure */
54static inline int num_booting_cpus(void)
55{
56 return cpus_weight(cpu_callout_map);
57}
58
59/* 52/*
60 * These are defined by the board-specific code. 53 * These are defined by the board-specific code.
61 */ 54 */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index f257509b914f..ddaf36a1e389 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -146,9 +146,6 @@ extern unsigned int sni_brd_type;
146#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE 146#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
147#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) 147#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
148 148
149#define SNI_DS1216_A20R_BASE 0xbc081ffc
150#define SNI_DS1216_RM200_BASE 0xbcd41ffc
151
152#define SNI_PCIT_INT_REG 0xbfff000c 149#define SNI_PCIT_INT_REG 0xbfff000c
153 150
154#define SNI_PCIT_INT_START 24 151#define SNI_PCIT_INT_START 24
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index bb0b289dbc9e..46bdb3f566f9 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -44,7 +44,7 @@ struct task_struct;
44 * different thread. 44 * different thread.
45 */ 45 */
46 46
47#define switch_to(prev,next,last) \ 47#define __mips_mt_fpaff_switch_to(prev) \
48do { \ 48do { \
49 if (cpu_has_fpu && \ 49 if (cpu_has_fpu && \
50 (prev->thread.mflags & MF_FPUBOUND) && \ 50 (prev->thread.mflags & MF_FPUBOUND) && \
@@ -52,24 +52,24 @@ do { \
52 prev->thread.mflags &= ~MF_FPUBOUND; \ 52 prev->thread.mflags &= ~MF_FPUBOUND; \
53 prev->cpus_allowed = prev->thread.user_cpus_allowed; \ 53 prev->cpus_allowed = prev->thread.user_cpus_allowed; \
54 } \ 54 } \
55 if (cpu_has_dsp) \
56 __save_dsp(prev); \
57 next->thread.emulated_fp = 0; \ 55 next->thread.emulated_fp = 0; \
58 (last) = resume(prev, next, task_thread_info(next)); \
59 if (cpu_has_dsp) \
60 __restore_dsp(current); \
61} while(0) 56} while(0)
62 57
63#else 58#else
59#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
60#endif
61
64#define switch_to(prev,next,last) \ 62#define switch_to(prev,next,last) \
65do { \ 63do { \
64 __mips_mt_fpaff_switch_to(prev); \
66 if (cpu_has_dsp) \ 65 if (cpu_has_dsp) \
67 __save_dsp(prev); \ 66 __save_dsp(prev); \
68 (last) = resume(prev, next, task_thread_info(next)); \ 67 (last) = resume(prev, next, task_thread_info(next)); \
69 if (cpu_has_dsp) \ 68 if (cpu_has_dsp) \
70 __restore_dsp(current); \ 69 __restore_dsp(current); \
70 if (cpu_has_userlocal) \
71 write_c0_userlocal(task_thread_info(current)->tp_value);\
71} while(0) 72} while(0)
72#endif
73 73
74/* 74/*
75 * On SMP systems, when the scheduler does migration-cost autodetection, 75 * On SMP systems, when the scheduler does migration-cost autodetection,
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 0fbedafdcea8..74e7d8061e58 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -105,12 +105,6 @@
105#define rbtx4938_pcireset_ptr \ 105#define rbtx4938_pcireset_ptr \
106 ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) 106 ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
107 107
108/* SPI */
109#define RBTX4938_SEEPROM1_CHIPID 0
110#define RBTX4938_SEEPROM2_CHIPID 1
111#define RBTX4938_SEEPROM3_CHIPID 2
112#define RBTX4938_SRTC_CHIPID 3
113
114/* 108/*
115 * IRQ mappings 109 * IRQ mappings
116 */ 110 */
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h
index 0dbbab820a5a..6a60c83e152b 100644
--- a/include/asm-mips/tx4938/spi.h
+++ b/include/asm-mips/tx4938/spi.h
@@ -14,61 +14,7 @@
14#ifndef __ASM_TX_BOARDS_TX4938_SPI_H 14#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
15#define __ASM_TX_BOARDS_TX4938_SPI_H 15#define __ASM_TX_BOARDS_TX4938_SPI_H
16 16
17/* SPI */ 17extern int spi_eeprom_register(int chipid);
18struct spi_dev_desc {
19 unsigned int baud;
20 unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
21 unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */
22 unsigned int polarity:1; /* 0:High-Active */
23 unsigned int phase:1; /* 0:Sample-Then-Shift */
24};
25
26extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
27extern void txx9_spi_irqinit(int irc_irq) __init;
28extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
29 unsigned char **inbufs, unsigned int *incounts,
30 unsigned char **outbufs, unsigned int *outcounts,
31 int cansleep);
32extern int spi_eeprom_write_enable(int chipid, int enable);
33extern int spi_eeprom_read_status(int chipid);
34extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); 18extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
35extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
36extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
37
38#define TXX9_IMCLK (txx9_gbus_clock / 2)
39
40/*
41* SPI
42*/
43
44/* SPMCR : SPI Master Control */
45#define TXx9_SPMCR_OPMODE 0xc0
46#define TXx9_SPMCR_CONFIG 0x40
47#define TXx9_SPMCR_ACTIVE 0x80
48#define TXx9_SPMCR_SPSTP 0x02
49#define TXx9_SPMCR_BCLR 0x01
50
51/* SPCR0 : SPI Status */
52#define TXx9_SPCR0_TXIFL_MASK 0xc000
53#define TXx9_SPCR0_RXIFL_MASK 0x3000
54#define TXx9_SPCR0_SIDIE 0x0800
55#define TXx9_SPCR0_SOEIE 0x0400
56#define TXx9_SPCR0_RBSIE 0x0200
57#define TXx9_SPCR0_TBSIE 0x0100
58#define TXx9_SPCR0_IFSPSE 0x0010
59#define TXx9_SPCR0_SBOS 0x0004
60#define TXx9_SPCR0_SPHA 0x0002
61#define TXx9_SPCR0_SPOL 0x0001
62
63/* SPSR : SPI Status */
64#define TXx9_SPSR_TBSI 0x8000
65#define TXx9_SPSR_RBSI 0x4000
66#define TXx9_SPSR_TBS_MASK 0x3800
67#define TXx9_SPSR_RBS_MASK 0x0700
68#define TXx9_SPSR_SPOE 0x0080
69#define TXx9_SPSR_IFSD 0x0008
70#define TXx9_SPSR_SIDLE 0x0004
71#define TXx9_SPSR_STRDY 0x0002
72#define TXx9_SPSR_SRRDY 0x0001
73 19
74#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ 20#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index ec0eeebd8802..9de52a5b0f3d 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -169,10 +169,9 @@
169 169
170/* 170/*
171 * On the RM9000 there is a problem which makes the CreateDirtyExclusive 171 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
172 * cache operation unusable on SMP systems. 172 * eache operation unusable on SMP systems.
173 */ 173 */
174#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ 174#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
175 defined(CONFIG_BASLER_EXCITE)
176#define RM9000_CDEX_SMP_WAR 1 175#define RM9000_CDEX_SMP_WAR 1
177#endif 176#endif
178 177
@@ -182,11 +181,10 @@
182 * I-cache line worth of instructions being fetched may case spurious 181 * I-cache line worth of instructions being fetched may case spurious
183 * exceptions. 182 * exceptions.
184 */ 183 */
185#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \ 184#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
186 defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \ 185 defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \
187 defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \ 186 defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \
188 defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \ 187 defined(CONFIG_WR_PPMC)
189 defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
190#define ICACHE_REFILLS_WORKAROUND_WAR 1 188#define ICACHE_REFILLS_WORKAROUND_WAR 1
191#endif 189#endif
192 190
@@ -200,6 +198,14 @@
200#endif 198#endif
201 199
202/* 200/*
201 * 34K core erratum: "Problems Executing the TLBR Instruction"
202 */
203#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
204 defined(CONFIG_PMC_MSP7120_FPGA)
205#define MIPS34K_MISSED_ITLB_WAR 1
206#endif
207
208/*
203 * Workarounds default to off 209 * Workarounds default to off
204 */ 210 */
205#ifndef ICACHE_REFILLS_WORKAROUND_WAR 211#ifndef ICACHE_REFILLS_WORKAROUND_WAR
@@ -238,5 +244,8 @@
238#ifndef R10000_LLSC_WAR 244#ifndef R10000_LLSC_WAR
239#define R10000_LLSC_WAR 0 245#define R10000_LLSC_WAR 0
240#endif 246#endif
247#ifndef MIPS34K_MISSED_ITLB_WAR
248#define MIPS34K_MISSED_ITLB_WAR 0
249#endif
241 250
242#endif /* _ASM_WAR_H */ 251#endif /* _ASM_WAR_H */
diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h
deleted file mode 100644
index 6aa90cae1114..000000000000
--- a/include/asm-mips/watch.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 1997, 1998, 2000, 2001 by Ralf Baechle
7 */
8#ifndef _ASM_WATCH_H
9#define _ASM_WATCH_H
10
11#include <linux/linkage.h>
12
13/*
14 * Types of reference for watch_set()
15 */
16enum wref_type {
17 wr_save = 1,
18 wr_load = 2
19};
20
21extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref);
22extern asmlinkage void __watch_clear(void);
23extern asmlinkage void __watch_reenable(void);
24
25#define watch_set(addr, ref) \
26 if (cpu_has_watch) \
27 __watch_set(addr, ref)
28#define watch_clear() \
29 if (cpu_has_watch) \
30 __watch_clear()
31#define watch_reenable() \
32 if (cpu_has_watch) \
33 __watch_reenable()
34
35#endif /* _ASM_WATCH_H */
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index c6d4ab86b83c..b021b3a2b65a 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -13,10 +13,6 @@
13#ifndef __ASM_MV643XX_H 13#ifndef __ASM_MV643XX_H
14#define __ASM_MV643XX_H 14#define __ASM_MV643XX_H
15 15
16#ifdef __mips__
17#include <asm/addrspace.h>
18#include <asm/marvell.h>
19#endif
20#include <asm/types.h> 16#include <asm/types.h>
21 17
22/****************************************/ 18/****************************************/
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 09:33:35 -0500