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authorMichael Ellerman <michael@ellerman.id.au>2009-06-17 14:13:53 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-07-07 23:50:23 -0400
commit33875f03307452650309a7d071678b2ca5f2fc26 (patch)
tree8e33ec3932388d1fcabb20bbde2f55d7e4916842
parent29e5fa59e5ebe06d6bd7e04e7752a47ead23f89e (diff)
powerpc/cell: Use pr_devel() in axon_msi.c
pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-rw-r--r--arch/powerpc/platforms/cell/axon_msi.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index c71498dbf211..aca5741ddc67 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -85,7 +85,7 @@ static inline void axon_msi_debug_setup(struct device_node *dn,
85 85
86static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) 86static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
87{ 87{
88 pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); 88 pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
89 89
90 dcr_write(msic->dcr_host, dcr_n, val); 90 dcr_write(msic->dcr_host, dcr_n, val);
91} 91}
@@ -98,7 +98,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
98 int retry = 0; 98 int retry = 0;
99 99
100 write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); 100 write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
101 pr_debug("axon_msi: original write_offset 0x%x\n", write_offset); 101 pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
102 102
103 /* write_offset doesn't wrap properly, so we have to mask it */ 103 /* write_offset doesn't wrap properly, so we have to mask it */
104 write_offset &= MSIC_FIFO_SIZE_MASK; 104 write_offset &= MSIC_FIFO_SIZE_MASK;
@@ -108,7 +108,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
108 msi = le32_to_cpu(msic->fifo_virt[idx]); 108 msi = le32_to_cpu(msic->fifo_virt[idx]);
109 msi &= 0xFFFF; 109 msi &= 0xFFFF;
110 110
111 pr_debug("axon_msi: woff %x roff %x msi %x\n", 111 pr_devel("axon_msi: woff %x roff %x msi %x\n",
112 write_offset, msic->read_offset, msi); 112 write_offset, msic->read_offset, msi);
113 113
114 if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) { 114 if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) {
@@ -123,12 +123,12 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
123 */ 123 */
124 udelay(1); 124 udelay(1);
125 retry++; 125 retry++;
126 pr_debug("axon_msi: invalid irq 0x%x!\n", msi); 126 pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
127 continue; 127 continue;
128 } 128 }
129 129
130 if (retry) { 130 if (retry) {
131 pr_debug("axon_msi: late irq 0x%x, retry %d\n", 131 pr_devel("axon_msi: late irq 0x%x, retry %d\n",
132 msi, retry); 132 msi, retry);
133 retry = 0; 133 retry = 0;
134 } 134 }
@@ -332,7 +332,7 @@ static int axon_msi_shutdown(struct of_device *device)
332 struct axon_msic *msic = dev_get_drvdata(&device->dev); 332 struct axon_msic *msic = dev_get_drvdata(&device->dev);
333 u32 tmp; 333 u32 tmp;
334 334
335 pr_debug("axon_msi: disabling %s\n", 335 pr_devel("axon_msi: disabling %s\n",
336 msic->irq_host->of_node->full_name); 336 msic->irq_host->of_node->full_name);
337 tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); 337 tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
338 tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; 338 tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
@@ -349,7 +349,7 @@ static int axon_msi_probe(struct of_device *device,
349 unsigned int virq; 349 unsigned int virq;
350 int dcr_base, dcr_len; 350 int dcr_base, dcr_len;
351 351
352 pr_debug("axon_msi: setting up dn %s\n", dn->full_name); 352 pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
353 353
354 msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL); 354 msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
355 if (!msic) { 355 if (!msic) {
@@ -403,7 +403,7 @@ static int axon_msi_probe(struct of_device *device,
403 403
404 set_irq_data(virq, msic); 404 set_irq_data(virq, msic);
405 set_irq_chained_handler(virq, axon_msi_cascade); 405 set_irq_chained_handler(virq, axon_msi_cascade);
406 pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq); 406 pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
407 407
408 /* Enable the MSIC hardware */ 408 /* Enable the MSIC hardware */
409 msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32); 409 msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
@@ -484,13 +484,13 @@ void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
484 484
485 addr = of_translate_address(dn, of_get_property(dn, "reg", NULL)); 485 addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
486 if (addr == OF_BAD_ADDR) { 486 if (addr == OF_BAD_ADDR) {
487 pr_debug("axon_msi: couldn't translate reg property\n"); 487 pr_devel("axon_msi: couldn't translate reg property\n");
488 return; 488 return;
489 } 489 }
490 490
491 msic->trigger = ioremap(addr, 0x4); 491 msic->trigger = ioremap(addr, 0x4);
492 if (!msic->trigger) { 492 if (!msic->trigger) {
493 pr_debug("axon_msi: ioremap failed\n"); 493 pr_devel("axon_msi: ioremap failed\n");
494 return; 494 return;
495 } 495 }
496 496
@@ -498,7 +498,7 @@ void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
498 498
499 if (!debugfs_create_file(name, 0600, powerpc_debugfs_root, 499 if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
500 msic, &fops_msic)) { 500 msic, &fops_msic)) {
501 pr_debug("axon_msi: debugfs_create_file failed!\n"); 501 pr_devel("axon_msi: debugfs_create_file failed!\n");
502 return; 502 return;
503 } 503 }
504} 504}