[ARM] S3C64XX: Add GPIO SPCONSLP and SLPEN register definitions

Add GPIO register definitions for SPCONSLP and SLPEN
for controlling the state of the pins over sleep.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

1 files changed, 27 insertions, 0 deletions

diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
index 51a84cd6320e..d45d66b8c2fa 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
@@ -33,6 +33,10 @@
 #define S3C64XX_GPP_BASE        S3C64XX_GPIOREG(0x0160)
 #define S3C64XX_GPQ_BASE        S3C64XX_GPIOREG(0x0180)
 
+/* SPCON */
+
+#define S3C64XX_SPCON           S3C64XX_GPIOREG(0x1A0)
+
 /* External interrupt registers */
 
 #define S3C64XX_EINT12CON       S3C64XX_GPIOREG(0x200)
@@ -75,5 +79,28 @@
 #define S3C64XX_EINT0MASK       S3C64XX_GPIOREG(0x920)
 #define S3C64XX_EINT0PEND       S3C64XX_GPIOREG(0x924)
 
+/* GPIO sleep configuration */
+
+#define S3C64XX_SPCONSLP        S3C64XX_GPIOREG(0x880)
+
+#define S3C64XX_SPCONSLP_TDO_PULLDOWN   (1 << 14)
+#define S3C64XX_SPCONSLP_CKE1INIT       (1 << 5)
+
+#define S3C64XX_SPCONSLP_RSTOUT_MASK    (0x3 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT0    (0x0 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT1    (0x1 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_HIZ     (0x2 << 12)
+
+#define S3C64XX_SPCONSLP_KPCOL_MASK     (0x3 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT0     (0x0 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT1     (0x1 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_INP      (0x2 << 0)
+
+
+#define S3C64XX_SLPEN           S3C64XX_GPIOREG(0x930)
+
+#define S3C64XX_SLPEN_USE_xSLP          (1 << 0)
+#define S3C64XX_SLPEN_CFG_BYSLPEN       (1 << 1)
+
 #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */