aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorCyrill Gorcunov <gorcunov@openvz.org>2010-03-24 00:09:26 -0400
committerIngo Molnar <mingo@elte.hu>2010-03-26 03:45:49 -0400
commitd814f30105798b6677ecb73ed61d691ff96dada9 (patch)
treecd86bae8a9790987c990a445fb70e662f3736fc6
parent88978e562302c836c1c4597700c79d971e93abc0 (diff)
x86, perf: Add raw events support for the P4 PMU
The adding of raw event support lead to complete code refactoring. I hope is became more readable then it was. The list of changes: 1) The 64bit config field is enough to hold all information we need to track event details. To achieve it we used *own* enum for events selection in ESCR register and map this key into proper value at moment of event enabling. For the same reason we use 12LSB bits in CCCR register -- to track which exactly cache trace event was requested. And we cear this bits at real 'write' moment. 2) There is no per-cpu area reserved for P4 PMU anymore. We don't need it. All is held by config. 3) Now we may use any available counter, ie we try to grab any possible counter. v2: - Lin Ming reported the lack of ESCR selector in CCCR for cache events v3: - Don't loose cache event codes at config unpacking procedure, we may need it one day so no obscure hack behind our back, better to clear reserved bits explicitly when needed (thanks Ming for pointing out) - Lin Ming fixed misplaced opcodes in cache events Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Tested-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Stephane Eranian <eranian@google.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Cyrill Gorcunov <gorcunov@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> LKML-Reference: <1269403766.3409.6.camel@minggr.sh.intel.com> [ v4: did a few whitespace fixlets ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat
-rw-r--r--arch/x86/include/asm/perf_event_p4.h691
-rw-r--r--arch/x86/kernel/cpu/perf_event_p4.c746
2 files changed, 806 insertions, 631 deletions
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index facf96186b26..b05400a542ff 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -15,38 +15,40 @@
15 * perf-MSRs are not shared and every thread has its 15 * perf-MSRs are not shared and every thread has its
16 * own perf-MSRs set) 16 * own perf-MSRs set)
17 */ 17 */
18#define ARCH_P4_TOTAL_ESCR (46) 18#define ARCH_P4_TOTAL_ESCR (46)
19#define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 19#define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */
20#define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 20#define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
21#define ARCH_P4_MAX_CCCR (18) 21#define ARCH_P4_MAX_CCCR (18)
22#define ARCH_P4_MAX_COUNTER (ARCH_P4_MAX_CCCR / 2) 22#define ARCH_P4_MAX_COUNTER (ARCH_P4_MAX_CCCR / 2)
23 23
24#define P4_EVNTSEL_EVENT_MASK 0x7e000000U 24#define P4_ESCR_EVENT_MASK 0x7e000000U
25#define P4_EVNTSEL_EVENT_SHIFT 25 25#define P4_ESCR_EVENT_SHIFT 25
26#define P4_EVNTSEL_EVENTMASK_MASK 0x01fffe00U 26#define P4_ESCR_EVENTMASK_MASK 0x01fffe00U
27#define P4_EVNTSEL_EVENTMASK_SHIFT 9 27#define P4_ESCR_EVENTMASK_SHIFT 9
28#define P4_EVNTSEL_TAG_MASK 0x000001e0U 28#define P4_ESCR_TAG_MASK 0x000001e0U
29#define P4_EVNTSEL_TAG_SHIFT 5 29#define P4_ESCR_TAG_SHIFT 5
30#define P4_EVNTSEL_TAG_ENABLE 0x00000010U 30#define P4_ESCR_TAG_ENABLE 0x00000010U
31#define P4_EVNTSEL_T0_OS 0x00000008U 31#define P4_ESCR_T0_OS 0x00000008U
32#define P4_EVNTSEL_T0_USR 0x00000004U 32#define P4_ESCR_T0_USR 0x00000004U
33#define P4_EVNTSEL_T1_OS 0x00000002U 33#define P4_ESCR_T1_OS 0x00000002U
34#define P4_EVNTSEL_T1_USR 0x00000001U 34#define P4_ESCR_T1_USR 0x00000001U
35
36#define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT)
37#define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT)
38#define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT)
35 39
36/* Non HT mask */ 40/* Non HT mask */
37#define P4_EVNTSEL_MASK \ 41#define P4_ESCR_MASK \
38 (P4_EVNTSEL_EVENT_MASK | \ 42 (P4_ESCR_EVENT_MASK | \
39 P4_EVNTSEL_EVENTMASK_MASK | \ 43 P4_ESCR_EVENTMASK_MASK | \
40 P4_EVNTSEL_TAG_MASK | \ 44 P4_ESCR_TAG_MASK | \
41 P4_EVNTSEL_TAG_ENABLE | \ 45 P4_ESCR_TAG_ENABLE | \
42 P4_EVNTSEL_T0_OS | \ 46 P4_ESCR_T0_OS | \
43 P4_EVNTSEL_T0_USR) 47 P4_ESCR_T0_USR)
44 48
45/* HT mask */ 49/* HT mask */
46#define P4_EVNTSEL_MASK_HT \ 50#define P4_ESCR_MASK_HT \
47 (P4_EVNTSEL_MASK | \ 51 (P4_ESCR_MASK | P4_ESCR_T1_OS | P4_ESCR_T1_USR)
48 P4_EVNTSEL_T1_OS | \
49 P4_EVNTSEL_T1_USR)
50 52
51#define P4_CCCR_OVF 0x80000000U 53#define P4_CCCR_OVF 0x80000000U
52#define P4_CCCR_CASCADE 0x40000000U 54#define P4_CCCR_CASCADE 0x40000000U
@@ -56,7 +58,6 @@
56#define P4_CCCR_EDGE 0x01000000U 58#define P4_CCCR_EDGE 0x01000000U
57#define P4_CCCR_THRESHOLD_MASK 0x00f00000U 59#define P4_CCCR_THRESHOLD_MASK 0x00f00000U
58#define P4_CCCR_THRESHOLD_SHIFT 20 60#define P4_CCCR_THRESHOLD_SHIFT 20
59#define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)
60#define P4_CCCR_COMPLEMENT 0x00080000U 61#define P4_CCCR_COMPLEMENT 0x00080000U
61#define P4_CCCR_COMPARE 0x00040000U 62#define P4_CCCR_COMPARE 0x00040000U
62#define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 63#define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U
@@ -67,6 +68,13 @@
67#define P4_CCCR_THREAD_ANY 0x00030000U 68#define P4_CCCR_THREAD_ANY 0x00030000U
68#define P4_CCCR_RESERVED 0x00000fffU 69#define P4_CCCR_RESERVED 0x00000fffU
69 70
71#define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)
72#define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
73
74/* Custom bits in reerved CCCR area */
75#define P4_CCCR_CACHE_OPS_MASK 0x0000003fU
76
77
70/* Non HT mask */ 78/* Non HT mask */
71#define P4_CCCR_MASK \ 79#define P4_CCCR_MASK \
72 (P4_CCCR_OVF | \ 80 (P4_CCCR_OVF | \
@@ -81,25 +89,11 @@
81 P4_CCCR_ENABLE) 89 P4_CCCR_ENABLE)
82 90
83/* HT mask */ 91/* HT mask */
84#define P4_CCCR_MASK_HT \ 92#define P4_CCCR_MASK_HT (P4_CCCR_MASK | P4_CCCR_THREAD_ANY)
85 (P4_CCCR_MASK | \
86 P4_CCCR_THREAD_ANY)
87 93
88/* 94#define P4_GEN_ESCR_EMASK(class, name, bit) \
89 * format is 32 bit: ee ss aa aa 95 class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
90 * where 96#define P4_ESCR_EMASK_BIT(class, name) class##__##name
91 * ee - 8 bit event
92 * ss - 8 bit selector
93 * aa aa - 16 bits reserved for tags/attributes
94 */
95#define P4_EVENT_PACK(event, selector) (((event) << 24) | ((selector) << 16))
96#define P4_EVENT_UNPACK_EVENT(packed) (((packed) >> 24) & 0xff)
97#define P4_EVENT_UNPACK_SELECTOR(packed) (((packed) >> 16) & 0xff)
98#define P4_EVENT_PACK_ATTR(attr) ((attr))
99#define P4_EVENT_UNPACK_ATTR(packed) ((packed) & 0xffff)
100#define P4_MAKE_EVENT_ATTR(class, name, bit) class##_##name = (1 << bit)
101#define P4_EVENT_ATTR(class, name) class##_##name
102#define P4_EVENT_ATTR_STR(class, name) __stringify(class##_##name)
103 97
104/* 98/*
105 * config field is 64bit width and consists of 99 * config field is 64bit width and consists of
@@ -117,35 +111,29 @@
117#define p4_config_pack_escr(v) (((u64)(v)) << 32) 111#define p4_config_pack_escr(v) (((u64)(v)) << 32)
118#define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 112#define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL)
119#define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 113#define p4_config_unpack_escr(v) (((u64)(v)) >> 32)
120#define p4_config_unpack_cccr(v) (((u64)(v)) & 0xfffff000ULL) 114#define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL)
121 115
122#define p4_config_unpack_emask(v) \ 116#define p4_config_unpack_emask(v) \
123 ({ \ 117 ({ \
124 u32 t = p4_config_unpack_escr((v)); \ 118 u32 t = p4_config_unpack_escr((v)); \
125 t &= P4_EVNTSEL_EVENTMASK_MASK; \ 119 t = t & P4_ESCR_EVENTMASK_MASK; \
126 t >>= P4_EVNTSEL_EVENTMASK_SHIFT; \ 120 t = t >> P4_ESCR_EVENTMASK_SHIFT; \
121 t; \
122 })
123
124#define p4_config_unpack_event(v) \
125 ({ \
126 u32 t = p4_config_unpack_escr((v)); \
127 t = t & P4_ESCR_EVENT_MASK; \
128 t = t >> P4_ESCR_EVENT_SHIFT; \
127 t; \ 129 t; \
128 }) 130 })
129 131
130#define p4_config_unpack_key(v) (((u64)(v)) & P4_CCCR_RESERVED) 132#define p4_config_unpack_cache_event(v) (((u64)(v)) & P4_CCCR_CACHE_OPS_MASK)
131 133
132#define P4_CONFIG_HT_SHIFT 63 134#define P4_CONFIG_HT_SHIFT 63
133#define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 135#define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT)
134 136
135static inline u32 p4_config_unpack_opcode(u64 config)
136{
137 u32 e, s;
138
139 /*
140 * we don't care about HT presence here since
141 * event opcode doesn't depend on it
142 */
143 e = (p4_config_unpack_escr(config) & P4_EVNTSEL_EVENT_MASK) >> P4_EVNTSEL_EVENT_SHIFT;
144 s = (p4_config_unpack_cccr(config) & P4_CCCR_ESCR_SELECT_MASK) >> P4_CCCR_ESCR_SELECT_SHIFT;
145
146 return P4_EVENT_PACK(e, s);
147}
148
149static inline bool p4_is_event_cascaded(u64 config) 137static inline bool p4_is_event_cascaded(u64 config)
150{ 138{
151 u32 cccr = p4_config_unpack_cccr(config); 139 u32 cccr = p4_config_unpack_cccr(config);
@@ -212,19 +200,73 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
212 200
213 if (!p4_ht_thread(cpu)) { 201 if (!p4_ht_thread(cpu)) {
214 if (!exclude_os) 202 if (!exclude_os)
215 escr |= P4_EVNTSEL_T0_OS; 203 escr |= P4_ESCR_T0_OS;
216 if (!exclude_usr) 204 if (!exclude_usr)
217 escr |= P4_EVNTSEL_T0_USR; 205 escr |= P4_ESCR_T0_USR;
218 } else { 206 } else {
219 if (!exclude_os) 207 if (!exclude_os)
220 escr |= P4_EVNTSEL_T1_OS; 208 escr |= P4_ESCR_T1_OS;
221 if (!exclude_usr) 209 if (!exclude_usr)
222 escr |= P4_EVNTSEL_T1_USR; 210 escr |= P4_ESCR_T1_USR;
223 } 211 }
224 212
225 return escr; 213 return escr;
226} 214}
227 215
216enum P4_EVENTS {
217 P4_EVENT_TC_DELIVER_MODE,
218 P4_EVENT_BPU_FETCH_REQUEST,
219 P4_EVENT_ITLB_REFERENCE,
220 P4_EVENT_MEMORY_CANCEL,
221 P4_EVENT_MEMORY_COMPLETE,
222 P4_EVENT_LOAD_PORT_REPLAY,
223 P4_EVENT_STORE_PORT_REPLAY,
224 P4_EVENT_MOB_LOAD_REPLAY,
225 P4_EVENT_PAGE_WALK_TYPE,
226 P4_EVENT_BSQ_CACHE_REFERENCE,
227 P4_EVENT_IOQ_ALLOCATION,
228 P4_EVENT_IOQ_ACTIVE_ENTRIES,
229 P4_EVENT_FSB_DATA_ACTIVITY,
230 P4_EVENT_BSQ_ALLOCATION,
231 P4_EVENT_BSQ_ACTIVE_ENTRIES,
232 P4_EVENT_SSE_INPUT_ASSIST,
233 P4_EVENT_PACKED_SP_UOP,
234 P4_EVENT_PACKED_DP_UOP,
235 P4_EVENT_SCALAR_SP_UOP,
236 P4_EVENT_SCALAR_DP_UOP,
237 P4_EVENT_64BIT_MMX_UOP,
238 P4_EVENT_128BIT_MMX_UOP,
239 P4_EVENT_X87_FP_UOP,
240 P4_EVENT_TC_MISC,
241 P4_EVENT_GLOBAL_POWER_EVENTS,
242 P4_EVENT_TC_MS_XFER,
243 P4_EVENT_UOP_QUEUE_WRITES,
244 P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
245 P4_EVENT_RETIRED_BRANCH_TYPE,
246 P4_EVENT_RESOURCE_STALL,
247 P4_EVENT_WC_BUFFER,
248 P4_EVENT_B2B_CYCLES,
249 P4_EVENT_BNR,
250 P4_EVENT_SNOOP,
251 P4_EVENT_RESPONSE,
252 P4_EVENT_FRONT_END_EVENT,
253 P4_EVENT_EXECUTION_EVENT,
254 P4_EVENT_REPLAY_EVENT,
255 P4_EVENT_INSTR_RETIRED,
256 P4_EVENT_UOPS_RETIRED,
257 P4_EVENT_UOP_TYPE,
258 P4_EVENT_BRANCH_RETIRED,
259 P4_EVENT_MISPRED_BRANCH_RETIRED,
260 P4_EVENT_X87_ASSIST,
261 P4_EVENT_MACHINE_CLEAR,
262 P4_EVENT_INSTR_COMPLETED,
263};
264
265#define P4_OPCODE(event) event##_OPCODE
266#define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0)
267#define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8)
268#define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel)
269
228/* 270/*
229 * Comments below the event represent ESCR restriction 271 * Comments below the event represent ESCR restriction
230 * for this event and counter index per ESCR 272 * for this event and counter index per ESCR
@@ -238,484 +280,515 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
238 * working so that we should not use this CCCR and respective 280 * working so that we should not use this CCCR and respective
239 * counter as result 281 * counter as result
240 */ 282 */
241#define P4_TC_DELIVER_MODE P4_EVENT_PACK(0x01, 0x01) 283enum P4_EVENT_OPCODES {
284 P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),
242 /* 285 /*
243 * MSR_P4_TC_ESCR0: 4, 5 286 * MSR_P4_TC_ESCR0: 4, 5
244 * MSR_P4_TC_ESCR1: 6, 7 287 * MSR_P4_TC_ESCR1: 6, 7
245 */ 288 */
246 289
247#define P4_BPU_FETCH_REQUEST P4_EVENT_PACK(0x03, 0x00) 290 P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00),
248 /* 291 /*
249 * MSR_P4_BPU_ESCR0: 0, 1 292 * MSR_P4_BPU_ESCR0: 0, 1
250 * MSR_P4_BPU_ESCR1: 2, 3 293 * MSR_P4_BPU_ESCR1: 2, 3
251 */ 294 */
252 295
253#define P4_ITLB_REFERENCE P4_EVENT_PACK(0x18, 0x03) 296 P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03),
254 /* 297 /*
255 * MSR_P4_ITLB_ESCR0: 0, 1 298 * MSR_P4_ITLB_ESCR0: 0, 1
256 * MSR_P4_ITLB_ESCR1: 2, 3 299 * MSR_P4_ITLB_ESCR1: 2, 3
257 */ 300 */
258 301
259#define P4_MEMORY_CANCEL P4_EVENT_PACK(0x02, 0x05) 302 P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05),
260 /* 303 /*
261 * MSR_P4_DAC_ESCR0: 8, 9 304 * MSR_P4_DAC_ESCR0: 8, 9
262 * MSR_P4_DAC_ESCR1: 10, 11 305 * MSR_P4_DAC_ESCR1: 10, 11
263 */ 306 */
264 307
265#define P4_MEMORY_COMPLETE P4_EVENT_PACK(0x08, 0x02) 308 P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02),
266 /* 309 /*
267 * MSR_P4_SAAT_ESCR0: 8, 9 310 * MSR_P4_SAAT_ESCR0: 8, 9
268 * MSR_P4_SAAT_ESCR1: 10, 11 311 * MSR_P4_SAAT_ESCR1: 10, 11
269 */ 312 */
270 313
271#define P4_LOAD_PORT_REPLAY P4_EVENT_PACK(0x04, 0x02) 314 P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02),
272 /* 315 /*
273 * MSR_P4_SAAT_ESCR0: 8, 9 316 * MSR_P4_SAAT_ESCR0: 8, 9
274 * MSR_P4_SAAT_ESCR1: 10, 11 317 * MSR_P4_SAAT_ESCR1: 10, 11
275 */ 318 */
276 319
277#define P4_STORE_PORT_REPLAY P4_EVENT_PACK(0x05, 0x02) 320 P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02),
278 /* 321 /*
279 * MSR_P4_SAAT_ESCR0: 8, 9 322 * MSR_P4_SAAT_ESCR0: 8, 9
280 * MSR_P4_SAAT_ESCR1: 10, 11 323 * MSR_P4_SAAT_ESCR1: 10, 11
281 */ 324 */
282 325
283#define P4_MOB_LOAD_REPLAY P4_EVENT_PACK(0x03, 0x02) 326 P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02),
284 /* 327 /*
285 * MSR_P4_MOB_ESCR0: 0, 1 328 * MSR_P4_MOB_ESCR0: 0, 1
286 * MSR_P4_MOB_ESCR1: 2, 3 329 * MSR_P4_MOB_ESCR1: 2, 3
287 */ 330 */
288 331
289#define P4_PAGE_WALK_TYPE P4_EVENT_PACK(0x01, 0x04) 332 P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04),
290 /* 333 /*
291 * MSR_P4_PMH_ESCR0: 0, 1 334 * MSR_P4_PMH_ESCR0: 0, 1
292 * MSR_P4_PMH_ESCR1: 2, 3 335 * MSR_P4_PMH_ESCR1: 2, 3
293 */ 336 */
294 337
295#define P4_BSQ_CACHE_REFERENCE P4_EVENT_PACK(0x0c, 0x07) 338 P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07),
296 /* 339 /*
297 * MSR_P4_BSU_ESCR0: 0, 1 340 * MSR_P4_BSU_ESCR0: 0, 1
298 * MSR_P4_BSU_ESCR1: 2, 3 341 * MSR_P4_BSU_ESCR1: 2, 3
299 */ 342 */
300 343
301#define P4_IOQ_ALLOCATION P4_EVENT_PACK(0x03, 0x06) 344 P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06),
302 /* 345 /*
303 * MSR_P4_FSB_ESCR0: 0, 1 346 * MSR_P4_FSB_ESCR0: 0, 1
304 * MSR_P4_FSB_ESCR1: 2, 3 347 * MSR_P4_FSB_ESCR1: 2, 3
305 */ 348 */
306 349
307#define P4_IOQ_ACTIVE_ENTRIES P4_EVENT_PACK(0x1a, 0x06) 350 P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06),
308 /* 351 /*
309 * MSR_P4_FSB_ESCR1: 2, 3 352 * MSR_P4_FSB_ESCR1: 2, 3
310 */ 353 */
311 354
312#define P4_FSB_DATA_ACTIVITY P4_EVENT_PACK(0x17, 0x06) 355 P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06),
313 /* 356 /*
314 * MSR_P4_FSB_ESCR0: 0, 1 357 * MSR_P4_FSB_ESCR0: 0, 1
315 * MSR_P4_FSB_ESCR1: 2, 3 358 * MSR_P4_FSB_ESCR1: 2, 3
316 */ 359 */
317 360
318#define P4_BSQ_ALLOCATION P4_EVENT_PACK(0x05, 0x07) 361 P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07),
319 /* 362 /*
320 * MSR_P4_BSU_ESCR0: 0, 1 363 * MSR_P4_BSU_ESCR0: 0, 1
321 */ 364 */
322 365
323#define P4_BSQ_ACTIVE_ENTRIES P4_EVENT_PACK(0x06, 0x07) 366 P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07),
324 /* 367 /*
325 * NOTE: no ESCR name in docs, it's guessed 368 * NOTE: no ESCR name in docs, it's guessed
326 * MSR_P4_BSU_ESCR1: 2, 3 369 * MSR_P4_BSU_ESCR1: 2, 3
327 */ 370 */
328 371
329#define P4_SSE_INPUT_ASSIST P4_EVENT_PACK(0x34, 0x01) 372 P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01),
330 /* 373 /*
331 * MSR_P4_FIRM_ESCR0: 8, 9 374 * MSR_P4_FIRM_ESCR0: 8, 9
332 * MSR_P4_FIRM_ESCR1: 10, 11 375 * MSR_P4_FIRM_ESCR1: 10, 11
333 */ 376 */
334 377
335#define P4_PACKED_SP_UOP P4_EVENT_PACK(0x08, 0x01) 378 P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01),
336 /* 379 /*
337 * MSR_P4_FIRM_ESCR0: 8, 9 380 * MSR_P4_FIRM_ESCR0: 8, 9
338 * MSR_P4_FIRM_ESCR1: 10, 11 381 * MSR_P4_FIRM_ESCR1: 10, 11
339 */ 382 */
340 383
341#define P4_PACKED_DP_UOP P4_EVENT_PACK(0x0c, 0x01) 384 P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01),
342 /* 385 /*
343 * MSR_P4_FIRM_ESCR0: 8, 9 386 * MSR_P4_FIRM_ESCR0: 8, 9
344 * MSR_P4_FIRM_ESCR1: 10, 11 387 * MSR_P4_FIRM_ESCR1: 10, 11
345 */ 388 */
346 389
347#define P4_SCALAR_SP_UOP P4_EVENT_PACK(0x0a, 0x01) 390 P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01),
348 /* 391 /*
349 * MSR_P4_FIRM_ESCR0: 8, 9 392 * MSR_P4_FIRM_ESCR0: 8, 9
350 * MSR_P4_FIRM_ESCR1: 10, 11 393 * MSR_P4_FIRM_ESCR1: 10, 11
351 */ 394 */
352 395
353#define P4_SCALAR_DP_UOP P4_EVENT_PACK(0x0e, 0x01) 396 P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01),
354 /* 397 /*
355 * MSR_P4_FIRM_ESCR0: 8, 9 398 * MSR_P4_FIRM_ESCR0: 8, 9
356 * MSR_P4_FIRM_ESCR1: 10, 11 399 * MSR_P4_FIRM_ESCR1: 10, 11
357 */ 400 */
358 401
359#define P4_64BIT_MMX_UOP P4_EVENT_PACK(0x02, 0x01) 402 P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01),
360 /* 403 /*
361 * MSR_P4_FIRM_ESCR0: 8, 9 404 * MSR_P4_FIRM_ESCR0: 8, 9
362 * MSR_P4_FIRM_ESCR1: 10, 11 405 * MSR_P4_FIRM_ESCR1: 10, 11
363 */ 406 */
364 407
365#define P4_128BIT_MMX_UOP P4_EVENT_PACK(0x1a, 0x01) 408 P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01),
366 /* 409 /*
367 * MSR_P4_FIRM_ESCR0: 8, 9 410 * MSR_P4_FIRM_ESCR0: 8, 9
368 * MSR_P4_FIRM_ESCR1: 10, 11 411 * MSR_P4_FIRM_ESCR1: 10, 11
369 */ 412 */
370 413
371#define P4_X87_FP_UOP P4_EVENT_PACK(0x04, 0x01) 414 P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01),
372 /* 415 /*
373 * MSR_P4_FIRM_ESCR0: 8, 9 416 * MSR_P4_FIRM_ESCR0: 8, 9
374 * MSR_P4_FIRM_ESCR1: 10, 11 417 * MSR_P4_FIRM_ESCR1: 10, 11
375 */ 418 */
376 419
377#define P4_TC_MISC P4_EVENT_PACK(0x06, 0x01) 420 P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01),
378 /* 421 /*
379 * MSR_P4_TC_ESCR0: 4, 5 422 * MSR_P4_TC_ESCR0: 4, 5
380 * MSR_P4_TC_ESCR1: 6, 7 423 * MSR_P4_TC_ESCR1: 6, 7
381 */ 424 */
382 425
383#define P4_GLOBAL_POWER_EVENTS P4_EVENT_PACK(0x13, 0x06) 426 P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06),
384 /* 427 /*
385 * MSR_P4_FSB_ESCR0: 0, 1 428 * MSR_P4_FSB_ESCR0: 0, 1
386 * MSR_P4_FSB_ESCR1: 2, 3 429 * MSR_P4_FSB_ESCR1: 2, 3
387 */ 430 */
388 431
389#define P4_TC_MS_XFER P4_EVENT_PACK(0x05, 0x00) 432 P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00),
390 /* 433 /*
391 * MSR_P4_MS_ESCR0: 4, 5 434 * MSR_P4_MS_ESCR0: 4, 5
392 * MSR_P4_MS_ESCR1: 6, 7 435 * MSR_P4_MS_ESCR1: 6, 7
393 */ 436 */
394 437
395#define P4_UOP_QUEUE_WRITES P4_EVENT_PACK(0x09, 0x00) 438 P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00),
396 /* 439 /*
397 * MSR_P4_MS_ESCR0: 4, 5 440 * MSR_P4_MS_ESCR0: 4, 5
398 * MSR_P4_MS_ESCR1: 6, 7 441 * MSR_P4_MS_ESCR1: 6, 7
399 */ 442 */
400 443
401#define P4_RETIRED_MISPRED_BRANCH_TYPE P4_EVENT_PACK(0x05, 0x02) 444 P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02),
402 /* 445 /*
403 * MSR_P4_TBPU_ESCR0: 4, 5 446 * MSR_P4_TBPU_ESCR0: 4, 5
404 * MSR_P4_TBPU_ESCR1: 6, 7 447 * MSR_P4_TBPU_ESCR1: 6, 7
405 */ 448 */
406 449
407#define P4_RETIRED_BRANCH_TYPE P4_EVENT_PACK(0x04, 0x02) 450 P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02),
408 /* 451 /*
409 * MSR_P4_TBPU_ESCR0: 4, 5 452 * MSR_P4_TBPU_ESCR0: 4, 5
410 * MSR_P4_TBPU_ESCR1: 6, 7 453 * MSR_P4_TBPU_ESCR1: 6, 7
411 */ 454 */
412 455
413#define P4_RESOURCE_STALL P4_EVENT_PACK(0x01, 0x01) 456 P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01),
414 /* 457 /*
415 * MSR_P4_ALF_ESCR0: 12, 13, 16 458 * MSR_P4_ALF_ESCR0: 12, 13, 16
416 * MSR_P4_ALF_ESCR1: 14, 15, 17 459 * MSR_P4_ALF_ESCR1: 14, 15, 17
417 */ 460 */
418 461
419#define P4_WC_BUFFER P4_EVENT_PACK(0x05, 0x05) 462 P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05),
420 /* 463 /*
421 * MSR_P4_DAC_ESCR0: 8, 9 464 * MSR_P4_DAC_ESCR0: 8, 9
422 * MSR_P4_DAC_ESCR1: 10, 11 465 * MSR_P4_DAC_ESCR1: 10, 11
423 */ 466 */
424 467
425#define P4_B2B_CYCLES P4_EVENT_PACK(0x16, 0x03) 468 P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03),
426 /* 469 /*
427 * MSR_P4_FSB_ESCR0: 0, 1 470 * MSR_P4_FSB_ESCR0: 0, 1
428 * MSR_P4_FSB_ESCR1: 2, 3 471 * MSR_P4_FSB_ESCR1: 2, 3
429 */ 472 */
430 473
431#define P4_BNR P4_EVENT_PACK(0x08, 0x03) 474 P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03),
432 /* 475 /*
433 * MSR_P4_FSB_ESCR0: 0, 1 476 * MSR_P4_FSB_ESCR0: 0, 1
434 * MSR_P4_FSB_ESCR1: 2, 3 477 * MSR_P4_FSB_ESCR1: 2, 3
435 */ 478 */
436 479
437#define P4_SNOOP P4_EVENT_PACK(0x06, 0x03) 480 P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03),
438 /* 481 /*
439 * MSR_P4_FSB_ESCR0: 0, 1 482 * MSR_P4_FSB_ESCR0: 0, 1
440 * MSR_P4_FSB_ESCR1: 2, 3 483 * MSR_P4_FSB_ESCR1: 2, 3
441 */ 484 */
442 485
443#define P4_RESPONSE P4_EVENT_PACK(0x04, 0x03) 486 P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03),
444 /* 487 /*
445 * MSR_P4_FSB_ESCR0: 0, 1 488 * MSR_P4_FSB_ESCR0: 0, 1
446 * MSR_P4_FSB_ESCR1: 2, 3 489 * MSR_P4_FSB_ESCR1: 2, 3
447 */ 490 */
448 491
449#define P4_FRONT_END_EVENT P4_EVENT_PACK(0x08, 0x05) 492 P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05),
450 /* 493 /*
451 * MSR_P4_CRU_ESCR2: 12, 13, 16 494 * MSR_P4_CRU_ESCR2: 12, 13, 16
452 * MSR_P4_CRU_ESCR3: 14, 15, 17 495 * MSR_P4_CRU_ESCR3: 14, 15, 17
453 */ 496 */
454 497
455#define P4_EXECUTION_EVENT P4_EVENT_PACK(0x0c, 0x05) 498 P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05),
456 /* 499 /*
457 * MSR_P4_CRU_ESCR2: 12, 13, 16 500 * MSR_P4_CRU_ESCR2: 12, 13, 16
458 * MSR_P4_CRU_ESCR3: 14, 15, 17 501 * MSR_P4_CRU_ESCR3: 14, 15, 17
459 */ 502 */
460 503
461#define P4_REPLAY_EVENT P4_EVENT_PACK(0x09, 0x05) 504 P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05),
462 /* 505 /*
463 * MSR_P4_CRU_ESCR2: 12, 13, 16 506 * MSR_P4_CRU_ESCR2: 12, 13, 16
464 * MSR_P4_CRU_ESCR3: 14, 15, 17 507 * MSR_P4_CRU_ESCR3: 14, 15, 17
465 */ 508 */
466 509
467#define P4_INSTR_RETIRED P4_EVENT_PACK(0x02, 0x04) 510 P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04),
468 /* 511 /*
469 * MSR_P4_CRU_ESCR0: 12, 13, 16 512 * MSR_P4_CRU_ESCR0: 12, 13, 16
470 * MSR_P4_CRU_ESCR1: 14, 15, 17 513 * MSR_P4_CRU_ESCR1: 14, 15, 17
471 */ 514 */
472 515
473#define P4_UOPS_RETIRED P4_EVENT_PACK(0x01, 0x04) 516 P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04),
474 /* 517 /*
475 * MSR_P4_CRU_ESCR0: 12, 13, 16 518 * MSR_P4_CRU_ESCR0: 12, 13, 16
476 * MSR_P4_CRU_ESCR1: 14, 15, 17 519 * MSR_P4_CRU_ESCR1: 14, 15, 17
477 */ 520 */
478 521
479#define P4_UOP_TYPE P4_EVENT_PACK(0x02, 0x02) 522 P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02),
480 /* 523 /*
481 * MSR_P4_RAT_ESCR0: 12, 13, 16 524 * MSR_P4_RAT_ESCR0: 12, 13, 16
482 * MSR_P4_RAT_ESCR1: 14, 15, 17 525 * MSR_P4_RAT_ESCR1: 14, 15, 17
483 */ 526 */
484 527
485#define P4_BRANCH_RETIRED P4_EVENT_PACK(0x06, 0x05) 528 P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05),
486 /* 529 /*
487 * MSR_P4_CRU_ESCR2: 12, 13, 16 530 * MSR_P4_CRU_ESCR2: 12, 13, 16
488 * MSR_P4_CRU_ESCR3: 14, 15, 17 531 * MSR_P4_CRU_ESCR3: 14, 15, 17
489 */ 532 */
490 533
491#define P4_MISPRED_BRANCH_RETIRED P4_EVENT_PACK(0x03, 0x04) 534 P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04),
492 /* 535 /*
493 * MSR_P4_CRU_ESCR0: 12, 13, 16 536 * MSR_P4_CRU_ESCR0: 12, 13, 16
494 * MSR_P4_CRU_ESCR1: 14, 15, 17 537 * MSR_P4_CRU_ESCR1: 14, 15, 17
495 */ 538 */
496 539
497#define P4_X87_ASSIST P4_EVENT_PACK(0x03, 0x05) 540 P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05),
498 /* 541 /*
499 * MSR_P4_CRU_ESCR2: 12, 13, 16 542 * MSR_P4_CRU_ESCR2: 12, 13, 16
500 * MSR_P4_CRU_ESCR3: 14, 15, 17 543 * MSR_P4_CRU_ESCR3: 14, 15, 17
501 */ 544 */
502 545
503#define P4_MACHINE_CLEAR P4_EVENT_PACK(0x02, 0x05) 546 P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05),
504 /* 547 /*
505 * MSR_P4_CRU_ESCR2: 12, 13, 16 548 * MSR_P4_CRU_ESCR2: 12, 13, 16
506 * MSR_P4_CRU_ESCR3: 14, 15, 17 549 * MSR_P4_CRU_ESCR3: 14, 15, 17
507 */ 550 */
508 551
509#define P4_INSTR_COMPLETED P4_EVENT_PACK(0x07, 0x04) 552 P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04),
510 /* 553 /*
511 * MSR_P4_CRU_ESCR0: 12, 13, 16 554 * MSR_P4_CRU_ESCR0: 12, 13, 16
512 * MSR_P4_CRU_ESCR1: 14, 15, 17 555 * MSR_P4_CRU_ESCR1: 14, 15, 17
513 */ 556 */
557};
514 558
515/* 559/*
516 * a caller should use P4_EVENT_ATTR helper to 560 * a caller should use P4_ESCR_EMASK_NAME helper to
517 * pick the attribute needed, for example 561 * pick the EventMask needed, for example
518 * 562 *
519 * P4_EVENT_ATTR(P4_TC_DELIVER_MODE, DD) 563 * P4_ESCR_EMASK_NAME(P4_EVENT_TC_DELIVER_MODE, DD)
520 */ 564 */
521enum P4_EVENTS_ATTR { 565enum P4_ESCR_EMASKS {
522 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DD, 0), 566 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0),
523 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DB, 1), 567 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1),
524 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DI, 2), 568 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2),
525 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BD, 3), 569 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3),
526 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BB, 4), 570 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4),
527 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BI, 5), 571 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5),
528 P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, ID, 6), 572 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6),
529 573
530 P4_MAKE_EVENT_ATTR(P4_BPU_FETCH_REQUEST, TCMISS, 0), 574 P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0),
531 575
532 P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT, 0), 576 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0),
533 P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, MISS, 1), 577 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1),
534 P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT_UK, 2), 578 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2),
535 579
536 P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, ST_RB_FULL, 2), 580 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2),
537 P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, 64K_CONF, 3), 581 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3),
538 582
539 P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, LSC, 0), 583 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0),
540 P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, SSC, 1), 584 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
541 585
542 P4_MAKE_EVENT_ATTR(P4_LOAD_PORT_REPLAY, SPLIT_LD, 1), 586 P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1),
543 587
544 P4_MAKE_EVENT_ATTR(P4_STORE_PORT_REPLAY, SPLIT_ST, 1), 588 P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1),
545 589
546 P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STA, 1), 590 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1),
547 P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STD, 3), 591 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3),
548 P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 592 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
549 P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 593 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
550 594
551 P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, DTMISS, 0), 595 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0),
552 P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, ITMISS, 1), 596 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1),
553 597
554 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 598 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
555 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 599 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
556 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 600 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
557 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 601 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
558 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 602 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
559 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 603 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
560 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 604 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
561 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 605 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
562 P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 606 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
563 607
564 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, DEFAULT, 0), 608 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0),
565 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_READ, 5), 609 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5),
566 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_WRITE, 6), 610 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6),
567 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_UC, 7), 611 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7),
568 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WC, 8), 612 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8),
569 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WT, 9), 613 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9),
570 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WP, 10), 614 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10),
571 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WB, 11), 615 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11),
572 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OWN, 13), 616 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13),
573 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OTHER, 14), 617 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14),
574 P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, PREFETCH, 15), 618 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15),
575 619
576 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 620 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
577 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 621 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
578 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 622 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
579 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 623 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
580 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 624 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
581 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 625 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
582 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 626 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
583 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 627 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
584 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OWN, 13), 628 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13),
585 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OTHER, 14), 629 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14),
586 P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 630 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
587 631
588 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 632 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
589 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 633 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
590 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 634 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
591 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 635 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
592 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 636 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
593 P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 637 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
594 638
595 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE0, 0), 639 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0),
596 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE1, 1), 640 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1),
597 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN0, 2), 641 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2),
598 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN1, 3), 642 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3),
599 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 643 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
600 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 644 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
601 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 645 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
602 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 646 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
603 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 647 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
604 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 648 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
605 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE0, 11), 649 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11),
606 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE1, 12), 650 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12),
607 P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE2, 13), 651 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13),
608 652
609 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 653 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
610 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 654 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
611 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 655 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
612 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 656 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
613 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 657 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
614 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 658 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
615 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 659 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
616 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 660 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
617 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 661 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
618 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 662 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
619 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 663 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
620 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 664 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
621 P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 665 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
622 666
623 P4_MAKE_EVENT_ATTR(P4_SSE_INPUT_ASSIST, ALL, 15), 667 P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15),
624 668
625 P4_MAKE_EVENT_ATTR(P4_PACKED_SP_UOP, ALL, 15), 669 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15),
626 670
627 P4_MAKE_EVENT_ATTR(P4_PACKED_DP_UOP, ALL, 15), 671 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15),
628 672
629 P4_MAKE_EVENT_ATTR(P4_SCALAR_SP_UOP, ALL, 15), 673 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15),
630 674
631 P4_MAKE_EVENT_ATTR(P4_SCALAR_DP_UOP, ALL, 15), 675 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15),
632 676
633 P4_MAKE_EVENT_ATTR(P4_64BIT_MMX_UOP, ALL, 15), 677 P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15),
634 678
635 P4_MAKE_EVENT_ATTR(P4_128BIT_MMX_UOP, ALL, 15), 679 P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15),
636 680
637 P4_MAKE_EVENT_ATTR(P4_X87_FP_UOP, ALL, 15), 681 P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15),
638 682
639 P4_MAKE_EVENT_ATTR(P4_TC_MISC, FLUSH, 4), 683 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4),
640 684
641 P4_MAKE_EVENT_ATTR(P4_GLOBAL_POWER_EVENTS, RUNNING, 0), 685 P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0),
642 686
643 P4_MAKE_EVENT_ATTR(P4_TC_MS_XFER, CISC, 0), 687 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0),
644 688
645 P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 689 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
646 P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 690 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
647 P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_ROM, 2), 691 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2),
648 692
649 P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 693 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
650 P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 694 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
651 P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 695 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
652 P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 696 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
653 697
654 P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 698 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
655 P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CALL, 2), 699 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2),
656 P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, RETURN, 3), 700 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3),
657 P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, INDIRECT, 4), 701 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4),
658 702
659 P4_MAKE_EVENT_ATTR(P4_RESOURCE_STALL, SBFULL, 5), 703 P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5),
660 704
661 P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_EVICTS, 0), 705 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0),
662 P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_FULL_EVICTS, 1), 706 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1),
663 707
664 P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, NBOGUS, 0), 708 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0),
665 P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, BOGUS, 1), 709 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1),
666 710
667 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS0, 0), 711 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0),
668 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS1, 1), 712 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1),
669 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS2, 2), 713 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2),
670 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS3, 3), 714 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3),
671 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS0, 4), 715 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4),
672 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS1, 5), 716 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5),
673 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS2, 6), 717 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6),
674 P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS3, 7), 718 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7),
675 719
676 P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS, 0), 720 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0),
677 P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, BOGUS, 1), 721 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1),
678 722
679 P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSNTAG, 0), 723 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0),
680 P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSTAG, 1), 724 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1),
681 P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSNTAG, 2), 725 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2),
682 P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSTAG, 3), 726 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3),
683 727
684 P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, NBOGUS, 0), 728 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0),
685 P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, BOGUS, 1), 729 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1),
686 730
687 P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGLOADS, 1), 731 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1),
688 P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGSTORES, 2), 732 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2),
689 733
690 P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNP, 0), 734 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0),
691 P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNM, 1), 735 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1),
692 P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTP, 2), 736 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2),
693 P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTM, 3), 737 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3),
694 738
695 P4_MAKE_EVENT_ATTR(P4_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 739 P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
696 740
697 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSU, 0), 741 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0),
698 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSO, 1), 742 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1),
699 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAO, 2), 743 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2),
700 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAU, 3), 744 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3),
701 P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, PREA, 4), 745 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4),
702 746
703 P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, CLEAR, 0), 747 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0),
704 P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, MOCLEAR, 1), 748 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1),
705 P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, SMCLEAR, 2), 749 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2),
706 750
707 P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, NBOGUS, 0), 751 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0),
708 P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, BOGUS, 1), 752 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1),
709}; 753};
710 754
711enum { 755/* P4 PEBS: stale for a while */
712 KEY_P4_L1D_OP_READ_RESULT_MISS = PERF_COUNT_HW_MAX, 756#define P4_PEBS_METRIC_MASK 0x00001fffU
713 KEY_P4_LL_OP_READ_RESULT_MISS, 757#define P4_PEBS_UOB_TAG 0x01000000U
714 KEY_P4_DTLB_OP_READ_RESULT_MISS, 758#define P4_PEBS_ENABLE 0x02000000U
715 KEY_P4_DTLB_OP_WRITE_RESULT_MISS, 759
716 KEY_P4_ITLB_OP_READ_RESULT_ACCESS, 760/* Replay metrics for MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT */
717 KEY_P4_ITLB_OP_READ_RESULT_MISS, 761#define P4_PEBS__1stl_cache_load_miss_retired 0x3000001
718 KEY_P4_UOP_TYPE, 762#define P4_PEBS__2ndl_cache_load_miss_retired 0x3000002
763#define P4_PEBS__dtlb_load_miss_retired 0x3000004
764#define P4_PEBS__dtlb_store_miss_retired 0x3000004
765#define P4_PEBS__dtlb_all_miss_retired 0x3000004
766#define P4_PEBS__tagged_mispred_branch 0x3018000
767#define P4_PEBS__mob_load_replay_retired 0x3000200
768#define P4_PEBS__split_load_retired 0x3000400
769#define P4_PEBS__split_store_retired 0x3000400
770
771#define P4_VERT__1stl_cache_load_miss_retired 0x0000001
772#define P4_VERT__2ndl_cache_load_miss_retired 0x0000001
773#define P4_VERT__dtlb_load_miss_retired 0x0000001
774#define P4_VERT__dtlb_store_miss_retired 0x0000002
775#define P4_VERT__dtlb_all_miss_retired 0x0000003
776#define P4_VERT__tagged_mispred_branch 0x0000010
777#define P4_VERT__mob_load_replay_retired 0x0000001
778#define P4_VERT__split_load_retired 0x0000001
779#define P4_VERT__split_store_retired 0x0000002
780
781enum P4_CACHE_EVENTS {
782 P4_CACHE__NONE,
783
784 P4_CACHE__1stl_cache_load_miss_retired,
785 P4_CACHE__2ndl_cache_load_miss_retired,
786 P4_CACHE__dtlb_load_miss_retired,
787 P4_CACHE__dtlb_store_miss_retired,
788 P4_CACHE__itlb_reference_hit,
789 P4_CACHE__itlb_reference_miss,
790
791 P4_CACHE__MAX
719}; 792};
720 793
721#endif /* PERF_EVENT_P4_H */ 794#endif /* PERF_EVENT_P4_H */
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index b8a811ab7609..f8fe069f14e2 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -11,35 +11,281 @@
11 11
12#include <asm/perf_event_p4.h> 12#include <asm/perf_event_p4.h>
13 13
14#define P4_CNTR_LIMIT 3
14/* 15/*
15 * array indices: 0,1 - HT threads, used with HT enabled cpu 16 * array indices: 0,1 - HT threads, used with HT enabled cpu
16 */ 17 */
17struct p4_event_template { 18struct p4_event_bind {
18 u32 opcode; /* ESCR event + CCCR selector */ 19 unsigned int opcode; /* Event code and ESCR selector */
19 u64 config; /* packed predefined bits */ 20 unsigned int escr_msr[2]; /* ESCR MSR for this event */
20 int dep; /* upstream dependency event index */ 21 unsigned char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on abscence */
21 int key; /* index into p4_templates */
22 u64 msr; /*
23 * the high 32 bits set into MSR_IA32_PEBS_ENABLE and
24 * the low 32 bits set into MSR_P4_PEBS_MATRIX_VERT
25 * for cache events
26 */
27 unsigned int emask; /* ESCR EventMask */
28 unsigned int escr_msr[2]; /* ESCR MSR for this event */
29 unsigned int cntr[2]; /* counter index (offset) */
30}; 22};
31 23
32struct p4_pmu_res { 24struct p4_cache_event_bind {
33 /* maps hw_conf::idx into template for ESCR sake */ 25 unsigned int metric_pebs;
34 struct p4_event_template *tpl[ARCH_P4_MAX_CCCR]; 26 unsigned int metric_vert;
35}; 27};
36 28
37static DEFINE_PER_CPU(struct p4_pmu_res, p4_pmu_config); 29#define P4_GEN_CACHE_EVENT_BIND(name) \
30 [P4_CACHE__##name] = { \
31 .metric_pebs = P4_PEBS__##name, \
32 .metric_vert = P4_VERT__##name, \
33 }
34
35static struct p4_cache_event_bind p4_cache_event_bind_map[] = {
36 P4_GEN_CACHE_EVENT_BIND(1stl_cache_load_miss_retired),
37 P4_GEN_CACHE_EVENT_BIND(2ndl_cache_load_miss_retired),
38 P4_GEN_CACHE_EVENT_BIND(dtlb_load_miss_retired),
39 P4_GEN_CACHE_EVENT_BIND(dtlb_store_miss_retired),
40};
41
42/*
43 * Note that we don't use CCCR1 here, there is an
44 * exception for P4_BSQ_ALLOCATION but we just have
45 * no workaround
46 *
47 * consider this binding as resources which particular
48 * event may borrow, it doesn't contain EventMask,
49 * Tags and friends -- they are left to a caller
50 */
51static struct p4_event_bind p4_event_bind_map[] = {
52 [P4_EVENT_TC_DELIVER_MODE] = {
53 .opcode = P4_OPCODE(P4_EVENT_TC_DELIVER_MODE),
54 .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
55 .cntr = { {4, 5, -1}, {6, 7, -1} },
56 },
57 [P4_EVENT_BPU_FETCH_REQUEST] = {
58 .opcode = P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST),
59 .escr_msr = { MSR_P4_BPU_ESCR0, MSR_P4_BPU_ESCR1 },
60 .cntr = { {0, -1, -1}, {2, -1, -1} },
61 },
62 [P4_EVENT_ITLB_REFERENCE] = {
63 .opcode = P4_OPCODE(P4_EVENT_ITLB_REFERENCE),
64 .escr_msr = { MSR_P4_ITLB_ESCR0, MSR_P4_ITLB_ESCR1 },
65 .cntr = { {0, -1, -1}, {2, -1, -1} },
66 },
67 [P4_EVENT_MEMORY_CANCEL] = {
68 .opcode = P4_OPCODE(P4_EVENT_MEMORY_CANCEL),
69 .escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
70 .cntr = { {8, 9, -1}, {10, 11, -1} },
71 },
72 [P4_EVENT_MEMORY_COMPLETE] = {
73 .opcode = P4_OPCODE(P4_EVENT_MEMORY_COMPLETE),
74 .escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
75 .cntr = { {8, 9, -1}, {10, 11, -1} },
76 },
77 [P4_EVENT_LOAD_PORT_REPLAY] = {
78 .opcode = P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY),
79 .escr_msr = { MSR_P4_SAAT_ESCR0, MSR_P4_SAAT_ESCR1 },
80 .cntr = { {8, 9, -1}, {10, 11, -1} },
81 },
82 [P4_EVENT_STORE_PORT_REPLAY] = {
83 .opcode = P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY),
84 .escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
85 .cntr = { {8, 9, -1}, {10, 11, -1} },
86 },
87 [P4_EVENT_MOB_LOAD_REPLAY] = {
88 .opcode = P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY),
89 .escr_msr = { MSR_P4_MOB_ESCR0, MSR_P4_MOB_ESCR1 },
90 .cntr = { {0, -1, -1}, {2, -1, -1} },
91 },
92 [P4_EVENT_PAGE_WALK_TYPE] = {
93 .opcode = P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE),
94 .escr_msr = { MSR_P4_PMH_ESCR0, MSR_P4_PMH_ESCR1 },
95 .cntr = { {0, -1, -1}, {2, -1, -1} },
96 },
97 [P4_EVENT_BSQ_CACHE_REFERENCE] = {
98 .opcode = P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE),
99 .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 },
100 .cntr = { {0, -1, -1}, {2, -1, -1} },
101 },
102 [P4_EVENT_IOQ_ALLOCATION] = {
103 .opcode = P4_OPCODE(P4_EVENT_IOQ_ALLOCATION),
104 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
105 .cntr = { {0, -1, -1}, {2, -1, -1} },
106 },
107 [P4_EVENT_IOQ_ACTIVE_ENTRIES] = { /* shared ESCR */
108 .opcode = P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES),
109 .escr_msr = { MSR_P4_FSB_ESCR1, MSR_P4_FSB_ESCR1 },
110 .cntr = { {2, -1, -1}, {3, -1, -1} },
111 },
112 [P4_EVENT_FSB_DATA_ACTIVITY] = {
113 .opcode = P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY),
114 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
115 .cntr = { {0, -1, -1}, {2, -1, -1} },
116 },
117 [P4_EVENT_BSQ_ALLOCATION] = { /* shared ESCR, broken CCCR1 */
118 .opcode = P4_OPCODE(P4_EVENT_BSQ_ALLOCATION),
119 .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR0 },
120 .cntr = { {0, -1, -1}, {1, -1, -1} },
121 },
122 [P4_EVENT_BSQ_ACTIVE_ENTRIES] = { /* shared ESCR */
123 .opcode = P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES),
124 .escr_msr = { MSR_P4_BSU_ESCR1 , MSR_P4_BSU_ESCR1 },
125 .cntr = { {2, -1, -1}, {3, -1, -1} },
126 },
127 [P4_EVENT_SSE_INPUT_ASSIST] = {
128 .opcode = P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST),
129 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
130 .cntr = { {8, 9, -1}, {10, 11, -1} },
131 },
132 [P4_EVENT_PACKED_SP_UOP] = {
133 .opcode = P4_OPCODE(P4_EVENT_PACKED_SP_UOP),
134 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
135 .cntr = { {8, 9, -1}, {10, 11, -1} },
136 },
137 [P4_EVENT_PACKED_DP_UOP] = {
138 .opcode = P4_OPCODE(P4_EVENT_PACKED_DP_UOP),
139 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
140 .cntr = { {8, 9, -1}, {10, 11, -1} },
141 },
142 [P4_EVENT_SCALAR_SP_UOP] = {
143 .opcode = P4_OPCODE(P4_EVENT_SCALAR_SP_UOP),
144 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
145 .cntr = { {8, 9, -1}, {10, 11, -1} },
146 },
147 [P4_EVENT_SCALAR_DP_UOP] = {
148 .opcode = P4_OPCODE(P4_EVENT_SCALAR_DP_UOP),
149 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
150 .cntr = { {8, 9, -1}, {10, 11, -1} },
151 },
152 [P4_EVENT_64BIT_MMX_UOP] = {
153 .opcode = P4_OPCODE(P4_EVENT_64BIT_MMX_UOP),
154 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
155 .cntr = { {8, 9, -1}, {10, 11, -1} },
156 },
157 [P4_EVENT_128BIT_MMX_UOP] = {
158 .opcode = P4_OPCODE(P4_EVENT_128BIT_MMX_UOP),
159 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
160 .cntr = { {8, 9, -1}, {10, 11, -1} },
161 },
162 [P4_EVENT_X87_FP_UOP] = {
163 .opcode = P4_OPCODE(P4_EVENT_X87_FP_UOP),
164 .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
165 .cntr = { {8, 9, -1}, {10, 11, -1} },
166 },
167 [P4_EVENT_TC_MISC] = {
168 .opcode = P4_OPCODE(P4_EVENT_TC_MISC),
169 .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
170 .cntr = { {4, 5, -1}, {6, 7, -1} },
171 },
172 [P4_EVENT_GLOBAL_POWER_EVENTS] = {
173 .opcode = P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS),
174 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
175 .cntr = { {0, -1, -1}, {2, -1, -1} },
176 },
177 [P4_EVENT_TC_MS_XFER] = {
178 .opcode = P4_OPCODE(P4_EVENT_TC_MS_XFER),
179 .escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
180 .cntr = { {4, 5, -1}, {6, 7, -1} },
181 },
182 [P4_EVENT_UOP_QUEUE_WRITES] = {
183 .opcode = P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES),
184 .escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
185 .cntr = { {4, 5, -1}, {6, 7, -1} },
186 },
187 [P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE] = {
188 .opcode = P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE),
189 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR0 },
190 .cntr = { {4, 5, -1}, {6, 7, -1} },
191 },
192 [P4_EVENT_RETIRED_BRANCH_TYPE] = {
193 .opcode = P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE),
194 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
195 .cntr = { {4, 5, -1}, {6, 7, -1} },
196 },
197 [P4_EVENT_RESOURCE_STALL] = {
198 .opcode = P4_OPCODE(P4_EVENT_RESOURCE_STALL),
199 .escr_msr = { MSR_P4_ALF_ESCR0, MSR_P4_ALF_ESCR1 },
200 .cntr = { {12, 13, 16}, {14, 15, 17} },
201 },
202 [P4_EVENT_WC_BUFFER] = {
203 .opcode = P4_OPCODE(P4_EVENT_WC_BUFFER),
204 .escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
205 .cntr = { {8, 9, -1}, {10, 11, -1} },
206 },
207 [P4_EVENT_B2B_CYCLES] = {
208 .opcode = P4_OPCODE(P4_EVENT_B2B_CYCLES),
209 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
210 .cntr = { {0, -1, -1}, {2, -1, -1} },
211 },
212 [P4_EVENT_BNR] = {
213 .opcode = P4_OPCODE(P4_EVENT_BNR),
214 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
215 .cntr = { {0, -1, -1}, {2, -1, -1} },
216 },
217 [P4_EVENT_SNOOP] = {
218 .opcode = P4_OPCODE(P4_EVENT_SNOOP),
219 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
220 .cntr = { {0, -1, -1}, {2, -1, -1} },
221 },
222 [P4_EVENT_RESPONSE] = {
223 .opcode = P4_OPCODE(P4_EVENT_RESPONSE),
224 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
225 .cntr = { {0, -1, -1}, {2, -1, -1} },
226 },
227 [P4_EVENT_FRONT_END_EVENT] = {
228 .opcode = P4_OPCODE(P4_EVENT_FRONT_END_EVENT),
229 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
230 .cntr = { {12, 13, 16}, {14, 15, 17} },
231 },
232 [P4_EVENT_EXECUTION_EVENT] = {
233 .opcode = P4_OPCODE(P4_EVENT_EXECUTION_EVENT),
234 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
235 .cntr = { {12, 13, 16}, {14, 15, 17} },
236 },
237 [P4_EVENT_REPLAY_EVENT] = {
238 .opcode = P4_OPCODE(P4_EVENT_REPLAY_EVENT),
239 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
240 .cntr = { {12, 13, 16}, {14, 15, 17} },
241 },
242 [P4_EVENT_INSTR_RETIRED] = {
243 .opcode = P4_OPCODE(P4_EVENT_INSTR_RETIRED),
244 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
245 .cntr = { {12, 13, 16}, {14, 15, 17} },
246 },
247 [P4_EVENT_UOPS_RETIRED] = {
248 .opcode = P4_OPCODE(P4_EVENT_UOPS_RETIRED),
249 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
250 .cntr = { {12, 13, 16}, {14, 15, 17} },
251 },
252 [P4_EVENT_UOP_TYPE] = {
253 .opcode = P4_OPCODE(P4_EVENT_UOP_TYPE),
254 .escr_msr = { MSR_P4_RAT_ESCR0, MSR_P4_RAT_ESCR1 },
255 .cntr = { {12, 13, 16}, {14, 15, 17} },
256 },
257 [P4_EVENT_BRANCH_RETIRED] = {
258 .opcode = P4_OPCODE(P4_EVENT_BRANCH_RETIRED),
259 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
260 .cntr = { {12, 13, 16}, {14, 15, 17} },
261 },
262 [P4_EVENT_MISPRED_BRANCH_RETIRED] = {
263 .opcode = P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED),
264 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
265 .cntr = { {12, 13, 16}, {14, 15, 17} },
266 },
267 [P4_EVENT_X87_ASSIST] = {
268 .opcode = P4_OPCODE(P4_EVENT_X87_ASSIST),
269 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
270 .cntr = { {12, 13, 16}, {14, 15, 17} },
271 },
272 [P4_EVENT_MACHINE_CLEAR] = {
273 .opcode = P4_OPCODE(P4_EVENT_MACHINE_CLEAR),
274 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
275 .cntr = { {12, 13, 16}, {14, 15, 17} },
276 },
277 [P4_EVENT_INSTR_COMPLETED] = {
278 .opcode = P4_OPCODE(P4_EVENT_INSTR_COMPLETED),
279 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
280 .cntr = { {12, 13, 16}, {14, 15, 17} },
281 },
282};
38 283
39#define P4_CACHE_EVENT_CONFIG(event, bit) \ 284#define P4_GEN_CACHE_EVENT(event, bit, cache_event) \
40 p4_config_pack_escr(P4_EVENT_UNPACK_EVENT(event) << P4_EVNTSEL_EVENT_SHIFT) | \ 285 p4_config_pack_escr(P4_ESCR_EVENT(event) | \
41 p4_config_pack_escr((event##_##bit) << P4_EVNTSEL_EVENTMASK_SHIFT) | \ 286 P4_ESCR_EMASK_BIT(event, bit)) | \
42 p4_config_pack_cccr(P4_EVENT_UNPACK_SELECTOR(event) << P4_CCCR_ESCR_SELECT_SHIFT) 287 p4_config_pack_cccr(cache_event | \
288 P4_CCCR_ESEL(P4_OPCODE_ESEL(P4_OPCODE(event))))
43 289
44static __initconst u64 p4_hw_cache_event_ids 290static __initconst u64 p4_hw_cache_event_ids
45 [PERF_COUNT_HW_CACHE_MAX] 291 [PERF_COUNT_HW_CACHE_MAX]
@@ -49,42 +295,35 @@ static __initconst u64 p4_hw_cache_event_ids
49 [ C(L1D ) ] = { 295 [ C(L1D ) ] = {
50 [ C(OP_READ) ] = { 296 [ C(OP_READ) ] = {
51 [ C(RESULT_ACCESS) ] = 0x0, 297 [ C(RESULT_ACCESS) ] = 0x0,
52 /* 1stL_cache_load_miss_retired */ 298 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
53 [ C(RESULT_MISS) ] = P4_CACHE_EVENT_CONFIG(P4_REPLAY_EVENT, NBOGUS) 299 P4_CACHE__1stl_cache_load_miss_retired),
54 | KEY_P4_L1D_OP_READ_RESULT_MISS,
55 }, 300 },
56 }, 301 },
57 [ C(LL ) ] = { 302 [ C(LL ) ] = {
58 [ C(OP_READ) ] = { 303 [ C(OP_READ) ] = {
59 [ C(RESULT_ACCESS) ] = 0x0, 304 [ C(RESULT_ACCESS) ] = 0x0,
60 /* 2ndL_cache_load_miss_retired */ 305 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
61 [ C(RESULT_MISS) ] = P4_CACHE_EVENT_CONFIG(P4_REPLAY_EVENT, NBOGUS) 306 P4_CACHE__2ndl_cache_load_miss_retired),
62 | KEY_P4_LL_OP_READ_RESULT_MISS,
63 }, 307 },
64 }, 308},
65 [ C(DTLB) ] = { 309 [ C(DTLB) ] = {
66 [ C(OP_READ) ] = { 310 [ C(OP_READ) ] = {
67 [ C(RESULT_ACCESS) ] = 0x0, 311 [ C(RESULT_ACCESS) ] = 0x0,
68 /* DTLB_load_miss_retired */ 312 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
69 [ C(RESULT_MISS) ] = P4_CACHE_EVENT_CONFIG(P4_REPLAY_EVENT, NBOGUS) 313 P4_CACHE__dtlb_load_miss_retired),
70 | KEY_P4_DTLB_OP_READ_RESULT_MISS,
71 }, 314 },
72 [ C(OP_WRITE) ] = { 315 [ C(OP_WRITE) ] = {
73 [ C(RESULT_ACCESS) ] = 0x0, 316 [ C(RESULT_ACCESS) ] = 0x0,
74 /* DTLB_store_miss_retired */ 317 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
75 [ C(RESULT_MISS) ] = P4_CACHE_EVENT_CONFIG(P4_REPLAY_EVENT, NBOGUS) 318 P4_CACHE__dtlb_store_miss_retired),
76 | KEY_P4_DTLB_OP_WRITE_RESULT_MISS,
77 }, 319 },
78 }, 320 },
79 [ C(ITLB) ] = { 321 [ C(ITLB) ] = {
80 [ C(OP_READ) ] = { 322 [ C(OP_READ) ] = {
81 /* ITLB_reference.HIT */ 323 [ C(RESULT_ACCESS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, HIT,
82 [ C(RESULT_ACCESS) ] = P4_CACHE_EVENT_CONFIG(P4_ITLB_REFERENCE, HIT) 324 P4_CACHE__itlb_reference_hit),
83 | KEY_P4_ITLB_OP_READ_RESULT_ACCESS, 325 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS,
84 326 P4_CACHE__itlb_reference_miss),
85 /* ITLB_reference.MISS */
86 [ C(RESULT_MISS) ] = P4_CACHE_EVENT_CONFIG(P4_ITLB_REFERENCE, MISS)
87 | KEY_P4_ITLB_OP_READ_RESULT_MISS,
88 }, 327 },
89 [ C(OP_WRITE) ] = { 328 [ C(OP_WRITE) ] = {
90 [ C(RESULT_ACCESS) ] = -1, 329 [ C(RESULT_ACCESS) ] = -1,
@@ -97,220 +336,90 @@ static __initconst u64 p4_hw_cache_event_ids
97 }, 336 },
98}; 337};
99 338
100/* 339static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
101 * WARN: CCCR1 doesn't have a working enable bit so try to not 340 /* non-halted CPU clocks */
102 * use it if possible 341 [PERF_COUNT_HW_CPU_CYCLES] =
103 * 342 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS) |
104 * Also as only we start to support raw events we will need to 343 P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)),
105 * append _all_ P4_EVENT_PACK'ed events here 344
106 */ 345 /*
107struct p4_event_template p4_templates[] = { 346 * retired instructions
108 [0] = { 347 * in a sake of simplicity we don't use the FSB tagging
109 .opcode = P4_GLOBAL_POWER_EVENTS, 348 */
110 .config = 0, 349 [PERF_COUNT_HW_INSTRUCTIONS] =
111 .dep = -1, 350 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_INSTR_RETIRED) |
112 .key = 0, 351 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG) |
113 .emask = 352 P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSNTAG)),
114 P4_EVENT_ATTR(P4_GLOBAL_POWER_EVENTS, RUNNING), 353
115 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 }, 354 /* cache hits */
116 .cntr = { 0, 2 }, 355 [PERF_COUNT_HW_CACHE_REFERENCES] =
117 }, 356 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
118 [1] = { 357 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
119 .opcode = P4_INSTR_RETIRED, 358 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
120 .config = 0, 359 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
121 .dep = -1, /* needs front-end tagging */ 360 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
122 .key = 1, 361 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
123 .emask = 362 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM)),
124 P4_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSNTAG) | 363
125 P4_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSNTAG), 364 /* cache misses */
126 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 }, 365 [PERF_COUNT_HW_CACHE_MISSES] =
127 .cntr = { 12, 14 }, 366 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
128 }, 367 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
129 [2] = { 368 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
130 .opcode = P4_BSQ_CACHE_REFERENCE, 369 P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS)),
131 .config = 0, 370
132 .dep = -1, 371 /* branch instructions retired */
133 .key = 2, 372 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =
134 .emask = 373 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_RETIRED_BRANCH_TYPE) |
135 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) | 374 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL) |
136 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) | 375 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CALL) |
137 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) | 376 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN) |
138 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) | 377 P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT)),
139 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) | 378
140 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITM), 379 /* mispredicted branches retired */
141 .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 }, 380 [PERF_COUNT_HW_BRANCH_MISSES] =
142 .cntr = { 0, 2 }, 381 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_MISPRED_BRANCH_RETIRED) |
143 }, 382 P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS)),
144 [3] = { 383
145 .opcode = P4_BSQ_CACHE_REFERENCE, 384 /* bus ready clocks (cpu is driving #DRDY_DRV\#DRDY_OWN): */
146 .config = 0, 385 [PERF_COUNT_HW_BUS_CYCLES] =
147 .dep = -1, 386 p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_FSB_DATA_ACTIVITY) |
148 .key = 3, 387 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV) |
149 .emask = 388 P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN)) |
150 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) | 389 p4_config_pack_cccr(P4_CCCR_EDGE | P4_CCCR_COMPARE),
151 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
152 P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, WR_2ndL_MISS),
153 .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 },
154 .cntr = { 0, 3 },
155 },
156 [4] = {
157 .opcode = P4_RETIRED_BRANCH_TYPE,
158 .config = 0,
159 .dep = -1,
160 .key = 4,
161 .emask =
162 P4_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CONDITIONAL) |
163 P4_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CALL) |
164 P4_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, RETURN) |
165 P4_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, INDIRECT),
166 .escr_msr = { MSR_P4_TBPU_ESCR0, MSR_P4_TBPU_ESCR1 },
167 .cntr = { 4, 6 },
168 },
169 [5] = {
170 .opcode = P4_MISPRED_BRANCH_RETIRED,
171 .config = 0,
172 .dep = -1,
173 .key = 5,
174 .emask =
175 P4_EVENT_ATTR(P4_MISPRED_BRANCH_RETIRED, NBOGUS),
176 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
177 .cntr = { 12, 14 },
178 },
179 [6] = {
180 .opcode = P4_FSB_DATA_ACTIVITY,
181 .config = p4_config_pack_cccr(P4_CCCR_EDGE | P4_CCCR_COMPARE),
182 .dep = -1,
183 .key = 6,
184 .emask =
185 P4_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_DRV) |
186 P4_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OWN),
187 .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
188 .cntr = { 0, 2 },
189 },
190 [KEY_P4_L1D_OP_READ_RESULT_MISS] = {
191 .opcode = P4_REPLAY_EVENT,
192 .config = 0,
193 .dep = -1,
194 .msr = (u64)(1 << 0 | 1 << 24) << 32 | (1 << 0),
195 .key = KEY_P4_L1D_OP_READ_RESULT_MISS,
196 .emask =
197 P4_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS),
198 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR2 },
199 .cntr = { 16, 17 },
200 },
201 [KEY_P4_LL_OP_READ_RESULT_MISS] = {
202 .opcode = P4_REPLAY_EVENT,
203 .config = 0,
204 .dep = -1,
205 .msr = (u64)(1 << 1 | 1 << 24) << 32 | (1 << 0),
206 .key = KEY_P4_LL_OP_READ_RESULT_MISS,
207 .emask =
208 P4_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS),
209 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR2 },
210 .cntr = { 16, 17 },
211 },
212 [KEY_P4_DTLB_OP_READ_RESULT_MISS] = {
213 .opcode = P4_REPLAY_EVENT,
214 .config = 0,
215 .dep = -1,
216 .msr = (u64)(1 << 2 | 1 << 24) << 32 | (1 << 0),
217 .key = KEY_P4_DTLB_OP_READ_RESULT_MISS,
218 .emask =
219 P4_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS),
220 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR2 },
221 .cntr = { 16, 17 },
222 },
223 [KEY_P4_DTLB_OP_WRITE_RESULT_MISS] = {
224 .opcode = P4_REPLAY_EVENT,
225 .config = 0,
226 .dep = -1,
227 .msr = (u64)(1 << 2 | 1 << 24) << 32 | (1 << 1),
228 .key = KEY_P4_DTLB_OP_WRITE_RESULT_MISS,
229 .emask =
230 P4_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS),
231 .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR2 },
232 .cntr = { 16, 17 },
233 },
234 [KEY_P4_ITLB_OP_READ_RESULT_ACCESS] = {
235 .opcode = P4_ITLB_REFERENCE,
236 .config = 0,
237 .dep = -1,
238 .msr = 0,
239 .key = KEY_P4_ITLB_OP_READ_RESULT_ACCESS,
240 .emask =
241 P4_EVENT_ATTR(P4_ITLB_REFERENCE, HIT),
242 .escr_msr = { MSR_P4_ITLB_ESCR0, MSR_P4_ITLB_ESCR1 },
243 .cntr = { 0, 2 },
244 },
245 [KEY_P4_ITLB_OP_READ_RESULT_MISS] = {
246 .opcode = P4_ITLB_REFERENCE,
247 .config = 0,
248 .dep = -1,
249 .msr = 0,
250 .key = KEY_P4_ITLB_OP_READ_RESULT_MISS,
251 .emask =
252 P4_EVENT_ATTR(P4_ITLB_REFERENCE, MISS),
253 .escr_msr = { MSR_P4_ITLB_ESCR0, MSR_P4_ITLB_ESCR1 },
254 .cntr = { 0, 2 },
255 },
256 [KEY_P4_UOP_TYPE] = {
257 .opcode = P4_UOP_TYPE,
258 .config = 0,
259 .dep = -1,
260 .key = KEY_P4_UOP_TYPE,
261 .emask =
262 P4_EVENT_ATTR(P4_UOP_TYPE, TAGLOADS) |
263 P4_EVENT_ATTR(P4_UOP_TYPE, TAGSTORES),
264 .escr_msr = { MSR_P4_RAT_ESCR0, MSR_P4_RAT_ESCR1 },
265 .cntr = { 16, 17 },
266 },
267}; 390};
268 391
392static struct p4_event_bind *p4_config_get_bind(u64 config)
393{
394 unsigned int evnt = p4_config_unpack_event(config);
395 struct p4_event_bind *bind = NULL;
396
397 if (evnt < ARRAY_SIZE(p4_event_bind_map))
398 bind = &p4_event_bind_map[evnt];
399
400 return bind;
401}
402
269static u64 p4_pmu_event_map(int hw_event) 403static u64 p4_pmu_event_map(int hw_event)
270{ 404{
271 struct p4_event_template *tpl; 405 struct p4_event_bind *bind;
406 unsigned int esel;
272 u64 config; 407 u64 config;
273 408
274 if (hw_event > ARRAY_SIZE(p4_templates)) { 409 if (hw_event > ARRAY_SIZE(p4_general_events)) {
275 printk_once(KERN_ERR "PMU: Incorrect event index\n"); 410 printk_once(KERN_ERR "P4 PMU: Bad index: %i\n", hw_event);
276 return 0; 411 return 0;
277 } 412 }
278 tpl = &p4_templates[hw_event];
279 413
280 /* 414 config = p4_general_events[hw_event];
281 * fill config up according to 415 bind = p4_config_get_bind(config);
282 * a predefined event template 416 esel = P4_OPCODE_ESEL(bind->opcode);
283 */ 417 config |= p4_config_pack_cccr(P4_CCCR_ESEL(esel));
284 config = tpl->config;
285 config |= p4_config_pack_escr(P4_EVENT_UNPACK_EVENT(tpl->opcode) << P4_EVNTSEL_EVENT_SHIFT);
286 config |= p4_config_pack_escr(tpl->emask << P4_EVNTSEL_EVENTMASK_SHIFT);
287 config |= p4_config_pack_cccr(P4_EVENT_UNPACK_SELECTOR(tpl->opcode) << P4_CCCR_ESCR_SELECT_SHIFT);
288 config |= p4_config_pack_cccr(hw_event & P4_CCCR_RESERVED);
289 418
290 return config; 419 return config;
291} 420}
292 421
293/* 422/*
294 * Note that we still have 5 events (from global events SDM list)
295 * intersected in opcode+emask bits so we will need another
296 * scheme there do distinguish templates.
297 */
298static inline int p4_pmu_emask_match(unsigned int dst, unsigned int src)
299{
300 return dst & src;
301}
302
303static struct p4_event_template *p4_pmu_template_lookup(u64 config)
304{
305 int key = p4_config_unpack_key(config);
306
307 if (key < ARRAY_SIZE(p4_templates))
308 return &p4_templates[key];
309 else
310 return NULL;
311}
312
313/*
314 * We don't control raw events so it's up to the caller 423 * We don't control raw events so it's up to the caller
315 * to pass sane values (and we don't count the thread number 424 * to pass sane values (and we don't count the thread number
316 * on HT machine but allow HT-compatible specifics to be 425 * on HT machine but allow HT-compatible specifics to be
@@ -319,13 +428,14 @@ static struct p4_event_template *p4_pmu_template_lookup(u64 config)
319static u64 p4_pmu_raw_event(u64 hw_event) 428static u64 p4_pmu_raw_event(u64 hw_event)
320{ 429{
321 return hw_event & 430 return hw_event &
322 (p4_config_pack_escr(P4_EVNTSEL_MASK_HT) | 431 (p4_config_pack_escr(P4_ESCR_MASK_HT) |
323 p4_config_pack_cccr(P4_CCCR_MASK_HT)); 432 p4_config_pack_cccr(P4_CCCR_MASK_HT));
324} 433}
325 434
326static int p4_hw_config(struct perf_event_attr *attr, struct hw_perf_event *hwc) 435static int p4_hw_config(struct perf_event_attr *attr, struct hw_perf_event *hwc)
327{ 436{
328 int cpu = raw_smp_processor_id(); 437 int cpu = raw_smp_processor_id();
438 u32 escr, cccr;
329 439
330 /* 440 /*
331 * the reason we use cpu that early is that: if we get scheduled 441 * the reason we use cpu that early is that: if we get scheduled
@@ -333,13 +443,10 @@ static int p4_hw_config(struct perf_event_attr *attr, struct hw_perf_event *hwc)
333 * specific flags in config (and will save some cpu cycles) 443 * specific flags in config (and will save some cpu cycles)
334 */ 444 */
335 445
336 /* CCCR by default */ 446 cccr = p4_default_cccr_conf(cpu);
337 hwc->config = p4_config_pack_cccr(p4_default_cccr_conf(cpu)); 447 escr = p4_default_escr_conf(cpu, attr->exclude_kernel, attr->exclude_user);
448 hwc->config = p4_config_pack_escr(escr) | p4_config_pack_cccr(cccr);
338 449
339 /* Count user and OS events unless not requested to */
340 hwc->config |= p4_config_pack_escr(p4_default_escr_conf(cpu, attr->exclude_kernel,
341 attr->exclude_user));
342 /* on HT machine we need a special bit */
343 if (p4_ht_active() && p4_ht_thread(cpu)) 450 if (p4_ht_active() && p4_ht_thread(cpu))
344 hwc->config = p4_set_ht_bit(hwc->config); 451 hwc->config = p4_set_ht_bit(hwc->config);
345 452
@@ -368,7 +475,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event)
368 */ 475 */
369 (void)checking_wrmsrl(hwc->config_base + hwc->idx, 476 (void)checking_wrmsrl(hwc->config_base + hwc->idx,
370 (u64)(p4_config_unpack_cccr(hwc->config)) & 477 (u64)(p4_config_unpack_cccr(hwc->config)) &
371 ~P4_CCCR_ENABLE & ~P4_CCCR_OVF); 478 ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
372} 479}
373 480
374static void p4_pmu_disable_all(void) 481static void p4_pmu_disable_all(void)
@@ -389,27 +496,14 @@ static void p4_pmu_enable_event(struct perf_event *event)
389 struct hw_perf_event *hwc = &event->hw; 496 struct hw_perf_event *hwc = &event->hw;
390 int thread = p4_ht_config_thread(hwc->config); 497 int thread = p4_ht_config_thread(hwc->config);
391 u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config)); 498 u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config));
392 u64 escr_base; 499 unsigned int idx = p4_config_unpack_event(hwc->config);
393 struct p4_event_template *tpl; 500 unsigned int idx_cache = p4_config_unpack_cache_event(hwc->config);
394 struct p4_pmu_res *c; 501 struct p4_event_bind *bind;
502 struct p4_cache_event_bind *bind_cache;
503 u64 escr_addr, cccr;
395 504
396 /* 505 bind = &p4_event_bind_map[idx];
397 * some preparation work from per-cpu private fields 506 escr_addr = (u64)bind->escr_msr[thread];
398 * since we need to find out which ESCR to use
399 */
400 c = &__get_cpu_var(p4_pmu_config);
401 tpl = c->tpl[hwc->idx];
402 if (!tpl) {
403 pr_crit("%s: Wrong index: %d\n", __func__, hwc->idx);
404 return;
405 }
406
407 if (tpl->msr) {
408 (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, tpl->msr >> 32);
409 (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, tpl->msr & 0xffffffff);
410 }
411
412 escr_base = (u64)tpl->escr_msr[thread];
413 507
414 /* 508 /*
415 * - we dont support cascaded counters yet 509 * - we dont support cascaded counters yet
@@ -418,9 +512,27 @@ static void p4_pmu_enable_event(struct perf_event *event)
418 WARN_ON_ONCE(p4_is_event_cascaded(hwc->config)); 512 WARN_ON_ONCE(p4_is_event_cascaded(hwc->config));
419 WARN_ON_ONCE(hwc->idx == 1); 513 WARN_ON_ONCE(hwc->idx == 1);
420 514
421 (void)checking_wrmsrl(escr_base, escr_conf); 515 /* we need a real Event value */
516 escr_conf &= ~P4_ESCR_EVENT_MASK;
517 escr_conf |= P4_ESCR_EVENT(P4_OPCODE_EVNT(bind->opcode));
518
519 cccr = p4_config_unpack_cccr(hwc->config);
520
521 /*
522 * it could be Cache event so that we need to
523 * set metrics into additional MSRs
524 */
525 BUILD_BUG_ON(P4_CACHE__MAX > P4_CCCR_CACHE_OPS_MASK);
526 if (idx_cache > P4_CACHE__NONE &&
527 idx_cache < ARRAY_SIZE(p4_cache_event_bind_map)) {
528 bind_cache = &p4_cache_event_bind_map[idx_cache];
529 (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)bind_cache->metric_pebs);
530 (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)bind_cache->metric_vert);
531 }
532
533 (void)checking_wrmsrl(escr_addr, escr_conf);
422 (void)checking_wrmsrl(hwc->config_base + hwc->idx, 534 (void)checking_wrmsrl(hwc->config_base + hwc->idx,
423 (u64)(p4_config_unpack_cccr(hwc->config)) | P4_CCCR_ENABLE); 535 (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE);
424} 536}
425 537
426static void p4_pmu_enable_all(void) 538static void p4_pmu_enable_all(void)
@@ -516,13 +628,13 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
516 if (p4_ht_thread(cpu)) { 628 if (p4_ht_thread(cpu)) {
517 cccr &= ~P4_CCCR_OVF_PMI_T0; 629 cccr &= ~P4_CCCR_OVF_PMI_T0;
518 cccr |= P4_CCCR_OVF_PMI_T1; 630 cccr |= P4_CCCR_OVF_PMI_T1;
519 if (escr & P4_EVNTSEL_T0_OS) { 631 if (escr & P4_ESCR_T0_OS) {
520 escr &= ~P4_EVNTSEL_T0_OS; 632 escr &= ~P4_ESCR_T0_OS;
521 escr |= P4_EVNTSEL_T1_OS; 633 escr |= P4_ESCR_T1_OS;
522 } 634 }
523 if (escr & P4_EVNTSEL_T0_USR) { 635 if (escr & P4_ESCR_T0_USR) {
524 escr &= ~P4_EVNTSEL_T0_USR; 636 escr &= ~P4_ESCR_T0_USR;
525 escr |= P4_EVNTSEL_T1_USR; 637 escr |= P4_ESCR_T1_USR;
526 } 638 }
527 hwc->config = p4_config_pack_escr(escr); 639 hwc->config = p4_config_pack_escr(escr);
528 hwc->config |= p4_config_pack_cccr(cccr); 640 hwc->config |= p4_config_pack_cccr(cccr);
@@ -530,13 +642,13 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
530 } else { 642 } else {
531 cccr &= ~P4_CCCR_OVF_PMI_T1; 643 cccr &= ~P4_CCCR_OVF_PMI_T1;
532 cccr |= P4_CCCR_OVF_PMI_T0; 644 cccr |= P4_CCCR_OVF_PMI_T0;
533 if (escr & P4_EVNTSEL_T1_OS) { 645 if (escr & P4_ESCR_T1_OS) {
534 escr &= ~P4_EVNTSEL_T1_OS; 646 escr &= ~P4_ESCR_T1_OS;
535 escr |= P4_EVNTSEL_T0_OS; 647 escr |= P4_ESCR_T0_OS;
536 } 648 }
537 if (escr & P4_EVNTSEL_T1_USR) { 649 if (escr & P4_ESCR_T1_USR) {
538 escr &= ~P4_EVNTSEL_T1_USR; 650 escr &= ~P4_ESCR_T1_USR;
539 escr |= P4_EVNTSEL_T0_USR; 651 escr |= P4_ESCR_T0_USR;
540 } 652 }
541 hwc->config = p4_config_pack_escr(escr); 653 hwc->config = p4_config_pack_escr(escr);
542 hwc->config |= p4_config_pack_cccr(cccr); 654 hwc->config |= p4_config_pack_cccr(cccr);
@@ -606,66 +718,56 @@ static int p4_get_escr_idx(unsigned int addr)
606 return -1; 718 return -1;
607} 719}
608 720
721static int p4_next_cntr(int thread, unsigned long *used_mask,
722 struct p4_event_bind *bind)
723{
724 int i = 0, j;
725
726 for (i = 0; i < P4_CNTR_LIMIT; i++) {
727 j = bind->cntr[thread][i++];
728 if (j == -1 || !test_bit(j, used_mask))
729 return j;
730 }
731
732 return -1;
733}
734
609static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) 735static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
610{ 736{
611 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; 737 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
612 unsigned long escr_mask[BITS_TO_LONGS(ARCH_P4_TOTAL_ESCR)]; 738 unsigned long escr_mask[BITS_TO_LONGS(ARCH_P4_TOTAL_ESCR)];
613
614 struct hw_perf_event *hwc;
615 struct p4_event_template *tpl;
616 struct p4_pmu_res *c;
617 int cpu = raw_smp_processor_id(); 739 int cpu = raw_smp_processor_id();
618 int escr_idx, thread, i, num; 740 struct hw_perf_event *hwc;
741 struct p4_event_bind *bind;
742 unsigned int i, thread, num;
743 int cntr_idx, escr_idx;
619 744
620 bitmap_zero(used_mask, X86_PMC_IDX_MAX); 745 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
621 bitmap_zero(escr_mask, ARCH_P4_TOTAL_ESCR); 746 bitmap_zero(escr_mask, ARCH_P4_TOTAL_ESCR);
622 747
623 c = &__get_cpu_var(p4_pmu_config);
624 /*
625 * Firstly find out which resource events are going
626 * to use, if ESCR+CCCR tuple is already borrowed
627 * then get out of here
628 */
629 for (i = 0, num = n; i < n; i++, num--) { 748 for (i = 0, num = n; i < n; i++, num--) {
749
630 hwc = &cpuc->event_list[i]->hw; 750 hwc = &cpuc->event_list[i]->hw;
631 tpl = p4_pmu_template_lookup(hwc->config);
632 if (!tpl)
633 goto done;
634 thread = p4_ht_thread(cpu); 751 thread = p4_ht_thread(cpu);
635 escr_idx = p4_get_escr_idx(tpl->escr_msr[thread]); 752 bind = p4_config_get_bind(hwc->config);
636 if (escr_idx == -1) 753 escr_idx = p4_get_escr_idx(bind->escr_msr[thread]);
637 goto done;
638 754
639 /* already allocated and remains on the same cpu */
640 if (hwc->idx != -1 && !p4_should_swap_ts(hwc->config, cpu)) { 755 if (hwc->idx != -1 && !p4_should_swap_ts(hwc->config, cpu)) {
756 cntr_idx = hwc->idx;
641 if (assign) 757 if (assign)
642 assign[i] = hwc->idx; 758 assign[i] = hwc->idx;
643 /* upstream dependent event */
644 if (unlikely(tpl->dep != -1))
645 printk_once(KERN_WARNING "PMU: Dep events are "
646 "not implemented yet\n");
647 goto reserve; 759 goto reserve;
648 } 760 }
649 761
650 /* it may be already borrowed */ 762 cntr_idx = p4_next_cntr(thread, used_mask, bind);
651 if (test_bit(tpl->cntr[thread], used_mask) || 763 if (cntr_idx == -1 || test_bit(escr_idx, escr_mask))
652 test_bit(escr_idx, escr_mask))
653 goto done; 764 goto done;
654 765
655 /*
656 * ESCR+CCCR+COUNTERs are available to use lets swap
657 * thread specific bits, push assigned bits
658 * back and save template into per-cpu
659 * area (which will allow us to find out the ESCR
660 * to be used at moment of "enable event via real MSR")
661 */
662 p4_pmu_swap_config_ts(hwc, cpu); 766 p4_pmu_swap_config_ts(hwc, cpu);
663 if (assign) { 767 if (assign)
664 assign[i] = tpl->cntr[thread]; 768 assign[i] = cntr_idx;
665 c->tpl[assign[i]] = tpl;
666 }
667reserve: 769reserve:
668 set_bit(tpl->cntr[thread], used_mask); 770 set_bit(cntr_idx, used_mask);
669 set_bit(escr_idx, escr_mask); 771 set_bit(escr_idx, escr_mask);
670 } 772 }
671 773
@@ -684,7 +786,7 @@ static __initconst struct x86_pmu p4_pmu = {
684 .perfctr = MSR_P4_BPU_PERFCTR0, 786 .perfctr = MSR_P4_BPU_PERFCTR0,
685 .event_map = p4_pmu_event_map, 787 .event_map = p4_pmu_event_map,
686 .raw_event = p4_pmu_raw_event, 788 .raw_event = p4_pmu_raw_event,
687 .max_events = ARRAY_SIZE(p4_templates), 789 .max_events = ARRAY_SIZE(p4_general_events),
688 .get_event_constraints = x86_get_event_constraints, 790 .get_event_constraints = x86_get_event_constraints,
689 /* 791 /*
690 * IF HT disabled we may need to use all 792 * IF HT disabled we may need to use all
@@ -716,7 +818,7 @@ static __init int p4_pmu_init(void)
716 } 818 }
717 819
718 memcpy(hw_cache_event_ids, p4_hw_cache_event_ids, 820 memcpy(hw_cache_event_ids, p4_hw_cache_event_ids,
719 sizeof(hw_cache_event_ids)); 821 sizeof(hw_cache_event_ids));
720 822
721 pr_cont("Netburst events, "); 823 pr_cont("Netburst events, ");
722 824
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 08:04:08 -0400