diff options
author | Robert Richter <robert.richter@amd.com> | 2009-05-22 13:47:38 -0400 |
---|---|---|
committer | Robert Richter <robert.richter@amd.com> | 2009-06-11 13:42:11 -0400 |
commit | d2731a4387ad6c6bca07abfe9ed41d450fb6d665 (patch) | |
tree | d3b5703a00edc9b59c0f2344dbd4cd927936cb16 | |
parent | ff9faa8b676e195476b86f03fe58db0f01bda8f3 (diff) |
x86/oprofile: remove MSR macros for AMD cpus
The macros CTRL_READ() and CTRL_WRITE() make the code hard to read and
maintain. This patch replaces them by rdmsr()/wrmsr() functions and
simplifies the code.
Signed-off-by: Robert Richter <robert.richter@amd.com>
-rw-r--r-- | arch/x86/oprofile/op_model_amd.c | 29 |
1 files changed, 12 insertions, 17 deletions
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 4b9254a67e68..c6181c265ae0 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c | |||
@@ -26,12 +26,7 @@ | |||
26 | #define NUM_COUNTERS 4 | 26 | #define NUM_COUNTERS 4 |
27 | #define NUM_CONTROLS 4 | 27 | #define NUM_CONTROLS 4 |
28 | 28 | ||
29 | #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0) | ||
30 | #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0) | ||
31 | #define CTR_OVERFLOWED(n) (!((n) & (1U<<31))) | 29 | #define CTR_OVERFLOWED(n) (!((n) & (1U<<31))) |
32 | |||
33 | #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0) | ||
34 | #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0) | ||
35 | #define CTRL_CLEAR_LO(x) (x &= (1<<21)) | 30 | #define CTRL_CLEAR_LO(x) (x &= (1<<21)) |
36 | #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0) | 31 | #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0) |
37 | #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff)) | 32 | #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff)) |
@@ -101,17 +96,17 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs) | |||
101 | for (i = 0 ; i < NUM_CONTROLS; ++i) { | 96 | for (i = 0 ; i < NUM_CONTROLS; ++i) { |
102 | if (unlikely(!CTRL_IS_RESERVED(msrs, i))) | 97 | if (unlikely(!CTRL_IS_RESERVED(msrs, i))) |
103 | continue; | 98 | continue; |
104 | CTRL_READ(low, high, msrs, i); | 99 | rdmsr(msrs->controls[i].addr, low, high); |
105 | CTRL_CLEAR_LO(low); | 100 | CTRL_CLEAR_LO(low); |
106 | CTRL_CLEAR_HI(high); | 101 | CTRL_CLEAR_HI(high); |
107 | CTRL_WRITE(low, high, msrs, i); | 102 | wrmsr(msrs->controls[i].addr, low, high); |
108 | } | 103 | } |
109 | 104 | ||
110 | /* avoid a false detection of ctr overflows in NMI handler */ | 105 | /* avoid a false detection of ctr overflows in NMI handler */ |
111 | for (i = 0; i < NUM_COUNTERS; ++i) { | 106 | for (i = 0; i < NUM_COUNTERS; ++i) { |
112 | if (unlikely(!CTR_IS_RESERVED(msrs, i))) | 107 | if (unlikely(!CTR_IS_RESERVED(msrs, i))) |
113 | continue; | 108 | continue; |
114 | CTR_WRITE(1, msrs, i); | 109 | wrmsr(msrs->counters[i].addr, -1, -1); |
115 | } | 110 | } |
116 | 111 | ||
117 | /* enable active counters */ | 112 | /* enable active counters */ |
@@ -119,9 +114,9 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs) | |||
119 | if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) { | 114 | if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) { |
120 | reset_value[i] = counter_config[i].count; | 115 | reset_value[i] = counter_config[i].count; |
121 | 116 | ||
122 | CTR_WRITE(counter_config[i].count, msrs, i); | 117 | wrmsr(msrs->counters[i].addr, -(unsigned int)counter_config[i].count, -1); |
123 | 118 | ||
124 | CTRL_READ(low, high, msrs, i); | 119 | rdmsr(msrs->controls[i].addr, low, high); |
125 | CTRL_CLEAR_LO(low); | 120 | CTRL_CLEAR_LO(low); |
126 | CTRL_CLEAR_HI(high); | 121 | CTRL_CLEAR_HI(high); |
127 | CTRL_SET_ENABLE(low); | 122 | CTRL_SET_ENABLE(low); |
@@ -133,7 +128,7 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs) | |||
133 | CTRL_SET_HOST_ONLY(high, 0); | 128 | CTRL_SET_HOST_ONLY(high, 0); |
134 | CTRL_SET_GUEST_ONLY(high, 0); | 129 | CTRL_SET_GUEST_ONLY(high, 0); |
135 | 130 | ||
136 | CTRL_WRITE(low, high, msrs, i); | 131 | wrmsr(msrs->controls[i].addr, low, high); |
137 | } else { | 132 | } else { |
138 | reset_value[i] = 0; | 133 | reset_value[i] = 0; |
139 | } | 134 | } |
@@ -267,10 +262,10 @@ static int op_amd_check_ctrs(struct pt_regs * const regs, | |||
267 | for (i = 0 ; i < NUM_COUNTERS; ++i) { | 262 | for (i = 0 ; i < NUM_COUNTERS; ++i) { |
268 | if (!reset_value[i]) | 263 | if (!reset_value[i]) |
269 | continue; | 264 | continue; |
270 | CTR_READ(low, high, msrs, i); | 265 | rdmsr(msrs->counters[i].addr, low, high); |
271 | if (CTR_OVERFLOWED(low)) { | 266 | if (CTR_OVERFLOWED(low)) { |
272 | oprofile_add_sample(regs, i); | 267 | oprofile_add_sample(regs, i); |
273 | CTR_WRITE(reset_value[i], msrs, i); | 268 | wrmsr(msrs->counters[i].addr, -(unsigned int)reset_value[i], -1); |
274 | } | 269 | } |
275 | } | 270 | } |
276 | 271 | ||
@@ -286,9 +281,9 @@ static void op_amd_start(struct op_msrs const * const msrs) | |||
286 | int i; | 281 | int i; |
287 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { | 282 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
288 | if (reset_value[i]) { | 283 | if (reset_value[i]) { |
289 | CTRL_READ(low, high, msrs, i); | 284 | rdmsr(msrs->controls[i].addr, low, high); |
290 | CTRL_SET_ACTIVE(low); | 285 | CTRL_SET_ACTIVE(low); |
291 | CTRL_WRITE(low, high, msrs, i); | 286 | wrmsr(msrs->controls[i].addr, low, high); |
292 | } | 287 | } |
293 | } | 288 | } |
294 | 289 | ||
@@ -307,9 +302,9 @@ static void op_amd_stop(struct op_msrs const * const msrs) | |||
307 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { | 302 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
308 | if (!reset_value[i]) | 303 | if (!reset_value[i]) |
309 | continue; | 304 | continue; |
310 | CTRL_READ(low, high, msrs, i); | 305 | rdmsr(msrs->controls[i].addr, low, high); |
311 | CTRL_SET_INACTIVE(low); | 306 | CTRL_SET_INACTIVE(low); |
312 | CTRL_WRITE(low, high, msrs, i); | 307 | wrmsr(msrs->controls[i].addr, low, high); |
313 | } | 308 | } |
314 | 309 | ||
315 | op_amd_stop_ibs(); | 310 | op_amd_stop_ibs(); |