aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2011-03-03 14:28:35 -0500
committerDavid S. Miller <davem@davemloft.net>2011-03-03 14:28:35 -0500
commita45d49d1053fd5954260a70e555daabd5672577d (patch)
tree042d1421b20d6437884c4f0311e5a69caf6d959c
parente066008b38ca9ace1b6de8dbbac8ed460640791d (diff)
parenta52055e055f5b551c0814c4381e43b204f9db777 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/jkirsher/net-next-2.6
Diffstat
-rw-r--r--drivers/net/igb/igb_ethtool.c13
-rw-r--r--drivers/net/igb/igb_main.c7
-rw-r--r--drivers/net/ixgbe/ixgbe.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c63
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c104
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c438
-rw-r--r--drivers/net/ixgbe/ixgbe_common.h4
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82598.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82598.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_nl.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_ethtool.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_fcoe.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_fcoe.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c12
-rw-r--r--drivers/net/ixgbe/ixgbe_mbx.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_mbx.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.c238
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_sriov.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_sriov.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h40
-rw-r--r--drivers/net/ixgbe/ixgbe_x540.c34
-rw-r--r--drivers/net/ixgbevf/ixgbevf_main.c9
27 files changed, 547 insertions, 447 deletions
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c
index a70e16bcfa7e..61f7849cb5a7 100644
--- a/drivers/net/igb/igb_ethtool.c
+++ b/drivers/net/igb/igb_ethtool.c
@@ -727,8 +727,9 @@ static void igb_get_drvinfo(struct net_device *netdev,
727 char firmware_version[32]; 727 char firmware_version[32];
728 u16 eeprom_data; 728 u16 eeprom_data;
729 729
730 strncpy(drvinfo->driver, igb_driver_name, 32); 730 strncpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver) - 1);
731 strncpy(drvinfo->version, igb_driver_version, 32); 731 strncpy(drvinfo->version, igb_driver_version,
732 sizeof(drvinfo->version) - 1);
732 733
733 /* EEPROM image version # is reported as firmware version # for 734 /* EEPROM image version # is reported as firmware version # for
734 * 82575 controllers */ 735 * 82575 controllers */
@@ -738,8 +739,10 @@ static void igb_get_drvinfo(struct net_device *netdev,
738 (eeprom_data & 0x0FF0) >> 4, 739 (eeprom_data & 0x0FF0) >> 4,
739 eeprom_data & 0x000F); 740 eeprom_data & 0x000F);
740 741
741 strncpy(drvinfo->fw_version, firmware_version, 32); 742 strncpy(drvinfo->fw_version, firmware_version,
742 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); 743 sizeof(drvinfo->fw_version) - 1);
744 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
745 sizeof(drvinfo->bus_info) - 1);
743 drvinfo->n_stats = IGB_STATS_LEN; 746 drvinfo->n_stats = IGB_STATS_LEN;
744 drvinfo->testinfo_len = IGB_TEST_LEN; 747 drvinfo->testinfo_len = IGB_TEST_LEN;
745 drvinfo->regdump_len = igb_get_regs_len(netdev); 748 drvinfo->regdump_len = igb_get_regs_len(netdev);
@@ -1070,7 +1073,7 @@ static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1070 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1073 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1071 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1074 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1072 wr32(reg, (_test[pat] & write)); 1075 wr32(reg, (_test[pat] & write));
1073 val = rd32(reg); 1076 val = rd32(reg) & mask;
1074 if (val != (_test[pat] & write & mask)) { 1077 if (val != (_test[pat] & write & mask)) {
1075 dev_err(&adapter->pdev->dev, "pattern test reg %04X " 1078 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1076 "failed: got 0x%08X expected 0x%08X\n", 1079 "failed: got 0x%08X expected 0x%08X\n",
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index 579dbba5f9e4..eef380af0537 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -2291,7 +2291,12 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
2291 switch (hw->mac.type) { 2291 switch (hw->mac.type) {
2292 case e1000_82576: 2292 case e1000_82576:
2293 case e1000_i350: 2293 case e1000_i350:
2294 adapter->vfs_allocated_count = (max_vfs > 7) ? 7 : max_vfs; 2294 if (max_vfs > 7) {
2295 dev_warn(&pdev->dev,
2296 "Maximum of 7 VFs per PF, using max\n");
2297 adapter->vfs_allocated_count = 7;
2298 } else
2299 adapter->vfs_allocated_count = max_vfs;
2295 break; 2300 break;
2296 default: 2301 default:
2297 break; 2302 break;
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index 12769b58c2e7..b60b81bc2b15 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index d0f1d9d2c416..fc41329399be 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -627,7 +627,6 @@ out:
627 return 0; 627 return 0;
628} 628}
629 629
630
631/** 630/**
632 * ixgbe_setup_mac_link_82598 - Set MAC link speed 631 * ixgbe_setup_mac_link_82598 - Set MAC link speed
633 * @hw: pointer to hardware structure 632 * @hw: pointer to hardware structure
@@ -698,7 +697,6 @@ static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
698 /* Setup the PHY according to input speed */ 697 /* Setup the PHY according to input speed */
699 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 698 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
700 autoneg_wait_to_complete); 699 autoneg_wait_to_complete);
701
702 /* Set up MAC */ 700 /* Set up MAC */
703 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 701 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
704 702
@@ -770,7 +768,6 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
770 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 768 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
771 goto no_phy_reset; 769 goto no_phy_reset;
772 770
773
774 hw->phy.ops.reset(hw); 771 hw->phy.ops.reset(hw);
775 } 772 }
776 773
@@ -779,12 +776,9 @@ no_phy_reset:
779 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 776 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
780 * access and verify no pending requests before reset 777 * access and verify no pending requests before reset
781 */ 778 */
782 status = ixgbe_disable_pcie_master(hw); 779 ixgbe_disable_pcie_master(hw);
783 if (status != 0) {
784 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
785 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
786 }
787 780
781mac_reset_top:
788 /* 782 /*
789 * Issue global reset to the MAC. This needs to be a SW reset. 783 * Issue global reset to the MAC. This needs to be a SW reset.
790 * If link reset is used, it might reset the MAC when mng is using it 784 * If link reset is used, it might reset the MAC when mng is using it
@@ -805,6 +799,19 @@ no_phy_reset:
805 hw_dbg(hw, "Reset polling failed to complete.\n"); 799 hw_dbg(hw, "Reset polling failed to complete.\n");
806 } 800 }
807 801
802 /*
803 * Double resets are required for recovery from certain error
804 * conditions. Between resets, it is necessary to stall to allow time
805 * for any pending HW events to complete. We use 1usec since that is
806 * what is needed for ixgbe_disable_pcie_master(). The second reset
807 * then clears out any effects of those events.
808 */
809 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
810 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
811 udelay(1);
812 goto mac_reset_top;
813 }
814
808 msleep(50); 815 msleep(50);
809 816
810 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 817 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
@@ -824,15 +831,15 @@ no_phy_reset:
824 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 831 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
825 } 832 }
826 833
834 /* Store the permanent mac address */
835 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
836
827 /* 837 /*
828 * Store MAC address from RAR0, clear receive address registers, and 838 * Store MAC address from RAR0, clear receive address registers, and
829 * clear the multicast table 839 * clear the multicast table
830 */ 840 */
831 hw->mac.ops.init_rx_addrs(hw); 841 hw->mac.ops.init_rx_addrs(hw);
832 842
833 /* Store the permanent mac address */
834 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
835
836reset_hw_out: 843reset_hw_out:
837 if (phy_status) 844 if (phy_status)
838 status = phy_status; 845 status = phy_status;
@@ -849,6 +856,13 @@ reset_hw_out:
849static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 856static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
850{ 857{
851 u32 rar_high; 858 u32 rar_high;
859 u32 rar_entries = hw->mac.num_rar_entries;
860
861 /* Make sure we are using a valid rar index range */
862 if (rar >= rar_entries) {
863 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
864 return IXGBE_ERR_INVALID_ARGUMENT;
865 }
852 866
853 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 867 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
854 rar_high &= ~IXGBE_RAH_VIND_MASK; 868 rar_high &= ~IXGBE_RAH_VIND_MASK;
@@ -868,14 +882,17 @@ static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
868 u32 rar_high; 882 u32 rar_high;
869 u32 rar_entries = hw->mac.num_rar_entries; 883 u32 rar_entries = hw->mac.num_rar_entries;
870 884
871 if (rar < rar_entries) { 885
872 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 886 /* Make sure we are using a valid rar index range */
873 if (rar_high & IXGBE_RAH_VIND_MASK) { 887 if (rar >= rar_entries) {
874 rar_high &= ~IXGBE_RAH_VIND_MASK;
875 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
876 }
877 } else {
878 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 888 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
889 return IXGBE_ERR_INVALID_ARGUMENT;
890 }
891
892 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
893 if (rar_high & IXGBE_RAH_VIND_MASK) {
894 rar_high &= ~IXGBE_RAH_VIND_MASK;
895 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
879 } 896 }
880 897
881 return 0; 898 return 0;
@@ -994,13 +1011,12 @@ static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
994} 1011}
995 1012
996/** 1013/**
997 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module 1014 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
998 * over I2C interface through an intermediate phy.
999 * @hw: pointer to hardware structure 1015 * @hw: pointer to hardware structure
1000 * @byte_offset: EEPROM byte offset to read 1016 * @byte_offset: EEPROM byte offset to read
1001 * @eeprom_data: value read 1017 * @eeprom_data: value read
1002 * 1018 *
1003 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1019 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1004 **/ 1020 **/
1005static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1021static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1006 u8 *eeprom_data) 1022 u8 *eeprom_data)
@@ -1179,13 +1195,14 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
1179 .set_vmdq = &ixgbe_set_vmdq_82598, 1195 .set_vmdq = &ixgbe_set_vmdq_82598,
1180 .clear_vmdq = &ixgbe_clear_vmdq_82598, 1196 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1181 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 1197 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1182 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1183 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 1198 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1184 .enable_mc = &ixgbe_enable_mc_generic, 1199 .enable_mc = &ixgbe_enable_mc_generic,
1185 .disable_mc = &ixgbe_disable_mc_generic, 1200 .disable_mc = &ixgbe_disable_mc_generic,
1186 .clear_vfta = &ixgbe_clear_vfta_82598, 1201 .clear_vfta = &ixgbe_clear_vfta_82598,
1187 .set_vfta = &ixgbe_set_vfta_82598, 1202 .set_vfta = &ixgbe_set_vfta_82598,
1188 .fc_enable = &ixgbe_fc_enable_82598, 1203 .fc_enable = &ixgbe_fc_enable_82598,
1204 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1205 .release_swfw_sync = &ixgbe_release_swfw_sync,
1189}; 1206};
1190 1207
1191static struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1208static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index a21f5817685b..5ef968a10d42 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -112,7 +112,8 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
112 goto setup_sfp_out; 112 goto setup_sfp_out;
113 113
114 /* PHY config will finish before releasing the semaphore */ 114 /* PHY config will finish before releasing the semaphore */
115 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 115 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
116 IXGBE_GSSR_MAC_CSR_SM);
116 if (ret_val != 0) { 117 if (ret_val != 0) {
117 ret_val = IXGBE_ERR_SWFW_SYNC; 118 ret_val = IXGBE_ERR_SWFW_SYNC;
118 goto setup_sfp_out; 119 goto setup_sfp_out;
@@ -329,11 +330,14 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
329 enum ixgbe_media_type media_type; 330 enum ixgbe_media_type media_type;
330 331
331 /* Detect if there is a copper PHY attached. */ 332 /* Detect if there is a copper PHY attached. */
332 if (hw->phy.type == ixgbe_phy_cu_unknown || 333 switch (hw->phy.type) {
333 hw->phy.type == ixgbe_phy_tn || 334 case ixgbe_phy_cu_unknown:
334 hw->phy.type == ixgbe_phy_aq) { 335 case ixgbe_phy_tn:
336 case ixgbe_phy_aq:
335 media_type = ixgbe_media_type_copper; 337 media_type = ixgbe_media_type_copper;
336 goto out; 338 goto out;
339 default:
340 break;
337 } 341 }
338 342
339 switch (hw->device_id) { 343 switch (hw->device_id) {
@@ -354,6 +358,9 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
354 case IXGBE_DEV_ID_82599_CX4: 358 case IXGBE_DEV_ID_82599_CX4:
355 media_type = ixgbe_media_type_cx4; 359 media_type = ixgbe_media_type_cx4;
356 break; 360 break;
361 case IXGBE_DEV_ID_82599_T3_LOM:
362 media_type = ixgbe_media_type_copper;
363 break;
357 default: 364 default:
358 media_type = ixgbe_media_type_unknown; 365 media_type = ixgbe_media_type_unknown;
359 break; 366 break;
@@ -411,14 +418,14 @@ static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
411 return status; 418 return status;
412} 419}
413 420
414 /** 421/**
415 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 422 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
416 * @hw: pointer to hardware structure 423 * @hw: pointer to hardware structure
417 * 424 *
418 * The base drivers may require better control over SFP+ module 425 * The base drivers may require better control over SFP+ module
419 * PHY states. This includes selectively shutting down the Tx 426 * PHY states. This includes selectively shutting down the Tx
420 * laser on the PHY, effectively halting physical link. 427 * laser on the PHY, effectively halting physical link.
421 **/ 428 **/
422static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 429static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
423{ 430{
424 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 431 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
@@ -536,7 +543,6 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
536 * Section 73.10.2, we may have to wait up to 500ms if KR is 543 * Section 73.10.2, we may have to wait up to 500ms if KR is
537 * attempted. 82599 uses the same timing for 10g SFI. 544 * attempted. 82599 uses the same timing for 10g SFI.
538 */ 545 */
539
540 for (i = 0; i < 5; i++) { 546 for (i = 0; i < 5; i++) {
541 /* Wait for the link partner to also set speed */ 547 /* Wait for the link partner to also set speed */
542 msleep(100); 548 msleep(100);
@@ -761,7 +767,6 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
761 else 767 else
762 orig_autoc = autoc; 768 orig_autoc = autoc;
763 769
764
765 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 770 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
766 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 771 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
767 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 772 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
@@ -898,12 +903,9 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
898 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 903 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
899 * access and verify no pending requests before reset 904 * access and verify no pending requests before reset
900 */ 905 */
901 status = ixgbe_disable_pcie_master(hw); 906 ixgbe_disable_pcie_master(hw);
902 if (status != 0) {
903 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
904 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
905 }
906 907
908mac_reset_top:
907 /* 909 /*
908 * Issue global reset to the MAC. This needs to be a SW reset. 910 * Issue global reset to the MAC. This needs to be a SW reset.
909 * If link reset is used, it might reset the MAC when mng is using it 911 * If link reset is used, it might reset the MAC when mng is using it
@@ -924,6 +926,19 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
924 hw_dbg(hw, "Reset polling failed to complete.\n"); 926 hw_dbg(hw, "Reset polling failed to complete.\n");
925 } 927 }
926 928
929 /*
930 * Double resets are required for recovery from certain error
931 * conditions. Between resets, it is necessary to stall to allow time
932 * for any pending HW events to complete. We use 1usec since that is
933 * what is needed for ixgbe_disable_pcie_master(). The second reset
934 * then clears out any effects of those events.
935 */
936 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
937 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
938 udelay(1);
939 goto mac_reset_top;
940 }
941
927 msleep(50); 942 msleep(50);
928 943
929 /* 944 /*
@@ -951,6 +966,9 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
951 } 966 }
952 } 967 }
953 968
969 /* Store the permanent mac address */
970 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
971
954 /* 972 /*
955 * Store MAC address from RAR0, clear receive address registers, and 973 * Store MAC address from RAR0, clear receive address registers, and
956 * clear the multicast table. Also reset num_rar_entries to 128, 974 * clear the multicast table. Also reset num_rar_entries to 128,
@@ -959,9 +977,6 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
959 hw->mac.num_rar_entries = 128; 977 hw->mac.num_rar_entries = 128;
960 hw->mac.ops.init_rx_addrs(hw); 978 hw->mac.ops.init_rx_addrs(hw);
961 979
962 /* Store the permanent mac address */
963 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
964
965 /* Store the permanent SAN mac address */ 980 /* Store the permanent SAN mac address */
966 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 981 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
967 982
@@ -1733,13 +1748,34 @@ static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1733 * @hw: pointer to hardware structure 1748 * @hw: pointer to hardware structure
1734 * 1749 *
1735 * Determines the physical layer module found on the current adapter. 1750 * Determines the physical layer module found on the current adapter.
1751 * If PHY already detected, maintains current PHY type in hw struct,
1752 * otherwise executes the PHY detection routine.
1736 **/ 1753 **/
1737static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1754s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1738{ 1755{
1739 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1756 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1757
1758 /* Detect PHY if not unknown - returns success if already detected. */
1740 status = ixgbe_identify_phy_generic(hw); 1759 status = ixgbe_identify_phy_generic(hw);
1741 if (status != 0) 1760 if (status != 0) {
1742 status = ixgbe_identify_sfp_module_generic(hw); 1761 /* 82599 10GBASE-T requires an external PHY */
1762 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1763 goto out;
1764 else
1765 status = ixgbe_identify_sfp_module_generic(hw);
1766 }
1767
1768 /* Set PHY type none if no PHY detected */
1769 if (hw->phy.type == ixgbe_phy_unknown) {
1770 hw->phy.type = ixgbe_phy_none;
1771 status = 0;
1772 }
1773
1774 /* Return error if SFP module has been detected but is not supported */
1775 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1776 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1777
1778out:
1743 return status; 1779 return status;
1744} 1780}
1745 1781
@@ -1763,11 +1799,12 @@ static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1763 1799
1764 hw->phy.ops.identify(hw); 1800 hw->phy.ops.identify(hw);
1765 1801
1766 if (hw->phy.type == ixgbe_phy_tn || 1802 switch (hw->phy.type) {
1767 hw->phy.type == ixgbe_phy_aq || 1803 case ixgbe_phy_tn:
1768 hw->phy.type == ixgbe_phy_cu_unknown) { 1804 case ixgbe_phy_aq:
1805 case ixgbe_phy_cu_unknown:
1769 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, 1806 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1770 &ext_ability); 1807 &ext_ability);
1771 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 1808 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1772 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1809 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1773 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 1810 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
@@ -1775,6 +1812,8 @@ static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1775 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 1812 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1776 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1813 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1777 goto out; 1814 goto out;
1815 default:
1816 break;
1778 } 1817 }
1779 1818
1780 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1819 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
@@ -1886,6 +1925,7 @@ static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1886 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 1925 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1887 break; 1926 break;
1888 else 1927 else
1928 /* Use interrupt-safe sleep just in case */
1889 udelay(10); 1929 udelay(10);
1890 } 1930 }
1891 1931
@@ -1995,7 +2035,6 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
1995 .set_vmdq = &ixgbe_set_vmdq_generic, 2035 .set_vmdq = &ixgbe_set_vmdq_generic,
1996 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2036 .clear_vmdq = &ixgbe_clear_vmdq_generic,
1997 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2037 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1998 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1999 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2038 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2000 .enable_mc = &ixgbe_enable_mc_generic, 2039 .enable_mc = &ixgbe_enable_mc_generic,
2001 .disable_mc = &ixgbe_disable_mc_generic, 2040 .disable_mc = &ixgbe_disable_mc_generic,
@@ -2006,6 +2045,9 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2006 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2045 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2007 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2046 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2008 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2047 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2048 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2049 .release_swfw_sync = &ixgbe_release_swfw_sync,
2050
2009}; 2051};
2010 2052
2011static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2053static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index ebbda7d15254..a7fb2e00f766 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -46,10 +46,7 @@ static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
48 48
49static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
50static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
51static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
52static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
53static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num); 50static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
54 51
55/** 52/**
@@ -454,8 +451,7 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
454 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 451 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
455 * access and verify no pending requests 452 * access and verify no pending requests
456 */ 453 */
457 if (ixgbe_disable_pcie_master(hw) != 0) 454 ixgbe_disable_pcie_master(hw);
458 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
459 455
460 return 0; 456 return 0;
461} 457}
@@ -603,7 +599,6 @@ s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
603 ixgbe_shift_out_eeprom_bits(hw, data, 16); 599 ixgbe_shift_out_eeprom_bits(hw, data, 16);
604 ixgbe_standby_eeprom(hw); 600 ixgbe_standby_eeprom(hw);
605 601
606 msleep(hw->eeprom.semaphore_delay);
607 /* Done with writing - release the EEPROM */ 602 /* Done with writing - release the EEPROM */
608 ixgbe_release_eeprom(hw); 603 ixgbe_release_eeprom(hw);
609 } 604 }
@@ -747,10 +742,10 @@ s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
747static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 742static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
748{ 743{
749 s32 status = 0; 744 s32 status = 0;
750 u32 eec = 0; 745 u32 eec;
751 u32 i; 746 u32 i;
752 747
753 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 748 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
754 status = IXGBE_ERR_SWFW_SYNC; 749 status = IXGBE_ERR_SWFW_SYNC;
755 750
756 if (status == 0) { 751 if (status == 0) {
@@ -773,18 +768,18 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
773 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 768 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
774 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 769 hw_dbg(hw, "Could not acquire EEPROM grant\n");
775 770
776 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 771 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
777 status = IXGBE_ERR_EEPROM; 772 status = IXGBE_ERR_EEPROM;
778 } 773 }
779 }
780 774
781 /* Setup EEPROM for Read/Write */ 775 /* Setup EEPROM for Read/Write */
782 if (status == 0) { 776 if (status == 0) {
783 /* Clear CS and SK */ 777 /* Clear CS and SK */
784 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 778 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
785 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 779 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
786 IXGBE_WRITE_FLUSH(hw); 780 IXGBE_WRITE_FLUSH(hw);
787 udelay(1); 781 udelay(1);
782 }
788 } 783 }
789 return status; 784 return status;
790} 785}
@@ -798,13 +793,10 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
798static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 793static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
799{ 794{
800 s32 status = IXGBE_ERR_EEPROM; 795 s32 status = IXGBE_ERR_EEPROM;
801 u32 timeout; 796 u32 timeout = 2000;
802 u32 i; 797 u32 i;
803 u32 swsm; 798 u32 swsm;
804 799
805 /* Set timeout value based on size of EEPROM */
806 timeout = hw->eeprom.word_size + 1;
807
808 /* Get SMBI software semaphore between device drivers first */ 800 /* Get SMBI software semaphore between device drivers first */
809 for (i = 0; i < timeout; i++) { 801 for (i = 0; i < timeout; i++) {
810 /* 802 /*
@@ -816,7 +808,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
816 status = 0; 808 status = 0;
817 break; 809 break;
818 } 810 }
819 msleep(1); 811 udelay(50);
820 } 812 }
821 813
822 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 814 /* Now get the semaphore between SW/FW through the SWESMBI bit */
@@ -844,11 +836,14 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
844 * was not granted because we don't have access to the EEPROM 836 * was not granted because we don't have access to the EEPROM
845 */ 837 */
846 if (i >= timeout) { 838 if (i >= timeout) {
847 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " 839 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
848 "not granted.\n"); 840 "not granted.\n");
849 ixgbe_release_eeprom_semaphore(hw); 841 ixgbe_release_eeprom_semaphore(hw);
850 status = IXGBE_ERR_EEPROM; 842 status = IXGBE_ERR_EEPROM;
851 } 843 }
844 } else {
845 hw_dbg(hw, "Software semaphore SMBI between device drivers "
846 "not granted.\n");
852 } 847 }
853 848
854 return status; 849 return status;
@@ -1081,10 +1076,13 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1081 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1076 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1082 1077
1083 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1078 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1079
1080 /* Delay before attempt to obtain semaphore again to allow FW access */
1081 msleep(hw->eeprom.semaphore_delay);
1084} 1082}
1085 1083
1086/** 1084/**
1087 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum 1085 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1088 * @hw: pointer to hardware structure 1086 * @hw: pointer to hardware structure
1089 **/ 1087 **/
1090u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1088u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
@@ -1190,7 +1188,7 @@ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1190 if (status == 0) { 1188 if (status == 0) {
1191 checksum = hw->eeprom.ops.calc_checksum(hw); 1189 checksum = hw->eeprom.ops.calc_checksum(hw);
1192 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1190 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1193 checksum); 1191 checksum);
1194 } else { 1192 } else {
1195 hw_dbg(hw, "EEPROM read failed\n"); 1193 hw_dbg(hw, "EEPROM read failed\n");
1196 } 1194 }
@@ -1238,37 +1236,37 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1238 u32 rar_low, rar_high; 1236 u32 rar_low, rar_high;
1239 u32 rar_entries = hw->mac.num_rar_entries; 1237 u32 rar_entries = hw->mac.num_rar_entries;
1240 1238
1239 /* Make sure we are using a valid rar index range */
1240 if (index >= rar_entries) {
1241 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1242 return IXGBE_ERR_INVALID_ARGUMENT;
1243 }
1244
1241 /* setup VMDq pool selection before this RAR gets enabled */ 1245 /* setup VMDq pool selection before this RAR gets enabled */
1242 hw->mac.ops.set_vmdq(hw, index, vmdq); 1246 hw->mac.ops.set_vmdq(hw, index, vmdq);
1243 1247
1244 /* Make sure we are using a valid rar index range */ 1248 /*
1245 if (index < rar_entries) { 1249 * HW expects these in little endian so we reverse the byte
1246 /* 1250 * order from network order (big endian) to little endian
1247 * HW expects these in little endian so we reverse the byte 1251 */
1248 * order from network order (big endian) to little endian 1252 rar_low = ((u32)addr[0] |
1249 */ 1253 ((u32)addr[1] << 8) |
1250 rar_low = ((u32)addr[0] | 1254 ((u32)addr[2] << 16) |
1251 ((u32)addr[1] << 8) | 1255 ((u32)addr[3] << 24));
1252 ((u32)addr[2] << 16) | 1256 /*
1253 ((u32)addr[3] << 24)); 1257 * Some parts put the VMDq setting in the extra RAH bits,
1254 /* 1258 * so save everything except the lower 16 bits that hold part
1255 * Some parts put the VMDq setting in the extra RAH bits, 1259 * of the address and the address valid bit.
1256 * so save everything except the lower 16 bits that hold part 1260 */
1257 * of the address and the address valid bit. 1261 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1258 */ 1262 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1259 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1263 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1260 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1261 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1262 1264
1263 if (enable_addr != 0) 1265 if (enable_addr != 0)
1264 rar_high |= IXGBE_RAH_AV; 1266 rar_high |= IXGBE_RAH_AV;
1265 1267
1266 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1268 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1267 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1269 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1268 } else {
1269 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1270 return IXGBE_ERR_RAR_INDEX;
1271 }
1272 1270
1273 return 0; 1271 return 0;
1274} 1272}
@@ -1286,58 +1284,26 @@ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1286 u32 rar_entries = hw->mac.num_rar_entries; 1284 u32 rar_entries = hw->mac.num_rar_entries;
1287 1285
1288 /* Make sure we are using a valid rar index range */ 1286 /* Make sure we are using a valid rar index range */
1289 if (index < rar_entries) { 1287 if (index >= rar_entries) {
1290 /*
1291 * Some parts put the VMDq setting in the extra RAH bits,
1292 * so save everything except the lower 16 bits that hold part
1293 * of the address and the address valid bit.
1294 */
1295 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1296 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1297
1298 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1299 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1300 } else {
1301 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1288 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1302 return IXGBE_ERR_RAR_INDEX; 1289 return IXGBE_ERR_INVALID_ARGUMENT;
1303 } 1290 }
1304 1291
1305 /* clear VMDq pool/queue selection for this RAR */ 1292 /*
1306 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1293 * Some parts put the VMDq setting in the extra RAH bits,
1307 1294 * so save everything except the lower 16 bits that hold part
1308 return 0; 1295 * of the address and the address valid bit.
1309} 1296 */
1310
1311/**
1312 * ixgbe_enable_rar - Enable Rx address register
1313 * @hw: pointer to hardware structure
1314 * @index: index into the RAR table
1315 *
1316 * Enables the select receive address register.
1317 **/
1318static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1319{
1320 u32 rar_high;
1321
1322 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1297 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1323 rar_high |= IXGBE_RAH_AV; 1298 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1299
1300 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1324 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1301 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1325}
1326 1302
1327/** 1303 /* clear VMDq pool/queue selection for this RAR */
1328 * ixgbe_disable_rar - Disable Rx address register 1304 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1329 * @hw: pointer to hardware structure
1330 * @index: index into the RAR table
1331 *
1332 * Disables the select receive address register.
1333 **/
1334static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1335{
1336 u32 rar_high;
1337 1305
1338 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1306 return 0;
1339 rar_high &= (~IXGBE_RAH_AV);
1340 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1341} 1307}
1342 1308
1343/** 1309/**
@@ -1386,7 +1352,6 @@ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1386 } 1352 }
1387 1353
1388 /* Clear the MTA */ 1354 /* Clear the MTA */
1389 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1390 hw->addr_ctrl.mta_in_use = 0; 1355 hw->addr_ctrl.mta_in_use = 0;
1391 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1356 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1392 1357
@@ -1401,105 +1366,6 @@ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1401} 1366}
1402 1367
1403/** 1368/**
1404 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1405 * @hw: pointer to hardware structure
1406 * @addr: new address
1407 *
1408 * Adds it to unused receive address register or goes into promiscuous mode.
1409 **/
1410static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1411{
1412 u32 rar_entries = hw->mac.num_rar_entries;
1413 u32 rar;
1414
1415 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1416 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1417
1418 /*
1419 * Place this address in the RAR if there is room,
1420 * else put the controller into promiscuous mode
1421 */
1422 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1423 rar = hw->addr_ctrl.rar_used_count -
1424 hw->addr_ctrl.mc_addr_in_rar_count;
1425 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1426 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1427 hw->addr_ctrl.rar_used_count++;
1428 } else {
1429 hw->addr_ctrl.overflow_promisc++;
1430 }
1431
1432 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1433}
1434
1435/**
1436 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1437 * @hw: pointer to hardware structure
1438 * @netdev: pointer to net device structure
1439 *
1440 * The given list replaces any existing list. Clears the secondary addrs from
1441 * receive address registers. Uses unused receive address registers for the
1442 * first secondary addresses, and falls back to promiscuous mode as needed.
1443 *
1444 * Drivers using secondary unicast addresses must set user_set_promisc when
1445 * manually putting the device into promiscuous mode.
1446 **/
1447s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
1448 struct net_device *netdev)
1449{
1450 u32 i;
1451 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1452 u32 uc_addr_in_use;
1453 u32 fctrl;
1454 struct netdev_hw_addr *ha;
1455
1456 /*
1457 * Clear accounting of old secondary address list,
1458 * don't count RAR[0]
1459 */
1460 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1461 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1462 hw->addr_ctrl.overflow_promisc = 0;
1463
1464 /* Zero out the other receive addresses */
1465 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
1466 for (i = 0; i < uc_addr_in_use; i++) {
1467 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1468 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
1469 }
1470
1471 /* Add the new addresses */
1472 netdev_for_each_uc_addr(ha, netdev) {
1473 hw_dbg(hw, " Adding the secondary addresses:\n");
1474 ixgbe_add_uc_addr(hw, ha->addr, 0);
1475 }
1476
1477 if (hw->addr_ctrl.overflow_promisc) {
1478 /* enable promisc if not already in overflow or set by user */
1479 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1480 hw_dbg(hw, " Entering address overflow promisc mode\n");
1481 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1482 fctrl |= IXGBE_FCTRL_UPE;
1483 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1484 hw->addr_ctrl.uc_set_promisc = true;
1485 }
1486 } else {
1487 /* only disable if set by overflow, not by user */
1488 if ((old_promisc_setting && hw->addr_ctrl.uc_set_promisc) &&
1489 !(hw->addr_ctrl.user_set_promisc)) {
1490 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1491 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1492 fctrl &= ~IXGBE_FCTRL_UPE;
1493 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1494 hw->addr_ctrl.uc_set_promisc = false;
1495 }
1496 }
1497
1498 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
1499 return 0;
1500}
1501
1502/**
1503 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1369 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1504 * @hw: pointer to hardware structure 1370 * @hw: pointer to hardware structure
1505 * @mc_addr: the multicast address 1371 * @mc_addr: the multicast address
@@ -1550,7 +1416,6 @@ static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1550 u32 vector; 1416 u32 vector;
1551 u32 vector_bit; 1417 u32 vector_bit;
1552 u32 vector_reg; 1418 u32 vector_reg;
1553 u32 mta_reg;
1554 1419
1555 hw->addr_ctrl.mta_in_use++; 1420 hw->addr_ctrl.mta_in_use++;
1556 1421
@@ -1568,9 +1433,7 @@ static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1568 */ 1433 */
1569 vector_reg = (vector >> 5) & 0x7F; 1434 vector_reg = (vector >> 5) & 0x7F;
1570 vector_bit = vector & 0x1F; 1435 vector_bit = vector & 0x1F;
1571 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1436 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
1572 mta_reg |= (1 << vector_bit);
1573 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1574} 1437}
1575 1438
1576/** 1439/**
@@ -1596,18 +1459,21 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1596 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 1459 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
1597 hw->addr_ctrl.mta_in_use = 0; 1460 hw->addr_ctrl.mta_in_use = 0;
1598 1461
1599 /* Clear the MTA */ 1462 /* Clear mta_shadow */
1600 hw_dbg(hw, " Clearing MTA\n"); 1463 hw_dbg(hw, " Clearing MTA\n");
1601 for (i = 0; i < hw->mac.mcft_size; i++) 1464 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
1602 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1603 1465
1604 /* Add the new addresses */ 1466 /* Update mta shadow */
1605 netdev_for_each_mc_addr(ha, netdev) { 1467 netdev_for_each_mc_addr(ha, netdev) {
1606 hw_dbg(hw, " Adding the multicast addresses:\n"); 1468 hw_dbg(hw, " Adding the multicast addresses:\n");
1607 ixgbe_set_mta(hw, ha->addr); 1469 ixgbe_set_mta(hw, ha->addr);
1608 } 1470 }
1609 1471
1610 /* Enable mta */ 1472 /* Enable mta */
1473 for (i = 0; i < hw->mac.mcft_size; i++)
1474 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1475 hw->mac.mta_shadow[i]);
1476
1611 if (hw->addr_ctrl.mta_in_use > 0) 1477 if (hw->addr_ctrl.mta_in_use > 0)
1612 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1478 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1613 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1479 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
@@ -1624,15 +1490,8 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1624 **/ 1490 **/
1625s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1491s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1626{ 1492{
1627 u32 i;
1628 u32 rar_entries = hw->mac.num_rar_entries;
1629 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1493 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1630 1494
1631 if (a->mc_addr_in_rar_count > 0)
1632 for (i = (rar_entries - a->mc_addr_in_rar_count);
1633 i < rar_entries; i++)
1634 ixgbe_enable_rar(hw, i);
1635
1636 if (a->mta_in_use > 0) 1495 if (a->mta_in_use > 0)
1637 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1496 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1638 hw->mac.mc_filter_type); 1497 hw->mac.mc_filter_type);
@@ -1648,15 +1507,8 @@ s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1648 **/ 1507 **/
1649s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1508s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1650{ 1509{
1651 u32 i;
1652 u32 rar_entries = hw->mac.num_rar_entries;
1653 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1510 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1654 1511
1655 if (a->mc_addr_in_rar_count > 0)
1656 for (i = (rar_entries - a->mc_addr_in_rar_count);
1657 i < rar_entries; i++)
1658 ixgbe_disable_rar(hw, i);
1659
1660 if (a->mta_in_use > 0) 1512 if (a->mta_in_use > 0)
1661 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1513 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1662 1514
@@ -1703,7 +1555,9 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1703 * 2: Tx flow control is enabled (we can send pause frames but 1555 * 2: Tx flow control is enabled (we can send pause frames but
1704 * we do not support receiving pause frames). 1556 * we do not support receiving pause frames).
1705 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1557 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1558#ifdef CONFIG_DCB
1706 * 4: Priority Flow Control is enabled. 1559 * 4: Priority Flow Control is enabled.
1560#endif
1707 * other: Invalid. 1561 * other: Invalid.
1708 */ 1562 */
1709 switch (hw->fc.current_mode) { 1563 switch (hw->fc.current_mode) {
@@ -2159,10 +2013,16 @@ out:
2159 **/ 2013 **/
2160s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2014s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2161{ 2015{
2016 struct ixgbe_adapter *adapter = hw->back;
2162 u32 i; 2017 u32 i;
2163 u32 reg_val; 2018 u32 reg_val;
2164 u32 number_of_queues; 2019 u32 number_of_queues;
2165 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2020 s32 status = 0;
2021 u16 dev_status = 0;
2022
2023 /* Just jump out if bus mastering is already disabled */
2024 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2025 goto out;
2166 2026
2167 /* Disable the receive unit by stopping each queue */ 2027 /* Disable the receive unit by stopping each queue */
2168 number_of_queues = hw->mac.max_rx_queues; 2028 number_of_queues = hw->mac.max_rx_queues;
@@ -2179,13 +2039,43 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2179 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2039 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2180 2040
2181 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2041 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2182 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { 2042 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2183 status = 0; 2043 goto check_device_status;
2044 udelay(100);
2045 }
2046
2047 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2048 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2049
2050 /*
2051 * Before proceeding, make sure that the PCIe block does not have
2052 * transactions pending.
2053 */
2054check_device_status:
2055 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2056 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2057 &dev_status);
2058 if (!(dev_status & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2184 break; 2059 break;
2185 }
2186 udelay(100); 2060 udelay(100);
2187 } 2061 }
2188 2062
2063 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2064 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2065 else
2066 goto out;
2067
2068 /*
2069 * Two consecutive resets are required via CTRL.RST per datasheet
2070 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2071 * of this need. The first reset prevents new master requests from
2072 * being issued by our device. We then must wait 1usec for any
2073 * remaining completions from the PCIe bus to trickle in, and then reset
2074 * again to clear out any effects they may have had on our device.
2075 */
2076 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2077
2078out:
2189 return status; 2079 return status;
2190} 2080}
2191 2081
@@ -2206,6 +2096,10 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2206 s32 timeout = 200; 2096 s32 timeout = 200;
2207 2097
2208 while (timeout) { 2098 while (timeout) {
2099 /*
2100 * SW EEPROM semaphore bit is used for access to all
2101 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2102 */
2209 if (ixgbe_get_eeprom_semaphore(hw)) 2103 if (ixgbe_get_eeprom_semaphore(hw))
2210 return IXGBE_ERR_SWFW_SYNC; 2104 return IXGBE_ERR_SWFW_SYNC;
2211 2105
@@ -2223,7 +2117,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2223 } 2117 }
2224 2118
2225 if (!timeout) { 2119 if (!timeout) {
2226 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); 2120 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2227 return IXGBE_ERR_SWFW_SYNC; 2121 return IXGBE_ERR_SWFW_SYNC;
2228 } 2122 }
2229 2123
@@ -2427,37 +2321,38 @@ s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2427 u32 mpsar_lo, mpsar_hi; 2321 u32 mpsar_lo, mpsar_hi;
2428 u32 rar_entries = hw->mac.num_rar_entries; 2322 u32 rar_entries = hw->mac.num_rar_entries;
2429 2323
2430 if (rar < rar_entries) { 2324 /* Make sure we are using a valid rar index range */
2431 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2325 if (rar >= rar_entries) {
2432 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2326 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2327 return IXGBE_ERR_INVALID_ARGUMENT;
2328 }
2433 2329
2434 if (!mpsar_lo && !mpsar_hi) 2330 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2435 goto done; 2331 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2436 2332
2437 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2333 if (!mpsar_lo && !mpsar_hi)
2438 if (mpsar_lo) { 2334 goto done;
2439 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2440 mpsar_lo = 0;
2441 }
2442 if (mpsar_hi) {
2443 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2444 mpsar_hi = 0;
2445 }
2446 } else if (vmdq < 32) {
2447 mpsar_lo &= ~(1 << vmdq);
2448 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2449 } else {
2450 mpsar_hi &= ~(1 << (vmdq - 32));
2451 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2452 }
2453 2335
2454 /* was that the last pool using this rar? */ 2336 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2455 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2337 if (mpsar_lo) {
2456 hw->mac.ops.clear_rar(hw, rar); 2338 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2339 mpsar_lo = 0;
2340 }
2341 if (mpsar_hi) {
2342 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2343 mpsar_hi = 0;
2344 }
2345 } else if (vmdq < 32) {
2346 mpsar_lo &= ~(1 << vmdq);
2347 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2457 } else { 2348 } else {
2458 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2349 mpsar_hi &= ~(1 << (vmdq - 32));
2350 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2459 } 2351 }
2460 2352
2353 /* was that the last pool using this rar? */
2354 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2355 hw->mac.ops.clear_rar(hw, rar);
2461done: 2356done:
2462 return 0; 2357 return 0;
2463} 2358}
@@ -2473,18 +2368,20 @@ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2473 u32 mpsar; 2368 u32 mpsar;
2474 u32 rar_entries = hw->mac.num_rar_entries; 2369 u32 rar_entries = hw->mac.num_rar_entries;
2475 2370
2476 if (rar < rar_entries) { 2371 /* Make sure we are using a valid rar index range */
2477 if (vmdq < 32) { 2372 if (rar >= rar_entries) {
2478 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2479 mpsar |= 1 << vmdq;
2480 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2481 } else {
2482 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2483 mpsar |= 1 << (vmdq - 32);
2484 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2485 }
2486 } else {
2487 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2373 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2374 return IXGBE_ERR_INVALID_ARGUMENT;
2375 }
2376
2377 if (vmdq < 32) {
2378 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2379 mpsar |= 1 << vmdq;
2380 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2381 } else {
2382 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2383 mpsar |= 1 << (vmdq - 32);
2384 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2488 } 2385 }
2489 return 0; 2386 return 0;
2490} 2387}
@@ -2497,7 +2394,6 @@ s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2497{ 2394{
2498 int i; 2395 int i;
2499 2396
2500
2501 for (i = 0; i < 128; i++) 2397 for (i = 0; i < 128; i++)
2502 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 2398 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2503 2399
@@ -2726,12 +2622,21 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2726 * Reads the links register to determine if link is up and the current speed 2622 * Reads the links register to determine if link is up and the current speed
2727 **/ 2623 **/
2728s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 2624s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2729 bool *link_up, bool link_up_wait_to_complete) 2625 bool *link_up, bool link_up_wait_to_complete)
2730{ 2626{
2731 u32 links_reg; 2627 u32 links_reg, links_orig;
2732 u32 i; 2628 u32 i;
2733 2629
2630 /* clear the old state */
2631 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
2632
2734 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 2633 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2634
2635 if (links_orig != links_reg) {
2636 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
2637 links_orig, links_reg);
2638 }
2639
2735 if (link_up_wait_to_complete) { 2640 if (link_up_wait_to_complete) {
2736 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 2641 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2737 if (links_reg & IXGBE_LINKS_UP) { 2642 if (links_reg & IXGBE_LINKS_UP) {
@@ -2754,10 +2659,13 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2754 IXGBE_LINKS_SPEED_10G_82599) 2659 IXGBE_LINKS_SPEED_10G_82599)
2755 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2660 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2756 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 2661 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2757 IXGBE_LINKS_SPEED_1G_82599) 2662 IXGBE_LINKS_SPEED_1G_82599)
2758 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2663 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2759 else 2664 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2665 IXGBE_LINKS_SPEED_100_82599)
2760 *speed = IXGBE_LINK_SPEED_100_FULL; 2666 *speed = IXGBE_LINK_SPEED_100_FULL;
2667 else
2668 *speed = IXGBE_LINK_SPEED_UNKNOWN;
2761 2669
2762 /* if link is down, zero out the current_mode */ 2670 /* if link is down, zero out the current_mode */
2763 if (*link_up == false) { 2671 if (*link_up == false) {
diff --git a/drivers/net/ixgbe/ixgbe_common.h b/drivers/net/ixgbe/ixgbe_common.h
index 90cceb4a6317..508f635fc2ca 100644
--- a/drivers/net/ixgbe/ixgbe_common.h
+++ b/drivers/net/ixgbe/ixgbe_common.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -63,8 +63,6 @@ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
63s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw); 63s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
64s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 64s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
65 struct net_device *netdev); 65 struct net_device *netdev);
66s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
67 struct net_device *netdev);
68s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw); 66s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
69s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw); 67s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
70s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval); 68s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
diff --git a/drivers/net/ixgbe/ixgbe_dcb.c b/drivers/net/ixgbe/ixgbe_dcb.c
index 13c962efbfc9..c2ee6fcb4e91 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.c
+++ b/drivers/net/ixgbe/ixgbe_dcb.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_dcb.h b/drivers/net/ixgbe/ixgbe_dcb.h
index e5935114815e..515bc27477f6 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.h
+++ b/drivers/net/ixgbe/ixgbe_dcb.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ixgbe/ixgbe_dcb_82598.c
index 2965edcdac7b..c97cf9160dc0 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.h b/drivers/net/ixgbe/ixgbe_dcb_82598.h
index 0d2a758effce..1e9750c2b46b 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.h
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index b0d97a98c84d..beaa1c1c1e67 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.h b/drivers/net/ixgbe/ixgbe_dcb_82599.h
index 5b0ca85614d1..0b39ab4ffc70 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.h
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ixgbe/ixgbe_dcb_nl.c
index a977df3fe81b..d7f0024014b1 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index 309272f8f103..83511c022926 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_fcoe.c b/drivers/net/ixgbe/ixgbe_fcoe.c
index c54a88274d51..27203c87ea14 100644
--- a/drivers/net/ixgbe/ixgbe_fcoe.c
+++ b/drivers/net/ixgbe/ixgbe_fcoe.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_fcoe.h b/drivers/net/ixgbe/ixgbe_fcoe.h
index 65cc8fb14fe7..02a00d2415d9 100644
--- a/drivers/net/ixgbe/ixgbe_fcoe.h
+++ b/drivers/net/ixgbe/ixgbe_fcoe.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index f0d0c5aad2b4..32231ffe0717 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -54,7 +54,8 @@ static const char ixgbe_driver_string[] =
54 54
55#define DRV_VERSION "3.2.9-k2" 55#define DRV_VERSION "3.2.9-k2"
56const char ixgbe_driver_version[] = DRV_VERSION; 56const char ixgbe_driver_version[] = DRV_VERSION;
57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation."; 57static const char ixgbe_copyright[] =
58 "Copyright (c) 1999-2011 Intel Corporation.";
58 59
59static const struct ixgbe_info *ixgbe_info_tbl[] = { 60static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info, 61 [board_82598] = &ixgbe_82598_info,
@@ -2597,6 +2598,11 @@ static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2597 2598
2598 i--; 2599 i--;
2599 for (; i >= 0; i--) { 2600 for (; i >= 0; i--) {
2601 /* free only the irqs that were actually requested */
2602 if (!adapter->q_vector[i]->rxr_count &&
2603 !adapter->q_vector[i]->txr_count)
2604 continue;
2605
2600 free_irq(adapter->msix_entries[i].vector, 2606 free_irq(adapter->msix_entries[i].vector,
2601 adapter->q_vector[i]); 2607 adapter->q_vector[i]);
2602 } 2608 }
@@ -3884,7 +3890,7 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3884 * If we're not hot-pluggable SFP+, we just need to configure link 3890 * If we're not hot-pluggable SFP+, we just need to configure link
3885 * and bring it up. 3891 * and bring it up.
3886 */ 3892 */
3887 if (hw->phy.type == ixgbe_phy_unknown) 3893 if (hw->phy.type == ixgbe_phy_none)
3888 schedule_work(&adapter->sfp_config_module_task); 3894 schedule_work(&adapter->sfp_config_module_task);
3889 3895
3890 /* enable transmits */ 3896 /* enable transmits */
diff --git a/drivers/net/ixgbe/ixgbe_mbx.c b/drivers/net/ixgbe/ixgbe_mbx.c
index f215c4c296c4..2acacfa5e375 100644
--- a/drivers/net/ixgbe/ixgbe_mbx.c
+++ b/drivers/net/ixgbe/ixgbe_mbx.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_mbx.h b/drivers/net/ixgbe/ixgbe_mbx.h
index ada0ce32a7a6..fe6ea81dc7f8 100644
--- a/drivers/net/ixgbe/ixgbe_mbx.h
+++ b/drivers/net/ixgbe/ixgbe_mbx.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 8f7123e8fc0a..197230b2d1ac 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -138,17 +138,51 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
138 **/ 138 **/
139s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 139s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
140{ 140{
141 u32 i;
142 u16 ctrl = 0;
143 s32 status = 0;
144
145 if (hw->phy.type == ixgbe_phy_unknown)
146 status = ixgbe_identify_phy_generic(hw);
147
148 if (status != 0 || hw->phy.type == ixgbe_phy_none)
149 goto out;
150
141 /* Don't reset PHY if it's shut down due to overtemp. */ 151 /* Don't reset PHY if it's shut down due to overtemp. */
142 if (!hw->phy.reset_if_overtemp && 152 if (!hw->phy.reset_if_overtemp &&
143 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 153 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
144 return 0; 154 goto out;
145 155
146 /* 156 /*
147 * Perform soft PHY reset to the PHY_XS. 157 * Perform soft PHY reset to the PHY_XS.
148 * This will cause a soft reset to the PHY 158 * This will cause a soft reset to the PHY
149 */ 159 */
150 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 160 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
151 MDIO_CTRL1_RESET); 161 MDIO_MMD_PHYXS,
162 MDIO_CTRL1_RESET);
163
164 /*
165 * Poll for reset bit to self-clear indicating reset is complete.
166 * Some PHYs could take up to 3 seconds to complete and need about
167 * 1.7 usec delay after the reset is complete.
168 */
169 for (i = 0; i < 30; i++) {
170 msleep(100);
171 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
172 MDIO_MMD_PHYXS, &ctrl);
173 if (!(ctrl & MDIO_CTRL1_RESET)) {
174 udelay(2);
175 break;
176 }
177 }
178
179 if (ctrl & MDIO_CTRL1_RESET) {
180 status = IXGBE_ERR_RESET_FAILED;
181 hw_dbg(hw, "PHY reset polling failed to complete.\n");
182 }
183
184out:
185 return status;
152} 186}
153 187
154/** 188/**
@@ -171,7 +205,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
171 else 205 else
172 gssr = IXGBE_GSSR_PHY0_SM; 206 gssr = IXGBE_GSSR_PHY0_SM;
173 207
174 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) 208 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
175 status = IXGBE_ERR_SWFW_SYNC; 209 status = IXGBE_ERR_SWFW_SYNC;
176 210
177 if (status == 0) { 211 if (status == 0) {
@@ -243,7 +277,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
243 } 277 }
244 } 278 }
245 279
246 ixgbe_release_swfw_sync(hw, gssr); 280 hw->mac.ops.release_swfw_sync(hw, gssr);
247 } 281 }
248 282
249 return status; 283 return status;
@@ -269,7 +303,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
269 else 303 else
270 gssr = IXGBE_GSSR_PHY0_SM; 304 gssr = IXGBE_GSSR_PHY0_SM;
271 305
272 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) 306 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
273 status = IXGBE_ERR_SWFW_SYNC; 307 status = IXGBE_ERR_SWFW_SYNC;
274 308
275 if (status == 0) { 309 if (status == 0) {
@@ -336,7 +370,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
336 } 370 }
337 } 371 }
338 372
339 ixgbe_release_swfw_sync(hw, gssr); 373 hw->mac.ops.release_swfw_sync(hw, gssr);
340 } 374 }
341 375
342 return status; 376 return status;
@@ -556,11 +590,10 @@ out:
556} 590}
557 591
558/** 592/**
559 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns 593 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
560 * the PHY type.
561 * @hw: pointer to hardware structure 594 * @hw: pointer to hardware structure
562 * 595 *
563 * Searches for and indentifies the SFP module. Assings appropriate PHY type. 596 * Searches for and identifies the SFP module and assigns appropriate PHY type.
564 **/ 597 **/
565s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 598s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
566{ 599{
@@ -581,41 +614,62 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
581 goto out; 614 goto out;
582 } 615 }
583 616
584 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 617 status = hw->phy.ops.read_i2c_eeprom(hw,
618 IXGBE_SFF_IDENTIFIER,
585 &identifier); 619 &identifier);
586 620
587 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 621 if (status == IXGBE_ERR_SWFW_SYNC ||
588 status = IXGBE_ERR_SFP_NOT_PRESENT; 622 status == IXGBE_ERR_I2C ||
589 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 623 status == IXGBE_ERR_SFP_NOT_PRESENT)
590 if (hw->phy.type != ixgbe_phy_nl) { 624 goto err_read_i2c_eeprom;
591 hw->phy.id = 0;
592 hw->phy.type = ixgbe_phy_unknown;
593 }
594 goto out;
595 }
596 625
597 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { 626 /* LAN ID is needed for sfp_type determination */
598 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 627 hw->mac.ops.set_lan_id(hw);
599 &comp_codes_1g); 628
600 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 629 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
601 &comp_codes_10g); 630 hw->phy.type = ixgbe_phy_sfp_unsupported;
602 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, 631 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
603 &cable_tech); 632 } else {
604 633 status = hw->phy.ops.read_i2c_eeprom(hw,
605 /* ID Module 634 IXGBE_SFF_1GBE_COMP_CODES,
606 * ========= 635 &comp_codes_1g);
607 * 0 SFP_DA_CU 636
608 * 1 SFP_SR 637 if (status == IXGBE_ERR_SWFW_SYNC ||
609 * 2 SFP_LR 638 status == IXGBE_ERR_I2C ||
610 * 3 SFP_DA_CORE0 - 82599-specific 639 status == IXGBE_ERR_SFP_NOT_PRESENT)
611 * 4 SFP_DA_CORE1 - 82599-specific 640 goto err_read_i2c_eeprom;
612 * 5 SFP_SR/LR_CORE0 - 82599-specific 641
613 * 6 SFP_SR/LR_CORE1 - 82599-specific 642 status = hw->phy.ops.read_i2c_eeprom(hw,
614 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 643 IXGBE_SFF_10GBE_COMP_CODES,
615 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 644 &comp_codes_10g);
616 * 9 SFP_1g_cu_CORE0 - 82599-specific 645
617 * 10 SFP_1g_cu_CORE1 - 82599-specific 646 if (status == IXGBE_ERR_SWFW_SYNC ||
618 */ 647 status == IXGBE_ERR_I2C ||
648 status == IXGBE_ERR_SFP_NOT_PRESENT)
649 goto err_read_i2c_eeprom;
650 status = hw->phy.ops.read_i2c_eeprom(hw,
651 IXGBE_SFF_CABLE_TECHNOLOGY,
652 &cable_tech);
653
654 if (status == IXGBE_ERR_SWFW_SYNC ||
655 status == IXGBE_ERR_I2C ||
656 status == IXGBE_ERR_SFP_NOT_PRESENT)
657 goto err_read_i2c_eeprom;
658
659 /* ID Module
660 * =========
661 * 0 SFP_DA_CU
662 * 1 SFP_SR
663 * 2 SFP_LR
664 * 3 SFP_DA_CORE0 - 82599-specific
665 * 4 SFP_DA_CORE1 - 82599-specific
666 * 5 SFP_SR/LR_CORE0 - 82599-specific
667 * 6 SFP_SR/LR_CORE1 - 82599-specific
668 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
669 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
670 * 9 SFP_1g_cu_CORE0 - 82599-specific
671 * 10 SFP_1g_cu_CORE1 - 82599-specific
672 */
619 if (hw->mac.type == ixgbe_mac_82598EB) { 673 if (hw->mac.type == ixgbe_mac_82598EB) {
620 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 674 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
621 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 675 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
@@ -647,31 +701,27 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
647 ixgbe_sfp_type_da_act_lmt_core1; 701 ixgbe_sfp_type_da_act_lmt_core1;
648 } else { 702 } else {
649 hw->phy.sfp_type = 703 hw->phy.sfp_type =
650 ixgbe_sfp_type_unknown; 704 ixgbe_sfp_type_unknown;
651 } 705 }
652 } else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 706 } else if (comp_codes_10g &
707 (IXGBE_SFF_10GBASESR_CAPABLE |
708 IXGBE_SFF_10GBASELR_CAPABLE)) {
653 if (hw->bus.lan_id == 0) 709 if (hw->bus.lan_id == 0)
654 hw->phy.sfp_type = 710 hw->phy.sfp_type =
655 ixgbe_sfp_type_srlr_core0; 711 ixgbe_sfp_type_srlr_core0;
656 else 712 else
657 hw->phy.sfp_type = 713 hw->phy.sfp_type =
658 ixgbe_sfp_type_srlr_core1; 714 ixgbe_sfp_type_srlr_core1;
659 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 715 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
660 if (hw->bus.lan_id == 0)
661 hw->phy.sfp_type =
662 ixgbe_sfp_type_srlr_core0;
663 else
664 hw->phy.sfp_type =
665 ixgbe_sfp_type_srlr_core1;
666 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
667 if (hw->bus.lan_id == 0) 716 if (hw->bus.lan_id == 0)
668 hw->phy.sfp_type = 717 hw->phy.sfp_type =
669 ixgbe_sfp_type_1g_cu_core0; 718 ixgbe_sfp_type_1g_cu_core0;
670 else 719 else
671 hw->phy.sfp_type = 720 hw->phy.sfp_type =
672 ixgbe_sfp_type_1g_cu_core1; 721 ixgbe_sfp_type_1g_cu_core1;
673 else 722 } else {
674 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 723 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
724 }
675 } 725 }
676 726
677 if (hw->phy.sfp_type != stored_sfp_type) 727 if (hw->phy.sfp_type != stored_sfp_type)
@@ -688,16 +738,33 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
688 /* Determine PHY vendor */ 738 /* Determine PHY vendor */
689 if (hw->phy.type != ixgbe_phy_nl) { 739 if (hw->phy.type != ixgbe_phy_nl) {
690 hw->phy.id = identifier; 740 hw->phy.id = identifier;
691 hw->phy.ops.read_i2c_eeprom(hw, 741 status = hw->phy.ops.read_i2c_eeprom(hw,
692 IXGBE_SFF_VENDOR_OUI_BYTE0, 742 IXGBE_SFF_VENDOR_OUI_BYTE0,
693 &oui_bytes[0]); 743 &oui_bytes[0]);
694 hw->phy.ops.read_i2c_eeprom(hw, 744
745 if (status == IXGBE_ERR_SWFW_SYNC ||
746 status == IXGBE_ERR_I2C ||
747 status == IXGBE_ERR_SFP_NOT_PRESENT)
748 goto err_read_i2c_eeprom;
749
750 status = hw->phy.ops.read_i2c_eeprom(hw,
695 IXGBE_SFF_VENDOR_OUI_BYTE1, 751 IXGBE_SFF_VENDOR_OUI_BYTE1,
696 &oui_bytes[1]); 752 &oui_bytes[1]);
697 hw->phy.ops.read_i2c_eeprom(hw, 753
754 if (status == IXGBE_ERR_SWFW_SYNC ||
755 status == IXGBE_ERR_I2C ||
756 status == IXGBE_ERR_SFP_NOT_PRESENT)
757 goto err_read_i2c_eeprom;
758
759 status = hw->phy.ops.read_i2c_eeprom(hw,
698 IXGBE_SFF_VENDOR_OUI_BYTE2, 760 IXGBE_SFF_VENDOR_OUI_BYTE2,
699 &oui_bytes[2]); 761 &oui_bytes[2]);
700 762
763 if (status == IXGBE_ERR_SWFW_SYNC ||
764 status == IXGBE_ERR_I2C ||
765 status == IXGBE_ERR_SFP_NOT_PRESENT)
766 goto err_read_i2c_eeprom;
767
701 vendor_oui = 768 vendor_oui =
702 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 769 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
703 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 770 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
@@ -707,7 +774,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
707 case IXGBE_SFF_VENDOR_OUI_TYCO: 774 case IXGBE_SFF_VENDOR_OUI_TYCO:
708 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 775 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
709 hw->phy.type = 776 hw->phy.type =
710 ixgbe_phy_sfp_passive_tyco; 777 ixgbe_phy_sfp_passive_tyco;
711 break; 778 break;
712 case IXGBE_SFF_VENDOR_OUI_FTL: 779 case IXGBE_SFF_VENDOR_OUI_FTL:
713 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 780 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
@@ -724,7 +791,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
724 default: 791 default:
725 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 792 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
726 hw->phy.type = 793 hw->phy.type =
727 ixgbe_phy_sfp_passive_unknown; 794 ixgbe_phy_sfp_passive_unknown;
728 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 795 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
729 hw->phy.type = 796 hw->phy.type =
730 ixgbe_phy_sfp_active_unknown; 797 ixgbe_phy_sfp_active_unknown;
@@ -734,7 +801,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
734 } 801 }
735 } 802 }
736 803
737 /* All passive DA cables are supported */ 804 /* Allow any DA cable vendor */
738 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 805 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
739 IXGBE_SFF_DA_ACTIVE_CABLE)) { 806 IXGBE_SFF_DA_ACTIVE_CABLE)) {
740 status = 0; 807 status = 0;
@@ -776,15 +843,24 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
776 843
777out: 844out:
778 return status; 845 return status;
846
847err_read_i2c_eeprom:
848 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
849 if (hw->phy.type != ixgbe_phy_nl) {
850 hw->phy.id = 0;
851 hw->phy.type = ixgbe_phy_unknown;
852 }
853 return IXGBE_ERR_SFP_NOT_PRESENT;
779} 854}
780 855
781/** 856/**
782 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see 857 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
783 * if it supports a given SFP+ module type, if so it returns the offsets to the
784 * phy init sequence block.
785 * @hw: pointer to hardware structure 858 * @hw: pointer to hardware structure
786 * @list_offset: offset to the SFP ID list 859 * @list_offset: offset to the SFP ID list
787 * @data_offset: offset to the SFP data block 860 * @data_offset: offset to the SFP data block
861 *
862 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
863 * so it returns the offsets to the phy init sequence block.
788 **/ 864 **/
789s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 865s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
790 u16 *list_offset, 866 u16 *list_offset,
@@ -899,11 +975,22 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
899 u8 dev_addr, u8 *data) 975 u8 dev_addr, u8 *data)
900{ 976{
901 s32 status = 0; 977 s32 status = 0;
902 u32 max_retry = 1; 978 u32 max_retry = 10;
903 u32 retry = 0; 979 u32 retry = 0;
980 u16 swfw_mask = 0;
904 bool nack = 1; 981 bool nack = 1;
905 982
983 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
984 swfw_mask = IXGBE_GSSR_PHY1_SM;
985 else
986 swfw_mask = IXGBE_GSSR_PHY0_SM;
987
906 do { 988 do {
989 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
990 status = IXGBE_ERR_SWFW_SYNC;
991 goto read_byte_out;
992 }
993
907 ixgbe_i2c_start(hw); 994 ixgbe_i2c_start(hw);
908 995
909 /* Device Address and write indication */ 996 /* Device Address and write indication */
@@ -946,6 +1033,8 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
946 break; 1033 break;
947 1034
948fail: 1035fail:
1036 ixgbe_release_swfw_sync(hw, swfw_mask);
1037 msleep(100);
949 ixgbe_i2c_bus_clear(hw); 1038 ixgbe_i2c_bus_clear(hw);
950 retry++; 1039 retry++;
951 if (retry < max_retry) 1040 if (retry < max_retry)
@@ -955,6 +1044,9 @@ fail:
955 1044
956 } while (retry < max_retry); 1045 } while (retry < max_retry);
957 1046
1047 ixgbe_release_swfw_sync(hw, swfw_mask);
1048
1049read_byte_out:
958 return status; 1050 return status;
959} 1051}
960 1052
@@ -973,6 +1065,17 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
973 s32 status = 0; 1065 s32 status = 0;
974 u32 max_retry = 1; 1066 u32 max_retry = 1;
975 u32 retry = 0; 1067 u32 retry = 0;
1068 u16 swfw_mask = 0;
1069
1070 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1071 swfw_mask = IXGBE_GSSR_PHY1_SM;
1072 else
1073 swfw_mask = IXGBE_GSSR_PHY0_SM;
1074
1075 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
1076 status = IXGBE_ERR_SWFW_SYNC;
1077 goto write_byte_out;
1078 }
976 1079
977 do { 1080 do {
978 ixgbe_i2c_start(hw); 1081 ixgbe_i2c_start(hw);
@@ -1013,6 +1116,9 @@ fail:
1013 hw_dbg(hw, "I2C byte write error.\n"); 1116 hw_dbg(hw, "I2C byte write error.\n");
1014 } while (retry < max_retry); 1117 } while (retry < max_retry);
1015 1118
1119 ixgbe_release_swfw_sync(hw, swfw_mask);
1120
1121write_byte_out:
1016 return status; 1122 return status;
1017} 1123}
1018 1124
@@ -1331,6 +1437,8 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1331 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1437 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1332 u32 i; 1438 u32 i;
1333 1439
1440 ixgbe_i2c_start(hw);
1441
1334 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1442 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1335 1443
1336 for (i = 0; i < 9; i++) { 1444 for (i = 0; i < 9; i++) {
@@ -1345,6 +1453,8 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1345 udelay(IXGBE_I2C_T_LOW); 1453 udelay(IXGBE_I2C_T_LOW);
1346 } 1454 }
1347 1455
1456 ixgbe_i2c_start(hw);
1457
1348 /* Put the i2c bus back to default state */ 1458 /* Put the i2c bus back to default state */
1349 ixgbe_i2c_stop(hw); 1459 ixgbe_i2c_stop(hw);
1350} 1460}
diff --git a/drivers/net/ixgbe/ixgbe_phy.h b/drivers/net/ixgbe/ixgbe_phy.h
index e2c6b7eac641..2327baf04426 100644
--- a/drivers/net/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ixgbe/ixgbe_phy.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_sriov.c b/drivers/net/ixgbe/ixgbe_sriov.c
index fb4868d0a32d..58c9b45989ff 100644
--- a/drivers/net/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ixgbe/ixgbe_sriov.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_sriov.h b/drivers/net/ixgbe/ixgbe_sriov.h
index 49dc14debef7..e7dd029d576a 100644
--- a/drivers/net/ixgbe/ixgbe_sriov.h
+++ b/drivers/net/ixgbe/ixgbe_sriov.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index ab65d13969fd..013751db5fc0 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -91,7 +91,7 @@
91 91
92/* General Receive Control */ 92/* General Receive Control */
93#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 93#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
94#define IXGBE_GRC_APME 0x00000002 /* Advanced Power Management Enable */ 94#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
95 95
96#define IXGBE_VPDDIAG0 0x10204 96#define IXGBE_VPDDIAG0 0x10204
97#define IXGBE_VPDDIAG1 0x10208 97#define IXGBE_VPDDIAG1 0x10208
@@ -342,7 +342,7 @@
342/* Wake Up Control */ 342/* Wake Up Control */
343#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 343#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
344#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 344#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
345#define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/ 345#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
346 346
347/* Wake Up Filter Control */ 347/* Wake Up Filter Control */
348#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 348#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
@@ -1614,6 +1614,8 @@
1614#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */ 1614#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1615 1615
1616/* PCI Bus Info */ 1616/* PCI Bus Info */
1617#define IXGBE_PCI_DEVICE_STATUS 0xAA
1618#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
1617#define IXGBE_PCI_LINK_STATUS 0xB2 1619#define IXGBE_PCI_LINK_STATUS 0xB2
1618#define IXGBE_PCI_DEVICE_CONTROL2 0xC8 1620#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1619#define IXGBE_PCI_LINK_WIDTH 0x3F0 1621#define IXGBE_PCI_LINK_WIDTH 0x3F0
@@ -2242,6 +2244,7 @@ enum ixgbe_mac_type {
2242 2244
2243enum ixgbe_phy_type { 2245enum ixgbe_phy_type {
2244 ixgbe_phy_unknown = 0, 2246 ixgbe_phy_unknown = 0,
2247 ixgbe_phy_none,
2245 ixgbe_phy_tn, 2248 ixgbe_phy_tn,
2246 ixgbe_phy_aq, 2249 ixgbe_phy_aq,
2247 ixgbe_phy_cu_unknown, 2250 ixgbe_phy_cu_unknown,
@@ -2330,32 +2333,31 @@ enum ixgbe_bus_type {
2330/* PCI bus speeds */ 2333/* PCI bus speeds */
2331enum ixgbe_bus_speed { 2334enum ixgbe_bus_speed {
2332 ixgbe_bus_speed_unknown = 0, 2335 ixgbe_bus_speed_unknown = 0,
2333 ixgbe_bus_speed_33, 2336 ixgbe_bus_speed_33 = 33,
2334 ixgbe_bus_speed_66, 2337 ixgbe_bus_speed_66 = 66,
2335 ixgbe_bus_speed_100, 2338 ixgbe_bus_speed_100 = 100,
2336 ixgbe_bus_speed_120, 2339 ixgbe_bus_speed_120 = 120,
2337 ixgbe_bus_speed_133, 2340 ixgbe_bus_speed_133 = 133,
2338 ixgbe_bus_speed_2500, 2341 ixgbe_bus_speed_2500 = 2500,
2339 ixgbe_bus_speed_5000, 2342 ixgbe_bus_speed_5000 = 5000,
2340 ixgbe_bus_speed_reserved 2343 ixgbe_bus_speed_reserved
2341}; 2344};
2342 2345
2343/* PCI bus widths */ 2346/* PCI bus widths */
2344enum ixgbe_bus_width { 2347enum ixgbe_bus_width {
2345 ixgbe_bus_width_unknown = 0, 2348 ixgbe_bus_width_unknown = 0,
2346 ixgbe_bus_width_pcie_x1, 2349 ixgbe_bus_width_pcie_x1 = 1,
2347 ixgbe_bus_width_pcie_x2, 2350 ixgbe_bus_width_pcie_x2 = 2,
2348 ixgbe_bus_width_pcie_x4 = 4, 2351 ixgbe_bus_width_pcie_x4 = 4,
2349 ixgbe_bus_width_pcie_x8 = 8, 2352 ixgbe_bus_width_pcie_x8 = 8,
2350 ixgbe_bus_width_32, 2353 ixgbe_bus_width_32 = 32,
2351 ixgbe_bus_width_64, 2354 ixgbe_bus_width_64 = 64,
2352 ixgbe_bus_width_reserved 2355 ixgbe_bus_width_reserved
2353}; 2356};
2354 2357
2355struct ixgbe_addr_filter_info { 2358struct ixgbe_addr_filter_info {
2356 u32 num_mc_addrs; 2359 u32 num_mc_addrs;
2357 u32 rar_used_count; 2360 u32 rar_used_count;
2358 u32 mc_addr_in_rar_count;
2359 u32 mta_in_use; 2361 u32 mta_in_use;
2360 u32 overflow_promisc; 2362 u32 overflow_promisc;
2361 bool uc_set_promisc; 2363 bool uc_set_promisc;
@@ -2493,6 +2495,8 @@ struct ixgbe_mac_operations {
2493 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 2495 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2494 s32 (*setup_sfp)(struct ixgbe_hw *); 2496 s32 (*setup_sfp)(struct ixgbe_hw *);
2495 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 2497 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2498 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2499 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2496 2500
2497 /* Link */ 2501 /* Link */
2498 void (*disable_tx_laser)(struct ixgbe_hw *); 2502 void (*disable_tx_laser)(struct ixgbe_hw *);
@@ -2515,7 +2519,6 @@ struct ixgbe_mac_operations {
2515 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 2519 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2516 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 2520 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2517 s32 (*init_rx_addrs)(struct ixgbe_hw *); 2521 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2518 s32 (*update_uc_addr_list)(struct ixgbe_hw *, struct net_device *);
2519 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *); 2522 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
2520 s32 (*enable_mc)(struct ixgbe_hw *); 2523 s32 (*enable_mc)(struct ixgbe_hw *);
2521 s32 (*disable_mc)(struct ixgbe_hw *); 2524 s32 (*disable_mc)(struct ixgbe_hw *);
@@ -2556,6 +2559,7 @@ struct ixgbe_eeprom_info {
2556 u16 address_bits; 2559 u16 address_bits;
2557}; 2560};
2558 2561
2562#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
2559struct ixgbe_mac_info { 2563struct ixgbe_mac_info {
2560 struct ixgbe_mac_operations ops; 2564 struct ixgbe_mac_operations ops;
2561 enum ixgbe_mac_type type; 2565 enum ixgbe_mac_type type;
@@ -2566,6 +2570,8 @@ struct ixgbe_mac_info {
2566 u16 wwnn_prefix; 2570 u16 wwnn_prefix;
2567 /* prefix for World Wide Port Name (WWPN) */ 2571 /* prefix for World Wide Port Name (WWPN) */
2568 u16 wwpn_prefix; 2572 u16 wwpn_prefix;
2573#define IXGBE_MAX_MTA 128
2574 u32 mta_shadow[IXGBE_MAX_MTA];
2569 s32 mc_filter_type; 2575 s32 mc_filter_type;
2570 u32 mcft_size; 2576 u32 mcft_size;
2571 u32 vft_size; 2577 u32 vft_size;
@@ -2578,6 +2584,7 @@ struct ixgbe_mac_info {
2578 u32 orig_autoc2; 2584 u32 orig_autoc2;
2579 bool orig_link_settings_stored; 2585 bool orig_link_settings_stored;
2580 bool autotry_restart; 2586 bool autotry_restart;
2587 u8 flags;
2581}; 2588};
2582 2589
2583struct ixgbe_phy_info { 2590struct ixgbe_phy_info {
@@ -2684,7 +2691,6 @@ struct ixgbe_info {
2684#define IXGBE_ERR_EEPROM_VERSION -24 2691#define IXGBE_ERR_EEPROM_VERSION -24
2685#define IXGBE_ERR_NO_SPACE -25 2692#define IXGBE_ERR_NO_SPACE -25
2686#define IXGBE_ERR_OVERTEMP -26 2693#define IXGBE_ERR_OVERTEMP -26
2687#define IXGBE_ERR_RAR_INDEX -27
2688#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 2694#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
2689#define IXGBE_ERR_PBA_SECTION -31 2695#define IXGBE_ERR_PBA_SECTION -31
2690#define IXGBE_ERR_INVALID_ARGUMENT -32 2696#define IXGBE_ERR_INVALID_ARGUMENT -32
diff --git a/drivers/net/ixgbe/ixgbe_x540.c b/drivers/net/ixgbe/ixgbe_x540.c
index f2518b01067d..2e3a2b4fa8b2 100644
--- a/drivers/net/ixgbe/ixgbe_x540.c
+++ b/drivers/net/ixgbe/ixgbe_x540.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -31,7 +31,6 @@
31 31
32#include "ixgbe.h" 32#include "ixgbe.h"
33#include "ixgbe_phy.h" 33#include "ixgbe_phy.h"
34//#include "ixgbe_mbx.h"
35 34
36#define IXGBE_X540_MAX_TX_QUEUES 128 35#define IXGBE_X540_MAX_TX_QUEUES 128
37#define IXGBE_X540_MAX_RX_QUEUES 128 36#define IXGBE_X540_MAX_RX_QUEUES 128
@@ -110,12 +109,9 @@ static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
110 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 109 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
111 * access and verify no pending requests before reset 110 * access and verify no pending requests before reset
112 */ 111 */
113 status = ixgbe_disable_pcie_master(hw); 112 ixgbe_disable_pcie_master(hw);
114 if (status != 0) {
115 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
116 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
117 }
118 113
114mac_reset_top:
119 /* 115 /*
120 * Issue global reset to the MAC. Needs to be SW reset if link is up. 116 * Issue global reset to the MAC. Needs to be SW reset if link is up.
121 * If link reset is used when link is up, it might reset the PHY when 117 * If link reset is used when link is up, it might reset the PHY when
@@ -148,6 +144,19 @@ static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
148 hw_dbg(hw, "Reset polling failed to complete.\n"); 144 hw_dbg(hw, "Reset polling failed to complete.\n");
149 } 145 }
150 146
147 /*
148 * Double resets are required for recovery from certain error
149 * conditions. Between resets, it is necessary to stall to allow time
150 * for any pending HW events to complete. We use 1usec since that is
151 * what is needed for ixgbe_disable_pcie_master(). The second reset
152 * then clears out any effects of those events.
153 */
154 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
155 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
156 udelay(1);
157 goto mac_reset_top;
158 }
159
151 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */ 160 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
152 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 161 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
153 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 162 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
@@ -191,7 +200,7 @@ static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
191 * clear the multicast table. Also reset num_rar_entries to 128, 200 * clear the multicast table. Also reset num_rar_entries to 128,
192 * since we modify this value when programming the SAN MAC address. 201 * since we modify this value when programming the SAN MAC address.
193 */ 202 */
194 hw->mac.num_rar_entries = 128; 203 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
195 hw->mac.ops.init_rx_addrs(hw); 204 hw->mac.ops.init_rx_addrs(hw);
196 205
197 /* Store the permanent mac address */ 206 /* Store the permanent mac address */
@@ -278,7 +287,7 @@ static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
278{ 287{
279 s32 status; 288 s32 status;
280 289
281 if (ixgbe_acquire_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM) == 0) 290 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0)
282 status = ixgbe_read_eerd_generic(hw, offset, data); 291 status = ixgbe_read_eerd_generic(hw, offset, data);
283 else 292 else
284 status = IXGBE_ERR_SWFW_SYNC; 293 status = IXGBE_ERR_SWFW_SYNC;
@@ -311,7 +320,7 @@ static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
311 (data << IXGBE_EEPROM_RW_REG_DATA) | 320 (data << IXGBE_EEPROM_RW_REG_DATA) |
312 IXGBE_EEPROM_RW_REG_START; 321 IXGBE_EEPROM_RW_REG_START;
313 322
314 if (ixgbe_acquire_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM) == 0) { 323 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
315 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 324 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
316 if (status != 0) { 325 if (status != 0) {
317 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 326 hw_dbg(hw, "Eeprom write EEWR timed out\n");
@@ -676,7 +685,6 @@ static struct ixgbe_mac_operations mac_ops_X540 = {
676 .set_vmdq = &ixgbe_set_vmdq_generic, 685 .set_vmdq = &ixgbe_set_vmdq_generic,
677 .clear_vmdq = &ixgbe_clear_vmdq_generic, 686 .clear_vmdq = &ixgbe_clear_vmdq_generic,
678 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 687 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
679 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
680 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 688 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
681 .enable_mc = &ixgbe_enable_mc_generic, 689 .enable_mc = &ixgbe_enable_mc_generic,
682 .disable_mc = &ixgbe_disable_mc_generic, 690 .disable_mc = &ixgbe_disable_mc_generic,
@@ -687,6 +695,8 @@ static struct ixgbe_mac_operations mac_ops_X540 = {
687 .setup_sfp = NULL, 695 .setup_sfp = NULL,
688 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 696 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
689 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 697 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
698 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
699 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
690}; 700};
691 701
692static struct ixgbe_eeprom_operations eeprom_ops_X540 = { 702static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
@@ -702,7 +712,7 @@ static struct ixgbe_phy_operations phy_ops_X540 = {
702 .identify = &ixgbe_identify_phy_generic, 712 .identify = &ixgbe_identify_phy_generic,
703 .identify_sfp = &ixgbe_identify_sfp_module_generic, 713 .identify_sfp = &ixgbe_identify_sfp_module_generic,
704 .init = NULL, 714 .init = NULL,
705 .reset = &ixgbe_reset_phy_generic, 715 .reset = NULL,
706 .read_reg = &ixgbe_read_phy_reg_generic, 716 .read_reg = &ixgbe_read_phy_reg_generic,
707 .write_reg = &ixgbe_write_phy_reg_generic, 717 .write_reg = &ixgbe_write_phy_reg_generic,
708 .setup_link = &ixgbe_setup_phy_link_generic, 718 .setup_link = &ixgbe_setup_phy_link_generic,
diff --git a/drivers/net/ixgbevf/ixgbevf_main.c b/drivers/net/ixgbevf/ixgbevf_main.c
index 1e735a14091c..82768812552d 100644
--- a/drivers/net/ixgbevf/ixgbevf_main.c
+++ b/drivers/net/ixgbevf/ixgbevf_main.c
@@ -178,8 +178,6 @@ static inline bool ixgbevf_check_tx_hang(struct ixgbevf_adapter *adapter,
178 tx_ring->tx_buffer_info[eop].time_stamp && 178 tx_ring->tx_buffer_info[eop].time_stamp &&
179 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ)) { 179 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ)) {
180 /* detected Tx unit hang */ 180 /* detected Tx unit hang */
181 union ixgbe_adv_tx_desc *tx_desc;
182 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
183 printk(KERN_ERR "Detected Tx Unit Hang\n" 181 printk(KERN_ERR "Detected Tx Unit Hang\n"
184 " Tx Queue <%d>\n" 182 " Tx Queue <%d>\n"
185 " TDH, TDT <%x>, <%x>\n" 183 " TDH, TDT <%x>, <%x>\n"
@@ -334,7 +332,6 @@ static void ixgbevf_receive_skb(struct ixgbevf_q_vector *q_vector,
334 struct ixgbevf_adapter *adapter = q_vector->adapter; 332 struct ixgbevf_adapter *adapter = q_vector->adapter;
335 bool is_vlan = (status & IXGBE_RXD_STAT_VP); 333 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
336 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); 334 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
337 int ret;
338 335
339 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { 336 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
340 if (adapter->vlgrp && is_vlan) 337 if (adapter->vlgrp && is_vlan)
@@ -345,9 +342,9 @@ static void ixgbevf_receive_skb(struct ixgbevf_q_vector *q_vector,
345 napi_gro_receive(&q_vector->napi, skb); 342 napi_gro_receive(&q_vector->napi, skb);
346 } else { 343 } else {
347 if (adapter->vlgrp && is_vlan) 344 if (adapter->vlgrp && is_vlan)
348 ret = vlan_hwaccel_rx(skb, adapter->vlgrp, tag); 345 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
349 else 346 else
350 ret = netif_rx(skb); 347 netif_rx(skb);
351 } 348 }
352} 349}
353 350
@@ -3287,8 +3284,6 @@ static const struct net_device_ops ixgbe_netdev_ops = {
3287 3284
3288static void ixgbevf_assign_netdev_ops(struct net_device *dev) 3285static void ixgbevf_assign_netdev_ops(struct net_device *dev)
3289{ 3286{
3290 struct ixgbevf_adapter *adapter;
3291 adapter = netdev_priv(dev);
3292 dev->netdev_ops = &ixgbe_netdev_ops; 3287 dev->netdev_ops = &ixgbe_netdev_ops;
3293 ixgbevf_set_ethtool_ops(dev); 3288 ixgbevf_set_ethtool_ops(dev);
3294 dev->watchdog_timeo = 5 * HZ; 3289 dev->watchdog_timeo = 5 * HZ;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 00:06:24 -0400