Merge branch 'for_2.6.34_4f4e65_a' of git://git.pwsan.com/linux-2.6 into omap-for-linus

55 files changed, 5113 insertions, 3755 deletions

diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 04f1d29cba2c..3e052f6532b1 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -52,12 +52,6 @@ const struct clkops clkops_dummy = {
         .disable        = clk_omap1_dummy_disable,
 };
 
-/* XXX can be replaced with a fixed_divisor_recalc */
-unsigned long omap1_watchdog_recalc(struct clk *clk)
-{
-        return clk->parent->rate / 14;
-}
-
 unsigned long omap1_uart_recalc(struct clk *clk)
 {
         unsigned int val = __raw_readl(clk->enable_reg);
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 65e7b5b85d83..edefb3440d30 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -149,7 +149,8 @@ static struct arm_idlect1_clk armwdt_ck = {
                 .flags          = CLOCK_IDLE_CONTROL,
                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
                 .enable_bit     = EN_WDTCK,
-                .recalc         = &omap1_watchdog_recalc,
+                .fixed_div      = 14,
+                .recalc         = &omap_fixed_divisor_recalc,
         },
         .idlect_shift   = 0,
 };
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b32678b848bc..34c2867e0f63 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,14 +6,22 @@
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
 
 omap-2-3-common                         = irq.o sdrc.o omap_hwmod.o
-omap-3-4-common                         = dpll.o
+omap-3-4-common                         = dpll3xxx.o
 prcm-common                             = prcm.o powerdomain.o
-clock-common                            = clock.o clock_common_data.o clockdomain.o
-
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
+clock-common                            = clock.o clock_common_data.o \
+                                          clockdomain.o clkt_dpll.o \
+                                          clkt_clksel.o
+clock-omap2xxx                          = clkt2xxx_dpllcore.o \
+                                          clkt2xxx_virt_prcm_set.o \
+                                          clkt2xxx_apll.o clkt2xxx_osc.o \
+                                          clkt2xxx_sys.o
+clock-omap3xxx                          = clkt34xx_dpll3m2.o
+
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
+                            $(clock-omap2xxx)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
-                            $(omap-3-4-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o
+                            $(omap-3-4-common) $(clock-omap3xxx)
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) $(clock-common)
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
new file mode 100644
index 000000000000..fc32ff8e790f
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -0,0 +1,120 @@
+/*
+ * OMAP2xxx APLL clock control functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/prcm.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED                 0
+#define EN_APLL_LOCKED                  3
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ             0
+#define APLLS_CLKIN_13MHZ               2
+#define APLLS_CLKIN_12MHZ               3
+
+/* Private functions */
+
+/* Enable an APLL if off */
+static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
+{
+        u32 cval, apll_mask;
+
+        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+        if ((cval & apll_mask) == apll_mask)
+                return 0;   /* apll already enabled */
+
+        cval &= ~apll_mask;
+        cval |= apll_mask;
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+
+        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
+                             clk->name);
+
+        /*
+         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+         * fails?
+         */
+        return 0;
+}
+
+static int omap2_clk_apll96_enable(struct clk *clk)
+{
+        return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
+}
+
+static int omap2_clk_apll54_enable(struct clk *clk)
+{
+        return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
+}
+
+/* Stop APLL */
+static void omap2_clk_apll_disable(struct clk *clk)
+{
+        u32 cval;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+}
+
+/* Public data */
+
+const struct clkops clkops_apll96 = {
+        .enable         = omap2_clk_apll96_enable,
+        .disable        = omap2_clk_apll_disable,
+};
+
+const struct clkops clkops_apll54 = {
+        .enable         = omap2_clk_apll54_enable,
+        .disable        = omap2_clk_apll_disable,
+};
+
+/* Public functions */
+
+u32 omap2xxx_get_apll_clkin(void)
+{
+        u32 aplls, srate = 0;
+
+        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
+
+        if (aplls == APLLS_CLKIN_19_2MHZ)
+                srate = 19200000;
+        else if (aplls == APLLS_CLKIN_13MHZ)
+                srate = 13000000;
+        else if (aplls == APLLS_CLKIN_12MHZ)
+                srate = 12000000;
+
+        return srate;
+}
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
new file mode 100644
index 000000000000..019048434f13
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -0,0 +1,173 @@
+/*
+ * DPLL + CORE_CLK composite clock functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX The DPLL and CORE clocks should be split into two separate clock
+ * types.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/sdrc.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
+
+/**
+ * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
+ * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
+ *
+ * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
+ * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
+ * (the latter is unusual).  This currently should be called with
+ * struct clk *dpll_ck, which is a composite clock of dpll_ck and
+ * core_ck.
+ */
+unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
+{
+        long long core_clk;
+        u32 v;
+
+        core_clk = omap2_get_dpll_rate(clk);
+
+        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        v &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (v == CORE_CLK_SRC_32K)
+                core_clk = 32768;
+        else
+                core_clk *= v;
+
+        return core_clk;
+}
+
+/*
+ * Uses the current prcm set to tell if a rate is valid.
+ * You can go slower, but not faster within a given rate set.
+ */
+static long omap2_dpllcore_round_rate(unsigned long target_rate)
+{
+        u32 high, low, core_clk_src;
+
+        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
+                high = curr_prcm_set->dpll_speed * 2;
+                low = curr_prcm_set->dpll_speed;
+        } else {                                /* DPLL clockout x 2 */
+                high = curr_prcm_set->dpll_speed;
+                low = curr_prcm_set->dpll_speed / 2;
+        }
+
+#ifdef DOWN_VARIABLE_DPLL
+        if (target_rate > high)
+                return high;
+        else
+                return target_rate;
+#else
+        if (target_rate > low)
+                return high;
+        else
+                return low;
+#endif
+
+}
+
+unsigned long omap2_dpllcore_recalc(struct clk *clk)
+{
+        return omap2xxx_clk_get_core_rate(clk);
+}
+
+int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, low, mult, div, valid_rate, done_rate;
+        u32 bypass = 0;
+        struct prcm_config tmpset;
+        const struct dpll_data *dd;
+
+        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if ((rate == (cur_rate / 2)) && (mult == 2)) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
+        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (rate != cur_rate) {
+                valid_rate = omap2_dpllcore_round_rate(rate);
+                if (valid_rate != rate)
+                        return -EINVAL;
+
+                if (mult == 1)
+                        low = curr_prcm_set->dpll_speed;
+                else
+                        low = curr_prcm_set->dpll_speed / 2;
+
+                dd = clk->dpll_data;
+                if (!dd)
+                        return -EINVAL;
+
+                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
+                                           dd->div1_mask);
+                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
+                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
+                if (rate > low) {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
+                        mult = ((rate / 2) / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                } else {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
+                        mult = (rate / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL;
+                }
+                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
+                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
+
+                /* Worst case */
+                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
+
+                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
+                        bypass = 1;
+
+                /* For omap2xxx_sdrc_init_params() */
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+
+                /* Force dll lock mode */
+                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
+                               bypass);
+
+                /* Errata: ret dll entry state */
+                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+                omap2xxx_sdrc_reprogram(done_rate, 0);
+        }
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
new file mode 100644
index 000000000000..2167be84a5bc
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -0,0 +1,62 @@
+/*
+ * OMAP2xxx osc_clk-specific clock code
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+
+static int omap2_enable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(prcm_clksrc_ctrl);
+
+        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+
+        return 0;
+}
+
+static void omap2_disable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(prcm_clksrc_ctrl);
+
+        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+}
+
+const struct clkops clkops_oscck = {
+        .enable         = omap2_enable_osc_ck,
+        .disable        = omap2_disable_osc_ck,
+};
+
+unsigned long omap2_osc_clk_recalc(struct clk *clk)
+{
+        return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
+}
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
new file mode 100644
index 000000000000..822b5a79f457
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -0,0 +1,50 @@
+/*
+ * OMAP2xxx sys_clk-specific clock code
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+
+void __iomem *prcm_clksrc_ctrl;
+
+u32 omap2xxx_get_sysclkdiv(void)
+{
+        u32 div;
+
+        div = __raw_readl(prcm_clksrc_ctrl);
+        div &= OMAP_SYSCLKDIV_MASK;
+        div >>= OMAP_SYSCLKDIV_SHIFT;
+
+        return div;
+}
+
+unsigned long omap2xxx_sys_clk_recalc(struct clk *clk)
+{
+        return clk->parent->rate / omap2xxx_get_sysclkdiv();
+}
+
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
new file mode 100644
index 000000000000..3b1eac4d5390
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -0,0 +1,254 @@
+/*
+ * OMAP2xxx DVFS virtual clock functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of this code should be replaceable by the upcoming OPP layer
+ * code.  However, some notion of "rate set" is probably still necessary
+ * for OMAP2xxx at least.  Rate sets should be generalized so they can be
+ * used for any OMAP chip, not just OMAP2xxx.  In particular, Richard Woodruff
+ * has in the past expressed a preference to use rate sets for OPP changes,
+ * rather than dynamically recalculating the clock tree, so if someone wants
+ * this badly enough to write the code to handle it, we should support it
+ * as an option.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/sdrc.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+const struct prcm_config *curr_prcm_set;
+const struct prcm_config *rate_table;
+
+/**
+ * omap2_table_mpu_recalc - just return the MPU speed
+ * @clk: virt_prcm_set struct clk
+ *
+ * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
+ */
+unsigned long omap2_table_mpu_recalc(struct clk *clk)
+{
+        return curr_prcm_set->mpu_speed;
+}
+
+/*
+ * Look for a rate equal or less than the target rate given a configuration set.
+ *
+ * What's not entirely clear is "which" field represents the key field.
+ * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
+ * just uses the ARM rates.
+ */
+long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+        const struct prcm_config *ptr;
+        long highest_rate;
+        long sys_ck_rate;
+
+        sys_ck_rate = clk_get_rate(sclk);
+
+        highest_rate = -EINVAL;
+
+        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+                if (ptr->xtal_speed != sys_ck_rate)
+                        continue;
+
+                highest_rate = ptr->mpu_speed;
+
+                /* Can check only after xtal frequency check */
+                if (ptr->mpu_speed <= rate)
+                        break;
+        }
+        return highest_rate;
+}
+
+/* Sets basic clocks based on the specified rate */
+int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, done_rate, bypass = 0, tmp;
+        const struct prcm_config *prcm;
+        unsigned long found_speed = 0;
+        unsigned long flags;
+        long sys_ck_rate;
+
+        sys_ck_rate = clk_get_rate(sclk);
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+
+                if (prcm->xtal_speed != sys_ck_rate)
+                        continue;
+
+                if (prcm->mpu_speed <= rate) {
+                        found_speed = prcm->mpu_speed;
+                        break;
+                }
+        }
+
+        if (!found_speed) {
+                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
+                       rate / 1000000);
+                return -EINVAL;
+        }
+
+        curr_prcm_set = prcm;
+        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+
+        if (prcm->dpll_speed == cur_rate / 2) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
+        } else if (prcm->dpll_speed == cur_rate * 2) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (prcm->dpll_speed != cur_rate) {
+                local_irq_save(flags);
+
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        bypass = 1;
+
+                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+                    CORE_CLK_SRC_DPLL_X2)
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                else
+                        done_rate = CORE_CLK_SRC_DPLL;
+
+                /* MPU divider */
+                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+
+                /* dsp + iva1 div(2420), iva2.1(2430) */
+                cm_write_mod_reg(prcm->cm_clksel_dsp,
+                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
+
+                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+
+                /* Major subsystem dividers */
+                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+                                 CM_CLKSEL1);
+
+                if (cpu_is_omap2430())
+                        cm_write_mod_reg(prcm->cm_clksel_mdm,
+                                         OMAP2430_MDM_MOD, CM_CLKSEL);
+
+                /* x2 to enter omap2xxx_sdrc_init_params() */
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+
+                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
+                               bypass);
+
+                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+                omap2xxx_sdrc_reprogram(done_rate, 0);
+
+                local_irq_restore(flags);
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_CPU_FREQ
+/*
+ * Walk PRCM rate table and fillout cpufreq freq_table
+ * XXX This should be replaced by an OPP layer in the near future
+ */
+static struct cpufreq_frequency_table *freq_table;
+
+void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        const struct prcm_config *prcm;
+        long sys_ck_rate;
+        int i = 0;
+        int tbl_sz = 0;
+
+        if (!cpu_is_omap24xx())
+                return;
+
+        sys_ck_rate = clk_get_rate(sclk);
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck_rate)
+                        continue;
+
+                /* don't put bypass rates in table */
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        continue;
+
+                tbl_sz++;
+        }
+
+        /*
+         * XXX Ensure that we're doing what CPUFreq expects for this error
+         * case and the following one
+         */
+        if (tbl_sz == 0) {
+                pr_warning("%s: no matching entries in rate_table\n",
+                           __func__);
+                return;
+        }
+
+        /* Include the CPUFREQ_TABLE_END terminator entry */
+        tbl_sz++;
+
+        freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz,
+                             GFP_ATOMIC);
+        if (!freq_table) {
+                pr_err("%s: could not kzalloc frequency table\n", __func__);
+                return;
+        }
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck_rate)
+                        continue;
+
+                /* don't put bypass rates in table */
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        continue;
+
+                freq_table[i].index = i;
+                freq_table[i].frequency = prcm->mpu_speed / 1000;
+                i++;
+        }
+
+        freq_table[i].index = i;
+        freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+        *table = &freq_table[0];
+}
+
+void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        if (!cpu_is_omap24xx())
+                return;
+
+        kfree(freq_table);
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
new file mode 100644
index 000000000000..8716a01d1f5b
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -0,0 +1,120 @@
+/*
+ * OMAP34xx M2 divider clock code
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Jouni Högander
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/sdrc.h>
+
+#include "clock.h"
+#include "clock34xx.h"
+#include "sdrc.h"
+
+#define CYCLES_PER_MHZ                  1000000
+
+/*
+ * CORE DPLL (DPLL3) M2 divider rate programming functions
+ *
+ * These call into SRAM code to do the actual CM writes, since the SDRAM
+ * is clocked from DPLL3.
+ */
+
+/**
+ * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
+ * @clk: struct clk * of DPLL to set
+ * @rate: rounded target rate
+ *
+ * Program the DPLL M2 divider with the rounded target rate.  Returns
+ * -EINVAL upon error, or 0 upon success.
+ */
+int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 new_div = 0;
+        u32 unlock_dll = 0;
+        u32 c;
+        unsigned long validrate, sdrcrate, _mpurate;
+        struct omap_sdrc_params *sdrc_cs0;
+        struct omap_sdrc_params *sdrc_cs1;
+        int ret;
+
+        if (!clk || !rate)
+                return -EINVAL;
+
+        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+        if (validrate != rate)
+                return -EINVAL;
+
+        sdrcrate = sdrc_ick_p->rate;
+        if (rate > clk->rate)
+                sdrcrate <<= ((rate / clk->rate) >> 1);
+        else
+                sdrcrate >>= ((clk->rate / rate) >> 1);
+
+        ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
+        if (ret)
+                return -EINVAL;
+
+        if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
+                pr_debug("clock: will unlock SDRC DLL\n");
+                unlock_dll = 1;
+        }
+
+        /*
+         * XXX This only needs to be done when the CPU frequency changes
+         */
+        _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+        c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+        c += 1;  /* for safety */
+        c *= SDRC_MPURATE_LOOPS;
+        c >>= SDRC_MPURATE_SCALE;
+        if (c == 0)
+                c = 1;
+
+        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+                 validrate);
+        pr_debug("clock: SDRC CS0 timing params used:"
+                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
+        if (sdrc_cs1)
+                pr_debug("clock: SDRC CS1 timing params used: "
+                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+
+        if (sdrc_cs1)
+                omap3_configure_core_dpll(
+                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+                                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+        else
+                omap3_configure_core_dpll(
+                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+                                  0, 0, 0, 0);
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
new file mode 100644
index 000000000000..25a2363106de
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -0,0 +1,417 @@
+/*
+ * clkt_clksel.c - OMAP2/3/4 clksel clock functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX At some point these clksel clocks should be split into
+ * "divider" clocks and "mux" clocks to better match the hardware.
+ *
+ * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
+ * many of the OMAP1 clocks should be convertible to use this
+ * mechanism.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+
+/* Private functions */
+
+/**
+ * _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
+ * @clk: OMAP struct clk ptr to inspect
+ * @src_clk: OMAP struct clk ptr of the parent clk to search for
+ *
+ * Scan the struct clksel array associated with the clock to find
+ * the element associated with the supplied parent clock address.
+ * Returns a pointer to the struct clksel on success or NULL on error.
+ */
+static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
+                                                        struct clk *src_clk)
+{
+        const struct clksel *clks;
+
+        if (!clk->clksel)
+                return NULL;
+
+        for (clks = clk->clksel; clks->parent; clks++) {
+                if (clks->parent == src_clk)
+                        break; /* Found the requested parent */
+        }
+
+        if (!clks->parent) {
+                printk(KERN_ERR "clock: Could not find parent clock %s in "
+                       "clksel array of clock %s\n", src_clk->name,
+                       clk->name);
+                return NULL;
+        }
+
+        return clks;
+}
+
+/*
+ * Converts encoded control register address into a full address
+ * On error, the return value (parent_div) will be 0.
+ */
+static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
+                                       u32 *field_val)
+{
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+
+        clks = _omap2_get_clksel_by_parent(clk, src_clk);
+        if (!clks)
+                return 0;
+
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
+                        break; /* Found the default rate for this platform */
+        }
+
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find default rate for "
+                       "clock %s parent %s\n", clk->name,
+                       src_clk->parent->name);
+                return 0;
+        }
+
+        /* Should never happen.  Add a clksel mask to the struct clk. */
+        WARN_ON(clk->clksel_mask == 0);
+
+        *field_val = clkr->val;
+
+        return clkr->div;
+}
+
+
+/* Public functions */
+
+/**
+ * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
+ * @clk: OMAP clock struct ptr to use
+ *
+ * Given a pointer to a source-selectable struct clk, read the hardware
+ * register and determine what its parent is currently set to.  Update the
+ * clk->parent field with the appropriate clk ptr.
+ */
+void omap2_init_clksel_parent(struct clk *clk)
+{
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+        u32 r, found = 0;
+
+        if (!clk->clksel)
+                return;
+
+        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        r >>= __ffs(clk->clksel_mask);
+
+        for (clks = clk->clksel; clks->parent && !found; clks++) {
+                for (clkr = clks->rates; clkr->div && !found; clkr++) {
+                        if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
+                                if (clk->parent != clks->parent) {
+                                        pr_debug("clock: inited %s parent "
+                                                 "to %s (was %s)\n",
+                                                 clk->name, clks->parent->name,
+                                                 ((clk->parent) ?
+                                                  clk->parent->name : "NULL"));
+                                        clk_reparent(clk, clks->parent);
+                                };
+                                found = 1;
+                        }
+                }
+        }
+
+        if (!found)
+                printk(KERN_ERR "clock: init parent: could not find "
+                       "regval %0x for clock %s\n", r,  clk->name);
+
+        return;
+}
+
+/*
+ * Used for clocks that are part of CLKSEL_xyz governed clocks.
+ * REVISIT: Maybe change to use clk->enable() functions like on omap1?
+ */
+unsigned long omap2_clksel_recalc(struct clk *clk)
+{
+        unsigned long rate;
+        u32 div = 0;
+
+        pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
+
+        div = omap2_clksel_get_divisor(clk);
+        if (div == 0)
+                return clk->rate;
+
+        rate = clk->parent->rate / div;
+
+        pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
+
+        return rate;
+}
+
+/**
+ * omap2_clksel_round_rate_div - find divisor for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ * @new_div: ptr to where we should store the divisor
+ *
+ * Finds 'best' divider value in an array based on the source and target
+ * rates.  The divider array must be sorted with smallest divider first.
+ * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
+ * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
+ */
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+                                u32 *new_div)
+{
+        unsigned long test_rate;
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+        u32 last_div = 0;
+
+        pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
+                 clk->name, target_rate);
+
+        *new_div = 1;
+
+        clks = _omap2_get_clksel_by_parent(clk, clk->parent);
+        if (!clks)
+                return ~0;
+
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (!(clkr->flags & cpu_mask))
+                        continue;
+
+                /* Sanity check */
+                if (clkr->div <= last_div)
+                        pr_err("clock: clksel_rate table not sorted "
+                               "for clock %s", clk->name);
+
+                last_div = clkr->div;
+
+                test_rate = clk->parent->rate / clkr->div;
+
+                if (test_rate <= target_rate)
+                        break; /* found it */
+        }
+
+        if (!clkr->div) {
+                pr_err("clock: Could not find divisor for target "
+                       "rate %ld for clock %s parent %s\n", target_rate,
+                       clk->name, clk->parent->name);
+                return ~0;
+        }
+
+        *new_div = clkr->div;
+
+        pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
+                 (clk->parent->rate / clkr->div));
+
+        return clk->parent->rate / clkr->div;
+}
+
+/**
+ * omap2_clksel_round_rate - find rounded rate for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ *
+ * Compatibility wrapper for OMAP clock framework
+ * Finds best target rate based on the source clock and possible dividers.
+ * rates. The divider array must be sorted with smallest divider first.
+ * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
+ * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
+ */
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
+{
+        u32 new_div;
+
+        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
+}
+
+
+/* Given a clock and a rate apply a clock specific rounding function */
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk->round_rate)
+                return clk->round_rate(clk, rate);
+
+        if (clk->flags & RATE_FIXED)
+                printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
+                       "on fixed-rate clock %s\n", clk->name);
+
+        return clk->rate;
+}
+
+/**
+ * omap2_clksel_to_divisor() - turn clksel field value into integer divider
+ * @clk: OMAP struct clk to use
+ * @field_val: register field value to find
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a register field
+ * value to search for, find the corresponding clock divisor.  The register
+ * field value should be pre-masked and shifted down so the LSB is at bit 0
+ * before calling.  Returns 0 on error
+ */
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
+{
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+
+        clks = _omap2_get_clksel_by_parent(clk, clk->parent);
+        if (!clks)
+                return 0;
+
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
+                        break;
+        }
+
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find fieldval %d for "
+                       "clock %s parent %s\n", field_val, clk->name,
+                       clk->parent->name);
+                return 0;
+        }
+
+        return clkr->div;
+}
+
+/**
+ * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
+ * @clk: OMAP struct clk to use
+ * @div: integer divisor to search for
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
+ * find the corresponding register field value.  The return register value is
+ * the value before left-shifting.  Returns ~0 on error
+ */
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
+{
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+
+        /* should never happen */
+        WARN_ON(div == 0);
+
+        clks = _omap2_get_clksel_by_parent(clk, clk->parent);
+        if (!clks)
+                return ~0;
+
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if ((clkr->flags & cpu_mask) && (clkr->div == div))
+                        break;
+        }
+
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find divisor %d for "
+                       "clock %s parent %s\n", div, clk->name,
+                       clk->parent->name);
+                return ~0;
+        }
+
+        return clkr->val;
+}
+
+/**
+ * omap2_clksel_get_divisor - get current divider applied to parent clock.
+ * @clk: OMAP struct clk to use.
+ *
+ * Returns the integer divisor upon success or 0 on error.
+ */
+u32 omap2_clksel_get_divisor(struct clk *clk)
+{
+        u32 v;
+
+        if (!clk->clksel_mask)
+                return 0;
+
+        v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        v >>= __ffs(clk->clksel_mask);
+
+        return omap2_clksel_to_divisor(clk, v);
+}
+
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 v, field_val, validrate, new_div = 0;
+
+        if (!clk->clksel_mask)
+                return -EINVAL;
+
+        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+        if (validrate != rate)
+                return -EINVAL;
+
+        field_val = omap2_divisor_to_clksel(clk, new_div);
+        if (field_val == ~0)
+                return -EINVAL;
+
+        v = __raw_readl(clk->clksel_reg);
+        v &= ~clk->clksel_mask;
+        v |= field_val << __ffs(clk->clksel_mask);
+        __raw_writel(v, clk->clksel_reg);
+        v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+
+        clk->rate = clk->parent->rate / new_div;
+
+        omap2xxx_clk_commit(clk);
+
+        return 0;
+}
+
+int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
+{
+        u32 field_val, v, parent_div;
+
+        if (!clk->clksel)
+                return -EINVAL;
+
+        parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
+        if (!parent_div)
+                return -EINVAL;
+
+        /* Set new source value (previous dividers if any in effect) */
+        v = __raw_readl(clk->clksel_reg);
+        v &= ~clk->clksel_mask;
+        v |= field_val << __ffs(clk->clksel_mask);
+        __raw_writel(v, clk->clksel_reg);
+        v = __raw_readl(clk->clksel_reg);    /* OCP barrier */
+
+        omap2xxx_clk_commit(clk);
+
+        clk_reparent(clk, new_parent);
+
+        /* CLKSEL clocks follow their parents' rates, divided by a divisor */
+        clk->rate = new_parent->rate;
+
+        if (parent_div > 0)
+                clk->rate /= parent_div;
+
+        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+                 clk->name, clk->parent->name, clk->rate);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
new file mode 100644
index 000000000000..9eee0e67d5d6
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -0,0 +1,386 @@
+/*
+ * OMAP2/3/4 DPLL clock functions
+ *
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/div64.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+
+/* DPLL rate rounding: minimum DPLL multiplier, divider values */
+#define DPLL_MIN_MULTIPLIER             1
+#define DPLL_MIN_DIVIDER                1
+
+/* Possible error results from _dpll_test_mult */
+#define DPLL_MULT_UNDERFLOW             -1
+
+/*
+ * Scale factor to mitigate roundoff errors in DPLL rate rounding.
+ * The higher the scale factor, the greater the risk of arithmetic overflow,
+ * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
+ * must be a power of DPLL_SCALE_BASE.
+ */
+#define DPLL_SCALE_FACTOR               64
+#define DPLL_SCALE_BASE                 2
+#define DPLL_ROUNDING_VAL               ((DPLL_SCALE_BASE / 2) * \
+                                         (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
+
+/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
+#define DPLL_FINT_BAND1_MIN             750000
+#define DPLL_FINT_BAND1_MAX             2100000
+#define DPLL_FINT_BAND2_MIN             7500000
+#define DPLL_FINT_BAND2_MAX             21000000
+
+/* _dpll_test_fint() return codes */
+#define DPLL_FINT_UNDERFLOW             -1
+#define DPLL_FINT_INVALID               -2
+
+/* Private functions */
+
+/*
+ * _dpll_test_fint - test whether an Fint value is valid for the DPLL
+ * @clk: DPLL struct clk to test
+ * @n: divider value (N) to test
+ *
+ * Tests whether a particular divider @n will result in a valid DPLL
+ * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
+ * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
+ * (assuming that it is counting N upwards), or -2 if the enclosing loop
+ * should skip to the next iteration (again assuming N is increasing).
+ */
+static int _dpll_test_fint(struct clk *clk, u8 n)
+{
+        struct dpll_data *dd;
+        long fint;
+        int ret = 0;
+
+        dd = clk->dpll_data;
+
+        /* DPLL divider must result in a valid jitter correction val */
+        fint = clk->parent->rate / (n + 1);
+        if (fint < DPLL_FINT_BAND1_MIN) {
+
+                pr_debug("rejecting n=%d due to Fint failure, "
+                         "lowering max_divider\n", n);
+                dd->max_divider = n;
+                ret = DPLL_FINT_UNDERFLOW;
+
+        } else if (fint > DPLL_FINT_BAND1_MAX &&
+                   fint < DPLL_FINT_BAND2_MIN) {
+
+                pr_debug("rejecting n=%d due to Fint failure\n", n);
+                ret = DPLL_FINT_INVALID;
+
+        } else if (fint > DPLL_FINT_BAND2_MAX) {
+
+                pr_debug("rejecting n=%d due to Fint failure, "
+                         "boosting min_divider\n", n);
+                dd->min_divider = n;
+                ret = DPLL_FINT_INVALID;
+
+        }
+
+        return ret;
+}
+
+static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
+                                            unsigned int m, unsigned int n)
+{
+        unsigned long long num;
+
+        num = (unsigned long long)parent_rate * m;
+        do_div(num, n);
+        return num;
+}
+
+/*
+ * _dpll_test_mult - test a DPLL multiplier value
+ * @m: pointer to the DPLL m (multiplier) value under test
+ * @n: current DPLL n (divider) value under test
+ * @new_rate: pointer to storage for the resulting rounded rate
+ * @target_rate: the desired DPLL rate
+ * @parent_rate: the DPLL's parent clock rate
+ *
+ * This code tests a DPLL multiplier value, ensuring that the
+ * resulting rate will not be higher than the target_rate, and that
+ * the multiplier value itself is valid for the DPLL.  Initially, the
+ * integer pointed to by the m argument should be prescaled by
+ * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
+ * a non-scaled m upon return.  This non-scaled m will result in a
+ * new_rate as close as possible to target_rate (but not greater than
+ * target_rate) given the current (parent_rate, n, prescaled m)
+ * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
+ * non-scaled m attempted to underflow, which can allow the calling
+ * function to bail out early; or 0 upon success.
+ */
+static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
+                           unsigned long target_rate,
+                           unsigned long parent_rate)
+{
+        int r = 0, carry = 0;
+
+        /* Unscale m and round if necessary */
+        if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
+                carry = 1;
+        *m = (*m / DPLL_SCALE_FACTOR) + carry;
+
+        /*
+         * The new rate must be <= the target rate to avoid programming
+         * a rate that is impossible for the hardware to handle
+         */
+        *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+        if (*new_rate > target_rate) {
+                (*m)--;
+                *new_rate = 0;
+        }
+
+        /* Guard against m underflow */
+        if (*m < DPLL_MIN_MULTIPLIER) {
+                *m = DPLL_MIN_MULTIPLIER;
+                *new_rate = 0;
+                r = DPLL_MULT_UNDERFLOW;
+        }
+
+        if (*new_rate == 0)
+                *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
+
+        return r;
+}
+
+/* Public functions */
+
+void omap2_init_dpll_parent(struct clk *clk)
+{
+        u32 v;
+        struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return;
+
+        /* Return bypass rate if DPLL is bypassed */
+        v = __raw_readl(dd->control_reg);
+        v &= dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+
+        /* Reparent in case the dpll is in bypass */
+        if (cpu_is_omap24xx()) {
+                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        } else if (cpu_is_omap34xx()) {
+                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        } else if (cpu_is_omap44xx()) {
+                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        }
+        return;
+}
+
+/**
+ * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
+ * @clk: struct clk * of a DPLL
+ *
+ * DPLLs can be locked or bypassed - basically, enabled or disabled.
+ * When locked, the DPLL output depends on the M and N values.  When
+ * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
+ * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
+ * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
+ * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
+ * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
+ * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
+ * if the clock @clk is not a DPLL.
+ */
+u32 omap2_get_dpll_rate(struct clk *clk)
+{
+        long long dpll_clk;
+        u32 dpll_mult, dpll_div, v;
+        struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return 0;
+
+        /* Return bypass rate if DPLL is bypassed */
+        v = __raw_readl(dd->control_reg);
+        v &= dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+
+        if (cpu_is_omap24xx()) {
+                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
+                        return dd->clk_bypass->rate;
+        } else if (cpu_is_omap34xx()) {
+                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
+                        return dd->clk_bypass->rate;
+        } else if (cpu_is_omap44xx()) {
+                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+                        return dd->clk_bypass->rate;
+        }
+
+        v = __raw_readl(dd->mult_div1_reg);
+        dpll_mult = v & dd->mult_mask;
+        dpll_mult >>= __ffs(dd->mult_mask);
+        dpll_div = v & dd->div1_mask;
+        dpll_div >>= __ffs(dd->div1_mask);
+
+        dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+        do_div(dpll_clk, dpll_div + 1);
+
+        return dpll_clk;
+}
+
+/* DPLL rate rounding code */
+
+/**
+ * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
+ * @clk: struct clk * of the DPLL
+ * @tolerance: maximum rate error tolerance
+ *
+ * Set the maximum DPLL rate error tolerance for the rate rounding
+ * algorithm.  The rate tolerance is an attempt to balance DPLL power
+ * saving (the least divider value "n") vs. rate fidelity (the least
+ * difference between the desired DPLL target rate and the rounded
+ * rate out of the algorithm).  So, increasing the tolerance is likely
+ * to decrease DPLL power consumption and increase DPLL rate error.
+ * Returns -EINVAL if provided a null clock ptr or a clk that is not a
+ * DPLL; or 0 upon success.
+ */
+int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
+{
+        if (!clk || !clk->dpll_data)
+                return -EINVAL;
+
+        clk->dpll_data->rate_tolerance = tolerance;
+
+        return 0;
+}
+
+/**
+ * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
+ * @clk: struct clk * for a DPLL
+ * @target_rate: desired DPLL clock rate
+ *
+ * Given a DPLL, a desired target rate, and a rate tolerance, round
+ * the target rate to a possible, programmable rate for this DPLL.
+ * Rate tolerance is assumed to be set by the caller before this
+ * function is called.  Attempts to select the minimum possible n
+ * within the tolerance to reduce power consumption.  Stores the
+ * computed (m, n) in the DPLL's dpll_data structure so set_rate()
+ * will not need to call this (expensive) function again.  Returns ~0
+ * if the target rate cannot be rounded, either because the rate is
+ * too low or because the rate tolerance is set too tightly; or the
+ * rounded rate upon success.
+ */
+long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+{
+        int m, n, r, e, scaled_max_m;
+        unsigned long scaled_rt_rp, new_rate;
+        int min_e = -1, min_e_m = -1, min_e_n = -1;
+        struct dpll_data *dd;
+
+        if (!clk || !clk->dpll_data)
+                return ~0;
+
+        dd = clk->dpll_data;
+
+        pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
+                 "%ld\n", clk->name, target_rate);
+
+        scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+        scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
+
+        dd->last_rounded_rate = 0;
+
+        for (n = dd->min_divider; n <= dd->max_divider; n++) {
+
+                /* Is the (input clk, divider) pair valid for the DPLL? */
+                r = _dpll_test_fint(clk, n);
+                if (r == DPLL_FINT_UNDERFLOW)
+                        break;
+                else if (r == DPLL_FINT_INVALID)
+                        continue;
+
+                /* Compute the scaled DPLL multiplier, based on the divider */
+                m = scaled_rt_rp * n;
+
+                /*
+                 * Since we're counting n up, a m overflow means we
+                 * can bail out completely (since as n increases in
+                 * the next iteration, there's no way that m can
+                 * increase beyond the current m)
+                 */
+                if (m > scaled_max_m)
+                        break;
+
+                r = _dpll_test_mult(&m, n, &new_rate, target_rate,
+                                    dd->clk_ref->rate);
+
+                /* m can't be set low enough for this n - try with a larger n */
+                if (r == DPLL_MULT_UNDERFLOW)
+                        continue;
+
+                e = target_rate - new_rate;
+                pr_debug("clock: n = %d: m = %d: rate error is %d "
+                         "(new_rate = %ld)\n", n, m, e, new_rate);
+
+                if (min_e == -1 ||
+                    min_e >= (int)(abs(e) - dd->rate_tolerance)) {
+                        min_e = e;
+                        min_e_m = m;
+                        min_e_n = n;
+
+                        pr_debug("clock: found new least error %d\n", min_e);
+
+                        /* We found good settings -- bail out now */
+                        if (min_e <= dd->rate_tolerance)
+                                break;
+                }
+        }
+
+        if (min_e < 0) {
+                pr_debug("clock: error: target rate or tolerance too low\n");
+                return ~0;
+        }
+
+        dd->last_rounded_m = min_e_m;
+        dd->last_rounded_n = min_e_n;
+        dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
+                                                       min_e_m,  min_e_n);
+
+        pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
+                 min_e, min_e_m, min_e_n);
+        pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
+                 dd->last_rounded_rate, target_rate);
+
+        return dd->last_rounded_rate;
+}
+
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 759c72a48f7f..999b91e023b1 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -28,10 +28,7 @@
 #include <plat/clockdomain.h>
 #include <plat/cpu.h>
 #include <plat/prcm.h>
-#include <asm/div64.h>
 
-#include <plat/sdrc.h>
-#include "sdrc.h"
 #include "clock.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
@@ -39,81 +36,66 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-/* DPLL rate rounding: minimum DPLL multiplier, divider values */
-#define DPLL_MIN_MULTIPLIER             1
-#define DPLL_MIN_DIVIDER                1
-
-/* Possible error results from _dpll_test_mult */
-#define DPLL_MULT_UNDERFLOW             -1
-
-/*
- * Scale factor to mitigate roundoff errors in DPLL rate rounding.
- * The higher the scale factor, the greater the risk of arithmetic overflow,
- * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
- * must be a power of DPLL_SCALE_BASE.
- */
-#define DPLL_SCALE_FACTOR               64
-#define DPLL_SCALE_BASE                 2
-#define DPLL_ROUNDING_VAL               ((DPLL_SCALE_BASE / 2) * \
-                                         (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
-
-/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
-#define DPLL_FINT_BAND1_MIN             750000
-#define DPLL_FINT_BAND1_MAX             2100000
-#define DPLL_FINT_BAND2_MIN             7500000
-#define DPLL_FINT_BAND2_MAX             21000000
-
-/* _dpll_test_fint() return codes */
-#define DPLL_FINT_UNDERFLOW             -1
-#define DPLL_FINT_INVALID               -2
-
 u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
  * OMAP2/3/4 specific clock functions
  *-------------------------------------------------------------------------*/
 
-void omap2_init_dpll_parent(struct clk *clk)
+/* Private functions */
+
+/**
+ * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
+ * @clk: struct clk * belonging to the module
+ *
+ * If the necessary clocks for the OMAP hardware IP block that
+ * corresponds to clock @clk are enabled, then wait for the module to
+ * indicate readiness (i.e., to leave IDLE).  This code does not
+ * belong in the clock code and will be moved in the medium term to
+ * module-dependent code.  No return value.
+ */
+static void _omap2_module_wait_ready(struct clk *clk)
 {
-        u32 v;
-        struct dpll_data *dd;
+        void __iomem *companion_reg, *idlest_reg;
+        u8 other_bit, idlest_bit;
 
-        dd = clk->dpll_data;
-        if (!dd)
-                return;
+        /* Not all modules have multiple clocks that their IDLEST depends on */
+        if (clk->ops->find_companion) {
+                clk->ops->find_companion(clk, &companion_reg, &other_bit);
+                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+                        return;
+        }
 
-        /* Return bypass rate if DPLL is bypassed */
-        v = __raw_readl(dd->control_reg);
-        v &= dd->enable_mask;
-        v >>= __ffs(dd->enable_mask);
+        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
 
-        /* Reparent in case the dpll is in bypass */
-        if (cpu_is_omap24xx()) {
-                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        clk_reparent(clk, dd->clk_bypass);
-        } else if (cpu_is_omap34xx()) {
-                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        clk_reparent(clk, dd->clk_bypass);
-        } else if (cpu_is_omap44xx()) {
-                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        clk_reparent(clk, dd->clk_bypass);
-        }
-        return;
+        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
 }
 
+/* Enables clock without considering parent dependencies or use count
+ * REVISIT: Maybe change this to use clk->enable like on omap1?
+ */
+static int _omap2_clk_enable(struct clk *clk)
+{
+        return clk->ops->enable(clk);
+}
+
+/* Disables clock without considering parent dependencies or use count */
+static void _omap2_clk_disable(struct clk *clk)
+{
+        clk->ops->disable(clk);
+}
+
+/* Public functions */
+
 /**
- * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
+ * omap2xxx_clk_commit - commit clock parent/rate changes in hardware
  * @clk: struct clk *
  *
  * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
  * don't take effect until the VALID_CONFIG bit is written, write the
  * VALID_CONFIG bit and wait for the write to complete.  No return value.
  */
-static void _omap2xxx_clk_commit(struct clk *clk)
+void omap2xxx_clk_commit(struct clk *clk)
 {
         if (!cpu_is_omap24xx())
                 return;
@@ -127,52 +109,6 @@ static void _omap2xxx_clk_commit(struct clk *clk)
         prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
 }
 
-/*
- * _dpll_test_fint - test whether an Fint value is valid for the DPLL
- * @clk: DPLL struct clk to test
- * @n: divider value (N) to test
- *
- * Tests whether a particular divider @n will result in a valid DPLL
- * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
- * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
- * (assuming that it is counting N upwards), or -2 if the enclosing loop
- * should skip to the next iteration (again assuming N is increasing).
- */
-static int _dpll_test_fint(struct clk *clk, u8 n)
-{
-        struct dpll_data *dd;
-        long fint;
-        int ret = 0;
-
-        dd = clk->dpll_data;
-
-        /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / (n + 1);
-        if (fint < DPLL_FINT_BAND1_MIN) {
-
-                pr_debug("rejecting n=%d due to Fint failure, "
-                         "lowering max_divider\n", n);
-                dd->max_divider = n;
-                ret = DPLL_FINT_UNDERFLOW;
-
-        } else if (fint > DPLL_FINT_BAND1_MAX &&
-                   fint < DPLL_FINT_BAND2_MIN) {
-
-                pr_debug("rejecting n=%d due to Fint failure\n", n);
-                ret = DPLL_FINT_INVALID;
-
-        } else if (fint > DPLL_FINT_BAND2_MAX) {
-
-                pr_debug("rejecting n=%d due to Fint failure, "
-                         "boosting min_divider\n", n);
-                dd->min_divider = n;
-                ret = DPLL_FINT_INVALID;
-
-        }
-
-        return ret;
-}
-
 /**
  * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
  * @clk: OMAP clock struct ptr to use
@@ -181,7 +117,6 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
  * clockdomain pointer, and save it into the struct clk.  Intended to be
  * called during clk_register().  No return value.
  */
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
 void omap2_init_clk_clkdm(struct clk *clk)
 {
         struct clockdomain *clkdm;
@@ -199,117 +134,6 @@ void omap2_init_clk_clkdm(struct clk *clk)
                          "clkdm %s\n", clk->name, clk->clkdm_name);
         }
 }
-#endif
-
-/**
- * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
- * @clk: OMAP clock struct ptr to use
- *
- * Given a pointer to a source-selectable struct clk, read the hardware
- * register and determine what its parent is currently set to.  Update the
- * clk->parent field with the appropriate clk ptr.
- */
-void omap2_init_clksel_parent(struct clk *clk)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-        u32 r, found = 0;
-
-        if (!clk->clksel)
-                return;
-
-        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
-        r >>= __ffs(clk->clksel_mask);
-
-        for (clks = clk->clksel; clks->parent && !found; clks++) {
-                for (clkr = clks->rates; clkr->div && !found; clkr++) {
-                        if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
-                                if (clk->parent != clks->parent) {
-                                        pr_debug("clock: inited %s parent "
-                                                 "to %s (was %s)\n",
-                                                 clk->name, clks->parent->name,
-                                                 ((clk->parent) ?
-                                                  clk->parent->name : "NULL"));
-                                        clk_reparent(clk, clks->parent);
-                                };
-                                found = 1;
-                        }
-                }
-        }
-
-        if (!found)
-                printk(KERN_ERR "clock: init parent: could not find "
-                       "regval %0x for clock %s\n", r,  clk->name);
-
-        return;
-}
-
-/**
- * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
- * @clk: struct clk * of a DPLL
- *
- * DPLLs can be locked or bypassed - basically, enabled or disabled.
- * When locked, the DPLL output depends on the M and N values.  When
- * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
- * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
- * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
- * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
- * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
- * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
- * if the clock @clk is not a DPLL.
- */
-u32 omap2_get_dpll_rate(struct clk *clk)
-{
-        long long dpll_clk;
-        u32 dpll_mult, dpll_div, v;
-        struct dpll_data *dd;
-
-        dd = clk->dpll_data;
-        if (!dd)
-                return 0;
-
-        /* Return bypass rate if DPLL is bypassed */
-        v = __raw_readl(dd->control_reg);
-        v &= dd->enable_mask;
-        v >>= __ffs(dd->enable_mask);
-
-        if (cpu_is_omap24xx()) {
-                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
-        } else if (cpu_is_omap34xx()) {
-                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
-        } else if (cpu_is_omap44xx()) {
-                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
-                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        return dd->clk_bypass->rate;
-        }
-
-        v = __raw_readl(dd->mult_div1_reg);
-        dpll_mult = v & dd->mult_mask;
-        dpll_mult >>= __ffs(dd->mult_mask);
-        dpll_div = v & dd->div1_mask;
-        dpll_div >>= __ffs(dd->div1_mask);
-
-        dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
-        do_div(dpll_clk, dpll_div + 1);
-
-        return dpll_clk;
-}
-
-/*
- * Used for clocks that have the same value as the parent clock,
- * divided by some factor
- */
-unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
-{
-        WARN_ON(!clk->fixed_div);
-
-        return clk->parent->rate / clk->fixed_div;
-}
 
 /**
  * omap2_clk_dflt_find_companion - find companion clock to @clk
@@ -370,33 +194,6 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
         *idlest_bit = clk->enable_bit;
 }
 
-/**
- * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
- * @clk: struct clk * belonging to the module
- *
- * If the necessary clocks for the OMAP hardware IP block that
- * corresponds to clock @clk are enabled, then wait for the module to
- * indicate readiness (i.e., to leave IDLE).  This code does not
- * belong in the clock code and will be moved in the medium term to
- * module-dependent code.  No return value.
- */
-static void omap2_module_wait_ready(struct clk *clk)
-{
-        void __iomem *companion_reg, *idlest_reg;
-        u8 other_bit, idlest_bit;
-
-        /* Not all modules have multiple clocks that their IDLEST depends on */
-        if (clk->ops->find_companion) {
-                clk->ops->find_companion(clk, &companion_reg, &other_bit);
-                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
-                        return;
-        }
-
-        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
-
-        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
-}
-
 int omap2_dflt_clk_enable(struct clk *clk)
 {
         u32 v;
@@ -416,7 +213,7 @@ int omap2_dflt_clk_enable(struct clk *clk)
         v = __raw_readl(clk->enable_reg); /* OCP barrier */
 
         if (clk->ops->find_idlest)
-                omap2_module_wait_ready(clk);
+                _omap2_module_wait_ready(clk);
 
         return 0;
 }
@@ -456,30 +253,14 @@ const struct clkops clkops_omap2_dflt = {
         .disable        = omap2_dflt_clk_disable,
 };
 
-/* Enables clock without considering parent dependencies or use count
- * REVISIT: Maybe change this to use clk->enable like on omap1?
- */
-static int _omap2_clk_enable(struct clk *clk)
-{
-        return clk->ops->enable(clk);
-}
-
-/* Disables clock without considering parent dependencies or use count */
-static void _omap2_clk_disable(struct clk *clk)
-{
-        clk->ops->disable(clk);
-}
-
 void omap2_clk_disable(struct clk *clk)
 {
         if (clk->usecount > 0 && !(--clk->usecount)) {
                 _omap2_clk_disable(clk);
                 if (clk->parent)
                         omap2_clk_disable(clk->parent);
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
                 if (clk->clkdm)
                         omap2_clkdm_clk_disable(clk->clkdm, clk);
-#endif
 
         }
 }
@@ -489,10 +270,8 @@ int omap2_clk_enable(struct clk *clk)
         int ret = 0;
 
         if (clk->usecount++ == 0) {
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
                 if (clk->clkdm)
                         omap2_clkdm_clk_enable(clk->clkdm, clk);
-#endif
 
                 if (clk->parent) {
                         ret = omap2_clk_enable(clk->parent);
@@ -511,282 +290,12 @@ int omap2_clk_enable(struct clk *clk)
         return ret;
 
 err:
-#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
         if (clk->clkdm)
                 omap2_clkdm_clk_disable(clk->clkdm, clk);
-#endif
         clk->usecount--;
         return ret;
 }
 
-/*
- * Used for clocks that are part of CLKSEL_xyz governed clocks.
- * REVISIT: Maybe change to use clk->enable() functions like on omap1?
- */
-unsigned long omap2_clksel_recalc(struct clk *clk)
-{
-        unsigned long rate;
-        u32 div = 0;
-
-        pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
-
-        div = omap2_clksel_get_divisor(clk);
-        if (div == 0)
-                return clk->rate;
-
-        rate = clk->parent->rate / div;
-
-        pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
-
-        return rate;
-}
-
-/**
- * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
- * @clk: OMAP struct clk ptr to inspect
- * @src_clk: OMAP struct clk ptr of the parent clk to search for
- *
- * Scan the struct clksel array associated with the clock to find
- * the element associated with the supplied parent clock address.
- * Returns a pointer to the struct clksel on success or NULL on error.
- */
-static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
-                                                       struct clk *src_clk)
-{
-        const struct clksel *clks;
-
-        if (!clk->clksel)
-                return NULL;
-
-        for (clks = clk->clksel; clks->parent; clks++) {
-                if (clks->parent == src_clk)
-                        break; /* Found the requested parent */
-        }
-
-        if (!clks->parent) {
-                printk(KERN_ERR "clock: Could not find parent clock %s in "
-                       "clksel array of clock %s\n", src_clk->name,
-                       clk->name);
-                return NULL;
-        }
-
-        return clks;
-}
-
-/**
- * omap2_clksel_round_rate_div - find divisor for the given clock and rate
- * @clk: OMAP struct clk to use
- * @target_rate: desired clock rate
- * @new_div: ptr to where we should store the divisor
- *
- * Finds 'best' divider value in an array based on the source and target
- * rates.  The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
- *
- * Returns the rounded clock rate or returns 0xffffffff on error.
- */
-u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
-                                u32 *new_div)
-{
-        unsigned long test_rate;
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-        u32 last_div = 0;
-
-        pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
-                 clk->name, target_rate);
-
-        *new_div = 1;
-
-        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (!clks)
-                return ~0;
-
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if (!(clkr->flags & cpu_mask))
-                    continue;
-
-                /* Sanity check */
-                if (clkr->div <= last_div)
-                        pr_err("clock: clksel_rate table not sorted "
-                               "for clock %s", clk->name);
-
-                last_div = clkr->div;
-
-                test_rate = clk->parent->rate / clkr->div;
-
-                if (test_rate <= target_rate)
-                        break; /* found it */
-        }
-
-        if (!clkr->div) {
-                pr_err("clock: Could not find divisor for target "
-                       "rate %ld for clock %s parent %s\n", target_rate,
-                       clk->name, clk->parent->name);
-                return ~0;
-        }
-
-        *new_div = clkr->div;
-
-        pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
-                 (clk->parent->rate / clkr->div));
-
-        return (clk->parent->rate / clkr->div);
-}
-
-/**
- * omap2_clksel_round_rate - find rounded rate for the given clock and rate
- * @clk: OMAP struct clk to use
- * @target_rate: desired clock rate
- *
- * Compatibility wrapper for OMAP clock framework
- * Finds best target rate based on the source clock and possible dividers.
- * rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
- *
- * Returns the rounded clock rate or returns 0xffffffff on error.
- */
-long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
-{
-        u32 new_div;
-
-        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
-}
-
-
-/* Given a clock and a rate apply a clock specific rounding function */
-long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (clk->round_rate)
-                return clk->round_rate(clk, rate);
-
-        if (clk->flags & RATE_FIXED)
-                printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
-                       "on fixed-rate clock %s\n", clk->name);
-
-        return clk->rate;
-}
-
-/**
- * omap2_clksel_to_divisor() - turn clksel field value into integer divider
- * @clk: OMAP struct clk to use
- * @field_val: register field value to find
- *
- * Given a struct clk of a rate-selectable clksel clock, and a register field
- * value to search for, find the corresponding clock divisor.  The register
- * field value should be pre-masked and shifted down so the LSB is at bit 0
- * before calling.  Returns 0 on error
- */
-u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-
-        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (!clks)
-                return 0;
-
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
-                        break;
-        }
-
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find fieldval %d for "
-                       "clock %s parent %s\n", field_val, clk->name,
-                       clk->parent->name);
-                return 0;
-        }
-
-        return clkr->div;
-}
-
-/**
- * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
- * @clk: OMAP struct clk to use
- * @div: integer divisor to search for
- *
- * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
- * find the corresponding register field value.  The return register value is
- * the value before left-shifting.  Returns ~0 on error
- */
-u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-
-        /* should never happen */
-        WARN_ON(div == 0);
-
-        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (!clks)
-                return ~0;
-
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if ((clkr->flags & cpu_mask) && (clkr->div == div))
-                        break;
-        }
-
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find divisor %d for "
-                       "clock %s parent %s\n", div, clk->name,
-                       clk->parent->name);
-                return ~0;
-        }
-
-        return clkr->val;
-}
-
-/**
- * omap2_clksel_get_divisor - get current divider applied to parent clock.
- * @clk: OMAP struct clk to use.
- *
- * Returns the integer divisor upon success or 0 on error.
- */
-u32 omap2_clksel_get_divisor(struct clk *clk)
-{
-        u32 v;
-
-        if (!clk->clksel_mask)
-                return 0;
-
-        v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
-        v >>= __ffs(clk->clksel_mask);
-
-        return omap2_clksel_to_divisor(clk, v);
-}
-
-int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 v, field_val, validrate, new_div = 0;
-
-        if (!clk->clksel_mask)
-                return -EINVAL;
-
-        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
-        if (validrate != rate)
-                return -EINVAL;
-
-        field_val = omap2_divisor_to_clksel(clk, new_div);
-        if (field_val == ~0)
-                return -EINVAL;
-
-        v = __raw_readl(clk->clksel_reg);
-        v &= ~clk->clksel_mask;
-        v |= field_val << __ffs(clk->clksel_mask);
-        __raw_writel(v, clk->clksel_reg);
-        v = __raw_readl(clk->clksel_reg); /* OCP barrier */
-
-        clk->rate = clk->parent->rate / new_div;
-
-        _omap2xxx_clk_commit(clk);
-
-        return 0;
-}
-
-
 /* Set the clock rate for a clock source */
 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 {
@@ -806,265 +315,15 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
         return ret;
 }
 
-/*
- * Converts encoded control register address into a full address
- * On error, the return value (parent_div) will be 0.
- */
-static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
-                                       u32 *field_val)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-
-        clks = omap2_get_clksel_by_parent(clk, src_clk);
-        if (!clks)
-                return 0;
-
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
-                        break; /* Found the default rate for this platform */
-        }
-
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find default rate for "
-                       "clock %s parent %s\n", clk->name,
-                       src_clk->parent->name);
-                return 0;
-        }
-
-        /* Should never happen.  Add a clksel mask to the struct clk. */
-        WARN_ON(clk->clksel_mask == 0);
-
-        *field_val = clkr->val;
-
-        return clkr->div;
-}
-
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
-        u32 field_val, v, parent_div;
-
         if (clk->flags & CONFIG_PARTICIPANT)
                 return -EINVAL;
 
         if (!clk->clksel)
                 return -EINVAL;
 
-        parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
-        if (!parent_div)
-                return -EINVAL;
-
-        /* Set new source value (previous dividers if any in effect) */
-        v = __raw_readl(clk->clksel_reg);
-        v &= ~clk->clksel_mask;
-        v |= field_val << __ffs(clk->clksel_mask);
-        __raw_writel(v, clk->clksel_reg);
-        v = __raw_readl(clk->clksel_reg);    /* OCP barrier */
-
-        _omap2xxx_clk_commit(clk);
-
-        clk_reparent(clk, new_parent);
-
-        /* CLKSEL clocks follow their parents' rates, divided by a divisor */
-        clk->rate = new_parent->rate;
-
-        if (parent_div > 0)
-                clk->rate /= parent_div;
-
-        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
-                 clk->name, clk->parent->name, clk->rate);
-
-        return 0;
-}
-
-/* DPLL rate rounding code */
-
-/**
- * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
- * @clk: struct clk * of the DPLL
- * @tolerance: maximum rate error tolerance
- *
- * Set the maximum DPLL rate error tolerance for the rate rounding
- * algorithm.  The rate tolerance is an attempt to balance DPLL power
- * saving (the least divider value "n") vs. rate fidelity (the least
- * difference between the desired DPLL target rate and the rounded
- * rate out of the algorithm).  So, increasing the tolerance is likely
- * to decrease DPLL power consumption and increase DPLL rate error.
- * Returns -EINVAL if provided a null clock ptr or a clk that is not a
- * DPLL; or 0 upon success.
- */
-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
-{
-        if (!clk || !clk->dpll_data)
-                return -EINVAL;
-
-        clk->dpll_data->rate_tolerance = tolerance;
-
-        return 0;
-}
-
-static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
-                                            unsigned int m, unsigned int n)
-{
-        unsigned long long num;
-
-        num = (unsigned long long)parent_rate * m;
-        do_div(num, n);
-        return num;
-}
-
-/*
- * _dpll_test_mult - test a DPLL multiplier value
- * @m: pointer to the DPLL m (multiplier) value under test
- * @n: current DPLL n (divider) value under test
- * @new_rate: pointer to storage for the resulting rounded rate
- * @target_rate: the desired DPLL rate
- * @parent_rate: the DPLL's parent clock rate
- *
- * This code tests a DPLL multiplier value, ensuring that the
- * resulting rate will not be higher than the target_rate, and that
- * the multiplier value itself is valid for the DPLL.  Initially, the
- * integer pointed to by the m argument should be prescaled by
- * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
- * a non-scaled m upon return.  This non-scaled m will result in a
- * new_rate as close as possible to target_rate (but not greater than
- * target_rate) given the current (parent_rate, n, prescaled m)
- * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
- * non-scaled m attempted to underflow, which can allow the calling
- * function to bail out early; or 0 upon success.
- */
-static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
-                           unsigned long target_rate,
-                           unsigned long parent_rate)
-{
-        int r = 0, carry = 0;
-
-        /* Unscale m and round if necessary */
-        if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
-                carry = 1;
-        *m = (*m / DPLL_SCALE_FACTOR) + carry;
-
-        /*
-         * The new rate must be <= the target rate to avoid programming
-         * a rate that is impossible for the hardware to handle
-         */
-        *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
-        if (*new_rate > target_rate) {
-                (*m)--;
-                *new_rate = 0;
-        }
-
-        /* Guard against m underflow */
-        if (*m < DPLL_MIN_MULTIPLIER) {
-                *m = DPLL_MIN_MULTIPLIER;
-                *new_rate = 0;
-                r = DPLL_MULT_UNDERFLOW;
-        }
-
-        if (*new_rate == 0)
-                *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
-
-        return r;
-}
-
-/**
- * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
- * @clk: struct clk * for a DPLL
- * @target_rate: desired DPLL clock rate
- *
- * Given a DPLL, a desired target rate, and a rate tolerance, round
- * the target rate to a possible, programmable rate for this DPLL.
- * Rate tolerance is assumed to be set by the caller before this
- * function is called.  Attempts to select the minimum possible n
- * within the tolerance to reduce power consumption.  Stores the
- * computed (m, n) in the DPLL's dpll_data structure so set_rate()
- * will not need to call this (expensive) function again.  Returns ~0
- * if the target rate cannot be rounded, either because the rate is
- * too low or because the rate tolerance is set too tightly; or the
- * rounded rate upon success.
- */
-long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
-{
-        int m, n, r, e, scaled_max_m;
-        unsigned long scaled_rt_rp, new_rate;
-        int min_e = -1, min_e_m = -1, min_e_n = -1;
-        struct dpll_data *dd;
-
-        if (!clk || !clk->dpll_data)
-                return ~0;
-
-        dd = clk->dpll_data;
-
-        pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
-                 "%ld\n", clk->name, target_rate);
-
-        scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
-        scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
-
-        dd->last_rounded_rate = 0;
-
-        for (n = dd->min_divider; n <= dd->max_divider; n++) {
-
-                /* Is the (input clk, divider) pair valid for the DPLL? */
-                r = _dpll_test_fint(clk, n);
-                if (r == DPLL_FINT_UNDERFLOW)
-                        break;
-                else if (r == DPLL_FINT_INVALID)
-                        continue;
-
-                /* Compute the scaled DPLL multiplier, based on the divider */
-                m = scaled_rt_rp * n;
-
-                /*
-                 * Since we're counting n up, a m overflow means we
-                 * can bail out completely (since as n increases in
-                 * the next iteration, there's no way that m can
-                 * increase beyond the current m)
-                 */
-                if (m > scaled_max_m)
-                        break;
-
-                r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-                                    dd->clk_ref->rate);
-
-                /* m can't be set low enough for this n - try with a larger n */
-                if (r == DPLL_MULT_UNDERFLOW)
-                        continue;
-
-                e = target_rate - new_rate;
-                pr_debug("clock: n = %d: m = %d: rate error is %d "
-                         "(new_rate = %ld)\n", n, m, e, new_rate);
-
-                if (min_e == -1 ||
-                    min_e >= (int)(abs(e) - dd->rate_tolerance)) {
-                        min_e = e;
-                        min_e_m = m;
-                        min_e_n = n;
-
-                        pr_debug("clock: found new least error %d\n", min_e);
-
-                        /* We found good settings -- bail out now */
-                        if (min_e <= dd->rate_tolerance)
-                                break;
-                }
-        }
-
-        if (min_e < 0) {
-                pr_debug("clock: error: target rate or tolerance too low\n");
-                return ~0;
-        }
-
-        dd->last_rounded_m = min_e_m;
-        dd->last_rounded_n = min_e_n;
-        dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
-                                                       min_e_m,  min_e_n);
-
-        pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
-                 min_e, min_e_m, min_e_n);
-        pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
-                 dd->last_rounded_rate, target_rate);
-
-        return dd->last_rounded_rate;
+        return omap2_clksel_set_parent(clk, new_parent);
 }
 
 /*-------------------------------------------------------------------------
@@ -1092,3 +351,20 @@ void omap2_clk_disable_unused(struct clk *clk)
                 pwrdm_clkdm_state_switch(clk->clkdm);
 }
 #endif
+
+/* Common data */
+
+struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+#ifdef CONFIG_CPU_FREQ
+        /* These will be removed when the OPP code is integrated */
+        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+        .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table,
+#endif
+};
+
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 93c48df3b5b1..7bc344bcbb47 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -47,7 +47,6 @@
 #define DPLL_LOW_POWER_BYPASS   0x5
 #define DPLL_LOCKED             0x7
 
-int omap2_clk_init(void);
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
@@ -78,19 +77,19 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
                                 u32 *new_div);
 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
-unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
 u32 omap2_get_dpll_rate(struct clk *clk);
 void omap2_init_dpll_parent(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
-void omap2_clk_prepare_for_reboot(void);
 int omap2_dflt_clk_enable(struct clk *clk);
 void omap2_dflt_clk_disable(struct clk *clk);
 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
                                    u8 *other_bit);
 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
                                 u8 *idlest_bit);
+void omap2xxx_clk_commit(struct clk *clk);
 
 extern u8 cpu_mask;
 
@@ -104,5 +103,12 @@ extern const struct clksel_rate gpt_32k_rates[];
 extern const struct clksel_rate gpt_sys_rates[];
 extern const struct clksel_rate gfx_l3_rates[];
 
+#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_CPU_FREQ)
+extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
+#else
+#define omap2_clk_init_cpufreq_table    0
+#define omap2_clk_exit_cpufreq_table    0
+#endif
 
 #endif
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 5420356eb407..a48b01ab0e35 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -1,15 +1,15 @@
 /*
- *  linux/arch/arm/mach-omap2/clock.c
+ * clock2xxx.c - OMAP2xxx-specific clock integration code
  *
- *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- *  Copyright (C) 2004-2008 Nokia Corporation
+ * Copyright (C) 2005-2008 Texas Instruments, Inc.
+ * Copyright (C) 2004-2010 Nokia Corporation
  *
- *  Contacts:
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Paul Walmsley
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
  *
- *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- *  Gordon McNutt and RidgeRun, Inc.
+ * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ * Gordon McNutt and RidgeRun, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,55 +17,25 @@
  */
 #undef DEBUG
 
-#include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
 #include <linux/errno.h>
-#include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <linux/cpufreq.h>
-#include <linux/bitops.h>
 
 #include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/prcm.h>
-#include <plat/clkdev_omap.h>
-#include <asm/div64.h>
-#include <asm/clkdev.h>
 
-#include <plat/sdrc.h>
 #include "clock.h"
 #include "clock2xxx.h"
-#include "opp2xxx.h"
-#include "prm.h"
-#include "prm-regbits-24xx.h"
 #include "cm.h"
 #include "cm-regbits-24xx.h"
 
-
-/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
-#define EN_APLL_STOPPED                 0
-#define EN_APLL_LOCKED                  3
-
-/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
-#define APLLS_CLKIN_19_2MHZ             0
-#define APLLS_CLKIN_13MHZ               2
-#define APLLS_CLKIN_12MHZ               3
-
-/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
-
-const struct prcm_config *curr_prcm_set;
-const struct prcm_config *rate_table;
-
 struct clk *vclk, *sclk, *dclk;
 
-void __iomem *prcm_clksrc_ctrl;
-
-/*-------------------------------------------------------------------------
+/*
  * Omap24xx specific clock functions
- *-------------------------------------------------------------------------*/
+ */
+
+#ifdef CONFIG_ARCH_OMAP2430
 
 /**
  * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
@@ -86,6 +56,10 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
         *idlest_bit = clk->enable_bit;
 }
 
+#else
+#define omap2430_clk_i2chs_find_idlest  NULL
+#endif
+
 /* 2430 I2CHS has non-standard IDLEST register */
 const struct clkops clkops_omap2430_i2chs_wait = {
         .enable         = omap2_dflt_clk_enable,
@@ -94,491 +68,10 @@ const struct clkops clkops_omap2430_i2chs_wait = {
         .find_companion = omap2_clk_dflt_find_companion,
 };
 
-/**
- * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
- * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
- *
- * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
- * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
- * (the latter is unusual).  This currently should be called with
- * struct clk *dpll_ck, which is a composite clock of dpll_ck and
- * core_ck.
- */
-unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
-{
-        long long core_clk;
-        u32 v;
-
-        core_clk = omap2_get_dpll_rate(clk);
-
-        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        v &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if (v == CORE_CLK_SRC_32K)
-                core_clk = 32768;
-        else
-                core_clk *= v;
-
-        return core_clk;
-}
-
-static int omap2_enable_osc_ck(struct clk *clk)
-{
-        u32 pcc;
-
-        pcc = __raw_readl(prcm_clksrc_ctrl);
-
-        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-
-        return 0;
-}
-
-static void omap2_disable_osc_ck(struct clk *clk)
-{
-        u32 pcc;
-
-        pcc = __raw_readl(prcm_clksrc_ctrl);
-
-        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-}
-
-const struct clkops clkops_oscck = {
-        .enable         = omap2_enable_osc_ck,
-        .disable        = omap2_disable_osc_ck,
-};
-
-#ifdef OLD_CK
-/* Recalculate SYST_CLK */
-static void omap2_sys_clk_recalc(struct clk *clk)
-{
-        u32 div = PRCM_CLKSRC_CTRL;
-        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
-        div >>= clk->rate_offset;
-        clk->rate = (clk->parent->rate / div);
-        propagate_rate(clk);
-}
-#endif  /* OLD_CK */
-
-/* Enable an APLL if off */
-static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
-{
-        u32 cval, apll_mask;
-
-        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
-
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-
-        if ((cval & apll_mask) == apll_mask)
-                return 0;   /* apll already enabled */
-
-        cval &= ~apll_mask;
-        cval |= apll_mask;
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-
-        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
-                             clk->name);
-
-        /*
-         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
-         * fails?
-         */
-        return 0;
-}
-
-static int omap2_clk_apll96_enable(struct clk *clk)
-{
-        return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
-}
-
-static int omap2_clk_apll54_enable(struct clk *clk)
-{
-        return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
-}
-
-/* Stop APLL */
-static void omap2_clk_apll_disable(struct clk *clk)
-{
-        u32 cval;
-
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-}
-
-const struct clkops clkops_apll96 = {
-        .enable         = omap2_clk_apll96_enable,
-        .disable        = omap2_clk_apll_disable,
-};
-
-const struct clkops clkops_apll54 = {
-        .enable         = omap2_clk_apll54_enable,
-        .disable        = omap2_clk_apll_disable,
-};
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-long omap2_dpllcore_round_rate(unsigned long target_rate)
-{
-        u32 high, low, core_clk_src;
-
-        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
-                high = curr_prcm_set->dpll_speed * 2;
-                low = curr_prcm_set->dpll_speed;
-        } else {                                /* DPLL clockout x 2 */
-                high = curr_prcm_set->dpll_speed;
-                low = curr_prcm_set->dpll_speed / 2;
-        }
-
-#ifdef DOWN_VARIABLE_DPLL
-        if (target_rate > high)
-                return high;
-        else
-                return target_rate;
-#else
-        if (target_rate > low)
-                return high;
-        else
-                return low;
-#endif
-
-}
-
-unsigned long omap2_dpllcore_recalc(struct clk *clk)
-{
-        return omap2xxx_clk_get_core_rate(clk);
-}
-
-int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
-{
-        u32 cur_rate, low, mult, div, valid_rate, done_rate;
-        u32 bypass = 0;
-        struct prcm_config tmpset;
-        const struct dpll_data *dd;
-
-        cur_rate = omap2xxx_clk_get_core_rate(dclk);
-        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if ((rate == (cur_rate / 2)) && (mult == 2)) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
-        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-        } else if (rate != cur_rate) {
-                valid_rate = omap2_dpllcore_round_rate(rate);
-                if (valid_rate != rate)
-                        return -EINVAL;
-
-                if (mult == 1)
-                        low = curr_prcm_set->dpll_speed;
-                else
-                        low = curr_prcm_set->dpll_speed / 2;
-
-                dd = clk->dpll_data;
-                if (!dd)
-                        return -EINVAL;
-
-                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
-                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
-                                           dd->div1_mask);
-                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
-                if (rate > low) {
-                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
-                        mult = ((rate / 2) / 1000000);
-                        done_rate = CORE_CLK_SRC_DPLL_X2;
-                } else {
-                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
-                        mult = (rate / 1000000);
-                        done_rate = CORE_CLK_SRC_DPLL;
-                }
-                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
-                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
-
-                /* Worst case */
-                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
-
-                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
-                        bypass = 1;
-
-                /* For omap2xxx_sdrc_init_params() */
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
-                /* Force dll lock mode */
-                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
-                               bypass);
-
-                /* Errata: ret dll entry state */
-                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
-                omap2xxx_sdrc_reprogram(done_rate, 0);
-        }
-
-        return 0;
-}
-
-/**
- * omap2_table_mpu_recalc - just return the MPU speed
- * @clk: virt_prcm_set struct clk
- *
- * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
- */
-unsigned long omap2_table_mpu_recalc(struct clk *clk)
-{
-        return curr_prcm_set->mpu_speed;
-}
-
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
- *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
- */
-long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
-{
-        const struct prcm_config *ptr;
-        long highest_rate;
-        long sys_ck_rate;
-
-        sys_ck_rate = clk_get_rate(sclk);
-
-        highest_rate = -EINVAL;
-
-        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
-                if (!(ptr->flags & cpu_mask))
-                        continue;
-                if (ptr->xtal_speed != sys_ck_rate)
-                        continue;
-
-                highest_rate = ptr->mpu_speed;
-
-                /* Can check only after xtal frequency check */
-                if (ptr->mpu_speed <= rate)
-                        break;
-        }
-        return highest_rate;
-}
-
-/* Sets basic clocks based on the specified rate */
-int omap2_select_table_rate(struct clk *clk, unsigned long rate)
-{
-        u32 cur_rate, done_rate, bypass = 0, tmp;
-        const struct prcm_config *prcm;
-        unsigned long found_speed = 0;
-        unsigned long flags;
-        long sys_ck_rate;
-
-        sys_ck_rate = clk_get_rate(sclk);
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-
-                if (prcm->xtal_speed != sys_ck_rate)
-                        continue;
-
-                if (prcm->mpu_speed <= rate) {
-                        found_speed = prcm->mpu_speed;
-                        break;
-                }
-        }
-
-        if (!found_speed) {
-                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
-                       rate / 1000000);
-                return -EINVAL;
-        }
-
-        curr_prcm_set = prcm;
-        cur_rate = omap2xxx_clk_get_core_rate(dclk);
-
-        if (prcm->dpll_speed == cur_rate / 2) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
-        } else if (prcm->dpll_speed == cur_rate * 2) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-        } else if (prcm->dpll_speed != cur_rate) {
-                local_irq_save(flags);
-
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        bypass = 1;
-
-                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
-                    CORE_CLK_SRC_DPLL_X2)
-                        done_rate = CORE_CLK_SRC_DPLL_X2;
-                else
-                        done_rate = CORE_CLK_SRC_DPLL;
-
-                /* MPU divider */
-                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
-
-                /* dsp + iva1 div(2420), iva2.1(2430) */
-                cm_write_mod_reg(prcm->cm_clksel_dsp,
-                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
-
-                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
-
-                /* Major subsystem dividers */
-                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
-                                 CM_CLKSEL1);
-
-                if (cpu_is_omap2430())
-                        cm_write_mod_reg(prcm->cm_clksel_mdm,
-                                         OMAP2430_MDM_MOD, CM_CLKSEL);
-
-                /* x2 to enter omap2xxx_sdrc_init_params() */
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
-                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
-                               bypass);
-
-                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
-                omap2xxx_sdrc_reprogram(done_rate, 0);
-
-                local_irq_restore(flags);
-        }
-
-        return 0;
-}
-
-#ifdef CONFIG_CPU_FREQ
-/*
- * Walk PRCM rate table and fillout cpufreq freq_table
- * XXX This should be replaced by an OPP layer in the near future
- */
-static struct cpufreq_frequency_table *freq_table;
-
-void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
-{
-        const struct prcm_config *prcm;
-        long sys_ck_rate;
-        int i = 0;
-        int tbl_sz = 0;
-
-        sys_ck_rate = clk_get_rate(sclk);
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck_rate)
-                        continue;
-
-                /* don't put bypass rates in table */
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        continue;
-
-                tbl_sz++;
-        }
-
-        /*
-         * XXX Ensure that we're doing what CPUFreq expects for this error
-         * case and the following one
-         */
-        if (tbl_sz == 0) {
-                pr_warning("%s: no matching entries in rate_table\n",
-                           __func__);
-                return;
-        }
-
-        /* Include the CPUFREQ_TABLE_END terminator entry */
-        tbl_sz++;
-
-        freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz,
-                             GFP_ATOMIC);
-        if (!freq_table) {
-                pr_err("%s: could not kzalloc frequency table\n", __func__);
-                return;
-        }
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck_rate)
-                        continue;
-
-                /* don't put bypass rates in table */
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        continue;
-
-                freq_table[i].index = i;
-                freq_table[i].frequency = prcm->mpu_speed / 1000;
-                i++;
-        }
-
-        freq_table[i].index = i;
-        freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        *table = &freq_table[0];
-}
-
-void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
-{
-        kfree(freq_table);
-}
-
-#endif
-
-struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-#ifdef  CONFIG_CPU_FREQ
-        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
-        .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table,
-#endif
-};
-
-static u32 omap2_get_apll_clkin(void)
-{
-        u32 aplls, srate = 0;
-
-        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
-        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
-        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
-
-        if (aplls == APLLS_CLKIN_19_2MHZ)
-                srate = 19200000;
-        else if (aplls == APLLS_CLKIN_13MHZ)
-                srate = 13000000;
-        else if (aplls == APLLS_CLKIN_12MHZ)
-                srate = 12000000;
-
-        return srate;
-}
-
-static u32 omap2_get_sysclkdiv(void)
-{
-        u32 div;
-
-        div = __raw_readl(prcm_clksrc_ctrl);
-        div &= OMAP_SYSCLKDIV_MASK;
-        div >>= OMAP_SYSCLKDIV_SHIFT;
-
-        return div;
-}
-
-unsigned long omap2_osc_clk_recalc(struct clk *clk)
-{
-        return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
-}
-
-unsigned long omap2_sys_clk_recalc(struct clk *clk)
-{
-        return clk->parent->rate / omap2_get_sysclkdiv();
-}
-
 /*
  * Set clocks for bypass mode for reboot to work.
  */
-void omap2_clk_prepare_for_reboot(void)
+void omap2xxx_clk_prepare_for_reboot(void)
 {
         u32 rate;
 
@@ -593,11 +86,14 @@ void omap2_clk_prepare_for_reboot(void)
  * Switch the MPU rate if specified on cmdline.
  * We cannot do this early until cmdline is parsed.
  */
-static int __init omap2_clk_arch_init(void)
+static int __init omap2xxx_clk_arch_init(void)
 {
         struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
         unsigned long sys_ck_rate;
 
+        if (!cpu_is_omap24xx())
+                return 0;
+
         if (!mpurate)
                 return -EINVAL;
 
@@ -621,6 +117,6 @@ static int __init omap2_clk_arch_init(void)
 
         return 0;
 }
-arch_initcall(omap2_clk_arch_init);
+arch_initcall(omap2xxx_clk_arch_init);
 
 
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index e35efde4bd80..32f3d0aa8fc4 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -11,12 +11,15 @@
 unsigned long omap2_table_mpu_recalc(struct clk *clk);
 int omap2_select_table_rate(struct clk *clk, unsigned long rate);
 long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
-unsigned long omap2_sys_clk_recalc(struct clk *clk);
+unsigned long omap2xxx_sys_clk_recalc(struct clk *clk);
 unsigned long omap2_osc_clk_recalc(struct clk *clk);
-unsigned long omap2_sys_clk_recalc(struct clk *clk);
 unsigned long omap2_dpllcore_recalc(struct clk *clk);
 int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
 unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
+u32 omap2xxx_get_apll_clkin(void);
+u32 omap2xxx_get_sysclkdiv(void);
+void omap2xxx_clk_prepare_for_reboot(void);
+int omap2xxx_clk_init(void);
 
 /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
 #ifdef CONFIG_ARCH_OMAP2420
diff --git a/arch/arm/mach-omap2/clock2xxx_data.c b/arch/arm/mach-omap2/clock2xxx_data.c
index 97dc7cf7751d..52c7a6c2d9e0 100644
--- a/arch/arm/mach-omap2/clock2xxx_data.c
+++ b/arch/arm/mach-omap2/clock2xxx_data.c
@@ -79,7 +79,7 @@ static struct clk sys_ck = {		/* (*12, *13, 19.2, 26, 38.4)MHz */
         .ops            = &clkops_null,
         .parent         = &osc_ck,
         .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_sys_clk_recalc,
+        .recalc         = &omap2xxx_sys_clk_recalc,
 };
 
 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
@@ -261,7 +261,7 @@ static struct clk func_12m_ck = {
         .parent         = &func_48m_ck,
         .fixed_div      = 4,
         .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_fixed_divisor_recalc,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 /* Secure timer, only available in secure mode */
@@ -557,7 +557,7 @@ static struct clk iva1_mpu_int_ifck = {
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
         .fixed_div      = 2,
-        .recalc         = &omap2_fixed_divisor_recalc,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 /*
@@ -2238,7 +2238,7 @@ static struct omap_clk omap24xx_clks[] = {
  * init code
  */
 
-int __init omap2_clk_init(void)
+int __init omap2xxx_clk_init(void)
 {
         const struct prcm_config *prcm;
         struct omap_clk *c;
@@ -2264,7 +2264,7 @@ int __init omap2_clk_init(void)
 
         osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
         propagate_rate(&osc_ck);
-        sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
+        sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
         propagate_rate(&sys_ck);
 
         for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index d4217b93e10b..1f1b5a6b3eea 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,10 +2,10 @@
  * OMAP3-specific clock framework functions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2010 Nokia Corporation
  *
- * Written by Paul Walmsley
- * Testing and integration fixes by Jouni Högander
+ * Paul Walmsley
+ * Jouni Högander
  *
  * Parts of this code are based on code written by
  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
@@ -16,34 +16,22 @@
  */
 #undef DEBUG
 
-#include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <linux/limits.h>
-#include <linux/bitops.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/sdrc.h>
-#include <asm/div64.h>
-#include <asm/clkdev.h>
 
 #include "clock.h"
 #include "clock34xx.h"
-#include "sdrc.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
 
-#define CYCLES_PER_MHZ                  1000000
-
 /*
  * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
  * that are sourced by DPLL5, and both of these require this clock
@@ -162,129 +150,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
         return omap3_noncore_dpll_set_rate(clk, rate);
 }
 
-
-/*
- * CORE DPLL (DPLL3) rate programming functions
- *
- * These call into SRAM code to do the actual CM writes, since the SDRAM
- * is clocked from DPLL3.
- */
-
-/**
- * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
- * @clk: struct clk * of DPLL to set
- * @rate: rounded target rate
- *
- * Program the DPLL M2 divider with the rounded target rate.  Returns
- * -EINVAL upon error, or 0 upon success.
- */
-int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 new_div = 0;
-        u32 unlock_dll = 0;
-        u32 c;
-        unsigned long validrate, sdrcrate, _mpurate;
-        struct omap_sdrc_params *sdrc_cs0;
-        struct omap_sdrc_params *sdrc_cs1;
-        int ret;
-
-        if (!clk || !rate)
-                return -EINVAL;
-
-        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
-        if (validrate != rate)
-                return -EINVAL;
-
-        sdrcrate = sdrc_ick_p->rate;
-        if (rate > clk->rate)
-                sdrcrate <<= ((rate / clk->rate) >> 1);
-        else
-                sdrcrate >>= ((clk->rate / rate) >> 1);
-
-        ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
-        if (ret)
-                return -EINVAL;
-
-        if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
-                pr_debug("clock: will unlock SDRC DLL\n");
-                unlock_dll = 1;
-        }
-
-        /*
-         * XXX This only needs to be done when the CPU frequency changes
-         */
-        _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
-        c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
-        c += 1;  /* for safety */
-        c *= SDRC_MPURATE_LOOPS;
-        c >>= SDRC_MPURATE_SCALE;
-        if (c == 0)
-                c = 1;
-
-        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
-                 validrate);
-        pr_debug("clock: SDRC CS0 timing params used:"
-                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
-                 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
-                 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
-        if (sdrc_cs1)
-                pr_debug("clock: SDRC CS1 timing params used: "
-                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
-                 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
-                 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
-
-        if (sdrc_cs1)
-                omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
-                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
-                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
-                                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
-                                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
-        else
-                omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
-                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
-                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
-                                  0, 0, 0, 0);
-
-        return 0;
-}
-
-/* Common clock code */
-
-/*
- * As it is structured now, this will prevent an OMAP2/3 multiboot
- * kernel from compiling.  This will need further attention.
- */
-#if defined(CONFIG_ARCH_OMAP3)
-
-struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-};
-
-/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2_clk_prepare_for_reboot(void)
-{
-        /* REVISIT: Not ready for 343x */
-#if 0
-        u32 rate;
-
-        if (vclk == NULL || sclk == NULL)
-                return;
-
-        rate = clk_get_rate(sclk);
-        clk_set_rate(vclk, rate);
-#endif
-}
-
-void omap3_clk_lock_dpll5(void)
+void __init omap3_clk_lock_dpll5(void)
 {
         struct clk *dpll5_clk;
         struct clk *dpll5_m2_clk;
@@ -306,17 +172,22 @@ void omap3_clk_lock_dpll5(void)
         return;
 }
 
+/* Common clock code */
+
 /* REVISIT: Move this init stuff out into clock.c */
 
 /*
  * Switch the MPU rate if specified on cmdline.
  * We cannot do this early until cmdline is parsed.
  */
-static int __init omap2_clk_arch_init(void)
+static int __init omap3xxx_clk_arch_init(void)
 {
         struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
         unsigned long osc_sys_rate;
 
+        if (!cpu_is_omap34xx())
+                return 0;
+
         if (!mpurate)
                 return -EINVAL;
 
@@ -345,9 +216,6 @@ static int __init omap2_clk_arch_init(void)
 
         return 0;
 }
-arch_initcall(omap2_clk_arch_init);
-
-
-#endif
+arch_initcall(omap3xxx_clk_arch_init);
 
 
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 9a2c07eac9ad..73f2109d6436 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -8,6 +8,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
 
+int omap3xxx_clk_init(void);
 int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
 void omap3_clk_lock_dpll5(void);
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index 74930e3158e3..0d04f92f63e1 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -735,7 +735,7 @@ static struct clk omap_12m_fck = {
         .ops            = &clkops_null,
         .parent         = &omap_48m_fck,
         .fixed_div      = 4,
-        .recalc         = &omap2_fixed_divisor_recalc,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 /* This virstual clock is the source for dpll4_m4x2_ck */
@@ -1588,7 +1588,7 @@ static struct clk ssi_sst_fck_3430es1 = {
         .ops            = &clkops_null,
         .parent         = &ssi_ssr_fck_3430es1,
         .fixed_div      = 2,
-        .recalc         = &omap2_fixed_divisor_recalc,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static struct clk ssi_sst_fck_3430es2 = {
@@ -1596,7 +1596,7 @@ static struct clk ssi_sst_fck_3430es2 = {
         .ops            = &clkops_null,
         .parent         = &ssi_ssr_fck_3430es2,
         .fixed_div      = 2,
-        .recalc         = &omap2_fixed_divisor_recalc,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 
@@ -2988,139 +2988,140 @@ static struct clk wdt1_fck = {
  * clkdev
  */
 
-static struct omap_clk omap34xx_clks[] = {
-        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
-        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
-        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
-        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
-        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
-        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
-        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
-        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
-        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
-        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
-        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
-        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
-        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
+/* XXX At some point we should rename this file to clock3xxx_data.c */
+static struct omap_clk omap3xxx_clks[] = {
+        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
+        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
+        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
+        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
+        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
+        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
+        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
-        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
-        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
-        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
-        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
-        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
-        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
-        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
-        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
-        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
-        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
-        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
-        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
-        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
-        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
-        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
-        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
-        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
-        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
-        CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
-        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
+        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
+        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
+        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
+        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
+        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
+        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
+        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
+        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
+        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
+        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
+        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
+        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
+        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
+        CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
+        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
-        CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
-        CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
-        CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
+        CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
+        CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
+        CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2 | CK_3517),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2 | CK_3517),
         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
         CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
-        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
-        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
-        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
-        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
-        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
-        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
+        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2 | CK_AM35XX),
+        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
-        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
-        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
-        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
-        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
-        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
-        CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
-        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
-        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
-        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
+        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_3XXX),
+        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_3XXX),
+        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_3XXX),
+        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_3XXX),
+        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_3XXX),
+        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_3XXX),
+        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
+        CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_3XXX),
+        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_3XXX),
+        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_3XXX),
+        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_3XXX),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
-        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
-        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
+        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
+        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_3XXX),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
-        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
+        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
-        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
-        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
-        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
+        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2 | CK_AM35XX),
+        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2 | CK_AM35XX),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
         CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
         CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
         CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
-        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
-        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
+        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
+        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_3XXX),
         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
-        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
-        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
+        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
+        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_3XXX),
+        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_3XXX),
+        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
@@ -3131,96 +3132,100 @@ static struct omap_clk omap34xx_clks[] = {
         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
         CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
-        CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_343X),
-        CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_343X),
-        CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_343X),
+        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
+        CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_3XXX),
+        CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_3XXX),
+        CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_3XXX),
         CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
-        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2),
+        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2 | CK_AM35XX),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
-        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
-        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
-        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2 | CK_AM35XX),
         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
-        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
-        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
-        CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
+        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
+        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
+        CLK("omap_wdt", "fck",          &wdt2_fck,      CK_3XXX),
         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
-        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
-        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
-        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
-        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
-        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
-        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
-        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
-        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
-        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
-        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
-        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
-        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
-        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
-        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
-        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
-        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
-        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
-        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
-        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
-        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_343X),
-        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
-        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
-        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
-        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
-        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
+        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
+        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
+        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
+        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
+        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
+        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
+        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
+        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
+        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
+        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
+        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
+        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
+        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
+        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_3XXX),
+        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_3XXX),
+        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_3XXX),
+        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
+        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
+        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
+        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
+        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
+        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
-        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
-        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
+        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
+        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
 };
 
 
-int __init omap2_clk_init(void)
+int __init omap3xxx_clk_init(void)
 {
-        /* struct prcm_config *prcm; */
         struct omap_clk *c;
-        /* u32 clkrate; */
-        u32 cpu_clkflg;
-
-        if (cpu_is_omap34xx()) {
+        u32 cpu_clkflg = CK_3XXX;
+
+        if (cpu_is_omap3517()) {
+                cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
+                cpu_clkflg |= CK_3517;
+        } else if (cpu_is_omap3505()) {
+                cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
+                cpu_clkflg |= CK_3505;
+        } else if (cpu_is_omap34xx()) {
                 cpu_mask = RATE_IN_343X;
-                cpu_clkflg = CK_343X;
+                cpu_clkflg |= CK_343X;
 
                 /*
                  * Update this if there are further clock changes between ES2
@@ -3237,31 +3242,16 @@ int __init omap2_clk_init(void)
 
         clk_init(&omap2_clk_functions);
 
-        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
                 clk_preinit(c->lk.clk);
 
-        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
                 if (c->cpu & cpu_clkflg) {
                         clkdev_add(&c->lk);
                         clk_register(c->lk.clk);
                         omap2_init_clk_clkdm(c->lk.clk);
                 }
 
-        /* REVISIT: Not yet ready for OMAP3 */
-#if 0
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                        break;
-        }
-        curr_prcm_set = prcm;
-#endif
-
         recalculate_root_clocks();
 
         printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c
index e370868a79a8..c238717e3760 100644
--- a/arch/arm/mach-omap2/clock44xx.c
+++ b/arch/arm/mach-omap2/clock44xx.c
@@ -13,21 +13,7 @@
 #include <linux/errno.h>
 #include "clock.h"
 
-struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-};
-
 const struct clkops clkops_noncore_dpll_ops = {
         .enable         = &omap3_noncore_dpll_enable,
         .disable        = &omap3_noncore_dpll_disable,
 };
-
-void omap2_clk_prepare_for_reboot(void)
-{
-        return;
-}
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
index 59b9ced4daa1..1f55b6b574fb 100644
--- a/arch/arm/mach-omap2/clock44xx.h
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -10,6 +10,8 @@
 #define OMAP4430_MAX_DPLL_MULT  2048
 #define OMAP4430_MAX_DPLL_DIV   128
 
+int omap4xxx_clk_init(void);
+
 extern const struct clkops clkops_noncore_dpll_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 9d882bcb56e3..35ffe638def8 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -2726,11 +2726,9 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "utmi_p2_gfclk_ck",             &utmi_p2_gfclk_ck,      CK_443X),
 };
 
-int __init omap2_clk_init(void)
+int __init omap4xxx_clk_init(void)
 {
-        /* struct prcm_config *prcm; */
         struct omap_clk *c;
-        /* u32 clkrate; */
         u32 cpu_clkflg;
 
         if (cpu_is_omap44xx()) {
@@ -2749,9 +2747,7 @@ int __init omap2_clk_init(void)
                 if (c->cpu & cpu_clkflg) {
                         clkdev_add(&c->lk);
                         clk_register(c->lk.clk);
-                        /* TODO
                         omap2_init_clk_clkdm(c->lk.clk);
-                        */
                 }
 
         recalculate_root_clocks();
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index dd285f001467..a38a615b422f 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1,10 +1,11 @@
 /*
- * OMAP2/3 clockdomain framework functions
+ * OMAP2/3/4 clockdomain framework functions
  *
- * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
  * Copyright (C) 2008-2009 Nokia Corporation
  *
  * Written by Paul Walmsley and Jouni Högander
+ * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -26,43 +27,124 @@
 
 #include <linux/bitops.h>
 
-#include <plat/clock.h>
-
 #include "prm.h"
 #include "prm-regbits-24xx.h"
 #include "cm.h"
 
+#include <plat/clock.h>
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
+#include <plat/prcm.h>
 
 /* clkdm_list contains all registered struct clockdomains */
 static LIST_HEAD(clkdm_list);
 
-/* clkdm_mutex protects clkdm_list add and del ops */
-static DEFINE_MUTEX(clkdm_mutex);
-
-/* array of powerdomain deps to be added/removed when clkdm in hwsup mode */
-static struct clkdm_pwrdm_autodep *autodeps;
+/* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
+static struct clkdm_autodep *autodeps;
 
 
 /* Private functions */
 
+static struct clockdomain *_clkdm_lookup(const char *name)
+{
+        struct clockdomain *clkdm, *temp_clkdm;
+
+        if (!name)
+                return NULL;
+
+        clkdm = NULL;
+
+        list_for_each_entry(temp_clkdm, &clkdm_list, node) {
+                if (!strcmp(name, temp_clkdm->name)) {
+                        clkdm = temp_clkdm;
+                        break;
+                }
+        }
+
+        return clkdm;
+}
+
+/**
+ * _clkdm_register - register a clockdomain
+ * @clkdm: struct clockdomain * to register
+ *
+ * Adds a clockdomain to the internal clockdomain list.
+ * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
+ * already registered by the provided name, or 0 upon success.
+ */
+static int _clkdm_register(struct clockdomain *clkdm)
+{
+        struct powerdomain *pwrdm;
+
+        if (!clkdm || !clkdm->name)
+                return -EINVAL;
+
+        if (!omap_chip_is(clkdm->omap_chip))
+                return -EINVAL;
+
+        pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
+        if (!pwrdm) {
+                pr_err("clockdomain: %s: powerdomain %s does not exist\n",
+                        clkdm->name, clkdm->pwrdm.name);
+                return -EINVAL;
+        }
+        clkdm->pwrdm.ptr = pwrdm;
+
+        /* Verify that the clockdomain is not already registered */
+        if (_clkdm_lookup(clkdm->name))
+                return -EEXIST;
+
+        list_add(&clkdm->node, &clkdm_list);
+
+        pwrdm_add_clkdm(pwrdm, clkdm);
+
+        pr_debug("clockdomain: registered %s\n", clkdm->name);
+
+        return 0;
+}
+
+/* _clkdm_deps_lookup - look up the specified clockdomain in a clkdm list */
+static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
+                                            struct clkdm_dep *deps)
+{
+        struct clkdm_dep *cd;
+
+        if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip))
+                return ERR_PTR(-EINVAL);
+
+        for (cd = deps; cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+
+                if (!cd->clkdm && cd->clkdm_name)
+                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+
+                if (cd->clkdm == clkdm)
+                        break;
+        }
+
+        if (!cd->clkdm_name)
+                return ERR_PTR(-ENOENT);
+
+        return cd;
+}
+
 /*
- * _autodep_lookup - resolve autodep pwrdm names to pwrdm pointers; store
- * @autodep: struct clkdm_pwrdm_autodep * to resolve
+ * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
+ * @autodep: struct clkdm_autodep * to resolve
  *
- * Resolve autodep powerdomain names to powerdomain pointers via
- * pwrdm_lookup() and store the pointers in the autodep structure.  An
- * "autodep" is a powerdomain sleep/wakeup dependency that is
+ * Resolve autodep clockdomain names to clockdomain pointers via
+ * clkdm_lookup() and store the pointers in the autodep structure.  An
+ * "autodep" is a clockdomain sleep/wakeup dependency that is
  * automatically added and removed whenever clocks in the associated
  * clockdomain are enabled or disabled (respectively) when the
  * clockdomain is in hardware-supervised mode.  Meant to be called
  * once at clockdomain layer initialization, since these should remain
  * fixed for a particular architecture.  No return value.
  */
-static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
+static void _autodep_lookup(struct clkdm_autodep *autodep)
 {
-        struct powerdomain *pwrdm;
+        struct clockdomain *clkdm;
 
         if (!autodep)
                 return;
@@ -70,13 +152,13 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
         if (!omap_chip_is(autodep->omap_chip))
                 return;
 
-        pwrdm = pwrdm_lookup(autodep->pwrdm.name);
-        if (!pwrdm) {
-                pr_err("clockdomain: autodeps: powerdomain %s does not exist\n",
-                         autodep->pwrdm.name);
-                pwrdm = ERR_PTR(-ENOENT);
+        clkdm = clkdm_lookup(autodep->clkdm.name);
+        if (!clkdm) {
+                pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
+                         autodep->clkdm.name);
+                clkdm = ERR_PTR(-ENOENT);
         }
-        autodep->pwrdm.ptr = pwrdm;
+        autodep->clkdm.ptr = clkdm;
 }
 
 /*
@@ -89,21 +171,21 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
  */
 static void _clkdm_add_autodeps(struct clockdomain *clkdm)
 {
-        struct clkdm_pwrdm_autodep *autodep;
+        struct clkdm_autodep *autodep;
 
-        for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
-                if (IS_ERR(autodep->pwrdm.ptr))
+        for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+                if (IS_ERR(autodep->clkdm.ptr))
                         continue;
 
                 if (!omap_chip_is(autodep->omap_chip))
                         continue;
 
                 pr_debug("clockdomain: adding %s sleepdep/wkdep for "
-                         "pwrdm %s\n", autodep->pwrdm.ptr->name,
-                         clkdm->pwrdm.ptr->name);
+                         "clkdm %s\n", autodep->clkdm.ptr->name,
+                         clkdm->name);
 
-                pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
-                pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
+                clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
+                clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
         }
 }
 
@@ -117,21 +199,21 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
  */
 static void _clkdm_del_autodeps(struct clockdomain *clkdm)
 {
-        struct clkdm_pwrdm_autodep *autodep;
+        struct clkdm_autodep *autodep;
 
-        for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
-                if (IS_ERR(autodep->pwrdm.ptr))
+        for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+                if (IS_ERR(autodep->clkdm.ptr))
                         continue;
 
                 if (!omap_chip_is(autodep->omap_chip))
                         continue;
 
                 pr_debug("clockdomain: removing %s sleepdep/wkdep for "
-                         "pwrdm %s\n", autodep->pwrdm.ptr->name,
-                         clkdm->pwrdm.ptr->name);
+                         "clkdm %s\n", autodep->clkdm.ptr->name,
+                         clkdm->name);
 
-                pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
-                pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
+                clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
+                clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
         }
 }
 
@@ -145,152 +227,167 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
  */
 static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
 {
-        u32 v;
+        u32 bits, v;
 
         if (cpu_is_omap24xx()) {
                 if (enable)
-                        v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
+                        bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
                 else
-                        v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
-        } else if (cpu_is_omap34xx()) {
+                        bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
+        } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
                 if (enable)
-                        v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
+                        bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
                 else
-                        v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
+                        bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
         } else {
                 BUG();
         }
 
-        cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
-                            v << __ffs(clkdm->clktrctrl_mask),
-                            clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
-}
-
-static struct clockdomain *_clkdm_lookup(const char *name)
-{
-        struct clockdomain *clkdm, *temp_clkdm;
-
-        if (!name)
-                return NULL;
+        bits = bits << __ffs(clkdm->clktrctrl_mask);
 
-        clkdm = NULL;
+        v = __raw_readl(clkdm->clkstctrl_reg);
+        v &= ~(clkdm->clktrctrl_mask);
+        v |= bits;
+        __raw_writel(v, clkdm->clkstctrl_reg);
 
-        list_for_each_entry(temp_clkdm, &clkdm_list, node) {
-                if (!strcmp(name, temp_clkdm->name)) {
-                        clkdm = temp_clkdm;
-                        break;
-                }
-        }
-
-        return clkdm;
 }
 
-
-/* Public functions */
-
 /**
- * clkdm_init - set up the clockdomain layer
- * @clkdms: optional pointer to an array of clockdomains to register
- * @init_autodeps: optional pointer to an array of autodeps to register
+ * _init_wkdep_usecount - initialize wkdep usecounts to match hardware
+ * @clkdm: clockdomain to initialize wkdep usecounts
  *
- * Set up internal state.  If a pointer to an array of clockdomains
- * was supplied, loop through the list of clockdomains, register all
- * that are available on the current platform.  Similarly, if a
- * pointer to an array of clockdomain-powerdomain autodependencies was
- * provided, register those.  No return value.
+ * Initialize the wakeup dependency usecount variables for clockdomain @clkdm.
+ * If a wakeup dependency is present in the hardware, the usecount will be
+ * set to 1; otherwise, it will be set to 0.  Software should clear all
+ * software wakeup dependencies prior to calling this function if it wishes
+ * to ensure that all usecounts start at 0.  No return value.
  */
-void clkdm_init(struct clockdomain **clkdms,
-                struct clkdm_pwrdm_autodep *init_autodeps)
+static void _init_wkdep_usecount(struct clockdomain *clkdm)
 {
-        struct clockdomain **c = NULL;
-        struct clkdm_pwrdm_autodep *autodep = NULL;
+        u32 v;
+        struct clkdm_dep *cd;
 
-        if (clkdms)
-                for (c = clkdms; *c; c++)
-                        clkdm_register(*c);
+        if (!clkdm->wkdep_srcs)
+                return;
 
-        autodeps = init_autodeps;
-        if (autodeps)
-                for (autodep = autodeps; autodep->pwrdm.ptr; autodep++)
-                        _autodep_lookup(autodep);
+        for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+
+                if (!cd->clkdm && cd->clkdm_name)
+                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+
+                if (!cd->clkdm) {
+                        WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not "
+                             "found\n", clkdm->name, cd->clkdm_name);
+                        continue;
+                }
+
+                v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
+                                            PM_WKDEP,
+                                            (1 << cd->clkdm->dep_bit));
+
+                if (v)
+                        pr_debug("clockdomain: %s: wakeup dependency already "
+                                 "set to wake up when %s wakes\n",
+                                 clkdm->name, cd->clkdm->name);
+
+                atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0);
+        }
 }
 
 /**
- * clkdm_register - register a clockdomain
- * @clkdm: struct clockdomain * to register
+ * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware
+ * @clkdm: clockdomain to initialize sleepdep usecounts
  *
- * Adds a clockdomain to the internal clockdomain list.
- * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
- * already registered by the provided name, or 0 upon success.
+ * Initialize the sleep dependency usecount variables for clockdomain @clkdm.
+ * If a sleep dependency is present in the hardware, the usecount will be
+ * set to 1; otherwise, it will be set to 0.  Software should clear all
+ * software sleep dependencies prior to calling this function if it wishes
+ * to ensure that all usecounts start at 0.  No return value.
  */
-int clkdm_register(struct clockdomain *clkdm)
+static void _init_sleepdep_usecount(struct clockdomain *clkdm)
 {
-        int ret = -EINVAL;
-        struct powerdomain *pwrdm;
+        u32 v;
+        struct clkdm_dep *cd;
 
-        if (!clkdm || !clkdm->name)
-                return -EINVAL;
+        if (!cpu_is_omap34xx())
+                return;
 
-        if (!omap_chip_is(clkdm->omap_chip))
-                return -EINVAL;
+        if (!clkdm->sleepdep_srcs)
+                return;
 
-        pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
-        if (!pwrdm) {
-                pr_err("clockdomain: %s: powerdomain %s does not exist\n",
-                        clkdm->name, clkdm->pwrdm.name);
-                return -EINVAL;
-        }
-        clkdm->pwrdm.ptr = pwrdm;
+        for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
 
-        mutex_lock(&clkdm_mutex);
-        /* Verify that the clockdomain is not already registered */
-        if (_clkdm_lookup(clkdm->name)) {
-                ret = -EEXIST;
-                goto cr_unlock;
-        }
+                if (!cd->clkdm && cd->clkdm_name)
+                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
 
-        list_add(&clkdm->node, &clkdm_list);
+                if (!cd->clkdm) {
+                        WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s "
+                             "not found\n", clkdm->name, cd->clkdm_name);
+                        continue;
+                }
 
-        pwrdm_add_clkdm(pwrdm, clkdm);
+                v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
+                                            OMAP3430_CM_SLEEPDEP,
+                                            (1 << cd->clkdm->dep_bit));
 
-        pr_debug("clockdomain: registered %s\n", clkdm->name);
-        ret = 0;
+                if (v)
+                        pr_debug("clockdomain: %s: sleep dependency already "
+                                 "set to prevent from idling until %s "
+                                 "idles\n", clkdm->name, cd->clkdm->name);
 
-cr_unlock:
-        mutex_unlock(&clkdm_mutex);
+                atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0);
+        }
+};
 
-        return ret;
-}
+/* Public functions */
 
 /**
- * clkdm_unregister - unregister a clockdomain
- * @clkdm: struct clockdomain * to unregister
+ * clkdm_init - set up the clockdomain layer
+ * @clkdms: optional pointer to an array of clockdomains to register
+ * @init_autodeps: optional pointer to an array of autodeps to register
  *
- * Removes a clockdomain from the internal clockdomain list.  Returns
- * -EINVAL if clkdm argument is NULL.
+ * Set up internal state.  If a pointer to an array of clockdomains
+ * @clkdms was supplied, loop through the list of clockdomains,
+ * register all that are available on the current platform. Similarly,
+ * if a pointer to an array of clockdomain autodependencies
+ * @init_autodeps was provided, register those.  No return value.
  */
-int clkdm_unregister(struct clockdomain *clkdm)
+void clkdm_init(struct clockdomain **clkdms,
+                struct clkdm_autodep *init_autodeps)
 {
-        if (!clkdm)
-                return -EINVAL;
-
-        pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm);
+        struct clockdomain **c = NULL;
+        struct clockdomain *clkdm;
+        struct clkdm_autodep *autodep = NULL;
 
-        mutex_lock(&clkdm_mutex);
-        list_del(&clkdm->node);
-        mutex_unlock(&clkdm_mutex);
+        if (clkdms)
+                for (c = clkdms; *c; c++)
+                        _clkdm_register(*c);
 
-        pr_debug("clockdomain: unregistered %s\n", clkdm->name);
+        autodeps = init_autodeps;
+        if (autodeps)
+                for (autodep = autodeps; autodep->clkdm.ptr; autodep++)
+                        _autodep_lookup(autodep);
 
-        return 0;
+        /*
+         * Ensure that the *dep_usecount registers reflect the current
+         * state of the PRCM.
+         */
+        list_for_each_entry(clkdm, &clkdm_list, node) {
+                _init_wkdep_usecount(clkdm);
+                _init_sleepdep_usecount(clkdm);
+        }
 }
 
 /**
  * clkdm_lookup - look up a clockdomain by name, return a pointer
  * @name: name of clockdomain
  *
- * Find a registered clockdomain by its name.  Returns a pointer to the
- * struct clockdomain if found, or NULL otherwise.
+ * Find a registered clockdomain by its name @name.  Returns a pointer
+ * to the struct clockdomain if found, or NULL otherwise.
  */
 struct clockdomain *clkdm_lookup(const char *name)
 {
@@ -301,14 +398,12 @@ struct clockdomain *clkdm_lookup(const char *name)
 
         clkdm = NULL;
 
-        mutex_lock(&clkdm_mutex);
         list_for_each_entry(temp_clkdm, &clkdm_list, node) {
                 if (!strcmp(name, temp_clkdm->name)) {
                         clkdm = temp_clkdm;
                         break;
                 }
         }
-        mutex_unlock(&clkdm_mutex);
 
         return clkdm;
 }
@@ -317,8 +412,8 @@ struct clockdomain *clkdm_lookup(const char *name)
  * clkdm_for_each - call function on each registered clockdomain
  * @fn: callback function *
  *
- * Call the supplied function for each registered clockdomain.
- * The callback function can return anything but 0 to bail
+ * Call the supplied function @fn for each registered clockdomain.
+ * The callback function @fn can return anything but 0 to bail
  * out early from the iterator.  The callback function is called with
  * the clkdm_mutex held, so no clockdomain structure manipulation
  * functions should be called from the callback, although hardware
@@ -336,13 +431,11 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
         if (!fn)
                 return -EINVAL;
 
-        mutex_lock(&clkdm_mutex);
         list_for_each_entry(clkdm, &clkdm_list, node) {
                 ret = (*fn)(clkdm, user);
                 if (ret)
                         break;
         }
-        mutex_unlock(&clkdm_mutex);
 
         return ret;
 }
@@ -353,7 +446,7 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
  * @clkdm: struct clockdomain *
  *
  * Return a pointer to the struct powerdomain that the specified clockdomain
- * 'clkdm' exists in, or returns NULL if clkdm argument is NULL.
+ * @clkdm exists in, or returns NULL if @clkdm is NULL.
  */
 struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
 {
@@ -367,11 +460,309 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
 /* Hardware clockdomain control */
 
 /**
+ * clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1
+ * @clkdm1: wake this struct clockdomain * up (dependent)
+ * @clkdm2: when this struct clockdomain * wakes up (source)
+ *
+ * When the clockdomain represented by @clkdm2 wakes up, wake up
+ * @clkdm1. Implemented in hardware on the OMAP, this feature is
+ * designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
+ * Returns -EINVAL if presented with invalid clockdomain pointers,
+ * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
+ * success.
+ */
+int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+        struct clkdm_dep *cd;
+
+        if (!clkdm1 || !clkdm2)
+                return -EINVAL;
+
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+        if (IS_ERR(cd)) {
+                pr_debug("clockdomain: hardware cannot set/clear wake up of "
+                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                return PTR_ERR(cd);
+        }
+
+        if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
+                pr_debug("clockdomain: hardware will wake up %s when %s wakes "
+                         "up\n", clkdm1->name, clkdm2->name);
+
+                prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                     clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        }
+
+        return 0;
+}
+
+/**
+ * clkdm_del_wkdep - remove a wakeup dependency from clkdm2 to clkdm1
+ * @clkdm1: wake this struct clockdomain * up (dependent)
+ * @clkdm2: when this struct clockdomain * wakes up (source)
+ *
+ * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
+ * wakes up.  Returns -EINVAL if presented with invalid clockdomain
+ * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
+ * 0 upon success.
+ */
+int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+        struct clkdm_dep *cd;
+
+        if (!clkdm1 || !clkdm2)
+                return -EINVAL;
+
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+        if (IS_ERR(cd)) {
+                pr_debug("clockdomain: hardware cannot set/clear wake up of "
+                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                return PTR_ERR(cd);
+        }
+
+        if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
+                pr_debug("clockdomain: hardware will no longer wake up %s "
+                         "after %s wakes up\n", clkdm1->name, clkdm2->name);
+
+                prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                       clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        }
+
+        return 0;
+}
+
+/**
+ * clkdm_read_wkdep - read wakeup dependency state from clkdm2 to clkdm1
+ * @clkdm1: wake this struct clockdomain * up (dependent)
+ * @clkdm2: when this struct clockdomain * wakes up (source)
+ *
+ * Return 1 if a hardware wakeup dependency exists wherein @clkdm1 will be
+ * awoken when @clkdm2 wakes up; 0 if dependency is not set; -EINVAL
+ * if either clockdomain pointer is invalid; or -ENOENT if the hardware
+ * is incapable.
+ *
+ * REVISIT: Currently this function only represents software-controllable
+ * wakeup dependencies.  Wakeup dependencies fixed in hardware are not
+ * yet handled here.
+ */
+int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+        struct clkdm_dep *cd;
+
+        if (!clkdm1 || !clkdm2)
+                return -EINVAL;
+
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+        if (IS_ERR(cd)) {
+                pr_debug("clockdomain: hardware cannot set/clear wake up of "
+                         "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+                return PTR_ERR(cd);
+        }
+
+        /* XXX It's faster to return the atomic wkdep_usecount */
+        return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
+                                       (1 << clkdm2->dep_bit));
+}
+
+/**
+ * clkdm_clear_all_wkdeps - remove all wakeup dependencies from target clkdm
+ * @clkdm: struct clockdomain * to remove all wakeup dependencies from
+ *
+ * Remove all inter-clockdomain wakeup dependencies that could cause
+ * @clkdm to wake.  Intended to be used during boot to initialize the
+ * PRCM to a known state, after all clockdomains are put into swsup idle
+ * and woken up.  Returns -EINVAL if @clkdm pointer is invalid, or
+ * 0 upon success.
+ */
+int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+
+        if (!clkdm)
+                return -EINVAL;
+
+        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+
+                /* PRM accesses are slow, so minimize them */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->wkdep_usecount, 0);
+        }
+
+        prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
+
+        return 0;
+}
+
+/**
+ * clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1
+ * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ * @clkdm2: when this struct clockdomain * is active (source)
+ *
+ * Prevent @clkdm1 from automatically going inactive (and then to
+ * retention or off) if @clkdm2 is active.  Returns -EINVAL if
+ * presented with invalid clockdomain pointers or called on a machine
+ * that does not support software-configurable hardware sleep
+ * dependencies, -ENOENT if the specified dependency cannot be set in
+ * hardware, or 0 upon success.
+ */
+int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+        struct clkdm_dep *cd;
+
+        if (!cpu_is_omap34xx())
+                return -EINVAL;
+
+        if (!clkdm1 || !clkdm2)
+                return -EINVAL;
+
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+        if (IS_ERR(cd)) {
+                pr_debug("clockdomain: hardware cannot set/clear sleep "
+                         "dependency affecting %s from %s\n", clkdm1->name,
+                         clkdm2->name);
+                return PTR_ERR(cd);
+        }
+
+        if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
+                pr_debug("clockdomain: will prevent %s from sleeping if %s "
+                         "is active\n", clkdm1->name, clkdm2->name);
+
+                cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                                    clkdm1->pwrdm.ptr->prcm_offs,
+                                    OMAP3430_CM_SLEEPDEP);
+        }
+
+        return 0;
+}
+
+/**
+ * clkdm_del_sleepdep - remove a sleep dependency from clkdm2 to clkdm1
+ * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ * @clkdm2: when this struct clockdomain * is active (source)
+ *
+ * Allow @clkdm1 to automatically go inactive (and then to retention or
+ * off), independent of the activity state of @clkdm2.  Returns -EINVAL
+ * if presented with invalid clockdomain pointers or called on a machine
+ * that does not support software-configurable hardware sleep dependencies,
+ * -ENOENT if the specified dependency cannot be cleared in hardware, or
+ * 0 upon success.
+ */
+int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+        struct clkdm_dep *cd;
+
+        if (!cpu_is_omap34xx())
+                return -EINVAL;
+
+        if (!clkdm1 || !clkdm2)
+                return -EINVAL;
+
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+        if (IS_ERR(cd)) {
+                pr_debug("clockdomain: hardware cannot set/clear sleep "
+                         "dependency affecting %s from %s\n", clkdm1->name,
+                         clkdm2->name);
+                return PTR_ERR(cd);
+        }
+
+        if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
+                pr_debug("clockdomain: will no longer prevent %s from "
+                         "sleeping if %s is active\n", clkdm1->name,
+                         clkdm2->name);
+
+                cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                                      clkdm1->pwrdm.ptr->prcm_offs,
+                                      OMAP3430_CM_SLEEPDEP);
+        }
+
+        return 0;
+}
+
+/**
+ * clkdm_read_sleepdep - read sleep dependency state from clkdm2 to clkdm1
+ * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
+ * @clkdm2: when this struct clockdomain * is active (source)
+ *
+ * Return 1 if a hardware sleep dependency exists wherein @clkdm1 will
+ * not be allowed to automatically go inactive if @clkdm2 is active;
+ * 0 if @clkdm1's automatic power state inactivity transition is independent
+ * of @clkdm2's; -EINVAL if either clockdomain pointer is invalid or called
+ * on a machine that does not support software-configurable hardware sleep
+ * dependencies; or -ENOENT if the hardware is incapable.
+ *
+ * REVISIT: Currently this function only represents software-controllable
+ * sleep dependencies.  Sleep dependencies fixed in hardware are not
+ * yet handled here.
+ */
+int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+{
+        struct clkdm_dep *cd;
+
+        if (!cpu_is_omap34xx())
+                return -EINVAL;
+
+        if (!clkdm1 || !clkdm2)
+                return -EINVAL;
+
+        cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+        if (IS_ERR(cd)) {
+                pr_debug("clockdomain: hardware cannot set/clear sleep "
+                         "dependency affecting %s from %s\n", clkdm1->name,
+                         clkdm2->name);
+                return PTR_ERR(cd);
+        }
+
+        /* XXX It's faster to return the atomic sleepdep_usecount */
+        return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+                                       OMAP3430_CM_SLEEPDEP,
+                                       (1 << clkdm2->dep_bit));
+}
+
+/**
+ * clkdm_clear_all_sleepdeps - remove all sleep dependencies from target clkdm
+ * @clkdm: struct clockdomain * to remove all sleep dependencies from
+ *
+ * Remove all inter-clockdomain sleep dependencies that could prevent
+ * @clkdm from idling.  Intended to be used during boot to initialize the
+ * PRCM to a known state, after all clockdomains are put into swsup idle
+ * and woken up.  Returns -EINVAL if @clkdm pointer is invalid, or
+ * 0 upon success.
+ */
+int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+{
+        struct clkdm_dep *cd;
+        u32 mask = 0;
+
+        if (!cpu_is_omap34xx())
+                return -EINVAL;
+
+        if (!clkdm)
+                return -EINVAL;
+
+        for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
+                if (!omap_chip_is(cd->omap_chip))
+                        continue;
+
+                /* PRM accesses are slow, so minimize them */
+                mask |= 1 << cd->clkdm->dep_bit;
+                atomic_set(&cd->sleepdep_usecount, 0);
+        }
+
+        prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+                               OMAP3430_CM_SLEEPDEP);
+
+        return 0;
+}
+
+/**
  * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode
- * @clk: struct clk * of a clockdomain
+ * @clkdm: struct clkdm * of a clockdomain
  *
- * Return the clockdomain's current state transition mode from the
- * corresponding domain CM_CLKSTCTRL register.  Returns -EINVAL if clk
+ * Return the clockdomain @clkdm current state transition mode from the
+ * corresponding domain CM_CLKSTCTRL register.  Returns -EINVAL if @clkdm
  * is NULL or the current mode upon success.
  */
 static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
@@ -381,7 +772,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
         if (!clkdm)
                 return -EINVAL;
 
-        v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
+        v = __raw_readl(clkdm->clkstctrl_reg);
         v &= clkdm->clktrctrl_mask;
         v >>= __ffs(clkdm->clktrctrl_mask);
 
@@ -393,7 +784,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
  * @clkdm: struct clockdomain *
  *
  * Instruct the CM to force a sleep transition on the specified
- * clockdomain 'clkdm'.  Returns -EINVAL if clk is NULL or if
+ * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if
  * clockdomain does not support software-initiated sleep; 0 upon
  * success.
  */
@@ -413,15 +804,17 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
         if (cpu_is_omap24xx()) {
 
                 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
-                                    clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);
+                            clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
 
-        } else if (cpu_is_omap34xx()) {
+        } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
 
-                u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
+                u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
                          __ffs(clkdm->clktrctrl_mask));
 
-                cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
-                                    clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
+                u32 v = __raw_readl(clkdm->clkstctrl_reg);
+                v &= ~(clkdm->clktrctrl_mask);
+                v |= bits;
+                __raw_writel(v, clkdm->clkstctrl_reg);
 
         } else {
                 BUG();
@@ -435,7 +828,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
  * @clkdm: struct clockdomain *
  *
  * Instruct the CM to force a wakeup transition on the specified
- * clockdomain 'clkdm'.  Returns -EINVAL if clkdm is NULL or if the
+ * clockdomain @clkdm.  Returns -EINVAL if @clkdm is NULL or if the
  * clockdomain does not support software-controlled wakeup; 0 upon
  * success.
  */
@@ -455,15 +848,17 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
         if (cpu_is_omap24xx()) {
 
                 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
-                                      clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);
+                              clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
 
-        } else if (cpu_is_omap34xx()) {
+        } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
 
-                u32 v = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
+                u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
                          __ffs(clkdm->clktrctrl_mask));
 
-                cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
-                                    clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
+                u32 v = __raw_readl(clkdm->clkstctrl_reg);
+                v &= ~(clkdm->clktrctrl_mask);
+                v |= bits;
+                __raw_writel(v, clkdm->clkstctrl_reg);
 
         } else {
                 BUG();
@@ -476,7 +871,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
  * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
  * @clkdm: struct clockdomain *
  *
- * Allow the hardware to automatically switch the clockdomain into
+ * Allow the hardware to automatically switch the clockdomain @clkdm into
  * active or idle states, as needed by downstream clocks.  If the
  * clockdomain has any downstream clocks enabled in the clock
  * framework, wkdep/sleepdep autodependencies are added; this is so
@@ -509,8 +904,8 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
  * @clkdm: struct clockdomain *
  *
  * Prevent the hardware from automatically switching the clockdomain
- * into inactive or idle states.  If the clockdomain has downstream
- * clocks enabled in the clock framework, wkdep/sleepdep
+ * @clkdm into inactive or idle states.  If the clockdomain has
+ * downstream clocks enabled in the clock framework, wkdep/sleepdep
  * autodependencies are removed.  No return value.
  */
 void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
@@ -541,14 +936,14 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
  * @clkdm: struct clockdomain *
  * @clk: struct clk * of the enabled downstream clock
  *
- * Increment the usecount of this clockdomain 'clkdm' and ensure that
- * it is awake.  Intended to be called by clk_enable() code.  If the
- * clockdomain is in software-supervised idle mode, force the
- * clockdomain to wake.  If the clockdomain is in hardware-supervised
- * idle mode, add clkdm-pwrdm autodependencies, to ensure that devices
- * in the clockdomain can be read from/written to by on-chip processors.
- * Returns -EINVAL if passed null pointers; returns 0 upon success or
- * if the clockdomain is in hwsup idle mode.
+ * Increment the usecount of the clockdomain @clkdm and ensure that it
+ * is awake before @clk is enabled.  Intended to be called by
+ * clk_enable() code.  If the clockdomain is in software-supervised
+ * idle mode, force the clockdomain to wake.  If the clockdomain is in
+ * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
+ * ensure that devices in the clockdomain can be read from/written to
+ * by on-chip processors.  Returns -EINVAL if passed null pointers;
+ * returns 0 upon success or if the clockdomain is in hwsup idle mode.
  */
 int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
 {
@@ -559,7 +954,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
          * downstream clocks for debugging purposes?
          */
 
-        if (!clkdm || !clk || !clkdm->clktrctrl_mask)
+        if (!clkdm || !clk || !clkdm->clkstctrl_reg)
                 return -EINVAL;
 
         if (atomic_inc_return(&clkdm->usecount) > 1)
@@ -593,13 +988,14 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
  * @clkdm: struct clockdomain *
  * @clk: struct clk * of the disabled downstream clock
  *
- * Decrement the usecount of this clockdomain 'clkdm'. Intended to be
- * called by clk_disable() code.  If the usecount goes to 0, put the
- * clockdomain to sleep (software-supervised mode) or remove the
- * clkdm-pwrdm autodependencies (hardware-supervised mode).  Returns
- * -EINVAL if passed null pointers; -ERANGE if the clkdm usecount
- * underflows and debugging is enabled; or returns 0 upon success or
- * if the clockdomain is in hwsup idle mode.
+ * Decrement the usecount of this clockdomain @clkdm when @clk is
+ * disabled.  Intended to be called by clk_disable() code.  If the
+ * clockdomain usecount goes to 0, put the clockdomain to sleep
+ * (software-supervised mode) or remove the clkdm autodependencies
+ * (hardware-supervised mode).  Returns -EINVAL if passed null
+ * pointers; -ERANGE if the @clkdm usecount underflows and debugging
+ * is enabled; or returns 0 upon success or if the clockdomain is in
+ * hwsup idle mode.
  */
 int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
@@ -610,7 +1006,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
          * downstream clocks for debugging purposes?
          */
 
-        if (!clkdm || !clk || !clkdm->clktrctrl_mask)
+        if (!clkdm || !clk || !clkdm->clkstctrl_reg)
                 return -EINVAL;
 
 #ifdef DEBUG
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index c4ee0761d908..7db6298493fd 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -1,16 +1,420 @@
 /*
  * OMAP2/3 clockdomains
  *
- * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
  *
- * Written by Paul Walmsley
+ * Written by Paul Walmsley and Jouni Högander
+ *
+ * This file contains clockdomains and clockdomain wakeup/sleep
+ * dependencies for the OMAP2/3 chips.  Some notes:
+ *
+ * A useful validation rule for struct clockdomain: Any clockdomain
+ * referenced by a wkdep_srcs or sleepdep_srcs array must have a
+ * dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really just
+ * software-controllable dependencies.  Non-software-controllable
+ * dependencies do exist, but they are not encoded below (yet).
+ *
+ * 24xx does not support programmable sleep dependencies (SLEEPDEP)
+ *
+ * The overly-specific dep_bit names are due to a bit name collision
+ * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
+ * value are the same for all powerdomains: 2
+ *
+ * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
+ * sanity check?
+ * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
+ */
+
+/*
+ * To-Do List
+ * -> Port the Sleep/Wakeup dependencies for the domains
+ *    from the Power domain framework
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
 
 #include <plat/clockdomain.h>
+#include "cm.h"
+#include "prm.h"
+
+/*
+ * Clockdomain dependencies for wkdeps/sleepdeps
+ *
+ * XXX Hardware dependencies (e.g., dependencies that cannot be
+ * changed in software) are not included here yet, but should be.
+ */
+
+/* OMAP2/3-common wakeup dependencies */
+
+/*
+ * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
+ * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
+ * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
+ * These can share data since they will never be present simultaneously
+ * on the same device.
+ */
+static struct clkdm_dep gfx_sgx_wkdeps[] = {
+        {
+                .clkdm_name = "core_l3_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "core_l4_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
+                                            CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
+                                            CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+
+/* 24XX-specific possible dependencies */
+
+#ifdef CONFIG_ARCH_OMAP24XX
+
+/* Wakeup dependency source arrays */
+
+/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
+static struct clkdm_dep dsp_24xx_wkdeps[] = {
+        {
+                .clkdm_name = "core_l3_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "core_l4_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        { NULL },
+};
+
+/*
+ * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
+ * 2430 adds MDM
+ */
+static struct clkdm_dep mpu_24xx_wkdeps[] = {
+        {
+                .clkdm_name = "core_l3_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "core_l4_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "dsp_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "mdm_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+        },
+        { NULL },
+};
+
+/*
+ * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
+ * 2430 adds MDM
+ */
+static struct clkdm_dep core_24xx_wkdeps[] = {
+        {
+                .clkdm_name = "dsp_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "gfx_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "mdm_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+        },
+        { NULL },
+};
+
+#endif
+
+
+/* 2430-specific possible wakeup dependencies */
+
+#ifdef CONFIG_ARCH_OMAP2430
+
+/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
+static struct clkdm_dep mdm_2430_wkdeps[] = {
+        {
+                .clkdm_name = "core_l3_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "core_l4_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
+        },
+        { NULL },
+};
+
+#endif /* CONFIG_ARCH_OMAP2430 */
+
+
+/* OMAP3-specific possible dependencies */
+
+#ifdef CONFIG_ARCH_OMAP3
+
+/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep per_wkdeps[] = {
+        {
+                .clkdm_name = "core_l3_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "core_l4_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
+static struct clkdm_dep usbhost_wkdeps[] = {
+        {
+                .clkdm_name = "core_l3_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "core_l4_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
+static struct clkdm_dep mpu_3xxx_wkdeps[] = {
+        {
+                .clkdm_name = "core_l3_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "core_l4_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "dss_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "per_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
+static struct clkdm_dep iva2_wkdeps[] = {
+        {
+                .clkdm_name = "core_l3_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "core_l4_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "dss_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "per_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+
+/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
+static struct clkdm_dep cam_wkdeps[] = {
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
+static struct clkdm_dep dss_wkdeps[] = {
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "wkup_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/* 3430: PM_WKDEP_NEON: MPU */
+static struct clkdm_dep neon_wkdeps[] = {
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+
+/* Sleep dependency source arrays for OMAP3-specific clkdms */
+
+/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
+static struct clkdm_dep dss_sleepdeps[] = {
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
+static struct clkdm_dep per_sleepdeps[] = {
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
+static struct clkdm_dep usbhost_sleepdeps[] = {
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        {
+                .clkdm_name = "iva2_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/* 3430: CM_SLEEPDEP_CAM: MPU */
+static struct clkdm_dep cam_sleepdeps[] = {
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+/*
+ * 3430ES1: CM_SLEEPDEP_GFX: MPU
+ * 3430ES2: CM_SLEEPDEP_SGX: MPU
+ * These can share data since they will never be present simultaneously
+ * on the same device.
+ */
+static struct clkdm_dep gfx_sgx_sleepdeps[] = {
+        {
+                .clkdm_name = "mpu_clkdm",
+                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+        },
+        { NULL },
+};
+
+#endif /* CONFIG_ARCH_OMAP3 */
+
 
 /*
  * OMAP2/3-common clockdomains
@@ -21,10 +425,13 @@
  * sys_clkout/sys_clkout2.
  */
 
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
 /* This is an implicit clockdomain - it is never defined as such in TRM */
 static struct clockdomain wkup_clkdm = {
         .name           = "wkup_clkdm",
         .pwrdm          = { .name = "wkup_pwrdm" },
+        .dep_bit        = OMAP_EN_WKUP_SHIFT,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
 
@@ -40,6 +447,8 @@ static struct clockdomain cm_clkdm = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
 
+#endif
+
 /*
  * 2420-only clockdomains
  */
@@ -50,6 +459,8 @@ static struct clockdomain mpu_2420_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = mpu_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
@@ -58,11 +469,64 @@ static struct clockdomain iva1_2420_clkdm = {
         .name           = "iva1_clkdm",
         .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+        .wkdep_srcs     = dsp_24xx_wkdeps,
         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
-#endif  /* CONFIG_ARCH_OMAP2420 */
+static struct clockdomain dsp_2420_clkdm = {
+        .name           = "dsp_clkdm",
+        .pwrdm          = { .name = "dsp_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static struct clockdomain gfx_2420_clkdm = {
+        .name           = "gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = gfx_sgx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static struct clockdomain core_l3_2420_clkdm = {
+        .name           = "core_l3_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = core_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static struct clockdomain core_l4_2420_clkdm = {
+        .name           = "core_l4_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = core_24xx_wkdeps,
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+static struct clockdomain dss_2420_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+        .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+#endif   /* CONFIG_ARCH_OMAP2420 */
 
 
 /*
@@ -75,80 +539,105 @@ static struct clockdomain mpu_2430_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP2430_CM_REGADDR(MPU_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = mpu_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
+/* Another case of bit name collisions between several registers: EN_MDM */
 static struct clockdomain mdm_clkdm = {
         .name           = "mdm_clkdm",
         .pwrdm          = { .name = "mdm_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
+        .wkdep_srcs     = mdm_2430_wkdeps,
         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-#endif    /* CONFIG_ARCH_OMAP2430 */
-
-
-/*
- * 24XX-only clockdomains
- */
-
-#if defined(CONFIG_ARCH_OMAP24XX)
-
-static struct clockdomain dsp_clkdm = {
+static struct clockdomain dsp_2430_clkdm = {
         .name           = "dsp_clkdm",
         .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
+        .wkdep_srcs     = dsp_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-static struct clockdomain gfx_24xx_clkdm = {
+static struct clockdomain gfx_2430_clkdm = {
         .name           = "gfx_clkdm",
         .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = gfx_sgx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-static struct clockdomain core_l3_24xx_clkdm = {
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_2430_clkdm = {
         .name           = "core_l3_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
+        .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-static struct clockdomain core_l4_24xx_clkdm = {
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_2430_clkdm = {
         .name           = "core_l4_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
+        .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-static struct clockdomain dss_24xx_clkdm = {
+static struct clockdomain dss_2430_clkdm = {
         .name           = "dss_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
-#endif   /* CONFIG_ARCH_OMAP24XX */
+#endif    /* CONFIG_ARCH_OMAP2430 */
 
 
 /*
- * 34xx clockdomains
+ * OMAP3 clockdomains
  */
 
-#if defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP3)
 
-static struct clockdomain mpu_34xx_clkdm = {
+static struct clockdomain mpu_3xxx_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
+        .wkdep_srcs     = mpu_3xxx_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -157,6 +646,9 @@ static struct clockdomain neon_clkdm = {
         .name           = "neon_clkdm",
         .pwrdm          = { .name = "neon_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = neon_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -165,6 +657,10 @@ static struct clockdomain iva2_clkdm = {
         .name           = "iva2_clkdm",
         .pwrdm          = { .name = "iva2_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
+        .wkdep_srcs     = iva2_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -173,6 +669,9 @@ static struct clockdomain gfx_3430es1_clkdm = {
         .name           = "gfx_clkdm",
         .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = gfx_sgx_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 };
@@ -181,6 +680,10 @@ static struct clockdomain sgx_clkdm = {
         .name           = "sgx_clkdm",
         .pwrdm          = { .name = "sgx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = gfx_sgx_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
@@ -196,30 +699,51 @@ static struct clockdomain d2d_clkdm = {
         .name           = "d2d_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
-static struct clockdomain core_l3_34xx_clkdm = {
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l3_3xxx_clkdm = {
         .name           = "core_l3_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
-static struct clockdomain core_l4_34xx_clkdm = {
+/*
+ * XXX add usecounting for clkdm dependencies, otherwise the presence
+ * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
+ * could cause trouble
+ */
+static struct clockdomain core_l4_3xxx_clkdm = {
         .name           = "core_l4_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP3430_EN_CORE_SHIFT,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
 
-static struct clockdomain dss_34xx_clkdm = {
+/* Another case of bit name collisions between several registers: EN_DSS */
+static struct clockdomain dss_3xxx_clkdm = {
         .name           = "dss_clkdm",
         .pwrdm          = { .name = "dss_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
+        .wkdep_srcs     = dss_wkdeps,
+        .sleepdep_srcs  = dss_sleepdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -228,6 +752,10 @@ static struct clockdomain cam_clkdm = {
         .name           = "cam_clkdm",
         .pwrdm          = { .name = "cam_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = cam_wkdeps,
+        .sleepdep_srcs  = cam_sleepdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -236,6 +764,10 @@ static struct clockdomain usbhost_clkdm = {
         .name           = "usbhost_clkdm",
         .pwrdm          = { .name = "usbhost_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .wkdep_srcs     = usbhost_wkdeps,
+        .sleepdep_srcs  = usbhost_sleepdeps,
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
@@ -244,6 +776,11 @@ static struct clockdomain per_clkdm = {
         .name           = "per_clkdm",
         .pwrdm          = { .name = "per_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
+        .dep_bit        = OMAP3430_EN_PER_SHIFT,
+        .wkdep_srcs     = per_wkdeps,
+        .sleepdep_srcs  = per_sleepdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -256,6 +793,8 @@ static struct clockdomain emu_clkdm = {
         .name           = "emu_clkdm",
         .pwrdm          = { .name = "emu_pwrdm" },
         .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
+                                                 OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -290,64 +829,70 @@ static struct clockdomain dpll5_clkdm = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
-#endif   /* CONFIG_ARCH_OMAP34XX */
+#endif   /* CONFIG_ARCH_OMAP3 */
+
+#include "clockdomains44xx.h"
 
 /*
- * Clockdomain-powerdomain hwsup dependencies (34XX only)
+ * Clockdomain hwsup dependencies (OMAP3 only)
  */
 
-static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
+static struct clkdm_autodep clkdm_autodeps[] = {
         {
-                .pwrdm     = { .name = "mpu_pwrdm" },
+                .clkdm     = { .name = "mpu_clkdm" },
                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
         },
         {
-                .pwrdm     = { .name = "iva2_pwrdm" },
+                .clkdm     = { .name = "iva2_clkdm" },
                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
         },
         {
-                .pwrdm     = { .name = NULL },
+                .clkdm     = { .name = NULL },
         }
 };
 
 /*
- *
+ * List of clockdomain pointers per platform
  */
 
 static struct clockdomain *clockdomains_omap[] = {
 
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         &wkup_clkdm,
         &cm_clkdm,
         &prm_clkdm,
+#endif
 
 #ifdef CONFIG_ARCH_OMAP2420
         &mpu_2420_clkdm,
         &iva1_2420_clkdm,
+        &dsp_2420_clkdm,
+        &gfx_2420_clkdm,
+        &core_l3_2420_clkdm,
+        &core_l4_2420_clkdm,
+        &dss_2420_clkdm,
 #endif
 
 #ifdef CONFIG_ARCH_OMAP2430
         &mpu_2430_clkdm,
         &mdm_clkdm,
+        &dsp_2430_clkdm,
+        &gfx_2430_clkdm,
+        &core_l3_2430_clkdm,
+        &core_l4_2430_clkdm,
+        &dss_2430_clkdm,
 #endif
 
-#ifdef CONFIG_ARCH_OMAP24XX
-        &dsp_clkdm,
-        &gfx_24xx_clkdm,
-        &core_l3_24xx_clkdm,
-        &core_l4_24xx_clkdm,
-        &dss_24xx_clkdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP34XX
-        &mpu_34xx_clkdm,
+#ifdef CONFIG_ARCH_OMAP3
+        &mpu_3xxx_clkdm,
         &neon_clkdm,
         &iva2_clkdm,
         &gfx_3430es1_clkdm,
         &sgx_clkdm,
         &d2d_clkdm,
-        &core_l3_34xx_clkdm,
-        &core_l4_34xx_clkdm,
-        &dss_34xx_clkdm,
+        &core_l3_3xxx_clkdm,
+        &core_l4_3xxx_clkdm,
+        &dss_3xxx_clkdm,
         &cam_clkdm,
         &usbhost_clkdm,
         &per_clkdm,
@@ -359,6 +904,33 @@ static struct clockdomain *clockdomains_omap[] = {
         &dpll5_clkdm,
 #endif
 
+#ifdef CONFIG_ARCH_OMAP4
+        &l4_cefuse_44xx_clkdm,
+        &l4_cfg_44xx_clkdm,
+        &tesla_44xx_clkdm,
+        &l3_gfx_44xx_clkdm,
+        &ivahd_44xx_clkdm,
+        &l4_secure_44xx_clkdm,
+        &l4_per_44xx_clkdm,
+        &abe_44xx_clkdm,
+        &l3_instr_44xx_clkdm,
+        &l3_init_44xx_clkdm,
+        &mpuss_44xx_clkdm,
+        &mpu0_44xx_clkdm,
+        &mpu1_44xx_clkdm,
+        &l3_emif_44xx_clkdm,
+        &l4_ao_44xx_clkdm,
+        &ducati_44xx_clkdm,
+        &l3_2_44xx_clkdm,
+        &l3_1_44xx_clkdm,
+        &l3_d2d_44xx_clkdm,
+        &iss_44xx_clkdm,
+        &l3_dss_44xx_clkdm,
+        &l4_wkup_44xx_clkdm,
+        &emu_sys_44xx_clkdm,
+        &l3_dma_44xx_clkdm,
+#endif
+
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx.h
new file mode 100644
index 000000000000..438aaee2e392
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains44xx.h
@@ -0,0 +1,250 @@
+/*
+ * OMAP4 Clock domains framework
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * To-Do List
+ * -> Populate the Sleep/Wakeup dependencies for the domains
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
+
+#include <plat/clockdomain.h>
+
+#if defined(CONFIG_ARCH_OMAP4)
+
+static struct clockdomain l4_cefuse_44xx_clkdm = {
+        .name             = "l4_cefuse_clkdm",
+        .pwrdm            = { .name = "cefuse_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_CEFUSE_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_cfg_44xx_clkdm = {
+        .name             = "l4_cfg_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_L4CFG_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain tesla_44xx_clkdm = {
+        .name             = "tesla_clkdm",
+        .pwrdm            = { .name = "tesla_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_TESLA_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_gfx_44xx_clkdm = {
+        .name             = "l3_gfx_clkdm",
+        .pwrdm            = { .name = "gfx_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_GFX_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain ivahd_44xx_clkdm = {
+        .name             = "ivahd_clkdm",
+        .pwrdm            = { .name = "ivahd_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_IVAHD_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_secure_44xx_clkdm = {
+        .name             = "l4_secure_clkdm",
+        .pwrdm            = { .name = "l4per_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_L4SEC_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_per_44xx_clkdm = {
+        .name             = "l4_per_clkdm",
+        .pwrdm            = { .name = "l4per_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_L4PER_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain abe_44xx_clkdm = {
+        .name             = "abe_clkdm",
+        .pwrdm            = { .name = "abe_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM1_ABE_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_instr_44xx_clkdm = {
+        .name             = "l3_instr_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_L3INSTR_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_init_44xx_clkdm = {
+        .name             = "l3_init_clkdm",
+        .pwrdm            = { .name = "l3init_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_L3INIT_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpuss_44xx_clkdm = {
+        .name             = "mpuss_clkdm",
+        .pwrdm            = { .name = "mpu_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_MPU_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpu0_44xx_clkdm = {
+        .name             = "mpu0_clkdm",
+        .pwrdm            = { .name = "cpu0_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_PDA_CPU0_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain mpu1_44xx_clkdm = {
+        .name             = "mpu1_clkdm",
+        .pwrdm            = { .name = "cpu1_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_PDA_CPU1_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_emif_44xx_clkdm = {
+        .name             = "l3_emif_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_MEMIF_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_ao_44xx_clkdm = {
+        .name             = "l4_ao_clkdm",
+        .pwrdm            = { .name = "always_on_core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_ALWON_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain ducati_44xx_clkdm = {
+        .name             = "ducati_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_DUCATI_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_2_44xx_clkdm = {
+        .name             = "l3_2_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_L3_2_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_1_44xx_clkdm = {
+        .name             = "l3_1_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_L3_1_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_d2d_44xx_clkdm = {
+        .name             = "l3_d2d_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_D2D_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain iss_44xx_clkdm = {
+        .name             = "iss_clkdm",
+        .pwrdm            = { .name = "cam_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_CAM_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_dss_44xx_clkdm = {
+        .name             = "l3_dss_clkdm",
+        .pwrdm            = { .name = "dss_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_DSS_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l4_wkup_44xx_clkdm = {
+        .name             = "l4_wkup_clkdm",
+        .pwrdm            = { .name = "wkup_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_WKUP_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain emu_sys_44xx_clkdm = {
+        .name             = "emu_sys_clkdm",
+        .pwrdm            = { .name = "emu_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_EMU_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct clockdomain l3_dma_44xx_clkdm = {
+        .name             = "l3_dma_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .clkstctrl_reg    = OMAP4430_CM_SDMA_CLKSTCTRL,
+        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 0e67f75aa35c..ac8458e43252 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -26,7 +26,7 @@
 
 
 /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
-#define OMAP4430_ABE_DYNDEP_SHIFT                               (1 << 3)
+#define OMAP4430_ABE_DYNDEP_SHIFT                               3
 #define OMAP4430_ABE_DYNDEP_MASK                                BITFIELD(3, 3)
 
 /*
@@ -34,15 +34,15 @@
  * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
  * CM_TESLA_STATICDEP
  */
-#define OMAP4430_ABE_STATDEP_SHIFT                              (1 << 3)
+#define OMAP4430_ABE_STATDEP_SHIFT                              3
 #define OMAP4430_ABE_STATDEP_MASK                               BITFIELD(3, 3)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         (1 << 16)
+#define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          BITFIELD(16, 16)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
-#define OMAP4430_ALWONCORE_STATDEP_SHIFT                        (1 << 16)
+#define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
 #define OMAP4430_ALWONCORE_STATDEP_MASK                         BITFIELD(16, 16)
 
 /*
@@ -50,371 +50,371 @@
  * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
  * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU
  */
-#define OMAP4430_AUTO_DPLL_MODE_SHIFT                           (1 << 0)
+#define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
 #define OMAP4430_AUTO_DPLL_MODE_MASK                            BITFIELD(0, 2)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_CEFUSE_DYNDEP_SHIFT                            (1 << 17)
+#define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
 #define OMAP4430_CEFUSE_DYNDEP_MASK                             BITFIELD(17, 17)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
-#define OMAP4430_CEFUSE_STATDEP_SHIFT                           (1 << 17)
+#define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
 #define OMAP4430_CEFUSE_STATDEP_MASK                            BITFIELD(17, 17)
 
 /* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                (1 << 13)
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 BITFIELD(13, 13)
 
 /* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            (1 << 12)
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             BITFIELD(12, 12)
 
 /* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   (1 << 9)
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    BITFIELD(9, 9)
 
 /* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   (1 << 11)
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    BITFIELD(11, 11)
 
 /* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    BITFIELD(8, 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                (1 << 11)
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 BITFIELD(11, 11)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               (1 << 12)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                BITFIELD(12, 12)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               (1 << 13)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                BITFIELD(13, 13)
 
 /* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            (1 << 9)
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             BITFIELD(9, 9)
 
 /* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            (1 << 9)
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             BITFIELD(9, 9)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           (1 << 9)
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            BITFIELD(9, 9)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      (1 << 9)
+#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       BITFIELD(9, 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  (1 << 9)
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   BITFIELD(9, 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  (1 << 10)
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   BITFIELD(10, 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   (1 << 11)
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    BITFIELD(11, 11)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   (1 << 12)
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    BITFIELD(12, 12)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   (1 << 13)
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    BITFIELD(13, 13)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   (1 << 14)
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    BITFIELD(14, 14)
 
 /* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            (1 << 10)
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             BITFIELD(10, 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     (1 << 9)
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      BITFIELD(9, 9)
 
 /* Used by CM_DUCATI_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  (1 << 8)
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   BITFIELD(8, 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT               (1 << 10)
+#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT               10
 #define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK                BITFIELD(10, 10)
 
 /* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  (1 << 8)
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   BITFIELD(8, 8)
 
 /* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   (1 << 10)
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    BITFIELD(10, 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               (1 << 15)
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                BITFIELD(15, 15)
 
 /* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               (1 << 10)
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                BITFIELD(10, 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         (1 << 11)
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          BITFIELD(11, 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           (1 << 20)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            BITFIELD(20, 20)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                (1 << 26)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 BITFIELD(26, 26)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           (1 << 21)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            BITFIELD(21, 21)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                (1 << 27)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 BITFIELD(27, 27)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT               (1 << 31)
+#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT               31
 #define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK                BITFIELD(31, 31)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              (1 << 13)
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               BITFIELD(13, 13)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               (1 << 12)
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                BITFIELD(12, 12)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            (1 << 28)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             BITFIELD(28, 28)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            (1 << 29)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             BITFIELD(29, 29)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                BITFIELD(11, 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               (1 << 16)
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                BITFIELD(16, 16)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            (1 << 17)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             BITFIELD(17, 17)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            (1 << 18)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             BITFIELD(18, 18)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            (1 << 19)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             BITFIELD(19, 19)
 
 /* Used by CM_CAM_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     (1 << 8)
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      BITFIELD(8, 8)
 
 /* Used by CM_IVAHD_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                BITFIELD(8, 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT        (1 << 14)
+#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT        14
 #define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK         BITFIELD(14, 14)
 
 /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    BITFIELD(8, 8)
 
 /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    BITFIELD(8, 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  BITFIELD(8, 8)
 
 /* Used by CM_SDMA_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  BITFIELD(8, 8)
 
 /* Used by CM_DSS_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  BITFIELD(8, 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 BITFIELD(8, 8)
 
 /* Used by CM_GFX_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  BITFIELD(8, 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 BITFIELD(8, 8)
 
 /* Used by CM_L3INSTR_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                BITFIELD(8, 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               BITFIELD(8, 8)
 
 /* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    BITFIELD(8, 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               BITFIELD(8, 8)
 
 /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  BITFIELD(8, 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  BITFIELD(9, 9)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 BITFIELD(9, 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  BITFIELD(8, 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               BITFIELD(9, 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                (1 << 12)
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 BITFIELD(12, 12)
 
 /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  BITFIELD(8, 8)
 
 /* Used by CM1_ABE_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 BITFIELD(9, 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               (1 << 16)
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                BITFIELD(16, 16)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                (1 << 17)
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 BITFIELD(17, 17)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                (1 << 18)
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 BITFIELD(18, 18)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                (1 << 19)
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 BITFIELD(19, 19)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            (1 << 25)
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             BITFIELD(25, 25)
 
 /* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT             (1 << 10)
+#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT             10
 #define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK              BITFIELD(10, 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             (1 << 20)
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              BITFIELD(20, 20)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             (1 << 21)
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              BITFIELD(21, 21)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             (1 << 22)
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              BITFIELD(22, 22)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                (1 << 24)
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 BITFIELD(24, 24)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 (1 << 10)
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  BITFIELD(10, 10)
 
 /* Used by CM_GFX_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    (1 << 9)
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     BITFIELD(9, 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                BITFIELD(11, 11)
 
 /* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                (1 << 10)
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 BITFIELD(10, 10)
 
 /* Used by CM_ALWON_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 BITFIELD(9, 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      (1 << 8)
+#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       BITFIELD(8, 8)
 
 /* Used by CM_TESLA_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                BITFIELD(8, 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                (1 << 22)
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 BITFIELD(22, 22)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                (1 << 23)
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 BITFIELD(23, 23)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                (1 << 24)
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 BITFIELD(24, 24)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              (1 << 15)
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               BITFIELD(15, 15)
 
 /* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   (1 << 10)
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    BITFIELD(10, 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                (1 << 30)
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 BITFIELD(30, 30)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              (1 << 25)
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               BITFIELD(25, 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                BITFIELD(11, 11)
 
 /*
@@ -426,7 +426,7 @@
  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
  * CM1_ABE_TIMER8_CLKCTRL
  */
-#define OMAP4430_CLKSEL_SHIFT                                   (1 << 24)
+#define OMAP4430_CLKSEL_SHIFT                                   24
 #define OMAP4430_CLKSEL_MASK                                    BITFIELD(24, 24)
 
 /*
@@ -434,43 +434,43 @@
  * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT,
  * CM_CLKSEL_USB_60MHZ
  */
-#define OMAP4430_CLKSEL_0_0_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_0_0_SHIFT                               0
 #define OMAP4430_CLKSEL_0_0_MASK                                BITFIELD(0, 0)
 
 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
-#define OMAP4430_CLKSEL_0_1_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_0_1_SHIFT                               0
 #define OMAP4430_CLKSEL_0_1_MASK                                BITFIELD(0, 1)
 
 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
-#define OMAP4430_CLKSEL_24_25_SHIFT                             (1 << 24)
+#define OMAP4430_CLKSEL_24_25_SHIFT                             24
 #define OMAP4430_CLKSEL_24_25_MASK                              BITFIELD(24, 25)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
-#define OMAP4430_CLKSEL_60M_SHIFT                               (1 << 24)
+#define OMAP4430_CLKSEL_60M_SHIFT                               24
 #define OMAP4430_CLKSEL_60M_MASK                                BITFIELD(24, 24)
 
 /* Used by CM1_ABE_AESS_CLKCTRL */
-#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         (1 << 24)
+#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          BITFIELD(24, 24)
 
 /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
-#define OMAP4430_CLKSEL_CORE_SHIFT                              (1 << 0)
+#define OMAP4430_CLKSEL_CORE_SHIFT                              0
 #define OMAP4430_CLKSEL_CORE_MASK                               BITFIELD(0, 0)
 
 /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          (1 << 1)
+#define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           BITFIELD(1, 1)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
-#define OMAP4430_CLKSEL_DIV_SHIFT                               (1 << 24)
+#define OMAP4430_CLKSEL_DIV_SHIFT                               24
 #define OMAP4430_CLKSEL_DIV_MASK                                BITFIELD(24, 24)
 
 /* Used by CM_CAM_FDIF_CLKCTRL */
-#define OMAP4430_CLKSEL_FCLK_SHIFT                              (1 << 24)
+#define OMAP4430_CLKSEL_FCLK_SHIFT                              24
 #define OMAP4430_CLKSEL_FCLK_MASK                               BITFIELD(24, 25)
 
 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   (1 << 25)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    BITFIELD(25, 25)
 
 /*
@@ -478,58 +478,58 @@
  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
  * CM1_ABE_MCBSP3_CLKCTRL
  */
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      (1 << 26)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       BITFIELD(26, 27)
 
 /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
-#define OMAP4430_CLKSEL_L3_SHIFT                                (1 << 4)
+#define OMAP4430_CLKSEL_L3_SHIFT                                4
 #define OMAP4430_CLKSEL_L3_MASK                                 BITFIELD(4, 4)
 
 /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         (1 << 2)
+#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          BITFIELD(2, 2)
 
 /* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
-#define OMAP4430_CLKSEL_L4_SHIFT                                (1 << 8)
+#define OMAP4430_CLKSEL_L4_SHIFT                                8
 #define OMAP4430_CLKSEL_L4_MASK                                 BITFIELD(8, 8)
 
 /* Used by CM_CLKSEL_ABE */
-#define OMAP4430_CLKSEL_OPP_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_OPP_SHIFT                               0
 #define OMAP4430_CLKSEL_OPP_MASK                                BITFIELD(0, 1)
 
 /* Used by CM_GFX_GFX_CLKCTRL */
-#define OMAP4430_CLKSEL_PER_192M_SHIFT                          (1 << 25)
+#define OMAP4430_CLKSEL_PER_192M_SHIFT                          25
 #define OMAP4430_CLKSEL_PER_192M_MASK                           BITFIELD(25, 26)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       (1 << 27)
+#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        BITFIELD(27, 29)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     (1 << 24)
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      BITFIELD(24, 26)
 
 /* Used by CM_GFX_GFX_CLKCTRL */
-#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          (1 << 24)
+#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           BITFIELD(24, 24)
 
 /*
  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
  */
-#define OMAP4430_CLKSEL_SOURCE_SHIFT                            (1 << 24)
+#define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
 #define OMAP4430_CLKSEL_SOURCE_MASK                             BITFIELD(24, 25)
 
 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
-#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      (1 << 24)
+#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       BITFIELD(24, 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           (1 << 24)
+#define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            BITFIELD(24, 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           (1 << 25)
+#define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            BITFIELD(25, 25)
 
 /*
@@ -544,23 +544,23 @@
  * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
  * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE
  */
-#define OMAP4430_CLKTRCTRL_SHIFT                                (1 << 0)
+#define OMAP4430_CLKTRCTRL_SHIFT                                0
 #define OMAP4430_CLKTRCTRL_MASK                                 BITFIELD(0, 1)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        (1 << 0)
+#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         BITFIELD(0, 6)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       (1 << 8)
+#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        BITFIELD(8, 18)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_D2D_DYNDEP_SHIFT                               (1 << 18)
+#define OMAP4430_D2D_DYNDEP_SHIFT                               18
 #define OMAP4430_D2D_DYNDEP_MASK                                BITFIELD(18, 18)
 
 /* Used by CM_MPU_STATICDEP */
-#define OMAP4430_D2D_STATDEP_SHIFT                              (1 << 18)
+#define OMAP4430_D2D_STATDEP_SHIFT                              18
 #define OMAP4430_D2D_STATDEP_MASK                               BITFIELD(18, 18)
 
 /*
@@ -570,19 +570,19 @@
  * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
  * CM_SSC_DELTAMSTEP_DPLL_MPU
  */
-#define OMAP4430_DELTAMSTEP_SHIFT                               (1 << 0)
+#define OMAP4430_DELTAMSTEP_SHIFT                               0
 #define OMAP4430_DELTAMSTEP_MASK                                BITFIELD(0, 19)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DLL_OVERRIDE_SHIFT                             (1 << 2)
+#define OMAP4430_DLL_OVERRIDE_SHIFT                             2
 #define OMAP4430_DLL_OVERRIDE_MASK                              BITFIELD(2, 2)
 
 /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
-#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         (1 << 0)
+#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         0
 #define OMAP4430_DLL_OVERRIDE_0_0_MASK                          BITFIELD(0, 0)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DLL_RESET_SHIFT                                (1 << 3)
+#define OMAP4430_DLL_RESET_SHIFT                                3
 #define OMAP4430_DLL_RESET_MASK                                 BITFIELD(3, 3)
 
 /*
@@ -590,40 +590,40 @@
  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
  * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
  */
-#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          (1 << 23)
+#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           BITFIELD(23, 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
-#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 (1 << 8)
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  BITFIELD(8, 8)
 
 /* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */
-#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    (1 << 20)
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     BITFIELD(20, 20)
 
 /*
  * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
  * CM_DIV_M3_DPLL_CORE
  */
-#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       (1 << 0)
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        BITFIELD(0, 4)
 
 /*
  * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
  * CM_DIV_M3_DPLL_CORE
  */
-#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  (1 << 5)
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   BITFIELD(5, 5)
 
 /*
  * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
  * CM_DIV_M3_DPLL_CORE
  */
-#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 (1 << 8)
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  BITFIELD(8, 8)
 
 /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
-#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  (1 << 10)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   BITFIELD(10, 10)
 
 /*
@@ -631,11 +631,11 @@
  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
  * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
  */
-#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          (1 << 0)
+#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           BITFIELD(0, 4)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
-#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      (1 << 0)
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       BITFIELD(0, 6)
 
 /*
@@ -643,11 +643,11 @@
  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
  * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
  */
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     (1 << 5)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      BITFIELD(5, 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              (1 << 7)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               BITFIELD(7, 7)
 
 /*
@@ -655,23 +655,23 @@
  * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
  * CM_DIV_M2_DPLL_MPU
  */
-#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    (1 << 8)
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     BITFIELD(8, 8)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        (1 << 8)
+#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         BITFIELD(8, 10)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         (1 << 11)
+#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          BITFIELD(11, 15)
 
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         (1 << 3)
+#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          BITFIELD(3, 7)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT                 (1 << 1)
+#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT                 1
 #define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK                  BITFIELD(1, 1)
 
 /*
@@ -679,11 +679,11 @@
  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
  * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
  */
-#define OMAP4430_DPLL_DIV_SHIFT                                 (1 << 0)
+#define OMAP4430_DPLL_DIV_SHIFT                                 0
 #define OMAP4430_DPLL_DIV_MASK                                  BITFIELD(0, 6)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_DIV_0_7_SHIFT                             (1 << 0)
+#define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
 #define OMAP4430_DPLL_DIV_0_7_MASK                              BITFIELD(0, 7)
 
 /*
@@ -691,11 +691,11 @@
  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
  * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
  */
-#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       (1 << 8)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        BITFIELD(8, 8)
 
 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
-#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   (1 << 3)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    BITFIELD(3, 3)
 
 /*
@@ -703,7 +703,7 @@
  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
  * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
  */
-#define OMAP4430_DPLL_EN_SHIFT                                  (1 << 0)
+#define OMAP4430_DPLL_EN_SHIFT                                  0
 #define OMAP4430_DPLL_EN_MASK                                   BITFIELD(0, 2)
 
 /*
@@ -711,7 +711,7 @@
  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
  * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
  */
-#define OMAP4430_DPLL_LPMODE_EN_SHIFT                           (1 << 10)
+#define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
 #define OMAP4430_DPLL_LPMODE_EN_MASK                            BITFIELD(10, 10)
 
 /*
@@ -719,11 +719,11 @@
  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
  * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
  */
-#define OMAP4430_DPLL_MULT_SHIFT                                (1 << 8)
+#define OMAP4430_DPLL_MULT_SHIFT                                8
 #define OMAP4430_DPLL_MULT_MASK                                 BITFIELD(8, 18)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_MULT_USB_SHIFT                            (1 << 8)
+#define OMAP4430_DPLL_MULT_USB_SHIFT                            8
 #define OMAP4430_DPLL_MULT_USB_MASK                             BITFIELD(8, 19)
 
 /*
@@ -731,11 +731,11 @@
  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
  * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
  */
-#define OMAP4430_DPLL_REGM4XEN_SHIFT                            (1 << 11)
+#define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
 #define OMAP4430_DPLL_REGM4XEN_MASK                             BITFIELD(11, 11)
 
 /* Used by CM_CLKSEL_DPLL_USB */
-#define OMAP4430_DPLL_SD_DIV_SHIFT                              (1 << 24)
+#define OMAP4430_DPLL_SD_DIV_SHIFT                              24
 #define OMAP4430_DPLL_SD_DIV_MASK                               BITFIELD(24, 31)
 
 /*
@@ -743,7 +743,7 @@
  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
  * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
  */
-#define OMAP4430_DPLL_SSC_ACK_SHIFT                             (1 << 13)
+#define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
 #define OMAP4430_DPLL_SSC_ACK_MASK                              BITFIELD(13, 13)
 
 /*
@@ -751,7 +751,7 @@
  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
  * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
  */
-#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      (1 << 14)
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       BITFIELD(14, 14)
 
 /*
@@ -759,154 +759,154 @@
  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
  * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
  */
-#define OMAP4430_DPLL_SSC_EN_SHIFT                              (1 << 12)
+#define OMAP4430_DPLL_SSC_EN_SHIFT                              12
 #define OMAP4430_DPLL_SSC_EN_MASK                               BITFIELD(12, 12)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_DSS_DYNDEP_SHIFT                               (1 << 8)
+#define OMAP4430_DSS_DYNDEP_SHIFT                               8
 #define OMAP4430_DSS_DYNDEP_MASK                                BITFIELD(8, 8)
 
 /*
  * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
  * CM_MPU_STATICDEP
  */
-#define OMAP4430_DSS_STATDEP_SHIFT                              (1 << 8)
+#define OMAP4430_DSS_STATDEP_SHIFT                              8
 #define OMAP4430_DSS_STATDEP_MASK                               BITFIELD(8, 8)
 
 /* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_DUCATI_DYNDEP_SHIFT                            (1 << 0)
+#define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
 #define OMAP4430_DUCATI_DYNDEP_MASK                             BITFIELD(0, 0)
 
 /* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */
-#define OMAP4430_DUCATI_STATDEP_SHIFT                           (1 << 0)
+#define OMAP4430_DUCATI_STATDEP_SHIFT                           0
 #define OMAP4430_DUCATI_STATDEP_MASK                            BITFIELD(0, 0)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_FREQ_UPDATE_SHIFT                              (1 << 0)
+#define OMAP4430_FREQ_UPDATE_SHIFT                              0
 #define OMAP4430_FREQ_UPDATE_MASK                               BITFIELD(0, 0)
 
 /* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_GFX_DYNDEP_SHIFT                               (1 << 10)
+#define OMAP4430_GFX_DYNDEP_SHIFT                               10
 #define OMAP4430_GFX_DYNDEP_MASK                                BITFIELD(10, 10)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP4430_GFX_STATDEP_SHIFT                              (1 << 10)
+#define OMAP4430_GFX_STATDEP_SHIFT                              10
 #define OMAP4430_GFX_STATDEP_MASK                               BITFIELD(10, 10)
 
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
-#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         (1 << 0)
+#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          BITFIELD(0, 0)
 
 /*
  * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
  * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
  */
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     BITFIELD(0, 4)
 
 /*
  * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
  * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
  */
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                BITFIELD(5, 5)
 
 /*
  * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
  * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
  */
-#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               BITFIELD(8, 8)
 
 /*
  * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
  * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
  */
-#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    BITFIELD(12, 12)
 
 /*
  * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
  * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
  */
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     BITFIELD(0, 4)
 
 /*
  * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
  * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
  */
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                BITFIELD(5, 5)
 
 /*
  * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
  * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
  */
-#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               BITFIELD(8, 8)
 
 /*
  * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
  * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
  */
-#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    BITFIELD(12, 12)
 
 /*
  * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
  * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
  */
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     BITFIELD(0, 4)
 
 /*
  * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
  * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
  */
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                BITFIELD(5, 5)
 
 /*
  * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
  * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
  */
-#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               BITFIELD(8, 8)
 
 /*
  * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
  * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
  */
-#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    BITFIELD(12, 12)
 
 /*
  * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
  * CM_DIV_M7_DPLL_CORE
  */
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     BITFIELD(0, 4)
 
 /*
  * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
  * CM_DIV_M7_DPLL_CORE
  */
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                BITFIELD(5, 5)
 
 /*
  * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
  * CM_DIV_M7_DPLL_CORE
  */
-#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               BITFIELD(8, 8)
 
 /*
  * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
  * CM_DIV_M7_DPLL_CORE
  */
-#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    BITFIELD(12, 12)
 
 /*
@@ -962,22 +962,22 @@
  * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
  * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
  */
-#define OMAP4430_IDLEST_SHIFT                                   (1 << 16)
+#define OMAP4430_IDLEST_SHIFT                                   16
 #define OMAP4430_IDLEST_MASK                                    BITFIELD(16, 17)
 
 /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_ISS_DYNDEP_SHIFT                               (1 << 9)
+#define OMAP4430_ISS_DYNDEP_SHIFT                               9
 #define OMAP4430_ISS_DYNDEP_MASK                                BITFIELD(9, 9)
 
 /*
  * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
  * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
  */
-#define OMAP4430_ISS_STATDEP_SHIFT                              (1 << 9)
+#define OMAP4430_ISS_STATDEP_SHIFT                              9
 #define OMAP4430_ISS_STATDEP_MASK                               BITFIELD(9, 9)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
-#define OMAP4430_IVAHD_DYNDEP_SHIFT                             (1 << 2)
+#define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
 #define OMAP4430_IVAHD_DYNDEP_MASK                              BITFIELD(2, 2)
 
 /*
@@ -986,25 +986,25 @@
  * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP,
  * CM_TESLA_STATICDEP
  */
-#define OMAP4430_IVAHD_STATDEP_SHIFT                            (1 << 2)
+#define OMAP4430_IVAHD_STATDEP_SHIFT                            2
 #define OMAP4430_IVAHD_STATDEP_MASK                             BITFIELD(2, 2)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_L3INIT_DYNDEP_SHIFT                            (1 << 7)
+#define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
 #define OMAP4430_L3INIT_DYNDEP_MASK                             BITFIELD(7, 7)
 
 /*
  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
  * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
  */
-#define OMAP4430_L3INIT_STATDEP_SHIFT                           (1 << 7)
+#define OMAP4430_L3INIT_STATDEP_SHIFT                           7
 #define OMAP4430_L3INIT_STATDEP_MASK                            BITFIELD(7, 7)
 
 /*
  * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
  * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
-#define OMAP4430_L3_1_DYNDEP_SHIFT                              (1 << 5)
+#define OMAP4430_L3_1_DYNDEP_SHIFT                              5
 #define OMAP4430_L3_1_DYNDEP_MASK                               BITFIELD(5, 5)
 
 /*
@@ -1013,7 +1013,7 @@
  * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
  * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
  */
-#define OMAP4430_L3_1_STATDEP_SHIFT                             (1 << 5)
+#define OMAP4430_L3_1_STATDEP_SHIFT                             5
 #define OMAP4430_L3_1_STATDEP_MASK                              BITFIELD(5, 5)
 
 /*
@@ -1022,7 +1022,7 @@
  * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
  * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP
  */
-#define OMAP4430_L3_2_DYNDEP_SHIFT                              (1 << 6)
+#define OMAP4430_L3_2_DYNDEP_SHIFT                              6
 #define OMAP4430_L3_2_DYNDEP_MASK                               BITFIELD(6, 6)
 
 /*
@@ -1031,11 +1031,11 @@
  * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
  * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
  */
-#define OMAP4430_L3_2_STATDEP_SHIFT                             (1 << 6)
+#define OMAP4430_L3_2_STATDEP_SHIFT                             6
 #define OMAP4430_L3_2_STATDEP_MASK                              BITFIELD(6, 6)
 
 /* Used by CM_L3_1_DYNAMICDEP */
-#define OMAP4430_L4CFG_DYNDEP_SHIFT                             (1 << 12)
+#define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
 #define OMAP4430_L4CFG_DYNDEP_MASK                              BITFIELD(12, 12)
 
 /*
@@ -1043,11 +1043,11 @@
  * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
  * CM_TESLA_STATICDEP
  */
-#define OMAP4430_L4CFG_STATDEP_SHIFT                            (1 << 12)
+#define OMAP4430_L4CFG_STATDEP_SHIFT                            12
 #define OMAP4430_L4CFG_STATDEP_MASK                             BITFIELD(12, 12)
 
 /* Used by CM_L3_2_DYNAMICDEP */
-#define OMAP4430_L4PER_DYNDEP_SHIFT                             (1 << 13)
+#define OMAP4430_L4PER_DYNDEP_SHIFT                             13
 #define OMAP4430_L4PER_DYNDEP_MASK                              BITFIELD(13, 13)
 
 /*
@@ -1055,36 +1055,36 @@
  * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
  * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
  */
-#define OMAP4430_L4PER_STATDEP_SHIFT                            (1 << 13)
+#define OMAP4430_L4PER_STATDEP_SHIFT                            13
 #define OMAP4430_L4PER_STATDEP_MASK                             BITFIELD(13, 13)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
-#define OMAP4430_L4SEC_DYNDEP_SHIFT                             (1 << 14)
+#define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
 #define OMAP4430_L4SEC_DYNDEP_MASK                              BITFIELD(14, 14)
 
 /*
  * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
  * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP
  */
-#define OMAP4430_L4SEC_STATDEP_SHIFT                            (1 << 14)
+#define OMAP4430_L4SEC_STATDEP_SHIFT                            14
 #define OMAP4430_L4SEC_STATDEP_MASK                             BITFIELD(14, 14)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_L4WKUP_DYNDEP_SHIFT                            (1 << 15)
+#define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
 #define OMAP4430_L4WKUP_DYNDEP_MASK                             BITFIELD(15, 15)
 
 /*
  * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
  * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
  */
-#define OMAP4430_L4WKUP_STATDEP_SHIFT                           (1 << 15)
+#define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
 #define OMAP4430_L4WKUP_STATDEP_MASK                            BITFIELD(15, 15)
 
 /*
  * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
  * CM_MPU_DYNAMICDEP
  */
-#define OMAP4430_MEMIF_DYNDEP_SHIFT                             (1 << 4)
+#define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
 #define OMAP4430_MEMIF_DYNDEP_MASK                              BITFIELD(4, 4)
 
 /*
@@ -1093,7 +1093,7 @@
  * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
  * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
  */
-#define OMAP4430_MEMIF_STATDEP_SHIFT                            (1 << 4)
+#define OMAP4430_MEMIF_STATDEP_SHIFT                            4
 #define OMAP4430_MEMIF_STATDEP_MASK                             BITFIELD(4, 4)
 
 /*
@@ -1103,7 +1103,7 @@
  * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
  * CM_SSC_MODFREQDIV_DPLL_MPU
  */
-#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      (1 << 8)
+#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       BITFIELD(8, 10)
 
 /*
@@ -1113,7 +1113,7 @@
  * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
  * CM_SSC_MODFREQDIV_DPLL_MPU
  */
-#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      (1 << 0)
+#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       BITFIELD(0, 6)
 
 /*
@@ -1169,23 +1169,23 @@
  * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
  * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
  */
-#define OMAP4430_MODULEMODE_SHIFT                               (1 << 0)
+#define OMAP4430_MODULEMODE_SHIFT                               0
 #define OMAP4430_MODULEMODE_MASK                                BITFIELD(0, 1)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      (1 << 9)
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       BITFIELD(9, 9)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       (1 << 8)
+#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        BITFIELD(8, 8)
 
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         (1 << 9)
+#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         9
 #define OMAP4430_OPTFCLKEN_CLK32K_MASK                          BITFIELD(9, 9)
 
 /* Used by CM_CAM_ISS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         BITFIELD(8, 8)
 
 /*
@@ -1195,119 +1195,119 @@
  * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
  * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE
  */
-#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          (1 << 8)
+#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           BITFIELD(8, 8)
 
 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         BITFIELD(8, 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         (1 << 8)
+#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          BITFIELD(8, 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          (1 << 8)
+#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
 #define OMAP4430_OPTFCLKEN_FCLK0_MASK                           BITFIELD(8, 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          (1 << 9)
+#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
 #define OMAP4430_OPTFCLKEN_FCLK1_MASK                           BITFIELD(9, 9)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          (1 << 10)
+#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           BITFIELD(10, 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     (1 << 15)
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      BITFIELD(15, 15)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                (1 << 13)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 BITFIELD(13, 13)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                (1 << 14)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 BITFIELD(14, 14)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 (1 << 11)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  BITFIELD(11, 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 (1 << 12)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  BITFIELD(12, 12)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  (1 << 8)
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   BITFIELD(8, 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                (1 << 9)
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 BITFIELD(9, 9)
 
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         BITFIELD(8, 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     BITFIELD(10, 10)
 
 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              (1 << 11)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               BITFIELD(11, 11)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        (1 << 10)
+#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         BITFIELD(10, 10)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         (1 << 11)
+#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          BITFIELD(11, 11)
 
 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       (1 << 8)
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        BITFIELD(8, 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    (1 << 8)
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     BITFIELD(8, 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    (1 << 9)
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     BITFIELD(9, 9)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     BITFIELD(10, 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    (1 << 8)
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     BITFIELD(8, 8)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    (1 << 9)
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     BITFIELD(9, 9)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
-#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     BITFIELD(10, 10)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           (1 << 8)
+#define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
 #define OMAP4430_OPTFCLKEN_XCLK_MASK                            BITFIELD(8, 8)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */
-#define OMAP4430_OVERRIDE_ENABLE_SHIFT                          (1 << 19)
+#define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
 #define OMAP4430_OVERRIDE_ENABLE_MASK                           BITFIELD(19, 19)
 
 /* Used by CM_CLKSEL_ABE */
-#define OMAP4430_PAD_CLKS_GATE_SHIFT                            (1 << 8)
+#define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
 #define OMAP4430_PAD_CLKS_GATE_MASK                             BITFIELD(8, 8)
 
 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
-#define OMAP4430_PERF_CURRENT_SHIFT                             (1 << 0)
+#define OMAP4430_PERF_CURRENT_SHIFT                             0
 #define OMAP4430_PERF_CURRENT_MASK                              BITFIELD(0, 7)
 
 /*
@@ -1315,66 +1315,66 @@
  * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
  * CM_IVA_DVFS_PERF_TESLA
  */
-#define OMAP4430_PERF_REQ_SHIFT                                 (1 << 0)
+#define OMAP4430_PERF_REQ_SHIFT                                 0
 #define OMAP4430_PERF_REQ_MASK                                  BITFIELD(0, 7)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT                         (1 << 0)
+#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT                         0
 #define OMAP4430_PER_DPLL_EMU_DIV_MASK                          BITFIELD(0, 6)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT                        (1 << 8)
+#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT                        8
 #define OMAP4430_PER_DPLL_EMU_MULT_MASK                         BITFIELD(8, 18)
 
 /* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE1_COMPLETED_SHIFT                         (1 << 0)
+#define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
 #define OMAP4430_PHASE1_COMPLETED_MASK                          BITFIELD(0, 0)
 
 /* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE2A_COMPLETED_SHIFT                        (1 << 1)
+#define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
 #define OMAP4430_PHASE2A_COMPLETED_MASK                         BITFIELD(1, 1)
 
 /* Used by CM_RESTORE_ST */
-#define OMAP4430_PHASE2B_COMPLETED_SHIFT                        (1 << 2)
+#define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
 #define OMAP4430_PHASE2B_COMPLETED_MASK                         BITFIELD(2, 2)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         (1 << 20)
+#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
 #define OMAP4430_PMD_STM_MUX_CTRL_MASK                          BITFIELD(20, 21)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
-#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       (1 << 22)
+#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        BITFIELD(22, 23)
 
 /* Used by CM_DYN_DEP_PRESCAL */
-#define OMAP4430_PRESCAL_SHIFT                                  (1 << 0)
+#define OMAP4430_PRESCAL_SHIFT                                  0
 #define OMAP4430_PRESCAL_MASK                                   BITFIELD(0, 5)
 
 /* Used by REVISION_CM2, REVISION_CM1 */
-#define OMAP4430_REV_SHIFT                                      (1 << 0)
+#define OMAP4430_REV_SHIFT                                      0
 #define OMAP4430_REV_MASK                                       BITFIELD(0, 7)
 
 /*
  * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
  * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
  */
-#define OMAP4430_SAR_MODE_SHIFT                                 (1 << 4)
+#define OMAP4430_SAR_MODE_SHIFT                                 4
 #define OMAP4430_SAR_MODE_MASK                                  BITFIELD(4, 4)
 
 /* Used by CM_SCALE_FCLK */
-#define OMAP4430_SCALE_FCLK_SHIFT                               (1 << 0)
+#define OMAP4430_SCALE_FCLK_SHIFT                               0
 #define OMAP4430_SCALE_FCLK_MASK                                BITFIELD(0, 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_SDMA_DYNDEP_SHIFT                              (1 << 11)
+#define OMAP4430_SDMA_DYNDEP_SHIFT                              11
 #define OMAP4430_SDMA_DYNDEP_MASK                               BITFIELD(11, 11)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP4430_SDMA_STATDEP_SHIFT                             (1 << 11)
+#define OMAP4430_SDMA_STATDEP_SHIFT                             11
 #define OMAP4430_SDMA_STATDEP_MASK                              BITFIELD(11, 11)
 
 /* Used by CM_CLKSEL_ABE */
-#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         (1 << 10)
+#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
 #define OMAP4430_SLIMBUS_CLK_GATE_MASK                          BITFIELD(10, 10)
 
 /*
@@ -1390,7 +1390,7 @@
  * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
  * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
  */
-#define OMAP4430_STBYST_SHIFT                                   (1 << 18)
+#define OMAP4430_STBYST_SHIFT                                   18
 #define OMAP4430_STBYST_MASK                                    BITFIELD(18, 18)
 
 /*
@@ -1398,11 +1398,11 @@
  * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU
  */
-#define OMAP4430_ST_DPLL_CLK_SHIFT                              (1 << 0)
+#define OMAP4430_ST_DPLL_CLK_SHIFT                              0
 #define OMAP4430_ST_DPLL_CLK_MASK                               BITFIELD(0, 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
-#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        (1 << 9)
+#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         BITFIELD(9, 9)
 
 /*
@@ -1410,58 +1410,58 @@
  * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
  * CM_DIV_M2_DPLL_MPU
  */
-#define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           (1 << 9)
+#define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            BITFIELD(9, 9)
 
 /*
  * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
  * CM_DIV_M3_DPLL_CORE
  */
-#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        (1 << 9)
+#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         BITFIELD(9, 9)
 
 /* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
-#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         (1 << 11)
+#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          BITFIELD(11, 11)
 
 /*
  * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
  * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
  */
-#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      BITFIELD(9, 9)
 
 /*
  * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
  * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
  */
-#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      BITFIELD(9, 9)
 
 /*
  * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
  * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
  */
-#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      BITFIELD(9, 9)
 
 /*
  * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
  * CM_DIV_M7_DPLL_CORE
  */
-#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      BITFIELD(9, 9)
 
 /* Used by CM_SYS_CLKSEL */
-#define OMAP4430_SYS_CLKSEL_SHIFT                               (1 << 0)
+#define OMAP4430_SYS_CLKSEL_SHIFT                               0
 #define OMAP4430_SYS_CLKSEL_MASK                                BITFIELD(0, 2)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
-#define OMAP4430_TESLA_DYNDEP_SHIFT                             (1 << 1)
+#define OMAP4430_TESLA_DYNDEP_SHIFT                             1
 #define OMAP4430_TESLA_DYNDEP_MASK                              BITFIELD(1, 1)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
-#define OMAP4430_TESLA_STATDEP_SHIFT                            (1 << 1)
+#define OMAP4430_TESLA_STATDEP_SHIFT                            1
 #define OMAP4430_TESLA_STATDEP_MASK                             BITFIELD(1, 1)
 
 /*
@@ -1469,6 +1469,6 @@
  * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
  * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
-#define OMAP4430_WINDOWSIZE_SHIFT                               (1 << 24)
+#define OMAP4430_WINDOWSIZE_SHIFT                               24
 #define OMAP4430_WINDOWSIZE_MASK                                BITFIELD(24, 27)
 #endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 90a4086fbdf4..4e4ac8ccd7f5 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -67,7 +67,8 @@
 #define CM_CLKSEL                                       0x0040
 #define CM_CLKSEL1                                      CM_CLKSEL
 #define CM_CLKSEL2                                      0x0044
-#define CM_CLKSTCTRL                                    0x0048
+#define OMAP2_CM_CLKSTCTRL                              0x0048
+#define OMAP4_CM_CLKSTCTRL                              0x0000
 
 
 /* Architecture-specific registers */
@@ -88,7 +89,7 @@
 #define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
 #define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
 #define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
-#define OMAP3430_CM_CLKSEL3                             CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
 #define OMAP3430_CM_CLKSTST                             0x004c
 #define OMAP3430ES2_CM_CLKSEL4                          0x004c
 #define OMAP3430ES2_CM_CLKSEL5                          0x0050
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll3xxx.c
index f6055b493294..2b559fc64855 100644
--- a/arch/arm/mach-omap2/dpll.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -44,17 +44,7 @@
 
 #define MAX_DPLL_WAIT_TRIES             1000000
 
-
-/**
- * omap3_dpll_recalc - recalculate DPLL rate
- * @clk: DPLL struct clk
- *
- * Recalculate and propagate the DPLL rate.
- */
-unsigned long omap3_dpll_recalc(struct clk *clk)
-{
-        return omap2_get_dpll_rate(clk);
-}
+/* Private functions */
 
 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
@@ -136,8 +126,6 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
         return f;
 }
 
-/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
-
 /*
  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
  * @clk: pointer to a DPLL struct clk
@@ -237,6 +225,63 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
         return 0;
 }
 
+/*
+ * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ * @freqsel: FREQSEL value to set
+ *
+ * Program the DPLL with the supplied M, N values, and wait for the DPLL to
+ * lock..  Returns -EINVAL upon error, or 0 upon success.
+ */
+static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+{
+        struct dpll_data *dd = clk->dpll_data;
+        u32 v;
+
+        /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+        _omap3_noncore_dpll_bypass(clk);
+
+        /* Set jitter correction */
+        if (!cpu_is_omap44xx()) {
+                v = __raw_readl(dd->control_reg);
+                v &= ~dd->freqsel_mask;
+                v |= freqsel << __ffs(dd->freqsel_mask);
+                __raw_writel(v, dd->control_reg);
+        }
+
+        /* Set DPLL multiplier, divider */
+        v = __raw_readl(dd->mult_div1_reg);
+        v &= ~(dd->mult_mask | dd->div1_mask);
+        v |= m << __ffs(dd->mult_mask);
+        v |= (n - 1) << __ffs(dd->div1_mask);
+        __raw_writel(v, dd->mult_div1_reg);
+
+        /* We let the clock framework set the other output dividers later */
+
+        /* REVISIT: Set ramp-up delay? */
+
+        _omap3_noncore_dpll_lock(clk);
+
+        return 0;
+}
+
+/* Public functions */
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+unsigned long omap3_dpll_recalc(struct clk *clk)
+{
+        return omap2_get_dpll_rate(clk);
+}
+
+/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+
 /**
  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
  * @clk: pointer to a DPLL struct clk
@@ -292,48 +337,6 @@ void omap3_noncore_dpll_disable(struct clk *clk)
 
 /* Non-CORE DPLL rate set code */
 
-/*
- * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
- * @clk: struct clk * of DPLL to set
- * @m: DPLL multiplier to set
- * @n: DPLL divider to set
- * @freqsel: FREQSEL value to set
- *
- * Program the DPLL with the supplied M, N values, and wait for the DPLL to
- * lock..  Returns -EINVAL upon error, or 0 upon success.
- */
-int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
-{
-        struct dpll_data *dd = clk->dpll_data;
-        u32 v;
-
-        /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
-        _omap3_noncore_dpll_bypass(clk);
-
-        /* Set jitter correction */
-        if (!cpu_is_omap44xx()) {
-                v = __raw_readl(dd->control_reg);
-                v &= ~dd->freqsel_mask;
-                v |= freqsel << __ffs(dd->freqsel_mask);
-                __raw_writel(v, dd->control_reg);
-        }
-
-        /* Set DPLL multiplier, divider */
-        v = __raw_readl(dd->mult_div1_reg);
-        v &= ~(dd->mult_mask | dd->div1_mask);
-        v |= m << __ffs(dd->mult_mask);
-        v |= (n - 1) << __ffs(dd->div1_mask);
-        __raw_writel(v, dd->mult_div1_reg);
-
-        /* We let the clock framework set the other output dividers later */
-
-        /* REVISIT: Set ramp-up delay? */
-
-        _omap3_noncore_dpll_lock(clk);
-
-        return 0;
-}
-
 /**
  * omap3_noncore_dpll_set_rate - set non-core DPLL rate
  * @clk: struct clk * of DPLL to set
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 3d65c50bd017..9e7c4aeeae02 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -281,6 +281,7 @@ void __init omap4_check_revision(void)
 
         if ((hawkeye == 0xb852) && (rev == 0x0)) {
                 omap_revision = OMAP4430_REV_ES1_0;
+                omap_chip.oc |= CHIP_IS_OMAP4430ES1;
                 pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
                 return;
         }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5a7996402c53..01ef2ae93593 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -35,7 +35,9 @@
 #include <plat/serial.h>
 #include <plat/vram.h>
 
-#include "clock.h"
+#include "clock2xxx.h"
+#include "clock34xx.h"
+#include "clock44xx.h"
 
 #include <plat/omap-pm.h>
 #include <plat/powerdomain.h>
@@ -312,15 +314,24 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
         else if (cpu_is_omap34xx())
                 hwmods = omap34xx_hwmods;
 
+        pwrdm_init(powerdomains_omap);
+        clkdm_init(clockdomains_omap, clkdm_autodeps);
 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
         /* The OPP tables have to be registered before a clk init */
         omap_hwmod_init(hwmods);
         omap2_mux_init();
         omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
-        pwrdm_init(powerdomains_omap);
-        clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
 #endif
-        omap2_clk_init();
+
+        if (cpu_is_omap24xx())
+                omap2xxx_clk_init();
+        else if (cpu_is_omap34xx())
+                omap3xxx_clk_init();
+        else if (cpu_is_omap44xx())
+                omap4xxx_clk_init();
+        else
+                pr_err("Could not init clock framework - unknown CPU\n");
+
         omap_serial_early_init();
 #ifndef CONFIG_ARCH_OMAP4
         omap_hwmod_late_init();
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 478ae585ca39..70912d1c71e0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -299,15 +299,14 @@ static int _disable_wakeup(struct omap_hwmod *oh)
  * be accessed by the IVA, there should be a sleepdep between the IVA
  * initiator and the module).  Only applies to modules in smart-idle
  * mode.  Returns -EINVAL upon error or passes along
- * pwrdm_add_sleepdep() value upon success.
+ * clkdm_add_sleepdep() value upon success.
  */
 static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 {
         if (!oh->_clk)
                 return -EINVAL;
 
-        return pwrdm_add_sleepdep(oh->_clk->clkdm->pwrdm.ptr,
-                                  init_oh->_clk->clkdm->pwrdm.ptr);
+        return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
 }
 
 /**
@@ -320,15 +319,14 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
  * be accessed by the IVA, there should be no sleepdep between the IVA
  * initiator and the module).  Only applies to modules in smart-idle
  * mode.  Returns -EINVAL upon error or passes along
- * pwrdm_add_sleepdep() value upon success.
+ * clkdm_del_sleepdep() value upon success.
  */
 static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 {
         if (!oh->_clk)
                 return -EINVAL;
 
-        return pwrdm_del_sleepdep(oh->_clk->clkdm->pwrdm.ptr,
-                                  init_oh->_clk->clkdm->pwrdm.ptr);
+        return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
 }
 
 /**
@@ -994,6 +992,23 @@ void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs)
         __raw_writel(v, oh->_rt_va + reg_offs);
 }
 
+int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
+{
+        u32 v;
+        int retval = 0;
+
+        if (!oh)
+                return -EINVAL;
+
+        v = oh->_sysc_cache;
+
+        retval = _set_slave_idlemode(oh, idlemode, &v);
+        if (!retval)
+                _write_sysconfig(v, oh);
+
+        return retval;
+}
+
 /**
  * omap_hwmod_register - register a struct omap_hwmod
  * @oh: struct omap_hwmod *
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a0866268aa41..0ce356f351a3 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -67,9 +67,9 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
 #if 0
                 /* MPU */
                 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
-                DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
-                DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
-                DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
+                DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
+                DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
+                DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 #endif
 #if 0
@@ -93,7 +93,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
-                DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
+                DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
 #endif
 #if 0
                 /* DSP */
@@ -103,11 +103,11 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
                         DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
-                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
-                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
-                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
-                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
-                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
+                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
+                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
+                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
+                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
+                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
                 }
 #endif
         } else {
@@ -577,7 +577,7 @@ static int __init pm_dbg_init(void)
         (void) debugfs_create_file("time", S_IRUGO,
                 d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
 
-        pwrdm_for_each_nolock(pwrdms_setup, (void *)d);
+        pwrdm_for_each(pwrdms_setup, (void *)d);
 
         pm_dbg_dir = debugfs_create_dir("registers", d);
         if (IS_ERR(pm_dbg_dir))
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index cba05b9f041f..374299ea7ade 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -57,11 +57,8 @@ static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
                                   void __iomem *sdrc_power);
 
-static struct powerdomain *mpu_pwrdm;
-static struct powerdomain *core_pwrdm;
-
-static struct clockdomain *dsp_clkdm;
-static struct clockdomain *gfx_clkdm;
+static struct powerdomain *mpu_pwrdm, *core_pwrdm;
+static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
 
 static struct clk *osc_ck, *emul_ck;
 
@@ -219,11 +216,12 @@ static void omap2_enter_mpu_retention(void)
                 /* Try to enter MPU retention */
                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
                                   OMAP_LOGICRETSTATE,
-                                  MPU_MOD, PM_PWSTCTRL);
+                                  MPU_MOD, OMAP2_PM_PWSTCTRL);
         } else {
                 /* Block MPU retention */
 
-                prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
+                prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD,
+                                                 OMAP2_PM_PWSTCTRL);
                 only_idle = 1;
         }
 
@@ -333,9 +331,17 @@ static struct platform_suspend_ops omap_pm_ops = {
         .valid          = suspend_valid_only_mem,
 };
 
-static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused)
+/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        omap2_clkdm_allow_idle(clkdm);
+        clkdm_clear_all_wkdeps(clkdm);
+        clkdm_clear_all_sleepdeps(clkdm);
+
+        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+                omap2_clkdm_allow_idle(clkdm);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+                 atomic_read(&clkdm->usecount) == 0)
+                omap2_clkdm_sleep(clkdm);
         return 0;
 }
 
@@ -348,14 +354,6 @@ static void __init prcm_setup_regs(void)
         prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 
-        /* Set all domain wakeup dependencies */
-        prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
-        if (cpu_is_omap2430())
-                prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
-
         /*
          * Set CORE powerdomain memory banks to retain their contents
          * during RETENTION
@@ -384,8 +382,12 @@ static void __init prcm_setup_regs(void)
         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
         omap2_clkdm_sleep(gfx_clkdm);
 
-        /* Enable clockdomain hardware-supervised control for all clkdms */
-        clkdm_for_each(_pm_clkdm_enable_hwsup, NULL);
+        /*
+         * Clear clockdomain wakeup dependencies and enable
+         * hardware-supervised idle for all clkdms
+         */
+        clkdm_for_each(clkdms_setup, NULL);
+        clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
         /* Enable clock autoidle for all domains */
         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
@@ -481,7 +483,7 @@ static int __init omap2_pm_init(void)
         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 
-        /* Look up important powerdomains, clockdomains */
+        /* Look up important powerdomains */
 
         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
         if (!mpu_pwrdm)
@@ -491,9 +493,19 @@ static int __init omap2_pm_init(void)
         if (!core_pwrdm)
                 pr_err("PM: core_pwrdm not found\n");
 
+        /* Look up important clockdomains */
+
+        mpu_clkdm = clkdm_lookup("mpu_clkdm");
+        if (!mpu_clkdm)
+                pr_err("PM: mpu_clkdm not found\n");
+
+        wkup_clkdm = clkdm_lookup("wkup_clkdm");
+        if (!wkup_clkdm)
+                pr_err("PM: wkup_clkdm not found\n");
+
         dsp_clkdm = clkdm_lookup("dsp_clkdm");
         if (!dsp_clkdm)
-                pr_err("PM: mpu_clkdm not found\n");
+                pr_err("PM: dsp_clkdm not found\n");
 
         gfx_clkdm = clkdm_lookup("gfx_clkdm");
         if (!gfx_clkdm)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 910a7acf542d..5087b153b093 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -685,7 +685,7 @@ static void __init omap3_iva_idle(void)
         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
                           OMAP3430_RST2_IVA2 |
                           OMAP3430_RST3_IVA2,
-                          OMAP3430_IVA2_MOD, RM_RSTCTRL);
+                          OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Enable IVA2 clock */
         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
@@ -696,7 +696,7 @@ static void __init omap3_iva_idle(void)
                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 
         /* Un-reset IVA2 */
-        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
+        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Disable IVA2 clock */
         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
@@ -705,7 +705,7 @@ static void __init omap3_iva_idle(void)
         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
                           OMAP3430_RST2_IVA2 |
                           OMAP3430_RST3_IVA2,
-                          OMAP3430_IVA2_MOD, RM_RSTCTRL);
+                          OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 }
 
 static void __init omap3_d2d_idle(void)
@@ -728,8 +728,8 @@ static void __init omap3_d2d_idle(void)
         /* reset modem */
         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
-                          CORE_MOD, RM_RSTCTRL);
-        prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
+                          CORE_MOD, OMAP2_RM_RSTCTRL);
+        prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 }
 
 static void __init prcm_setup_regs(void)
@@ -916,13 +916,13 @@ static void __init prcm_setup_regs(void)
         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 
         /* Clear any pending 'reset' flags */
-        prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
+        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 
         /* Clear any pending PRCM interrupts */
         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
@@ -998,6 +998,9 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  */
 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
+        clkdm_clear_all_wkdeps(clkdm);
+        clkdm_clear_all_sleepdeps(clkdm);
+
         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
                 omap2_clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
@@ -1018,6 +1021,7 @@ void omap_push_sram_idle(void)
 static int __init omap3_pm_init(void)
 {
         struct power_state *pwrst, *tmp;
+        struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
         int ret;
 
         if (!cpu_is_omap34xx())
@@ -1057,6 +1061,11 @@ static int __init omap3_pm_init(void)
         core_pwrdm = pwrdm_lookup("core_pwrdm");
         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 
+        neon_clkdm = clkdm_lookup("neon_clkdm");
+        mpu_clkdm = clkdm_lookup("mpu_clkdm");
+        per_clkdm = clkdm_lookup("per_clkdm");
+        core_clkdm = clkdm_lookup("core_clkdm");
+
         omap_push_sram_idle();
 #ifdef CONFIG_SUSPEND
         suspend_set_ops(&omap_pm_ops);
@@ -1065,14 +1074,14 @@ static int __init omap3_pm_init(void)
         pm_idle = omap3_pm_idle;
         omap3_idle_init();
 
-        pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
+        clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
         /*
          * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
          * IO-pad wakeup.  Otherwise it will unnecessarily waste power
          * waking up PER with every CORE wakeup - see
          * http://marc.info/?l=linux-omap&m=121852150710062&w=2
         */
-        pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
+        clkdm_add_wkdep(per_clkdm, core_clkdm);
 
         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
                 omap3_secure_ram_storage =
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 26b3f3ee82a3..dc03289d5dea 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -2,10 +2,12 @@
  * OMAP powerdomain control
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
+ * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -26,12 +28,15 @@
 
 #include "cm.h"
 #include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
 
 #include <plat/cpu.h>
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
+#include <plat/prcm.h>
 
 #include "pm.h"
 
@@ -40,28 +45,42 @@ enum {
         PWRDM_STATE_PREV,
 };
 
-/* pwrdm_list contains all registered struct powerdomains */
-static LIST_HEAD(pwrdm_list);
+/* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */
+static u16 pwrstctrl_reg_offs;
 
-/*
- * pwrdm_rwlock protects pwrdm_list add and del ops - also reused to
- * protect pwrdm_clkdms[] during clkdm add/del ops
+/* Variable holding value of the CPU dependent PWRSTST Register Offset */
+static u16 pwrstst_reg_offs;
+
+/* OMAP3 and OMAP4 specific register bit initialisations
+ * Notice that the names here are not according to each power
+ * domain but the bit mapping used applies to all of them
  */
-static DEFINE_RWLOCK(pwrdm_rwlock);
 
+/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
+#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
+#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
+#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
+#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
+#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
 
-/* Private functions */
+/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
+#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE
+#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE
+#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE
+#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE
+#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
 
-static u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
-        u32 v;
+/* OMAP3 and OMAP4 Memory Status bits */
+#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
+#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
+#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
+#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
+#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
 
-        v = prm_read_mod_reg(domain, idx);
-        v &= mask;
-        v >>= __ffs(mask);
+/* pwrdm_list contains all registered struct powerdomains */
+static LIST_HEAD(pwrdm_list);
 
-        return v;
-}
+/* Private functions */
 
 static struct powerdomain *_pwrdm_lookup(const char *name)
 {
@@ -79,32 +98,40 @@ static struct powerdomain *_pwrdm_lookup(const char *name)
         return pwrdm;
 }
 
-/* _pwrdm_deps_lookup - look up the specified powerdomain in a pwrdm list */
-static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
-                                              struct pwrdm_dep *deps)
+/**
+ * _pwrdm_register - register a powerdomain
+ * @pwrdm: struct powerdomain * to register
+ *
+ * Adds a powerdomain to the internal powerdomain list.  Returns
+ * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
+ * already registered by the provided name, or 0 upon success.
+ */
+static int _pwrdm_register(struct powerdomain *pwrdm)
 {
-        struct pwrdm_dep *pd;
+        int i;
 
-        if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip))
-                return ERR_PTR(-EINVAL);
+        if (!pwrdm)
+                return -EINVAL;
 
-        for (pd = deps; pd->pwrdm_name; pd++) {
+        if (!omap_chip_is(pwrdm->omap_chip))
+                return -EINVAL;
 
-                if (!omap_chip_is(pd->omap_chip))
-                        continue;
+        if (_pwrdm_lookup(pwrdm->name))
+                return -EEXIST;
 
-                if (!pd->pwrdm && pd->pwrdm_name)
-                        pd->pwrdm = pwrdm_lookup(pd->pwrdm_name);
+        list_add(&pwrdm->node, &pwrdm_list);
 
-                if (pd->pwrdm == pwrdm)
-                        break;
+        /* Initialize the powerdomain's state counter */
+        for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
+                pwrdm->state_counter[i] = 0;
 
-        }
+        pwrdm_wait_transition(pwrdm);
+        pwrdm->state = pwrdm_read_pwrst(pwrdm);
+        pwrdm->state_counter[pwrdm->state] = 1;
 
-        if (!pd->pwrdm_name)
-                return ERR_PTR(-ENOENT);
+        pr_debug("powerdomain: registered %s\n", pwrdm->name);
 
-        return pd->pwrdm;
+        return 0;
 }
 
 static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
@@ -154,134 +181,71 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
         return 0;
 }
 
-static __init void _pwrdm_setup(struct powerdomain *pwrdm)
-{
-        int i;
-
-        for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
-                pwrdm->state_counter[i] = 0;
-
-        pwrdm_wait_transition(pwrdm);
-        pwrdm->state = pwrdm_read_pwrst(pwrdm);
-        pwrdm->state_counter[pwrdm->state] = 1;
-
-}
-
 /* Public functions */
 
 /**
  * pwrdm_init - set up the powerdomain layer
+ * @pwrdm_list: array of struct powerdomain pointers to register
  *
- * Loop through the list of powerdomains, registering all that are
- * available on the current CPU. If pwrdm_list is supplied and not
- * null, all of the referenced powerdomains will be registered.  No
- * return value.
+ * Loop through the array of powerdomains @pwrdm_list, registering all
+ * that are available on the current CPU. If pwrdm_list is supplied
+ * and not null, all of the referenced powerdomains will be
+ * registered.  No return value.  XXX pwrdm_list is not really a
+ * "list"; it is an array.  Rename appropriately.
  */
 void pwrdm_init(struct powerdomain **pwrdm_list)
 {
         struct powerdomain **p = NULL;
 
-        if (pwrdm_list) {
-                for (p = pwrdm_list; *p; p++) {
-                        pwrdm_register(*p);
-                        _pwrdm_setup(*p);
-                }
+        if (cpu_is_omap24xx() | cpu_is_omap34xx()) {
+                pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL;
+                pwrstst_reg_offs = OMAP2_PM_PWSTST;
+        } else if (cpu_is_omap44xx()) {
+                pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL;
+                pwrstst_reg_offs = OMAP4_PM_PWSTST;
+        } else {
+                printk(KERN_ERR "Power Domain struct not supported for " \
+                                                        "this CPU\n");
+                return;
         }
-}
 
-/**
- * pwrdm_register - register a powerdomain
- * @pwrdm: struct powerdomain * to register
- *
- * Adds a powerdomain to the internal powerdomain list.  Returns
- * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
- * already registered by the provided name, or 0 upon success.
- */
-int pwrdm_register(struct powerdomain *pwrdm)
-{
-        unsigned long flags;
-        int ret = -EINVAL;
-
-        if (!pwrdm)
-                return -EINVAL;
-
-        if (!omap_chip_is(pwrdm->omap_chip))
-                return -EINVAL;
-
-        write_lock_irqsave(&pwrdm_rwlock, flags);
-        if (_pwrdm_lookup(pwrdm->name)) {
-                ret = -EEXIST;
-                goto pr_unlock;
+        if (pwrdm_list) {
+                for (p = pwrdm_list; *p; p++)
+                        _pwrdm_register(*p);
         }
-
-        list_add(&pwrdm->node, &pwrdm_list);
-
-        pr_debug("powerdomain: registered %s\n", pwrdm->name);
-        ret = 0;
-
-pr_unlock:
-        write_unlock_irqrestore(&pwrdm_rwlock, flags);
-
-        return ret;
-}
-
-/**
- * pwrdm_unregister - unregister a powerdomain
- * @pwrdm: struct powerdomain * to unregister
- *
- * Removes a powerdomain from the internal powerdomain list.  Returns
- * -EINVAL if pwrdm argument is NULL.
- */
-int pwrdm_unregister(struct powerdomain *pwrdm)
-{
-        unsigned long flags;
-
-        if (!pwrdm)
-                return -EINVAL;
-
-        write_lock_irqsave(&pwrdm_rwlock, flags);
-        list_del(&pwrdm->node);
-        write_unlock_irqrestore(&pwrdm_rwlock, flags);
-
-        pr_debug("powerdomain: unregistered %s\n", pwrdm->name);
-
-        return 0;
 }
 
 /**
  * pwrdm_lookup - look up a powerdomain by name, return a pointer
  * @name: name of powerdomain
  *
- * Find a registered powerdomain by its name.  Returns a pointer to the
- * struct powerdomain if found, or NULL otherwise.
+ * Find a registered powerdomain by its name @name.  Returns a pointer
+ * to the struct powerdomain if found, or NULL otherwise.
  */
 struct powerdomain *pwrdm_lookup(const char *name)
 {
         struct powerdomain *pwrdm;
-        unsigned long flags;
 
         if (!name)
                 return NULL;
 
-        read_lock_irqsave(&pwrdm_rwlock, flags);
         pwrdm = _pwrdm_lookup(name);
-        read_unlock_irqrestore(&pwrdm_rwlock, flags);
 
         return pwrdm;
 }
 
 /**
- * pwrdm_for_each_nolock - call function on each registered clockdomain
+ * pwrdm_for_each - call function on each registered clockdomain
  * @fn: callback function *
  *
- * Call the supplied function for each registered powerdomain.  The
- * callback function can return anything but 0 to bail out early from
- * the iterator.  Returns the last return value of the callback function, which
- * should be 0 for success or anything else to indicate failure; or -EINVAL if
- * the function pointer is null.
+ * Call the supplied function @fn for each registered powerdomain.
+ * The callback function @fn can return anything but 0 to bail out
+ * early from the iterator.  Returns the last return value of the
+ * callback function, which should be 0 for success or anything else
+ * to indicate failure; or -EINVAL if the function pointer is null.
  */
-int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
-                                void *user)
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+                   void *user)
 {
         struct powerdomain *temp_pwrdm;
         int ret = 0;
@@ -299,40 +263,17 @@ int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
 }
 
 /**
- * pwrdm_for_each - call function on each registered clockdomain
- * @fn: callback function *
- *
- * This function is the same as 'pwrdm_for_each_nolock()', but keeps the
- * &pwrdm_rwlock locked for reading, so no powerdomain structure manipulation
- * functions should be called from the callback, although hardware powerdomain
- * control functions are fine.
- */
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
-                        void *user)
-{
-        unsigned long flags;
-        int ret;
-
-        read_lock_irqsave(&pwrdm_rwlock, flags);
-        ret = pwrdm_for_each_nolock(fn, user);
-        read_unlock_irqrestore(&pwrdm_rwlock, flags);
-
-        return ret;
-}
-
-/**
  * pwrdm_add_clkdm - add a clockdomain to a powerdomain
  * @pwrdm: struct powerdomain * to add the clockdomain to
  * @clkdm: struct clockdomain * to associate with a powerdomain
  *
- * Associate the clockdomain 'clkdm' with a powerdomain 'pwrdm'.  This
+ * Associate the clockdomain @clkdm with a powerdomain @pwrdm.  This
  * enables the use of pwrdm_for_each_clkdm().  Returns -EINVAL if
  * presented with invalid pointers; -ENOMEM if memory could not be allocated;
  * or 0 upon success.
  */
 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
 {
-        unsigned long flags;
         int i;
         int ret = -EINVAL;
 
@@ -342,8 +283,6 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
         pr_debug("powerdomain: associating clockdomain %s with powerdomain "
                  "%s\n", clkdm->name, pwrdm->name);
 
-        write_lock_irqsave(&pwrdm_rwlock, flags);
-
         for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
                 if (!pwrdm->pwrdm_clkdms[i])
                         break;
@@ -368,8 +307,6 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
         ret = 0;
 
 pac_exit:
-        write_unlock_irqrestore(&pwrdm_rwlock, flags);
-
         return ret;
 }
 
@@ -378,14 +315,13 @@ pac_exit:
  * @pwrdm: struct powerdomain * to add the clockdomain to
  * @clkdm: struct clockdomain * to associate with a powerdomain
  *
- * Dissociate the clockdomain 'clkdm' from the powerdomain
- * 'pwrdm'. Returns -EINVAL if presented with invalid pointers;
- * -ENOENT if the clkdm was not associated with the powerdomain, or 0
- * upon success.
+ * Dissociate the clockdomain @clkdm from the powerdomain
+ * @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT
+ * if @clkdm was not associated with the powerdomain, or 0 upon
+ * success.
  */
 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
 {
-        unsigned long flags;
         int ret = -EINVAL;
         int i;
 
@@ -395,8 +331,6 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
         pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
                  "%s\n", clkdm->name, pwrdm->name);
 
-        write_lock_irqsave(&pwrdm_rwlock, flags);
-
         for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
                 if (pwrdm->pwrdm_clkdms[i] == clkdm)
                         break;
@@ -413,8 +347,6 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
         ret = 0;
 
 pdc_exit:
-        write_unlock_irqrestore(&pwrdm_rwlock, flags);
-
         return ret;
 }
 
@@ -423,259 +355,34 @@ pdc_exit:
  * @pwrdm: struct powerdomain * to iterate over
  * @fn: callback function *
  *
- * Call the supplied function for each clockdomain in the powerdomain
- * 'pwrdm'.  The callback function can return anything but 0 to bail
- * out early from the iterator.  The callback function is called with
- * the pwrdm_rwlock held for reading, so no powerdomain structure
- * manipulation functions should be called from the callback, although
- * hardware powerdomain control functions are fine.  Returns -EINVAL
- * if presented with invalid pointers; or passes along the last return
- * value of the callback function, which should be 0 for success or
- * anything else to indicate failure.
+ * Call the supplied function @fn for each clockdomain in the powerdomain
+ * @pwrdm.  The callback function can return anything but 0 to bail
+ * out early from the iterator.  Returns -EINVAL if presented with
+ * invalid pointers; or passes along the last return value of the
+ * callback function, which should be 0 for success or anything else
+ * to indicate failure.
  */
 int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
                          int (*fn)(struct powerdomain *pwrdm,
                                    struct clockdomain *clkdm))
 {
-        unsigned long flags;
         int ret = 0;
         int i;
 
         if (!fn)
                 return -EINVAL;
 
-        read_lock_irqsave(&pwrdm_rwlock, flags);
-
         for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
                 ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
 
-        read_unlock_irqrestore(&pwrdm_rwlock, flags);
-
         return ret;
 }
 
-
-/**
- * pwrdm_add_wkdep - add a wakeup dependency from pwrdm2 to pwrdm1
- * @pwrdm1: wake this struct powerdomain * up (dependent)
- * @pwrdm2: when this struct powerdomain * wakes up (source)
- *
- * When the powerdomain represented by pwrdm2 wakes up (due to an
- * interrupt), wake up pwrdm1.  Implemented in hardware on the OMAP,
- * this feature is designed to reduce wakeup latency of the dependent
- * powerdomain.  Returns -EINVAL if presented with invalid powerdomain
- * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
- * 0 upon success.
- */
-int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
-        struct powerdomain *p;
-
-        if (!pwrdm1)
-                return -EINVAL;
-
-        p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
-        if (IS_ERR(p)) {
-                pr_debug("powerdomain: hardware cannot set/clear wake up of "
-                         "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return PTR_ERR(p);
-        }
-
-        pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n",
-                 pwrdm1->name, pwrdm2->name);
-
-        prm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
-                             pwrdm1->prcm_offs, PM_WKDEP);
-
-        return 0;
-}
-
-/**
- * pwrdm_del_wkdep - remove a wakeup dependency from pwrdm2 to pwrdm1
- * @pwrdm1: wake this struct powerdomain * up (dependent)
- * @pwrdm2: when this struct powerdomain * wakes up (source)
- *
- * Remove a wakeup dependency that causes pwrdm1 to wake up when pwrdm2
- * wakes up.  Returns -EINVAL if presented with invalid powerdomain
- * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
- * 0 upon success.
- */
-int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
-        struct powerdomain *p;
-
-        if (!pwrdm1)
-                return -EINVAL;
-
-        p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
-        if (IS_ERR(p)) {
-                pr_debug("powerdomain: hardware cannot set/clear wake up of "
-                         "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return PTR_ERR(p);
-        }
-
-        pr_debug("powerdomain: hardware will no longer wake up %s after %s "
-                 "wakes up\n", pwrdm1->name, pwrdm2->name);
-
-        prm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
-                               pwrdm1->prcm_offs, PM_WKDEP);
-
-        return 0;
-}
-
-/**
- * pwrdm_read_wkdep - read wakeup dependency state from pwrdm2 to pwrdm1
- * @pwrdm1: wake this struct powerdomain * up (dependent)
- * @pwrdm2: when this struct powerdomain * wakes up (source)
- *
- * Return 1 if a hardware wakeup dependency exists wherein pwrdm1 will be
- * awoken when pwrdm2 wakes up; 0 if dependency is not set; -EINVAL
- * if either powerdomain pointer is invalid; or -ENOENT if the hardware
- * is incapable.
- *
- * REVISIT: Currently this function only represents software-controllable
- * wakeup dependencies.  Wakeup dependencies fixed in hardware are not
- * yet handled here.
- */
-int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
-        struct powerdomain *p;
-
-        if (!pwrdm1)
-                return -EINVAL;
-
-        p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
-        if (IS_ERR(p)) {
-                pr_debug("powerdomain: hardware cannot set/clear wake up of "
-                         "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return PTR_ERR(p);
-        }
-
-        return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP,
-                                        (1 << pwrdm2->dep_bit));
-}
-
-/**
- * pwrdm_add_sleepdep - add a sleep dependency from pwrdm2 to pwrdm1
- * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
- * @pwrdm2: when this struct powerdomain * is active (source)
- *
- * Prevent pwrdm1 from automatically going inactive (and then to
- * retention or off) if pwrdm2 is still active.  Returns -EINVAL if
- * presented with invalid powerdomain pointers or called on a machine
- * that does not support software-configurable hardware sleep dependencies,
- * -ENOENT if the specified dependency cannot be set in hardware, or
- * 0 upon success.
- */
-int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
-        struct powerdomain *p;
-
-        if (!cpu_is_omap34xx())
-                return -EINVAL;
-
-        if (!pwrdm1)
-                return -EINVAL;
-
-        p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
-        if (IS_ERR(p)) {
-                pr_debug("powerdomain: hardware cannot set/clear sleep "
-                         "dependency affecting %s from %s\n", pwrdm1->name,
-                         pwrdm2->name);
-                return PTR_ERR(p);
-        }
-
-        pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n",
-                 pwrdm1->name, pwrdm2->name);
-
-        cm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
-                            pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
-
-        return 0;
-}
-
-/**
- * pwrdm_del_sleepdep - remove a sleep dependency from pwrdm2 to pwrdm1
- * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
- * @pwrdm2: when this struct powerdomain * is active (source)
- *
- * Allow pwrdm1 to automatically go inactive (and then to retention or
- * off), independent of the activity state of pwrdm2.  Returns -EINVAL
- * if presented with invalid powerdomain pointers or called on a machine
- * that does not support software-configurable hardware sleep dependencies,
- * -ENOENT if the specified dependency cannot be cleared in hardware, or
- * 0 upon success.
- */
-int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
-        struct powerdomain *p;
-
-        if (!cpu_is_omap34xx())
-                return -EINVAL;
-
-        if (!pwrdm1)
-                return -EINVAL;
-
-        p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
-        if (IS_ERR(p)) {
-                pr_debug("powerdomain: hardware cannot set/clear sleep "
-                         "dependency affecting %s from %s\n", pwrdm1->name,
-                         pwrdm2->name);
-                return PTR_ERR(p);
-        }
-
-        pr_debug("powerdomain: will no longer prevent %s from sleeping if "
-                 "%s is active\n", pwrdm1->name, pwrdm2->name);
-
-        cm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
-                              pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
-
-        return 0;
-}
-
-/**
- * pwrdm_read_sleepdep - read sleep dependency state from pwrdm2 to pwrdm1
- * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
- * @pwrdm2: when this struct powerdomain * is active (source)
- *
- * Return 1 if a hardware sleep dependency exists wherein pwrdm1 will
- * not be allowed to automatically go inactive if pwrdm2 is active;
- * 0 if pwrdm1's automatic power state inactivity transition is independent
- * of pwrdm2's; -EINVAL if either powerdomain pointer is invalid or called
- * on a machine that does not support software-configurable hardware sleep
- * dependencies; or -ENOENT if the hardware is incapable.
- *
- * REVISIT: Currently this function only represents software-controllable
- * sleep dependencies.  Sleep dependencies fixed in hardware are not
- * yet handled here.
- */
-int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
-{
-        struct powerdomain *p;
-
-        if (!cpu_is_omap34xx())
-                return -EINVAL;
-
-        if (!pwrdm1)
-                return -EINVAL;
-
-        p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
-        if (IS_ERR(p)) {
-                pr_debug("powerdomain: hardware cannot set/clear sleep "
-                         "dependency affecting %s from %s\n", pwrdm1->name,
-                         pwrdm2->name);
-                return PTR_ERR(p);
-        }
-
-        return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP,
-                                        (1 << pwrdm2->dep_bit));
-}
-
 /**
  * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
  * @pwrdm: struct powerdomain *
  *
- * Return the number of controllable memory banks in powerdomain pwrdm,
+ * Return the number of controllable memory banks in powerdomain @pwrdm,
  * starting with 1.  Returns -EINVAL if the powerdomain pointer is null.
  */
 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
@@ -691,7 +398,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
  * @pwrdm: struct powerdomain * to set
  * @pwrst: one of the PWRDM_POWER_* macros
  *
- * Set the powerdomain pwrdm's next power state to pwrst.  The powerdomain
+ * Set the powerdomain @pwrdm's next power state to @pwrst.  The powerdomain
  * may not enter this state immediately if the preconditions for this state
  * have not been satisfied.  Returns -EINVAL if the powerdomain pointer is
  * null or if the power state is invalid for the powerdomin, or returns 0
@@ -710,7 +417,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 
         prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
                              (pwrst << OMAP_POWERSTATE_SHIFT),
-                             pwrdm->prcm_offs, PM_PWSTCTRL);
+                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
 
         return 0;
 }
@@ -719,7 +426,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
  * pwrdm_read_next_pwrst - get next powerdomain power state
  * @pwrdm: struct powerdomain * to get power state
  *
- * Return the powerdomain pwrdm's next power state.  Returns -EINVAL
+ * Return the powerdomain @pwrdm's next power state.  Returns -EINVAL
  * if the powerdomain pointer is null or returns the next power state
  * upon success.
  */
@@ -728,15 +435,15 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL,
-                                        OMAP_POWERSTATE_MASK);
+        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                 pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK);
 }
 
 /**
  * pwrdm_read_pwrst - get current powerdomain power state
  * @pwrdm: struct powerdomain * to get power state
  *
- * Return the powerdomain pwrdm's current power state.  Returns -EINVAL
+ * Return the powerdomain @pwrdm's current power state. Returns -EINVAL
  * if the powerdomain pointer is null or returns the current power state
  * upon success.
  */
@@ -745,15 +452,15 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm)
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
-                                        OMAP_POWERSTATEST_MASK);
+        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                 pwrstst_reg_offs, OMAP_POWERSTATEST_MASK);
 }
 
 /**
  * pwrdm_read_prev_pwrst - get previous powerdomain power state
  * @pwrdm: struct powerdomain * to get previous power state
  *
- * Return the powerdomain pwrdm's previous power state.  Returns -EINVAL
+ * Return the powerdomain @pwrdm's previous power state.  Returns -EINVAL
  * if the powerdomain pointer is null or returns the previous power state
  * upon success.
  */
@@ -771,11 +478,11 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
  * @pwrdm: struct powerdomain * to set
  * @pwrst: one of the PWRDM_POWER_* macros
  *
- * Set the next power state that the logic portion of the powerdomain
- * pwrdm will enter when the powerdomain enters retention.  This will
- * be either RETENTION or OFF, if supported.  Returns -EINVAL if the
- * powerdomain pointer is null or the target power state is not not
- * supported, or returns 0 upon success.
+ * Set the next power state @pwrst that the logic portion of the
+ * powerdomain @pwrdm will enter when the powerdomain enters retention.
+ * This will be either RETENTION or OFF, if supported.  Returns
+ * -EINVAL if the powerdomain pointer is null or the target power
+ * state is not not supported, or returns 0 upon success.
  */
 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 {
@@ -796,7 +503,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
          */
         prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE,
                              (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)),
-                             pwrdm->prcm_offs, PM_PWSTCTRL);
+                                 pwrdm->prcm_offs, pwrstctrl_reg_offs);
 
         return 0;
 }
@@ -807,13 +514,14 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
  * @bank: memory bank number to set (0-3)
  * @pwrst: one of the PWRDM_POWER_* macros
  *
- * Set the next power state that memory bank x of the powerdomain
- * pwrdm will enter when the powerdomain enters the ON state.  Bank
- * will be a number from 0 to 3, and represents different types of
- * memory, depending on the powerdomain.  Returns -EINVAL if the
- * powerdomain pointer is null or the target power state is not not
- * supported for this memory bank, -EEXIST if the target memory bank
- * does not exist or is not controllable, or returns 0 upon success.
+ * Set the next power state @pwrst that memory bank @bank of the
+ * powerdomain @pwrdm will enter when the powerdomain enters the ON
+ * state.  @bank will be a number from 0 to 3, and represents different
+ * types of memory, depending on the powerdomain.  Returns -EINVAL if
+ * the powerdomain pointer is null or the target power state is not
+ * not supported for this memory bank, -EEXIST if the target memory
+ * bank does not exist or is not controllable, or returns 0 upon
+ * success.
  */
 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 {
@@ -839,16 +547,19 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
          */
         switch (bank) {
         case 0:
-                m = OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK;
+                m = OMAP_MEM0_ONSTATE_MASK;
                 break;
         case 1:
-                m = OMAP3430_L1FLATMEMONSTATE_MASK;
+                m = OMAP_MEM1_ONSTATE_MASK;
                 break;
         case 2:
-                m = OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK;
+                m = OMAP_MEM2_ONSTATE_MASK;
                 break;
         case 3:
-                m = OMAP3430_L2FLATMEMONSTATE_MASK;
+                m = OMAP_MEM3_ONSTATE_MASK;
+                break;
+        case 4:
+                m = OMAP_MEM4_ONSTATE_MASK;
                 break;
         default:
                 WARN_ON(1); /* should never happen */
@@ -856,7 +567,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
         }
 
         prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),
-                             pwrdm->prcm_offs, PM_PWSTCTRL);
+                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
 
         return 0;
 }
@@ -867,14 +578,15 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
  * @bank: memory bank number to set (0-3)
  * @pwrst: one of the PWRDM_POWER_* macros
  *
- * Set the next power state that memory bank x of the powerdomain
- * pwrdm will enter when the powerdomain enters the RETENTION state.
- * Bank will be a number from 0 to 3, and represents different types
- * of memory, depending on the powerdomain.  pwrst will be either
- * RETENTION or OFF, if supported. Returns -EINVAL if the powerdomain
- * pointer is null or the target power state is not not supported for
- * this memory bank, -EEXIST if the target memory bank does not exist
- * or is not controllable, or returns 0 upon success.
+ * Set the next power state @pwrst that memory bank @bank of the
+ * powerdomain @pwrdm will enter when the powerdomain enters the
+ * RETENTION state.  Bank will be a number from 0 to 3, and represents
+ * different types of memory, depending on the powerdomain.  @pwrst
+ * will be either RETENTION or OFF, if supported.  Returns -EINVAL if
+ * the powerdomain pointer is null or the target power state is not
+ * not supported for this memory bank, -EEXIST if the target memory
+ * bank does not exist or is not controllable, or returns 0 upon
+ * success.
  */
 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 {
@@ -900,16 +612,19 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
          */
         switch (bank) {
         case 0:
-                m = OMAP3430_SHAREDL1CACHEFLATRETSTATE;
+                m = OMAP_MEM0_RETSTATE_MASK;
                 break;
         case 1:
-                m = OMAP3430_L1FLATMEMRETSTATE;
+                m = OMAP_MEM1_RETSTATE_MASK;
                 break;
         case 2:
-                m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
+                m = OMAP_MEM2_RETSTATE_MASK;
                 break;
         case 3:
-                m = OMAP3430_L2FLATMEMRETSTATE;
+                m = OMAP_MEM3_RETSTATE_MASK;
+                break;
+        case 4:
+                m = OMAP_MEM4_RETSTATE_MASK;
                 break;
         default:
                 WARN_ON(1); /* should never happen */
@@ -917,7 +632,7 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
         }
 
         prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
-                             PM_PWSTCTRL);
+                             pwrstctrl_reg_offs);
 
         return 0;
 }
@@ -926,27 +641,27 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
  * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state
  * @pwrdm: struct powerdomain * to get current logic retention power state
  *
- * Return the current power state that the logic portion of
- * powerdomain pwrdm will enter
- * Returns -EINVAL if the powerdomain pointer is null or returns the
- * current logic retention power state upon success.
+ * Return the power state that the logic portion of powerdomain @pwrdm
+ * will enter when the powerdomain enters retention.  Returns -EINVAL
+ * if the powerdomain pointer is null or returns the logic retention
+ * power state upon success.
  */
 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 {
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
-                                        OMAP3430_LOGICSTATEST);
+        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                 pwrstst_reg_offs, OMAP3430_LOGICSTATEST);
 }
 
 /**
  * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state
  * @pwrdm: struct powerdomain * to get previous logic power state
  *
- * Return the powerdomain pwrdm's logic power state.  Returns -EINVAL
- * if the powerdomain pointer is null or returns the previous logic
- * power state upon success.
+ * Return the powerdomain @pwrdm's previous logic power state.  Returns
+ * -EINVAL if the powerdomain pointer is null or returns the previous
+ * logic power state upon success.
  */
 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 {
@@ -968,8 +683,8 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
  * @pwrdm: struct powerdomain * to get current memory bank power state
  * @bank: memory bank number (0-3)
  *
- * Return the powerdomain pwrdm's current memory power state for bank
- * x.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
+ * Return the powerdomain @pwrdm's current memory power state for bank
+ * @bank.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
  * the target memory bank does not exist or is not controllable, or
  * returns the current memory power state upon success.
  */
@@ -994,23 +709,27 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
          */
         switch (bank) {
         case 0:
-                m = OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK;
+                m = OMAP_MEM0_STATEST_MASK;
                 break;
         case 1:
-                m = OMAP3430_L1FLATMEMSTATEST_MASK;
+                m = OMAP_MEM1_STATEST_MASK;
                 break;
         case 2:
-                m = OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK;
+                m = OMAP_MEM2_STATEST_MASK;
                 break;
         case 3:
-                m = OMAP3430_L2FLATMEMSTATEST_MASK;
+                m = OMAP_MEM3_STATEST_MASK;
+                break;
+        case 4:
+                m = OMAP_MEM4_STATEST_MASK;
                 break;
         default:
                 WARN_ON(1); /* should never happen */
                 return -EEXIST;
         }
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m);
+        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                         pwrstst_reg_offs, m);
 }
 
 /**
@@ -1018,10 +737,11 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
  * @pwrdm: struct powerdomain * to get previous memory bank power state
  * @bank: memory bank number (0-3)
  *
- * Return the powerdomain pwrdm's previous memory power state for bank
- * x.  Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
- * the target memory bank does not exist or is not controllable, or
- * returns the previous memory power state upon success.
+ * Return the powerdomain @pwrdm's previous memory power state for
+ * bank @bank.  Returns -EINVAL if the powerdomain pointer is null,
+ * -EEXIST if the target memory bank does not exist or is not
+ * controllable, or returns the previous memory power state upon
+ * success.
  */
 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
@@ -1068,10 +788,10 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
  * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
  * @pwrdm: struct powerdomain * to clear
  *
- * Clear the powerdomain's previous power state register.  Clears the
- * entire register, including logic and memory bank previous power states.
- * Returns -EINVAL if the powerdomain pointer is null, or returns 0 upon
- * success.
+ * Clear the powerdomain's previous power state register @pwrdm.
+ * Clears the entire register, including logic and memory bank
+ * previous power states.  Returns -EINVAL if the powerdomain pointer
+ * is null, or returns 0 upon success.
  */
 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 {
@@ -1096,11 +816,11 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
  * @pwrdm: struct powerdomain *
  *
  * Enable automatic context save-and-restore upon power state change
- * for some devices in a powerdomain.  Warning: this only affects a
- * subset of devices in a powerdomain; check the TRM closely.  Returns
- * -EINVAL if the powerdomain pointer is null or if the powerdomain
- * does not support automatic save-and-restore, or returns 0 upon
- * success.
+ * for some devices in the powerdomain @pwrdm.  Warning: this only
+ * affects a subset of devices in a powerdomain; check the TRM
+ * closely.  Returns -EINVAL if the powerdomain pointer is null or if
+ * the powerdomain does not support automatic save-and-restore, or
+ * returns 0 upon success.
  */
 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
 {
@@ -1114,7 +834,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
                  pwrdm->name);
 
         prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-                             pwrdm->prcm_offs, PM_PWSTCTRL);
+                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
 
         return 0;
 }
@@ -1124,11 +844,11 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
  * @pwrdm: struct powerdomain *
  *
  * Disable automatic context save-and-restore upon power state change
- * for some devices in a powerdomain.  Warning: this only affects a
- * subset of devices in a powerdomain; check the TRM closely.  Returns
- * -EINVAL if the powerdomain pointer is null or if the powerdomain
- * does not support automatic save-and-restore, or returns 0 upon
- * success.
+ * for some devices in the powerdomain @pwrdm.  Warning: this only
+ * affects a subset of devices in a powerdomain; check the TRM
+ * closely.  Returns -EINVAL if the powerdomain pointer is null or if
+ * the powerdomain does not support automatic save-and-restore, or
+ * returns 0 upon success.
  */
 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 {
@@ -1142,7 +862,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
                  pwrdm->name);
 
         prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
-                             pwrdm->prcm_offs, PM_PWSTCTRL);
+                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
 
         return 0;
 }
@@ -1151,7 +871,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
  * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
  * @pwrdm: struct powerdomain *
  *
- * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore
+ * Returns 1 if powerdomain @pwrdm supports hardware save-and-restore
  * for some devices, or 0 if it does not.
  */
 bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
@@ -1163,7 +883,7 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
  * pwrdm_wait_transition - wait for powerdomain power transition to finish
  * @pwrdm: struct powerdomain * to wait for
  *
- * If the powerdomain pwrdm is in the process of a state transition,
+ * If the powerdomain @pwrdm is in the process of a state transition,
  * spin until it completes the power transition, or until an iteration
  * bailout value is reached. Returns -EINVAL if the powerdomain
  * pointer is null, -EAGAIN if the bailout value was reached, or
@@ -1183,10 +903,10 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
          */
 
         /* XXX Is this udelay() value meaningful? */
-        while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) &
+        while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) &
                 OMAP_INTRANSITION) &&
                (c++ < PWRDM_TRANSITION_BAILOUT))
-                udelay(1);
+                        udelay(1);
 
         if (c > PWRDM_TRANSITION_BAILOUT) {
                 printk(KERN_ERR "powerdomain: waited too long for "
@@ -1213,12 +933,6 @@ int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
 
         return -EINVAL;
 }
-int pwrdm_clk_state_switch(struct clk *clk)
-{
-        if (clk != NULL && clk->clkdm != NULL)
-                return pwrdm_clkdm_state_switch(clk->clkdm);
-        return -EINVAL;
-}
 
 int pwrdm_pre_transition(void)
 {
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 057b2e3e2c35..105cbcaefd3b 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -1,8 +1,8 @@
 /*
  * OMAP2/3 common powerdomain definitions
  *
- * Copyright (C) 2007-8 Texas Instruments, Inc.
- * Copyright (C) 2007-8 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  * Debugging and integration fixes by Jouni Högander
@@ -12,26 +12,21 @@
  * published by the Free Software Foundation.
  */
 
+/*
+ * To Do List
+ * -> Move the Sleep/Wakeup dependencies from Power Domain framework to
+ *    Clock Domain Framework
+ */
+
 #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
 #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
 
 /*
  * This file contains all of the powerdomains that have some element
- * of software control for the OMAP24xx and OMAP34XX chips.
- *
- * A few notes:
+ * of software control for the OMAP24xx and OMAP34xx chips.
  *
  * This is not an exhaustive listing of powerdomains on the chips; only
  * powerdomains that can be controlled in software.
- *
- * A useful validation rule for struct powerdomain:
- * Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array
- * must have a dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really
- * just software-controllable dependencies.  Non-software-controllable
- * dependencies do exist, but they are not encoded below (yet).
- *
- * 24xx does not support programmable sleep dependencies (SLEEPDEP)
- *
  */
 
 /*
@@ -41,26 +36,17 @@
  *
  * On the 2420, this is a 'C55 DSP called, simply, the DSP.  Its
  * powerdomain is called the "DSP power domain."  On the 2430, the
- * on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1.  Its
- * powerdomain is still called the "DSP power domain."  On the 3430,
- * the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but
- * its powerdomain is now called the "IVA2 power domain."
+ * on-board DSP is a 'C64 DSP, now called (along with its hardware
+ * accelerators) the IVA2 or IVA2.1.  Its powerdomain is still called
+ * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the
+ * 2430, also known as the IVA2; but its powerdomain is now called the
+ * "IVA2 power domain."
  *
  * The 2420 also has something called the IVA, which is a separate ARM
  * core, and has nothing to do with the DSP/IVA2.
  *
  * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
  * address offset is different between the C55 and C64 DSPs.
- *
- * The overly-specific dep_bit names are due to a bit name collision
- * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
- * value are the same for all powerdomains: 2
- */
-
-/*
- * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
- * sanity check?
- * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
  */
 
 #include <plat/powerdomain.h>
@@ -68,69 +54,23 @@
 #include "prcm-common.h"
 #include "prm.h"
 #include "cm.h"
-
-/* OMAP2/3-common powerdomains and wakeup dependencies */
-
-/*
- * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
- * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
- * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
- */
-static struct pwrdm_dep gfx_sgx_wkdeps[] = {
-        {
-                .pwrdm_name = "core_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "iva2_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                            CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "wkup_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
-                                            CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/*
- * 3430: CM_SLEEPDEP_CAM: MPU
- * 3430ES1: CM_SLEEPDEP_GFX: MPU
- * 3430ES2: CM_SLEEPDEP_SGX: MPU
- */
-static struct pwrdm_dep cam_gfx_sleepdeps[] = {
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-
 #include "powerdomains24xx.h"
 #include "powerdomains34xx.h"
+#include "powerdomains44xx.h"
 
+/* OMAP2/3-common powerdomains */
 
-/*
- * OMAP2/3 common powerdomains
- */
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 
 /*
  * The GFX powerdomain is not present on 3430ES2, but currently we do not
  * have a macro to filter it out at compile-time.
  */
-static struct powerdomain gfx_pwrdm = {
+static struct powerdomain gfx_omap2_pwrdm = {
         .name             = "gfx_pwrdm",
         .prcm_offs        = GFX_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
                                            CHIP_IS_OMAP3430ES1),
-        .wkdep_srcs       = gfx_sgx_wkdeps,
-        .sleepdep_srcs    = cam_gfx_sleepdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
         .banks            = 1,
@@ -142,22 +82,24 @@ static struct powerdomain gfx_pwrdm = {
         },
 };
 
-static struct powerdomain wkup_pwrdm = {
+static struct powerdomain wkup_omap2_pwrdm = {
         .name           = "wkup_pwrdm",
         .prcm_offs      = WKUP_MOD,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
-        .dep_bit        = OMAP_EN_WKUP_SHIFT,
 };
 
+#endif
 
 
 /* As powerdomains are added or removed above, this list must also be changed */
 static struct powerdomain *powerdomains_omap[] __initdata = {
 
-        &gfx_pwrdm,
-        &wkup_pwrdm,
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+        &wkup_omap2_pwrdm,
+        &gfx_omap2_pwrdm,
+#endif
 
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
         &dsp_pwrdm,
         &mpu_24xx_pwrdm,
         &core_24xx_pwrdm,
@@ -167,12 +109,12 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
         &mdm_pwrdm,
 #endif
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
         &iva2_pwrdm,
-        &mpu_34xx_pwrdm,
+        &mpu_3xxx_pwrdm,
         &neon_pwrdm,
-        &core_34xx_pre_es3_1_pwrdm,
-        &core_34xx_es3_1_pwrdm,
+        &core_3xxx_pre_es3_1_pwrdm,
+        &core_3xxx_es3_1_pwrdm,
         &cam_pwrdm,
         &dss_pwrdm,
         &per_pwrdm,
@@ -186,6 +128,24 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
         &dpll5_pwrdm,
 #endif
 
+#ifdef CONFIG_ARCH_OMAP4
+        &core_44xx_pwrdm,
+        &gfx_44xx_pwrdm,
+        &abe_44xx_pwrdm,
+        &dss_44xx_pwrdm,
+        &tesla_44xx_pwrdm,
+        &wkup_44xx_pwrdm,
+        &cpu0_44xx_pwrdm,
+        &cpu1_44xx_pwrdm,
+        &emu_44xx_pwrdm,
+        &mpu_44xx_pwrdm,
+        &ivahd_44xx_pwrdm,
+        &cam_44xx_pwrdm,
+        &l3init_44xx_pwrdm,
+        &l4per_44xx_pwrdm,
+        &always_on_core_44xx_pwrdm,
+        &cefuse_44xx_pwrdm,
+#endif
         NULL
 };
 
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h
index bd249a495aa9..652a01b729e9 100644
--- a/arch/arm/mach-omap2/powerdomains24xx.h
+++ b/arch/arm/mach-omap2/powerdomains24xx.h
@@ -2,7 +2,7 @@
  * OMAP24XX powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  * Debugging and integration fixes by Jouni Högander
@@ -32,90 +32,12 @@
 
 #ifdef CONFIG_ARCH_OMAP24XX
 
-
-/* Wakeup dependency source arrays */
-
-/*
- * 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP
- * 2430 PM_WKDEP_MDM: same as above
- */
-static struct pwrdm_dep dsp_mdm_24xx_wkdeps[] = {
-        {
-                .pwrdm_name = "core_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "wkup_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        { NULL },
-};
-
-/*
- * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
- * 2430 adds MDM
- */
-static struct pwrdm_dep mpu_24xx_wkdeps[] = {
-        {
-                .pwrdm_name = "core_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "dsp_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "wkup_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "mdm_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
-        },
-        { NULL },
-};
-
-/*
- * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
- * 2430 adds MDM
- */
-static struct pwrdm_dep core_24xx_wkdeps[] = {
-        {
-                .pwrdm_name = "dsp_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "gfx_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "wkup_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
-        },
-        {
-                .pwrdm_name = "mdm_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
-        },
-        { NULL },
-};
-
-
 /* Powerdomains */
 
 static struct powerdomain dsp_pwrdm = {
         .name             = "dsp_pwrdm",
         .prcm_offs        = OMAP24XX_DSP_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
-        .dep_bit          = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
-        .wkdep_srcs       = dsp_mdm_24xx_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
         .banks            = 1,
@@ -131,8 +53,6 @@ static struct powerdomain mpu_24xx_pwrdm = {
         .name             = "mpu_pwrdm",
         .prcm_offs        = MPU_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
-        .dep_bit          = OMAP24XX_EN_MPU_SHIFT,
-        .wkdep_srcs       = mpu_24xx_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
@@ -148,9 +68,7 @@ static struct powerdomain core_24xx_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = CORE_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
-        .wkdep_srcs       = core_24xx_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .dep_bit          = OMAP24XX_EN_CORE_SHIFT,
         .banks            = 3,
         .pwrsts_mem_ret   = {
                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
@@ -176,13 +94,10 @@ static struct powerdomain core_24xx_pwrdm = {
 
 /* XXX 2430 KILLDOMAINWKUP bit?  No current users apparently */
 
-/* Another case of bit name collisions between several registers: EN_MDM */
 static struct powerdomain mdm_pwrdm = {
         .name             = "mdm_pwrdm",
         .prcm_offs        = OMAP2430_MDM_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
-        .dep_bit          = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
-        .wkdep_srcs       = dsp_mdm_24xx_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
         .banks            = 1,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 588f7e07d0ea..186c0132466b 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -1,8 +1,8 @@
 /*
- * OMAP34XX powerdomain definitions
+ * OMAP3 powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2010 Nokia Corporation
  *
  * Written by Paul Walmsley
  * Debugging and integration fixes by Jouni Högander
@@ -32,128 +32,7 @@
  * 34XX-specific powerdomains, dependencies
  */
 
-#ifdef CONFIG_ARCH_OMAP34XX
-
-/*
- * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
- * (USBHOST is ES2 only)
- */
-static struct pwrdm_dep per_usbhost_wkdeps[] = {
-        {
-                .pwrdm_name = "core_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "iva2_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "wkup_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/*
- * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
- */
-static struct pwrdm_dep mpu_34xx_wkdeps[] = {
-        {
-                .pwrdm_name = "core_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "iva2_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "dss_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "per_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/*
- * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
- */
-static struct pwrdm_dep iva2_wkdeps[] = {
-        {
-                .pwrdm_name = "core_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "wkup_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "dss_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "per_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-
-/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
-static struct pwrdm_dep cam_dss_wkdeps[] = {
-        {
-                .pwrdm_name = "iva2_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "wkup_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-/* 3430: PM_WKDEP_NEON: MPU */
-static struct pwrdm_dep neon_wkdeps[] = {
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
-
-/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
-
-/*
- * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
- * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
- */
-static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
-        {
-                .pwrdm_name = "mpu_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        {
-                .pwrdm_name = "iva2_pwrdm",
-                .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
-        },
-        { NULL },
-};
-
+#ifdef CONFIG_ARCH_OMAP3
 
 /*
  * Powerdomains
@@ -163,8 +42,6 @@ static struct powerdomain iva2_pwrdm = {
         .name             = "iva2_pwrdm",
         .prcm_offs        = OMAP3430_IVA2_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-        .dep_bit          = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
-        .wkdep_srcs       = iva2_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 4,
@@ -182,12 +59,10 @@ static struct powerdomain iva2_pwrdm = {
         },
 };
 
-static struct powerdomain mpu_34xx_pwrdm = {
+static struct powerdomain mpu_3xxx_pwrdm = {
         .name             = "mpu_pwrdm",
         .prcm_offs        = MPU_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-        .dep_bit          = OMAP3430_EN_MPU_SHIFT,
-        .wkdep_srcs       = mpu_34xx_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .flags            = PWRDM_HAS_MPU_QUIRK,
@@ -200,15 +75,13 @@ static struct powerdomain mpu_34xx_pwrdm = {
         },
 };
 
-/* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
+static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = CORE_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
                                            CHIP_IS_OMAP3430ES2 |
                                            CHIP_IS_OMAP3430ES3_0),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .dep_bit          = OMAP3430_EN_CORE_SHIFT,
         .banks            = 2,
         .pwrsts_mem_ret   = {
                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
@@ -220,13 +93,11 @@ static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
         },
 };
 
-/* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_es3_1_pwrdm = {
+static struct powerdomain core_3xxx_es3_1_pwrdm = {
         .name             = "core_pwrdm",
         .prcm_offs        = CORE_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .dep_bit          = OMAP3430_EN_CORE_SHIFT,
         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
         .banks            = 2,
         .pwrsts_mem_ret   = {
@@ -239,14 +110,10 @@ static struct powerdomain core_34xx_es3_1_pwrdm = {
         },
 };
 
-/* Another case of bit name collisions between several registers: EN_DSS */
 static struct powerdomain dss_pwrdm = {
         .name             = "dss_pwrdm",
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .prcm_offs        = OMAP3430_DSS_MOD,
-        .dep_bit          = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
-        .wkdep_srcs       = cam_dss_wkdeps,
-        .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
         .banks            = 1,
@@ -267,8 +134,6 @@ static struct powerdomain sgx_pwrdm = {
         .name             = "sgx_pwrdm",
         .prcm_offs        = OMAP3430ES2_SGX_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-        .wkdep_srcs       = gfx_sgx_wkdeps,
-        .sleepdep_srcs    = cam_gfx_sleepdeps,
         /* XXX This is accurate for 3430 SGX, but what about GFX? */
         .pwrsts           = PWRSTS_OFF_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
@@ -285,8 +150,6 @@ static struct powerdomain cam_pwrdm = {
         .name             = "cam_pwrdm",
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .prcm_offs        = OMAP3430_CAM_MOD,
-        .wkdep_srcs       = cam_dss_wkdeps,
-        .sleepdep_srcs    = cam_gfx_sleepdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
         .banks            = 1,
@@ -302,9 +165,6 @@ static struct powerdomain per_pwrdm = {
         .name             = "per_pwrdm",
         .prcm_offs        = OMAP3430_PER_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-        .dep_bit          = OMAP3430_EN_PER_SHIFT,
-        .wkdep_srcs       = per_usbhost_wkdeps,
-        .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
@@ -326,7 +186,6 @@ static struct powerdomain neon_pwrdm = {
         .name             = "neon_pwrdm",
         .prcm_offs        = OMAP3430_NEON_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-        .wkdep_srcs       = neon_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
 };
@@ -335,8 +194,6 @@ static struct powerdomain usbhost_pwrdm = {
         .name             = "usbhost_pwrdm",
         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
-        .wkdep_srcs       = per_usbhost_wkdeps,
-        .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_RET,
         /*
@@ -386,7 +243,7 @@ static struct powerdomain dpll5_pwrdm = {
 };
 
 
-#endif    /* CONFIG_ARCH_OMAP34XX */
+#endif    /* CONFIG_ARCH_OMAP3 */
 
 
 #endif
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
new file mode 100644
index 000000000000..c1015147d579
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -0,0 +1,310 @@
+/*
+ * OMAP4 Power domains framework
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
+#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
+
+#include <plat/powerdomain.h>
+
+#include "prcm-common.h"
+#include "cm.h"
+#include "cm-regbits-44xx.h"
+#include "prm.h"
+#include "prm-regbits-44xx.h"
+
+#if defined(CONFIG_ARCH_OMAP4)
+
+/* core_44xx_pwrdm: CORE power domain */
+static struct powerdomain core_44xx_pwrdm = {
+        .name             = "core_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_CORE_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 5,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRDM_POWER_RET,  /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ducati_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ducati_unicache */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRDM_POWER_ON,   /* core_other_bank */
+                [3] = PWRDM_POWER_ON,   /* ducati_l2ram */
+                [4] = PWRDM_POWER_ON,   /* ducati_unicache */
+        },
+};
+
+/* gfx_44xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gfx_44xx_pwrdm = {
+        .name             = "gfx_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_GFX_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* gfx_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* gfx_mem */
+        },
+};
+
+/* abe_44xx_pwrdm: Audio back end power domain */
+static struct powerdomain abe_44xx_pwrdm = {
+        .name             = "abe_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_ABE_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRDM_POWER_OFF,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_RET,  /* aessmem */
+                [1] = PWRDM_POWER_OFF,  /* periphmem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* aessmem */
+                [1] = PWRDM_POWER_ON,   /* periphmem */
+        },
+};
+
+/* dss_44xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_44xx_pwrdm = {
+        .name             = "dss_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_DSS_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* dss_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* dss_mem */
+        },
+};
+
+/* tesla_44xx_pwrdm: Tesla processor power domain */
+static struct powerdomain tesla_44xx_pwrdm = {
+        .name             = "tesla_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_TESLA_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_RET,  /* tesla_edma */
+                [1] = PWRSTS_OFF_RET,   /* tesla_l1 */
+                [2] = PWRSTS_OFF_RET,   /* tesla_l2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* tesla_edma */
+                [1] = PWRDM_POWER_ON,   /* tesla_l1 */
+                [2] = PWRDM_POWER_ON,   /* tesla_l2 */
+        },
+};
+
+/* wkup_44xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkup_44xx_pwrdm = {
+        .name             = "wkup_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_WKUP_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRDM_POWER_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* wkup_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* wkup_bank */
+        },
+};
+
+/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_44xx_pwrdm = {
+        .name             = "cpu0_pwrdm",
+        .prcm_offs        = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* cpu0_l1 */
+        },
+};
+
+/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_44xx_pwrdm = {
+        .name             = "cpu1_pwrdm",
+        .prcm_offs        = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* cpu1_l1 */
+        },
+};
+
+/* emu_44xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_44xx_pwrdm = {
+        .name             = "emu_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_EMU_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* emu_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* emu_bank */
+        },
+};
+
+/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_44xx_pwrdm = {
+        .name             = "mpu_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_MPU_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l1 */
+                [1] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [2] = PWRDM_POWER_RET,  /* mpu_ram */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* mpu_l1 */
+                [1] = PWRDM_POWER_ON,   /* mpu_l2 */
+                [2] = PWRDM_POWER_ON,   /* mpu_ram */
+        },
+};
+
+/* ivahd_44xx_pwrdm: IVA-HD power domain */
+static struct powerdomain ivahd_44xx_pwrdm = {
+        .name             = "ivahd_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_IVAHD_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRDM_POWER_OFF,
+        .banks            = 4,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* hwa_mem */
+                [1] = PWRDM_POWER_ON,   /* sl2_mem */
+                [2] = PWRDM_POWER_ON,   /* tcm1_mem */
+                [3] = PWRDM_POWER_ON,   /* tcm2_mem */
+        },
+};
+
+/* cam_44xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_44xx_pwrdm = {
+        .name             = "cam_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_CAM_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* cam_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* cam_mem */
+        },
+};
+
+/* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
+static struct powerdomain l3init_44xx_pwrdm = {
+        .name             = "l3init_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_L3INIT_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* l3init_bank1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* l3init_bank1 */
+        },
+};
+
+/* l4per_44xx_pwrdm: Target peripherals power domain */
+static struct powerdomain l4per_44xx_pwrdm = {
+        .name             = "l4per_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_L4PER_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRDM_POWER_OFF,  /* nonretained_bank */
+                [1] = PWRDM_POWER_RET,  /* retained_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRDM_POWER_ON,   /* nonretained_bank */
+                [1] = PWRDM_POWER_ON,   /* retained_bank */
+        },
+};
+
+/*
+ * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
+ * domain
+ */
+static struct powerdomain always_on_core_44xx_pwrdm = {
+        .name             = "always_on_core_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRDM_POWER_ON,
+};
+
+/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain cefuse_44xx_pwrdm = {
+        .name             = "cefuse_pwrdm",
+        .prcm_offs        = OMAP4430_PRM_CEFUSE_MOD,
+        .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+        .pwrsts           = PWRSTS_OFF_ON,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * always_on_iva
+ * always_on_mpu
+ * stdefuse
+ */
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 61ac2a418bd0..90f603d434c6 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -119,6 +119,15 @@
 #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD             0x0400
 #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD             0x0800
 
+/* Base Addresses for the OMAP4 */
+
+#define OMAP4430_CM1_BASE               0x4a004000
+#define OMAP4430_CM2_BASE               0x4a008000
+#define OMAP4430_PRM_BASE               0x4a306000
+#define OMAP4430_SCRM_BASE              0x4a30a000
+#define OMAP4430_CHIRONSS_BASE          0x48243000
+
+
 /* 24XX register bits shared between CM & PRM registers */
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index cf466ea1dffc..e8e121a41d6d 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -11,6 +11,7 @@
  * Rajendra Nayak <rnayak@ti.com>
  *
  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
+ * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -28,6 +29,7 @@
 #include <plat/control.h>
 
 #include "clock.h"
+#include "clock2xxx.h"
 #include "cm.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
@@ -121,7 +123,10 @@ struct omap3_prcm_regs prcm_context;
 u32 omap_prcm_get_reset_sources(void)
 {
         /* XXX This presumably needs modification for 34XX */
-        return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
+        if (cpu_is_omap24xx() | cpu_is_omap34xx())
+                return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
+        if (cpu_is_omap44xx())
+                return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 
@@ -129,11 +134,12 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 void omap_prcm_arch_reset(char mode)
 {
         s16 prcm_offs;
-        omap2_clk_prepare_for_reboot();
 
-        if (cpu_is_omap24xx())
+        if (cpu_is_omap24xx()) {
+                omap2xxx_clk_prepare_for_reboot();
+
                 prcm_offs = WKUP_MOD;
-        else if (cpu_is_omap34xx()) {
+        } else if (cpu_is_omap34xx()) {
                 u32 l;
 
                 prcm_offs = OMAP3430_GR_MOD;
@@ -144,10 +150,17 @@ void omap_prcm_arch_reset(char mode)
                  * cf. OMAP34xx TRM, Initialization / Software Booting
                  * Configuration. */
                 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
-        } else
+        } else if (cpu_is_omap44xx())
+                prcm_offs = OMAP4430_PRM_DEVICE_MOD;
+        else
                 WARN_ON(1);
 
-        prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
+        if (cpu_is_omap24xx() | cpu_is_omap34xx())
+                prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
+                                                 OMAP2_RM_RSTCTRL);
+        if (cpu_is_omap44xx())
+                prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
+                                                 OMAP4_RM_RSTCTRL);
 }
 
 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
@@ -188,6 +201,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
         return v;
 }
 
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+        u32 v;
+
+        v = prm_read_mod_reg(domain, idx);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
@@ -280,7 +305,7 @@ void omap3_prcm_save_context(void)
         prcm_context.emu_cm_clksel =
                          cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
         prcm_context.emu_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
         prcm_context.pll_cm_autoidle2 =
                          cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
         prcm_context.pll_cm_clksel4 =
@@ -333,23 +358,25 @@ void omap3_prcm_save_context(void)
         prcm_context.mpu_cm_autoidle2 =
                          cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
         prcm_context.iva2_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
         prcm_context.mpu_cm_clkstctrl =
-                         cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
         prcm_context.core_cm_clkstctrl =
-                         cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
         prcm_context.sgx_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+                                                OMAP2_CM_CLKSTCTRL);
         prcm_context.dss_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
         prcm_context.cam_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
         prcm_context.per_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
         prcm_context.neon_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
         prcm_context.usbhost_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
+                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                                OMAP2_CM_CLKSTCTRL);
         prcm_context.core_cm_autoidle1 =
                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
         prcm_context.core_cm_autoidle2 =
@@ -432,7 +459,7 @@ void omap3_prcm_restore_context(void)
         cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
                                          CM_CLKSEL1);
         cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
-                                         CM_CLKSTCTRL);
+                                         OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
                                          CM_AUTOIDLE2);
         cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
@@ -478,22 +505,23 @@ void omap3_prcm_restore_context(void)
                                         CM_AUTOIDLE2);
         cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
         cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
-                                        CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
+                                        OMAP2_CM_CLKSTCTRL);
+        cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
+                                        OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
-                                        CM_CLKSTCTRL);
+                                        OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
-                                        CM_CLKSTCTRL);
+                                        OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
-                                        CM_CLKSTCTRL);
+                                        OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
-                                        CM_CLKSTCTRL);
+                                        OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
-                                        CM_CLKSTCTRL);
+                                        OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
-                                        CM_CLKSTCTRL);
+                                        OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
-                                        OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
+                                OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
         cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
                                         CM_AUTOIDLE1);
         cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 301c810fb269..597be4a2b9ff 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -29,412 +29,412 @@
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT                                (1 << 1)
+#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT                                1
 #define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 BITFIELD(1, 1)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT                              (1 << 2)
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT                              2
 #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               BITFIELD(2, 2)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_ABB_IVA_DONE_EN_SHIFT                                  (1 << 31)
+#define OMAP4430_ABB_IVA_DONE_EN_SHIFT                                  31
 #define OMAP4430_ABB_IVA_DONE_EN_MASK                                   BITFIELD(31, 31)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_ABB_IVA_DONE_ST_SHIFT                                  (1 << 31)
+#define OMAP4430_ABB_IVA_DONE_ST_SHIFT                                  31
 #define OMAP4430_ABB_IVA_DONE_ST_MASK                                   BITFIELD(31, 31)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_ABB_MPU_DONE_EN_SHIFT                                  (1 << 7)
+#define OMAP4430_ABB_MPU_DONE_EN_SHIFT                                  7
 #define OMAP4430_ABB_MPU_DONE_EN_MASK                                   BITFIELD(7, 7)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_ABB_MPU_DONE_ST_SHIFT                                  (1 << 7)
+#define OMAP4430_ABB_MPU_DONE_ST_SHIFT                                  7
 #define OMAP4430_ABB_MPU_DONE_ST_MASK                                   BITFIELD(7, 7)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_ACTIVE_FBB_SEL_SHIFT                                   (1 << 2)
+#define OMAP4430_ACTIVE_FBB_SEL_SHIFT                                   2
 #define OMAP4430_ACTIVE_FBB_SEL_MASK                                    BITFIELD(2, 2)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_ACTIVE_RBB_SEL_SHIFT                                   (1 << 1)
+#define OMAP4430_ACTIVE_RBB_SEL_SHIFT                                   1
 #define OMAP4430_ACTIVE_RBB_SEL_MASK                                    BITFIELD(1, 1)
 
 /* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_AESSMEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_AESSMEM_ONSTATE_SHIFT                                  16
 #define OMAP4430_AESSMEM_ONSTATE_MASK                                   BITFIELD(16, 17)
 
 /* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_AESSMEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_AESSMEM_RETSTATE_SHIFT                                 8
 #define OMAP4430_AESSMEM_RETSTATE_MASK                                  BITFIELD(8, 8)
 
 /* Used by PM_ABE_PWRSTST */
-#define OMAP4430_AESSMEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_AESSMEM_STATEST_SHIFT                                  4
 #define OMAP4430_AESSMEM_STATEST_MASK                                   BITFIELD(4, 5)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_AIPOFF_SHIFT                                           (1 << 8)
+#define OMAP4430_AIPOFF_SHIFT                                           8
 #define OMAP4430_AIPOFF_MASK                                            BITFIELD(8, 8)
 
 /* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT                             (1 << 0)
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT                             0
 #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              BITFIELD(0, 1)
 
 /* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT                              (1 << 4)
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT                              4
 #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               BITFIELD(4, 5)
 
 /* Used by PRM_VOLTCTRL */
-#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT                              (1 << 2)
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT                              2
 #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               BITFIELD(2, 3)
 
 /* Used by PM_CAM_PWRSTCTRL */
-#define OMAP4430_CAM_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_CAM_MEM_ONSTATE_SHIFT                                  16
 #define OMAP4430_CAM_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
 
 /* Used by PM_CAM_PWRSTST */
-#define OMAP4430_CAM_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_CAM_MEM_STATEST_SHIFT                                  4
 #define OMAP4430_CAM_MEM_STATEST_MASK                                   BITFIELD(4, 5)
 
 /* Used by PRM_CLKREQCTRL */
-#define OMAP4430_CLKREQ_COND_SHIFT                                      (1 << 0)
+#define OMAP4430_CLKREQ_COND_SHIFT                                      0
 #define OMAP4430_CLKREQ_COND_MASK                                       BITFIELD(0, 2)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT                                 (1 << 0)
+#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT                                 0
 #define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT                                  (1 << 8)
+#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT                                  8
 #define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
-#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT                                  (1 << 16)
+#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT                                  16
 #define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_CORE_L_SHIFT                                   (1 << 4)
+#define OMAP4430_CMD_VDD_CORE_L_SHIFT                                   4
 #define OMAP4430_CMD_VDD_CORE_L_MASK                                    BITFIELD(4, 4)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_IVA_L_SHIFT                                    (1 << 12)
+#define OMAP4430_CMD_VDD_IVA_L_SHIFT                                    12
 #define OMAP4430_CMD_VDD_IVA_L_MASK                                     BITFIELD(12, 12)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_CMD_VDD_MPU_L_SHIFT                                    (1 << 17)
+#define OMAP4430_CMD_VDD_MPU_L_SHIFT                                    17
 #define OMAP4430_CMD_VDD_MPU_L_MASK                                     BITFIELD(17, 17)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT                              (1 << 18)
+#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT                              18
 #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               BITFIELD(18, 19)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT                             (1 << 9)
+#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT                             9
 #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              BITFIELD(9, 9)
 
 /* Used by PM_CORE_PWRSTST */
-#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT                              (1 << 6)
+#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT                              6
 #define OMAP4430_CORE_OCMRAM_STATEST_MASK                               BITFIELD(6, 7)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT                          (1 << 16)
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT                          16
 #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           BITFIELD(16, 17)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT                         (1 << 8)
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT                         8
 #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          BITFIELD(8, 8)
 
 /* Used by PM_CORE_PWRSTST */
-#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT                          (1 << 4)
+#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT                          4
 #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           BITFIELD(4, 5)
 
 /* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_DATA_SHIFT                                             (1 << 16)
+#define OMAP4430_DATA_SHIFT                                             16
 #define OMAP4430_DATA_MASK                                              BITFIELD(16, 23)
 
 /* Used by PRM_DEVICE_OFF_CTRL */
-#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT                                (1 << 0)
+#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT                                0
 #define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 BITFIELD(0, 0)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_DFILTEREN_SHIFT                                        (1 << 6)
+#define OMAP4430_DFILTEREN_SHIFT                                        6
 #define OMAP4430_DFILTEREN_MASK                                         BITFIELD(6, 6)
 
 /* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
-#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT                                (1 << 4)
+#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT                                4
 #define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 BITFIELD(4, 4)
 
 /* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT                                (1 << 4)
+#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT                                4
 #define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 BITFIELD(4, 4)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT                               (1 << 0)
+#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT                               0
 #define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                BITFIELD(0, 0)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT                               (1 << 0)
+#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT                               0
 #define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                BITFIELD(0, 0)
 
 /* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT                             (1 << 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT                             6
 #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              BITFIELD(6, 6)
 
 /* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT                             (1 << 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT                             6
 #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              BITFIELD(6, 6)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
-#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT                                (1 << 2)
+#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT                                2
 #define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 BITFIELD(2, 2)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT                                (1 << 2)
+#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT                                2
 #define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 BITFIELD(2, 2)
 
 /* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT                                (1 << 1)
+#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT                                1
 #define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 BITFIELD(1, 1)
 
 /* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT                                (1 << 1)
+#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT                                1
 #define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 BITFIELD(1, 1)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT                                (1 << 3)
+#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT                                3
 #define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 BITFIELD(3, 3)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT                                (1 << 3)
+#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT                                3
 #define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 BITFIELD(3, 3)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT                             (1 << 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT                             7
 #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              BITFIELD(7, 7)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT                             (1 << 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT                             7
 #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              BITFIELD(7, 7)
 
 /* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT                                (1 << 5)
+#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT                                5
 #define OMAP4430_DPLL_USB_RECAL_EN_MASK                                 BITFIELD(5, 5)
 
 /* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT                                (1 << 5)
+#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT                                5
 #define OMAP4430_DPLL_USB_RECAL_ST_MASK                                 BITFIELD(5, 5)
 
 /* Used by PM_DSS_PWRSTCTRL */
-#define OMAP4430_DSS_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_DSS_MEM_ONSTATE_SHIFT                                  16
 #define OMAP4430_DSS_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
 
 /* Used by PM_DSS_PWRSTCTRL */
-#define OMAP4430_DSS_MEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_DSS_MEM_RETSTATE_SHIFT                                 8
 #define OMAP4430_DSS_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
 
 /* Used by PM_DSS_PWRSTST */
-#define OMAP4430_DSS_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_DSS_MEM_STATEST_SHIFT                                  4
 #define OMAP4430_DSS_MEM_STATEST_MASK                                   BITFIELD(4, 5)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT                             (1 << 20)
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT                             20
 #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              BITFIELD(20, 21)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT                            (1 << 10)
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT                            10
 #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             BITFIELD(10, 10)
 
 /* Used by PM_CORE_PWRSTST */
-#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT                             (1 << 8)
+#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT                             8
 #define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              BITFIELD(8, 9)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT                          (1 << 22)
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT                          22
 #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           BITFIELD(22, 23)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT                         (1 << 11)
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT                         11
 #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          BITFIELD(11, 11)
 
 /* Used by PM_CORE_PWRSTST */
-#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT                          (1 << 10)
+#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT                          10
 #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           BITFIELD(10, 11)
 
 /* Used by RM_MPU_RSTST */
-#define OMAP4430_EMULATION_RST_SHIFT                                    (1 << 0)
+#define OMAP4430_EMULATION_RST_SHIFT                                    0
 #define OMAP4430_EMULATION_RST_MASK                                     BITFIELD(0, 0)
 
 /* Used by RM_DUCATI_RSTST */
-#define OMAP4430_EMULATION_RST1ST_SHIFT                                 (1 << 3)
+#define OMAP4430_EMULATION_RST1ST_SHIFT                                 3
 #define OMAP4430_EMULATION_RST1ST_MASK                                  BITFIELD(3, 3)
 
 /* Used by RM_DUCATI_RSTST */
-#define OMAP4430_EMULATION_RST2ST_SHIFT                                 (1 << 4)
+#define OMAP4430_EMULATION_RST2ST_SHIFT                                 4
 #define OMAP4430_EMULATION_RST2ST_MASK                                  BITFIELD(4, 4)
 
 /* Used by RM_IVAHD_RSTST */
-#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT                            (1 << 3)
+#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT                            3
 #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             BITFIELD(3, 3)
 
 /* Used by RM_IVAHD_RSTST */
-#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT                            (1 << 4)
+#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT                            4
 #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             BITFIELD(4, 4)
 
 /* Used by PM_EMU_PWRSTCTRL */
-#define OMAP4430_EMU_BANK_ONSTATE_SHIFT                                 (1 << 16)
+#define OMAP4430_EMU_BANK_ONSTATE_SHIFT                                 16
 #define OMAP4430_EMU_BANK_ONSTATE_MASK                                  BITFIELD(16, 17)
 
 /* Used by PM_EMU_PWRSTST */
-#define OMAP4430_EMU_BANK_STATEST_SHIFT                                 (1 << 4)
+#define OMAP4430_EMU_BANK_STATEST_SHIFT                                 4
 #define OMAP4430_EMU_BANK_STATEST_MASK                                  BITFIELD(4, 5)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
  */
-#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT                                (1 << 0)
+#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT                                0
 #define OMAP4430_ENABLE_RTA_EXPORT_MASK                                 BITFIELD(0, 0)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC1_SHIFT                                          (1 << 3)
+#define OMAP4430_ENFUNC1_SHIFT                                          3
 #define OMAP4430_ENFUNC1_MASK                                           BITFIELD(3, 3)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC3_SHIFT                                          (1 << 5)
+#define OMAP4430_ENFUNC3_SHIFT                                          5
 #define OMAP4430_ENFUNC3_MASK                                           BITFIELD(5, 5)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC4_SHIFT                                          (1 << 6)
+#define OMAP4430_ENFUNC4_SHIFT                                          6
 #define OMAP4430_ENFUNC4_MASK                                           BITFIELD(6, 6)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC5_SHIFT                                          (1 << 7)
+#define OMAP4430_ENFUNC5_SHIFT                                          7
 #define OMAP4430_ENFUNC5_MASK                                           BITFIELD(7, 7)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_ERRORGAIN_SHIFT                                        (1 << 16)
+#define OMAP4430_ERRORGAIN_SHIFT                                        16
 #define OMAP4430_ERRORGAIN_MASK                                         BITFIELD(16, 23)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_ERROROFFSET_SHIFT                                      (1 << 24)
+#define OMAP4430_ERROROFFSET_SHIFT                                      24
 #define OMAP4430_ERROROFFSET_MASK                                       BITFIELD(24, 31)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_EXTERNAL_WARM_RST_SHIFT                                (1 << 5)
+#define OMAP4430_EXTERNAL_WARM_RST_SHIFT                                5
 #define OMAP4430_EXTERNAL_WARM_RST_MASK                                 BITFIELD(5, 5)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_FORCEUPDATE_SHIFT                                      (1 << 1)
+#define OMAP4430_FORCEUPDATE_SHIFT                                      1
 #define OMAP4430_FORCEUPDATE_MASK                                       BITFIELD(1, 1)
 
 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
-#define OMAP4430_FORCEUPDATEWAIT_SHIFT                                  (1 << 8)
+#define OMAP4430_FORCEUPDATEWAIT_SHIFT                                  8
 #define OMAP4430_FORCEUPDATEWAIT_MASK                                   BITFIELD(8, 31)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
-#define OMAP4430_FORCEWKUP_EN_SHIFT                                     (1 << 10)
+#define OMAP4430_FORCEWKUP_EN_SHIFT                                     10
 #define OMAP4430_FORCEWKUP_EN_MASK                                      BITFIELD(10, 10)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
-#define OMAP4430_FORCEWKUP_ST_SHIFT                                     (1 << 10)
+#define OMAP4430_FORCEWKUP_ST_SHIFT                                     10
 #define OMAP4430_FORCEWKUP_ST_MASK                                      BITFIELD(10, 10)
 
 /* Used by PM_GFX_PWRSTCTRL */
-#define OMAP4430_GFX_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_GFX_MEM_ONSTATE_SHIFT                                  16
 #define OMAP4430_GFX_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
 
 /* Used by PM_GFX_PWRSTST */
-#define OMAP4430_GFX_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_GFX_MEM_STATEST_SHIFT                                  4
 #define OMAP4430_GFX_MEM_STATEST_MASK                                   BITFIELD(4, 5)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_GLOBAL_COLD_RST_SHIFT                                  (1 << 0)
+#define OMAP4430_GLOBAL_COLD_RST_SHIFT                                  0
 #define OMAP4430_GLOBAL_COLD_RST_MASK                                   BITFIELD(0, 0)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT                               (1 << 1)
+#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT                               1
 #define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                BITFIELD(1, 1)
 
 /* Used by PRM_IO_PMCTRL */
-#define OMAP4430_GLOBAL_WUEN_SHIFT                                      (1 << 16)
+#define OMAP4430_GLOBAL_WUEN_SHIFT                                      16
 #define OMAP4430_GLOBAL_WUEN_MASK                                       BITFIELD(16, 16)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_HSMCODE_SHIFT                                          (1 << 0)
+#define OMAP4430_HSMCODE_SHIFT                                          0
 #define OMAP4430_HSMCODE_MASK                                           BITFIELD(0, 2)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_HSMODEEN_SHIFT                                         (1 << 3)
+#define OMAP4430_HSMODEEN_SHIFT                                         3
 #define OMAP4430_HSMODEEN_MASK                                          BITFIELD(3, 3)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_HSSCLH_SHIFT                                           (1 << 16)
+#define OMAP4430_HSSCLH_SHIFT                                           16
 #define OMAP4430_HSSCLH_MASK                                            BITFIELD(16, 23)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_HSSCLL_SHIFT                                           (1 << 24)
+#define OMAP4430_HSSCLL_SHIFT                                           24
 #define OMAP4430_HSSCLL_MASK                                            BITFIELD(24, 31)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_HWA_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_HWA_MEM_ONSTATE_SHIFT                                  16
 #define OMAP4430_HWA_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_HWA_MEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_HWA_MEM_RETSTATE_SHIFT                                 8
 #define OMAP4430_HWA_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
 
 /* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_HWA_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_HWA_MEM_STATEST_SHIFT                                  4
 #define OMAP4430_HWA_MEM_STATEST_MASK                                   BITFIELD(4, 5)
 
 /* Used by RM_MPU_RSTST */
-#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT                               (1 << 1)
+#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT                               1
 #define OMAP4430_ICECRUSHER_MPU_RST_MASK                                BITFIELD(1, 1)
 
 /* Used by RM_DUCATI_RSTST */
-#define OMAP4430_ICECRUSHER_RST1ST_SHIFT                                (1 << 5)
+#define OMAP4430_ICECRUSHER_RST1ST_SHIFT                                5
 #define OMAP4430_ICECRUSHER_RST1ST_MASK                                 BITFIELD(5, 5)
 
 /* Used by RM_DUCATI_RSTST */
-#define OMAP4430_ICECRUSHER_RST2ST_SHIFT                                (1 << 6)
+#define OMAP4430_ICECRUSHER_RST2ST_SHIFT                                6
 #define OMAP4430_ICECRUSHER_RST2ST_MASK                                 BITFIELD(6, 6)
 
 /* Used by RM_IVAHD_RSTST */
-#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT                           (1 << 5)
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT                           5
 #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            BITFIELD(5, 5)
 
 /* Used by RM_IVAHD_RSTST */
-#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT                           (1 << 6)
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT                           6
 #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            BITFIELD(6, 6)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_ICEPICK_RST_SHIFT                                      (1 << 9)
+#define OMAP4430_ICEPICK_RST_SHIFT                                      9
 #define OMAP4430_ICEPICK_RST_MASK                                       BITFIELD(9, 9)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_INITVDD_SHIFT                                          (1 << 2)
+#define OMAP4430_INITVDD_SHIFT                                          2
 #define OMAP4430_INITVDD_MASK                                           BITFIELD(2, 2)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_INITVOLTAGE_SHIFT                                      (1 << 8)
+#define OMAP4430_INITVOLTAGE_SHIFT                                      8
 #define OMAP4430_INITVOLTAGE_MASK                                       BITFIELD(8, 15)
 
 /*
@@ -442,47 +442,47 @@
  * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
  * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
  */
-#define OMAP4430_INTRANSITION_SHIFT                                     (1 << 20)
+#define OMAP4430_INTRANSITION_SHIFT                                     20
 #define OMAP4430_INTRANSITION_MASK                                      BITFIELD(20, 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_IO_EN_SHIFT                                            (1 << 9)
+#define OMAP4430_IO_EN_SHIFT                                            9
 #define OMAP4430_IO_EN_MASK                                             BITFIELD(9, 9)
 
 /* Used by PRM_IO_PMCTRL */
-#define OMAP4430_IO_ON_STATUS_SHIFT                                     (1 << 5)
+#define OMAP4430_IO_ON_STATUS_SHIFT                                     5
 #define OMAP4430_IO_ON_STATUS_MASK                                      BITFIELD(5, 5)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_IO_ST_SHIFT                                            (1 << 9)
+#define OMAP4430_IO_ST_SHIFT                                            9
 #define OMAP4430_IO_ST_MASK                                             BITFIELD(9, 9)
 
 /* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOCLK_OVERRIDE_SHIFT                                  (1 << 0)
+#define OMAP4430_ISOCLK_OVERRIDE_SHIFT                                  0
 #define OMAP4430_ISOCLK_OVERRIDE_MASK                                   BITFIELD(0, 0)
 
 /* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOCLK_STATUS_SHIFT                                    (1 << 1)
+#define OMAP4430_ISOCLK_STATUS_SHIFT                                    1
 #define OMAP4430_ISOCLK_STATUS_MASK                                     BITFIELD(1, 1)
 
 /* Used by PRM_IO_PMCTRL */
-#define OMAP4430_ISOOVR_EXTEND_SHIFT                                    (1 << 4)
+#define OMAP4430_ISOOVR_EXTEND_SHIFT                                    4
 #define OMAP4430_ISOOVR_EXTEND_MASK                                     BITFIELD(4, 4)
 
 /* Used by PRM_IO_COUNT */
-#define OMAP4430_ISO_2_ON_TIME_SHIFT                                    (1 << 0)
+#define OMAP4430_ISO_2_ON_TIME_SHIFT                                    0
 #define OMAP4430_ISO_2_ON_TIME_MASK                                     BITFIELD(0, 7)
 
 /* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT                             (1 << 16)
+#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT                             16
 #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              BITFIELD(16, 17)
 
 /* Used by PM_L3INIT_PWRSTCTRL */
-#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT                            (1 << 8)
+#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT                            8
 #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             BITFIELD(8, 8)
 
 /* Used by PM_L3INIT_PWRSTST */
-#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT                             (1 << 4)
+#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT                             4
 #define OMAP4430_L3INIT_BANK1_STATEST_MASK                              BITFIELD(4, 5)
 
 /*
@@ -490,7 +490,7 @@
  * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL,
  * PM_IVAHD_PWRSTCTRL
  */
-#define OMAP4430_LOGICRETSTATE_SHIFT                                    (1 << 2)
+#define OMAP4430_LOGICRETSTATE_SHIFT                                    2
 #define OMAP4430_LOGICRETSTATE_MASK                                     BITFIELD(2, 2)
 
 /*
@@ -498,7 +498,7 @@
  * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
  * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
  */
-#define OMAP4430_LOGICSTATEST_SHIFT                                     (1 << 2)
+#define OMAP4430_LOGICSTATEST_SHIFT                                     2
 #define OMAP4430_LOGICSTATEST_MASK                                      BITFIELD(2, 2)
 
 /*
@@ -537,7 +537,7 @@
  * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT,
  * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT
  */
-#define OMAP4430_LOSTCONTEXT_DFF_SHIFT                                  (1 << 0)
+#define OMAP4430_LOSTCONTEXT_DFF_SHIFT                                  0
 #define OMAP4430_LOSTCONTEXT_DFF_MASK                                   BITFIELD(0, 0)
 
 /*
@@ -558,58 +558,58 @@
  * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT,
  * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT
  */
-#define OMAP4430_LOSTCONTEXT_RFF_SHIFT                                  (1 << 1)
+#define OMAP4430_LOSTCONTEXT_RFF_SHIFT                                  1
 #define OMAP4430_LOSTCONTEXT_RFF_MASK                                   BITFIELD(1, 1)
 
 /* Used by RM_ABE_AESS_CONTEXT */
-#define OMAP4430_LOSTMEM_AESSMEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_AESSMEM_SHIFT                                  8
 #define OMAP4430_LOSTMEM_AESSMEM_MASK                                   BITFIELD(8, 8)
 
 /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
-#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT                                  8
 #define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   BITFIELD(8, 8)
 
 /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT                           (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT                           8
 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            BITFIELD(8, 8)
 
 /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT                       (1 << 9)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT                       9
 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        BITFIELD(9, 9)
 
 /* Used by RM_L3_2_OCMC_RAM_CONTEXT */
-#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT                              (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT                              8
 #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               BITFIELD(8, 8)
 
 /*
  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
  * RM_SDMA_SDMA_CONTEXT
  */
-#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT                          (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT                          8
 #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           BITFIELD(8, 8)
 
 /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
-#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT                                  8
 #define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   BITFIELD(8, 8)
 
 /* Used by RM_DUCATI_DUCATI_CONTEXT */
-#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT                             (1 << 9)
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT                             9
 #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              BITFIELD(9, 9)
 
 /* Used by RM_DUCATI_DUCATI_CONTEXT */
-#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT                          (1 << 8)
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT                          8
 #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           BITFIELD(8, 8)
 
 /* Used by RM_EMU_DEBUGSS_CONTEXT */
-#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT                                 8
 #define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  BITFIELD(8, 8)
 
 /* Used by RM_GFX_GFX_CONTEXT */
-#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT                                  8
 #define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   BITFIELD(8, 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT                                  (1 << 10)
+#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT                                  10
 #define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   BITFIELD(10, 10)
 
 /*
@@ -619,19 +619,19 @@
  * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
  * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
  */
-#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT                             (1 << 8)
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT                             8
 #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              BITFIELD(8, 8)
 
 /* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_L1_SHIFT                                   (1 << 8)
+#define OMAP4430_LOSTMEM_MPU_L1_SHIFT                                   8
 #define OMAP4430_LOSTMEM_MPU_L1_MASK                                    BITFIELD(8, 8)
 
 /* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_L2_SHIFT                                   (1 << 9)
+#define OMAP4430_LOSTMEM_MPU_L2_SHIFT                                   9
 #define OMAP4430_LOSTMEM_MPU_L2_MASK                                    BITFIELD(9, 9)
 
 /* Used by RM_MPU_MPU_CONTEXT */
-#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT                                  (1 << 10)
+#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT                                  10
 #define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   BITFIELD(10, 10)
 
 /*
@@ -639,14 +639,14 @@
  * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
  * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
  */
-#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT                         (1 << 8)
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT                         8
 #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          BITFIELD(8, 8)
 
 /*
  * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
  * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
  */
-#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT                                (1 << 8)
+#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT                                8
 #define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 BITFIELD(8, 8)
 
 /*
@@ -654,35 +654,35 @@
  * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
  * RM_L4SEC_CRYPTODMA_CONTEXT
  */
-#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT                            (1 << 8)
+#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT                            8
 #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             BITFIELD(8, 8)
 
 /* Used by RM_IVAHD_SL2_CONTEXT */
-#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT                                  8
 #define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   BITFIELD(8, 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT                                 8
 #define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  BITFIELD(8, 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
-#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT                                 (1 << 9)
+#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT                                 9
 #define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  BITFIELD(9, 9)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT                               (1 << 10)
+#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT                               10
 #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                BITFIELD(10, 10)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT                                 8
 #define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  BITFIELD(8, 8)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
-#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT                                 (1 << 9)
+#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT                                 9
 #define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  BITFIELD(9, 9)
 
 /* Used by RM_WKUP_SARRAM_CONTEXT */
-#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT                                (1 << 8)
+#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT                                8
 #define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 BITFIELD(8, 8)
 
 /*
@@ -690,164 +690,164 @@
  * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
  * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
  */
-#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT                              (1 << 4)
+#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT                              4
 #define OMAP4430_LOWPOWERSTATECHANGE_MASK                               BITFIELD(4, 4)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_MEMORYCHANGE_SHIFT                                     (1 << 3)
+#define OMAP4430_MEMORYCHANGE_SHIFT                                     3
 #define OMAP4430_MEMORYCHANGE_MASK                                      BITFIELD(3, 3)
 
 /* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_READY_SHIFT                                      (1 << 1)
+#define OMAP4430_MODEM_READY_SHIFT                                      1
 #define OMAP4430_MODEM_READY_MASK                                       BITFIELD(1, 1)
 
 /* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT                               (1 << 9)
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT                               9
 #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                BITFIELD(9, 9)
 
 /* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_SLEEP_ST_SHIFT                                   (1 << 16)
+#define OMAP4430_MODEM_SLEEP_ST_SHIFT                                   16
 #define OMAP4430_MODEM_SLEEP_ST_MASK                                    BITFIELD(16, 16)
 
 /* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_MODEM_WAKE_IRQ_SHIFT                                   (1 << 8)
+#define OMAP4430_MODEM_WAKE_IRQ_SHIFT                                   8
 #define OMAP4430_MODEM_WAKE_IRQ_MASK                                    BITFIELD(8, 8)
 
 /* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L1_ONSTATE_SHIFT                                   (1 << 16)
+#define OMAP4430_MPU_L1_ONSTATE_SHIFT                                   16
 #define OMAP4430_MPU_L1_ONSTATE_MASK                                    BITFIELD(16, 17)
 
 /* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L1_RETSTATE_SHIFT                                  (1 << 8)
+#define OMAP4430_MPU_L1_RETSTATE_SHIFT                                  8
 #define OMAP4430_MPU_L1_RETSTATE_MASK                                   BITFIELD(8, 8)
 
 /* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_L1_STATEST_SHIFT                                   (1 << 4)
+#define OMAP4430_MPU_L1_STATEST_SHIFT                                   4
 #define OMAP4430_MPU_L1_STATEST_MASK                                    BITFIELD(4, 5)
 
 /* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L2_ONSTATE_SHIFT                                   (1 << 18)
+#define OMAP4430_MPU_L2_ONSTATE_SHIFT                                   18
 #define OMAP4430_MPU_L2_ONSTATE_MASK                                    BITFIELD(18, 19)
 
 /* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_L2_RETSTATE_SHIFT                                  (1 << 9)
+#define OMAP4430_MPU_L2_RETSTATE_SHIFT                                  9
 #define OMAP4430_MPU_L2_RETSTATE_MASK                                   BITFIELD(9, 9)
 
 /* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_L2_STATEST_SHIFT                                   (1 << 6)
+#define OMAP4430_MPU_L2_STATEST_SHIFT                                   6
 #define OMAP4430_MPU_L2_STATEST_MASK                                    BITFIELD(6, 7)
 
 /* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_RAM_ONSTATE_SHIFT                                  (1 << 20)
+#define OMAP4430_MPU_RAM_ONSTATE_SHIFT                                  20
 #define OMAP4430_MPU_RAM_ONSTATE_MASK                                   BITFIELD(20, 21)
 
 /* Used by PM_MPU_PWRSTCTRL */
-#define OMAP4430_MPU_RAM_RETSTATE_SHIFT                                 (1 << 10)
+#define OMAP4430_MPU_RAM_RETSTATE_SHIFT                                 10
 #define OMAP4430_MPU_RAM_RETSTATE_MASK                                  BITFIELD(10, 10)
 
 /* Used by PM_MPU_PWRSTST */
-#define OMAP4430_MPU_RAM_STATEST_SHIFT                                  (1 << 8)
+#define OMAP4430_MPU_RAM_STATEST_SHIFT                                  8
 #define OMAP4430_MPU_RAM_STATEST_MASK                                   BITFIELD(8, 9)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                            (1 << 2)
+#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                            2
 #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             BITFIELD(2, 2)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_MPU_WDT_RST_SHIFT                                      (1 << 3)
+#define OMAP4430_MPU_WDT_RST_SHIFT                                      3
 #define OMAP4430_MPU_WDT_RST_MASK                                       BITFIELD(3, 3)
 
 /* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT                         (1 << 18)
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT                         18
 #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          BITFIELD(18, 19)
 
 /* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT                        (1 << 9)
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT                        9
 #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         BITFIELD(9, 9)
 
 /* Used by PM_L4PER_PWRSTST */
-#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT                         (1 << 6)
+#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT                         6
 #define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          BITFIELD(6, 7)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT                            (1 << 24)
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT                            24
 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             BITFIELD(24, 25)
 
 /* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT                           (1 << 12)
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT                           12
 #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            BITFIELD(12, 12)
 
 /* Used by PM_CORE_PWRSTST */
-#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT                            (1 << 12)
+#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT                            12
 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             BITFIELD(12, 13)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
-#define OMAP4430_OFF_SHIFT                                              (1 << 0)
+#define OMAP4430_OFF_SHIFT                                              0
 #define OMAP4430_OFF_MASK                                               BITFIELD(0, 7)
 
 /* Used by PRM_LDO_BANDGAP_CTRL */
-#define OMAP4430_OFF_ENABLE_SHIFT                                       (1 << 0)
+#define OMAP4430_OFF_ENABLE_SHIFT                                       0
 #define OMAP4430_OFF_ENABLE_MASK                                        BITFIELD(0, 0)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
-#define OMAP4430_ON_SHIFT                                               (1 << 24)
+#define OMAP4430_ON_SHIFT                                               24
 #define OMAP4430_ON_MASK                                                BITFIELD(24, 31)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
-#define OMAP4430_ONLP_SHIFT                                             (1 << 16)
+#define OMAP4430_ONLP_SHIFT                                             16
 #define OMAP4430_ONLP_MASK                                              BITFIELD(16, 23)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_OPP_CHANGE_SHIFT                                       (1 << 2)
+#define OMAP4430_OPP_CHANGE_SHIFT                                       2
 #define OMAP4430_OPP_CHANGE_MASK                                        BITFIELD(2, 2)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_OPP_SEL_SHIFT                                          (1 << 0)
+#define OMAP4430_OPP_SEL_SHIFT                                          0
 #define OMAP4430_OPP_SEL_MASK                                           BITFIELD(0, 1)
 
 /* Used by PRM_SRAM_COUNT */
-#define OMAP4430_PCHARGECNT_VALUE_SHIFT                                 (1 << 0)
+#define OMAP4430_PCHARGECNT_VALUE_SHIFT                                 0
 #define OMAP4430_PCHARGECNT_VALUE_MASK                                  BITFIELD(0, 5)
 
 /* Used by PRM_PSCON_COUNT */
-#define OMAP4430_PCHARGE_TIME_SHIFT                                     (1 << 0)
+#define OMAP4430_PCHARGE_TIME_SHIFT                                     0
 #define OMAP4430_PCHARGE_TIME_MASK                                      BITFIELD(0, 7)
 
 /* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT                                (1 << 20)
+#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT                                20
 #define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 BITFIELD(20, 21)
 
 /* Used by PM_ABE_PWRSTCTRL */
-#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT                               (1 << 10)
+#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT                               10
 #define OMAP4430_PERIPHMEM_RETSTATE_MASK                                BITFIELD(10, 10)
 
 /* Used by PM_ABE_PWRSTST */
-#define OMAP4430_PERIPHMEM_STATEST_SHIFT                                (1 << 8)
+#define OMAP4430_PERIPHMEM_STATEST_SHIFT                                8
 #define OMAP4430_PERIPHMEM_STATEST_MASK                                 BITFIELD(8, 9)
 
 /* Used by PRM_PHASE1_CNDP */
-#define OMAP4430_PHASE1_CNDP_SHIFT                                      (1 << 0)
+#define OMAP4430_PHASE1_CNDP_SHIFT                                      0
 #define OMAP4430_PHASE1_CNDP_MASK                                       BITFIELD(0, 31)
 
 /* Used by PRM_PHASE2A_CNDP */
-#define OMAP4430_PHASE2A_CNDP_SHIFT                                     (1 << 0)
+#define OMAP4430_PHASE2A_CNDP_SHIFT                                     0
 #define OMAP4430_PHASE2A_CNDP_MASK                                      BITFIELD(0, 31)
 
 /* Used by PRM_PHASE2B_CNDP */
-#define OMAP4430_PHASE2B_CNDP_SHIFT                                     (1 << 0)
+#define OMAP4430_PHASE2B_CNDP_SHIFT                                     0
 #define OMAP4430_PHASE2B_CNDP_MASK                                      BITFIELD(0, 31)
 
 /* Used by PRM_PSCON_COUNT */
-#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT                            (1 << 8)
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT                            8
 #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             BITFIELD(8, 15)
 
 /*
@@ -856,7 +856,7 @@
  * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
  * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
  */
-#define OMAP4430_POWERSTATE_SHIFT                                       (1 << 0)
+#define OMAP4430_POWERSTATE_SHIFT                                       0
 #define OMAP4430_POWERSTATE_MASK                                        BITFIELD(0, 1)
 
 /*
@@ -864,35 +864,35 @@
  * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
  * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
  */
-#define OMAP4430_POWERSTATEST_SHIFT                                     (1 << 0)
+#define OMAP4430_POWERSTATEST_SHIFT                                     0
 #define OMAP4430_POWERSTATEST_MASK                                      BITFIELD(0, 1)
 
 /* Used by PRM_PWRREQCTRL */
-#define OMAP4430_PWRREQ_COND_SHIFT                                      (1 << 0)
+#define OMAP4430_PWRREQ_COND_SHIFT                                      0
 #define OMAP4430_PWRREQ_COND_MASK                                       BITFIELD(0, 1)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_CORE_L_SHIFT                                 (1 << 3)
+#define OMAP4430_RACEN_VDD_CORE_L_SHIFT                                 3
 #define OMAP4430_RACEN_VDD_CORE_L_MASK                                  BITFIELD(3, 3)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_IVA_L_SHIFT                                  (1 << 11)
+#define OMAP4430_RACEN_VDD_IVA_L_SHIFT                                  11
 #define OMAP4430_RACEN_VDD_IVA_L_MASK                                   BITFIELD(11, 11)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RACEN_VDD_MPU_L_SHIFT                                  (1 << 20)
+#define OMAP4430_RACEN_VDD_MPU_L_SHIFT                                  20
 #define OMAP4430_RACEN_VDD_MPU_L_MASK                                   BITFIELD(20, 20)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_CORE_L_SHIFT                                   (1 << 2)
+#define OMAP4430_RAC_VDD_CORE_L_SHIFT                                   2
 #define OMAP4430_RAC_VDD_CORE_L_MASK                                    BITFIELD(2, 2)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_IVA_L_SHIFT                                    (1 << 10)
+#define OMAP4430_RAC_VDD_IVA_L_SHIFT                                    10
 #define OMAP4430_RAC_VDD_IVA_L_MASK                                     BITFIELD(10, 10)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAC_VDD_MPU_L_SHIFT                                    (1 << 19)
+#define OMAP4430_RAC_VDD_MPU_L_SHIFT                                    19
 #define OMAP4430_RAC_VDD_MPU_L_MASK                                     BITFIELD(19, 19)
 
 /*
@@ -900,7 +900,7 @@
  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
-#define OMAP4430_RAMP_DOWN_COUNT_SHIFT                                  (1 << 16)
+#define OMAP4430_RAMP_DOWN_COUNT_SHIFT                                  16
 #define OMAP4430_RAMP_DOWN_COUNT_MASK                                   BITFIELD(16, 21)
 
 /*
@@ -908,7 +908,7 @@
  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
-#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT                                (1 << 24)
+#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT                                24
 #define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 BITFIELD(24, 25)
 
 /*
@@ -916,7 +916,7 @@
  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
-#define OMAP4430_RAMP_UP_COUNT_SHIFT                                    (1 << 0)
+#define OMAP4430_RAMP_UP_COUNT_SHIFT                                    0
 #define OMAP4430_RAMP_UP_COUNT_MASK                                     BITFIELD(0, 5)
 
 /*
@@ -924,1282 +924,1282 @@
  * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
-#define OMAP4430_RAMP_UP_PRESCAL_SHIFT                                  (1 << 8)
+#define OMAP4430_RAMP_UP_PRESCAL_SHIFT                                  8
 #define OMAP4430_RAMP_UP_PRESCAL_MASK                                   BITFIELD(8, 9)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_CORE_L_SHIFT                                   (1 << 1)
+#define OMAP4430_RAV_VDD_CORE_L_SHIFT                                   1
 #define OMAP4430_RAV_VDD_CORE_L_MASK                                    BITFIELD(1, 1)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_IVA_L_SHIFT                                    (1 << 9)
+#define OMAP4430_RAV_VDD_IVA_L_SHIFT                                    9
 #define OMAP4430_RAV_VDD_IVA_L_MASK                                     BITFIELD(9, 9)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_RAV_VDD_MPU_L_SHIFT                                    (1 << 18)
+#define OMAP4430_RAV_VDD_MPU_L_SHIFT                                    18
 #define OMAP4430_RAV_VDD_MPU_L_MASK                                     BITFIELD(18, 18)
 
 /* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_REGADDR_SHIFT                                          (1 << 8)
+#define OMAP4430_REGADDR_SHIFT                                          8
 #define OMAP4430_REGADDR_MASK                                           BITFIELD(8, 15)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
-#define OMAP4430_RET_SHIFT                                              (1 << 8)
+#define OMAP4430_RET_SHIFT                                              8
 #define OMAP4430_RET_MASK                                               BITFIELD(8, 15)
 
 /* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT                            (1 << 16)
+#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT                            16
 #define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             BITFIELD(16, 17)
 
 /* Used by PM_L4PER_PWRSTCTRL */
-#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT                           (1 << 8)
+#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT                           8
 #define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            BITFIELD(8, 8)
 
 /* Used by PM_L4PER_PWRSTST */
-#define OMAP4430_RETAINED_BANK_STATEST_SHIFT                            (1 << 4)
+#define OMAP4430_RETAINED_BANK_STATEST_SHIFT                            4
 #define OMAP4430_RETAINED_BANK_STATEST_MASK                             BITFIELD(4, 5)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
-#define OMAP4430_RETMODE_ENABLE_SHIFT                                   (1 << 0)
+#define OMAP4430_RETMODE_ENABLE_SHIFT                                   0
 #define OMAP4430_RETMODE_ENABLE_MASK                                    BITFIELD(0, 0)
 
 /* Used by REVISION_PRM */
-#define OMAP4430_REV_SHIFT                                              (1 << 0)
+#define OMAP4430_REV_SHIFT                                              0
 #define OMAP4430_REV_MASK                                               BITFIELD(0, 7)
 
 /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
-#define OMAP4430_RST1_SHIFT                                             (1 << 0)
+#define OMAP4430_RST1_SHIFT                                             0
 #define OMAP4430_RST1_MASK                                              BITFIELD(0, 0)
 
 /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
-#define OMAP4430_RST1ST_SHIFT                                           (1 << 0)
+#define OMAP4430_RST1ST_SHIFT                                           0
 #define OMAP4430_RST1ST_MASK                                            BITFIELD(0, 0)
 
 /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
-#define OMAP4430_RST2_SHIFT                                             (1 << 1)
+#define OMAP4430_RST2_SHIFT                                             1
 #define OMAP4430_RST2_MASK                                              BITFIELD(1, 1)
 
 /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
-#define OMAP4430_RST2ST_SHIFT                                           (1 << 1)
+#define OMAP4430_RST2ST_SHIFT                                           1
 #define OMAP4430_RST2ST_MASK                                            BITFIELD(1, 1)
 
 /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
-#define OMAP4430_RST3_SHIFT                                             (1 << 2)
+#define OMAP4430_RST3_SHIFT                                             2
 #define OMAP4430_RST3_MASK                                              BITFIELD(2, 2)
 
 /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
-#define OMAP4430_RST3ST_SHIFT                                           (1 << 2)
+#define OMAP4430_RST3ST_SHIFT                                           2
 #define OMAP4430_RST3ST_MASK                                            BITFIELD(2, 2)
 
 /* Used by PRM_RSTTIME */
-#define OMAP4430_RSTTIME1_SHIFT                                         (1 << 0)
+#define OMAP4430_RSTTIME1_SHIFT                                         0
 #define OMAP4430_RSTTIME1_MASK                                          BITFIELD(0, 9)
 
 /* Used by PRM_RSTTIME */
-#define OMAP4430_RSTTIME2_SHIFT                                         (1 << 10)
+#define OMAP4430_RSTTIME2_SHIFT                                         10
 #define OMAP4430_RSTTIME2_MASK                                          BITFIELD(10, 14)
 
 /* Used by PRM_RSTCTRL */
-#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT                               (1 << 1)
+#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT                               1
 #define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                BITFIELD(1, 1)
 
 /* Used by PRM_RSTCTRL */
-#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT                               (1 << 0)
+#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT                               0
 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                BITFIELD(0, 0)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_SA_VDD_CORE_L_SHIFT                                    (1 << 0)
+#define OMAP4430_SA_VDD_CORE_L_SHIFT                                    0
 #define OMAP4430_SA_VDD_CORE_L_MASK                                     BITFIELD(0, 0)
 
 /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT                                (1 << 0)
+#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT                                0
 #define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 BITFIELD(0, 6)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_SA_VDD_IVA_L_SHIFT                                     (1 << 8)
+#define OMAP4430_SA_VDD_IVA_L_SHIFT                                     8
 #define OMAP4430_SA_VDD_IVA_L_MASK                                      BITFIELD(8, 8)
 
 /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT                      (1 << 8)
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT                      8
 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(8, 14)
 
 /* Used by PRM_VC_CFG_CHANNEL */
-#define OMAP4430_SA_VDD_MPU_L_SHIFT                                     (1 << 16)
+#define OMAP4430_SA_VDD_MPU_L_SHIFT                                     16
 #define OMAP4430_SA_VDD_MPU_L_MASK                                      BITFIELD(16, 16)
 
 /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
-#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT                      (1 << 16)
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT                      16
 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(16, 22)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_SCLH_SHIFT                                             (1 << 0)
+#define OMAP4430_SCLH_SHIFT                                             0
 #define OMAP4430_SCLH_MASK                                              BITFIELD(0, 7)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
-#define OMAP4430_SCLL_SHIFT                                             (1 << 8)
+#define OMAP4430_SCLL_SHIFT                                             8
 #define OMAP4430_SCLL_MASK                                              BITFIELD(8, 15)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_SECURE_WDT_RST_SHIFT                                   (1 << 4)
+#define OMAP4430_SECURE_WDT_RST_SHIFT                                   4
 #define OMAP4430_SECURE_WDT_RST_MASK                                    BITFIELD(4, 4)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_SL2_MEM_ONSTATE_SHIFT                                  (1 << 18)
+#define OMAP4430_SL2_MEM_ONSTATE_SHIFT                                  18
 #define OMAP4430_SL2_MEM_ONSTATE_MASK                                   BITFIELD(18, 19)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_SL2_MEM_RETSTATE_SHIFT                                 (1 << 9)
+#define OMAP4430_SL2_MEM_RETSTATE_SHIFT                                 9
 #define OMAP4430_SL2_MEM_RETSTATE_MASK                                  BITFIELD(9, 9)
 
 /* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_SL2_MEM_STATEST_SHIFT                                  (1 << 6)
+#define OMAP4430_SL2_MEM_STATEST_SHIFT                                  6
 #define OMAP4430_SL2_MEM_STATEST_MASK                                   BITFIELD(6, 7)
 
 /* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_SLAVEADDR_SHIFT                                        (1 << 0)
+#define OMAP4430_SLAVEADDR_SHIFT                                        0
 #define OMAP4430_SLAVEADDR_MASK                                         BITFIELD(0, 6)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SLEEP_RBB_SEL_SHIFT                                    (1 << 3)
+#define OMAP4430_SLEEP_RBB_SEL_SHIFT                                    3
 #define OMAP4430_SLEEP_RBB_SEL_MASK                                     BITFIELD(3, 3)
 
 /* Used by PRM_SRAM_COUNT */
-#define OMAP4430_SLPCNT_VALUE_SHIFT                                     (1 << 16)
+#define OMAP4430_SLPCNT_VALUE_SHIFT                                     16
 #define OMAP4430_SLPCNT_VALUE_MASK                                      BITFIELD(16, 23)
 
 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
-#define OMAP4430_SMPSWAITTIMEMAX_SHIFT                                  (1 << 8)
+#define OMAP4430_SMPSWAITTIMEMAX_SHIFT                                  8
 #define OMAP4430_SMPSWAITTIMEMAX_MASK                                   BITFIELD(8, 23)
 
 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
-#define OMAP4430_SMPSWAITTIMEMIN_SHIFT                                  (1 << 8)
+#define OMAP4430_SMPSWAITTIMEMIN_SHIFT                                  8
 #define OMAP4430_SMPSWAITTIMEMIN_MASK                                   BITFIELD(8, 23)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SR2EN_SHIFT                                            (1 << 0)
+#define OMAP4430_SR2EN_SHIFT                                            0
 #define OMAP4430_SR2EN_MASK                                             BITFIELD(0, 0)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_SR2_IN_TRANSITION_SHIFT                                (1 << 6)
+#define OMAP4430_SR2_IN_TRANSITION_SHIFT                                6
 #define OMAP4430_SR2_IN_TRANSITION_MASK                                 BITFIELD(6, 6)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
-#define OMAP4430_SR2_STATUS_SHIFT                                       (1 << 3)
+#define OMAP4430_SR2_STATUS_SHIFT                                       3
 #define OMAP4430_SR2_STATUS_MASK                                        BITFIELD(3, 4)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
-#define OMAP4430_SR2_WTCNT_VALUE_SHIFT                                  (1 << 8)
+#define OMAP4430_SR2_WTCNT_VALUE_SHIFT                                  8
 #define OMAP4430_SR2_WTCNT_VALUE_MASK                                   BITFIELD(8, 15)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
-#define OMAP4430_SRAMLDO_STATUS_SHIFT                                   (1 << 8)
+#define OMAP4430_SRAMLDO_STATUS_SHIFT                                   8
 #define OMAP4430_SRAMLDO_STATUS_MASK                                    BITFIELD(8, 8)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
-#define OMAP4430_SRAM_IN_TRANSITION_SHIFT                               (1 << 9)
+#define OMAP4430_SRAM_IN_TRANSITION_SHIFT                               9
 #define OMAP4430_SRAM_IN_TRANSITION_MASK                                BITFIELD(9, 9)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
-#define OMAP4430_SRMODEEN_SHIFT                                         (1 << 4)
+#define OMAP4430_SRMODEEN_SHIFT                                         4
 #define OMAP4430_SRMODEEN_MASK                                          BITFIELD(4, 4)
 
 /* Used by PRM_VOLTSETUP_WARMRESET */
-#define OMAP4430_STABLE_COUNT_SHIFT                                     (1 << 0)
+#define OMAP4430_STABLE_COUNT_SHIFT                                     0
 #define OMAP4430_STABLE_COUNT_MASK                                      BITFIELD(0, 5)
 
 /* Used by PRM_VOLTSETUP_WARMRESET */
-#define OMAP4430_STABLE_PRESCAL_SHIFT                                   (1 << 8)
+#define OMAP4430_STABLE_PRESCAL_SHIFT                                   8
 #define OMAP4430_STABLE_PRESCAL_MASK                                    BITFIELD(8, 9)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT                                 (1 << 20)
+#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT                                 20
 #define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  BITFIELD(20, 21)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT                                (1 << 10)
+#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT                                10
 #define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 BITFIELD(10, 10)
 
 /* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_TCM1_MEM_STATEST_SHIFT                                 (1 << 8)
+#define OMAP4430_TCM1_MEM_STATEST_SHIFT                                 8
 #define OMAP4430_TCM1_MEM_STATEST_MASK                                  BITFIELD(8, 9)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT                                 (1 << 22)
+#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT                                 22
 #define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  BITFIELD(22, 23)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
-#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT                                (1 << 11)
+#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT                                11
 #define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 BITFIELD(11, 11)
 
 /* Used by PM_IVAHD_PWRSTST */
-#define OMAP4430_TCM2_MEM_STATEST_SHIFT                                 (1 << 10)
+#define OMAP4430_TCM2_MEM_STATEST_SHIFT                                 10
 #define OMAP4430_TCM2_MEM_STATEST_MASK                                  BITFIELD(10, 11)
 
 /* Used by RM_TESLA_RSTST */
-#define OMAP4430_TESLASS_EMU_RSTST_SHIFT                                (1 << 2)
+#define OMAP4430_TESLASS_EMU_RSTST_SHIFT                                2
 #define OMAP4430_TESLASS_EMU_RSTST_MASK                                 BITFIELD(2, 2)
 
 /* Used by RM_TESLA_RSTST */
-#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT                          (1 << 3)
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT                          3
 #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           BITFIELD(3, 3)
 
 /* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT                               (1 << 20)
+#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT                               20
 #define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                BITFIELD(20, 21)
 
 /* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT                              (1 << 10)
+#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT                              10
 #define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               BITFIELD(10, 10)
 
 /* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_EDMA_STATEST_SHIFT                               (1 << 8)
+#define OMAP4430_TESLA_EDMA_STATEST_SHIFT                               8
 #define OMAP4430_TESLA_EDMA_STATEST_MASK                                BITFIELD(8, 9)
 
 /* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L1_ONSTATE_SHIFT                                 (1 << 16)
+#define OMAP4430_TESLA_L1_ONSTATE_SHIFT                                 16
 #define OMAP4430_TESLA_L1_ONSTATE_MASK                                  BITFIELD(16, 17)
 
 /* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L1_RETSTATE_SHIFT                                (1 << 8)
+#define OMAP4430_TESLA_L1_RETSTATE_SHIFT                                8
 #define OMAP4430_TESLA_L1_RETSTATE_MASK                                 BITFIELD(8, 8)
 
 /* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_L1_STATEST_SHIFT                                 (1 << 4)
+#define OMAP4430_TESLA_L1_STATEST_SHIFT                                 4
 #define OMAP4430_TESLA_L1_STATEST_MASK                                  BITFIELD(4, 5)
 
 /* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L2_ONSTATE_SHIFT                                 (1 << 18)
+#define OMAP4430_TESLA_L2_ONSTATE_SHIFT                                 18
 #define OMAP4430_TESLA_L2_ONSTATE_MASK                                  BITFIELD(18, 19)
 
 /* Used by PM_TESLA_PWRSTCTRL */
-#define OMAP4430_TESLA_L2_RETSTATE_SHIFT                                (1 << 9)
+#define OMAP4430_TESLA_L2_RETSTATE_SHIFT                                9
 #define OMAP4430_TESLA_L2_RETSTATE_MASK                                 BITFIELD(9, 9)
 
 /* Used by PM_TESLA_PWRSTST */
-#define OMAP4430_TESLA_L2_STATEST_SHIFT                                 (1 << 6)
+#define OMAP4430_TESLA_L2_STATEST_SHIFT                                 6
 #define OMAP4430_TESLA_L2_STATEST_MASK                                  BITFIELD(6, 7)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP4430_TIMEOUT_SHIFT                                          (1 << 0)
+#define OMAP4430_TIMEOUT_SHIFT                                          0
 #define OMAP4430_TIMEOUT_MASK                                           BITFIELD(0, 15)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_TIMEOUTEN_SHIFT                                        (1 << 3)
+#define OMAP4430_TIMEOUTEN_SHIFT                                        3
 #define OMAP4430_TIMEOUTEN_MASK                                         BITFIELD(3, 3)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_TRANSITION_EN_SHIFT                                    (1 << 8)
+#define OMAP4430_TRANSITION_EN_SHIFT                                    8
 #define OMAP4430_TRANSITION_EN_MASK                                     BITFIELD(8, 8)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_TRANSITION_ST_SHIFT                                    (1 << 8)
+#define OMAP4430_TRANSITION_ST_SHIFT                                    8
 #define OMAP4430_TRANSITION_ST_MASK                                     BITFIELD(8, 8)
 
 /* Used by PRM_VC_VAL_BYPASS */
-#define OMAP4430_VALID_SHIFT                                            (1 << 24)
+#define OMAP4430_VALID_SHIFT                                            24
 #define OMAP4430_VALID_MASK                                             BITFIELD(24, 24)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_BYPASSACK_EN_SHIFT                                  (1 << 14)
+#define OMAP4430_VC_BYPASSACK_EN_SHIFT                                  14
 #define OMAP4430_VC_BYPASSACK_EN_MASK                                   BITFIELD(14, 14)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_BYPASSACK_ST_SHIFT                                  (1 << 14)
+#define OMAP4430_VC_BYPASSACK_ST_SHIFT                                  14
 #define OMAP4430_VC_BYPASSACK_ST_MASK                                   BITFIELD(14, 14)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_IVA_VPACK_EN_SHIFT                                  (1 << 30)
+#define OMAP4430_VC_IVA_VPACK_EN_SHIFT                                  30
 #define OMAP4430_VC_IVA_VPACK_EN_MASK                                   BITFIELD(30, 30)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_IVA_VPACK_ST_SHIFT                                  (1 << 30)
+#define OMAP4430_VC_IVA_VPACK_ST_SHIFT                                  30
 #define OMAP4430_VC_IVA_VPACK_ST_MASK                                   BITFIELD(30, 30)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VC_MPU_VPACK_EN_SHIFT                                  (1 << 6)
+#define OMAP4430_VC_MPU_VPACK_EN_SHIFT                                  6
 #define OMAP4430_VC_MPU_VPACK_EN_MASK                                   BITFIELD(6, 6)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VC_MPU_VPACK_ST_SHIFT                                  (1 << 6)
+#define OMAP4430_VC_MPU_VPACK_ST_SHIFT                                  6
 #define OMAP4430_VC_MPU_VPACK_ST_MASK                                   BITFIELD(6, 6)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_RAERR_EN_SHIFT                                      (1 << 12)
+#define OMAP4430_VC_RAERR_EN_SHIFT                                      12
 #define OMAP4430_VC_RAERR_EN_MASK                                       BITFIELD(12, 12)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_RAERR_ST_SHIFT                                      (1 << 12)
+#define OMAP4430_VC_RAERR_ST_SHIFT                                      12
 #define OMAP4430_VC_RAERR_ST_MASK                                       BITFIELD(12, 12)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_SAERR_EN_SHIFT                                      (1 << 11)
+#define OMAP4430_VC_SAERR_EN_SHIFT                                      11
 #define OMAP4430_VC_SAERR_EN_MASK                                       BITFIELD(11, 11)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_SAERR_ST_SHIFT                                      (1 << 11)
+#define OMAP4430_VC_SAERR_ST_SHIFT                                      11
 #define OMAP4430_VC_SAERR_ST_MASK                                       BITFIELD(11, 11)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VC_TOERR_EN_SHIFT                                      (1 << 13)
+#define OMAP4430_VC_TOERR_EN_SHIFT                                      13
 #define OMAP4430_VC_TOERR_EN_MASK                                       BITFIELD(13, 13)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VC_TOERR_ST_SHIFT                                      (1 << 13)
+#define OMAP4430_VC_TOERR_ST_SHIFT                                      13
 #define OMAP4430_VC_TOERR_ST_MASK                                       BITFIELD(13, 13)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP4430_VDDMAX_SHIFT                                           (1 << 24)
+#define OMAP4430_VDDMAX_SHIFT                                           24
 #define OMAP4430_VDDMAX_MASK                                            BITFIELD(24, 31)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
-#define OMAP4430_VDDMIN_SHIFT                                           (1 << 16)
+#define OMAP4430_VDDMIN_SHIFT                                           16
 #define OMAP4430_VDDMIN_MASK                                            BITFIELD(16, 23)
 
 /* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT                             (1 << 12)
+#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT                             12
 #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              BITFIELD(12, 12)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                            (1 << 8)
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                            8
 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             BITFIELD(8, 8)
 
 /* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT                              (1 << 14)
+#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT                              14
 #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               BITFIELD(14, 14)
 
 /* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_IVA_PRESENCE_SHIFT                                 (1 << 9)
+#define OMAP4430_VDD_IVA_PRESENCE_SHIFT                                 9
 #define OMAP4430_VDD_IVA_PRESENCE_MASK                                  BITFIELD(9, 9)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT                             (1 << 7)
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT                             7
 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              BITFIELD(7, 7)
 
 /* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT                              (1 << 13)
+#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT                              13
 #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               BITFIELD(13, 13)
 
 /* Used by PRM_VOLTCTRL */
-#define OMAP4430_VDD_MPU_PRESENCE_SHIFT                                 (1 << 8)
+#define OMAP4430_VDD_MPU_PRESENCE_SHIFT                                 8
 #define OMAP4430_VDD_MPU_PRESENCE_MASK                                  BITFIELD(8, 8)
 
 /* Used by PRM_RSTST */
-#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT                             (1 << 6)
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT                             6
 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              BITFIELD(6, 6)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT                                 (1 << 0)
+#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT                                 0
 #define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT                                  (1 << 8)
+#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT                                  8
 #define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
-#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT                                  (1 << 16)
+#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT                                  16
 #define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
-#define OMAP4430_VPENABLE_SHIFT                                         (1 << 0)
+#define OMAP4430_VPENABLE_SHIFT                                         0
 #define OMAP4430_VPENABLE_MASK                                          BITFIELD(0, 0)
 
 /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
-#define OMAP4430_VPINIDLE_SHIFT                                         (1 << 0)
+#define OMAP4430_VPINIDLE_SHIFT                                         0
 #define OMAP4430_VPINIDLE_MASK                                          BITFIELD(0, 0)
 
 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
-#define OMAP4430_VPVOLTAGE_SHIFT                                        (1 << 0)
+#define OMAP4430_VPVOLTAGE_SHIFT                                        0
 #define OMAP4430_VPVOLTAGE_MASK                                         BITFIELD(0, 7)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT                               (1 << 20)
+#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT                               20
 #define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                BITFIELD(20, 20)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT                               (1 << 20)
+#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT                               20
 #define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                BITFIELD(20, 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT                                (1 << 18)
+#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT                                18
 #define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 BITFIELD(18, 18)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT                                (1 << 18)
+#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT                                18
 #define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 BITFIELD(18, 18)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT                                (1 << 17)
+#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT                                17
 #define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 BITFIELD(17, 17)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT                                (1 << 17)
+#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT                                17
 #define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 BITFIELD(17, 17)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT                             (1 << 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT                             19
 #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              BITFIELD(19, 19)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT                             (1 << 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT                             19
 #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              BITFIELD(19, 19)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT                         (1 << 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT                         16
 #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          BITFIELD(16, 16)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT                         (1 << 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT                         16
 #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          BITFIELD(16, 16)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT                             (1 << 21)
+#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT                             21
 #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              BITFIELD(21, 21)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT                             (1 << 21)
+#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT                             21
 #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              BITFIELD(21, 21)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT                                (1 << 28)
+#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT                                28
 #define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 BITFIELD(28, 28)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT                                (1 << 28)
+#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT                                28
 #define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 BITFIELD(28, 28)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT                                 (1 << 26)
+#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT                                 26
 #define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  BITFIELD(26, 26)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT                                 (1 << 26)
+#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT                                 26
 #define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  BITFIELD(26, 26)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT                                 (1 << 25)
+#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT                                 25
 #define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  BITFIELD(25, 25)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT                                 (1 << 25)
+#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT                                 25
 #define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  BITFIELD(25, 25)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT                              (1 << 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT                              27
 #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               BITFIELD(27, 27)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT                              (1 << 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT                              27
 #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               BITFIELD(27, 27)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT                          (1 << 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT                          24
 #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           BITFIELD(24, 24)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT                          (1 << 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT                          24
 #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           BITFIELD(24, 24)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
-#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT                              (1 << 29)
+#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT                              29
 #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               BITFIELD(29, 29)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
-#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT                              (1 << 29)
+#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT                              29
 #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               BITFIELD(29, 29)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT                                (1 << 4)
+#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT                                4
 #define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 BITFIELD(4, 4)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT                                (1 << 4)
+#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT                                4
 #define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 BITFIELD(4, 4)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT                                 (1 << 2)
+#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT                                 2
 #define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  BITFIELD(2, 2)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT                                 (1 << 2)
+#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT                                 2
 #define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  BITFIELD(2, 2)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT                                 (1 << 1)
+#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT                                 1
 #define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  BITFIELD(1, 1)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT                                 (1 << 1)
+#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT                                 1
 #define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  BITFIELD(1, 1)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT                              (1 << 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT                              3
 #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               BITFIELD(3, 3)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT                              (1 << 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT                              3
 #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               BITFIELD(3, 3)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT                          (1 << 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT                          0
 #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           BITFIELD(0, 0)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT                          (1 << 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT                          0
 #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           BITFIELD(0, 0)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
-#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT                              (1 << 5)
+#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT                              5
 #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               BITFIELD(5, 5)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
-#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT                              (1 << 5)
+#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT                              5
 #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               BITFIELD(5, 5)
 
 /* Used by PRM_SRAM_COUNT */
-#define OMAP4430_VSETUPCNT_VALUE_SHIFT                                  (1 << 8)
+#define OMAP4430_VSETUPCNT_VALUE_SHIFT                                  8
 #define OMAP4430_VSETUPCNT_VALUE_MASK                                   BITFIELD(8, 15)
 
 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
-#define OMAP4430_VSTEPMAX_SHIFT                                         (1 << 0)
+#define OMAP4430_VSTEPMAX_SHIFT                                         0
 #define OMAP4430_VSTEPMAX_MASK                                          BITFIELD(0, 7)
 
 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
-#define OMAP4430_VSTEPMIN_SHIFT                                         (1 << 0)
+#define OMAP4430_VSTEPMIN_SHIFT                                         0
 #define OMAP4430_VSTEPMIN_MASK                                          BITFIELD(0, 7)
 
 /* Used by PRM_MODEM_IF_CTRL */
-#define OMAP4430_WAKE_MODEM_SHIFT                                       (1 << 0)
+#define OMAP4430_WAKE_MODEM_SHIFT                                       0
 #define OMAP4430_WAKE_MODEM_MASK                                        BITFIELD(0, 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT                             (1 << 1)
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT                             1
 #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              BITFIELD(1, 1)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT                                0
 #define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 BITFIELD(0, 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT                               3
 #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                BITFIELD(3, 3)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT                              (1 << 2)
+#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT                              2
 #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               BITFIELD(2, 2)
 
 /* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT                            7
 #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             BITFIELD(7, 7)
 
 /* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT                           (1 << 6)
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT                           6
 #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            BITFIELD(6, 6)
 
 /* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_ABE_DMIC_WKDEP */
-#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT                           (1 << 2)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT                           2
 #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            BITFIELD(2, 2)
 
 /* Used by PM_L4PER_DMTIMER10_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT                            (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT                            0
 #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             BITFIELD(0, 0)
 
 /* Used by PM_L4PER_DMTIMER11_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT                         (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT                         1
 #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          BITFIELD(1, 1)
 
 /* Used by PM_L4PER_DMTIMER11_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT                            (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT                            0
 #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             BITFIELD(0, 0)
 
 /* Used by PM_L4PER_DMTIMER2_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_L4PER_DMTIMER3_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT                          1
 #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           BITFIELD(1, 1)
 
 /* Used by PM_L4PER_DMTIMER3_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_L4PER_DMTIMER4_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT                          1
 #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           BITFIELD(1, 1)
 
 /* Used by PM_L4PER_DMTIMER4_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_L4PER_DMTIMER9_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT                          1
 #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           BITFIELD(1, 1)
 
 /* Used by PM_L4PER_DMTIMER9_WKDEP */
-#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT                              (1 << 5)
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT                              5
 #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               BITFIELD(5, 5)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT                                 (1 << 4)
+#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT                                 4
 #define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  BITFIELD(4, 4)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT                                (1 << 7)
+#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT                                7
 #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 BITFIELD(7, 7)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT                               (1 << 6)
+#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT                               6
 #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                BITFIELD(6, 6)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT                              (1 << 9)
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT                              9
 #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               BITFIELD(9, 9)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT                                 (1 << 8)
+#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT                                 8
 #define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  BITFIELD(8, 8)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT                                (1 << 11)
+#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT                                11
 #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 BITFIELD(11, 11)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT                               (1 << 10)
+#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT                               10
 #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                BITFIELD(10, 10)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT                        (1 << 1)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT                        1
 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT                        (1 << 1)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT                        1
 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_L4PER_GPIO3_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_L4PER_GPIO3_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_L4PER_GPIO4_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_L4PER_GPIO4_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_L4PER_GPIO5_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_L4PER_GPIO5_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_L4PER_GPIO6_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_L4PER_GPIO6_WKDEP */
-#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT                             (1 << 19)
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT                             19
 #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              BITFIELD(19, 19)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT                           (1 << 13)
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT                           13
 #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            BITFIELD(13, 13)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT                              (1 << 12)
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT                              12
 #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               BITFIELD(12, 12)
 
 /* Used by PM_DSS_DSS_WKDEP */
-#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT                            (1 << 14)
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT                            14
 #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             BITFIELD(14, 14)
 
 /* Used by PM_L4PER_HECC1_WKDEP */
-#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT                                0
 #define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 BITFIELD(0, 0)
 
 /* Used by PM_L4PER_HECC2_WKDEP */
-#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT                                0
 #define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT                            (1 << 6)
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT                            6
 #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             BITFIELD(6, 6)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT                           1
 #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT                              0
 #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               BITFIELD(0, 0)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT                            7
 #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             BITFIELD(7, 7)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT                          1
 #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
-#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT                            7
 #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             BITFIELD(7, 7)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT                          1
 #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
-#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT                            7
 #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             BITFIELD(7, 7)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT                          1
 #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
-#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT                            7
 #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             BITFIELD(7, 7)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT                          1
 #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
-#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_L4PER_I2C5_WKDEP */
-#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT                            7
 #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             BITFIELD(7, 7)
 
 /* Used by PM_L4PER_I2C5_WKDEP */
-#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_WKUP_KEYBOARD_WKDEP */
-#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                          7
 #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           BITFIELD(7, 7)
 
 /* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_ABE_MCASP_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT                         2
 #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          BITFIELD(2, 2)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                          7
 #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           BITFIELD(7, 7)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT                         2
 #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          BITFIELD(2, 2)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                          7
 #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           BITFIELD(7, 7)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT                         6
 #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          BITFIELD(6, 6)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                           0
 #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT                         2
 #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          BITFIELD(2, 2)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
-#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT                            1
 #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             BITFIELD(1, 1)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT                            1
 #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             BITFIELD(1, 1)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_L4PER_MCSPI3_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MCSPI3_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_L4PER_MCSPI4_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MCSPI4_WKDEP */
-#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT                              1
 #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT                                 0
 #define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT                                3
 #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 BITFIELD(3, 3)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
-#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT                               2
 #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                BITFIELD(2, 2)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT                              1
 #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT                                 0
 #define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT                                3
 #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 BITFIELD(3, 3)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
-#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT                               2
 #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                BITFIELD(2, 2)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT                              1
 #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT                                 0
 #define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
-#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT                               2
 #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                BITFIELD(2, 2)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT                            1
 #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             BITFIELD(1, 1)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT                            1
 #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             BITFIELD(1, 1)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT                            1
 #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             BITFIELD(1, 1)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
-#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT                              3
 #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               BITFIELD(3, 3)
 
 /* Used by PM_L3INIT_PCIESS_WKDEP */
-#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_PCIESS_WKDEP */
-#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT                             (1 << 7)
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT                             7
 #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              BITFIELD(7, 7)
 
 /* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT                            (1 << 6)
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT                            6
 #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             BITFIELD(6, 6)
 
 /* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT                              0
 #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               BITFIELD(0, 0)
 
 /* Used by PM_ABE_PDM_WKDEP */
-#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT                            (1 << 2)
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT                            2
 #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             BITFIELD(2, 2)
 
 /* Used by PM_WKUP_RTC_WKDEP */
-#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT                                  (1 << 0)
+#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT                                  0
 #define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_SATA_WKDEP */
-#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT                                 0
 #define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_SATA_WKDEP */
-#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT                               2
 #define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                BITFIELD(2, 2)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                        (1 << 7)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                        7
 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         BITFIELD(7, 7)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT                       (1 << 6)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT                       6
 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        BITFIELD(6, 6)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                         (1 << 0)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                         0
 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          BITFIELD(0, 0)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT                       (1 << 2)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT                       2
 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        BITFIELD(2, 2)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT                        (1 << 7)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT                        7
 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         BITFIELD(7, 7)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT                       (1 << 6)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT                       6
 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        BITFIELD(6, 6)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT                         (1 << 0)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT                         0
 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          BITFIELD(0, 0)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT                       (1 << 2)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT                       2
 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        BITFIELD(2, 2)
 
 /* Used by PM_ALWON_SR_CORE_WKDEP */
-#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT                           1
 #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            BITFIELD(1, 1)
 
 /* Used by PM_ALWON_SR_CORE_WKDEP */
-#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT                              0
 #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               BITFIELD(0, 0)
 
 /* Used by PM_ALWON_SR_IVA_WKDEP */
-#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT                            1
 #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             BITFIELD(1, 1)
 
 /* Used by PM_ALWON_SR_IVA_WKDEP */
-#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ALWON_SR_MPU_WKDEP */
-#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_WKUP_TIMER12_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT                              0
 #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               BITFIELD(0, 0)
 
 /* Used by PM_WKUP_TIMER1_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ABE_TIMER5_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ABE_TIMER5_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_ABE_TIMER6_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ABE_TIMER6_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_ABE_TIMER7_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ABE_TIMER7_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_ABE_TIMER8_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT                               0
 #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                BITFIELD(0, 0)
 
 /* Used by PM_ABE_TIMER8_WKDEP */
-#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT                             2
 #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              BITFIELD(2, 2)
 
 /* Used by PM_L4PER_UART1_WKDEP */
-#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT                                0
 #define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 BITFIELD(0, 0)
 
 /* Used by PM_L4PER_UART1_WKDEP */
-#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT                               3
 #define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                BITFIELD(3, 3)
 
 /* Used by PM_L4PER_UART2_WKDEP */
-#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT                                0
 #define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 BITFIELD(0, 0)
 
 /* Used by PM_L4PER_UART2_WKDEP */
-#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT                               3
 #define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                BITFIELD(3, 3)
 
 /* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT                             (1 << 1)
+#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT                             1
 #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              BITFIELD(1, 1)
 
 /* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT                                0
 #define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 BITFIELD(0, 0)
 
 /* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT                               3
 #define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                BITFIELD(3, 3)
 
 /* Used by PM_L4PER_UART3_WKDEP */
-#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT                              (1 << 2)
+#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT                              2
 #define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               BITFIELD(2, 2)
 
 /* Used by PM_L4PER_UART4_WKDEP */
-#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT                                0
 #define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 BITFIELD(0, 0)
 
 /* Used by PM_L4PER_UART4_WKDEP */
-#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT                               3
 #define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                BITFIELD(3, 3)
 
 /* Used by PM_L3INIT_UNIPRO1_WKDEP */
-#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT                           1
 #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_UNIPRO1_WKDEP */
-#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT                              0
 #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_USB_HOST_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT                          1
 #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT                       (1 << 1)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT                       1
 #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT                          (1 << 0)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT                          0
 #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_USB_HOST_WKDEP */
-#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT                             0
 #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_USB_OTG_WKDEP */
-#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT                           1
 #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_USB_OTG_WKDEP */
-#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT                              0
 #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_USB_TLL_WKDEP */
-#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT                           1
 #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            BITFIELD(1, 1)
 
 /* Used by PM_L3INIT_USB_TLL_WKDEP */
-#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT                              0
 #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               BITFIELD(0, 0)
 
 /* Used by PM_WKUP_USIM_WKDEP */
-#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT                                 0
 #define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  BITFIELD(0, 0)
 
 /* Used by PM_WKUP_USIM_WKDEP */
-#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT                                3
 #define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 BITFIELD(3, 3)
 
 /* Used by PM_WKUP_WDT2_WKDEP */
-#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT                              1
 #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               BITFIELD(1, 1)
 
 /* Used by PM_WKUP_WDT2_WKDEP */
-#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT                                 0
 #define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  BITFIELD(0, 0)
 
 /* Used by PM_ABE_WDT3_WKDEP */
-#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT                                 0
 #define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  BITFIELD(0, 0)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
-#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT                         (1 << 8)
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT                         8
 #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          BITFIELD(8, 8)
 
 /* Used by PM_L3INIT_XHPI_WKDEP */
-#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT                              1
 #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               BITFIELD(1, 1)
 
 /* Used by PRM_IO_PMCTRL */
-#define OMAP4430_WUCLK_CTRL_SHIFT                                       (1 << 8)
+#define OMAP4430_WUCLK_CTRL_SHIFT                                       8
 #define OMAP4430_WUCLK_CTRL_MASK                                        BITFIELD(8, 8)
 
 /* Used by PRM_IO_PMCTRL */
-#define OMAP4430_WUCLK_STATUS_SHIFT                                     (1 << 9)
+#define OMAP4430_WUCLK_STATUS_SHIFT                                     9
 #define OMAP4430_WUCLK_STATUS_MASK                                      BITFIELD(9, 9)
 #endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 40f006285163..5fba2aa8932c 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -179,9 +179,11 @@
 
 /* Registers appearing on both 24xx and 34xx */
 
-#define RM_RSTCTRL                                      0x0050
-#define RM_RSTTIME                                      0x0054
-#define RM_RSTST                                        0x0058
+#define OMAP2_RM_RSTCTRL                                0x0050
+#define OMAP2_RM_RSTTIME                                0x0054
+#define OMAP2_RM_RSTST                                  0x0058
+#define OMAP2_PM_PWSTCTRL                               0x00e0
+#define OMAP2_PM_PWSTST                                 0x00e4
 
 #define PM_WKEN                                         0x00a0
 #define PM_WKEN1                                        PM_WKEN
@@ -191,8 +193,6 @@
 #define PM_EVGENCTRL                                    0x00d4
 #define PM_EVGENONTIM                                   0x00d8
 #define PM_EVGENOFFTIM                                  0x00dc
-#define PM_PWSTCTRL                                     0x00e0
-#define PM_PWSTST                                       0x00e4
 
 /* Omap2 specific registers */
 #define OMAP24XX_PM_WKEN2                               0x00a4
@@ -220,6 +220,13 @@
 #define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
 #define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
 
+/* Omap4 specific registers */
+#define OMAP4_RM_RSTCTRL                                0x0000
+#define OMAP4_RM_RSTTIME                                0x0004
+#define OMAP4_RM_RSTST                                  0x0008
+#define OMAP4_PM_PWSTCTRL                               0x0000
+#define OMAP4_PM_PWSTST                                 0x0004
+
 
 #ifndef __ASSEMBLER__
 
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index c3626ea48143..22fcc14e63be 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -38,7 +38,7 @@
 #define PM_PREPWSTST_CORE_P     0x48306AE8
 #define PM_PREPWSTST_MPU_V      OMAP34XX_PRM_REGADDR(MPU_MOD, \
                                 OMAP3430_PM_PREPWSTST)
-#define PM_PWSTCTRL_MPU_P       OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
+#define PM_PWSTCTRL_MPU_P       OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
 #define CM_IDLEST1_CORE_V       OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
 #define SRAM_BASE_P             0x40200000
 #define CONTROL_STAT            0x480022F0
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index d9f8c844c385..0ae27538385d 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -173,7 +173,7 @@ EXPORT_SYMBOL(clk_get_parent);
  * OMAP specific clock functions shared between omap1 and omap2
  *-------------------------------------------------------------------------*/
 
-unsigned int __initdata mpurate;
+int __initdata mpurate;
 
 /*
  * By default we use the rate set by the bootloader.
@@ -199,6 +199,17 @@ unsigned long followparent_recalc(struct clk *clk)
         return clk->parent->rate;
 }
 
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+{
+        WARN_ON(!clk->fixed_div);
+
+        return clk->parent->rate / clk->fixed_div;
+}
+
 void clk_reparent(struct clk *child, struct clk *parent)
 {
         list_del_init(&child->sibling);
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 35b36caf5f91..bb937f3fabed 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -25,17 +25,25 @@ struct omap_clk {
                 },                      \
         }
 
-
+/* Platform flags for the clkdev-OMAP integration code */
 #define CK_310          (1 << 0)
-#define CK_7XX          (1 << 1)
+#define CK_7XX          (1 << 1)        /* 7xx, 850 */
 #define CK_1510         (1 << 2)
-#define CK_16XX         (1 << 3)
-#define CK_243X         (1 << 4)
-#define CK_242X         (1 << 5)
-#define CK_343X         (1 << 6)
-#define CK_3430ES1      (1 << 7)
-#define CK_3430ES2      (1 << 8)
-#define CK_443X         (1 << 9)
+#define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
+#define CK_242X         (1 << 4)
+#define CK_243X         (1 << 5)
+#define CK_3XXX         (1 << 6)        /* OMAP3 + AM3 common clocks*/
+#define CK_343X         (1 << 7)        /* OMAP34xx common clocks */
+#define CK_3430ES1      (1 << 8)        /* 34xxES1 only */
+#define CK_3430ES2      (1 << 9)        /* 34xxES2, ES3, non-Sitara 35xx only */
+#define CK_3505         (1 << 10)
+#define CK_3517         (1 << 11)
+#define CK_36XX         (1 << 12)       /* OMAP36xx/37xx-specific clocks */
+#define CK_443X         (1 << 13)
+
+#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
+
+
 
 #endif
 
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 94fe2a0ce40a..e41313208125 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -88,9 +88,9 @@ struct clk {
         void                    (*init)(struct clk *);
         __u8                    enable_bit;
         __s8                    usecount;
+        u8                      fixed_div;
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
                 defined(CONFIG_ARCH_OMAP4)
-        u8                      fixed_div;
         void __iomem            *clksel_reg;
         u32                     clksel_mask;
         const struct clksel     *clksel;
@@ -123,7 +123,7 @@ struct clk_functions {
 #endif
 };
 
-extern unsigned int mpurate;
+extern int mpurate;
 
 extern int clk_init(struct clk_functions *custom_clocks);
 extern void clk_preinit(struct clk *clk);
@@ -134,6 +134,7 @@ extern void propagate_rate(struct clk *clk);
 extern void recalculate_root_clocks(void);
 extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
+unsigned long omap_fixed_divisor_recalc(struct clk *clk);
 #ifdef CONFIG_CPU_FREQ
 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h
index eb734826e64e..ba0a6c07c0fe 100644
--- a/arch/arm/plat-omap/include/plat/clockdomain.h
+++ b/arch/arm/plat-omap/include/plat/clockdomain.h
@@ -4,7 +4,7 @@
  * OMAP2/3 clockdomain framework functions
  *
  * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -40,65 +40,95 @@
 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
 
-/*
- * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
- * and sleepdeps added when a powerdomain should stay active in hwsup mode;
- * and conversely, removed when the powerdomain should be allowed to go
- * inactive in hwsup mode.
+/**
+ * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
+ * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
+ * @omap_chip: OMAP chip types that this autodep is valid on
+ *
+ * A clockdomain that should have wkdeps and sleepdeps added when a
+ * clockdomain should stay active in hwsup mode; and conversely,
+ * removed when the clockdomain should be allowed to go inactive in
+ * hwsup mode.
+ *
+ * Autodeps are deprecated and should be removed after
+ * omap_hwmod-based fine-grained module idle control is added.
  */
-struct clkdm_pwrdm_autodep {
-
+struct clkdm_autodep {
         union {
-                /* Name of the powerdomain to add a wkdep/sleepdep on */
                 const char *name;
-
-                /* Powerdomain pointer (looked up at clkdm_init() time) */
-                struct powerdomain *ptr;
-        } pwrdm;
-
-        /* OMAP chip types that this clockdomain dep is valid on */
+                struct clockdomain *ptr;
+        } clkdm;
         const struct omap_chip_id omap_chip;
+};
 
+/**
+ * struct clkdm_dep - encode dependencies between clockdomains
+ * @clkdm_name: clockdomain name
+ * @clkdm: pointer to the struct clockdomain of @clkdm_name
+ * @omap_chip: OMAP chip types that this dependency is valid on
+ * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
+ * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
+ *
+ * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
+ * should not be pre-initialized.
+ *
+ * XXX Should also include hardware (fixed) dependencies.
+ */
+struct clkdm_dep {
+        const char *clkdm_name;
+        struct clockdomain *clkdm;
+        atomic_t wkdep_usecount;
+        atomic_t sleepdep_usecount;
+        const struct omap_chip_id omap_chip;
 };
 
+/**
+ * struct clockdomain - OMAP clockdomain
+ * @name: clockdomain name
+ * @pwrdm: powerdomain containing this clockdomain
+ * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
+ * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
+ * @flags: Clockdomain capability flags
+ * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
+ * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
+ * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
+ * @omap_chip: OMAP chip types that this clockdomain is valid on
+ * @usecount: Usecount tracking
+ * @node: list_head to link all clockdomains together
+ */
 struct clockdomain {
-
-        /* Clockdomain name */
         const char *name;
-
         union {
-                /* Powerdomain enclosing this clockdomain */
                 const char *name;
-
-                /* Powerdomain pointer assigned at clkdm_register() */
                 struct powerdomain *ptr;
         } pwrdm;
-
-        /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
+        void __iomem *clkstctrl_reg;
         const u16 clktrctrl_mask;
-
-        /* Clockdomain capability flags */
         const u8 flags;
-
-        /* OMAP chip types that this clockdomain is valid on */
+        const u8 dep_bit;
+        struct clkdm_dep *wkdep_srcs;
+        struct clkdm_dep *sleepdep_srcs;
         const struct omap_chip_id omap_chip;
-
-        /* Usecount tracking */
         atomic_t usecount;
-
         struct list_head node;
-
 };
 
-void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
-int clkdm_register(struct clockdomain *clkdm);
-int clkdm_unregister(struct clockdomain *clkdm);
+void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps);
 struct clockdomain *clkdm_lookup(const char *name);
 
 int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
                         void *user);
 struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
 
+int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
+int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+
 void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
 void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
 
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index a745d62fad0d..61e7b8a8c993 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -160,6 +160,14 @@
 #define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
 #define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
 
+/* AM35XX only CONTROL_GENERAL register offsets */
+#define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
+#define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
+#define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
+#define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
+#define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
+#define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
+#define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
 
 /* 34xx PADCONF register offsets */
 #define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
@@ -257,6 +265,15 @@
 #define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
 #define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
 
+/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
+#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
+#define AM35XX_USBOTG_FCLK_SHIFT        8
+#define AM35XX_CPGMAC_FCLK_SHIFT        9
+#define AM35XX_VPFE_FCLK_SHIFT          10
+
 /*
  * CONTROL OMAP STATUS register to identify OMAP3 features
  */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index a162f585b1e3..ccd78fd473d1 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -44,7 +44,7 @@
 int omap_type(void);
 
 struct omap_chip_id {
-        u8 oc;
+        u16 oc;
         u8 type;
 };
 
@@ -154,6 +154,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap242x():   True for OMAP2420, OMAP2422, OMAP2423
  * cpu_is_omap243x():   True for OMAP2430
  * cpu_is_omap343x():   True for OMAP3430
+ * cpu_is_omap443x():   True for OMAP4430
  */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
@@ -286,6 +287,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
  * cpu_is_omap2423():   True for OMAP2423
  * cpu_is_omap2430():   True for OMAP2430
  * cpu_is_omap3430():   True for OMAP3430
+ * cpu_is_omap4430():   True for OMAP4430
  * cpu_is_omap3505():   True for OMAP3505
  * cpu_is_omap3517():   True for OMAP3517
  */
@@ -334,6 +336,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define cpu_is_omap3505()               0
 #define cpu_is_omap3517()               0
 #define cpu_is_omap3430()               0
+#define cpu_is_omap4430()               0
 #define cpu_is_omap3630()               0
 
 /*
@@ -471,9 +474,12 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP3430ES3_0           (1 << 5)
 #define CHIP_IS_OMAP3430ES3_1           (1 << 6)
 #define CHIP_IS_OMAP3630ES1             (1 << 7)
+#define CHIP_IS_OMAP4430ES1             (1 << 8)
 
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1)
+
 /*
  * "GE" here represents "greater than or equal to" in terms of ES
  * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index dc1fac1d805c..76d49171fed9 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -131,11 +131,15 @@ int omap_device_enable_clocks(struct omap_device *od);
  */
 struct omap_device_pm_latency {
         u32 deactivate_lat;
+        u32 deactivate_lat_worst;
         int (*deactivate_func)(struct omap_device *od);
         u32 activate_lat;
+        u32 activate_lat_worst;
         int (*activate_func)(struct omap_device *od);
+        u32 flags;
 };
 
+#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
 
 /* Get omap_device pointer from platform_device pointer */
 #define to_omap_device(x) container_of((x), struct omap_device, pdev)
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 33933256a226..921990e2a29a 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -441,6 +441,8 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh);
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
 
+int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
+
 int omap_hwmod_reset(struct omap_hwmod *oh);
 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
 
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 0b960051eaed..e15c7e9da975 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -1,8 +1,8 @@
 /*
  * OMAP2/3 powerdomain control
  *
- * Copyright (C) 2007-8 Texas Instruments, Inc.
- * Copyright (C) 2007-8 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -37,6 +37,9 @@
 #define PWRSTS_OFF_RET          ((1 << PWRDM_POWER_OFF) | \
                                  (1 << PWRDM_POWER_RET))
 
+#define PWRSTS_RET_ON           ((1 << PWRDM_POWER_RET) | \
+                                 (1 << PWRDM_POWER_ON))
+
 #define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
 
 
@@ -48,16 +51,16 @@
                                           */
 
 /*
- * Number of memory banks that are power-controllable.  On OMAP3430, the
- * maximum is 4.
+ * Number of memory banks that are power-controllable.  On OMAP4430, the
+ * maximum is 5.
  */
-#define PWRDM_MAX_MEM_BANKS     4
+#define PWRDM_MAX_MEM_BANKS     5
 
 /*
  * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP3 is the worst case
+ * CORE powerdomain on OMAP4 is the worst case
  */
-#define PWRDM_MAX_CLKDMS        4
+#define PWRDM_MAX_CLKDMS        9
 
 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -65,63 +68,36 @@
 struct clockdomain;
 struct powerdomain;
 
-/* Encodes dependencies between powerdomains - statically defined */
-struct pwrdm_dep {
-
-        /* Powerdomain name */
-        const char *pwrdm_name;
-
-        /* Powerdomain pointer - resolved by the powerdomain code */
-        struct powerdomain *pwrdm;
-
-        /* Flags to mark OMAP chip restrictions, etc. */
-        const struct omap_chip_id omap_chip;
-
-};
-
+/**
+ * struct powerdomain - OMAP powerdomain
+ * @name: Powerdomain name
+ * @omap_chip: represents the OMAP chip types containing this pwrdm
+ * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ * @pwrsts: Possible powerdomain power states
+ * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
+ * @flags: Powerdomain flags
+ * @banks: Number of software-controllable memory banks in this powerdomain
+ * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
+ * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
+ * @pwrdm_clkdms: Clockdomains in this powerdomain
+ * @node: list_head linking all powerdomains
+ * @state:
+ * @state_counter:
+ * @timer:
+ * @state_timer:
+ */
 struct powerdomain {
-
-        /* Powerdomain name */
         const char *name;
-
-        /* the address offset from CM_BASE/PRM_BASE */
-        const s16 prcm_offs;
-
-        /* Used to represent the OMAP chip types containing this pwrdm */
         const struct omap_chip_id omap_chip;
-
-        /* Powerdomains that can be told to wake this powerdomain up */
-        struct pwrdm_dep *wkdep_srcs;
-
-        /* Powerdomains that can be told to keep this pwrdm from inactivity */
-        struct pwrdm_dep *sleepdep_srcs;
-
-        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
-        const u8 dep_bit;
-
-        /* Possible powerdomain power states */
+        const s16 prcm_offs;
         const u8 pwrsts;
-
-        /* Possible logic power states when pwrdm in RETENTION */
         const u8 pwrsts_logic_ret;
-
-        /* Powerdomain flags */
         const u8 flags;
-
-        /* Number of software-controllable memory banks in this powerdomain */
         const u8 banks;
-
-        /* Possible memory bank pwrstates when pwrdm in RETENTION */
         const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
-
-        /* Possible memory bank pwrstates when pwrdm is ON */
         const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
-
-        /* Clockdomains in this powerdomain */
         struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
-
         struct list_head node;
-
         int state;
         unsigned state_counter[PWRDM_MAX_PWRSTS];
 
@@ -134,8 +110,6 @@ struct powerdomain {
 
 void pwrdm_init(struct powerdomain **pwrdm_list);
 
-int pwrdm_register(struct powerdomain *pwrdm);
-int pwrdm_unregister(struct powerdomain *pwrdm);
 struct powerdomain *pwrdm_lookup(const char *name);
 
 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
@@ -149,13 +123,6 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
                          int (*fn)(struct powerdomain *pwrdm,
                                    struct clockdomain *clkdm));
 
-int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
-
 int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
 
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index e63e94e18975..66938a9f8dae 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -33,6 +33,14 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
 void omap3_prcm_save_context(void);
 void omap3_prcm_restore_context(void);
 
+u32 prm_read_mod_reg(s16 module, u16 idx);
+void prm_write_mod_reg(u32 val, s16 module, u16 idx);
+u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+u32 cm_read_mod_reg(s16 module, u16 idx);
+void cm_write_mod_reg(u32 val, s16 module, u16 idx);
+u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+
 #endif
 
 
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 1e5648d3e3d8..d8c75c8f78d7 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -148,10 +148,22 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                          "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          act_lat);
 
-                WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
-                     "activate step %d took longer than expected (%llu > %d)\n",
-                     od->pdev.name, od->pdev.id, od->pm_lat_level,
-                     act_lat, odpl->activate_lat);
+                if (act_lat > odpl->activate_lat) {
+                        odpl->activate_lat_worst = act_lat;
+                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
+                                odpl->activate_lat = act_lat;
+                                pr_warning("omap_device: %s.%d: new worst case "
+                                           "activate latency %d: %llu\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, act_lat);
+                        } else
+                                pr_warning("omap_device: %s.%d: activate "
+                                           "latency %d higher than exptected. "
+                                           "(%llu > %d)\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, act_lat,
+                                           odpl->activate_lat);
+                }
 
                 od->dev_wakeup_lat -= odpl->activate_lat;
         }
@@ -204,10 +216,23 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                          "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          deact_lat);
 
-                WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
-                     "deactivate step %d took longer than expected "
-                     "(%llu > %d)\n", od->pdev.name, od->pdev.id,
-                     od->pm_lat_level, deact_lat, odpl->deactivate_lat);
+                if (deact_lat > odpl->deactivate_lat) {
+                        odpl->deactivate_lat_worst = deact_lat;
+                        if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
+                                odpl->deactivate_lat = deact_lat;
+                                pr_warning("omap_device: %s.%d: new worst case "
+                                           "deactivate latency %d: %llu\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, deact_lat);
+                        } else
+                                pr_warning("omap_device: %s.%d: deactivate "
+                                           "latency %d higher than exptected. "
+                                           "(%llu > %d)\n",
+                                           od->pdev.name, od->pdev.id,
+                                           od->pm_lat_level, deact_lat,
+                                           odpl->deactivate_lat);
+                }
+
 
                 od->dev_wakeup_lat += odpl->activate_lat;