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authorGertjan van Wingerde <gwingerde@gmail.com>2010-04-11 08:31:12 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-04-12 15:22:12 -0400
commit8cdd15e0063edbe002945ba93faf80e79c947610 (patch)
treebaf54a9331b65274f32afa28b9b030ccaef25d4d
parenta9dce1494af33534867b8c7fab7351274fd651ca (diff)
rt2x00: Finish rt3070 support in rt2800 register initialization.
rt2x00 had preliminary support for RT3070 based devices, but the support was incomplete. Update the RT3070 register initialization to be similar to the latest Ralink vendor driver. With this patch my rt3070 based devices start showing a sign of life. Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c133
1 files changed, 71 insertions, 62 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 1890b9aea492..7d1cb7ea0952 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -1042,8 +1042,7 @@ EXPORT_SYMBOL_GPL(rt2800_link_stats);
1042static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 1042static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1043{ 1043{
1044 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 1044 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1045 if (rt2x00_is_usb(rt2x00dev) && 1045 if (rt2x00_rt(rt2x00dev, RT3070))
1046 rt2x00_rt_rev(rt2x00dev, RT3070, REV_RT3070E))
1047 return 0x1c + (2 * rt2x00dev->lna_gain); 1046 return 0x1c + (2 * rt2x00dev->lna_gain);
1048 else 1047 else
1049 return 0x2e + rt2x00dev->lna_gain; 1048 return 0x2e + rt2x00dev->lna_gain;
@@ -1191,11 +1190,16 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1191 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 1190 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1192 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 1191 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1193 1192
1194 if (rt2x00_is_usb(rt2x00dev) && 1193 if (rt2x00_rt(rt2x00dev, RT3070)) {
1195 rt2x00_rt_rev(rt2x00dev, RT3070, REV_RT3070E)) {
1196 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 1194 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1197 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 1195
1198 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 1196 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1197 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1198 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1199 } else {
1200 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1201 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1202 }
1199 } else { 1203 } else {
1200 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 1204 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1201 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 1205 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -1535,7 +1539,15 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1535 } 1539 }
1536 1540
1537 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1541 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1538 rt2800_bbp_write(rt2x00dev, 81, 0x37); 1542
1543 if (rt2x00_rt(rt2x00dev, RT3070)) {
1544 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1545 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1546 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1547 } else {
1548 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1549 }
1550
1539 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1551 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1540 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 1552 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1541 1553
@@ -1548,7 +1560,12 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1548 rt2800_bbp_write(rt2x00dev, 86, 0x00); 1560 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1549 rt2800_bbp_write(rt2x00dev, 91, 0x04); 1561 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1550 rt2800_bbp_write(rt2x00dev, 92, 0x00); 1562 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1551 rt2800_bbp_write(rt2x00dev, 103, 0x00); 1563
1564 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F))
1565 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1566 else
1567 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1568
1552 rt2800_bbp_write(rt2x00dev, 105, 0x05); 1569 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1553 rt2800_bbp_write(rt2x00dev, 106, 0x35); 1570 rt2800_bbp_write(rt2x00dev, 106, 0x35);
1554 1571
@@ -1558,13 +1575,6 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1558 rt2800_bbp_write(rt2x00dev, 80, 0x08); 1575 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1559 } 1576 }
1560 1577
1561 if (rt2x00_is_usb(rt2x00dev) &&
1562 rt2x00_rt_rev(rt2x00dev, RT3070, REV_RT3070E)) {
1563 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1564 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1565 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1566 }
1567
1568 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1578 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1569 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 1579 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1570 1580
@@ -1643,18 +1653,12 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1643{ 1653{
1644 u8 rfcsr; 1654 u8 rfcsr;
1645 u8 bbp; 1655 u8 bbp;
1656 u32 reg;
1657 u16 eeprom;
1646 1658
1647 if (rt2x00_is_usb(rt2x00dev) && 1659 if (!rt2x00_rt(rt2x00dev, RT3070))
1648 !rt2x00_rt_rev(rt2x00dev, RT3070, REV_RT3070E))
1649 return 0; 1660 return 0;
1650 1661
1651 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1652 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1653 !rt2x00_rf(rt2x00dev, RF3021) &&
1654 !rt2x00_rf(rt2x00dev, RF3022))
1655 return 0;
1656 }
1657
1658 /* 1662 /*
1659 * Init RF calibration. 1663 * Init RF calibration.
1660 */ 1664 */
@@ -1665,13 +1669,13 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1665 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 1669 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1666 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1670 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1667 1671
1668 if (rt2x00_is_usb(rt2x00dev)) { 1672 if (rt2x00_rt(rt2x00dev, RT3070)) {
1669 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1673 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1670 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1674 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1671 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1675 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1672 rt2800_rfcsr_write(rt2x00dev, 7, 0x70); 1676 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1673 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1677 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1674 rt2800_rfcsr_write(rt2x00dev, 10, 0x71); 1678 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1675 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1679 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1676 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 1680 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1677 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1681 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
@@ -1684,48 +1688,25 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1684 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1688 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1685 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 1689 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1686 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1690 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1687 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1688 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 1691 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1689 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) { 1692 }
1690 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 1693
1691 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 1694 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1692 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 1695 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1693 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 1696 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1694 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1697 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1695 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1698 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1696 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1697 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1698 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1699 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1700 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1701 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1702 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1703 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1704 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1705 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1706 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1707 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1708 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1709 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1710 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1711 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1712 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1713 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1714 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1715 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1716 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1717 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1718 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1719 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1720 } 1699 }
1721 1700
1722 /* 1701 /*
1723 * Set RX Filter calibration for 20MHz and 40MHz 1702 * Set RX Filter calibration for 20MHz and 40MHz
1724 */ 1703 */
1725 rt2x00dev->calibration[0] = 1704 if (rt2x00_rt(rt2x00dev, RT3070)) {
1726 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); 1705 rt2x00dev->calibration[0] =
1727 rt2x00dev->calibration[1] = 1706 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1728 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 1707 rt2x00dev->calibration[1] =
1708 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1709 }
1729 1710
1730 /* 1711 /*
1731 * Set back to initial state 1712 * Set back to initial state
@@ -1743,6 +1724,34 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1743 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 1724 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1744 rt2800_bbp_write(rt2x00dev, 4, bbp); 1725 rt2800_bbp_write(rt2x00dev, 4, bbp);
1745 1726
1727 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
1728 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1729
1730 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1731 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1732 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1733
1734 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1735 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1736 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1737 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1738 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1739 rt2x00_get_field16(eeprom,
1740 EEPROM_TXMIXER_GAIN_BG_VAL));
1741 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1742
1743 if (rt2x00_rt(rt2x00dev, RT3070)) {
1744 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
1745 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
1746 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1747 else
1748 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1749 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1750 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1751 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1752 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1753 }
1754
1746 return 0; 1755 return 0;
1747} 1756}
1748EXPORT_SYMBOL_GPL(rt2800_init_rfcsr); 1757EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);