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authorFrancois Romieu <romieu@fr.zoreil.com>2011-04-27 02:22:39 -0400
committerFrancois romieu <romieu@fr.zoreil.com>2011-05-09 15:03:10 -0400
commit85bffe6ca2e2d7e9510c115aa4f11c3d4209051f (patch)
treef18269a32218ab6eb9751e624c292194df6f2f99
parent31bd204f97e3796c5cfcfc582a93a10e45b99946 (diff)
r8169: merge firmware information into the chipset description data.
- RTL_GIGA_MAC_NONE is a fake index so put it at the end of the enumeration and shift everybody. - RTL_GIGA_MAC_VER_17 / RTL_GIGA_MAC_VER_16 ordering fixed. Though not wrong it was confusing enough to wonder if things were right. Renaming rtl_chip_info was not strictly necessary. It allows to check the patch for the correct use of the indexes though. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Realtek linux nic maintainers <nic_swsd@realtek.com>
Diffstat
-rw-r--r--drivers/net/r8169.c214
1 files changed, 110 insertions, 104 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 83e5202d30aa..4f1d45bd3303 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -98,40 +98,40 @@ static const int multicast_filter_limit = 32;
98#define RTL_R32(reg) readl (ioaddr + (reg)) 98#define RTL_R32(reg) readl (ioaddr + (reg))
99 99
100enum mac_version { 100enum mac_version {
101 RTL_GIGA_MAC_NONE = 0x00, 101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_01 = 0x01, // 8169 102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S 103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S 104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB 105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd 106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe 107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e 108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e 109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e 110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e 111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb 112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? 115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? 116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec 117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf 118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP 119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C 120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C 121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C 122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C 123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP 124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP 125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D 126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D 127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP 128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP 129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E 130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E 131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP 132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_32 = 0x20, // 8168E 133 RTL_GIGA_MAC_VER_33,
134 RTL_GIGA_MAC_VER_33 = 0x21, // 8168E 134 RTL_GIGA_MAC_NONE = 0xff,
135}; 135};
136 136
137enum rtl_tx_desc_version { 137enum rtl_tx_desc_version {
@@ -139,61 +139,84 @@ enum rtl_tx_desc_version {
139 RTL_TD_1 = 1, 139 RTL_TD_1 = 1,
140}; 140};
141 141
142#define _R(NAME,MAC,TD) \ 142#define _R(NAME,TD,FW) \
143 { .name = NAME, .mac_version = MAC, .txd_version = TD } 143 { .name = NAME, .txd_version = TD, .fw_name = FW }
144 144
145static const struct { 145static const struct {
146 const char *name; 146 const char *name;
147 u8 mac_version;
148 enum rtl_tx_desc_version txd_version; 147 enum rtl_tx_desc_version txd_version;
149} rtl_chip_info[] = {
150 _R("RTL8169", RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
151 _R("RTL8169s", RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
152 _R("RTL8110s", RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
153 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
154 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
155 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
156 _R("RTL8102e", RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
157 _R("RTL8102e", RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
158 _R("RTL8102e", RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
159 _R("RTL8101e", RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
160 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
161 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
162 _R("RTL8101e", RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
163 _R("RTL8100e", RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
164 _R("RTL8100e", RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
165 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
166 _R("RTL8101e", RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
167 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
168 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
169 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
170 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
171 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
172 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
173 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
174 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
175 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
176 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
177 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
178 _R("RTL8105e", RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
179 _R("RTL8105e", RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
180 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
181 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
182 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, RTL_TD_1) // PCI-E
183};
184#undef _R
185
186static const struct rtl_firmware_info {
187 int mac_version;
188 const char *fw_name; 148 const char *fw_name;
189} rtl_firmware_infos[] = { 149} rtl_chip_infos[] = {
190 { .mac_version = RTL_GIGA_MAC_VER_25, .fw_name = FIRMWARE_8168D_1 }, 150 /* PCI devices. */
191 { .mac_version = RTL_GIGA_MAC_VER_26, .fw_name = FIRMWARE_8168D_2 }, 151 [RTL_GIGA_MAC_VER_01] =
192 { .mac_version = RTL_GIGA_MAC_VER_29, .fw_name = FIRMWARE_8105E_1 }, 152 _R("RTL8169", RTL_TD_0, NULL),
193 { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 }, 153 [RTL_GIGA_MAC_VER_02] =
194 { .mac_version = RTL_GIGA_MAC_VER_32, .fw_name = FIRMWARE_8168E_1 }, 154 _R("RTL8169s", RTL_TD_0, NULL),
195 { .mac_version = RTL_GIGA_MAC_VER_33, .fw_name = FIRMWARE_8168E_2 } 155 [RTL_GIGA_MAC_VER_03] =
156 _R("RTL8110s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_04] =
158 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_05] =
160 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_06] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 /* PCI-E devices. */
164 [RTL_GIGA_MAC_VER_07] =
165 _R("RTL8102e", RTL_TD_1, NULL),
166 [RTL_GIGA_MAC_VER_08] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_09] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_10] =
171 _R("RTL8101e", RTL_TD_0, NULL),
172 [RTL_GIGA_MAC_VER_11] =
173 _R("RTL8168b/8111b", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_12] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_13] =
177 _R("RTL8101e", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_14] =
179 _R("RTL8100e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_15] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_16] =
183 _R("RTL8101e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_17] =
185 _R("RTL8168b/8111b", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_18] =
187 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
188 [RTL_GIGA_MAC_VER_19] =
189 _R("RTL8168c/8111c", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_20] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_21] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_22] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_23] =
197 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_24] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_25] =
201 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
202 [RTL_GIGA_MAC_VER_26] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
204 [RTL_GIGA_MAC_VER_27] =
205 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
206 [RTL_GIGA_MAC_VER_28] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_29] =
209 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
210 [RTL_GIGA_MAC_VER_30] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_31] =
213 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
214 [RTL_GIGA_MAC_VER_32] =
215 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
216 [RTL_GIGA_MAC_VER_33] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
196}; 218};
219#undef _R
197 220
198enum cfg_version { 221enum cfg_version {
199 RTL_CFG_0 = 0x00, 222 RTL_CFG_0 = 0x00,
@@ -1190,15 +1213,7 @@ static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1190 1213
1191static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) 1214static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1192{ 1215{
1193 int i; 1216 return rtl_chip_infos[tp->mac_version].fw_name;
1194
1195 for (i = 0; i < ARRAY_SIZE(rtl_firmware_infos); i++) {
1196 const struct rtl_firmware_info *info = rtl_firmware_infos + i;
1197
1198 if (info->mac_version == tp->mac_version)
1199 return info->fw_name;
1200 }
1201 return NULL;
1202} 1217}
1203 1218
1204static void rtl8169_get_drvinfo(struct net_device *dev, 1219static void rtl8169_get_drvinfo(struct net_device *dev,
@@ -3359,17 +3374,8 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3359 3374
3360 rtl8169_print_mac_version(tp); 3375 rtl8169_print_mac_version(tp);
3361 3376
3362 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { 3377 chipset = tp->mac_version;
3363 if (tp->mac_version == rtl_chip_info[i].mac_version) 3378 tp->txd_version = rtl_chip_infos[chipset].txd_version;
3364 break;
3365 }
3366 if (i == ARRAY_SIZE(rtl_chip_info)) {
3367 dev_err(&pdev->dev,
3368 "driver bug, MAC version not found in rtl_chip_info\n");
3369 goto err_out_msi_4;
3370 }
3371 chipset = i;
3372 tp->txd_version = rtl_chip_info[chipset].txd_version;
3373 3379
3374 RTL_W8(Cfg9346, Cfg9346_Unlock); 3380 RTL_W8(Cfg9346, Cfg9346_Unlock);
3375 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); 3381 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
@@ -3444,7 +3450,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3444 pci_set_drvdata(pdev, dev); 3450 pci_set_drvdata(pdev, dev);
3445 3451
3446 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", 3452 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3447 rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr, 3453 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3448 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); 3454 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3449 3455
3450 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || 3456 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-06 07:59:23 -0500