diff options
author | G, Manjunath Kondaiah <manjugk@ti.com> | 2010-12-20 21:27:18 -0500 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2010-12-20 21:38:29 -0500 |
commit | 745685df95961ebbf0bcafcf28f31217a75070ae (patch) | |
tree | 034c5e1d381979be706401691ea6a3e7ca41d708 | |
parent | d3c9be2f42223f256d06b2b69ed26afdcb02f64a (diff) |
OMAP2420: hwmod data: add system DMA
Add OMAP2420 DMA hwmod data and also add required
DMA device attributes.
Signed-off-by: G, Manjunath Kondaiah <manjugk@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_2420_data.c | 86 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/dma.h | 11 |
2 files changed, 97 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index d95342599793..42606f6b0cdf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
@@ -42,6 +42,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod; | |||
42 | static struct omap_hwmod omap2420_gpio2_hwmod; | 42 | static struct omap_hwmod omap2420_gpio2_hwmod; |
43 | static struct omap_hwmod omap2420_gpio3_hwmod; | 43 | static struct omap_hwmod omap2420_gpio3_hwmod; |
44 | static struct omap_hwmod omap2420_gpio4_hwmod; | 44 | static struct omap_hwmod omap2420_gpio4_hwmod; |
45 | static struct omap_hwmod omap2420_dma_system_hwmod; | ||
45 | 46 | ||
46 | /* L3 -> L4_CORE interface */ | 47 | /* L3 -> L4_CORE interface */ |
47 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { | 48 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
@@ -779,6 +780,88 @@ static struct omap_hwmod omap2420_gpio4_hwmod = { | |||
779 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 780 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
780 | }; | 781 | }; |
781 | 782 | ||
783 | /* system dma */ | ||
784 | static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { | ||
785 | .rev_offs = 0x0000, | ||
786 | .sysc_offs = 0x002c, | ||
787 | .syss_offs = 0x0028, | ||
788 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | ||
789 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | ||
790 | SYSC_HAS_AUTOIDLE), | ||
791 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
792 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
793 | }; | ||
794 | |||
795 | static struct omap_hwmod_class omap2420_dma_hwmod_class = { | ||
796 | .name = "dma", | ||
797 | .sysc = &omap2420_dma_sysc, | ||
798 | }; | ||
799 | |||
800 | /* dma attributes */ | ||
801 | static struct omap_dma_dev_attr dma_dev_attr = { | ||
802 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | ||
803 | IS_CSSA_32 | IS_CDSA_32, | ||
804 | .lch_count = 32, | ||
805 | }; | ||
806 | |||
807 | static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { | ||
808 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | ||
809 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | ||
810 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | ||
811 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | ||
812 | }; | ||
813 | |||
814 | static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { | ||
815 | { | ||
816 | .pa_start = 0x48056000, | ||
817 | .pa_end = 0x4a0560ff, | ||
818 | .flags = ADDR_TYPE_RT | ||
819 | }, | ||
820 | }; | ||
821 | |||
822 | /* dma_system -> L3 */ | ||
823 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { | ||
824 | .master = &omap2420_dma_system_hwmod, | ||
825 | .slave = &omap2420_l3_main_hwmod, | ||
826 | .clk = "core_l3_ck", | ||
827 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
828 | }; | ||
829 | |||
830 | /* dma_system master ports */ | ||
831 | static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { | ||
832 | &omap2420_dma_system__l3, | ||
833 | }; | ||
834 | |||
835 | /* l4_core -> dma_system */ | ||
836 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { | ||
837 | .master = &omap2420_l4_core_hwmod, | ||
838 | .slave = &omap2420_dma_system_hwmod, | ||
839 | .clk = "sdma_ick", | ||
840 | .addr = omap2420_dma_system_addrs, | ||
841 | .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs), | ||
842 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
843 | }; | ||
844 | |||
845 | /* dma_system slave ports */ | ||
846 | static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { | ||
847 | &omap2420_l4_core__dma_system, | ||
848 | }; | ||
849 | |||
850 | static struct omap_hwmod omap2420_dma_system_hwmod = { | ||
851 | .name = "dma", | ||
852 | .class = &omap2420_dma_hwmod_class, | ||
853 | .mpu_irqs = omap2420_dma_system_irqs, | ||
854 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs), | ||
855 | .main_clk = "core_l3_ck", | ||
856 | .slaves = omap2420_dma_system_slaves, | ||
857 | .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), | ||
858 | .masters = omap2420_dma_system_masters, | ||
859 | .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), | ||
860 | .dev_attr = &dma_dev_attr, | ||
861 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
862 | .flags = HWMOD_NO_IDLEST, | ||
863 | }; | ||
864 | |||
782 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { | 865 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
783 | &omap2420_l3_main_hwmod, | 866 | &omap2420_l3_main_hwmod, |
784 | &omap2420_l4_core_hwmod, | 867 | &omap2420_l4_core_hwmod, |
@@ -797,6 +880,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { | |||
797 | &omap2420_gpio2_hwmod, | 880 | &omap2420_gpio2_hwmod, |
798 | &omap2420_gpio3_hwmod, | 881 | &omap2420_gpio3_hwmod, |
799 | &omap2420_gpio4_hwmod, | 882 | &omap2420_gpio4_hwmod, |
883 | |||
884 | /* dma_system class*/ | ||
885 | &omap2420_dma_system_hwmod, | ||
800 | NULL, | 886 | NULL, |
801 | }; | 887 | }; |
802 | 888 | ||
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 23783990eb9a..c4665669a8a3 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h | |||
@@ -295,6 +295,13 @@ | |||
295 | #define DMA_ERRATA_3_3 BIT(0x5) | 295 | #define DMA_ERRATA_3_3 BIT(0x5) |
296 | #define DMA_ROMCODE_BUG BIT(0x6) | 296 | #define DMA_ROMCODE_BUG BIT(0x6) |
297 | 297 | ||
298 | /* Attributes for OMAP DMA Contrller */ | ||
299 | #define DMA_LINKED_LCH BIT(0x0) | ||
300 | #define GLOBAL_PRIORITY BIT(0x1) | ||
301 | #define RESERVE_CHANNEL BIT(0x2) | ||
302 | #define IS_CSSA_32 BIT(0x3) | ||
303 | #define IS_CDSA_32 BIT(0x4) | ||
304 | |||
298 | enum omap_reg_offsets { | 305 | enum omap_reg_offsets { |
299 | 306 | ||
300 | GCR, GSCR, GRST1, HW_ID, | 307 | GCR, GSCR, GRST1, HW_ID, |
@@ -389,6 +396,10 @@ struct omap_dma_channel_params { | |||
389 | #endif | 396 | #endif |
390 | }; | 397 | }; |
391 | 398 | ||
399 | struct omap_dma_dev_attr { | ||
400 | u32 dev_caps; | ||
401 | u16 lch_count; | ||
402 | }; | ||
392 | 403 | ||
393 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); | 404 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); |
394 | extern int omap_request_dma(int dev_id, const char *dev_name, | 405 | extern int omap_request_dma(int dev_id, const char *dev_name, |