diff options
| author | Dave Olson <dave.olson@qlogic.com> | 2008-01-09 02:16:17 -0500 |
|---|---|---|
| committer | Roland Dreier <rolandd@cisco.com> | 2008-01-25 17:15:44 -0500 |
| commit | 7387273307139ebf8d7f7fb3bb79d1ca48bd71d6 (patch) | |
| tree | 9d65581f68a0dd14589053aaafffa155193e5bf1 | |
| parent | 2ec8e662416cc9a171cdfe3d75e1ff00ba757859 (diff) | |
IB/ipath: Remove unused MDIO interface code
This code has been unused for some time, but still had leftovers
from when it was used.
Signed-off-by: Dave Olson <dave.olson@qlogic.com
Signed-off-by: Roland Dreier <rolandd@cisco.com>
| -rw-r--r-- | drivers/infiniband/hw/ipath/ipath_driver.c | 71 | ||||
| -rw-r--r-- | drivers/infiniband/hw/ipath/ipath_iba6110.c | 28 | ||||
| -rw-r--r-- | drivers/infiniband/hw/ipath/ipath_iba6120.c | 26 | ||||
| -rw-r--r-- | drivers/infiniband/hw/ipath/ipath_kernel.h | 29 | ||||
| -rw-r--r-- | drivers/infiniband/hw/ipath/ipath_registers.h | 16 |
5 files changed, 2 insertions, 168 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_driver.c b/drivers/infiniband/hw/ipath/ipath_driver.c index 5a9dc317f40a..bfcdf8c254c5 100644 --- a/drivers/infiniband/hw/ipath/ipath_driver.c +++ b/drivers/infiniband/hw/ipath/ipath_driver.c | |||
| @@ -1618,77 +1618,6 @@ bail: | |||
| 1618 | return ret; | 1618 | return ret; |
| 1619 | } | 1619 | } |
| 1620 | 1620 | ||
| 1621 | int ipath_waitfor_complete(struct ipath_devdata *dd, ipath_kreg reg_id, | ||
| 1622 | u64 bits_to_wait_for, u64 * valp) | ||
| 1623 | { | ||
| 1624 | unsigned long timeout; | ||
| 1625 | u64 lastval, val; | ||
| 1626 | int ret; | ||
| 1627 | |||
| 1628 | lastval = ipath_read_kreg64(dd, reg_id); | ||
| 1629 | /* wait a ridiculously long time */ | ||
| 1630 | timeout = jiffies + msecs_to_jiffies(5); | ||
| 1631 | do { | ||
| 1632 | val = ipath_read_kreg64(dd, reg_id); | ||
| 1633 | /* set so they have something, even on failures. */ | ||
| 1634 | *valp = val; | ||
| 1635 | if ((val & bits_to_wait_for) == bits_to_wait_for) { | ||
| 1636 | ret = 0; | ||
| 1637 | break; | ||
| 1638 | } | ||
| 1639 | if (val != lastval) | ||
| 1640 | ipath_cdbg(VERBOSE, "Changed from %llx to %llx, " | ||
| 1641 | "waiting for %llx bits\n", | ||
| 1642 | (unsigned long long) lastval, | ||
| 1643 | (unsigned long long) val, | ||
| 1644 | (unsigned long long) bits_to_wait_for); | ||
| 1645 | cond_resched(); | ||
| 1646 | if (time_after(jiffies, timeout)) { | ||
| 1647 | ipath_dbg("Didn't get bits %llx in register 0x%x, " | ||
| 1648 | "got %llx\n", | ||
| 1649 | (unsigned long long) bits_to_wait_for, | ||
| 1650 | reg_id, (unsigned long long) *valp); | ||
| 1651 | ret = -ENODEV; | ||
| 1652 | break; | ||
| 1653 | } | ||
| 1654 | } while (1); | ||
| 1655 | |||
| 1656 | return ret; | ||
| 1657 | } | ||
| 1658 | |||
| 1659 | /** | ||
| 1660 | * ipath_waitfor_mdio_cmdready - wait for last command to complete | ||
| 1661 | * @dd: the infinipath device | ||
| 1662 | * | ||
| 1663 | * Like ipath_waitfor_complete(), but we wait for the CMDVALID bit to go | ||
| 1664 | * away indicating the last command has completed. It doesn't return data | ||
| 1665 | */ | ||
| 1666 | int ipath_waitfor_mdio_cmdready(struct ipath_devdata *dd) | ||
| 1667 | { | ||
| 1668 | unsigned long timeout; | ||
| 1669 | u64 val; | ||
| 1670 | int ret; | ||
| 1671 | |||
| 1672 | /* wait a ridiculously long time */ | ||
| 1673 | timeout = jiffies + msecs_to_jiffies(5); | ||
| 1674 | do { | ||
| 1675 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_mdio); | ||
| 1676 | if (!(val & IPATH_MDIO_CMDVALID)) { | ||
| 1677 | ret = 0; | ||
| 1678 | break; | ||
| 1679 | } | ||
| 1680 | cond_resched(); | ||
| 1681 | if (time_after(jiffies, timeout)) { | ||
| 1682 | ipath_dbg("CMDVALID stuck in mdio reg? (%llx)\n", | ||
| 1683 | (unsigned long long) val); | ||
| 1684 | ret = -ENODEV; | ||
| 1685 | break; | ||
| 1686 | } | ||
| 1687 | } while (1); | ||
| 1688 | |||
| 1689 | return ret; | ||
| 1690 | } | ||
| 1691 | |||
| 1692 | 1621 | ||
| 1693 | /* | 1622 | /* |
| 1694 | * Flush all sends that might be in the ready to send state, as well as any | 1623 | * Flush all sends that might be in the ready to send state, as well as any |
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6110.c b/drivers/infiniband/hw/ipath/ipath_iba6110.c index 6976d96f6ce1..ac436c630bcc 100644 --- a/drivers/infiniband/hw/ipath/ipath_iba6110.c +++ b/drivers/infiniband/hw/ipath/ipath_iba6110.c | |||
| @@ -1274,8 +1274,7 @@ static void ipath_ht_init_hwerrors(struct ipath_devdata *dd) | |||
| 1274 | val &= ~INFINIPATH_HWE_HTCMISCERR4; | 1274 | val &= ~INFINIPATH_HWE_HTCMISCERR4; |
| 1275 | 1275 | ||
| 1276 | /* | 1276 | /* |
| 1277 | * PLL ignored because MDIO interface has a logic problem | 1277 | * PLL ignored because unused MDIO interface has a logic problem |
| 1278 | * for reads, on Comstock and Ponderosa. BRINGUP | ||
| 1279 | */ | 1278 | */ |
| 1280 | if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9) | 1279 | if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9) |
| 1281 | val &= ~INFINIPATH_HWE_SERDESPLLFAILED; | 1280 | val &= ~INFINIPATH_HWE_SERDESPLLFAILED; |
| @@ -1353,16 +1352,6 @@ static int ipath_ht_bringup_serdes(struct ipath_devdata *dd) | |||
| 1353 | } | 1352 | } |
| 1354 | 1353 | ||
| 1355 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); | 1354 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); |
| 1356 | if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) & | ||
| 1357 | INFINIPATH_XGXS_MDIOADDR_MASK) != 3) { | ||
| 1358 | val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK << | ||
| 1359 | INFINIPATH_XGXS_MDIOADDR_SHIFT); | ||
| 1360 | /* | ||
| 1361 | * we use address 3 | ||
| 1362 | */ | ||
| 1363 | val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT; | ||
| 1364 | change = 1; | ||
| 1365 | } | ||
| 1366 | if (val & INFINIPATH_XGXS_RESET) { | 1355 | if (val & INFINIPATH_XGXS_RESET) { |
| 1367 | /* normally true after boot */ | 1356 | /* normally true after boot */ |
| 1368 | val &= ~INFINIPATH_XGXS_RESET; | 1357 | val &= ~INFINIPATH_XGXS_RESET; |
| @@ -1398,21 +1387,6 @@ static int ipath_ht_bringup_serdes(struct ipath_devdata *dd) | |||
| 1398 | (unsigned long long) | 1387 | (unsigned long long) |
| 1399 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); | 1388 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); |
| 1400 | 1389 | ||
| 1401 | if (!ipath_waitfor_mdio_cmdready(dd)) { | ||
| 1402 | ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio, | ||
| 1403 | ipath_mdio_req(IPATH_MDIO_CMD_READ, 31, | ||
| 1404 | IPATH_MDIO_CTRL_XGXS_REG_8, | ||
| 1405 | 0)); | ||
| 1406 | if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio, | ||
| 1407 | IPATH_MDIO_DATAVALID, &val)) | ||
| 1408 | ipath_dbg("Never got MDIO data for XGXS status " | ||
| 1409 | "read\n"); | ||
| 1410 | else | ||
| 1411 | ipath_cdbg(VERBOSE, "MDIO Read reg8, " | ||
| 1412 | "'bank' 31 %x\n", (u32) val); | ||
| 1413 | } else | ||
| 1414 | ipath_dbg("Never got MDIO cmdready for XGXS status read\n"); | ||
| 1415 | |||
| 1416 | return ret; /* for now, say we always succeeded */ | 1390 | return ret; /* for now, say we always succeeded */ |
| 1417 | } | 1391 | } |
| 1418 | 1392 | ||
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6120.c b/drivers/infiniband/hw/ipath/ipath_iba6120.c index 066a8ea4b4df..57915fd718e2 100644 --- a/drivers/infiniband/hw/ipath/ipath_iba6120.c +++ b/drivers/infiniband/hw/ipath/ipath_iba6120.c | |||
| @@ -725,17 +725,8 @@ static int ipath_pe_bringup_serdes(struct ipath_devdata *dd) | |||
| 725 | 725 | ||
| 726 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); | 726 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); |
| 727 | prev_val = val; | 727 | prev_val = val; |
| 728 | if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) & | 728 | if (val & INFINIPATH_XGXS_RESET) |
| 729 | INFINIPATH_XGXS_MDIOADDR_MASK) != 3) { | ||
| 730 | val &= | ||
| 731 | ~(INFINIPATH_XGXS_MDIOADDR_MASK << | ||
| 732 | INFINIPATH_XGXS_MDIOADDR_SHIFT); | ||
| 733 | /* MDIO address 3 */ | ||
| 734 | val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT; | ||
| 735 | } | ||
| 736 | if (val & INFINIPATH_XGXS_RESET) { | ||
| 737 | val &= ~INFINIPATH_XGXS_RESET; | 729 | val &= ~INFINIPATH_XGXS_RESET; |
| 738 | } | ||
| 739 | if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) & | 730 | if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) & |
| 740 | INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) { | 731 | INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) { |
| 741 | /* need to compensate for Tx inversion in partner */ | 732 | /* need to compensate for Tx inversion in partner */ |
| @@ -765,21 +756,6 @@ static int ipath_pe_bringup_serdes(struct ipath_devdata *dd) | |||
| 765 | (unsigned long long) | 756 | (unsigned long long) |
| 766 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); | 757 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); |
| 767 | 758 | ||
| 768 | if (!ipath_waitfor_mdio_cmdready(dd)) { | ||
| 769 | ipath_write_kreg( | ||
| 770 | dd, dd->ipath_kregs->kr_mdio, | ||
| 771 | ipath_mdio_req(IPATH_MDIO_CMD_READ, 31, | ||
| 772 | IPATH_MDIO_CTRL_XGXS_REG_8, 0)); | ||
| 773 | if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio, | ||
| 774 | IPATH_MDIO_DATAVALID, &val)) | ||
| 775 | ipath_dbg("Never got MDIO data for XGXS " | ||
| 776 | "status read\n"); | ||
| 777 | else | ||
| 778 | ipath_cdbg(VERBOSE, "MDIO Read reg8, " | ||
| 779 | "'bank' 31 %x\n", (u32) val); | ||
| 780 | } else | ||
| 781 | ipath_dbg("Never got MDIO cmdready for XGXS status read\n"); | ||
| 782 | |||
| 783 | return ret; | 759 | return ret; |
| 784 | } | 760 | } |
| 785 | 761 | ||
diff --git a/drivers/infiniband/hw/ipath/ipath_kernel.h b/drivers/infiniband/hw/ipath/ipath_kernel.h index c47290422457..c0ecda35f2d9 100644 --- a/drivers/infiniband/hw/ipath/ipath_kernel.h +++ b/drivers/infiniband/hw/ipath/ipath_kernel.h | |||
| @@ -777,8 +777,6 @@ int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv); | |||
| 777 | 777 | ||
| 778 | /* free up any allocated data at closes */ | 778 | /* free up any allocated data at closes */ |
| 779 | void ipath_free_data(struct ipath_portdata *dd); | 779 | void ipath_free_data(struct ipath_portdata *dd); |
| 780 | int ipath_waitfor_mdio_cmdready(struct ipath_devdata *); | ||
| 781 | int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *); | ||
| 782 | u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *); | 780 | u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *); |
| 783 | void ipath_init_iba6120_funcs(struct ipath_devdata *); | 781 | void ipath_init_iba6120_funcs(struct ipath_devdata *); |
| 784 | void ipath_init_iba6110_funcs(struct ipath_devdata *); | 782 | void ipath_init_iba6110_funcs(struct ipath_devdata *); |
| @@ -802,33 +800,6 @@ void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val); | |||
| 802 | */ | 800 | */ |
| 803 | #define IPATH_DFLT_RCVHDRSIZE 9 | 801 | #define IPATH_DFLT_RCVHDRSIZE 9 |
| 804 | 802 | ||
| 805 | #define IPATH_MDIO_CMD_WRITE 1 | ||
| 806 | #define IPATH_MDIO_CMD_READ 2 | ||
| 807 | #define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */ | ||
| 808 | #define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */ | ||
| 809 | #define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */ | ||
| 810 | #define IPATH_MDIO_CTRL_STD 0x0 | ||
| 811 | |||
| 812 | static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data) | ||
| 813 | { | ||
| 814 | return (((u64) IPATH_MDIO_CLD_DIV) << 32) | | ||
| 815 | (cmd << 26) | | ||
| 816 | (dev << 21) | | ||
| 817 | (reg << 16) | | ||
| 818 | (data & 0xFFFF); | ||
| 819 | } | ||
| 820 | |||
| 821 | /* signal and fifo status, in bank 31 */ | ||
| 822 | #define IPATH_MDIO_CTRL_XGXS_REG_8 0x8 | ||
| 823 | /* controls loopback, redundancy */ | ||
| 824 | #define IPATH_MDIO_CTRL_8355_REG_1 0x10 | ||
| 825 | /* premph, encdec, etc. */ | ||
| 826 | #define IPATH_MDIO_CTRL_8355_REG_2 0x11 | ||
| 827 | /* Kchars, etc. */ | ||
| 828 | #define IPATH_MDIO_CTRL_8355_REG_6 0x15 | ||
| 829 | #define IPATH_MDIO_CTRL_8355_REG_9 0x18 | ||
| 830 | #define IPATH_MDIO_CTRL_8355_REG_10 0x1D | ||
| 831 | |||
| 832 | int ipath_get_user_pages(unsigned long, size_t, struct page **); | 803 | int ipath_get_user_pages(unsigned long, size_t, struct page **); |
| 833 | void ipath_release_user_pages(struct page **, size_t); | 804 | void ipath_release_user_pages(struct page **, size_t); |
| 834 | void ipath_release_user_pages_on_close(struct page **, size_t); | 805 | void ipath_release_user_pages_on_close(struct page **, size_t); |
diff --git a/drivers/infiniband/hw/ipath/ipath_registers.h b/drivers/infiniband/hw/ipath/ipath_registers.h index 156ef1473466..6d2a17f9c1da 100644 --- a/drivers/infiniband/hw/ipath/ipath_registers.h +++ b/drivers/infiniband/hw/ipath/ipath_registers.h | |||
| @@ -271,20 +271,6 @@ | |||
| 271 | #define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL | 271 | #define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL |
| 272 | #define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL | 272 | #define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL |
| 273 | 273 | ||
| 274 | /* kr_mdio bits */ | ||
| 275 | #define INFINIPATH_MDIO_CLKDIV_MASK 0x7FULL | ||
| 276 | #define INFINIPATH_MDIO_CLKDIV_SHIFT 32 | ||
| 277 | #define INFINIPATH_MDIO_COMMAND_MASK 0x7ULL | ||
| 278 | #define INFINIPATH_MDIO_COMMAND_SHIFT 26 | ||
| 279 | #define INFINIPATH_MDIO_DEVADDR_MASK 0x1FULL | ||
| 280 | #define INFINIPATH_MDIO_DEVADDR_SHIFT 21 | ||
| 281 | #define INFINIPATH_MDIO_REGADDR_MASK 0x1FULL | ||
| 282 | #define INFINIPATH_MDIO_REGADDR_SHIFT 16 | ||
| 283 | #define INFINIPATH_MDIO_DATA_MASK 0xFFFFULL | ||
| 284 | #define INFINIPATH_MDIO_DATA_SHIFT 0 | ||
| 285 | #define INFINIPATH_MDIO_CMDVALID 0x0000000040000000ULL | ||
| 286 | #define INFINIPATH_MDIO_RDDATAVALID 0x0000000080000000ULL | ||
| 287 | |||
| 288 | /* kr_partitionkey bits */ | 274 | /* kr_partitionkey bits */ |
| 289 | #define INFINIPATH_PKEY_SIZE 16 | 275 | #define INFINIPATH_PKEY_SIZE 16 |
| 290 | #define INFINIPATH_PKEY_MASK 0xFFFF | 276 | #define INFINIPATH_PKEY_MASK 0xFFFF |
| @@ -302,8 +288,6 @@ | |||
| 302 | 288 | ||
| 303 | /* kr_xgxsconfig bits */ | 289 | /* kr_xgxsconfig bits */ |
| 304 | #define INFINIPATH_XGXS_RESET 0x7ULL | 290 | #define INFINIPATH_XGXS_RESET 0x7ULL |
| 305 | #define INFINIPATH_XGXS_MDIOADDR_MASK 0xfULL | ||
| 306 | #define INFINIPATH_XGXS_MDIOADDR_SHIFT 4 | ||
| 307 | #define INFINIPATH_XGXS_RX_POL_SHIFT 19 | 291 | #define INFINIPATH_XGXS_RX_POL_SHIFT 19 |
| 308 | #define INFINIPATH_XGXS_RX_POL_MASK 0xfULL | 292 | #define INFINIPATH_XGXS_RX_POL_MASK 0xfULL |
| 309 | 293 | ||
