aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2011-02-12 00:09:04 -0500
committerDavid S. Miller <davem@davemloft.net>2011-02-12 00:09:04 -0500
commit58bb4bd0e0b1ab560a7320a760141ba52db68791 (patch)
tree47ca0cfe15778e851c7515e5eac1f9df0593c90c
parentdd68153def6b890a23288776cbd5bd2bad223a3f (diff)
parent1b1c0a489c1dcc1fa640c13404ca69e7beae07d9 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/jkirsher/net-next-2.6
-rw-r--r--drivers/net/e1000e/ethtool.c13
-rw-r--r--drivers/net/e1000e/netdev.c8
-rw-r--r--drivers/net/igb/e1000_82575.c10
-rw-r--r--drivers/net/igb/e1000_mbx.c38
-rw-r--r--drivers/net/igb/igb_main.c9
-rw-r--r--drivers/net/ixgbe/ixgbe.h5
-rw-r--r--drivers/net/ixgbe/ixgbe_common.h4
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.c177
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.h10
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82598.c94
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82598.h23
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.c115
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.h24
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_nl.c211
-rw-r--r--drivers/net/ixgbe/ixgbe_ethtool.c34
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c22
-rw-r--r--drivers/net/ixgbe/ixgbe_mbx.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_mbx.h2
-rw-r--r--include/linux/dcbnl.h5
19 files changed, 605 insertions, 201 deletions
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c
index daa7fe4b9fdd..65ef9b5548d8 100644
--- a/drivers/net/e1000e/ethtool.c
+++ b/drivers/net/e1000e/ethtool.c
@@ -1963,8 +1963,15 @@ static int e1000_set_coalesce(struct net_device *netdev,
1963static int e1000_nway_reset(struct net_device *netdev) 1963static int e1000_nway_reset(struct net_device *netdev)
1964{ 1964{
1965 struct e1000_adapter *adapter = netdev_priv(netdev); 1965 struct e1000_adapter *adapter = netdev_priv(netdev);
1966 if (netif_running(netdev)) 1966
1967 e1000e_reinit_locked(adapter); 1967 if (!netif_running(netdev))
1968 return -EAGAIN;
1969
1970 if (!adapter->hw.mac.autoneg)
1971 return -EINVAL;
1972
1973 e1000e_reinit_locked(adapter);
1974
1968 return 0; 1975 return 0;
1969} 1976}
1970 1977
@@ -2006,7 +2013,7 @@ static void e1000_get_strings(struct net_device *netdev, u32 stringset,
2006 2013
2007 switch (stringset) { 2014 switch (stringset) {
2008 case ETH_SS_TEST: 2015 case ETH_SS_TEST:
2009 memcpy(data, *e1000_gstrings_test, sizeof(e1000_gstrings_test)); 2016 memcpy(data, e1000_gstrings_test, sizeof(e1000_gstrings_test));
2010 break; 2017 break;
2011 case ETH_SS_STATS: 2018 case ETH_SS_STATS:
2012 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) { 2019 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 6025d5fb12a4..7cedfeb505b2 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -1843,7 +1843,9 @@ static int e1000_request_msix(struct e1000_adapter *adapter)
1843 int err = 0, vector = 0; 1843 int err = 0, vector = 0;
1844 1844
1845 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 1845 if (strlen(netdev->name) < (IFNAMSIZ - 5))
1846 sprintf(adapter->rx_ring->name, "%s-rx-0", netdev->name); 1846 snprintf(adapter->rx_ring->name,
1847 sizeof(adapter->rx_ring->name) - 1,
1848 "%s-rx-0", netdev->name);
1847 else 1849 else
1848 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); 1850 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1849 err = request_irq(adapter->msix_entries[vector].vector, 1851 err = request_irq(adapter->msix_entries[vector].vector,
@@ -1856,7 +1858,9 @@ static int e1000_request_msix(struct e1000_adapter *adapter)
1856 vector++; 1858 vector++;
1857 1859
1858 if (strlen(netdev->name) < (IFNAMSIZ - 5)) 1860 if (strlen(netdev->name) < (IFNAMSIZ - 5))
1859 sprintf(adapter->tx_ring->name, "%s-tx-0", netdev->name); 1861 snprintf(adapter->tx_ring->name,
1862 sizeof(adapter->tx_ring->name) - 1,
1863 "%s-tx-0", netdev->name);
1860 else 1864 else
1861 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); 1865 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
1862 err = request_irq(adapter->msix_entries[vector].vector, 1866 err = request_irq(adapter->msix_entries[vector].vector,
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index c1552b6f4a68..65c1833244f7 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -238,9 +238,15 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
238 size = 14; 238 size = 14;
239 nvm->word_size = 1 << size; 239 nvm->word_size = 1 << size;
240 240
241 /* if 82576 then initialize mailbox parameters */ 241 /* if part supports SR-IOV then initialize mailbox parameters */
242 if (mac->type == e1000_82576) 242 switch (mac->type) {
243 case e1000_82576:
244 case e1000_i350:
243 igb_init_mbx_params_pf(hw); 245 igb_init_mbx_params_pf(hw);
246 break;
247 default:
248 break;
249 }
244 250
245 /* setup PHY parameters */ 251 /* setup PHY parameters */
246 if (phy->media_type != e1000_media_type_copper) { 252 if (phy->media_type != e1000_media_type_copper) {
diff --git a/drivers/net/igb/e1000_mbx.c b/drivers/net/igb/e1000_mbx.c
index c474cdb70047..78d48c7fa859 100644
--- a/drivers/net/igb/e1000_mbx.c
+++ b/drivers/net/igb/e1000_mbx.c
@@ -422,26 +422,24 @@ s32 igb_init_mbx_params_pf(struct e1000_hw *hw)
422{ 422{
423 struct e1000_mbx_info *mbx = &hw->mbx; 423 struct e1000_mbx_info *mbx = &hw->mbx;
424 424
425 if (hw->mac.type == e1000_82576) { 425 mbx->timeout = 0;
426 mbx->timeout = 0; 426 mbx->usec_delay = 0;
427 mbx->usec_delay = 0; 427
428 428 mbx->size = E1000_VFMAILBOX_SIZE;
429 mbx->size = E1000_VFMAILBOX_SIZE; 429
430 430 mbx->ops.read = igb_read_mbx_pf;
431 mbx->ops.read = igb_read_mbx_pf; 431 mbx->ops.write = igb_write_mbx_pf;
432 mbx->ops.write = igb_write_mbx_pf; 432 mbx->ops.read_posted = igb_read_posted_mbx;
433 mbx->ops.read_posted = igb_read_posted_mbx; 433 mbx->ops.write_posted = igb_write_posted_mbx;
434 mbx->ops.write_posted = igb_write_posted_mbx; 434 mbx->ops.check_for_msg = igb_check_for_msg_pf;
435 mbx->ops.check_for_msg = igb_check_for_msg_pf; 435 mbx->ops.check_for_ack = igb_check_for_ack_pf;
436 mbx->ops.check_for_ack = igb_check_for_ack_pf; 436 mbx->ops.check_for_rst = igb_check_for_rst_pf;
437 mbx->ops.check_for_rst = igb_check_for_rst_pf; 437
438 438 mbx->stats.msgs_tx = 0;
439 mbx->stats.msgs_tx = 0; 439 mbx->stats.msgs_rx = 0;
440 mbx->stats.msgs_rx = 0; 440 mbx->stats.reqs = 0;
441 mbx->stats.reqs = 0; 441 mbx->stats.acks = 0;
442 mbx->stats.acks = 0; 442 mbx->stats.rsts = 0;
443 mbx->stats.rsts = 0;
444 }
445 443
446 return 0; 444 return 0;
447} 445}
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index 200cc3209672..cb6bf7b815ae 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -2287,9 +2287,14 @@ static int __devinit igb_sw_init(struct igb_adapter *adapter)
2287 2287
2288 spin_lock_init(&adapter->stats64_lock); 2288 spin_lock_init(&adapter->stats64_lock);
2289#ifdef CONFIG_PCI_IOV 2289#ifdef CONFIG_PCI_IOV
2290 if (hw->mac.type == e1000_82576) 2290 switch (hw->mac.type) {
2291 case e1000_82576:
2292 case e1000_i350:
2291 adapter->vfs_allocated_count = (max_vfs > 7) ? 7 : max_vfs; 2293 adapter->vfs_allocated_count = (max_vfs > 7) ? 7 : max_vfs;
2292 2294 break;
2295 default:
2296 break;
2297 }
2293#endif /* CONFIG_PCI_IOV */ 2298#endif /* CONFIG_PCI_IOV */
2294 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); 2299 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
2295 2300
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index 3b8c92463617..12769b58c2e7 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -334,6 +334,10 @@ struct ixgbe_adapter {
334 u16 bd_number; 334 u16 bd_number;
335 struct work_struct reset_task; 335 struct work_struct reset_task;
336 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; 336 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
337
338 /* DCB parameters */
339 struct ieee_pfc *ixgbe_ieee_pfc;
340 struct ieee_ets *ixgbe_ieee_ets;
337 struct ixgbe_dcb_config dcb_cfg; 341 struct ixgbe_dcb_config dcb_cfg;
338 struct ixgbe_dcb_config temp_dcb_cfg; 342 struct ixgbe_dcb_config temp_dcb_cfg;
339 u8 dcb_set_bitmap; 343 u8 dcb_set_bitmap;
@@ -521,7 +525,6 @@ extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
521extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 525extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
522extern void ixgbe_write_eitr(struct ixgbe_q_vector *); 526extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
523extern int ethtool_ioctl(struct ifreq *ifr); 527extern int ethtool_ioctl(struct ifreq *ifr);
524extern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index);
525extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 528extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
526extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc); 529extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
527extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc); 530extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
diff --git a/drivers/net/ixgbe/ixgbe_common.h b/drivers/net/ixgbe/ixgbe_common.h
index 66ed045a8cf0..90cceb4a6317 100644
--- a/drivers/net/ixgbe/ixgbe_common.h
+++ b/drivers/net/ixgbe/ixgbe_common.h
@@ -29,6 +29,7 @@
29#define _IXGBE_COMMON_H_ 29#define _IXGBE_COMMON_H_
30 30
31#include "ixgbe_type.h" 31#include "ixgbe_type.h"
32#include "ixgbe.h"
32 33
33u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw); 34u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
34s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw); 35s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
@@ -110,9 +111,8 @@ void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
110 111
111#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS) 112#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
112 113
113extern struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw);
114#define hw_dbg(hw, format, arg...) \ 114#define hw_dbg(hw, format, arg...) \
115 netdev_dbg(ixgbe_get_hw_dev(hw), format, ##arg) 115 netdev_dbg(((struct ixgbe_adapter *)(hw->back))->netdev, format, ##arg)
116#define e_dev_info(format, arg...) \ 116#define e_dev_info(format, arg...) \
117 dev_info(&adapter->pdev->dev, format, ## arg) 117 dev_info(&adapter->pdev->dev, format, ## arg)
118#define e_dev_warn(format, arg...) \ 118#define e_dev_warn(format, arg...) \
diff --git a/drivers/net/ixgbe/ixgbe_dcb.c b/drivers/net/ixgbe/ixgbe_dcb.c
index d16c260c1f50..13c962efbfc9 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.c
+++ b/drivers/net/ixgbe/ixgbe_dcb.c
@@ -34,6 +34,42 @@
34#include "ixgbe_dcb_82599.h" 34#include "ixgbe_dcb_82599.h"
35 35
36/** 36/**
37 * ixgbe_ieee_credits - This calculates the ieee traffic class
38 * credits from the configured bandwidth percentages. Credits
39 * are the smallest unit programable into the underlying
40 * hardware. The IEEE 802.1Qaz specification do not use bandwidth
41 * groups so this is much simplified from the CEE case.
42 */
43s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, __u16 *max, int max_frame)
44{
45 int min_percent = 100;
46 int min_credit, multiplier;
47 int i;
48
49 min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
50 DCB_CREDIT_QUANTUM;
51
52 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
53 if (bw[i] < min_percent && bw[i])
54 min_percent = bw[i];
55 }
56
57 multiplier = (min_credit / min_percent) + 1;
58
59 /* Find out the hw credits for each TC */
60 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
61 int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL);
62
63 if (val < min_credit)
64 val = min_credit;
65 refill[i] = val;
66
67 max[i] = (bw[i] * MAX_CREDIT)/100;
68 }
69 return 0;
70}
71
72/**
37 * ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits 73 * ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits
38 * @ixgbe_dcb_config: Struct containing DCB settings. 74 * @ixgbe_dcb_config: Struct containing DCB settings.
39 * @direction: Configuring either Tx or Rx. 75 * @direction: Configuring either Tx or Rx.
@@ -141,6 +177,59 @@ out:
141 return ret_val; 177 return ret_val;
142} 178}
143 179
180void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en)
181{
182 int i;
183
184 *pfc_en = 0;
185 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
186 *pfc_en |= (cfg->tc_config[i].dcb_pfc & 0xF) << i;
187}
188
189void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *cfg, int direction,
190 u16 *refill)
191{
192 struct tc_bw_alloc *p;
193 int i;
194
195 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
196 p = &cfg->tc_config[i].path[direction];
197 refill[i] = p->data_credits_refill;
198 }
199}
200
201void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *cfg, u16 *max)
202{
203 int i;
204
205 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
206 max[i] = cfg->tc_config[i].desc_credits_max;
207}
208
209void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *cfg, int direction,
210 u8 *bwgid)
211{
212 struct tc_bw_alloc *p;
213 int i;
214
215 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
216 p = &cfg->tc_config[i].path[direction];
217 bwgid[i] = p->bwg_id;
218 }
219}
220
221void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction,
222 u8 *ptype)
223{
224 struct tc_bw_alloc *p;
225 int i;
226
227 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
228 p = &cfg->tc_config[i].path[direction];
229 ptype[i] = p->prio_type;
230 }
231}
232
144/** 233/**
145 * ixgbe_dcb_hw_config - Config and enable DCB 234 * ixgbe_dcb_hw_config - Config and enable DCB
146 * @hw: pointer to hardware structure 235 * @hw: pointer to hardware structure
@@ -152,13 +241,30 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
152 struct ixgbe_dcb_config *dcb_config) 241 struct ixgbe_dcb_config *dcb_config)
153{ 242{
154 s32 ret = 0; 243 s32 ret = 0;
244 u8 pfc_en;
245 u8 ptype[MAX_TRAFFIC_CLASS];
246 u8 bwgid[MAX_TRAFFIC_CLASS];
247 u16 refill[MAX_TRAFFIC_CLASS];
248 u16 max[MAX_TRAFFIC_CLASS];
249
250 /* Unpack CEE standard containers */
251 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en);
252 ixgbe_dcb_unpack_refill(dcb_config, DCB_TX_CONFIG, refill);
253 ixgbe_dcb_unpack_max(dcb_config, max);
254 ixgbe_dcb_unpack_bwgid(dcb_config, DCB_TX_CONFIG, bwgid);
255 ixgbe_dcb_unpack_prio(dcb_config, DCB_TX_CONFIG, ptype);
256
155 switch (hw->mac.type) { 257 switch (hw->mac.type) {
156 case ixgbe_mac_82598EB: 258 case ixgbe_mac_82598EB:
157 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config); 259 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->rx_pba_cfg,
260 pfc_en, refill, max, bwgid,
261 ptype);
158 break; 262 break;
159 case ixgbe_mac_82599EB: 263 case ixgbe_mac_82599EB:
160 case ixgbe_mac_X540: 264 case ixgbe_mac_X540:
161 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config); 265 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg,
266 pfc_en, refill, max, bwgid,
267 ptype);
162 break; 268 break;
163 default: 269 default:
164 break; 270 break;
@@ -166,3 +272,70 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
166 return ret; 272 return ret;
167} 273}
168 274
275/* Helper routines to abstract HW specifics from DCB netlink ops */
276s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en)
277{
278 int ret = -EINVAL;
279
280 switch (hw->mac.type) {
281 case ixgbe_mac_82598EB:
282 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
283 break;
284 case ixgbe_mac_82599EB:
285 case ixgbe_mac_X540:
286 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en);
287 break;
288 default:
289 break;
290 }
291 return ret;
292}
293
294s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
295 u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa)
296{
297 int i;
298 u8 prio_type[IEEE_8021QAZ_MAX_TCS];
299
300 /* Map TSA onto CEE prio type */
301 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
302 switch (tsa[i]) {
303 case IEEE_8021QAZ_TSA_STRICT:
304 prio_type[i] = 2;
305 break;
306 case IEEE_8021QAZ_TSA_ETS:
307 prio_type[i] = 0;
308 break;
309 default:
310 /* Hardware only supports priority strict or
311 * ETS transmission selection algorithms if
312 * we receive some other value from dcbnl
313 * throw an error
314 */
315 return -EINVAL;
316 }
317 }
318
319 switch (hw->mac.type) {
320 case ixgbe_mac_82598EB:
321 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max,
322 prio_type);
323 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
324 bwg_id, prio_type);
325 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
326 bwg_id, prio_type);
327 break;
328 case ixgbe_mac_82599EB:
329 case ixgbe_mac_X540:
330 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
331 bwg_id, prio_type);
332 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
333 bwg_id, prio_type);
334 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
335 bwg_id, prio_type);
336 break;
337 default:
338 break;
339 }
340 return 0;
341}
diff --git a/drivers/net/ixgbe/ixgbe_dcb.h b/drivers/net/ixgbe/ixgbe_dcb.h
index 1cfe38ee1644..e5935114815e 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.h
+++ b/drivers/net/ixgbe/ixgbe_dcb.h
@@ -139,7 +139,6 @@ struct ixgbe_dcb_config {
139 struct tc_configuration tc_config[MAX_TRAFFIC_CLASS]; 139 struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
140 u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */ 140 u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
141 bool pfc_mode_enable; 141 bool pfc_mode_enable;
142 bool round_robin_enable;
143 142
144 enum dcb_rx_pba_cfg rx_pba_cfg; 143 enum dcb_rx_pba_cfg rx_pba_cfg;
145 144
@@ -148,12 +147,21 @@ struct ixgbe_dcb_config {
148}; 147};
149 148
150/* DCB driver APIs */ 149/* DCB driver APIs */
150void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en);
151void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *, int, u16 *);
152void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *, u16 *);
153void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *, int, u8 *);
154void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *, int, u8 *);
151 155
152/* DCB credits calculation */ 156/* DCB credits calculation */
157s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, __u16 *max, int max_frame);
153s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *, 158s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *,
154 struct ixgbe_dcb_config *, int, u8); 159 struct ixgbe_dcb_config *, int, u8);
155 160
156/* DCB hw initialization */ 161/* DCB hw initialization */
162s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
163 u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type);
164s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en);
157s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *); 165s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
158 166
159/* DCB definitions for credit calculation */ 167/* DCB definitions for credit calculation */
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ixgbe/ixgbe_dcb_82598.c
index 9a5e89c12e05..2965edcdac7b 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c
@@ -38,15 +38,14 @@
38 * 38 *
39 * Configure packet buffers for DCB mode. 39 * Configure packet buffers for DCB mode.
40 */ 40 */
41static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, 41static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, u8 rx_pba)
42 struct ixgbe_dcb_config *dcb_config)
43{ 42{
44 s32 ret_val = 0; 43 s32 ret_val = 0;
45 u32 value = IXGBE_RXPBSIZE_64KB; 44 u32 value = IXGBE_RXPBSIZE_64KB;
46 u8 i = 0; 45 u8 i = 0;
47 46
48 /* Setup Rx packet buffer sizes */ 47 /* Setup Rx packet buffer sizes */
49 switch (dcb_config->rx_pba_cfg) { 48 switch (rx_pba) {
50 case pba_80_48: 49 case pba_80_48:
51 /* Setup the first four at 80KB */ 50 /* Setup the first four at 80KB */
52 value = IXGBE_RXPBSIZE_80KB; 51 value = IXGBE_RXPBSIZE_80KB;
@@ -78,10 +77,11 @@ static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
78 * 77 *
79 * Configure Rx Data Arbiter and credits for each traffic class. 78 * Configure Rx Data Arbiter and credits for each traffic class.
80 */ 79 */
81static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, 80s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
82 struct ixgbe_dcb_config *dcb_config) 81 u16 *refill,
82 u16 *max,
83 u8 *prio_type)
83{ 84{
84 struct tc_bw_alloc *p;
85 u32 reg = 0; 85 u32 reg = 0;
86 u32 credit_refill = 0; 86 u32 credit_refill = 0;
87 u32 credit_max = 0; 87 u32 credit_max = 0;
@@ -102,13 +102,12 @@ static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
102 102
103 /* Configure traffic class credits and priority */ 103 /* Configure traffic class credits and priority */
104 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 104 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
105 p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG]; 105 credit_refill = refill[i];
106 credit_refill = p->data_credits_refill; 106 credit_max = max[i];
107 credit_max = p->data_credits_max;
108 107
109 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 108 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
110 109
111 if (p->prio_type == prio_link) 110 if (prio_type[i] == prio_link)
112 reg |= IXGBE_RT2CR_LSP; 111 reg |= IXGBE_RT2CR_LSP;
113 112
114 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); 113 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
@@ -135,10 +134,12 @@ static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
135 * 134 *
136 * Configure Tx Descriptor Arbiter and credits for each traffic class. 135 * Configure Tx Descriptor Arbiter and credits for each traffic class.
137 */ 136 */
138static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 137s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
139 struct ixgbe_dcb_config *dcb_config) 138 u16 *refill,
139 u16 *max,
140 u8 *bwg_id,
141 u8 *prio_type)
140{ 142{
141 struct tc_bw_alloc *p;
142 u32 reg, max_credits; 143 u32 reg, max_credits;
143 u8 i; 144 u8 i;
144 145
@@ -146,10 +147,8 @@ static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
146 147
147 /* Enable arbiter */ 148 /* Enable arbiter */
148 reg &= ~IXGBE_DPMCS_ARBDIS; 149 reg &= ~IXGBE_DPMCS_ARBDIS;
149 if (!(dcb_config->round_robin_enable)) { 150 /* Enable DFP and Recycle mode */
150 /* Enable DFP and Recycle mode */ 151 reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
151 reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
152 }
153 reg |= IXGBE_DPMCS_TSOEF; 152 reg |= IXGBE_DPMCS_TSOEF;
154 /* Configure Max TSO packet size 34KB including payload and headers */ 153 /* Configure Max TSO packet size 34KB including payload and headers */
155 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); 154 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
@@ -158,16 +157,15 @@ static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
158 157
159 /* Configure traffic class credits and priority */ 158 /* Configure traffic class credits and priority */
160 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 159 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
161 p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG]; 160 max_credits = max[i];
162 max_credits = dcb_config->tc_config[i].desc_credits_max;
163 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; 161 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
164 reg |= p->data_credits_refill; 162 reg |= refill[i];
165 reg |= (u32)(p->bwg_id) << IXGBE_TDTQ2TCCR_BWG_SHIFT; 163 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
166 164
167 if (p->prio_type == prio_group) 165 if (prio_type[i] == prio_group)
168 reg |= IXGBE_TDTQ2TCCR_GSP; 166 reg |= IXGBE_TDTQ2TCCR_GSP;
169 167
170 if (p->prio_type == prio_link) 168 if (prio_type[i] == prio_link)
171 reg |= IXGBE_TDTQ2TCCR_LSP; 169 reg |= IXGBE_TDTQ2TCCR_LSP;
172 170
173 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); 171 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
@@ -183,10 +181,12 @@ static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
183 * 181 *
184 * Configure Tx Data Arbiter and credits for each traffic class. 182 * Configure Tx Data Arbiter and credits for each traffic class.
185 */ 183 */
186static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 184s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
187 struct ixgbe_dcb_config *dcb_config) 185 u16 *refill,
186 u16 *max,
187 u8 *bwg_id,
188 u8 *prio_type)
188{ 189{
189 struct tc_bw_alloc *p;
190 u32 reg; 190 u32 reg;
191 u8 i; 191 u8 i;
192 192
@@ -200,15 +200,14 @@ static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
200 200
201 /* Configure traffic class credits and priority */ 201 /* Configure traffic class credits and priority */
202 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 202 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
203 p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG]; 203 reg = refill[i];
204 reg = p->data_credits_refill; 204 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
205 reg |= (u32)(p->data_credits_max) << IXGBE_TDPT2TCCR_MCL_SHIFT; 205 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
206 reg |= (u32)(p->bwg_id) << IXGBE_TDPT2TCCR_BWG_SHIFT;
207 206
208 if (p->prio_type == prio_group) 207 if (prio_type[i] == prio_group)
209 reg |= IXGBE_TDPT2TCCR_GSP; 208 reg |= IXGBE_TDPT2TCCR_GSP;
210 209
211 if (p->prio_type == prio_link) 210 if (prio_type[i] == prio_link)
212 reg |= IXGBE_TDPT2TCCR_LSP; 211 reg |= IXGBE_TDPT2TCCR_LSP;
213 212
214 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); 213 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
@@ -229,13 +228,12 @@ static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
229 * 228 *
230 * Configure Priority Flow Control for each traffic class. 229 * Configure Priority Flow Control for each traffic class.
231 */ 230 */
232s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, 231s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
233 struct ixgbe_dcb_config *dcb_config)
234{ 232{
235 u32 reg, rx_pba_size; 233 u32 reg, rx_pba_size;
236 u8 i; 234 u8 i;
237 235
238 if (!dcb_config->pfc_mode_enable) 236 if (!pfc_en)
239 goto out; 237 goto out;
240 238
241 /* Enable Transmit Priority Flow Control */ 239 /* Enable Transmit Priority Flow Control */
@@ -256,19 +254,20 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
256 * for each traffic class. 254 * for each traffic class.
257 */ 255 */
258 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 256 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
257 int enabled = pfc_en & (1 << i);
259 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 258 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
260 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT; 259 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
261 reg = (rx_pba_size - hw->fc.low_water) << 10; 260 reg = (rx_pba_size - hw->fc.low_water) << 10;
262 261
263 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx || 262 if (enabled == pfc_enabled_tx ||
264 dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full) 263 enabled == pfc_enabled_full)
265 reg |= IXGBE_FCRTL_XONE; 264 reg |= IXGBE_FCRTL_XONE;
266 265
267 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg); 266 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
268 267
269 reg = (rx_pba_size - hw->fc.high_water) << 10; 268 reg = (rx_pba_size - hw->fc.high_water) << 10;
270 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx || 269 if (enabled == pfc_enabled_tx ||
271 dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full) 270 enabled == pfc_enabled_full)
272 reg |= IXGBE_FCRTH_FCEN; 271 reg |= IXGBE_FCRTH_FCEN;
273 272
274 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 273 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
@@ -292,7 +291,7 @@ out:
292 * Configure queue statistics registers, all queues belonging to same traffic 291 * Configure queue statistics registers, all queues belonging to same traffic
293 * class uses a single set of queue statistics counters. 292 * class uses a single set of queue statistics counters.
294 */ 293 */
295static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) 294s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
296{ 295{
297 u32 reg = 0; 296 u32 reg = 0;
298 u8 i = 0; 297 u8 i = 0;
@@ -325,13 +324,16 @@ static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
325 * Configure dcb settings and enable dcb mode. 324 * Configure dcb settings and enable dcb mode.
326 */ 325 */
327s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, 326s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
328 struct ixgbe_dcb_config *dcb_config) 327 u8 rx_pba, u8 pfc_en, u16 *refill,
328 u16 *max, u8 *bwg_id, u8 *prio_type)
329{ 329{
330 ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config); 330 ixgbe_dcb_config_packet_buffers_82598(hw, rx_pba);
331 ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config); 331 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
332 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config); 332 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
333 ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config); 333 bwg_id, prio_type);
334 ixgbe_dcb_config_pfc_82598(hw, dcb_config); 334 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
335 bwg_id, prio_type);
336 ixgbe_dcb_config_pfc_82598(hw, pfc_en);
335 ixgbe_dcb_config_tc_stats_82598(hw); 337 ixgbe_dcb_config_tc_stats_82598(hw);
336 338
337 return 0; 339 return 0;
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.h b/drivers/net/ixgbe/ixgbe_dcb_82598.h
index abc03ccfa088..0d2a758effce 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.h
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.h
@@ -71,9 +71,28 @@
71/* DCB hardware-specific driver APIs */ 71/* DCB hardware-specific driver APIs */
72 72
73/* DCB PFC functions */ 73/* DCB PFC functions */
74s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, struct ixgbe_dcb_config *); 74s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8 pfc_en);
75 75
76/* DCB hw initialization */ 76/* DCB hw initialization */
77s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, struct ixgbe_dcb_config *); 77s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
78 u16 *refill,
79 u16 *max,
80 u8 *prio_type);
81
82s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
83 u16 *refill,
84 u16 *max,
85 u8 *bwg_id,
86 u8 *prio_type);
87
88s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
89 u16 *refill,
90 u16 *max,
91 u8 *bwg_id,
92 u8 *prio_type);
93
94s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
95 u8 rx_pba, u8 pfc_en, u16 *refill,
96 u16 *max, u8 *bwg_id, u8 *prio_type);
78 97
79#endif /* _DCB_82598_CONFIG_H */ 98#endif /* _DCB_82598_CONFIG_H */
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 374e1f74d0f5..b0d97a98c84d 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -33,19 +33,18 @@
33/** 33/**
34 * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers 34 * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers
35 * @hw: pointer to hardware structure 35 * @hw: pointer to hardware structure
36 * @dcb_config: pointer to ixgbe_dcb_config structure 36 * @rx_pba: method to distribute packet buffer
37 * 37 *
38 * Configure packet buffers for DCB mode. 38 * Configure packet buffers for DCB mode.
39 */ 39 */
40static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, 40static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, u8 rx_pba)
41 struct ixgbe_dcb_config *dcb_config)
42{ 41{
43 s32 ret_val = 0; 42 s32 ret_val = 0;
44 u32 value = IXGBE_RXPBSIZE_64KB; 43 u32 value = IXGBE_RXPBSIZE_64KB;
45 u8 i = 0; 44 u8 i = 0;
46 45
47 /* Setup Rx packet buffer sizes */ 46 /* Setup Rx packet buffer sizes */
48 switch (dcb_config->rx_pba_cfg) { 47 switch (rx_pba) {
49 case pba_80_48: 48 case pba_80_48:
50 /* Setup the first four at 80KB */ 49 /* Setup the first four at 80KB */
51 value = IXGBE_RXPBSIZE_80KB; 50 value = IXGBE_RXPBSIZE_80KB;
@@ -75,14 +74,19 @@ static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw,
75/** 74/**
76 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter 75 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
77 * @hw: pointer to hardware structure 76 * @hw: pointer to hardware structure
78 * @dcb_config: pointer to ixgbe_dcb_config structure 77 * @refill: refill credits index by traffic class
78 * @max: max credits index by traffic class
79 * @bwg_id: bandwidth grouping indexed by traffic class
80 * @prio_type: priority type indexed by traffic class
79 * 81 *
80 * Configure Rx Packet Arbiter and credits for each traffic class. 82 * Configure Rx Packet Arbiter and credits for each traffic class.
81 */ 83 */
82static s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, 84s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
83 struct ixgbe_dcb_config *dcb_config) 85 u16 *refill,
86 u16 *max,
87 u8 *bwg_id,
88 u8 *prio_type)
84{ 89{
85 struct tc_bw_alloc *p;
86 u32 reg = 0; 90 u32 reg = 0;
87 u32 credit_refill = 0; 91 u32 credit_refill = 0;
88 u32 credit_max = 0; 92 u32 credit_max = 0;
@@ -103,15 +107,13 @@ static s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
103 107
104 /* Configure traffic class credits and priority */ 108 /* Configure traffic class credits and priority */
105 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 109 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
106 p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG]; 110 credit_refill = refill[i];
107 111 credit_max = max[i];
108 credit_refill = p->data_credits_refill;
109 credit_max = p->data_credits_max;
110 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); 112 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
111 113
112 reg |= (u32)(p->bwg_id) << IXGBE_RTRPT4C_BWG_SHIFT; 114 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
113 115
114 if (p->prio_type == prio_link) 116 if (prio_type[i] == prio_link)
115 reg |= IXGBE_RTRPT4C_LSP; 117 reg |= IXGBE_RTRPT4C_LSP;
116 118
117 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); 119 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
@@ -130,14 +132,19 @@ static s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
130/** 132/**
131 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter 133 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
132 * @hw: pointer to hardware structure 134 * @hw: pointer to hardware structure
133 * @dcb_config: pointer to ixgbe_dcb_config structure 135 * @refill: refill credits index by traffic class
136 * @max: max credits index by traffic class
137 * @bwg_id: bandwidth grouping indexed by traffic class
138 * @prio_type: priority type indexed by traffic class
134 * 139 *
135 * Configure Tx Descriptor Arbiter and credits for each traffic class. 140 * Configure Tx Descriptor Arbiter and credits for each traffic class.
136 */ 141 */
137static s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, 142s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
138 struct ixgbe_dcb_config *dcb_config) 143 u16 *refill,
144 u16 *max,
145 u8 *bwg_id,
146 u8 *prio_type)
139{ 147{
140 struct tc_bw_alloc *p;
141 u32 reg, max_credits; 148 u32 reg, max_credits;
142 u8 i; 149 u8 i;
143 150
@@ -149,16 +156,15 @@ static s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
149 156
150 /* Configure traffic class credits and priority */ 157 /* Configure traffic class credits and priority */
151 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 158 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
152 p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG]; 159 max_credits = max[i];
153 max_credits = dcb_config->tc_config[i].desc_credits_max;
154 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; 160 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
155 reg |= p->data_credits_refill; 161 reg |= refill[i];
156 reg |= (u32)(p->bwg_id) << IXGBE_RTTDT2C_BWG_SHIFT; 162 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
157 163
158 if (p->prio_type == prio_group) 164 if (prio_type[i] == prio_group)
159 reg |= IXGBE_RTTDT2C_GSP; 165 reg |= IXGBE_RTTDT2C_GSP;
160 166
161 if (p->prio_type == prio_link) 167 if (prio_type[i] == prio_link)
162 reg |= IXGBE_RTTDT2C_LSP; 168 reg |= IXGBE_RTTDT2C_LSP;
163 169
164 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); 170 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
@@ -177,14 +183,19 @@ static s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
177/** 183/**
178 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter 184 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
179 * @hw: pointer to hardware structure 185 * @hw: pointer to hardware structure
180 * @dcb_config: pointer to ixgbe_dcb_config structure 186 * @refill: refill credits index by traffic class
187 * @max: max credits index by traffic class
188 * @bwg_id: bandwidth grouping indexed by traffic class
189 * @prio_type: priority type indexed by traffic class
181 * 190 *
182 * Configure Tx Packet Arbiter and credits for each traffic class. 191 * Configure Tx Packet Arbiter and credits for each traffic class.
183 */ 192 */
184static s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, 193s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
185 struct ixgbe_dcb_config *dcb_config) 194 u16 *refill,
195 u16 *max,
196 u8 *bwg_id,
197 u8 *prio_type)
186{ 198{
187 struct tc_bw_alloc *p;
188 u32 reg; 199 u32 reg;
189 u8 i; 200 u8 i;
190 201
@@ -205,15 +216,14 @@ static s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
205 216
206 /* Configure traffic class credits and priority */ 217 /* Configure traffic class credits and priority */
207 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 218 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
208 p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG]; 219 reg = refill[i];
209 reg = p->data_credits_refill; 220 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
210 reg |= (u32)(p->data_credits_max) << IXGBE_RTTPT2C_MCL_SHIFT; 221 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
211 reg |= (u32)(p->bwg_id) << IXGBE_RTTPT2C_BWG_SHIFT;
212 222
213 if (p->prio_type == prio_group) 223 if (prio_type[i] == prio_group)
214 reg |= IXGBE_RTTPT2C_GSP; 224 reg |= IXGBE_RTTPT2C_GSP;
215 225
216 if (p->prio_type == prio_link) 226 if (prio_type[i] == prio_link)
217 reg |= IXGBE_RTTPT2C_LSP; 227 reg |= IXGBE_RTTPT2C_LSP;
218 228
219 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); 229 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
@@ -233,17 +243,16 @@ static s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
233/** 243/**
234 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control 244 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
235 * @hw: pointer to hardware structure 245 * @hw: pointer to hardware structure
236 * @dcb_config: pointer to ixgbe_dcb_config structure 246 * @pfc_en: enabled pfc bitmask
237 * 247 *
238 * Configure Priority Flow Control (PFC) for each traffic class. 248 * Configure Priority Flow Control (PFC) for each traffic class.
239 */ 249 */
240s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, 250s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
241 struct ixgbe_dcb_config *dcb_config)
242{ 251{
243 u32 i, reg, rx_pba_size; 252 u32 i, reg, rx_pba_size;
244 253
245 /* If PFC is disabled globally then fall back to LFC. */ 254 /* If PFC is disabled globally then fall back to LFC. */
246 if (!dcb_config->pfc_mode_enable) { 255 if (!pfc_en) {
247 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 256 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
248 hw->mac.ops.fc_enable(hw, i); 257 hw->mac.ops.fc_enable(hw, i);
249 goto out; 258 goto out;
@@ -251,19 +260,18 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw,
251 260
252 /* Configure PFC Tx thresholds per TC */ 261 /* Configure PFC Tx thresholds per TC */
253 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 262 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
263 int enabled = pfc_en & (1 << i);
254 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 264 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
255 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT; 265 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
256 266
257 reg = (rx_pba_size - hw->fc.low_water) << 10; 267 reg = (rx_pba_size - hw->fc.low_water) << 10;
258 268
259 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full || 269 if (enabled)
260 dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx)
261 reg |= IXGBE_FCRTL_XONE; 270 reg |= IXGBE_FCRTL_XONE;
262 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg); 271 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
263 272
264 reg = (rx_pba_size - hw->fc.high_water) << 10; 273 reg = (rx_pba_size - hw->fc.high_water) << 10;
265 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full || 274 if (enabled)
266 dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx)
267 reg |= IXGBE_FCRTH_FCEN; 275 reg |= IXGBE_FCRTH_FCEN;
268 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); 276 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
269 } 277 }
@@ -349,7 +357,6 @@ static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
349/** 357/**
350 * ixgbe_dcb_config_82599 - Configure general DCB parameters 358 * ixgbe_dcb_config_82599 - Configure general DCB parameters
351 * @hw: pointer to hardware structure 359 * @hw: pointer to hardware structure
352 * @dcb_config: pointer to ixgbe_dcb_config structure
353 * 360 *
354 * Configure general DCB parameters. 361 * Configure general DCB parameters.
355 */ 362 */
@@ -406,19 +413,27 @@ static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw)
406/** 413/**
407 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB 414 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
408 * @hw: pointer to hardware structure 415 * @hw: pointer to hardware structure
409 * @dcb_config: pointer to ixgbe_dcb_config structure 416 * @rx_pba: method to distribute packet buffer
417 * @refill: refill credits index by traffic class
418 * @max: max credits index by traffic class
419 * @bwg_id: bandwidth grouping indexed by traffic class
420 * @prio_type: priority type indexed by traffic class
421 * @pfc_en: enabled pfc bitmask
410 * 422 *
411 * Configure dcb settings and enable dcb mode. 423 * Configure dcb settings and enable dcb mode.
412 */ 424 */
413s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, 425s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
414 struct ixgbe_dcb_config *dcb_config) 426 u8 rx_pba, u8 pfc_en, u16 *refill,
427 u16 *max, u8 *bwg_id, u8 *prio_type)
415{ 428{
416 ixgbe_dcb_config_packet_buffers_82599(hw, dcb_config); 429 ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba);
417 ixgbe_dcb_config_82599(hw); 430 ixgbe_dcb_config_82599(hw);
418 ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config); 431 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, prio_type);
419 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config); 432 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
420 ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config); 433 bwg_id, prio_type);
421 ixgbe_dcb_config_pfc_82599(hw, dcb_config); 434 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
435 bwg_id, prio_type);
436 ixgbe_dcb_config_pfc_82599(hw, pfc_en);
422 ixgbe_dcb_config_tc_stats_82599(hw); 437 ixgbe_dcb_config_tc_stats_82599(hw);
423 438
424 return 0; 439 return 0;
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.h b/drivers/net/ixgbe/ixgbe_dcb_82599.h
index 3841649fb954..5b0ca85614d1 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.h
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.h
@@ -102,11 +102,29 @@
102/* DCB hardware-specific driver APIs */ 102/* DCB hardware-specific driver APIs */
103 103
104/* DCB PFC functions */ 104/* DCB PFC functions */
105s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, 105s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en);
106 struct ixgbe_dcb_config *dcb_config);
107 106
108/* DCB hw initialization */ 107/* DCB hw initialization */
108s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
109 u16 *refill,
110 u16 *max,
111 u8 *bwg_id,
112 u8 *prio_type);
113
114s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
115 u16 *refill,
116 u16 *max,
117 u8 *bwg_id,
118 u8 *prio_type);
119
120s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
121 u16 *refill,
122 u16 *max,
123 u8 *bwg_id,
124 u8 *prio_type);
125
109s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, 126s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
110 struct ixgbe_dcb_config *config); 127 u8 rx_pba, u8 pfc_en, u16 *refill,
128 u16 *max, u8 *bwg_id, u8 *prio_type);
111 129
112#endif /* _DCB_82599_CONFIG_H */ 130#endif /* _DCB_82599_CONFIG_H */
diff --git a/drivers/net/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ixgbe/ixgbe_dcb_nl.c
index bf566e8a455e..a977df3fe81b 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c
@@ -37,7 +37,6 @@
37#define BIT_PG_RX 0x04 37#define BIT_PG_RX 0x04
38#define BIT_PG_TX 0x08 38#define BIT_PG_TX 0x08
39#define BIT_APP_UPCHG 0x10 39#define BIT_APP_UPCHG 0x10
40#define BIT_RESETLINK 0x40
41#define BIT_LINKSPEED 0x80 40#define BIT_LINKSPEED 0x80
42 41
43/* Responses for the DCB_C_SET_ALL command */ 42/* Responses for the DCB_C_SET_ALL command */
@@ -225,10 +224,8 @@ static void ixgbe_dcbnl_set_pg_tc_cfg_tx(struct net_device *netdev, int tc,
225 (adapter->temp_dcb_cfg.tc_config[tc].path[0].bwg_percent != 224 (adapter->temp_dcb_cfg.tc_config[tc].path[0].bwg_percent !=
226 adapter->dcb_cfg.tc_config[tc].path[0].bwg_percent) || 225 adapter->dcb_cfg.tc_config[tc].path[0].bwg_percent) ||
227 (adapter->temp_dcb_cfg.tc_config[tc].path[0].up_to_tc_bitmap != 226 (adapter->temp_dcb_cfg.tc_config[tc].path[0].up_to_tc_bitmap !=
228 adapter->dcb_cfg.tc_config[tc].path[0].up_to_tc_bitmap)) { 227 adapter->dcb_cfg.tc_config[tc].path[0].up_to_tc_bitmap))
229 adapter->dcb_set_bitmap |= BIT_PG_TX; 228 adapter->dcb_set_bitmap |= BIT_PG_TX;
230 adapter->dcb_set_bitmap |= BIT_RESETLINK;
231 }
232} 229}
233 230
234static void ixgbe_dcbnl_set_pg_bwg_cfg_tx(struct net_device *netdev, int bwg_id, 231static void ixgbe_dcbnl_set_pg_bwg_cfg_tx(struct net_device *netdev, int bwg_id,
@@ -239,10 +236,8 @@ static void ixgbe_dcbnl_set_pg_bwg_cfg_tx(struct net_device *netdev, int bwg_id,
239 adapter->temp_dcb_cfg.bw_percentage[0][bwg_id] = bw_pct; 236 adapter->temp_dcb_cfg.bw_percentage[0][bwg_id] = bw_pct;
240 237
241 if (adapter->temp_dcb_cfg.bw_percentage[0][bwg_id] != 238 if (adapter->temp_dcb_cfg.bw_percentage[0][bwg_id] !=
242 adapter->dcb_cfg.bw_percentage[0][bwg_id]) { 239 adapter->dcb_cfg.bw_percentage[0][bwg_id])
243 adapter->dcb_set_bitmap |= BIT_PG_TX; 240 adapter->dcb_set_bitmap |= BIT_PG_TX;
244 adapter->dcb_set_bitmap |= BIT_RESETLINK;
245 }
246} 241}
247 242
248static void ixgbe_dcbnl_set_pg_tc_cfg_rx(struct net_device *netdev, int tc, 243static void ixgbe_dcbnl_set_pg_tc_cfg_rx(struct net_device *netdev, int tc,
@@ -269,10 +264,8 @@ static void ixgbe_dcbnl_set_pg_tc_cfg_rx(struct net_device *netdev, int tc,
269 (adapter->temp_dcb_cfg.tc_config[tc].path[1].bwg_percent != 264 (adapter->temp_dcb_cfg.tc_config[tc].path[1].bwg_percent !=
270 adapter->dcb_cfg.tc_config[tc].path[1].bwg_percent) || 265 adapter->dcb_cfg.tc_config[tc].path[1].bwg_percent) ||
271 (adapter->temp_dcb_cfg.tc_config[tc].path[1].up_to_tc_bitmap != 266 (adapter->temp_dcb_cfg.tc_config[tc].path[1].up_to_tc_bitmap !=
272 adapter->dcb_cfg.tc_config[tc].path[1].up_to_tc_bitmap)) { 267 adapter->dcb_cfg.tc_config[tc].path[1].up_to_tc_bitmap))
273 adapter->dcb_set_bitmap |= BIT_PG_RX; 268 adapter->dcb_set_bitmap |= BIT_PG_RX;
274 adapter->dcb_set_bitmap |= BIT_RESETLINK;
275 }
276} 269}
277 270
278static void ixgbe_dcbnl_set_pg_bwg_cfg_rx(struct net_device *netdev, int bwg_id, 271static void ixgbe_dcbnl_set_pg_bwg_cfg_rx(struct net_device *netdev, int bwg_id,
@@ -283,10 +276,8 @@ static void ixgbe_dcbnl_set_pg_bwg_cfg_rx(struct net_device *netdev, int bwg_id,
283 adapter->temp_dcb_cfg.bw_percentage[1][bwg_id] = bw_pct; 276 adapter->temp_dcb_cfg.bw_percentage[1][bwg_id] = bw_pct;
284 277
285 if (adapter->temp_dcb_cfg.bw_percentage[1][bwg_id] != 278 if (adapter->temp_dcb_cfg.bw_percentage[1][bwg_id] !=
286 adapter->dcb_cfg.bw_percentage[1][bwg_id]) { 279 adapter->dcb_cfg.bw_percentage[1][bwg_id])
287 adapter->dcb_set_bitmap |= BIT_PG_RX; 280 adapter->dcb_set_bitmap |= BIT_PG_RX;
288 adapter->dcb_set_bitmap |= BIT_RESETLINK;
289 }
290} 281}
291 282
292static void ixgbe_dcbnl_get_pg_tc_cfg_tx(struct net_device *netdev, int tc, 283static void ixgbe_dcbnl_get_pg_tc_cfg_tx(struct net_device *netdev, int tc,
@@ -365,21 +356,17 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
365 return DCB_NO_HW_CHG; 356 return DCB_NO_HW_CHG;
366 357
367 /* 358 /*
368 * Only take down the adapter if the configuration change 359 * Only take down the adapter if an app change occured. FCoE
369 * requires a reset. 360 * may shuffle tx rings in this case and this can not be done
361 * without a reset currently.
370 */ 362 */
371 if (adapter->dcb_set_bitmap & BIT_RESETLINK) { 363 if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) {
372 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 364 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
373 msleep(1); 365 msleep(1);
374 366
375 if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) { 367 if (netif_running(netdev))
376 if (netif_running(netdev)) 368 netdev->netdev_ops->ndo_stop(netdev);
377 netdev->netdev_ops->ndo_stop(netdev); 369 ixgbe_clear_interrupt_scheme(adapter);
378 ixgbe_clear_interrupt_scheme(adapter);
379 } else {
380 if (netif_running(netdev))
381 ixgbe_down(adapter);
382 }
383 } 370 }
384 371
385 if (adapter->dcb_cfg.pfc_mode_enable) { 372 if (adapter->dcb_cfg.pfc_mode_enable) {
@@ -408,29 +395,51 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
408 } 395 }
409 } 396 }
410 397
411 if (adapter->dcb_set_bitmap & BIT_RESETLINK) { 398 if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) {
412 if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) { 399 ixgbe_init_interrupt_scheme(adapter);
413 ixgbe_init_interrupt_scheme(adapter); 400 if (netif_running(netdev))
414 if (netif_running(netdev)) 401 netdev->netdev_ops->ndo_open(netdev);
415 netdev->netdev_ops->ndo_open(netdev);
416 } else {
417 if (netif_running(netdev))
418 ixgbe_up(adapter);
419 }
420 ret = DCB_HW_CHG_RST; 402 ret = DCB_HW_CHG_RST;
421 } else if (adapter->dcb_set_bitmap & BIT_PFC) { 403 }
422 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 404
423 ixgbe_dcb_config_pfc_82598(&adapter->hw, 405 if (adapter->dcb_set_bitmap & BIT_PFC) {
424 &adapter->dcb_cfg); 406 u8 pfc_en;
425 else if (adapter->hw.mac.type == ixgbe_mac_82599EB) 407 ixgbe_dcb_unpack_pfc(&adapter->dcb_cfg, &pfc_en);
426 ixgbe_dcb_config_pfc_82599(&adapter->hw, 408 ixgbe_dcb_hw_pfc_config(&adapter->hw, pfc_en);
427 &adapter->dcb_cfg);
428 ret = DCB_HW_CHG; 409 ret = DCB_HW_CHG;
429 } 410 }
411
412 if (adapter->dcb_set_bitmap & (BIT_PG_TX|BIT_PG_RX)) {
413 u16 refill[MAX_TRAFFIC_CLASS], max[MAX_TRAFFIC_CLASS];
414 u8 bwg_id[MAX_TRAFFIC_CLASS], prio_type[MAX_TRAFFIC_CLASS];
415 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
416
417#ifdef CONFIG_FCOE
418 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
419 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
420#endif
421
422 ixgbe_dcb_calculate_tc_credits(&adapter->hw, &adapter->dcb_cfg,
423 max_frame, DCB_TX_CONFIG);
424 ixgbe_dcb_calculate_tc_credits(&adapter->hw, &adapter->dcb_cfg,
425 max_frame, DCB_RX_CONFIG);
426
427 ixgbe_dcb_unpack_refill(&adapter->dcb_cfg,
428 DCB_TX_CONFIG, refill);
429 ixgbe_dcb_unpack_max(&adapter->dcb_cfg, max);
430 ixgbe_dcb_unpack_bwgid(&adapter->dcb_cfg,
431 DCB_TX_CONFIG, bwg_id);
432 ixgbe_dcb_unpack_prio(&adapter->dcb_cfg,
433 DCB_TX_CONFIG, prio_type);
434
435 ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max,
436 bwg_id, prio_type);
437 }
438
430 if (adapter->dcb_cfg.pfc_mode_enable) 439 if (adapter->dcb_cfg.pfc_mode_enable)
431 adapter->hw.fc.current_mode = ixgbe_fc_pfc; 440 adapter->hw.fc.current_mode = ixgbe_fc_pfc;
432 441
433 if (adapter->dcb_set_bitmap & BIT_RESETLINK) 442 if (adapter->dcb_set_bitmap & BIT_APP_UPCHG)
434 clear_bit(__IXGBE_RESETTING, &adapter->state); 443 clear_bit(__IXGBE_RESETTING, &adapter->state);
435 adapter->dcb_set_bitmap = 0x00; 444 adapter->dcb_set_bitmap = 0x00;
436 return ret; 445 return ret;
@@ -568,18 +577,29 @@ static u8 ixgbe_dcbnl_setapp(struct net_device *netdev,
568 case DCB_APP_IDTYPE_ETHTYPE: 577 case DCB_APP_IDTYPE_ETHTYPE:
569#ifdef IXGBE_FCOE 578#ifdef IXGBE_FCOE
570 if (id == ETH_P_FCOE) { 579 if (id == ETH_P_FCOE) {
571 u8 tc; 580 u8 old_tc;
572 struct ixgbe_adapter *adapter; 581 struct ixgbe_adapter *adapter = netdev_priv(netdev);
573 582
574 adapter = netdev_priv(netdev); 583 /* Get current programmed tc */
575 tc = adapter->fcoe.tc; 584 old_tc = adapter->fcoe.tc;
576 rval = ixgbe_fcoe_setapp(adapter, up); 585 rval = ixgbe_fcoe_setapp(adapter, up);
577 if ((!rval) && (tc != adapter->fcoe.tc) && 586
578 (adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 587 if (rval ||
579 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { 588 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED) ||
589 !(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
590 break;
591
592 /* The FCoE application priority may be changed multiple
593 * times in quick sucession with switches that build up
594 * TLVs. To avoid creating uneeded device resets this
595 * checks the actual HW configuration and clears
596 * BIT_APP_UPCHG if a HW configuration change is not
597 * need
598 */
599 if (old_tc == adapter->fcoe.tc)
600 adapter->dcb_set_bitmap &= ~BIT_APP_UPCHG;
601 else
580 adapter->dcb_set_bitmap |= BIT_APP_UPCHG; 602 adapter->dcb_set_bitmap |= BIT_APP_UPCHG;
581 adapter->dcb_set_bitmap |= BIT_RESETLINK;
582 }
583 } 603 }
584#endif 604#endif
585 break; 605 break;
@@ -591,7 +611,98 @@ static u8 ixgbe_dcbnl_setapp(struct net_device *netdev,
591 return rval; 611 return rval;
592} 612}
593 613
614static int ixgbe_dcbnl_ieee_getets(struct net_device *dev,
615 struct ieee_ets *ets)
616{
617 struct ixgbe_adapter *adapter = netdev_priv(dev);
618 struct ieee_ets *my_ets = adapter->ixgbe_ieee_ets;
619
620 /* No IEEE PFC settings available */
621 if (!my_ets)
622 return -EINVAL;
623
624 ets->ets_cap = MAX_TRAFFIC_CLASS;
625 ets->cbs = my_ets->cbs;
626 memcpy(ets->tc_tx_bw, my_ets->tc_tx_bw, sizeof(ets->tc_tx_bw));
627 memcpy(ets->tc_rx_bw, my_ets->tc_rx_bw, sizeof(ets->tc_rx_bw));
628 memcpy(ets->tc_tsa, my_ets->tc_tsa, sizeof(ets->tc_tsa));
629 memcpy(ets->prio_tc, my_ets->prio_tc, sizeof(ets->prio_tc));
630 return 0;
631}
632
633static int ixgbe_dcbnl_ieee_setets(struct net_device *dev,
634 struct ieee_ets *ets)
635{
636 struct ixgbe_adapter *adapter = netdev_priv(dev);
637 __u16 refill[IEEE_8021QAZ_MAX_TCS], max[IEEE_8021QAZ_MAX_TCS];
638 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
639 int err;
640 /* naively give each TC a bwg to map onto CEE hardware */
641 __u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7};
642
643 if (!adapter->ixgbe_ieee_ets) {
644 adapter->ixgbe_ieee_ets = kmalloc(sizeof(struct ieee_ets),
645 GFP_KERNEL);
646 if (!adapter->ixgbe_ieee_ets)
647 return -ENOMEM;
648 }
649
650
651 memcpy(adapter->ixgbe_ieee_ets, ets, sizeof(*adapter->ixgbe_ieee_ets));
652
653 ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame);
654 err = ixgbe_dcb_hw_ets_config(&adapter->hw, refill, max,
655 bwg_id, ets->tc_tsa);
656 return err;
657}
658
659static int ixgbe_dcbnl_ieee_getpfc(struct net_device *dev,
660 struct ieee_pfc *pfc)
661{
662 struct ixgbe_adapter *adapter = netdev_priv(dev);
663 struct ieee_pfc *my_pfc = adapter->ixgbe_ieee_pfc;
664 int i;
665
666 /* No IEEE PFC settings available */
667 if (!my_pfc)
668 return -EINVAL;
669
670 pfc->pfc_cap = MAX_TRAFFIC_CLASS;
671 pfc->pfc_en = my_pfc->pfc_en;
672 pfc->mbc = my_pfc->mbc;
673 pfc->delay = my_pfc->delay;
674
675 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
676 pfc->requests[i] = adapter->stats.pxoffrxc[i];
677 pfc->indications[i] = adapter->stats.pxofftxc[i];
678 }
679
680 return 0;
681}
682
683static int ixgbe_dcbnl_ieee_setpfc(struct net_device *dev,
684 struct ieee_pfc *pfc)
685{
686 struct ixgbe_adapter *adapter = netdev_priv(dev);
687 int err;
688
689 if (!adapter->ixgbe_ieee_pfc) {
690 adapter->ixgbe_ieee_pfc = kmalloc(sizeof(struct ieee_pfc),
691 GFP_KERNEL);
692 if (!adapter->ixgbe_ieee_pfc)
693 return -ENOMEM;
694 }
695
696 memcpy(adapter->ixgbe_ieee_pfc, pfc, sizeof(*adapter->ixgbe_ieee_pfc));
697 err = ixgbe_dcb_hw_pfc_config(&adapter->hw, pfc->pfc_en);
698 return err;
699}
700
594const struct dcbnl_rtnl_ops dcbnl_ops = { 701const struct dcbnl_rtnl_ops dcbnl_ops = {
702 .ieee_getets = ixgbe_dcbnl_ieee_getets,
703 .ieee_setets = ixgbe_dcbnl_ieee_setets,
704 .ieee_getpfc = ixgbe_dcbnl_ieee_getpfc,
705 .ieee_setpfc = ixgbe_dcbnl_ieee_setpfc,
595 .getstate = ixgbe_dcbnl_get_state, 706 .getstate = ixgbe_dcbnl_get_state,
596 .setstate = ixgbe_dcbnl_set_state, 707 .setstate = ixgbe_dcbnl_set_state,
597 .getpermhwaddr = ixgbe_dcbnl_get_perm_hw_addr, 708 .getpermhwaddr = ixgbe_dcbnl_get_perm_hw_addr,
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index 2002ea88ca2a..309272f8f103 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -152,7 +152,17 @@ static int ixgbe_get_settings(struct net_device *netdev,
152 ecmd->supported |= (SUPPORTED_1000baseT_Full | 152 ecmd->supported |= (SUPPORTED_1000baseT_Full |
153 SUPPORTED_Autoneg); 153 SUPPORTED_Autoneg);
154 154
155 switch (hw->mac.type) {
156 case ixgbe_mac_X540:
157 ecmd->supported |= SUPPORTED_100baseT_Full;
158 break;
159 default:
160 break;
161 }
162
155 ecmd->advertising = ADVERTISED_Autoneg; 163 ecmd->advertising = ADVERTISED_Autoneg;
164 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
165 ecmd->advertising |= ADVERTISED_100baseT_Full;
156 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 166 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
157 ecmd->advertising |= ADVERTISED_10000baseT_Full; 167 ecmd->advertising |= ADVERTISED_10000baseT_Full;
158 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 168 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
@@ -167,6 +177,15 @@ static int ixgbe_get_settings(struct net_device *netdev,
167 ecmd->advertising |= (ADVERTISED_10000baseT_Full | 177 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
168 ADVERTISED_1000baseT_Full); 178 ADVERTISED_1000baseT_Full);
169 179
180 switch (hw->mac.type) {
181 case ixgbe_mac_X540:
182 if (!(ecmd->advertising & ADVERTISED_100baseT_Full))
183 ecmd->advertising |= (ADVERTISED_100baseT_Full);
184 break;
185 default:
186 break;
187 }
188
170 if (hw->phy.media_type == ixgbe_media_type_copper) { 189 if (hw->phy.media_type == ixgbe_media_type_copper) {
171 ecmd->supported |= SUPPORTED_TP; 190 ecmd->supported |= SUPPORTED_TP;
172 ecmd->advertising |= ADVERTISED_TP; 191 ecmd->advertising |= ADVERTISED_TP;
@@ -271,8 +290,19 @@ static int ixgbe_get_settings(struct net_device *netdev,
271 290
272 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 291 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
273 if (link_up) { 292 if (link_up) {
274 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ? 293 switch (link_speed) {
275 SPEED_10000 : SPEED_1000; 294 case IXGBE_LINK_SPEED_10GB_FULL:
295 ecmd->speed = SPEED_10000;
296 break;
297 case IXGBE_LINK_SPEED_1GB_FULL:
298 ecmd->speed = SPEED_1000;
299 break;
300 case IXGBE_LINK_SPEED_100_FULL:
301 ecmd->speed = SPEED_100;
302 break;
303 default:
304 break;
305 }
276 ecmd->duplex = DUPLEX_FULL; 306 ecmd->duplex = DUPLEX_FULL;
277 } else { 307 } else {
278 ecmd->speed = -1; 308 ecmd->speed = -1;
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index fbae703b46d7..4f81b5a00775 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -648,7 +648,7 @@ void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
648 * 648 *
649 * Returns : a tc index for use in range 0-7, or 0-3 649 * Returns : a tc index for use in range 0-7, or 0-3
650 */ 650 */
651u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx) 651static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
652{ 652{
653 int tc = -1; 653 int tc = -1;
654 int dcb_i = adapter->ring_feature[RING_F_DCB].indices; 654 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
@@ -5173,7 +5173,6 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5173 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5173 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5174 adapter->dcb_cfg.rx_pba_cfg = pba_equal; 5174 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5175 adapter->dcb_cfg.pfc_mode_enable = false; 5175 adapter->dcb_cfg.pfc_mode_enable = false;
5176 adapter->dcb_cfg.round_robin_enable = false;
5177 adapter->dcb_set_bitmap = 0x00; 5176 adapter->dcb_set_bitmap = 0x00;
5178 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, 5177 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5179 adapter->ring_feature[RING_F_DCB].indices); 5178 adapter->ring_feature[RING_F_DCB].indices);
@@ -5610,6 +5609,10 @@ static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5610 } 5609 }
5611 5610
5612 ixgbe_clear_interrupt_scheme(adapter); 5611 ixgbe_clear_interrupt_scheme(adapter);
5612#ifdef CONFIG_DCB
5613 kfree(adapter->ixgbe_ieee_pfc);
5614 kfree(adapter->ixgbe_ieee_ets);
5615#endif
5613 5616
5614#ifdef CONFIG_PM 5617#ifdef CONFIG_PM
5615 retval = pci_save_state(pdev); 5618 retval = pci_save_state(pdev);
@@ -6099,7 +6102,10 @@ static void ixgbe_watchdog_task(struct work_struct *work)
6099 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? 6102 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6100 "10 Gbps" : 6103 "10 Gbps" :
6101 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? 6104 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6102 "1 Gbps" : "unknown speed")), 6105 "1 Gbps" :
6106 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6107 "100 Mbps" :
6108 "unknown speed"))),
6103 ((flow_rx && flow_tx) ? "RX/TX" : 6109 ((flow_rx && flow_tx) ? "RX/TX" :
6104 (flow_rx ? "RX" : 6110 (flow_rx ? "RX" :
6105 (flow_tx ? "TX" : "None")))); 6111 (flow_tx ? "TX" : "None"))));
@@ -7704,16 +7710,6 @@ static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7704 7710
7705#endif /* CONFIG_IXGBE_DCA */ 7711#endif /* CONFIG_IXGBE_DCA */
7706 7712
7707/**
7708 * ixgbe_get_hw_dev return device
7709 * used by hardware layer to print debugging information
7710 **/
7711struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7712{
7713 struct ixgbe_adapter *adapter = hw->back;
7714 return adapter->netdev;
7715}
7716
7717module_exit(ixgbe_exit_module); 7713module_exit(ixgbe_exit_module);
7718 7714
7719/* ixgbe_main.c */ 7715/* ixgbe_main.c */
diff --git a/drivers/net/ixgbe/ixgbe_mbx.c b/drivers/net/ixgbe/ixgbe_mbx.c
index ea82c5a1cd3e..f215c4c296c4 100644
--- a/drivers/net/ixgbe/ixgbe_mbx.c
+++ b/drivers/net/ixgbe/ixgbe_mbx.c
@@ -437,6 +437,7 @@ out_no_read:
437 return ret_val; 437 return ret_val;
438} 438}
439 439
440#ifdef CONFIG_PCI_IOV
440/** 441/**
441 * ixgbe_init_mbx_params_pf - set initial values for pf mailbox 442 * ixgbe_init_mbx_params_pf - set initial values for pf mailbox
442 * @hw: pointer to the HW structure 443 * @hw: pointer to the HW structure
@@ -465,6 +466,7 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)
465 break; 466 break;
466 } 467 }
467} 468}
469#endif /* CONFIG_PCI_IOV */
468 470
469struct ixgbe_mbx_operations mbx_ops_generic = { 471struct ixgbe_mbx_operations mbx_ops_generic = {
470 .read = ixgbe_read_mbx_pf, 472 .read = ixgbe_read_mbx_pf,
diff --git a/drivers/net/ixgbe/ixgbe_mbx.h b/drivers/net/ixgbe/ixgbe_mbx.h
index 3df9b1590218..ada0ce32a7a6 100644
--- a/drivers/net/ixgbe/ixgbe_mbx.h
+++ b/drivers/net/ixgbe/ixgbe_mbx.h
@@ -86,7 +86,9 @@ s32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16);
86s32 ixgbe_check_for_msg(struct ixgbe_hw *, u16); 86s32 ixgbe_check_for_msg(struct ixgbe_hw *, u16);
87s32 ixgbe_check_for_ack(struct ixgbe_hw *, u16); 87s32 ixgbe_check_for_ack(struct ixgbe_hw *, u16);
88s32 ixgbe_check_for_rst(struct ixgbe_hw *, u16); 88s32 ixgbe_check_for_rst(struct ixgbe_hw *, u16);
89#ifdef CONFIG_PCI_IOV
89void ixgbe_init_mbx_params_pf(struct ixgbe_hw *); 90void ixgbe_init_mbx_params_pf(struct ixgbe_hw *);
91#endif /* CONFIG_PCI_IOV */
90 92
91extern struct ixgbe_mbx_operations mbx_ops_generic; 93extern struct ixgbe_mbx_operations mbx_ops_generic;
92 94
diff --git a/include/linux/dcbnl.h b/include/linux/dcbnl.h
index 68cd248f6d3e..cd8d518efa3b 100644
--- a/include/linux/dcbnl.h
+++ b/include/linux/dcbnl.h
@@ -25,6 +25,11 @@
25/* IEEE 802.1Qaz std supported values */ 25/* IEEE 802.1Qaz std supported values */
26#define IEEE_8021QAZ_MAX_TCS 8 26#define IEEE_8021QAZ_MAX_TCS 8
27 27
28#define IEEE_8021QAZ_TSA_STRICT 0
29#define IEEE_8021QAZ_TSA_CB_SHABER 1
30#define IEEE_8021QAZ_TSA_ETS 2
31#define IEEE_8021QAZ_TSA_VENDOR 255
32
28/* This structure contains the IEEE 802.1Qaz ETS managed object 33/* This structure contains the IEEE 802.1Qaz ETS managed object
29 * 34 *
30 * @willing: willing bit in ETS configuratin TLV 35 * @willing: willing bit in ETS configuratin TLV