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authorSakari Ailus <sakari.ailus@iki.fi>2011-02-12 16:05:06 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-03-22 03:53:46 -0400
commit448de7e7850b804bc8f5efa60305a83333c257bf (patch)
treeb88e08e84457715551b7f4b84ec3342a34e7d563
parentc30b46e58b31a0fc420049e21117444862fc7cb7 (diff)
[media] omap3isp: OMAP3 ISP core
The Image Signal Processor provides the system interface and the processing capability to connect RAW or YUV image-sensor modules to the OMAP3. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> Signed-off-by: David Cohen <dacohen@gmail.com> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Vimarsh Zutshi <vimarsh.zutshi@gmail.com> Signed-off-by: Tuukka Toivonen <tuukkat76@gmail.com> Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Signed-off-by: Antti Koskipaa <akoskipa@gmail.com> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: RaniSuneela <r-m@ti.com> Signed-off-by: Atanas Filipov <afilipov@mm-sol.com> Signed-off-by: Gjorgji Rosikopulos <grosikopulos@mm-sol.com> Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Nayden Kanchev <nkanchev@mm-sol.com> Signed-off-by: Phil Carmody <ext-phil.2.carmody@nokia.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Dominic Curran <dcurran@ti.com> Signed-off-by: Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi> Signed-off-by: Pallavi Kulkarni <p-kulkarni@ti.com> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/media/video/omap3isp/isp.c2220
-rw-r--r--drivers/media/video/omap3isp/isp.h430
-rw-r--r--drivers/media/video/omap3isp/ispreg.h1589
-rw-r--r--include/linux/omap3isp.h646
4 files changed, 4885 insertions, 0 deletions
diff --git a/drivers/media/video/omap3isp/isp.c b/drivers/media/video/omap3isp/isp.c
new file mode 100644
index 000000000000..1a9963bd6d40
--- /dev/null
+++ b/drivers/media/video/omap3isp/isp.c
@@ -0,0 +1,2220 @@
1/*
2 * isp.c
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2006-2010 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * Contributors:
13 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 * Sakari Ailus <sakari.ailus@iki.fi>
15 * David Cohen <dacohen@gmail.com>
16 * Stanimir Varbanov <svarbanov@mm-sol.com>
17 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
18 * Tuukka Toivonen <tuukkat76@gmail.com>
19 * Sergio Aguirre <saaguirre@ti.com>
20 * Antti Koskipaa <akoskipa@gmail.com>
21 * Ivan T. Ivanov <iivanov@mm-sol.com>
22 * RaniSuneela <r-m@ti.com>
23 * Atanas Filipov <afilipov@mm-sol.com>
24 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
25 * Hiroshi DOYU <hiroshi.doyu@nokia.com>
26 * Nayden Kanchev <nkanchev@mm-sol.com>
27 * Phil Carmody <ext-phil.2.carmody@nokia.com>
28 * Artem Bityutskiy <artem.bityutskiy@nokia.com>
29 * Dominic Curran <dcurran@ti.com>
30 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
31 * Pallavi Kulkarni <p-kulkarni@ti.com>
32 * Vaibhav Hiremath <hvaibhav@ti.com>
33 * Mohit Jalori <mjalori@ti.com>
34 * Sameer Venkatraman <sameerv@ti.com>
35 * Senthilvadivu Guruswamy <svadivu@ti.com>
36 * Thara Gopinath <thara@ti.com>
37 * Toni Leinonen <toni.leinonen@nokia.com>
38 * Troy Laramy <t-laramy@ti.com>
39 *
40 * This program is free software; you can redistribute it and/or modify
41 * it under the terms of the GNU General Public License version 2 as
42 * published by the Free Software Foundation.
43 *
44 * This program is distributed in the hope that it will be useful, but
45 * WITHOUT ANY WARRANTY; without even the implied warranty of
46 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
47 * General Public License for more details.
48 *
49 * You should have received a copy of the GNU General Public License
50 * along with this program; if not, write to the Free Software
51 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
52 * 02110-1301 USA
53 */
54
55#include <asm/cacheflush.h>
56
57#include <linux/clk.h>
58#include <linux/delay.h>
59#include <linux/device.h>
60#include <linux/dma-mapping.h>
61#include <linux/i2c.h>
62#include <linux/interrupt.h>
63#include <linux/module.h>
64#include <linux/platform_device.h>
65#include <linux/regulator/consumer.h>
66#include <linux/slab.h>
67#include <linux/sched.h>
68#include <linux/vmalloc.h>
69
70#include <media/v4l2-common.h>
71#include <media/v4l2-device.h>
72
73#include "isp.h"
74#include "ispreg.h"
75#include "ispccdc.h"
76#include "isppreview.h"
77#include "ispresizer.h"
78#include "ispcsi2.h"
79#include "ispccp2.h"
80#include "isph3a.h"
81#include "isphist.h"
82
83static unsigned int autoidle;
84module_param(autoidle, int, 0444);
85MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
86
87static void isp_save_ctx(struct isp_device *isp);
88
89static void isp_restore_ctx(struct isp_device *isp);
90
91static const struct isp_res_mapping isp_res_maps[] = {
92 {
93 .isp_rev = ISP_REVISION_2_0,
94 .map = 1 << OMAP3_ISP_IOMEM_MAIN |
95 1 << OMAP3_ISP_IOMEM_CCP2 |
96 1 << OMAP3_ISP_IOMEM_CCDC |
97 1 << OMAP3_ISP_IOMEM_HIST |
98 1 << OMAP3_ISP_IOMEM_H3A |
99 1 << OMAP3_ISP_IOMEM_PREV |
100 1 << OMAP3_ISP_IOMEM_RESZ |
101 1 << OMAP3_ISP_IOMEM_SBL |
102 1 << OMAP3_ISP_IOMEM_CSI2A_REGS1 |
103 1 << OMAP3_ISP_IOMEM_CSIPHY2,
104 },
105 {
106 .isp_rev = ISP_REVISION_15_0,
107 .map = 1 << OMAP3_ISP_IOMEM_MAIN |
108 1 << OMAP3_ISP_IOMEM_CCP2 |
109 1 << OMAP3_ISP_IOMEM_CCDC |
110 1 << OMAP3_ISP_IOMEM_HIST |
111 1 << OMAP3_ISP_IOMEM_H3A |
112 1 << OMAP3_ISP_IOMEM_PREV |
113 1 << OMAP3_ISP_IOMEM_RESZ |
114 1 << OMAP3_ISP_IOMEM_SBL |
115 1 << OMAP3_ISP_IOMEM_CSI2A_REGS1 |
116 1 << OMAP3_ISP_IOMEM_CSIPHY2 |
117 1 << OMAP3_ISP_IOMEM_CSI2A_REGS2 |
118 1 << OMAP3_ISP_IOMEM_CSI2C_REGS1 |
119 1 << OMAP3_ISP_IOMEM_CSIPHY1 |
120 1 << OMAP3_ISP_IOMEM_CSI2C_REGS2,
121 },
122};
123
124/* Structure for saving/restoring ISP module registers */
125static struct isp_reg isp_reg_list[] = {
126 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
127 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
128 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
129 {0, ISP_TOK_TERM, 0}
130};
131
132/*
133 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
134 * @isp: OMAP3 ISP device
135 *
136 * In order to force posting of pending writes, we need to write and
137 * readback the same register, in this case the revision register.
138 *
139 * See this link for reference:
140 * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
141 */
142void omap3isp_flush(struct isp_device *isp)
143{
144 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
145 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
146}
147
148/*
149 * isp_enable_interrupts - Enable ISP interrupts.
150 * @isp: OMAP3 ISP device
151 */
152static void isp_enable_interrupts(struct isp_device *isp)
153{
154 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
155 | IRQ0ENABLE_CSIB_IRQ
156 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
157 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
158 | IRQ0ENABLE_CCDC_VD0_IRQ
159 | IRQ0ENABLE_CCDC_VD1_IRQ
160 | IRQ0ENABLE_HS_VS_IRQ
161 | IRQ0ENABLE_HIST_DONE_IRQ
162 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
163 | IRQ0ENABLE_H3A_AF_DONE_IRQ
164 | IRQ0ENABLE_PRV_DONE_IRQ
165 | IRQ0ENABLE_RSZ_DONE_IRQ;
166
167 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
168 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
169}
170
171/*
172 * isp_disable_interrupts - Disable ISP interrupts.
173 * @isp: OMAP3 ISP device
174 */
175static void isp_disable_interrupts(struct isp_device *isp)
176{
177 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
178}
179
180/**
181 * isp_set_xclk - Configures the specified cam_xclk to the desired frequency.
182 * @isp: OMAP3 ISP device
183 * @xclk: Desired frequency of the clock in Hz. 0 = stable low, 1 is stable high
184 * @xclksel: XCLK to configure (0 = A, 1 = B).
185 *
186 * Configures the specified MCLK divisor in the ISP timing control register
187 * (TCTRL_CTRL) to generate the desired xclk clock value.
188 *
189 * Divisor = cam_mclk_hz / xclk
190 *
191 * Returns the final frequency that is actually being generated
192 **/
193static u32 isp_set_xclk(struct isp_device *isp, u32 xclk, u8 xclksel)
194{
195 u32 divisor;
196 u32 currentxclk;
197 unsigned long mclk_hz;
198
199 if (!omap3isp_get(isp))
200 return 0;
201
202 mclk_hz = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
203
204 if (xclk >= mclk_hz) {
205 divisor = ISPTCTRL_CTRL_DIV_BYPASS;
206 currentxclk = mclk_hz;
207 } else if (xclk >= 2) {
208 divisor = mclk_hz / xclk;
209 if (divisor >= ISPTCTRL_CTRL_DIV_BYPASS)
210 divisor = ISPTCTRL_CTRL_DIV_BYPASS - 1;
211 currentxclk = mclk_hz / divisor;
212 } else {
213 divisor = xclk;
214 currentxclk = 0;
215 }
216
217 switch (xclksel) {
218 case 0:
219 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
220 ISPTCTRL_CTRL_DIVA_MASK,
221 divisor << ISPTCTRL_CTRL_DIVA_SHIFT);
222 dev_dbg(isp->dev, "isp_set_xclk(): cam_xclka set to %d Hz\n",
223 currentxclk);
224 break;
225 case 1:
226 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
227 ISPTCTRL_CTRL_DIVB_MASK,
228 divisor << ISPTCTRL_CTRL_DIVB_SHIFT);
229 dev_dbg(isp->dev, "isp_set_xclk(): cam_xclkb set to %d Hz\n",
230 currentxclk);
231 break;
232 default:
233 omap3isp_put(isp);
234 dev_dbg(isp->dev, "ISP_ERR: isp_set_xclk(): Invalid requested "
235 "xclk. Must be 0 (A) or 1 (B).\n");
236 return -EINVAL;
237 }
238
239 /* Do we go from stable whatever to clock? */
240 if (divisor >= 2 && isp->xclk_divisor[xclksel] < 2)
241 omap3isp_get(isp);
242 /* Stopping the clock. */
243 else if (divisor < 2 && isp->xclk_divisor[xclksel] >= 2)
244 omap3isp_put(isp);
245
246 isp->xclk_divisor[xclksel] = divisor;
247
248 omap3isp_put(isp);
249
250 return currentxclk;
251}
252
253/*
254 * isp_power_settings - Sysconfig settings, for Power Management.
255 * @isp: OMAP3 ISP device
256 * @idle: Consider idle state.
257 *
258 * Sets the power settings for the ISP, and SBL bus.
259 */
260static void isp_power_settings(struct isp_device *isp, int idle)
261{
262 isp_reg_writel(isp,
263 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
264 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
265 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
266 ((isp->revision == ISP_REVISION_15_0) ?
267 ISP_SYSCONFIG_AUTOIDLE : 0),
268 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
269
270 if (isp->autoidle)
271 isp_reg_writel(isp, ISPCTRL_SBL_AUTOIDLE, OMAP3_ISP_IOMEM_MAIN,
272 ISP_CTRL);
273}
274
275/*
276 * Configure the bridge and lane shifter. Valid inputs are
277 *
278 * CCDC_INPUT_PARALLEL: Parallel interface
279 * CCDC_INPUT_CSI2A: CSI2a receiver
280 * CCDC_INPUT_CCP2B: CCP2b receiver
281 * CCDC_INPUT_CSI2C: CSI2c receiver
282 *
283 * The bridge and lane shifter are configured according to the selected input
284 * and the ISP platform data.
285 */
286void omap3isp_configure_bridge(struct isp_device *isp,
287 enum ccdc_input_entity input,
288 const struct isp_parallel_platform_data *pdata)
289{
290 u32 ispctrl_val;
291
292 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
293 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
294 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
295 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
296 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
297
298 switch (input) {
299 case CCDC_INPUT_PARALLEL:
300 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
301 ispctrl_val |= pdata->data_lane_shift << ISPCTRL_SHIFT_SHIFT;
302 ispctrl_val |= pdata->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
303 ispctrl_val |= pdata->bridge << ISPCTRL_PAR_BRIDGE_SHIFT;
304 break;
305
306 case CCDC_INPUT_CSI2A:
307 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
308 break;
309
310 case CCDC_INPUT_CCP2B:
311 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
312 break;
313
314 case CCDC_INPUT_CSI2C:
315 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
316 break;
317
318 default:
319 return;
320 }
321
322 ispctrl_val &= ~ISPCTRL_SYNC_DETECT_MASK;
323 ispctrl_val |= ISPCTRL_SYNC_DETECT_VSRISE;
324
325 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
326}
327
328/**
329 * isp_set_pixel_clock - Configures the ISP pixel clock
330 * @isp: OMAP3 ISP device
331 * @pixelclk: Average pixel clock in Hz
332 *
333 * Set the average pixel clock required by the sensor. The ISP will use the
334 * lowest possible memory bandwidth settings compatible with the clock.
335 **/
336static void isp_set_pixel_clock(struct isp_device *isp, unsigned int pixelclk)
337{
338 isp->isp_ccdc.vpcfg.pixelclk = pixelclk;
339}
340
341void omap3isp_hist_dma_done(struct isp_device *isp)
342{
343 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
344 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
345 /* Histogram cannot be enabled in this frame anymore */
346 atomic_set(&isp->isp_hist.buf_err, 1);
347 dev_dbg(isp->dev, "hist: Out of synchronization with "
348 "CCDC. Ignoring next buffer.\n");
349 }
350}
351
352static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
353{
354 static const char *name[] = {
355 "CSIA_IRQ",
356 "res1",
357 "res2",
358 "CSIB_LCM_IRQ",
359 "CSIB_IRQ",
360 "res5",
361 "res6",
362 "res7",
363 "CCDC_VD0_IRQ",
364 "CCDC_VD1_IRQ",
365 "CCDC_VD2_IRQ",
366 "CCDC_ERR_IRQ",
367 "H3A_AF_DONE_IRQ",
368 "H3A_AWB_DONE_IRQ",
369 "res14",
370 "res15",
371 "HIST_DONE_IRQ",
372 "CCDC_LSC_DONE",
373 "CCDC_LSC_PREFETCH_COMPLETED",
374 "CCDC_LSC_PREFETCH_ERROR",
375 "PRV_DONE_IRQ",
376 "CBUFF_IRQ",
377 "res22",
378 "res23",
379 "RSZ_DONE_IRQ",
380 "OVF_IRQ",
381 "res26",
382 "res27",
383 "MMU_ERR_IRQ",
384 "OCP_ERR_IRQ",
385 "SEC_ERR_IRQ",
386 "HS_VS_IRQ",
387 };
388 int i;
389
390 dev_dbg(isp->dev, "");
391
392 for (i = 0; i < ARRAY_SIZE(name); i++) {
393 if ((1 << i) & irqstatus)
394 printk(KERN_CONT "%s ", name[i]);
395 }
396 printk(KERN_CONT "\n");
397}
398
399static void isp_isr_sbl(struct isp_device *isp)
400{
401 struct device *dev = isp->dev;
402 u32 sbl_pcr;
403
404 /*
405 * Handle shared buffer logic overflows for video buffers.
406 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
407 */
408 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
409 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
410 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
411
412 if (sbl_pcr)
413 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
414
415 if (sbl_pcr & (ISPSBL_PCR_CCDC_WBL_OVF | ISPSBL_PCR_CSIA_WBL_OVF
416 | ISPSBL_PCR_CSIB_WBL_OVF)) {
417 isp->isp_ccdc.error = 1;
418 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
419 isp->isp_prev.error = 1;
420 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
421 isp->isp_res.error = 1;
422 }
423
424 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
425 isp->isp_prev.error = 1;
426 if (isp->isp_res.input == RESIZER_INPUT_VP &&
427 !(isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER))
428 isp->isp_res.error = 1;
429 }
430
431 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
432 | ISPSBL_PCR_RSZ2_WBL_OVF
433 | ISPSBL_PCR_RSZ3_WBL_OVF
434 | ISPSBL_PCR_RSZ4_WBL_OVF))
435 isp->isp_res.error = 1;
436
437 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
438 omap3isp_stat_sbl_overflow(&isp->isp_af);
439
440 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
441 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
442}
443
444/*
445 * isp_isr - Interrupt Service Routine for Camera ISP module.
446 * @irq: Not used currently.
447 * @_isp: Pointer to the OMAP3 ISP device
448 *
449 * Handles the corresponding callback if plugged in.
450 *
451 * Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the
452 * IRQ wasn't handled.
453 */
454static irqreturn_t isp_isr(int irq, void *_isp)
455{
456 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
457 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
458 IRQ0STATUS_CCDC_VD0_IRQ |
459 IRQ0STATUS_CCDC_VD1_IRQ |
460 IRQ0STATUS_HS_VS_IRQ;
461 struct isp_device *isp = _isp;
462 u32 irqstatus;
463 int ret;
464
465 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
466 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
467
468 isp_isr_sbl(isp);
469
470 if (irqstatus & IRQ0STATUS_CSIA_IRQ) {
471 ret = omap3isp_csi2_isr(&isp->isp_csi2a);
472 if (ret)
473 isp->isp_ccdc.error = 1;
474 }
475
476 if (irqstatus & IRQ0STATUS_CSIB_IRQ) {
477 ret = omap3isp_ccp2_isr(&isp->isp_ccp2);
478 if (ret)
479 isp->isp_ccdc.error = 1;
480 }
481
482 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
483 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
484 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
485 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
486 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
487 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
488 omap3isp_stat_isr_frame_sync(&isp->isp_af);
489 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
490 }
491
492 if (irqstatus & ccdc_events)
493 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
494
495 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
496 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
497 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
498 omap3isp_preview_isr(&isp->isp_prev);
499 }
500
501 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
502 omap3isp_resizer_isr(&isp->isp_res);
503
504 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
505 omap3isp_stat_isr(&isp->isp_aewb);
506
507 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
508 omap3isp_stat_isr(&isp->isp_af);
509
510 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
511 omap3isp_stat_isr(&isp->isp_hist);
512
513 omap3isp_flush(isp);
514
515#if defined(DEBUG) && defined(ISP_ISR_DEBUG)
516 isp_isr_dbg(isp, irqstatus);
517#endif
518
519 return IRQ_HANDLED;
520}
521
522/* -----------------------------------------------------------------------------
523 * Pipeline power management
524 *
525 * Entities must be powered up when part of a pipeline that contains at least
526 * one open video device node.
527 *
528 * To achieve this use the entity use_count field to track the number of users.
529 * For entities corresponding to video device nodes the use_count field stores
530 * the users count of the node. For entities corresponding to subdevs the
531 * use_count field stores the total number of users of all video device nodes
532 * in the pipeline.
533 *
534 * The omap3isp_pipeline_pm_use() function must be called in the open() and
535 * close() handlers of video device nodes. It increments or decrements the use
536 * count of all subdev entities in the pipeline.
537 *
538 * To react to link management on powered pipelines, the link setup notification
539 * callback updates the use count of all entities in the source and sink sides
540 * of the link.
541 */
542
543/*
544 * isp_pipeline_pm_use_count - Count the number of users of a pipeline
545 * @entity: The entity
546 *
547 * Return the total number of users of all video device nodes in the pipeline.
548 */
549static int isp_pipeline_pm_use_count(struct media_entity *entity)
550{
551 struct media_entity_graph graph;
552 int use = 0;
553
554 media_entity_graph_walk_start(&graph, entity);
555
556 while ((entity = media_entity_graph_walk_next(&graph))) {
557 if (media_entity_type(entity) == MEDIA_ENT_T_DEVNODE)
558 use += entity->use_count;
559 }
560
561 return use;
562}
563
564/*
565 * isp_pipeline_pm_power_one - Apply power change to an entity
566 * @entity: The entity
567 * @change: Use count change
568 *
569 * Change the entity use count by @change. If the entity is a subdev update its
570 * power state by calling the core::s_power operation when the use count goes
571 * from 0 to != 0 or from != 0 to 0.
572 *
573 * Return 0 on success or a negative error code on failure.
574 */
575static int isp_pipeline_pm_power_one(struct media_entity *entity, int change)
576{
577 struct v4l2_subdev *subdev;
578 int ret;
579
580 subdev = media_entity_type(entity) == MEDIA_ENT_T_V4L2_SUBDEV
581 ? media_entity_to_v4l2_subdev(entity) : NULL;
582
583 if (entity->use_count == 0 && change > 0 && subdev != NULL) {
584 ret = v4l2_subdev_call(subdev, core, s_power, 1);
585 if (ret < 0 && ret != -ENOIOCTLCMD)
586 return ret;
587 }
588
589 entity->use_count += change;
590 WARN_ON(entity->use_count < 0);
591
592 if (entity->use_count == 0 && change < 0 && subdev != NULL)
593 v4l2_subdev_call(subdev, core, s_power, 0);
594
595 return 0;
596}
597
598/*
599 * isp_pipeline_pm_power - Apply power change to all entities in a pipeline
600 * @entity: The entity
601 * @change: Use count change
602 *
603 * Walk the pipeline to update the use count and the power state of all non-node
604 * entities.
605 *
606 * Return 0 on success or a negative error code on failure.
607 */
608static int isp_pipeline_pm_power(struct media_entity *entity, int change)
609{
610 struct media_entity_graph graph;
611 struct media_entity *first = entity;
612 int ret = 0;
613
614 if (!change)
615 return 0;
616
617 media_entity_graph_walk_start(&graph, entity);
618
619 while (!ret && (entity = media_entity_graph_walk_next(&graph)))
620 if (media_entity_type(entity) != MEDIA_ENT_T_DEVNODE)
621 ret = isp_pipeline_pm_power_one(entity, change);
622
623 if (!ret)
624 return 0;
625
626 media_entity_graph_walk_start(&graph, first);
627
628 while ((first = media_entity_graph_walk_next(&graph))
629 && first != entity)
630 if (media_entity_type(first) != MEDIA_ENT_T_DEVNODE)
631 isp_pipeline_pm_power_one(first, -change);
632
633 return ret;
634}
635
636/*
637 * omap3isp_pipeline_pm_use - Update the use count of an entity
638 * @entity: The entity
639 * @use: Use (1) or stop using (0) the entity
640 *
641 * Update the use count of all entities in the pipeline and power entities on or
642 * off accordingly.
643 *
644 * Return 0 on success or a negative error code on failure. Powering entities
645 * off is assumed to never fail. No failure can occur when the use parameter is
646 * set to 0.
647 */
648int omap3isp_pipeline_pm_use(struct media_entity *entity, int use)
649{
650 int change = use ? 1 : -1;
651 int ret;
652
653 mutex_lock(&entity->parent->graph_mutex);
654
655 /* Apply use count to node. */
656 entity->use_count += change;
657 WARN_ON(entity->use_count < 0);
658
659 /* Apply power change to connected non-nodes. */
660 ret = isp_pipeline_pm_power(entity, change);
661
662 mutex_unlock(&entity->parent->graph_mutex);
663
664 return ret;
665}
666
667/*
668 * isp_pipeline_link_notify - Link management notification callback
669 * @source: Pad at the start of the link
670 * @sink: Pad at the end of the link
671 * @flags: New link flags that will be applied
672 *
673 * React to link management on powered pipelines by updating the use count of
674 * all entities in the source and sink sides of the link. Entities are powered
675 * on or off accordingly.
676 *
677 * Return 0 on success or a negative error code on failure. Powering entities
678 * off is assumed to never fail. This function will not fail for disconnection
679 * events.
680 */
681static int isp_pipeline_link_notify(struct media_pad *source,
682 struct media_pad *sink, u32 flags)
683{
684 int source_use = isp_pipeline_pm_use_count(source->entity);
685 int sink_use = isp_pipeline_pm_use_count(sink->entity);
686 int ret;
687
688 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
689 /* Powering off entities is assumed to never fail. */
690 isp_pipeline_pm_power(source->entity, -sink_use);
691 isp_pipeline_pm_power(sink->entity, -source_use);
692 return 0;
693 }
694
695 ret = isp_pipeline_pm_power(source->entity, sink_use);
696 if (ret < 0)
697 return ret;
698
699 ret = isp_pipeline_pm_power(sink->entity, source_use);
700 if (ret < 0)
701 isp_pipeline_pm_power(source->entity, -sink_use);
702
703 return ret;
704}
705
706/* -----------------------------------------------------------------------------
707 * Pipeline stream management
708 */
709
710/*
711 * isp_pipeline_enable - Enable streaming on a pipeline
712 * @pipe: ISP pipeline
713 * @mode: Stream mode (single shot or continuous)
714 *
715 * Walk the entities chain starting at the pipeline output video node and start
716 * all modules in the chain in the given mode.
717 *
718 * Return 0 if successfull, or the return value of the failed video::s_stream
719 * operation otherwise.
720 */
721static int isp_pipeline_enable(struct isp_pipeline *pipe,
722 enum isp_pipeline_stream_state mode)
723{
724 struct isp_device *isp = pipe->output->isp;
725 struct media_entity *entity;
726 struct media_pad *pad;
727 struct v4l2_subdev *subdev;
728 unsigned long flags;
729 int ret = 0;
730
731 spin_lock_irqsave(&pipe->lock, flags);
732 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
733 spin_unlock_irqrestore(&pipe->lock, flags);
734
735 pipe->do_propagation = false;
736
737 entity = &pipe->output->video.entity;
738 while (1) {
739 pad = &entity->pads[0];
740 if (!(pad->flags & MEDIA_PAD_FL_SINK))
741 break;
742
743 pad = media_entity_remote_source(pad);
744 if (pad == NULL ||
745 media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
746 break;
747
748 entity = pad->entity;
749 subdev = media_entity_to_v4l2_subdev(entity);
750
751 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
752 if (ret < 0 && ret != -ENOIOCTLCMD)
753 break;
754
755 if (subdev == &isp->isp_ccdc.subdev) {
756 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
757 s_stream, mode);
758 v4l2_subdev_call(&isp->isp_af.subdev, video,
759 s_stream, mode);
760 v4l2_subdev_call(&isp->isp_hist.subdev, video,
761 s_stream, mode);
762 pipe->do_propagation = true;
763 }
764 }
765
766 /* Frame number propagation. In continuous streaming mode the number
767 * is incremented in the frame start ISR. In mem-to-mem mode
768 * singleshot is used and frame start IRQs are not available.
769 * Thus we have to increment the number here.
770 */
771 if (pipe->do_propagation && mode == ISP_PIPELINE_STREAM_SINGLESHOT)
772 atomic_inc(&pipe->frame_number);
773
774 return ret;
775}
776
777static int isp_pipeline_wait_resizer(struct isp_device *isp)
778{
779 return omap3isp_resizer_busy(&isp->isp_res);
780}
781
782static int isp_pipeline_wait_preview(struct isp_device *isp)
783{
784 return omap3isp_preview_busy(&isp->isp_prev);
785}
786
787static int isp_pipeline_wait_ccdc(struct isp_device *isp)
788{
789 return omap3isp_stat_busy(&isp->isp_af)
790 || omap3isp_stat_busy(&isp->isp_aewb)
791 || omap3isp_stat_busy(&isp->isp_hist)
792 || omap3isp_ccdc_busy(&isp->isp_ccdc);
793}
794
795#define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
796
797static int isp_pipeline_wait(struct isp_device *isp,
798 int(*busy)(struct isp_device *isp))
799{
800 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
801
802 while (!time_after(jiffies, timeout)) {
803 if (!busy(isp))
804 return 0;
805 }
806
807 return 1;
808}
809
810/*
811 * isp_pipeline_disable - Disable streaming on a pipeline
812 * @pipe: ISP pipeline
813 *
814 * Walk the entities chain starting at the pipeline output video node and stop
815 * all modules in the chain. Wait synchronously for the modules to be stopped if
816 * necessary.
817 *
818 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
819 * can't be stopped (in which case a software reset of the ISP is probably
820 * necessary).
821 */
822static int isp_pipeline_disable(struct isp_pipeline *pipe)
823{
824 struct isp_device *isp = pipe->output->isp;
825 struct media_entity *entity;
826 struct media_pad *pad;
827 struct v4l2_subdev *subdev;
828 int failure = 0;
829 int ret;
830
831 /*
832 * We need to stop all the modules after CCDC first or they'll
833 * never stop since they may not get a full frame from CCDC.
834 */
835 entity = &pipe->output->video.entity;
836 while (1) {
837 pad = &entity->pads[0];
838 if (!(pad->flags & MEDIA_PAD_FL_SINK))
839 break;
840
841 pad = media_entity_remote_source(pad);
842 if (pad == NULL ||
843 media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
844 break;
845
846 entity = pad->entity;
847 subdev = media_entity_to_v4l2_subdev(entity);
848
849 if (subdev == &isp->isp_ccdc.subdev) {
850 v4l2_subdev_call(&isp->isp_aewb.subdev,
851 video, s_stream, 0);
852 v4l2_subdev_call(&isp->isp_af.subdev,
853 video, s_stream, 0);
854 v4l2_subdev_call(&isp->isp_hist.subdev,
855 video, s_stream, 0);
856 }
857
858 v4l2_subdev_call(subdev, video, s_stream, 0);
859
860 if (subdev == &isp->isp_res.subdev)
861 ret = isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
862 else if (subdev == &isp->isp_prev.subdev)
863 ret = isp_pipeline_wait(isp, isp_pipeline_wait_preview);
864 else if (subdev == &isp->isp_ccdc.subdev)
865 ret = isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
866 else
867 ret = 0;
868
869 if (ret) {
870 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
871 failure = -ETIMEDOUT;
872 }
873 }
874
875 return failure;
876}
877
878/*
879 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
880 * @pipe: ISP pipeline
881 * @state: Stream state (stopped, single shot or continuous)
882 *
883 * Set the pipeline to the given stream state. Pipelines can be started in
884 * single-shot or continuous mode.
885 *
886 * Return 0 if successfull, or the return value of the failed video::s_stream
887 * operation otherwise.
888 */
889int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
890 enum isp_pipeline_stream_state state)
891{
892 int ret;
893
894 if (state == ISP_PIPELINE_STREAM_STOPPED)
895 ret = isp_pipeline_disable(pipe);
896 else
897 ret = isp_pipeline_enable(pipe, state);
898 pipe->stream_state = state;
899
900 return ret;
901}
902
903/*
904 * isp_pipeline_resume - Resume streaming on a pipeline
905 * @pipe: ISP pipeline
906 *
907 * Resume video output and input and re-enable pipeline.
908 */
909static void isp_pipeline_resume(struct isp_pipeline *pipe)
910{
911 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
912
913 omap3isp_video_resume(pipe->output, !singleshot);
914 if (singleshot)
915 omap3isp_video_resume(pipe->input, 0);
916 isp_pipeline_enable(pipe, pipe->stream_state);
917}
918
919/*
920 * isp_pipeline_suspend - Suspend streaming on a pipeline
921 * @pipe: ISP pipeline
922 *
923 * Suspend pipeline.
924 */
925static void isp_pipeline_suspend(struct isp_pipeline *pipe)
926{
927 isp_pipeline_disable(pipe);
928}
929
930/*
931 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
932 * video node
933 * @me: ISP module's media entity
934 *
935 * Returns 1 if the entity has an enabled link to the output video node or 0
936 * otherwise. It's true only while pipeline can have no more than one output
937 * node.
938 */
939static int isp_pipeline_is_last(struct media_entity *me)
940{
941 struct isp_pipeline *pipe;
942 struct media_pad *pad;
943
944 if (!me->pipe)
945 return 0;
946 pipe = to_isp_pipeline(me);
947 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
948 return 0;
949 pad = media_entity_remote_source(&pipe->output->pad);
950 return pad->entity == me;
951}
952
953/*
954 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
955 * @me: ISP module's media entity
956 *
957 * Suspend the whole pipeline if module's entity has an enabled link to the
958 * output video node. It works only while pipeline can have no more than one
959 * output node.
960 */
961static void isp_suspend_module_pipeline(struct media_entity *me)
962{
963 if (isp_pipeline_is_last(me))
964 isp_pipeline_suspend(to_isp_pipeline(me));
965}
966
967/*
968 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
969 * @me: ISP module's media entity
970 *
971 * Resume the whole pipeline if module's entity has an enabled link to the
972 * output video node. It works only while pipeline can have no more than one
973 * output node.
974 */
975static void isp_resume_module_pipeline(struct media_entity *me)
976{
977 if (isp_pipeline_is_last(me))
978 isp_pipeline_resume(to_isp_pipeline(me));
979}
980
981/*
982 * isp_suspend_modules - Suspend ISP submodules.
983 * @isp: OMAP3 ISP device
984 *
985 * Returns 0 if suspend left in idle state all the submodules properly,
986 * or returns 1 if a general Reset is required to suspend the submodules.
987 */
988static int isp_suspend_modules(struct isp_device *isp)
989{
990 unsigned long timeout;
991
992 omap3isp_stat_suspend(&isp->isp_aewb);
993 omap3isp_stat_suspend(&isp->isp_af);
994 omap3isp_stat_suspend(&isp->isp_hist);
995 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
996 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
997 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
998 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
999 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
1000
1001 timeout = jiffies + ISP_STOP_TIMEOUT;
1002 while (omap3isp_stat_busy(&isp->isp_af)
1003 || omap3isp_stat_busy(&isp->isp_aewb)
1004 || omap3isp_stat_busy(&isp->isp_hist)
1005 || omap3isp_preview_busy(&isp->isp_prev)
1006 || omap3isp_resizer_busy(&isp->isp_res)
1007 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
1008 if (time_after(jiffies, timeout)) {
1009 dev_info(isp->dev, "can't stop modules.\n");
1010 return 1;
1011 }
1012 msleep(1);
1013 }
1014
1015 return 0;
1016}
1017
1018/*
1019 * isp_resume_modules - Resume ISP submodules.
1020 * @isp: OMAP3 ISP device
1021 */
1022static void isp_resume_modules(struct isp_device *isp)
1023{
1024 omap3isp_stat_resume(&isp->isp_aewb);
1025 omap3isp_stat_resume(&isp->isp_af);
1026 omap3isp_stat_resume(&isp->isp_hist);
1027 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1028 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1029 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1030 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1031 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1032}
1033
1034/*
1035 * isp_reset - Reset ISP with a timeout wait for idle.
1036 * @isp: OMAP3 ISP device
1037 */
1038static int isp_reset(struct isp_device *isp)
1039{
1040 unsigned long timeout = 0;
1041
1042 isp_reg_writel(isp,
1043 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1044 | ISP_SYSCONFIG_SOFTRESET,
1045 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1046 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1047 ISP_SYSSTATUS) & 0x1)) {
1048 if (timeout++ > 10000) {
1049 dev_alert(isp->dev, "cannot reset ISP\n");
1050 return -ETIMEDOUT;
1051 }
1052 udelay(1);
1053 }
1054
1055 return 0;
1056}
1057
1058/*
1059 * isp_save_context - Saves the values of the ISP module registers.
1060 * @isp: OMAP3 ISP device
1061 * @reg_list: Structure containing pairs of register address and value to
1062 * modify on OMAP.
1063 */
1064static void
1065isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1066{
1067 struct isp_reg *next = reg_list;
1068
1069 for (; next->reg != ISP_TOK_TERM; next++)
1070 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1071}
1072
1073/*
1074 * isp_restore_context - Restores the values of the ISP module registers.
1075 * @isp: OMAP3 ISP device
1076 * @reg_list: Structure containing pairs of register address and value to
1077 * modify on OMAP.
1078 */
1079static void
1080isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1081{
1082 struct isp_reg *next = reg_list;
1083
1084 for (; next->reg != ISP_TOK_TERM; next++)
1085 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1086}
1087
1088/*
1089 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1090 * @isp: OMAP3 ISP device
1091 *
1092 * Routine for saving the context of each module in the ISP.
1093 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1094 */
1095static void isp_save_ctx(struct isp_device *isp)
1096{
1097 isp_save_context(isp, isp_reg_list);
1098 if (isp->iommu)
1099 iommu_save_ctx(isp->iommu);
1100}
1101
1102/*
1103 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1104 * @isp: OMAP3 ISP device
1105 *
1106 * Routine for restoring the context of each module in the ISP.
1107 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1108 */
1109static void isp_restore_ctx(struct isp_device *isp)
1110{
1111 isp_restore_context(isp, isp_reg_list);
1112 if (isp->iommu)
1113 iommu_restore_ctx(isp->iommu);
1114 omap3isp_ccdc_restore_context(isp);
1115 omap3isp_preview_restore_context(isp);
1116}
1117
1118/* -----------------------------------------------------------------------------
1119 * SBL resources management
1120 */
1121#define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1122 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1123 OMAP3_ISP_SBL_PREVIEW_READ | \
1124 OMAP3_ISP_SBL_RESIZER_READ)
1125#define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1126 OMAP3_ISP_SBL_CSI2A_WRITE | \
1127 OMAP3_ISP_SBL_CSI2C_WRITE | \
1128 OMAP3_ISP_SBL_CCDC_WRITE | \
1129 OMAP3_ISP_SBL_PREVIEW_WRITE)
1130
1131void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1132{
1133 u32 sbl = 0;
1134
1135 isp->sbl_resources |= res;
1136
1137 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1138 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1139
1140 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1141 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1142
1143 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1144 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1145
1146 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1147 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1148
1149 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1150 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1151
1152 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1153 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1154
1155 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1156}
1157
1158void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1159{
1160 u32 sbl = 0;
1161
1162 isp->sbl_resources &= ~res;
1163
1164 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1165 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1166
1167 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1168 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1169
1170 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1171 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1172
1173 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1174 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1175
1176 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1177 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1178
1179 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1180 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1181
1182 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1183}
1184
1185/*
1186 * isp_module_sync_idle - Helper to sync module with its idle state
1187 * @me: ISP submodule's media entity
1188 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1189 * @stopping: flag which tells module wants to stop
1190 *
1191 * This function checks if ISP submodule needs to wait for next interrupt. If
1192 * yes, makes the caller to sleep while waiting for such event.
1193 */
1194int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1195 atomic_t *stopping)
1196{
1197 struct isp_pipeline *pipe = to_isp_pipeline(me);
1198
1199 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1200 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1201 !isp_pipeline_ready(pipe)))
1202 return 0;
1203
1204 /*
1205 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1206 * scenario. We'll call it here to avoid race conditions.
1207 */
1208 atomic_set(stopping, 1);
1209 smp_mb();
1210
1211 /*
1212 * If module is the last one, it's writing to memory. In this case,
1213 * it's necessary to check if the module is already paused due to
1214 * DMA queue underrun or if it has to wait for next interrupt to be
1215 * idle.
1216 * If it isn't the last one, the function won't sleep but *stopping
1217 * will still be set to warn next submodule caller's interrupt the
1218 * module wants to be idle.
1219 */
1220 if (isp_pipeline_is_last(me)) {
1221 struct isp_video *video = pipe->output;
1222 unsigned long flags;
1223 spin_lock_irqsave(&video->queue->irqlock, flags);
1224 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
1225 spin_unlock_irqrestore(&video->queue->irqlock, flags);
1226 atomic_set(stopping, 0);
1227 smp_mb();
1228 return 0;
1229 }
1230 spin_unlock_irqrestore(&video->queue->irqlock, flags);
1231 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1232 msecs_to_jiffies(1000))) {
1233 atomic_set(stopping, 0);
1234 smp_mb();
1235 return -ETIMEDOUT;
1236 }
1237 }
1238
1239 return 0;
1240}
1241
1242/*
1243 * omap3isp_module_sync_is_stopped - Helper to verify if module was stopping
1244 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1245 * @stopping: flag which tells module wants to stop
1246 *
1247 * This function checks if ISP submodule was stopping. In case of yes, it
1248 * notices the caller by setting stopping to 0 and waking up the wait queue.
1249 * Returns 1 if it was stopping or 0 otherwise.
1250 */
1251int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1252 atomic_t *stopping)
1253{
1254 if (atomic_cmpxchg(stopping, 1, 0)) {
1255 wake_up(wait);
1256 return 1;
1257 }
1258
1259 return 0;
1260}
1261
1262/* --------------------------------------------------------------------------
1263 * Clock management
1264 */
1265
1266#define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1267 ISPCTRL_HIST_CLK_EN | \
1268 ISPCTRL_RSZ_CLK_EN | \
1269 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1270 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1271
1272static void __isp_subclk_update(struct isp_device *isp)
1273{
1274 u32 clk = 0;
1275
1276 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_H3A)
1277 clk |= ISPCTRL_H3A_CLK_EN;
1278
1279 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1280 clk |= ISPCTRL_HIST_CLK_EN;
1281
1282 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1283 clk |= ISPCTRL_RSZ_CLK_EN;
1284
1285 /* NOTE: For CCDC & Preview submodules, we need to affect internal
1286 * RAM aswell.
1287 */
1288 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1289 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1290
1291 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1292 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1293
1294 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1295 ISPCTRL_CLKS_MASK, clk);
1296}
1297
1298void omap3isp_subclk_enable(struct isp_device *isp,
1299 enum isp_subclk_resource res)
1300{
1301 isp->subclk_resources |= res;
1302
1303 __isp_subclk_update(isp);
1304}
1305
1306void omap3isp_subclk_disable(struct isp_device *isp,
1307 enum isp_subclk_resource res)
1308{
1309 isp->subclk_resources &= ~res;
1310
1311 __isp_subclk_update(isp);
1312}
1313
1314/*
1315 * isp_enable_clocks - Enable ISP clocks
1316 * @isp: OMAP3 ISP device
1317 *
1318 * Return 0 if successful, or clk_enable return value if any of tthem fails.
1319 */
1320static int isp_enable_clocks(struct isp_device *isp)
1321{
1322 int r;
1323 unsigned long rate;
1324 int divisor;
1325
1326 /*
1327 * cam_mclk clock chain:
1328 * dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
1329 *
1330 * In OMAP3630 dpll4_m5x2 != 2 x dpll4_m5 but both are
1331 * set to the same value. Hence the rate set for dpll4_m5
1332 * has to be twice of what is set on OMAP3430 to get
1333 * the required value for cam_mclk
1334 */
1335 if (cpu_is_omap3630())
1336 divisor = 1;
1337 else
1338 divisor = 2;
1339
1340 r = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
1341 if (r) {
1342 dev_err(isp->dev, "clk_enable cam_ick failed\n");
1343 goto out_clk_enable_ick;
1344 }
1345 r = clk_set_rate(isp->clock[ISP_CLK_DPLL4_M5_CK],
1346 CM_CAM_MCLK_HZ/divisor);
1347 if (r) {
1348 dev_err(isp->dev, "clk_set_rate for dpll4_m5_ck failed\n");
1349 goto out_clk_enable_mclk;
1350 }
1351 r = clk_enable(isp->clock[ISP_CLK_CAM_MCLK]);
1352 if (r) {
1353 dev_err(isp->dev, "clk_enable cam_mclk failed\n");
1354 goto out_clk_enable_mclk;
1355 }
1356 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1357 if (rate != CM_CAM_MCLK_HZ)
1358 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1359 " expected : %d\n"
1360 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
1361 r = clk_enable(isp->clock[ISP_CLK_CSI2_FCK]);
1362 if (r) {
1363 dev_err(isp->dev, "clk_enable csi2_fck failed\n");
1364 goto out_clk_enable_csi2_fclk;
1365 }
1366 return 0;
1367
1368out_clk_enable_csi2_fclk:
1369 clk_disable(isp->clock[ISP_CLK_CAM_MCLK]);
1370out_clk_enable_mclk:
1371 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
1372out_clk_enable_ick:
1373 return r;
1374}
1375
1376/*
1377 * isp_disable_clocks - Disable ISP clocks
1378 * @isp: OMAP3 ISP device
1379 */
1380static void isp_disable_clocks(struct isp_device *isp)
1381{
1382 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
1383 clk_disable(isp->clock[ISP_CLK_CAM_MCLK]);
1384 clk_disable(isp->clock[ISP_CLK_CSI2_FCK]);
1385}
1386
1387static const char *isp_clocks[] = {
1388 "cam_ick",
1389 "cam_mclk",
1390 "dpll4_m5_ck",
1391 "csi2_96m_fck",
1392 "l3_ick",
1393};
1394
1395static void isp_put_clocks(struct isp_device *isp)
1396{
1397 unsigned int i;
1398
1399 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1400 if (isp->clock[i]) {
1401 clk_put(isp->clock[i]);
1402 isp->clock[i] = NULL;
1403 }
1404 }
1405}
1406
1407static int isp_get_clocks(struct isp_device *isp)
1408{
1409 struct clk *clk;
1410 unsigned int i;
1411
1412 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1413 clk = clk_get(isp->dev, isp_clocks[i]);
1414 if (IS_ERR(clk)) {
1415 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
1416 isp_put_clocks(isp);
1417 return PTR_ERR(clk);
1418 }
1419
1420 isp->clock[i] = clk;
1421 }
1422
1423 return 0;
1424}
1425
1426/*
1427 * omap3isp_get - Acquire the ISP resource.
1428 *
1429 * Initializes the clocks for the first acquire.
1430 *
1431 * Increment the reference count on the ISP. If the first reference is taken,
1432 * enable clocks and power-up all submodules.
1433 *
1434 * Return a pointer to the ISP device structure, or NULL if an error occured.
1435 */
1436struct isp_device *omap3isp_get(struct isp_device *isp)
1437{
1438 struct isp_device *__isp = isp;
1439
1440 if (isp == NULL)
1441 return NULL;
1442
1443 mutex_lock(&isp->isp_mutex);
1444 if (isp->ref_count > 0)
1445 goto out;
1446
1447 if (isp_enable_clocks(isp) < 0) {
1448 __isp = NULL;
1449 goto out;
1450 }
1451
1452 /* We don't want to restore context before saving it! */
1453 if (isp->has_context)
1454 isp_restore_ctx(isp);
1455 else
1456 isp->has_context = 1;
1457
1458 isp_enable_interrupts(isp);
1459
1460out:
1461 if (__isp != NULL)
1462 isp->ref_count++;
1463 mutex_unlock(&isp->isp_mutex);
1464
1465 return __isp;
1466}
1467
1468/*
1469 * omap3isp_put - Release the ISP
1470 *
1471 * Decrement the reference count on the ISP. If the last reference is released,
1472 * power-down all submodules, disable clocks and free temporary buffers.
1473 */
1474void omap3isp_put(struct isp_device *isp)
1475{
1476 if (isp == NULL)
1477 return;
1478
1479 mutex_lock(&isp->isp_mutex);
1480 BUG_ON(isp->ref_count == 0);
1481 if (--isp->ref_count == 0) {
1482 isp_disable_interrupts(isp);
1483 isp_save_ctx(isp);
1484 isp_disable_clocks(isp);
1485 }
1486 mutex_unlock(&isp->isp_mutex);
1487}
1488
1489/* --------------------------------------------------------------------------
1490 * Platform device driver
1491 */
1492
1493/*
1494 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1495 * @isp: OMAP3 ISP device
1496 */
1497#define ISP_PRINT_REGISTER(isp, name)\
1498 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1499 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1500#define SBL_PRINT_REGISTER(isp, name)\
1501 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1502 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1503
1504void omap3isp_print_status(struct isp_device *isp)
1505{
1506 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1507
1508 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1509 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1510 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1511 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1512 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1513 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1514 ISP_PRINT_REGISTER(isp, CTRL);
1515 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1516 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1517 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1518 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1519 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1520 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1521 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1522 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1523
1524 SBL_PRINT_REGISTER(isp, PCR);
1525 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1526
1527 dev_dbg(isp->dev, "--------------------------------------------\n");
1528}
1529
1530#ifdef CONFIG_PM
1531
1532/*
1533 * Power management support.
1534 *
1535 * As the ISP can't properly handle an input video stream interruption on a non
1536 * frame boundary, the ISP pipelines need to be stopped before sensors get
1537 * suspended. However, as suspending the sensors can require a running clock,
1538 * which can be provided by the ISP, the ISP can't be completely suspended
1539 * before the sensor.
1540 *
1541 * To solve this problem power management support is split into prepare/complete
1542 * and suspend/resume operations. The pipelines are stopped in prepare() and the
1543 * ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
1544 * resume(), and the the pipelines are restarted in complete().
1545 *
1546 * TODO: PM dependencies between the ISP and sensors are not modeled explicitly
1547 * yet.
1548 */
1549static int isp_pm_prepare(struct device *dev)
1550{
1551 struct isp_device *isp = dev_get_drvdata(dev);
1552 int reset;
1553
1554 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1555
1556 if (isp->ref_count == 0)
1557 return 0;
1558
1559 reset = isp_suspend_modules(isp);
1560 isp_disable_interrupts(isp);
1561 isp_save_ctx(isp);
1562 if (reset)
1563 isp_reset(isp);
1564
1565 return 0;
1566}
1567
1568static int isp_pm_suspend(struct device *dev)
1569{
1570 struct isp_device *isp = dev_get_drvdata(dev);
1571
1572 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1573
1574 if (isp->ref_count)
1575 isp_disable_clocks(isp);
1576
1577 return 0;
1578}
1579
1580static int isp_pm_resume(struct device *dev)
1581{
1582 struct isp_device *isp = dev_get_drvdata(dev);
1583
1584 if (isp->ref_count == 0)
1585 return 0;
1586
1587 return isp_enable_clocks(isp);
1588}
1589
1590static void isp_pm_complete(struct device *dev)
1591{
1592 struct isp_device *isp = dev_get_drvdata(dev);
1593
1594 if (isp->ref_count == 0)
1595 return;
1596
1597 isp_restore_ctx(isp);
1598 isp_enable_interrupts(isp);
1599 isp_resume_modules(isp);
1600}
1601
1602#else
1603
1604#define isp_pm_prepare NULL
1605#define isp_pm_suspend NULL
1606#define isp_pm_resume NULL
1607#define isp_pm_complete NULL
1608
1609#endif /* CONFIG_PM */
1610
1611static void isp_unregister_entities(struct isp_device *isp)
1612{
1613 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1614 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1615 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1616 omap3isp_preview_unregister_entities(&isp->isp_prev);
1617 omap3isp_resizer_unregister_entities(&isp->isp_res);
1618 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1619 omap3isp_stat_unregister_entities(&isp->isp_af);
1620 omap3isp_stat_unregister_entities(&isp->isp_hist);
1621
1622 v4l2_device_unregister(&isp->v4l2_dev);
1623 media_device_unregister(&isp->media_dev);
1624}
1625
1626/*
1627 * isp_register_subdev_group - Register a group of subdevices
1628 * @isp: OMAP3 ISP device
1629 * @board_info: I2C subdevs board information array
1630 *
1631 * Register all I2C subdevices in the board_info array. The array must be
1632 * terminated by a NULL entry, and the first entry must be the sensor.
1633 *
1634 * Return a pointer to the sensor media entity if it has been successfully
1635 * registered, or NULL otherwise.
1636 */
1637static struct v4l2_subdev *
1638isp_register_subdev_group(struct isp_device *isp,
1639 struct isp_subdev_i2c_board_info *board_info)
1640{
1641 struct v4l2_subdev *sensor = NULL;
1642 unsigned int first;
1643
1644 if (board_info->board_info == NULL)
1645 return NULL;
1646
1647 for (first = 1; board_info->board_info; ++board_info, first = 0) {
1648 struct v4l2_subdev *subdev;
1649 struct i2c_adapter *adapter;
1650
1651 adapter = i2c_get_adapter(board_info->i2c_adapter_id);
1652 if (adapter == NULL) {
1653 printk(KERN_ERR "%s: Unable to get I2C adapter %d for "
1654 "device %s\n", __func__,
1655 board_info->i2c_adapter_id,
1656 board_info->board_info->type);
1657 continue;
1658 }
1659
1660 subdev = v4l2_i2c_new_subdev_board(&isp->v4l2_dev, adapter,
1661 board_info->board_info, NULL);
1662 if (subdev == NULL) {
1663 printk(KERN_ERR "%s: Unable to register subdev %s\n",
1664 __func__, board_info->board_info->type);
1665 continue;
1666 }
1667
1668 if (first)
1669 sensor = subdev;
1670 }
1671
1672 return sensor;
1673}
1674
1675static int isp_register_entities(struct isp_device *isp)
1676{
1677 struct isp_platform_data *pdata = isp->pdata;
1678 struct isp_v4l2_subdevs_group *subdevs;
1679 int ret;
1680
1681 isp->media_dev.dev = isp->dev;
1682 strlcpy(isp->media_dev.model, "TI OMAP3 ISP",
1683 sizeof(isp->media_dev.model));
1684 isp->media_dev.link_notify = isp_pipeline_link_notify;
1685 ret = media_device_register(&isp->media_dev);
1686 if (ret < 0) {
1687 printk(KERN_ERR "%s: Media device registration failed (%d)\n",
1688 __func__, ret);
1689 return ret;
1690 }
1691
1692 isp->v4l2_dev.mdev = &isp->media_dev;
1693 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1694 if (ret < 0) {
1695 printk(KERN_ERR "%s: V4L2 device registration failed (%d)\n",
1696 __func__, ret);
1697 goto done;
1698 }
1699
1700 /* Register internal entities */
1701 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1702 if (ret < 0)
1703 goto done;
1704
1705 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1706 if (ret < 0)
1707 goto done;
1708
1709 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1710 if (ret < 0)
1711 goto done;
1712
1713 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1714 &isp->v4l2_dev);
1715 if (ret < 0)
1716 goto done;
1717
1718 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1719 if (ret < 0)
1720 goto done;
1721
1722 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1723 if (ret < 0)
1724 goto done;
1725
1726 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1727 if (ret < 0)
1728 goto done;
1729
1730 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1731 if (ret < 0)
1732 goto done;
1733
1734 /* Register external entities */
1735 for (subdevs = pdata->subdevs; subdevs->subdevs; ++subdevs) {
1736 struct v4l2_subdev *sensor;
1737 struct media_entity *input;
1738 unsigned int flags;
1739 unsigned int pad;
1740
1741 sensor = isp_register_subdev_group(isp, subdevs->subdevs);
1742 if (sensor == NULL)
1743 continue;
1744
1745 sensor->host_priv = subdevs;
1746
1747 /* Connect the sensor to the correct interface module. Parallel
1748 * sensors are connected directly to the CCDC, while serial
1749 * sensors are connected to the CSI2a, CCP2b or CSI2c receiver
1750 * through CSIPHY1 or CSIPHY2.
1751 */
1752 switch (subdevs->interface) {
1753 case ISP_INTERFACE_PARALLEL:
1754 input = &isp->isp_ccdc.subdev.entity;
1755 pad = CCDC_PAD_SINK;
1756 flags = 0;
1757 break;
1758
1759 case ISP_INTERFACE_CSI2A_PHY2:
1760 input = &isp->isp_csi2a.subdev.entity;
1761 pad = CSI2_PAD_SINK;
1762 flags = MEDIA_LNK_FL_IMMUTABLE
1763 | MEDIA_LNK_FL_ENABLED;
1764 break;
1765
1766 case ISP_INTERFACE_CCP2B_PHY1:
1767 case ISP_INTERFACE_CCP2B_PHY2:
1768 input = &isp->isp_ccp2.subdev.entity;
1769 pad = CCP2_PAD_SINK;
1770 flags = 0;
1771 break;
1772
1773 case ISP_INTERFACE_CSI2C_PHY1:
1774 input = &isp->isp_csi2c.subdev.entity;
1775 pad = CSI2_PAD_SINK;
1776 flags = MEDIA_LNK_FL_IMMUTABLE
1777 | MEDIA_LNK_FL_ENABLED;
1778 break;
1779
1780 default:
1781 printk(KERN_ERR "%s: invalid interface type %u\n",
1782 __func__, subdevs->interface);
1783 ret = -EINVAL;
1784 goto done;
1785 }
1786
1787 ret = media_entity_create_link(&sensor->entity, 0, input, pad,
1788 flags);
1789 if (ret < 0)
1790 goto done;
1791 }
1792
1793 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1794
1795done:
1796 if (ret < 0)
1797 isp_unregister_entities(isp);
1798
1799 return ret;
1800}
1801
1802static void isp_cleanup_modules(struct isp_device *isp)
1803{
1804 omap3isp_h3a_aewb_cleanup(isp);
1805 omap3isp_h3a_af_cleanup(isp);
1806 omap3isp_hist_cleanup(isp);
1807 omap3isp_resizer_cleanup(isp);
1808 omap3isp_preview_cleanup(isp);
1809 omap3isp_ccdc_cleanup(isp);
1810 omap3isp_ccp2_cleanup(isp);
1811 omap3isp_csi2_cleanup(isp);
1812}
1813
1814static int isp_initialize_modules(struct isp_device *isp)
1815{
1816 int ret;
1817
1818 ret = omap3isp_csiphy_init(isp);
1819 if (ret < 0) {
1820 dev_err(isp->dev, "CSI PHY initialization failed\n");
1821 goto error_csiphy;
1822 }
1823
1824 ret = omap3isp_csi2_init(isp);
1825 if (ret < 0) {
1826 dev_err(isp->dev, "CSI2 initialization failed\n");
1827 goto error_csi2;
1828 }
1829
1830 ret = omap3isp_ccp2_init(isp);
1831 if (ret < 0) {
1832 dev_err(isp->dev, "CCP2 initialization failed\n");
1833 goto error_ccp2;
1834 }
1835
1836 ret = omap3isp_ccdc_init(isp);
1837 if (ret < 0) {
1838 dev_err(isp->dev, "CCDC initialization failed\n");
1839 goto error_ccdc;
1840 }
1841
1842 ret = omap3isp_preview_init(isp);
1843 if (ret < 0) {
1844 dev_err(isp->dev, "Preview initialization failed\n");
1845 goto error_preview;
1846 }
1847
1848 ret = omap3isp_resizer_init(isp);
1849 if (ret < 0) {
1850 dev_err(isp->dev, "Resizer initialization failed\n");
1851 goto error_resizer;
1852 }
1853
1854 ret = omap3isp_hist_init(isp);
1855 if (ret < 0) {
1856 dev_err(isp->dev, "Histogram initialization failed\n");
1857 goto error_hist;
1858 }
1859
1860 ret = omap3isp_h3a_aewb_init(isp);
1861 if (ret < 0) {
1862 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1863 goto error_h3a_aewb;
1864 }
1865
1866 ret = omap3isp_h3a_af_init(isp);
1867 if (ret < 0) {
1868 dev_err(isp->dev, "H3A AF initialization failed\n");
1869 goto error_h3a_af;
1870 }
1871
1872 /* Connect the submodules. */
1873 ret = media_entity_create_link(
1874 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1875 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1876 if (ret < 0)
1877 goto error_link;
1878
1879 ret = media_entity_create_link(
1880 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1881 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1882 if (ret < 0)
1883 goto error_link;
1884
1885 ret = media_entity_create_link(
1886 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1887 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1888 if (ret < 0)
1889 goto error_link;
1890
1891 ret = media_entity_create_link(
1892 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1893 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1894 if (ret < 0)
1895 goto error_link;
1896
1897 ret = media_entity_create_link(
1898 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1899 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1900 if (ret < 0)
1901 goto error_link;
1902
1903 ret = media_entity_create_link(
1904 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1905 &isp->isp_aewb.subdev.entity, 0,
1906 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1907 if (ret < 0)
1908 goto error_link;
1909
1910 ret = media_entity_create_link(
1911 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1912 &isp->isp_af.subdev.entity, 0,
1913 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1914 if (ret < 0)
1915 goto error_link;
1916
1917 ret = media_entity_create_link(
1918 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1919 &isp->isp_hist.subdev.entity, 0,
1920 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1921 if (ret < 0)
1922 goto error_link;
1923
1924 return 0;
1925
1926error_link:
1927 omap3isp_h3a_af_cleanup(isp);
1928error_h3a_af:
1929 omap3isp_h3a_aewb_cleanup(isp);
1930error_h3a_aewb:
1931 omap3isp_hist_cleanup(isp);
1932error_hist:
1933 omap3isp_resizer_cleanup(isp);
1934error_resizer:
1935 omap3isp_preview_cleanup(isp);
1936error_preview:
1937 omap3isp_ccdc_cleanup(isp);
1938error_ccdc:
1939 omap3isp_ccp2_cleanup(isp);
1940error_ccp2:
1941 omap3isp_csi2_cleanup(isp);
1942error_csi2:
1943error_csiphy:
1944 return ret;
1945}
1946
1947/*
1948 * isp_remove - Remove ISP platform device
1949 * @pdev: Pointer to ISP platform device
1950 *
1951 * Always returns 0.
1952 */
1953static int isp_remove(struct platform_device *pdev)
1954{
1955 struct isp_device *isp = platform_get_drvdata(pdev);
1956 int i;
1957
1958 isp_unregister_entities(isp);
1959 isp_cleanup_modules(isp);
1960
1961 omap3isp_get(isp);
1962 iommu_put(isp->iommu);
1963 omap3isp_put(isp);
1964
1965 free_irq(isp->irq_num, isp);
1966 isp_put_clocks(isp);
1967
1968 for (i = 0; i < OMAP3_ISP_IOMEM_LAST; i++) {
1969 if (isp->mmio_base[i]) {
1970 iounmap(isp->mmio_base[i]);
1971 isp->mmio_base[i] = NULL;
1972 }
1973
1974 if (isp->mmio_base_phys[i]) {
1975 release_mem_region(isp->mmio_base_phys[i],
1976 isp->mmio_size[i]);
1977 isp->mmio_base_phys[i] = 0;
1978 }
1979 }
1980
1981 regulator_put(isp->isp_csiphy1.vdd);
1982 regulator_put(isp->isp_csiphy2.vdd);
1983 kfree(isp);
1984
1985 return 0;
1986}
1987
1988static int isp_map_mem_resource(struct platform_device *pdev,
1989 struct isp_device *isp,
1990 enum isp_mem_resources res)
1991{
1992 struct resource *mem;
1993
1994 /* request the mem region for the camera registers */
1995
1996 mem = platform_get_resource(pdev, IORESOURCE_MEM, res);
1997 if (!mem) {
1998 dev_err(isp->dev, "no mem resource?\n");
1999 return -ENODEV;
2000 }
2001
2002 if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
2003 dev_err(isp->dev,
2004 "cannot reserve camera register I/O region\n");
2005 return -ENODEV;
2006 }
2007 isp->mmio_base_phys[res] = mem->start;
2008 isp->mmio_size[res] = resource_size(mem);
2009
2010 /* map the region */
2011 isp->mmio_base[res] = ioremap_nocache(isp->mmio_base_phys[res],
2012 isp->mmio_size[res]);
2013 if (!isp->mmio_base[res]) {
2014 dev_err(isp->dev, "cannot map camera register I/O region\n");
2015 return -ENODEV;
2016 }
2017
2018 return 0;
2019}
2020
2021/*
2022 * isp_probe - Probe ISP platform device
2023 * @pdev: Pointer to ISP platform device
2024 *
2025 * Returns 0 if successful,
2026 * -ENOMEM if no memory available,
2027 * -ENODEV if no platform device resources found
2028 * or no space for remapping registers,
2029 * -EINVAL if couldn't install ISR,
2030 * or clk_get return error value.
2031 */
2032static int isp_probe(struct platform_device *pdev)
2033{
2034 struct isp_platform_data *pdata = pdev->dev.platform_data;
2035 struct isp_device *isp;
2036 int ret;
2037 int i, m;
2038
2039 if (pdata == NULL)
2040 return -EINVAL;
2041
2042 isp = kzalloc(sizeof(*isp), GFP_KERNEL);
2043 if (!isp) {
2044 dev_err(&pdev->dev, "could not allocate memory\n");
2045 return -ENOMEM;
2046 }
2047
2048 isp->autoidle = autoidle;
2049 isp->platform_cb.set_xclk = isp_set_xclk;
2050 isp->platform_cb.set_pixel_clock = isp_set_pixel_clock;
2051
2052 mutex_init(&isp->isp_mutex);
2053 spin_lock_init(&isp->stat_lock);
2054
2055 isp->dev = &pdev->dev;
2056 isp->pdata = pdata;
2057 isp->ref_count = 0;
2058
2059 isp->raw_dmamask = DMA_BIT_MASK(32);
2060 isp->dev->dma_mask = &isp->raw_dmamask;
2061 isp->dev->coherent_dma_mask = DMA_BIT_MASK(32);
2062
2063 platform_set_drvdata(pdev, isp);
2064
2065 /* Regulators */
2066 isp->isp_csiphy1.vdd = regulator_get(&pdev->dev, "VDD_CSIPHY1");
2067 isp->isp_csiphy2.vdd = regulator_get(&pdev->dev, "VDD_CSIPHY2");
2068
2069 /* Clocks */
2070 ret = isp_map_mem_resource(pdev, isp, OMAP3_ISP_IOMEM_MAIN);
2071 if (ret < 0)
2072 goto error;
2073
2074 ret = isp_get_clocks(isp);
2075 if (ret < 0)
2076 goto error;
2077
2078 if (omap3isp_get(isp) == NULL)
2079 goto error;
2080
2081 ret = isp_reset(isp);
2082 if (ret < 0)
2083 goto error_isp;
2084
2085 /* Memory resources */
2086 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2087 dev_info(isp->dev, "Revision %d.%d found\n",
2088 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2089
2090 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2091 if (isp->revision == isp_res_maps[m].isp_rev)
2092 break;
2093
2094 if (m == ARRAY_SIZE(isp_res_maps)) {
2095 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2096 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2097 ret = -ENODEV;
2098 goto error_isp;
2099 }
2100
2101 for (i = 1; i < OMAP3_ISP_IOMEM_LAST; i++) {
2102 if (isp_res_maps[m].map & 1 << i) {
2103 ret = isp_map_mem_resource(pdev, isp, i);
2104 if (ret)
2105 goto error_isp;
2106 }
2107 }
2108
2109 /* IOMMU */
2110 isp->iommu = iommu_get("isp");
2111 if (IS_ERR_OR_NULL(isp->iommu)) {
2112 isp->iommu = NULL;
2113 ret = -ENODEV;
2114 goto error_isp;
2115 }
2116
2117 /* Interrupt */
2118 isp->irq_num = platform_get_irq(pdev, 0);
2119 if (isp->irq_num <= 0) {
2120 dev_err(isp->dev, "No IRQ resource\n");
2121 ret = -ENODEV;
2122 goto error_isp;
2123 }
2124
2125 if (request_irq(isp->irq_num, isp_isr, IRQF_SHARED, "OMAP3 ISP", isp)) {
2126 dev_err(isp->dev, "Unable to request IRQ\n");
2127 ret = -EINVAL;
2128 goto error_isp;
2129 }
2130
2131 /* Entities */
2132 ret = isp_initialize_modules(isp);
2133 if (ret < 0)
2134 goto error_irq;
2135
2136 ret = isp_register_entities(isp);
2137 if (ret < 0)
2138 goto error_modules;
2139
2140 isp_power_settings(isp, 1);
2141 omap3isp_put(isp);
2142
2143 return 0;
2144
2145error_modules:
2146 isp_cleanup_modules(isp);
2147error_irq:
2148 free_irq(isp->irq_num, isp);
2149error_isp:
2150 iommu_put(isp->iommu);
2151 omap3isp_put(isp);
2152error:
2153 isp_put_clocks(isp);
2154
2155 for (i = 0; i < OMAP3_ISP_IOMEM_LAST; i++) {
2156 if (isp->mmio_base[i]) {
2157 iounmap(isp->mmio_base[i]);
2158 isp->mmio_base[i] = NULL;
2159 }
2160
2161 if (isp->mmio_base_phys[i]) {
2162 release_mem_region(isp->mmio_base_phys[i],
2163 isp->mmio_size[i]);
2164 isp->mmio_base_phys[i] = 0;
2165 }
2166 }
2167 regulator_put(isp->isp_csiphy2.vdd);
2168 regulator_put(isp->isp_csiphy1.vdd);
2169 platform_set_drvdata(pdev, NULL);
2170 kfree(isp);
2171
2172 return ret;
2173}
2174
2175static const struct dev_pm_ops omap3isp_pm_ops = {
2176 .prepare = isp_pm_prepare,
2177 .suspend = isp_pm_suspend,
2178 .resume = isp_pm_resume,
2179 .complete = isp_pm_complete,
2180};
2181
2182static struct platform_device_id omap3isp_id_table[] = {
2183 { "omap3isp", 0 },
2184 { },
2185};
2186MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2187
2188static struct platform_driver omap3isp_driver = {
2189 .probe = isp_probe,
2190 .remove = isp_remove,
2191 .id_table = omap3isp_id_table,
2192 .driver = {
2193 .owner = THIS_MODULE,
2194 .name = "omap3isp",
2195 .pm = &omap3isp_pm_ops,
2196 },
2197};
2198
2199/*
2200 * isp_init - ISP module initialization.
2201 */
2202static int __init isp_init(void)
2203{
2204 return platform_driver_register(&omap3isp_driver);
2205}
2206
2207/*
2208 * isp_cleanup - ISP module cleanup.
2209 */
2210static void __exit isp_cleanup(void)
2211{
2212 platform_driver_unregister(&omap3isp_driver);
2213}
2214
2215module_init(isp_init);
2216module_exit(isp_cleanup);
2217
2218MODULE_AUTHOR("Nokia Corporation");
2219MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2220MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/omap3isp/isp.h b/drivers/media/video/omap3isp/isp.h
new file mode 100644
index 000000000000..a8dfea413d34
--- /dev/null
+++ b/drivers/media/video/omap3isp/isp.h
@@ -0,0 +1,430 @@
1/*
2 * isp.h
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27#ifndef OMAP3_ISP_CORE_H
28#define OMAP3_ISP_CORE_H
29
30#include <media/v4l2-device.h>
31#include <linux/device.h>
32#include <linux/io.h>
33#include <linux/platform_device.h>
34#include <linux/wait.h>
35#include <plat/iommu.h>
36#include <plat/iovmm.h>
37
38#include "ispstat.h"
39#include "ispccdc.h"
40#include "ispreg.h"
41#include "ispresizer.h"
42#include "isppreview.h"
43#include "ispcsiphy.h"
44#include "ispcsi2.h"
45#include "ispccp2.h"
46
47#define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
48
49#define ISP_TOK_TERM 0xFFFFFFFF /*
50 * terminating token for ISP
51 * modules reg list
52 */
53#define to_isp_device(ptr_module) \
54 container_of(ptr_module, struct isp_device, isp_##ptr_module)
55#define to_device(ptr_module) \
56 (to_isp_device(ptr_module)->dev)
57
58enum isp_mem_resources {
59 OMAP3_ISP_IOMEM_MAIN,
60 OMAP3_ISP_IOMEM_CCP2,
61 OMAP3_ISP_IOMEM_CCDC,
62 OMAP3_ISP_IOMEM_HIST,
63 OMAP3_ISP_IOMEM_H3A,
64 OMAP3_ISP_IOMEM_PREV,
65 OMAP3_ISP_IOMEM_RESZ,
66 OMAP3_ISP_IOMEM_SBL,
67 OMAP3_ISP_IOMEM_CSI2A_REGS1,
68 OMAP3_ISP_IOMEM_CSIPHY2,
69 OMAP3_ISP_IOMEM_CSI2A_REGS2,
70 OMAP3_ISP_IOMEM_CSI2C_REGS1,
71 OMAP3_ISP_IOMEM_CSIPHY1,
72 OMAP3_ISP_IOMEM_CSI2C_REGS2,
73 OMAP3_ISP_IOMEM_LAST
74};
75
76enum isp_sbl_resource {
77 OMAP3_ISP_SBL_CSI1_READ = 0x1,
78 OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
79 OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
80 OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
81 OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
82 OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
83 OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
84 OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
85 OMAP3_ISP_SBL_RESIZER_READ = 0x100,
86 OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
87};
88
89enum isp_subclk_resource {
90 OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
91 OMAP3_ISP_SUBCLK_H3A = (1 << 1),
92 OMAP3_ISP_SUBCLK_HIST = (1 << 2),
93 OMAP3_ISP_SUBCLK_PREVIEW = (1 << 3),
94 OMAP3_ISP_SUBCLK_RESIZER = (1 << 4),
95};
96
97enum isp_interface_type {
98 ISP_INTERFACE_PARALLEL,
99 ISP_INTERFACE_CSI2A_PHY2,
100 ISP_INTERFACE_CCP2B_PHY1,
101 ISP_INTERFACE_CCP2B_PHY2,
102 ISP_INTERFACE_CSI2C_PHY1,
103};
104
105/* ISP: OMAP 34xx ES 1.0 */
106#define ISP_REVISION_1_0 0x10
107/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
108#define ISP_REVISION_2_0 0x20
109/* ISP2P: OMAP 36xx */
110#define ISP_REVISION_15_0 0xF0
111
112/*
113 * struct isp_res_mapping - Map ISP io resources to ISP revision.
114 * @isp_rev: ISP_REVISION_x_x
115 * @map: bitmap for enum isp_mem_resources
116 */
117struct isp_res_mapping {
118 u32 isp_rev;
119 u32 map;
120};
121
122/*
123 * struct isp_reg - Structure for ISP register values.
124 * @reg: 32-bit Register address.
125 * @val: 32-bit Register value.
126 */
127struct isp_reg {
128 enum isp_mem_resources mmio_range;
129 u32 reg;
130 u32 val;
131};
132
133/**
134 * struct isp_parallel_platform_data - Parallel interface platform data
135 * @width: Parallel bus width in bits (8, 10, 11 or 12)
136 * @data_lane_shift: Data lane shifter
137 * 0 - CAMEXT[13:0] -> CAM[13:0]
138 * 1 - CAMEXT[13:2] -> CAM[11:0]
139 * 2 - CAMEXT[13:4] -> CAM[9:0]
140 * 3 - CAMEXT[13:6] -> CAM[7:0]
141 * @clk_pol: Pixel clock polarity
142 * 0 - Non Inverted, 1 - Inverted
143 * @bridge: CCDC Bridge input control
144 * ISPCTRL_PAR_BRIDGE_DISABLE - Disable
145 * ISPCTRL_PAR_BRIDGE_LENDIAN - Little endian
146 * ISPCTRL_PAR_BRIDGE_BENDIAN - Big endian
147 */
148struct isp_parallel_platform_data {
149 unsigned int width;
150 unsigned int data_lane_shift:2;
151 unsigned int clk_pol:1;
152 unsigned int bridge:4;
153};
154
155/**
156 * struct isp_ccp2_platform_data - CCP2 interface platform data
157 * @strobe_clk_pol: Strobe/clock polarity
158 * 0 - Non Inverted, 1 - Inverted
159 * @crc: Enable the cyclic redundancy check
160 * @ccp2_mode: Enable CCP2 compatibility mode
161 * 0 - MIPI-CSI1 mode, 1 - CCP2 mode
162 * @phy_layer: Physical layer selection
163 * ISPCCP2_CTRL_PHY_SEL_CLOCK - Data/clock physical layer
164 * ISPCCP2_CTRL_PHY_SEL_STROBE - Data/strobe physical layer
165 * @vpclk_div: Video port output clock control
166 */
167struct isp_ccp2_platform_data {
168 unsigned int strobe_clk_pol:1;
169 unsigned int crc:1;
170 unsigned int ccp2_mode:1;
171 unsigned int phy_layer:1;
172 unsigned int vpclk_div:2;
173};
174
175/**
176 * struct isp_csi2_platform_data - CSI2 interface platform data
177 * @crc: Enable the cyclic redundancy check
178 * @vpclk_div: Video port output clock control
179 */
180struct isp_csi2_platform_data {
181 unsigned crc:1;
182 unsigned vpclk_div:2;
183};
184
185struct isp_subdev_i2c_board_info {
186 struct i2c_board_info *board_info;
187 int i2c_adapter_id;
188};
189
190struct isp_v4l2_subdevs_group {
191 struct isp_subdev_i2c_board_info *subdevs;
192 enum isp_interface_type interface;
193 union {
194 struct isp_parallel_platform_data parallel;
195 struct isp_ccp2_platform_data ccp2;
196 struct isp_csi2_platform_data csi2;
197 } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
198};
199
200struct isp_platform_data {
201 struct isp_v4l2_subdevs_group *subdevs;
202};
203
204struct isp_platform_callback {
205 u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
206 int (*csiphy_config)(struct isp_csiphy *phy,
207 struct isp_csiphy_dphy_cfg *dphy,
208 struct isp_csiphy_lanes_cfg *lanes);
209 void (*set_pixel_clock)(struct isp_device *isp, unsigned int pixelclk);
210};
211
212/*
213 * struct isp_device - ISP device structure.
214 * @dev: Device pointer specific to the OMAP3 ISP.
215 * @revision: Stores current ISP module revision.
216 * @irq_num: Currently used IRQ number.
217 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
218 * regions.
219 * @mmio_base_phys: Array with physical L4 bus addresses for ISP register
220 * regions.
221 * @mmio_size: Array with ISP register regions size in bytes.
222 * @raw_dmamask: Raw DMA mask
223 * @stat_lock: Spinlock for handling statistics
224 * @isp_mutex: Mutex for serializing requests to ISP.
225 * @has_context: Context has been saved at least once and can be restored.
226 * @ref_count: Reference count for handling multiple ISP requests.
227 * @cam_ick: Pointer to camera interface clock structure.
228 * @cam_mclk: Pointer to camera functional clock structure.
229 * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
230 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
231 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
232 * @irq: Currently attached ISP ISR callbacks information structure.
233 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
234 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
235 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
236 * White Balance SCM.
237 * @isp_res: Pointer to current settings for ISP Resizer.
238 * @isp_prev: Pointer to current settings for ISP Preview.
239 * @isp_ccdc: Pointer to current settings for ISP CCDC.
240 * @iommu: Pointer to requested IOMMU instance for ISP.
241 * @platform_cb: ISP driver callback function pointers for platform code
242 *
243 * This structure is used to store the OMAP ISP Information.
244 */
245struct isp_device {
246 struct v4l2_device v4l2_dev;
247 struct media_device media_dev;
248 struct device *dev;
249 u32 revision;
250
251 /* platform HW resources */
252 struct isp_platform_data *pdata;
253 unsigned int irq_num;
254
255 void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
256 unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
257 resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
258
259 u64 raw_dmamask;
260
261 /* ISP Obj */
262 spinlock_t stat_lock; /* common lock for statistic drivers */
263 struct mutex isp_mutex; /* For handling ref_count field */
264 int has_context;
265 int ref_count;
266 unsigned int autoidle;
267 u32 xclk_divisor[2]; /* Two clocks, a and b. */
268#define ISP_CLK_CAM_ICK 0
269#define ISP_CLK_CAM_MCLK 1
270#define ISP_CLK_DPLL4_M5_CK 2
271#define ISP_CLK_CSI2_FCK 3
272#define ISP_CLK_L3_ICK 4
273 struct clk *clock[5];
274
275 /* ISP modules */
276 struct ispstat isp_af;
277 struct ispstat isp_aewb;
278 struct ispstat isp_hist;
279 struct isp_res_device isp_res;
280 struct isp_prev_device isp_prev;
281 struct isp_ccdc_device isp_ccdc;
282 struct isp_csi2_device isp_csi2a;
283 struct isp_csi2_device isp_csi2c;
284 struct isp_ccp2_device isp_ccp2;
285 struct isp_csiphy isp_csiphy1;
286 struct isp_csiphy isp_csiphy2;
287
288 unsigned int sbl_resources;
289 unsigned int subclk_resources;
290
291 struct iommu *iommu;
292
293 struct isp_platform_callback platform_cb;
294};
295
296#define v4l2_dev_to_isp_device(dev) \
297 container_of(dev, struct isp_device, v4l2_dev)
298
299void omap3isp_hist_dma_done(struct isp_device *isp);
300
301void omap3isp_flush(struct isp_device *isp);
302
303int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
304 atomic_t *stopping);
305
306int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
307 atomic_t *stopping);
308
309int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
310 enum isp_pipeline_stream_state state);
311void omap3isp_configure_bridge(struct isp_device *isp,
312 enum ccdc_input_entity input,
313 const struct isp_parallel_platform_data *pdata);
314
315#define ISP_XCLK_NONE -1
316#define ISP_XCLK_A 0
317#define ISP_XCLK_B 1
318
319struct isp_device *omap3isp_get(struct isp_device *isp);
320void omap3isp_put(struct isp_device *isp);
321
322void omap3isp_print_status(struct isp_device *isp);
323
324void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
325void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
326
327void omap3isp_subclk_enable(struct isp_device *isp,
328 enum isp_subclk_resource res);
329void omap3isp_subclk_disable(struct isp_device *isp,
330 enum isp_subclk_resource res);
331
332int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
333
334int omap3isp_register_entities(struct platform_device *pdev,
335 struct v4l2_device *v4l2_dev);
336void omap3isp_unregister_entities(struct platform_device *pdev);
337
338/*
339 * isp_reg_readl - Read value of an OMAP3 ISP register
340 * @dev: Device pointer specific to the OMAP3 ISP.
341 * @isp_mmio_range: Range to which the register offset refers to.
342 * @reg_offset: Register offset to read from.
343 *
344 * Returns an unsigned 32 bit value with the required register contents.
345 */
346static inline
347u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
348 u32 reg_offset)
349{
350 return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
351}
352
353/*
354 * isp_reg_writel - Write value to an OMAP3 ISP register
355 * @dev: Device pointer specific to the OMAP3 ISP.
356 * @reg_value: 32 bit value to write to the register.
357 * @isp_mmio_range: Range to which the register offset refers to.
358 * @reg_offset: Register offset to write into.
359 */
360static inline
361void isp_reg_writel(struct isp_device *isp, u32 reg_value,
362 enum isp_mem_resources isp_mmio_range, u32 reg_offset)
363{
364 __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
365}
366
367/*
368 * isp_reg_and - Clear individual bits in an OMAP3 ISP register
369 * @dev: Device pointer specific to the OMAP3 ISP.
370 * @mmio_range: Range to which the register offset refers to.
371 * @reg: Register offset to work on.
372 * @clr_bits: 32 bit value which would be cleared in the register.
373 */
374static inline
375void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
376 u32 reg, u32 clr_bits)
377{
378 u32 v = isp_reg_readl(isp, mmio_range, reg);
379
380 isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
381}
382
383/*
384 * isp_reg_set - Set individual bits in an OMAP3 ISP register
385 * @dev: Device pointer specific to the OMAP3 ISP.
386 * @mmio_range: Range to which the register offset refers to.
387 * @reg: Register offset to work on.
388 * @set_bits: 32 bit value which would be set in the register.
389 */
390static inline
391void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
392 u32 reg, u32 set_bits)
393{
394 u32 v = isp_reg_readl(isp, mmio_range, reg);
395
396 isp_reg_writel(isp, v | set_bits, mmio_range, reg);
397}
398
399/*
400 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
401 * @dev: Device pointer specific to the OMAP3 ISP.
402 * @mmio_range: Range to which the register offset refers to.
403 * @reg: Register offset to work on.
404 * @clr_bits: 32 bit value which would be cleared in the register.
405 * @set_bits: 32 bit value which would be set in the register.
406 *
407 * The clear operation is done first, and then the set operation.
408 */
409static inline
410void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
411 u32 reg, u32 clr_bits, u32 set_bits)
412{
413 u32 v = isp_reg_readl(isp, mmio_range, reg);
414
415 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
416}
417
418static inline enum v4l2_buf_type
419isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
420{
421 if (pad >= subdev->entity.num_pads)
422 return 0;
423
424 if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
425 return V4L2_BUF_TYPE_VIDEO_OUTPUT;
426 else
427 return V4L2_BUF_TYPE_VIDEO_CAPTURE;
428}
429
430#endif /* OMAP3_ISP_CORE_H */
diff --git a/drivers/media/video/omap3isp/ispreg.h b/drivers/media/video/omap3isp/ispreg.h
new file mode 100644
index 000000000000..69f6af6f6b9c
--- /dev/null
+++ b/drivers/media/video/omap3isp/ispreg.h
@@ -0,0 +1,1589 @@
1/*
2 * ispreg.h
3 *
4 * TI OMAP3 ISP - Registers definitions
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27#ifndef OMAP3_ISP_REG_H
28#define OMAP3_ISP_REG_H
29
30#include <plat/omap34xx.h>
31
32
33#define CM_CAM_MCLK_HZ 172800000 /* Hz */
34
35/* ISP Submodules offset */
36
37#define OMAP3ISP_REG_BASE OMAP3430_ISP_BASE
38#define OMAP3ISP_REG(offset) (OMAP3ISP_REG_BASE + (offset))
39
40#define OMAP3ISP_CCP2_REG_OFFSET 0x0400
41#define OMAP3ISP_CCP2_REG_BASE (OMAP3ISP_REG_BASE + \
42 OMAP3ISP_CCP2_REG_OFFSET)
43#define OMAP3ISP_CCP2_REG(offset) (OMAP3ISP_CCP2_REG_BASE + (offset))
44
45#define OMAP3ISP_CCDC_REG_OFFSET 0x0600
46#define OMAP3ISP_CCDC_REG_BASE (OMAP3ISP_REG_BASE + \
47 OMAP3ISP_CCDC_REG_OFFSET)
48#define OMAP3ISP_CCDC_REG(offset) (OMAP3ISP_CCDC_REG_BASE + (offset))
49
50#define OMAP3ISP_HIST_REG_OFFSET 0x0A00
51#define OMAP3ISP_HIST_REG_BASE (OMAP3ISP_REG_BASE + \
52 OMAP3ISP_HIST_REG_OFFSET)
53#define OMAP3ISP_HIST_REG(offset) (OMAP3ISP_HIST_REG_BASE + (offset))
54
55#define OMAP3ISP_H3A_REG_OFFSET 0x0C00
56#define OMAP3ISP_H3A_REG_BASE (OMAP3ISP_REG_BASE + \
57 OMAP3ISP_H3A_REG_OFFSET)
58#define OMAP3ISP_H3A_REG(offset) (OMAP3ISP_H3A_REG_BASE + (offset))
59
60#define OMAP3ISP_PREV_REG_OFFSET 0x0E00
61#define OMAP3ISP_PREV_REG_BASE (OMAP3ISP_REG_BASE + \
62 OMAP3ISP_PREV_REG_OFFSET)
63#define OMAP3ISP_PREV_REG(offset) (OMAP3ISP_PREV_REG_BASE + (offset))
64
65#define OMAP3ISP_RESZ_REG_OFFSET 0x1000
66#define OMAP3ISP_RESZ_REG_BASE (OMAP3ISP_REG_BASE + \
67 OMAP3ISP_RESZ_REG_OFFSET)
68#define OMAP3ISP_RESZ_REG(offset) (OMAP3ISP_RESZ_REG_BASE + (offset))
69
70#define OMAP3ISP_SBL_REG_OFFSET 0x1200
71#define OMAP3ISP_SBL_REG_BASE (OMAP3ISP_REG_BASE + \
72 OMAP3ISP_SBL_REG_OFFSET)
73#define OMAP3ISP_SBL_REG(offset) (OMAP3ISP_SBL_REG_BASE + (offset))
74
75#define OMAP3ISP_CSI2A_REGS1_REG_OFFSET 0x1800
76#define OMAP3ISP_CSI2A_REGS1_REG_BASE (OMAP3ISP_REG_BASE + \
77 OMAP3ISP_CSI2A_REGS1_REG_OFFSET)
78#define OMAP3ISP_CSI2A_REGS1_REG(offset) \
79 (OMAP3ISP_CSI2A_REGS1_REG_BASE + (offset))
80
81#define OMAP3ISP_CSIPHY2_REG_OFFSET 0x1970
82#define OMAP3ISP_CSIPHY2_REG_BASE (OMAP3ISP_REG_BASE + \
83 OMAP3ISP_CSIPHY2_REG_OFFSET)
84#define OMAP3ISP_CSIPHY2_REG(offset) (OMAP3ISP_CSIPHY2_REG_BASE + (offset))
85
86#define OMAP3ISP_CSI2A_REGS2_REG_OFFSET 0x19C0
87#define OMAP3ISP_CSI2A_REGS2_REG_BASE (OMAP3ISP_REG_BASE + \
88 OMAP3ISP_CSI2A_REGS2_REG_OFFSET)
89#define OMAP3ISP_CSI2A_REGS2_REG(offset) \
90 (OMAP3ISP_CSI2A_REGS2_REG_BASE + (offset))
91
92#define OMAP3ISP_CSI2C_REGS1_REG_OFFSET 0x1C00
93#define OMAP3ISP_CSI2C_REGS1_REG_BASE (OMAP3ISP_REG_BASE + \
94 OMAP3ISP_CSI2C_REGS1_REG_OFFSET)
95#define OMAP3ISP_CSI2C_REGS1_REG(offset) \
96 (OMAP3ISP_CSI2C_REGS1_REG_BASE + (offset))
97
98#define OMAP3ISP_CSIPHY1_REG_OFFSET 0x1D70
99#define OMAP3ISP_CSIPHY1_REG_BASE (OMAP3ISP_REG_BASE + \
100 OMAP3ISP_CSIPHY1_REG_OFFSET)
101#define OMAP3ISP_CSIPHY1_REG(offset) (OMAP3ISP_CSIPHY1_REG_BASE + (offset))
102
103#define OMAP3ISP_CSI2C_REGS2_REG_OFFSET 0x1DC0
104#define OMAP3ISP_CSI2C_REGS2_REG_BASE (OMAP3ISP_REG_BASE + \
105 OMAP3ISP_CSI2C_REGS2_REG_OFFSET)
106#define OMAP3ISP_CSI2C_REGS2_REG(offset) \
107 (OMAP3ISP_CSI2C_REGS2_REG_BASE + (offset))
108
109/* ISP module register offset */
110
111#define ISP_REVISION (0x000)
112#define ISP_SYSCONFIG (0x004)
113#define ISP_SYSSTATUS (0x008)
114#define ISP_IRQ0ENABLE (0x00C)
115#define ISP_IRQ0STATUS (0x010)
116#define ISP_IRQ1ENABLE (0x014)
117#define ISP_IRQ1STATUS (0x018)
118#define ISP_TCTRL_GRESET_LENGTH (0x030)
119#define ISP_TCTRL_PSTRB_REPLAY (0x034)
120#define ISP_CTRL (0x040)
121#define ISP_SECURE (0x044)
122#define ISP_TCTRL_CTRL (0x050)
123#define ISP_TCTRL_FRAME (0x054)
124#define ISP_TCTRL_PSTRB_DELAY (0x058)
125#define ISP_TCTRL_STRB_DELAY (0x05C)
126#define ISP_TCTRL_SHUT_DELAY (0x060)
127#define ISP_TCTRL_PSTRB_LENGTH (0x064)
128#define ISP_TCTRL_STRB_LENGTH (0x068)
129#define ISP_TCTRL_SHUT_LENGTH (0x06C)
130#define ISP_PING_PONG_ADDR (0x070)
131#define ISP_PING_PONG_MEM_RANGE (0x074)
132#define ISP_PING_PONG_BUF_SIZE (0x078)
133
134/* CCP2 receiver registers */
135
136#define ISPCCP2_REVISION (0x000)
137#define ISPCCP2_SYSCONFIG (0x004)
138#define ISPCCP2_SYSCONFIG_SOFT_RESET (1 << 1)
139#define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1
140#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
141#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \
142 (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
143#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO \
144 (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
145#define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \
146 (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
147#define ISPCCP2_SYSSTATUS (0x008)
148#define ISPCCP2_SYSSTATUS_RESET_DONE (1 << 0)
149#define ISPCCP2_LC01_IRQENABLE (0x00C)
150#define ISPCCP2_LC01_IRQSTATUS (0x010)
151#define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ (1 << 11)
152#define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ (1 << 10)
153#define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ (1 << 9)
154#define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ (1 << 8)
155#define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ (1 << 7)
156#define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5)
157#define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ (1 << 4)
158#define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ (1 << 3)
159#define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ (1 << 2)
160#define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ (1 << 1)
161#define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ (1 << 0)
162
163#define ISPCCP2_LC23_IRQENABLE (0x014)
164#define ISPCCP2_LC23_IRQSTATUS (0x018)
165#define ISPCCP2_LCM_IRQENABLE (0x02C)
166#define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ (1 << 0)
167#define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ (1 << 1)
168#define ISPCCP2_LCM_IRQSTATUS (0x030)
169#define ISPCCP2_CTRL (0x040)
170#define ISPCCP2_CTRL_IF_EN (1 << 0)
171#define ISPCCP2_CTRL_PHY_SEL (1 << 1)
172#define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1)
173#define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1)
174#define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
175#define ISPCCP2_CTRL_PHY_SEL_SHIFT 1
176#define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2)
177#define ISPCCP2_CTRL_MODE (1 << 4)
178#define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9)
179#define ISPCCP2_CTRL_INV (1 << 10)
180#define ISPCCP2_CTRL_INV_MASK 0x1
181#define ISPCCP2_CTRL_INV_SHIFT 10
182#define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11)
183#define ISPCCP2_CTRL_VP_CLK_POL (1 << 12)
184#define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15
185#define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */
186#define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT 8 /* 3430 bits */
187#define ISPCCP2_CTRL_VP_OUT_CTRL_MASK 0x3 /* 3430 bits */
188#define ISPCCP2_DBG (0x044)
189#define ISPCCP2_GNQ (0x048)
190#define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x))
191#define ISPCCP2_LCx_CTRL_CHAN_EN (1 << 0)
192#define ISPCCP2_LCx_CTRL_CRC_EN (1 << 19)
193#define ISPCCP2_LCx_CTRL_CRC_MASK 0x1
194#define ISPCCP2_LCx_CTRL_CRC_SHIFT 2
195#define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19
196#define ISPCCP2_LCx_CTRL_REGION_EN (1 << 1)
197#define ISPCCP2_LCx_CTRL_REGION_MASK 0x1
198#define ISPCCP2_LCx_CTRL_REGION_SHIFT 1
199#define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f
200#define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0 0x2
201#define ISPCCP2_LCx_CTRL_FORMAT_MASK 0x1f
202#define ISPCCP2_LCx_CTRL_FORMAT_SHIFT 0x3
203#define ISPCCP2_LCx_CODE(x) ((0x054)+0x30*(x))
204#define ISPCCP2_LCx_STAT_START(x) ((0x058)+0x30*(x))
205#define ISPCCP2_LCx_STAT_SIZE(x) ((0x05C)+0x30*(x))
206#define ISPCCP2_LCx_SOF_ADDR(x) ((0x060)+0x30*(x))
207#define ISPCCP2_LCx_EOF_ADDR(x) ((0x064)+0x30*(x))
208#define ISPCCP2_LCx_DAT_START(x) ((0x068)+0x30*(x))
209#define ISPCCP2_LCx_DAT_SIZE(x) ((0x06C)+0x30*(x))
210#define ISPCCP2_LCx_DAT_MASK 0xFFF
211#define ISPCCP2_LCx_DAT_SHIFT 16
212#define ISPCCP2_LCx_DAT_PING_ADDR(x) ((0x070)+0x30*(x))
213#define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x))
214#define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x))
215#define ISPCCP2_LCM_CTRL (0x1D0)
216#define ISPCCP2_LCM_CTRL_CHAN_EN (1 << 0)
217#define ISPCCP2_LCM_CTRL_DST_PORT (1 << 2)
218#define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2
219#define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3
220#define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11
221#define ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT 5
222#define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK 0x7
223#define ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT 16
224#define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7
225#define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20
226#define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3
227#define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED (1 << 22)
228#define ISPCCP2_LCM_CTRL_SRC_PACK (1 << 23)
229#define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24
230#define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7
231#define ISPCCP2_LCM_VSIZE (0x1D4)
232#define ISPCCP2_LCM_VSIZE_SHIFT 16
233#define ISPCCP2_LCM_HSIZE (0x1D8)
234#define ISPCCP2_LCM_HSIZE_SHIFT 16
235#define ISPCCP2_LCM_PREFETCH (0x1DC)
236#define ISPCCP2_LCM_PREFETCH_SHIFT 3
237#define ISPCCP2_LCM_SRC_ADDR (0x1E0)
238#define ISPCCP2_LCM_SRC_OFST (0x1E4)
239#define ISPCCP2_LCM_DST_ADDR (0x1E8)
240#define ISPCCP2_LCM_DST_OFST (0x1EC)
241
242/* CCDC module register offset */
243
244#define ISPCCDC_PID (0x000)
245#define ISPCCDC_PCR (0x004)
246#define ISPCCDC_SYN_MODE (0x008)
247#define ISPCCDC_HD_VD_WID (0x00C)
248#define ISPCCDC_PIX_LINES (0x010)
249#define ISPCCDC_HORZ_INFO (0x014)
250#define ISPCCDC_VERT_START (0x018)
251#define ISPCCDC_VERT_LINES (0x01C)
252#define ISPCCDC_CULLING (0x020)
253#define ISPCCDC_HSIZE_OFF (0x024)
254#define ISPCCDC_SDOFST (0x028)
255#define ISPCCDC_SDR_ADDR (0x02C)
256#define ISPCCDC_CLAMP (0x030)
257#define ISPCCDC_DCSUB (0x034)
258#define ISPCCDC_COLPTN (0x038)
259#define ISPCCDC_BLKCMP (0x03C)
260#define ISPCCDC_FPC (0x040)
261#define ISPCCDC_FPC_ADDR (0x044)
262#define ISPCCDC_VDINT (0x048)
263#define ISPCCDC_ALAW (0x04C)
264#define ISPCCDC_REC656IF (0x050)
265#define ISPCCDC_CFG (0x054)
266#define ISPCCDC_FMTCFG (0x058)
267#define ISPCCDC_FMT_HORZ (0x05C)
268#define ISPCCDC_FMT_VERT (0x060)
269#define ISPCCDC_FMT_ADDR0 (0x064)
270#define ISPCCDC_FMT_ADDR1 (0x068)
271#define ISPCCDC_FMT_ADDR2 (0x06C)
272#define ISPCCDC_FMT_ADDR3 (0x070)
273#define ISPCCDC_FMT_ADDR4 (0x074)
274#define ISPCCDC_FMT_ADDR5 (0x078)
275#define ISPCCDC_FMT_ADDR6 (0x07C)
276#define ISPCCDC_FMT_ADDR7 (0x080)
277#define ISPCCDC_PRGEVEN0 (0x084)
278#define ISPCCDC_PRGEVEN1 (0x088)
279#define ISPCCDC_PRGODD0 (0x08C)
280#define ISPCCDC_PRGODD1 (0x090)
281#define ISPCCDC_VP_OUT (0x094)
282
283#define ISPCCDC_LSC_CONFIG (0x098)
284#define ISPCCDC_LSC_INITIAL (0x09C)
285#define ISPCCDC_LSC_TABLE_BASE (0x0A0)
286#define ISPCCDC_LSC_TABLE_OFFSET (0x0A4)
287
288/* SBL */
289#define ISPSBL_PCR 0x4
290#define ISPSBL_PCR_H3A_AEAWB_WBL_OVF (1 << 16)
291#define ISPSBL_PCR_H3A_AF_WBL_OVF (1 << 17)
292#define ISPSBL_PCR_RSZ4_WBL_OVF (1 << 18)
293#define ISPSBL_PCR_RSZ3_WBL_OVF (1 << 19)
294#define ISPSBL_PCR_RSZ2_WBL_OVF (1 << 20)
295#define ISPSBL_PCR_RSZ1_WBL_OVF (1 << 21)
296#define ISPSBL_PCR_PRV_WBL_OVF (1 << 22)
297#define ISPSBL_PCR_CCDC_WBL_OVF (1 << 23)
298#define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF (1 << 24)
299#define ISPSBL_PCR_CSIA_WBL_OVF (1 << 25)
300#define ISPSBL_PCR_CSIB_WBL_OVF (1 << 26)
301#define ISPSBL_CCDC_WR_0 (0x028)
302#define ISPSBL_CCDC_WR_0_DATA_READY (1 << 21)
303#define ISPSBL_CCDC_WR_1 (0x02C)
304#define ISPSBL_CCDC_WR_2 (0x030)
305#define ISPSBL_CCDC_WR_3 (0x034)
306
307#define ISPSBL_SDR_REQ_EXP 0xF8
308#define ISPSBL_SDR_REQ_HIST_EXP_SHIFT 0
309#define ISPSBL_SDR_REQ_HIST_EXP_MASK (0x3FF)
310#define ISPSBL_SDR_REQ_RSZ_EXP_SHIFT 10
311#define ISPSBL_SDR_REQ_RSZ_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT)
312#define ISPSBL_SDR_REQ_PRV_EXP_SHIFT 20
313#define ISPSBL_SDR_REQ_PRV_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT)
314
315/* Histogram registers */
316#define ISPHIST_PID (0x000)
317#define ISPHIST_PCR (0x004)
318#define ISPHIST_CNT (0x008)
319#define ISPHIST_WB_GAIN (0x00C)
320#define ISPHIST_R0_HORZ (0x010)
321#define ISPHIST_R0_VERT (0x014)
322#define ISPHIST_R1_HORZ (0x018)
323#define ISPHIST_R1_VERT (0x01C)
324#define ISPHIST_R2_HORZ (0x020)
325#define ISPHIST_R2_VERT (0x024)
326#define ISPHIST_R3_HORZ (0x028)
327#define ISPHIST_R3_VERT (0x02C)
328#define ISPHIST_ADDR (0x030)
329#define ISPHIST_DATA (0x034)
330#define ISPHIST_RADD (0x038)
331#define ISPHIST_RADD_OFF (0x03C)
332#define ISPHIST_H_V_INFO (0x040)
333
334/* H3A module registers */
335#define ISPH3A_PID (0x000)
336#define ISPH3A_PCR (0x004)
337#define ISPH3A_AEWWIN1 (0x04C)
338#define ISPH3A_AEWINSTART (0x050)
339#define ISPH3A_AEWINBLK (0x054)
340#define ISPH3A_AEWSUBWIN (0x058)
341#define ISPH3A_AEWBUFST (0x05C)
342#define ISPH3A_AFPAX1 (0x008)
343#define ISPH3A_AFPAX2 (0x00C)
344#define ISPH3A_AFPAXSTART (0x010)
345#define ISPH3A_AFIIRSH (0x014)
346#define ISPH3A_AFBUFST (0x018)
347#define ISPH3A_AFCOEF010 (0x01C)
348#define ISPH3A_AFCOEF032 (0x020)
349#define ISPH3A_AFCOEF054 (0x024)
350#define ISPH3A_AFCOEF076 (0x028)
351#define ISPH3A_AFCOEF098 (0x02C)
352#define ISPH3A_AFCOEF0010 (0x030)
353#define ISPH3A_AFCOEF110 (0x034)
354#define ISPH3A_AFCOEF132 (0x038)
355#define ISPH3A_AFCOEF154 (0x03C)
356#define ISPH3A_AFCOEF176 (0x040)
357#define ISPH3A_AFCOEF198 (0x044)
358#define ISPH3A_AFCOEF1010 (0x048)
359
360#define ISPPRV_PCR (0x004)
361#define ISPPRV_HORZ_INFO (0x008)
362#define ISPPRV_VERT_INFO (0x00C)
363#define ISPPRV_RSDR_ADDR (0x010)
364#define ISPPRV_RADR_OFFSET (0x014)
365#define ISPPRV_DSDR_ADDR (0x018)
366#define ISPPRV_DRKF_OFFSET (0x01C)
367#define ISPPRV_WSDR_ADDR (0x020)
368#define ISPPRV_WADD_OFFSET (0x024)
369#define ISPPRV_AVE (0x028)
370#define ISPPRV_HMED (0x02C)
371#define ISPPRV_NF (0x030)
372#define ISPPRV_WB_DGAIN (0x034)
373#define ISPPRV_WBGAIN (0x038)
374#define ISPPRV_WBSEL (0x03C)
375#define ISPPRV_CFA (0x040)
376#define ISPPRV_BLKADJOFF (0x044)
377#define ISPPRV_RGB_MAT1 (0x048)
378#define ISPPRV_RGB_MAT2 (0x04C)
379#define ISPPRV_RGB_MAT3 (0x050)
380#define ISPPRV_RGB_MAT4 (0x054)
381#define ISPPRV_RGB_MAT5 (0x058)
382#define ISPPRV_RGB_OFF1 (0x05C)
383#define ISPPRV_RGB_OFF2 (0x060)
384#define ISPPRV_CSC0 (0x064)
385#define ISPPRV_CSC1 (0x068)
386#define ISPPRV_CSC2 (0x06C)
387#define ISPPRV_CSC_OFFSET (0x070)
388#define ISPPRV_CNT_BRT (0x074)
389#define ISPPRV_CSUP (0x078)
390#define ISPPRV_SETUP_YC (0x07C)
391#define ISPPRV_SET_TBL_ADDR (0x080)
392#define ISPPRV_SET_TBL_DATA (0x084)
393#define ISPPRV_CDC_THR0 (0x090)
394#define ISPPRV_CDC_THR1 (ISPPRV_CDC_THR0 + (0x4))
395#define ISPPRV_CDC_THR2 (ISPPRV_CDC_THR0 + (0x4) * 2)
396#define ISPPRV_CDC_THR3 (ISPPRV_CDC_THR0 + (0x4) * 3)
397
398#define ISPPRV_REDGAMMA_TABLE_ADDR 0x0000
399#define ISPPRV_GREENGAMMA_TABLE_ADDR 0x0400
400#define ISPPRV_BLUEGAMMA_TABLE_ADDR 0x0800
401#define ISPPRV_NF_TABLE_ADDR 0x0C00
402#define ISPPRV_YENH_TABLE_ADDR 0x1000
403#define ISPPRV_CFA_TABLE_ADDR 0x1400
404
405#define ISPPRV_MAXOUTPUT_WIDTH 1280
406#define ISPPRV_MAXOUTPUT_WIDTH_ES2 3300
407#define ISPPRV_MAXOUTPUT_WIDTH_3630 4096
408#define ISPRSZ_MIN_OUTPUT 64
409#define ISPRSZ_MAX_OUTPUT 3312
410
411/* Resizer module register offset */
412#define ISPRSZ_PID (0x000)
413#define ISPRSZ_PCR (0x004)
414#define ISPRSZ_CNT (0x008)
415#define ISPRSZ_OUT_SIZE (0x00C)
416#define ISPRSZ_IN_START (0x010)
417#define ISPRSZ_IN_SIZE (0x014)
418#define ISPRSZ_SDR_INADD (0x018)
419#define ISPRSZ_SDR_INOFF (0x01C)
420#define ISPRSZ_SDR_OUTADD (0x020)
421#define ISPRSZ_SDR_OUTOFF (0x024)
422#define ISPRSZ_HFILT10 (0x028)
423#define ISPRSZ_HFILT32 (0x02C)
424#define ISPRSZ_HFILT54 (0x030)
425#define ISPRSZ_HFILT76 (0x034)
426#define ISPRSZ_HFILT98 (0x038)
427#define ISPRSZ_HFILT1110 (0x03C)
428#define ISPRSZ_HFILT1312 (0x040)
429#define ISPRSZ_HFILT1514 (0x044)
430#define ISPRSZ_HFILT1716 (0x048)
431#define ISPRSZ_HFILT1918 (0x04C)
432#define ISPRSZ_HFILT2120 (0x050)
433#define ISPRSZ_HFILT2322 (0x054)
434#define ISPRSZ_HFILT2524 (0x058)
435#define ISPRSZ_HFILT2726 (0x05C)
436#define ISPRSZ_HFILT2928 (0x060)
437#define ISPRSZ_HFILT3130 (0x064)
438#define ISPRSZ_VFILT10 (0x068)
439#define ISPRSZ_VFILT32 (0x06C)
440#define ISPRSZ_VFILT54 (0x070)
441#define ISPRSZ_VFILT76 (0x074)
442#define ISPRSZ_VFILT98 (0x078)
443#define ISPRSZ_VFILT1110 (0x07C)
444#define ISPRSZ_VFILT1312 (0x080)
445#define ISPRSZ_VFILT1514 (0x084)
446#define ISPRSZ_VFILT1716 (0x088)
447#define ISPRSZ_VFILT1918 (0x08C)
448#define ISPRSZ_VFILT2120 (0x090)
449#define ISPRSZ_VFILT2322 (0x094)
450#define ISPRSZ_VFILT2524 (0x098)
451#define ISPRSZ_VFILT2726 (0x09C)
452#define ISPRSZ_VFILT2928 (0x0A0)
453#define ISPRSZ_VFILT3130 (0x0A4)
454#define ISPRSZ_YENH (0x0A8)
455
456#define ISP_INT_CLR 0xFF113F11
457#define ISPPRV_PCR_EN 1
458#define ISPPRV_PCR_BUSY (1 << 1)
459#define ISPPRV_PCR_SOURCE (1 << 2)
460#define ISPPRV_PCR_ONESHOT (1 << 3)
461#define ISPPRV_PCR_WIDTH (1 << 4)
462#define ISPPRV_PCR_INVALAW (1 << 5)
463#define ISPPRV_PCR_DRKFEN (1 << 6)
464#define ISPPRV_PCR_DRKFCAP (1 << 7)
465#define ISPPRV_PCR_HMEDEN (1 << 8)
466#define ISPPRV_PCR_NFEN (1 << 9)
467#define ISPPRV_PCR_CFAEN (1 << 10)
468#define ISPPRV_PCR_CFAFMT_SHIFT 11
469#define ISPPRV_PCR_CFAFMT_MASK 0x7800
470#define ISPPRV_PCR_CFAFMT_BAYER (0 << 11)
471#define ISPPRV_PCR_CFAFMT_SONYVGA (1 << 11)
472#define ISPPRV_PCR_CFAFMT_RGBFOVEON (2 << 11)
473#define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11)
474#define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11)
475#define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11)
476#define ISPPRV_PCR_YNENHEN (1 << 15)
477#define ISPPRV_PCR_SUPEN (1 << 16)
478#define ISPPRV_PCR_YCPOS_SHIFT 17
479#define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17)
480#define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17)
481#define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17)
482#define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17)
483#define ISPPRV_PCR_RSZPORT (1 << 19)
484#define ISPPRV_PCR_SDRPORT (1 << 20)
485#define ISPPRV_PCR_SCOMP_EN (1 << 21)
486#define ISPPRV_PCR_SCOMP_SFT_SHIFT (22)
487#define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22)
488#define ISPPRV_PCR_GAMMA_BYPASS (1 << 26)
489#define ISPPRV_PCR_DCOREN (1 << 27)
490#define ISPPRV_PCR_DCCOUP (1 << 28)
491#define ISPPRV_PCR_DRK_FAIL (1 << 31)
492
493#define ISPPRV_HORZ_INFO_EPH_SHIFT 0
494#define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff
495#define ISPPRV_HORZ_INFO_SPH_SHIFT 16
496#define ISPPRV_HORZ_INFO_SPH_MASK 0x3fff0
497
498#define ISPPRV_VERT_INFO_ELV_SHIFT 0
499#define ISPPRV_VERT_INFO_ELV_MASK 0x3fff
500#define ISPPRV_VERT_INFO_SLV_SHIFT 16
501#define ISPPRV_VERT_INFO_SLV_MASK 0x3fff0
502
503#define ISPPRV_AVE_EVENDIST_SHIFT 2
504#define ISPPRV_AVE_EVENDIST_1 0x0
505#define ISPPRV_AVE_EVENDIST_2 0x1
506#define ISPPRV_AVE_EVENDIST_3 0x2
507#define ISPPRV_AVE_EVENDIST_4 0x3
508#define ISPPRV_AVE_ODDDIST_SHIFT 4
509#define ISPPRV_AVE_ODDDIST_1 0x0
510#define ISPPRV_AVE_ODDDIST_2 0x1
511#define ISPPRV_AVE_ODDDIST_3 0x2
512#define ISPPRV_AVE_ODDDIST_4 0x3
513
514#define ISPPRV_HMED_THRESHOLD_SHIFT 0
515#define ISPPRV_HMED_EVENDIST (1 << 8)
516#define ISPPRV_HMED_ODDDIST (1 << 9)
517
518#define ISPPRV_WBGAIN_COEF0_SHIFT 0
519#define ISPPRV_WBGAIN_COEF1_SHIFT 8
520#define ISPPRV_WBGAIN_COEF2_SHIFT 16
521#define ISPPRV_WBGAIN_COEF3_SHIFT 24
522
523#define ISPPRV_WBSEL_COEF0 0x0
524#define ISPPRV_WBSEL_COEF1 0x1
525#define ISPPRV_WBSEL_COEF2 0x2
526#define ISPPRV_WBSEL_COEF3 0x3
527
528#define ISPPRV_WBSEL_N0_0_SHIFT 0
529#define ISPPRV_WBSEL_N0_1_SHIFT 2
530#define ISPPRV_WBSEL_N0_2_SHIFT 4
531#define ISPPRV_WBSEL_N0_3_SHIFT 6
532#define ISPPRV_WBSEL_N1_0_SHIFT 8
533#define ISPPRV_WBSEL_N1_1_SHIFT 10
534#define ISPPRV_WBSEL_N1_2_SHIFT 12
535#define ISPPRV_WBSEL_N1_3_SHIFT 14
536#define ISPPRV_WBSEL_N2_0_SHIFT 16
537#define ISPPRV_WBSEL_N2_1_SHIFT 18
538#define ISPPRV_WBSEL_N2_2_SHIFT 20
539#define ISPPRV_WBSEL_N2_3_SHIFT 22
540#define ISPPRV_WBSEL_N3_0_SHIFT 24
541#define ISPPRV_WBSEL_N3_1_SHIFT 26
542#define ISPPRV_WBSEL_N3_2_SHIFT 28
543#define ISPPRV_WBSEL_N3_3_SHIFT 30
544
545#define ISPPRV_CFA_GRADTH_HOR_SHIFT 0
546#define ISPPRV_CFA_GRADTH_VER_SHIFT 8
547
548#define ISPPRV_BLKADJOFF_B_SHIFT 0
549#define ISPPRV_BLKADJOFF_G_SHIFT 8
550#define ISPPRV_BLKADJOFF_R_SHIFT 16
551
552#define ISPPRV_RGB_MAT1_MTX_RR_SHIFT 0
553#define ISPPRV_RGB_MAT1_MTX_GR_SHIFT 16
554
555#define ISPPRV_RGB_MAT2_MTX_BR_SHIFT 0
556#define ISPPRV_RGB_MAT2_MTX_RG_SHIFT 16
557
558#define ISPPRV_RGB_MAT3_MTX_GG_SHIFT 0
559#define ISPPRV_RGB_MAT3_MTX_BG_SHIFT 16
560
561#define ISPPRV_RGB_MAT4_MTX_RB_SHIFT 0
562#define ISPPRV_RGB_MAT4_MTX_GB_SHIFT 16
563
564#define ISPPRV_RGB_MAT5_MTX_BB_SHIFT 0
565
566#define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT 0
567#define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT 16
568
569#define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT 0
570
571#define ISPPRV_CSC0_RY_SHIFT 0
572#define ISPPRV_CSC0_GY_SHIFT 10
573#define ISPPRV_CSC0_BY_SHIFT 20
574
575#define ISPPRV_CSC1_RCB_SHIFT 0
576#define ISPPRV_CSC1_GCB_SHIFT 10
577#define ISPPRV_CSC1_BCB_SHIFT 20
578
579#define ISPPRV_CSC2_RCR_SHIFT 0
580#define ISPPRV_CSC2_GCR_SHIFT 10
581#define ISPPRV_CSC2_BCR_SHIFT 20
582
583#define ISPPRV_CSC_OFFSET_CR_SHIFT 0
584#define ISPPRV_CSC_OFFSET_CB_SHIFT 8
585#define ISPPRV_CSC_OFFSET_Y_SHIFT 16
586
587#define ISPPRV_CNT_BRT_BRT_SHIFT 0
588#define ISPPRV_CNT_BRT_CNT_SHIFT 8
589
590#define ISPPRV_CONTRAST_MAX 0x10
591#define ISPPRV_CONTRAST_MIN 0xFF
592#define ISPPRV_BRIGHT_MIN 0x00
593#define ISPPRV_BRIGHT_MAX 0xFF
594
595#define ISPPRV_CSUP_CSUPG_SHIFT 0
596#define ISPPRV_CSUP_THRES_SHIFT 8
597#define ISPPRV_CSUP_HPYF_SHIFT 16
598
599#define ISPPRV_SETUP_YC_MINC_SHIFT 0
600#define ISPPRV_SETUP_YC_MAXC_SHIFT 8
601#define ISPPRV_SETUP_YC_MINY_SHIFT 16
602#define ISPPRV_SETUP_YC_MAXY_SHIFT 24
603#define ISPPRV_YC_MAX 0xFF
604#define ISPPRV_YC_MIN 0x0
605
606/* Define bit fields within selected registers */
607#define ISP_REVISION_SHIFT 0
608
609#define ISP_SYSCONFIG_AUTOIDLE (1 << 0)
610#define ISP_SYSCONFIG_SOFTRESET (1 << 1)
611#define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12
612#define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0
613#define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1
614#define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x2
615
616#define ISP_SYSSTATUS_RESETDONE 0
617
618#define IRQ0ENABLE_CSIA_IRQ (1 << 0)
619#define IRQ0ENABLE_CSIC_IRQ (1 << 1)
620#define IRQ0ENABLE_CCP2_LCM_IRQ (1 << 3)
621#define IRQ0ENABLE_CCP2_LC0_IRQ (1 << 4)
622#define IRQ0ENABLE_CCP2_LC1_IRQ (1 << 5)
623#define IRQ0ENABLE_CCP2_LC2_IRQ (1 << 6)
624#define IRQ0ENABLE_CCP2_LC3_IRQ (1 << 7)
625#define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ | \
626 IRQ0ENABLE_CCP2_LC0_IRQ | \
627 IRQ0ENABLE_CCP2_LC1_IRQ | \
628 IRQ0ENABLE_CCP2_LC2_IRQ | \
629 IRQ0ENABLE_CCP2_LC3_IRQ)
630
631#define IRQ0ENABLE_CCDC_VD0_IRQ (1 << 8)
632#define IRQ0ENABLE_CCDC_VD1_IRQ (1 << 9)
633#define IRQ0ENABLE_CCDC_VD2_IRQ (1 << 10)
634#define IRQ0ENABLE_CCDC_ERR_IRQ (1 << 11)
635#define IRQ0ENABLE_H3A_AF_DONE_IRQ (1 << 12)
636#define IRQ0ENABLE_H3A_AWB_DONE_IRQ (1 << 13)
637#define IRQ0ENABLE_HIST_DONE_IRQ (1 << 16)
638#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ (1 << 17)
639#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
640#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
641#define IRQ0ENABLE_PRV_DONE_IRQ (1 << 20)
642#define IRQ0ENABLE_RSZ_DONE_IRQ (1 << 24)
643#define IRQ0ENABLE_OVF_IRQ (1 << 25)
644#define IRQ0ENABLE_PING_IRQ (1 << 26)
645#define IRQ0ENABLE_PONG_IRQ (1 << 27)
646#define IRQ0ENABLE_MMU_ERR_IRQ (1 << 28)
647#define IRQ0ENABLE_OCP_ERR_IRQ (1 << 29)
648#define IRQ0ENABLE_SEC_ERR_IRQ (1 << 30)
649#define IRQ0ENABLE_HS_VS_IRQ (1 << 31)
650
651#define IRQ0STATUS_CSIA_IRQ (1 << 0)
652#define IRQ0STATUS_CSI2C_IRQ (1 << 1)
653#define IRQ0STATUS_CCP2_LCM_IRQ (1 << 3)
654#define IRQ0STATUS_CCP2_LC0_IRQ (1 << 4)
655#define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ | \
656 IRQ0STATUS_CCP2_LC0_IRQ)
657
658#define IRQ0STATUS_CSIB_LC1_IRQ (1 << 5)
659#define IRQ0STATUS_CSIB_LC2_IRQ (1 << 6)
660#define IRQ0STATUS_CSIB_LC3_IRQ (1 << 7)
661#define IRQ0STATUS_CCDC_VD0_IRQ (1 << 8)
662#define IRQ0STATUS_CCDC_VD1_IRQ (1 << 9)
663#define IRQ0STATUS_CCDC_VD2_IRQ (1 << 10)
664#define IRQ0STATUS_CCDC_ERR_IRQ (1 << 11)
665#define IRQ0STATUS_H3A_AF_DONE_IRQ (1 << 12)
666#define IRQ0STATUS_H3A_AWB_DONE_IRQ (1 << 13)
667#define IRQ0STATUS_HIST_DONE_IRQ (1 << 16)
668#define IRQ0STATUS_CCDC_LSC_DONE_IRQ (1 << 17)
669#define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
670#define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
671#define IRQ0STATUS_PRV_DONE_IRQ (1 << 20)
672#define IRQ0STATUS_RSZ_DONE_IRQ (1 << 24)
673#define IRQ0STATUS_OVF_IRQ (1 << 25)
674#define IRQ0STATUS_PING_IRQ (1 << 26)
675#define IRQ0STATUS_PONG_IRQ (1 << 27)
676#define IRQ0STATUS_MMU_ERR_IRQ (1 << 28)
677#define IRQ0STATUS_OCP_ERR_IRQ (1 << 29)
678#define IRQ0STATUS_SEC_ERR_IRQ (1 << 30)
679#define IRQ0STATUS_HS_VS_IRQ (1 << 31)
680
681#define TCTRL_GRESET_LEN 0
682
683#define TCTRL_PSTRB_REPLAY_DELAY 0
684#define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT 25
685
686#define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL 0x0
687#define ISPCTRL_PAR_SER_CLK_SEL_CSIA 0x1
688#define ISPCTRL_PAR_SER_CLK_SEL_CSIB 0x2
689#define ISPCTRL_PAR_SER_CLK_SEL_CSIC 0x3
690#define ISPCTRL_PAR_SER_CLK_SEL_MASK 0x3
691
692#define ISPCTRL_PAR_BRIDGE_SHIFT 2
693#define ISPCTRL_PAR_BRIDGE_DISABLE (0x0 << 2)
694#define ISPCTRL_PAR_BRIDGE_LENDIAN (0x2 << 2)
695#define ISPCTRL_PAR_BRIDGE_BENDIAN (0x3 << 2)
696#define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2)
697
698#define ISPCTRL_PAR_CLK_POL_SHIFT 4
699#define ISPCTRL_PAR_CLK_POL_INV (1 << 4)
700#define ISPCTRL_PING_PONG_EN (1 << 5)
701#define ISPCTRL_SHIFT_SHIFT 6
702#define ISPCTRL_SHIFT_0 (0x0 << 6)
703#define ISPCTRL_SHIFT_2 (0x1 << 6)
704#define ISPCTRL_SHIFT_4 (0x2 << 6)
705#define ISPCTRL_SHIFT_MASK (0x3 << 6)
706
707#define ISPCTRL_CCDC_CLK_EN (1 << 8)
708#define ISPCTRL_SCMP_CLK_EN (1 << 9)
709#define ISPCTRL_H3A_CLK_EN (1 << 10)
710#define ISPCTRL_HIST_CLK_EN (1 << 11)
711#define ISPCTRL_PREV_CLK_EN (1 << 12)
712#define ISPCTRL_RSZ_CLK_EN (1 << 13)
713#define ISPCTRL_SYNC_DETECT_SHIFT 14
714#define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
715#define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
716#define ISPCTRL_SYNC_DETECT_VSFALL (0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
717#define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
718#define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
719
720#define ISPCTRL_CCDC_RAM_EN (1 << 16)
721#define ISPCTRL_PREV_RAM_EN (1 << 17)
722#define ISPCTRL_SBL_RD_RAM_EN (1 << 18)
723#define ISPCTRL_SBL_WR1_RAM_EN (1 << 19)
724#define ISPCTRL_SBL_WR0_RAM_EN (1 << 20)
725#define ISPCTRL_SBL_AUTOIDLE (1 << 21)
726#define ISPCTRL_SBL_SHARED_WPORTC (1 << 26)
727#define ISPCTRL_SBL_SHARED_RPORTA (1 << 27)
728#define ISPCTRL_SBL_SHARED_RPORTB (1 << 28)
729#define ISPCTRL_JPEG_FLUSH (1 << 30)
730#define ISPCTRL_CCDC_FLUSH (1 << 31)
731
732#define ISPSECURE_SECUREMODE 0
733
734#define ISPTCTRL_CTRL_DIV_LOW 0x0
735#define ISPTCTRL_CTRL_DIV_HIGH 0x1
736#define ISPTCTRL_CTRL_DIV_BYPASS 0x1F
737
738#define ISPTCTRL_CTRL_DIVA_SHIFT 0
739#define ISPTCTRL_CTRL_DIVA_MASK (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
740
741#define ISPTCTRL_CTRL_DIVB_SHIFT 5
742#define ISPTCTRL_CTRL_DIVB_MASK (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
743
744#define ISPTCTRL_CTRL_DIVC_SHIFT 10
745#define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10)
746
747#define ISPTCTRL_CTRL_SHUTEN (1 << 21)
748#define ISPTCTRL_CTRL_PSTRBEN (1 << 22)
749#define ISPTCTRL_CTRL_STRBEN (1 << 23)
750#define ISPTCTRL_CTRL_SHUTPOL (1 << 24)
751#define ISPTCTRL_CTRL_STRBPSTRBPOL (1 << 26)
752
753#define ISPTCTRL_CTRL_INSEL_SHIFT 27
754#define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27)
755#define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27)
756#define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27)
757
758#define ISPTCTRL_CTRL_GRESETEn (1 << 29)
759#define ISPTCTRL_CTRL_GRESETPOL (1 << 30)
760#define ISPTCTRL_CTRL_GRESETDIR (1 << 31)
761
762#define ISPTCTRL_FRAME_SHUT_SHIFT 0
763#define ISPTCTRL_FRAME_PSTRB_SHIFT 6
764#define ISPTCTRL_FRAME_STRB_SHIFT 12
765
766#define ISPCCDC_PID_PREV_SHIFT 0
767#define ISPCCDC_PID_CID_SHIFT 8
768#define ISPCCDC_PID_TID_SHIFT 16
769
770#define ISPCCDC_PCR_EN 1
771#define ISPCCDC_PCR_BUSY (1 << 1)
772
773#define ISPCCDC_SYN_MODE_VDHDOUT 0x1
774#define ISPCCDC_SYN_MODE_FLDOUT (1 << 1)
775#define ISPCCDC_SYN_MODE_VDPOL (1 << 2)
776#define ISPCCDC_SYN_MODE_HDPOL (1 << 3)
777#define ISPCCDC_SYN_MODE_FLDPOL (1 << 4)
778#define ISPCCDC_SYN_MODE_EXWEN (1 << 5)
779#define ISPCCDC_SYN_MODE_DATAPOL (1 << 6)
780#define ISPCCDC_SYN_MODE_FLDMODE (1 << 7)
781#define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8)
782#define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8)
783#define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8)
784#define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8)
785#define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8)
786#define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8)
787#define ISPCCDC_SYN_MODE_PACK8 (1 << 11)
788#define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12)
789#define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12)
790#define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12)
791#define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12)
792#define ISPCCDC_SYN_MODE_LPF (1 << 14)
793#define ISPCCDC_SYN_MODE_FLDSTAT (1 << 15)
794#define ISPCCDC_SYN_MODE_VDHDEN (1 << 16)
795#define ISPCCDC_SYN_MODE_WEN (1 << 17)
796#define ISPCCDC_SYN_MODE_VP2SDR (1 << 18)
797#define ISPCCDC_SYN_MODE_SDR2RSZ (1 << 19)
798
799#define ISPCCDC_HD_VD_WID_VDW_SHIFT 0
800#define ISPCCDC_HD_VD_WID_HDW_SHIFT 16
801
802#define ISPCCDC_PIX_LINES_HLPRF_SHIFT 0
803#define ISPCCDC_PIX_LINES_PPLN_SHIFT 16
804
805#define ISPCCDC_HORZ_INFO_NPH_SHIFT 0
806#define ISPCCDC_HORZ_INFO_NPH_MASK 0x00007fff
807#define ISPCCDC_HORZ_INFO_SPH_SHIFT 16
808#define ISPCCDC_HORZ_INFO_SPH_MASK 0x7fff0000
809
810#define ISPCCDC_VERT_START_SLV1_SHIFT 0
811#define ISPCCDC_VERT_START_SLV0_SHIFT 16
812#define ISPCCDC_VERT_START_SLV0_MASK 0x7fff0000
813
814#define ISPCCDC_VERT_LINES_NLV_SHIFT 0
815#define ISPCCDC_VERT_LINES_NLV_MASK 0x00007fff
816
817#define ISPCCDC_CULLING_CULV_SHIFT 0
818#define ISPCCDC_CULLING_CULHODD_SHIFT 16
819#define ISPCCDC_CULLING_CULHEVN_SHIFT 24
820
821#define ISPCCDC_HSIZE_OFF_SHIFT 0
822
823#define ISPCCDC_SDOFST_FINV (1 << 14)
824#define ISPCCDC_SDOFST_FOFST_1L 0
825#define ISPCCDC_SDOFST_FOFST_4L (3 << 12)
826#define ISPCCDC_SDOFST_LOFST3_SHIFT 0
827#define ISPCCDC_SDOFST_LOFST2_SHIFT 3
828#define ISPCCDC_SDOFST_LOFST1_SHIFT 6
829#define ISPCCDC_SDOFST_LOFST0_SHIFT 9
830#define EVENEVEN 1
831#define ODDEVEN 2
832#define EVENODD 3
833#define ODDODD 4
834
835#define ISPCCDC_CLAMP_OBGAIN_SHIFT 0
836#define ISPCCDC_CLAMP_OBST_SHIFT 10
837#define ISPCCDC_CLAMP_OBSLN_SHIFT 25
838#define ISPCCDC_CLAMP_OBSLEN_SHIFT 28
839#define ISPCCDC_CLAMP_CLAMPEN (1 << 31)
840
841#define ISPCCDC_COLPTN_R_Ye 0x0
842#define ISPCCDC_COLPTN_Gr_Cy 0x1
843#define ISPCCDC_COLPTN_Gb_G 0x2
844#define ISPCCDC_COLPTN_B_Mg 0x3
845#define ISPCCDC_COLPTN_CP0PLC0_SHIFT 0
846#define ISPCCDC_COLPTN_CP0PLC1_SHIFT 2
847#define ISPCCDC_COLPTN_CP0PLC2_SHIFT 4
848#define ISPCCDC_COLPTN_CP0PLC3_SHIFT 6
849#define ISPCCDC_COLPTN_CP1PLC0_SHIFT 8
850#define ISPCCDC_COLPTN_CP1PLC1_SHIFT 10
851#define ISPCCDC_COLPTN_CP1PLC2_SHIFT 12
852#define ISPCCDC_COLPTN_CP1PLC3_SHIFT 14
853#define ISPCCDC_COLPTN_CP2PLC0_SHIFT 16
854#define ISPCCDC_COLPTN_CP2PLC1_SHIFT 18
855#define ISPCCDC_COLPTN_CP2PLC2_SHIFT 20
856#define ISPCCDC_COLPTN_CP2PLC3_SHIFT 22
857#define ISPCCDC_COLPTN_CP3PLC0_SHIFT 24
858#define ISPCCDC_COLPTN_CP3PLC1_SHIFT 26
859#define ISPCCDC_COLPTN_CP3PLC2_SHIFT 28
860#define ISPCCDC_COLPTN_CP3PLC3_SHIFT 30
861
862#define ISPCCDC_BLKCMP_B_MG_SHIFT 0
863#define ISPCCDC_BLKCMP_GB_G_SHIFT 8
864#define ISPCCDC_BLKCMP_GR_CY_SHIFT 16
865#define ISPCCDC_BLKCMP_R_YE_SHIFT 24
866
867#define ISPCCDC_FPC_FPNUM_SHIFT 0
868#define ISPCCDC_FPC_FPCEN (1 << 15)
869#define ISPCCDC_FPC_FPERR (1 << 16)
870
871#define ISPCCDC_VDINT_1_SHIFT 0
872#define ISPCCDC_VDINT_1_MASK 0x00007fff
873#define ISPCCDC_VDINT_0_SHIFT 16
874#define ISPCCDC_VDINT_0_MASK 0x7fff0000
875
876#define ISPCCDC_ALAW_GWDI_12_3 (0x3 << 0)
877#define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0)
878#define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0)
879#define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0)
880#define ISPCCDC_ALAW_CCDTBL (1 << 3)
881
882#define ISPCCDC_REC656IF_R656ON 1
883#define ISPCCDC_REC656IF_ECCFVH (1 << 1)
884
885#define ISPCCDC_CFG_BW656 (1 << 5)
886#define ISPCCDC_CFG_FIDMD_SHIFT 6
887#define ISPCCDC_CFG_WENLOG (1 << 8)
888#define ISPCCDC_CFG_WENLOG_AND (0 << 8)
889#define ISPCCDC_CFG_WENLOG_OR (1 << 8)
890#define ISPCCDC_CFG_Y8POS (1 << 11)
891#define ISPCCDC_CFG_BSWD (1 << 12)
892#define ISPCCDC_CFG_MSBINVI (1 << 13)
893#define ISPCCDC_CFG_VDLC (1 << 15)
894
895#define ISPCCDC_FMTCFG_FMTEN 0x1
896#define ISPCCDC_FMTCFG_LNALT (1 << 1)
897#define ISPCCDC_FMTCFG_LNUM_SHIFT 2
898#define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4
899#define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8
900#define ISPCCDC_FMTCFG_VPIN_MASK 0x00007000
901#define ISPCCDC_FMTCFG_VPIN_12_3 (0x3 << 12)
902#define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12)
903#define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12)
904#define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12)
905#define ISPCCDC_FMTCFG_VPEN (1 << 15)
906
907#define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000
908#define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16
909#define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 (0x0 << 16)
910#define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 (0x1 << 16)
911#define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 (0x2 << 16)
912#define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 (0x3 << 16)
913#define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 (0x4 << 16)
914
915#define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT 0
916#define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT 16
917
918#define ISPCCDC_FMT_VERT_FMTLNV_SHIFT 0
919#define ISPCCDC_FMT_VERT_FMTSLV_SHIFT 16
920
921#define ISPCCDC_FMT_HORZ_FMTSPH_MASK 0x1fff0000
922#define ISPCCDC_FMT_HORZ_FMTLNH_MASK 0x00001fff
923
924#define ISPCCDC_FMT_VERT_FMTSLV_MASK 0x1fff0000
925#define ISPCCDC_FMT_VERT_FMTLNV_MASK 0x00001fff
926
927#define ISPCCDC_VP_OUT_HORZ_ST_SHIFT 0
928#define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT 4
929#define ISPCCDC_VP_OUT_VERT_NUM_SHIFT 17
930
931#define ISPRSZ_PID_PREV_SHIFT 0
932#define ISPRSZ_PID_CID_SHIFT 8
933#define ISPRSZ_PID_TID_SHIFT 16
934
935#define ISPRSZ_PCR_ENABLE (1 << 0)
936#define ISPRSZ_PCR_BUSY (1 << 1)
937#define ISPRSZ_PCR_ONESHOT (1 << 2)
938
939#define ISPRSZ_CNT_HRSZ_SHIFT 0
940#define ISPRSZ_CNT_HRSZ_MASK \
941 (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT)
942#define ISPRSZ_CNT_VRSZ_SHIFT 10
943#define ISPRSZ_CNT_VRSZ_MASK \
944 (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT)
945#define ISPRSZ_CNT_HSTPH_SHIFT 20
946#define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
947#define ISPRSZ_CNT_VSTPH_SHIFT 23
948#define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
949#define ISPRSZ_CNT_YCPOS (1 << 26)
950#define ISPRSZ_CNT_INPTYP (1 << 27)
951#define ISPRSZ_CNT_INPSRC (1 << 28)
952#define ISPRSZ_CNT_CBILIN (1 << 29)
953
954#define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0
955#define ISPRSZ_OUT_SIZE_HORZ_MASK \
956 (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT)
957#define ISPRSZ_OUT_SIZE_VERT_SHIFT 16
958#define ISPRSZ_OUT_SIZE_VERT_MASK \
959 (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT)
960
961#define ISPRSZ_IN_START_HORZ_ST_SHIFT 0
962#define ISPRSZ_IN_START_HORZ_ST_MASK \
963 (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT)
964#define ISPRSZ_IN_START_VERT_ST_SHIFT 16
965#define ISPRSZ_IN_START_VERT_ST_MASK \
966 (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT)
967
968#define ISPRSZ_IN_SIZE_HORZ_SHIFT 0
969#define ISPRSZ_IN_SIZE_HORZ_MASK \
970 (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT)
971#define ISPRSZ_IN_SIZE_VERT_SHIFT 16
972#define ISPRSZ_IN_SIZE_VERT_MASK \
973 (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT)
974
975#define ISPRSZ_SDR_INADD_ADDR_SHIFT 0
976#define ISPRSZ_SDR_INADD_ADDR_MASK 0xFFFFFFFF
977
978#define ISPRSZ_SDR_INOFF_OFFSET_SHIFT 0
979#define ISPRSZ_SDR_INOFF_OFFSET_MASK \
980 (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT)
981
982#define ISPRSZ_SDR_OUTADD_ADDR_SHIFT 0
983#define ISPRSZ_SDR_OUTADD_ADDR_MASK 0xFFFFFFFF
984
985
986#define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT 0
987#define ISPRSZ_SDR_OUTOFF_OFFSET_MASK \
988 (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT)
989
990#define ISPRSZ_HFILT_COEF0_SHIFT 0
991#define ISPRSZ_HFILT_COEF0_MASK \
992 (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT)
993#define ISPRSZ_HFILT_COEF1_SHIFT 16
994#define ISPRSZ_HFILT_COEF1_MASK \
995 (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT)
996
997#define ISPRSZ_HFILT32_COEF2_SHIFT 0
998#define ISPRSZ_HFILT32_COEF2_MASK 0x3FF
999#define ISPRSZ_HFILT32_COEF3_SHIFT 16
1000#define ISPRSZ_HFILT32_COEF3_MASK 0x3FF0000
1001
1002#define ISPRSZ_HFILT54_COEF4_SHIFT 0
1003#define ISPRSZ_HFILT54_COEF4_MASK 0x3FF
1004#define ISPRSZ_HFILT54_COEF5_SHIFT 16
1005#define ISPRSZ_HFILT54_COEF5_MASK 0x3FF0000
1006
1007#define ISPRSZ_HFILT76_COEFF6_SHIFT 0
1008#define ISPRSZ_HFILT76_COEFF6_MASK 0x3FF
1009#define ISPRSZ_HFILT76_COEFF7_SHIFT 16
1010#define ISPRSZ_HFILT76_COEFF7_MASK 0x3FF0000
1011
1012#define ISPRSZ_HFILT98_COEFF8_SHIFT 0
1013#define ISPRSZ_HFILT98_COEFF8_MASK 0x3FF
1014#define ISPRSZ_HFILT98_COEFF9_SHIFT 16
1015#define ISPRSZ_HFILT98_COEFF9_MASK 0x3FF0000
1016
1017#define ISPRSZ_HFILT1110_COEF10_SHIFT 0
1018#define ISPRSZ_HFILT1110_COEF10_MASK 0x3FF
1019#define ISPRSZ_HFILT1110_COEF11_SHIFT 16
1020#define ISPRSZ_HFILT1110_COEF11_MASK 0x3FF0000
1021
1022#define ISPRSZ_HFILT1312_COEFF12_SHIFT 0
1023#define ISPRSZ_HFILT1312_COEFF12_MASK 0x3FF
1024#define ISPRSZ_HFILT1312_COEFF13_SHIFT 16
1025#define ISPRSZ_HFILT1312_COEFF13_MASK 0x3FF0000
1026
1027#define ISPRSZ_HFILT1514_COEFF14_SHIFT 0
1028#define ISPRSZ_HFILT1514_COEFF14_MASK 0x3FF
1029#define ISPRSZ_HFILT1514_COEFF15_SHIFT 16
1030#define ISPRSZ_HFILT1514_COEFF15_MASK 0x3FF0000
1031
1032#define ISPRSZ_HFILT1716_COEF16_SHIFT 0
1033#define ISPRSZ_HFILT1716_COEF16_MASK 0x3FF
1034#define ISPRSZ_HFILT1716_COEF17_SHIFT 16
1035#define ISPRSZ_HFILT1716_COEF17_MASK 0x3FF0000
1036
1037#define ISPRSZ_HFILT1918_COEF18_SHIFT 0
1038#define ISPRSZ_HFILT1918_COEF18_MASK 0x3FF
1039#define ISPRSZ_HFILT1918_COEF19_SHIFT 16
1040#define ISPRSZ_HFILT1918_COEF19_MASK 0x3FF0000
1041
1042#define ISPRSZ_HFILT2120_COEF20_SHIFT 0
1043#define ISPRSZ_HFILT2120_COEF20_MASK 0x3FF
1044#define ISPRSZ_HFILT2120_COEF21_SHIFT 16
1045#define ISPRSZ_HFILT2120_COEF21_MASK 0x3FF0000
1046
1047#define ISPRSZ_HFILT2322_COEF22_SHIFT 0
1048#define ISPRSZ_HFILT2322_COEF22_MASK 0x3FF
1049#define ISPRSZ_HFILT2322_COEF23_SHIFT 16
1050#define ISPRSZ_HFILT2322_COEF23_MASK 0x3FF0000
1051
1052#define ISPRSZ_HFILT2524_COEF24_SHIFT 0
1053#define ISPRSZ_HFILT2524_COEF24_MASK 0x3FF
1054#define ISPRSZ_HFILT2524_COEF25_SHIFT 16
1055#define ISPRSZ_HFILT2524_COEF25_MASK 0x3FF0000
1056
1057#define ISPRSZ_HFILT2726_COEF26_SHIFT 0
1058#define ISPRSZ_HFILT2726_COEF26_MASK 0x3FF
1059#define ISPRSZ_HFILT2726_COEF27_SHIFT 16
1060#define ISPRSZ_HFILT2726_COEF27_MASK 0x3FF0000
1061
1062#define ISPRSZ_HFILT2928_COEF28_SHIFT 0
1063#define ISPRSZ_HFILT2928_COEF28_MASK 0x3FF
1064#define ISPRSZ_HFILT2928_COEF29_SHIFT 16
1065#define ISPRSZ_HFILT2928_COEF29_MASK 0x3FF0000
1066
1067#define ISPRSZ_HFILT3130_COEF30_SHIFT 0
1068#define ISPRSZ_HFILT3130_COEF30_MASK 0x3FF
1069#define ISPRSZ_HFILT3130_COEF31_SHIFT 16
1070#define ISPRSZ_HFILT3130_COEF31_MASK 0x3FF0000
1071
1072#define ISPRSZ_VFILT_COEF0_SHIFT 0
1073#define ISPRSZ_VFILT_COEF0_MASK \
1074 (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT)
1075#define ISPRSZ_VFILT_COEF1_SHIFT 16
1076#define ISPRSZ_VFILT_COEF1_MASK \
1077 (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT)
1078
1079#define ISPRSZ_VFILT10_COEF0_SHIFT 0
1080#define ISPRSZ_VFILT10_COEF0_MASK 0x3FF
1081#define ISPRSZ_VFILT10_COEF1_SHIFT 16
1082#define ISPRSZ_VFILT10_COEF1_MASK 0x3FF0000
1083
1084#define ISPRSZ_VFILT32_COEF2_SHIFT 0
1085#define ISPRSZ_VFILT32_COEF2_MASK 0x3FF
1086#define ISPRSZ_VFILT32_COEF3_SHIFT 16
1087#define ISPRSZ_VFILT32_COEF3_MASK 0x3FF0000
1088
1089#define ISPRSZ_VFILT54_COEF4_SHIFT 0
1090#define ISPRSZ_VFILT54_COEF4_MASK 0x3FF
1091#define ISPRSZ_VFILT54_COEF5_SHIFT 16
1092#define ISPRSZ_VFILT54_COEF5_MASK 0x3FF0000
1093
1094#define ISPRSZ_VFILT76_COEFF6_SHIFT 0
1095#define ISPRSZ_VFILT76_COEFF6_MASK 0x3FF
1096#define ISPRSZ_VFILT76_COEFF7_SHIFT 16
1097#define ISPRSZ_VFILT76_COEFF7_MASK 0x3FF0000
1098
1099#define ISPRSZ_VFILT98_COEFF8_SHIFT 0
1100#define ISPRSZ_VFILT98_COEFF8_MASK 0x3FF
1101#define ISPRSZ_VFILT98_COEFF9_SHIFT 16
1102#define ISPRSZ_VFILT98_COEFF9_MASK 0x3FF0000
1103
1104#define ISPRSZ_VFILT1110_COEF10_SHIFT 0
1105#define ISPRSZ_VFILT1110_COEF10_MASK 0x3FF
1106#define ISPRSZ_VFILT1110_COEF11_SHIFT 16
1107#define ISPRSZ_VFILT1110_COEF11_MASK 0x3FF0000
1108
1109#define ISPRSZ_VFILT1312_COEFF12_SHIFT 0
1110#define ISPRSZ_VFILT1312_COEFF12_MASK 0x3FF
1111#define ISPRSZ_VFILT1312_COEFF13_SHIFT 16
1112#define ISPRSZ_VFILT1312_COEFF13_MASK 0x3FF0000
1113
1114#define ISPRSZ_VFILT1514_COEFF14_SHIFT 0
1115#define ISPRSZ_VFILT1514_COEFF14_MASK 0x3FF
1116#define ISPRSZ_VFILT1514_COEFF15_SHIFT 16
1117#define ISPRSZ_VFILT1514_COEFF15_MASK 0x3FF0000
1118
1119#define ISPRSZ_VFILT1716_COEF16_SHIFT 0
1120#define ISPRSZ_VFILT1716_COEF16_MASK 0x3FF
1121#define ISPRSZ_VFILT1716_COEF17_SHIFT 16
1122#define ISPRSZ_VFILT1716_COEF17_MASK 0x3FF0000
1123
1124#define ISPRSZ_VFILT1918_COEF18_SHIFT 0
1125#define ISPRSZ_VFILT1918_COEF18_MASK 0x3FF
1126#define ISPRSZ_VFILT1918_COEF19_SHIFT 16
1127#define ISPRSZ_VFILT1918_COEF19_MASK 0x3FF0000
1128
1129#define ISPRSZ_VFILT2120_COEF20_SHIFT 0
1130#define ISPRSZ_VFILT2120_COEF20_MASK 0x3FF
1131#define ISPRSZ_VFILT2120_COEF21_SHIFT 16
1132#define ISPRSZ_VFILT2120_COEF21_MASK 0x3FF0000
1133
1134#define ISPRSZ_VFILT2322_COEF22_SHIFT 0
1135#define ISPRSZ_VFILT2322_COEF22_MASK 0x3FF
1136#define ISPRSZ_VFILT2322_COEF23_SHIFT 16
1137#define ISPRSZ_VFILT2322_COEF23_MASK 0x3FF0000
1138
1139#define ISPRSZ_VFILT2524_COEF24_SHIFT 0
1140#define ISPRSZ_VFILT2524_COEF24_MASK 0x3FF
1141#define ISPRSZ_VFILT2524_COEF25_SHIFT 16
1142#define ISPRSZ_VFILT2524_COEF25_MASK 0x3FF0000
1143
1144#define ISPRSZ_VFILT2726_COEF26_SHIFT 0
1145#define ISPRSZ_VFILT2726_COEF26_MASK 0x3FF
1146#define ISPRSZ_VFILT2726_COEF27_SHIFT 16
1147#define ISPRSZ_VFILT2726_COEF27_MASK 0x3FF0000
1148
1149#define ISPRSZ_VFILT2928_COEF28_SHIFT 0
1150#define ISPRSZ_VFILT2928_COEF28_MASK 0x3FF
1151#define ISPRSZ_VFILT2928_COEF29_SHIFT 16
1152#define ISPRSZ_VFILT2928_COEF29_MASK 0x3FF0000
1153
1154#define ISPRSZ_VFILT3130_COEF30_SHIFT 0
1155#define ISPRSZ_VFILT3130_COEF30_MASK 0x3FF
1156#define ISPRSZ_VFILT3130_COEF31_SHIFT 16
1157#define ISPRSZ_VFILT3130_COEF31_MASK 0x3FF0000
1158
1159#define ISPRSZ_YENH_CORE_SHIFT 0
1160#define ISPRSZ_YENH_CORE_MASK \
1161 (0xFF << ISPRSZ_YENH_CORE_SHIFT)
1162#define ISPRSZ_YENH_SLOP_SHIFT 8
1163#define ISPRSZ_YENH_SLOP_MASK \
1164 (0xF << ISPRSZ_YENH_SLOP_SHIFT)
1165#define ISPRSZ_YENH_GAIN_SHIFT 12
1166#define ISPRSZ_YENH_GAIN_MASK \
1167 (0xF << ISPRSZ_YENH_GAIN_SHIFT)
1168#define ISPRSZ_YENH_ALGO_SHIFT 16
1169#define ISPRSZ_YENH_ALGO_MASK \
1170 (0x3 << ISPRSZ_YENH_ALGO_SHIFT)
1171
1172#define ISPH3A_PCR_AEW_ALAW_EN_SHIFT 1
1173#define ISPH3A_PCR_AF_MED_TH_SHIFT 3
1174#define ISPH3A_PCR_AF_RGBPOS_SHIFT 11
1175#define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22
1176#define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000
1177#define ISPH3A_PCR_BUSYAF (1 << 15)
1178#define ISPH3A_PCR_BUSYAEAWB (1 << 18)
1179
1180#define ISPH3A_AEWWIN1_WINHC_SHIFT 0
1181#define ISPH3A_AEWWIN1_WINHC_MASK 0x3F
1182#define ISPH3A_AEWWIN1_WINVC_SHIFT 6
1183#define ISPH3A_AEWWIN1_WINVC_MASK 0x1FC0
1184#define ISPH3A_AEWWIN1_WINW_SHIFT 13
1185#define ISPH3A_AEWWIN1_WINW_MASK 0xFE000
1186#define ISPH3A_AEWWIN1_WINH_SHIFT 24
1187#define ISPH3A_AEWWIN1_WINH_MASK 0x7F000000
1188
1189#define ISPH3A_AEWINSTART_WINSH_SHIFT 0
1190#define ISPH3A_AEWINSTART_WINSH_MASK 0x0FFF
1191#define ISPH3A_AEWINSTART_WINSV_SHIFT 16
1192#define ISPH3A_AEWINSTART_WINSV_MASK 0x0FFF0000
1193
1194#define ISPH3A_AEWINBLK_WINH_SHIFT 0
1195#define ISPH3A_AEWINBLK_WINH_MASK 0x7F
1196#define ISPH3A_AEWINBLK_WINSV_SHIFT 16
1197#define ISPH3A_AEWINBLK_WINSV_MASK 0x0FFF0000
1198
1199#define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT 0
1200#define ISPH3A_AEWSUBWIN_AEWINCH_MASK 0x0F
1201#define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT 8
1202#define ISPH3A_AEWSUBWIN_AEWINCV_MASK 0x0F00
1203
1204#define ISPHIST_PCR_ENABLE_SHIFT 0
1205#define ISPHIST_PCR_ENABLE_MASK 0x01
1206#define ISPHIST_PCR_ENABLE (1 << ISPHIST_PCR_ENABLE_SHIFT)
1207#define ISPHIST_PCR_BUSY 0x02
1208
1209#define ISPHIST_CNT_DATASIZE_SHIFT 8
1210#define ISPHIST_CNT_DATASIZE_MASK 0x0100
1211#define ISPHIST_CNT_CLEAR_SHIFT 7
1212#define ISPHIST_CNT_CLEAR_MASK 0x080
1213#define ISPHIST_CNT_CLEAR (1 << ISPHIST_CNT_CLEAR_SHIFT)
1214#define ISPHIST_CNT_CFA_SHIFT 6
1215#define ISPHIST_CNT_CFA_MASK 0x040
1216#define ISPHIST_CNT_BINS_SHIFT 4
1217#define ISPHIST_CNT_BINS_MASK 0x030
1218#define ISPHIST_CNT_SOURCE_SHIFT 3
1219#define ISPHIST_CNT_SOURCE_MASK 0x08
1220#define ISPHIST_CNT_SHIFT_SHIFT 0
1221#define ISPHIST_CNT_SHIFT_MASK 0x07
1222
1223#define ISPHIST_WB_GAIN_WG00_SHIFT 24
1224#define ISPHIST_WB_GAIN_WG00_MASK 0xFF000000
1225#define ISPHIST_WB_GAIN_WG01_SHIFT 16
1226#define ISPHIST_WB_GAIN_WG01_MASK 0xFF0000
1227#define ISPHIST_WB_GAIN_WG02_SHIFT 8
1228#define ISPHIST_WB_GAIN_WG02_MASK 0xFF00
1229#define ISPHIST_WB_GAIN_WG03_SHIFT 0
1230#define ISPHIST_WB_GAIN_WG03_MASK 0xFF
1231
1232#define ISPHIST_REG_START_END_MASK 0x3FFF
1233#define ISPHIST_REG_START_SHIFT 16
1234#define ISPHIST_REG_END_SHIFT 0
1235#define ISPHIST_REG_START_MASK (ISPHIST_REG_START_END_MASK << \
1236 ISPHIST_REG_START_SHIFT)
1237#define ISPHIST_REG_END_MASK (ISPHIST_REG_START_END_MASK << \
1238 ISPHIST_REG_END_SHIFT)
1239
1240#define ISPHIST_REG_MASK (ISPHIST_REG_START_MASK | \
1241 ISPHIST_REG_END_MASK)
1242
1243#define ISPHIST_ADDR_SHIFT 0
1244#define ISPHIST_ADDR_MASK 0x3FF
1245
1246#define ISPHIST_DATA_SHIFT 0
1247#define ISPHIST_DATA_MASK 0xFFFFF
1248
1249#define ISPHIST_RADD_SHIFT 0
1250#define ISPHIST_RADD_MASK 0xFFFFFFFF
1251
1252#define ISPHIST_RADD_OFF_SHIFT 0
1253#define ISPHIST_RADD_OFF_MASK 0xFFFF
1254
1255#define ISPHIST_HV_INFO_HSIZE_SHIFT 16
1256#define ISPHIST_HV_INFO_HSIZE_MASK 0x3FFF0000
1257#define ISPHIST_HV_INFO_VSIZE_SHIFT 0
1258#define ISPHIST_HV_INFO_VSIZE_MASK 0x3FFF
1259
1260#define ISPHIST_HV_INFO_MASK 0x3FFF3FFF
1261
1262#define ISPCCDC_LSC_ENABLE 1
1263#define ISPCCDC_LSC_BUSY (1 << 7)
1264#define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700
1265#define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8
1266#define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800
1267#define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12
1268#define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE
1269#define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1
1270#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK (1<<6)
1271
1272#define ISPCCDC_LSC_INITIAL_X_MASK 0x3F
1273#define ISPCCDC_LSC_INITIAL_X_SHIFT 0
1274#define ISPCCDC_LSC_INITIAL_Y_MASK 0x3F0000
1275#define ISPCCDC_LSC_INITIAL_Y_SHIFT 16
1276
1277/* -----------------------------------------------------------------------------
1278 * CSI2 receiver registers (ES2.0)
1279 */
1280
1281#define ISPCSI2_REVISION (0x000)
1282#define ISPCSI2_SYSCONFIG (0x010)
1283#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
1284#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK \
1285 (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1286#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE \
1287 (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1288#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO \
1289 (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1290#define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \
1291 (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1292#define ISPCSI2_SYSCONFIG_SOFT_RESET (1 << 1)
1293#define ISPCSI2_SYSCONFIG_AUTO_IDLE (1 << 0)
1294
1295#define ISPCSI2_SYSSTATUS (0x014)
1296#define ISPCSI2_SYSSTATUS_RESET_DONE (1 << 0)
1297
1298#define ISPCSI2_IRQSTATUS (0x018)
1299#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ (1 << 14)
1300#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ (1 << 13)
1301#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 12)
1302#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11)
1303#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ (1 << 10)
1304#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ (1 << 9)
1305#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ (1 << 8)
1306#define ISPCSI2_IRQSTATUS_CONTEXT(n) (1 << (n))
1307
1308#define ISPCSI2_IRQENABLE (0x01c)
1309#define ISPCSI2_CTRL (0x040)
1310#define ISPCSI2_CTRL_VP_CLK_EN (1 << 15)
1311#define ISPCSI2_CTRL_VP_ONLY_EN (1 << 11)
1312#define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8
1313#define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \
1314 (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
1315#define ISPCSI2_CTRL_DBG_EN (1 << 7)
1316#define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5
1317#define ISPCSI2_CTRL_BURST_SIZE_MASK \
1318 (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT)
1319#define ISPCSI2_CTRL_FRAME (1 << 3)
1320#define ISPCSI2_CTRL_ECC_EN (1 << 2)
1321#define ISPCSI2_CTRL_SECURE (1 << 1)
1322#define ISPCSI2_CTRL_IF_EN (1 << 0)
1323
1324#define ISPCSI2_DBG_H (0x044)
1325#define ISPCSI2_GNQ (0x048)
1326#define ISPCSI2_PHY_CFG (0x050)
1327#define ISPCSI2_PHY_CFG_RESET_CTRL (1 << 30)
1328#define ISPCSI2_PHY_CFG_RESET_DONE (1 << 29)
1329#define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27
1330#define ISPCSI2_PHY_CFG_PWR_CMD_MASK \
1331 (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1332#define ISPCSI2_PHY_CFG_PWR_CMD_OFF \
1333 (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1334#define ISPCSI2_PHY_CFG_PWR_CMD_ON \
1335 (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1336#define ISPCSI2_PHY_CFG_PWR_CMD_ULPW \
1337 (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1338#define ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT 25
1339#define ISPCSI2_PHY_CFG_PWR_STATUS_MASK \
1340 (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1341#define ISPCSI2_PHY_CFG_PWR_STATUS_OFF \
1342 (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1343#define ISPCSI2_PHY_CFG_PWR_STATUS_ON \
1344 (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1345#define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \
1346 (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1347#define ISPCSI2_PHY_CFG_PWR_AUTO (1 << 24)
1348
1349#define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4))
1350#define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \
1351 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1352#define ISPCSI2_PHY_CFG_DATA_POL_PN(n) \
1353 (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1354#define ISPCSI2_PHY_CFG_DATA_POL_NP(n) \
1355 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1356
1357#define ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n) ((n) * 4)
1358#define ISPCSI2_PHY_CFG_DATA_POSITION_MASK(n) \
1359 (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1360#define ISPCSI2_PHY_CFG_DATA_POSITION_NC(n) \
1361 (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1362#define ISPCSI2_PHY_CFG_DATA_POSITION_1(n) \
1363 (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1364#define ISPCSI2_PHY_CFG_DATA_POSITION_2(n) \
1365 (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1366#define ISPCSI2_PHY_CFG_DATA_POSITION_3(n) \
1367 (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1368#define ISPCSI2_PHY_CFG_DATA_POSITION_4(n) \
1369 (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1370#define ISPCSI2_PHY_CFG_DATA_POSITION_5(n) \
1371 (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1372
1373#define ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT 3
1374#define ISPCSI2_PHY_CFG_CLOCK_POL_MASK \
1375 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1376#define ISPCSI2_PHY_CFG_CLOCK_POL_PN \
1377 (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1378#define ISPCSI2_PHY_CFG_CLOCK_POL_NP \
1379 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1380
1381#define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT 0
1382#define ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK \
1383 (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1384#define ISPCSI2_PHY_CFG_CLOCK_POSITION_1 \
1385 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1386#define ISPCSI2_PHY_CFG_CLOCK_POSITION_2 \
1387 (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1388#define ISPCSI2_PHY_CFG_CLOCK_POSITION_3 \
1389 (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1390#define ISPCSI2_PHY_CFG_CLOCK_POSITION_4 \
1391 (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1392#define ISPCSI2_PHY_CFG_CLOCK_POSITION_5 \
1393 (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1394
1395#define ISPCSI2_PHY_IRQSTATUS (0x054)
1396#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT (1 << 26)
1397#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25)
1398#define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 (1 << 24)
1399#define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 (1 << 23)
1400#define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 (1 << 22)
1401#define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 (1 << 21)
1402#define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 (1 << 20)
1403#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 (1 << 19)
1404#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 (1 << 18)
1405#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 (1 << 17)
1406#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 (1 << 16)
1407#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 (1 << 15)
1408#define ISPCSI2_PHY_IRQSTATUS_ERRESC5 (1 << 14)
1409#define ISPCSI2_PHY_IRQSTATUS_ERRESC4 (1 << 13)
1410#define ISPCSI2_PHY_IRQSTATUS_ERRESC3 (1 << 12)
1411#define ISPCSI2_PHY_IRQSTATUS_ERRESC2 (1 << 11)
1412#define ISPCSI2_PHY_IRQSTATUS_ERRESC1 (1 << 10)
1413#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 (1 << 9)
1414#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 (1 << 8)
1415#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 (1 << 7)
1416#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 (1 << 6)
1417#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 (1 << 5)
1418#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 (1 << 4)
1419#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 (1 << 3)
1420#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 (1 << 2)
1421#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 (1 << 1)
1422#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 1
1423
1424#define ISPCSI2_SHORT_PACKET (0x05c)
1425#define ISPCSI2_PHY_IRQENABLE (0x060)
1426#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT (1 << 26)
1427#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25)
1428#define ISPCSI2_PHY_IRQENABLE_STATEULPM5 (1 << 24)
1429#define ISPCSI2_PHY_IRQENABLE_STATEULPM4 (1 << 23)
1430#define ISPCSI2_PHY_IRQENABLE_STATEULPM3 (1 << 22)
1431#define ISPCSI2_PHY_IRQENABLE_STATEULPM2 (1 << 21)
1432#define ISPCSI2_PHY_IRQENABLE_STATEULPM1 (1 << 20)
1433#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 (1 << 19)
1434#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 (1 << 18)
1435#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 (1 << 17)
1436#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 (1 << 16)
1437#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 (1 << 15)
1438#define ISPCSI2_PHY_IRQENABLE_ERRESC5 (1 << 14)
1439#define ISPCSI2_PHY_IRQENABLE_ERRESC4 (1 << 13)
1440#define ISPCSI2_PHY_IRQENABLE_ERRESC3 (1 << 12)
1441#define ISPCSI2_PHY_IRQENABLE_ERRESC2 (1 << 11)
1442#define ISPCSI2_PHY_IRQENABLE_ERRESC1 (1 << 10)
1443#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 (1 << 9)
1444#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 (1 << 8)
1445#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 (1 << 7)
1446#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 (1 << 6)
1447#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 (1 << 5)
1448#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 (1 << 4)
1449#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 (1 << 3)
1450#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 (1 << 2)
1451#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 (1 << 1)
1452#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 (1 << 0)
1453
1454#define ISPCSI2_DBG_P (0x068)
1455#define ISPCSI2_TIMING (0x06c)
1456#define ISPCSI2_TIMING_FORCE_RX_MODE_IO(n) (1 << ((16 * ((n) - 1)) + 15))
1457#define ISPCSI2_TIMING_STOP_STATE_X16_IO(n) (1 << ((16 * ((n) - 1)) + 14))
1458#define ISPCSI2_TIMING_STOP_STATE_X4_IO(n) (1 << ((16 * ((n) - 1)) + 13))
1459#define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n) (16 * ((n) - 1))
1460#define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n) \
1461 (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
1462
1463#define ISPCSI2_CTX_CTRL1(n) ((0x070) + 0x20 * (n))
1464#define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8
1465#define ISPCSI2_CTX_CTRL1_COUNT_MASK \
1466 (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
1467#define ISPCSI2_CTX_CTRL1_EOF_EN (1 << 7)
1468#define ISPCSI2_CTX_CTRL1_EOL_EN (1 << 6)
1469#define ISPCSI2_CTX_CTRL1_CS_EN (1 << 5)
1470#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK (1 << 4)
1471#define ISPCSI2_CTX_CTRL1_PING_PONG (1 << 3)
1472#define ISPCSI2_CTX_CTRL1_CTX_EN (1 << 0)
1473
1474#define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n))
1475#define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13
1476#define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK \
1477 (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
1478#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11
1479#define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \
1480 (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
1481#define ISPCSI2_CTX_CTRL2_DPCM_PRED (1 << 10)
1482#define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0
1483#define ISPCSI2_CTX_CTRL2_FORMAT_MASK \
1484 (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
1485#define ISPCSI2_CTX_CTRL2_FRAME_SHIFT 16
1486#define ISPCSI2_CTX_CTRL2_FRAME_MASK \
1487 (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT)
1488
1489#define ISPCSI2_CTX_DAT_OFST(n) ((0x078) + 0x20 * (n))
1490#define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT 0
1491#define ISPCSI2_CTX_DAT_OFST_OFST_MASK \
1492 (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
1493
1494#define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n))
1495#define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n))
1496#define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n))
1497#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ (1 << 8)
1498#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ (1 << 7)
1499#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ (1 << 6)
1500#define ISPCSI2_CTX_IRQENABLE_CS_IRQ (1 << 5)
1501#define ISPCSI2_CTX_IRQENABLE_LE_IRQ (1 << 3)
1502#define ISPCSI2_CTX_IRQENABLE_LS_IRQ (1 << 2)
1503#define ISPCSI2_CTX_IRQENABLE_FE_IRQ (1 << 1)
1504#define ISPCSI2_CTX_IRQENABLE_FS_IRQ (1 << 0)
1505
1506#define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n))
1507#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 8)
1508#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ (1 << 7)
1509#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ (1 << 6)
1510#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ (1 << 5)
1511#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ (1 << 3)
1512#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ (1 << 2)
1513#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ (1 << 1)
1514#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ (1 << 0)
1515
1516#define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n))
1517#define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5
1518#define ISPCSI2_CTX_CTRL3_ALPHA_MASK \
1519 (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
1520
1521/* This instance is for OMAP3630 only */
1522#define ISPCSI2_CTX_TRANSCODEH(n) (0x000 + 0x8 * (n))
1523#define ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT 16
1524#define ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK \
1525 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1526#define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT 0
1527#define ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK \
1528 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1529#define ISPCSI2_CTX_TRANSCODEV(n) (0x004 + 0x8 * (n))
1530#define ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT 16
1531#define ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK \
1532 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1533#define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT 0
1534#define ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK \
1535 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1536
1537/* -----------------------------------------------------------------------------
1538 * CSI PHY registers
1539 */
1540
1541#define ISPCSIPHY_REG0 (0x000)
1542#define ISPCSIPHY_REG0_THS_TERM_SHIFT 8
1543#define ISPCSIPHY_REG0_THS_TERM_MASK \
1544 (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT)
1545#define ISPCSIPHY_REG0_THS_SETTLE_SHIFT 0
1546#define ISPCSIPHY_REG0_THS_SETTLE_MASK \
1547 (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
1548
1549#define ISPCSIPHY_REG1 (0x004)
1550#define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK (1 << 29)
1551/* This field is for OMAP3630 only */
1552#define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS (1 << 25)
1553#define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18
1554#define ISPCSIPHY_REG1_TCLK_TERM_MASK \
1555 (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
1556#define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_SHIFT 10
1557#define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK \
1558 (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN)
1559/* This field is for OMAP3430 only */
1560#define ISPCSIPHY_REG1_TCLK_MISS_SHIFT 8
1561#define ISPCSIPHY_REG1_TCLK_MISS_MASK \
1562 (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT)
1563/* This field is for OMAP3630 only */
1564#define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT 8
1565#define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK \
1566 (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT)
1567#define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT 0
1568#define ISPCSIPHY_REG1_TCLK_SETTLE_MASK \
1569 (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT)
1570
1571/* This register is for OMAP3630 only */
1572#define ISPCSIPHY_REG2 (0x008)
1573#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT 30
1574#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK \
1575 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT)
1576#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT 28
1577#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK \
1578 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT)
1579#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT 26
1580#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK \
1581 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT)
1582#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT 24
1583#define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK \
1584 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT)
1585#define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT 0
1586#define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK \
1587 (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT)
1588
1589#endif /* OMAP3_ISP_REG_H */
diff --git a/include/linux/omap3isp.h b/include/linux/omap3isp.h
new file mode 100644
index 000000000000..150822b4dbff
--- /dev/null
+++ b/include/linux/omap3isp.h
@@ -0,0 +1,646 @@
1/*
2 * omap3isp.h
3 *
4 * TI OMAP3 ISP - User-space API
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27#ifndef OMAP3_ISP_USER_H
28#define OMAP3_ISP_USER_H
29
30#include <linux/types.h>
31
32/*
33 * Private IOCTLs
34 *
35 * VIDIOC_OMAP3ISP_CCDC_CFG: Set CCDC configuration
36 * VIDIOC_OMAP3ISP_PRV_CFG: Set preview engine configuration
37 * VIDIOC_OMAP3ISP_AEWB_CFG: Set AEWB module configuration
38 * VIDIOC_OMAP3ISP_HIST_CFG: Set histogram module configuration
39 * VIDIOC_OMAP3ISP_AF_CFG: Set auto-focus module configuration
40 * VIDIOC_OMAP3ISP_STAT_REQ: Read statistics (AEWB/AF/histogram) data
41 * VIDIOC_OMAP3ISP_STAT_EN: Enable/disable a statistics module
42 */
43
44#define VIDIOC_OMAP3ISP_CCDC_CFG \
45 _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct omap3isp_ccdc_update_config)
46#define VIDIOC_OMAP3ISP_PRV_CFG \
47 _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct omap3isp_prev_update_config)
48#define VIDIOC_OMAP3ISP_AEWB_CFG \
49 _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct omap3isp_h3a_aewb_config)
50#define VIDIOC_OMAP3ISP_HIST_CFG \
51 _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct omap3isp_hist_config)
52#define VIDIOC_OMAP3ISP_AF_CFG \
53 _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct omap3isp_h3a_af_config)
54#define VIDIOC_OMAP3ISP_STAT_REQ \
55 _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct omap3isp_stat_data)
56#define VIDIOC_OMAP3ISP_STAT_EN \
57 _IOWR('V', BASE_VIDIOC_PRIVATE + 7, unsigned long)
58
59/*
60 * Events
61 *
62 * V4L2_EVENT_OMAP3ISP_AEWB: AEWB statistics data ready
63 * V4L2_EVENT_OMAP3ISP_AF: AF statistics data ready
64 * V4L2_EVENT_OMAP3ISP_HIST: Histogram statistics data ready
65 * V4L2_EVENT_OMAP3ISP_HS_VS: Horizontal/vertical synchronization detected
66 */
67
68#define V4L2_EVENT_OMAP3ISP_CLASS (V4L2_EVENT_PRIVATE_START | 0x100)
69#define V4L2_EVENT_OMAP3ISP_AEWB (V4L2_EVENT_OMAP3ISP_CLASS | 0x1)
70#define V4L2_EVENT_OMAP3ISP_AF (V4L2_EVENT_OMAP3ISP_CLASS | 0x2)
71#define V4L2_EVENT_OMAP3ISP_HIST (V4L2_EVENT_OMAP3ISP_CLASS | 0x3)
72#define V4L2_EVENT_OMAP3ISP_HS_VS (V4L2_EVENT_OMAP3ISP_CLASS | 0x4)
73
74struct omap3isp_stat_event_status {
75 __u32 frame_number;
76 __u16 config_counter;
77 __u8 buf_err;
78};
79
80/* AE/AWB related structures and flags*/
81
82/* H3A Range Constants */
83#define OMAP3ISP_AEWB_MAX_SATURATION_LIM 1023
84#define OMAP3ISP_AEWB_MIN_WIN_H 2
85#define OMAP3ISP_AEWB_MAX_WIN_H 256
86#define OMAP3ISP_AEWB_MIN_WIN_W 6
87#define OMAP3ISP_AEWB_MAX_WIN_W 256
88#define OMAP3ISP_AEWB_MIN_WINVC 1
89#define OMAP3ISP_AEWB_MIN_WINHC 1
90#define OMAP3ISP_AEWB_MAX_WINVC 128
91#define OMAP3ISP_AEWB_MAX_WINHC 36
92#define OMAP3ISP_AEWB_MAX_WINSTART 4095
93#define OMAP3ISP_AEWB_MIN_SUB_INC 2
94#define OMAP3ISP_AEWB_MAX_SUB_INC 32
95#define OMAP3ISP_AEWB_MAX_BUF_SIZE 83600
96
97#define OMAP3ISP_AF_IIRSH_MIN 0
98#define OMAP3ISP_AF_IIRSH_MAX 4095
99#define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MIN 1
100#define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MAX 36
101#define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MIN 1
102#define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MAX 128
103#define OMAP3ISP_AF_PAXEL_INCREMENT_MIN 2
104#define OMAP3ISP_AF_PAXEL_INCREMENT_MAX 32
105#define OMAP3ISP_AF_PAXEL_HEIGHT_MIN 2
106#define OMAP3ISP_AF_PAXEL_HEIGHT_MAX 256
107#define OMAP3ISP_AF_PAXEL_WIDTH_MIN 16
108#define OMAP3ISP_AF_PAXEL_WIDTH_MAX 256
109#define OMAP3ISP_AF_PAXEL_HZSTART_MIN 1
110#define OMAP3ISP_AF_PAXEL_HZSTART_MAX 4095
111#define OMAP3ISP_AF_PAXEL_VTSTART_MIN 0
112#define OMAP3ISP_AF_PAXEL_VTSTART_MAX 4095
113#define OMAP3ISP_AF_THRESHOLD_MAX 255
114#define OMAP3ISP_AF_COEF_MAX 4095
115#define OMAP3ISP_AF_PAXEL_SIZE 48
116#define OMAP3ISP_AF_MAX_BUF_SIZE 221184
117
118/**
119 * struct omap3isp_h3a_aewb_config - AE AWB configuration reset values
120 * saturation_limit: Saturation limit.
121 * @win_height: Window Height. Range 2 - 256, even values only.
122 * @win_width: Window Width. Range 6 - 256, even values only.
123 * @ver_win_count: Vertical Window Count. Range 1 - 128.
124 * @hor_win_count: Horizontal Window Count. Range 1 - 36.
125 * @ver_win_start: Vertical Window Start. Range 0 - 4095.
126 * @hor_win_start: Horizontal Window Start. Range 0 - 4095.
127 * @blk_ver_win_start: Black Vertical Windows Start. Range 0 - 4095.
128 * @blk_win_height: Black Window Height. Range 2 - 256, even values only.
129 * @subsample_ver_inc: Subsample Vertical points increment Range 2 - 32, even
130 * values only.
131 * @subsample_hor_inc: Subsample Horizontal points increment Range 2 - 32, even
132 * values only.
133 * @alaw_enable: AEW ALAW EN flag.
134 */
135struct omap3isp_h3a_aewb_config {
136 /*
137 * Common fields.
138 * They should be the first ones and must be in the same order as in
139 * ispstat_generic_config struct.
140 */
141 __u32 buf_size;
142 __u16 config_counter;
143
144 /* Private fields */
145 __u16 saturation_limit;
146 __u16 win_height;
147 __u16 win_width;
148 __u16 ver_win_count;
149 __u16 hor_win_count;
150 __u16 ver_win_start;
151 __u16 hor_win_start;
152 __u16 blk_ver_win_start;
153 __u16 blk_win_height;
154 __u16 subsample_ver_inc;
155 __u16 subsample_hor_inc;
156 __u8 alaw_enable;
157};
158
159/**
160 * struct omap3isp_stat_data - Statistic data sent to or received from user
161 * @ts: Timestamp of returned framestats.
162 * @buf: Pointer to pass to user.
163 * @frame_number: Frame number of requested stats.
164 * @cur_frame: Current frame number being processed.
165 * @config_counter: Number of the configuration associated with the data.
166 */
167struct omap3isp_stat_data {
168 struct timeval ts;
169 void __user *buf;
170 __u32 buf_size;
171 __u16 frame_number;
172 __u16 cur_frame;
173 __u16 config_counter;
174};
175
176
177/* Histogram related structs */
178
179/* Flags for number of bins */
180#define OMAP3ISP_HIST_BINS_32 0
181#define OMAP3ISP_HIST_BINS_64 1
182#define OMAP3ISP_HIST_BINS_128 2
183#define OMAP3ISP_HIST_BINS_256 3
184
185/* Number of bins * 4 colors * 4-bytes word */
186#define OMAP3ISP_HIST_MEM_SIZE_BINS(n) ((1 << ((n)+5))*4*4)
187
188#define OMAP3ISP_HIST_MEM_SIZE 1024
189#define OMAP3ISP_HIST_MIN_REGIONS 1
190#define OMAP3ISP_HIST_MAX_REGIONS 4
191#define OMAP3ISP_HIST_MAX_WB_GAIN 255
192#define OMAP3ISP_HIST_MIN_WB_GAIN 0
193#define OMAP3ISP_HIST_MAX_BIT_WIDTH 14
194#define OMAP3ISP_HIST_MIN_BIT_WIDTH 8
195#define OMAP3ISP_HIST_MAX_WG 4
196#define OMAP3ISP_HIST_MAX_BUF_SIZE 4096
197
198/* Source */
199#define OMAP3ISP_HIST_SOURCE_CCDC 0
200#define OMAP3ISP_HIST_SOURCE_MEM 1
201
202/* CFA pattern */
203#define OMAP3ISP_HIST_CFA_BAYER 0
204#define OMAP3ISP_HIST_CFA_FOVEONX3 1
205
206struct omap3isp_hist_region {
207 __u16 h_start;
208 __u16 h_end;
209 __u16 v_start;
210 __u16 v_end;
211};
212
213struct omap3isp_hist_config {
214 /*
215 * Common fields.
216 * They should be the first ones and must be in the same order as in
217 * ispstat_generic_config struct.
218 */
219 __u32 buf_size;
220 __u16 config_counter;
221
222 __u8 num_acc_frames; /* Num of image frames to be processed and
223 accumulated for each histogram frame */
224 __u16 hist_bins; /* number of bins: 32, 64, 128, or 256 */
225 __u8 cfa; /* BAYER or FOVEON X3 */
226 __u8 wg[OMAP3ISP_HIST_MAX_WG]; /* White Balance Gain */
227 __u8 num_regions; /* number of regions to be configured */
228 struct omap3isp_hist_region region[OMAP3ISP_HIST_MAX_REGIONS];
229};
230
231/* Auto Focus related structs */
232
233#define OMAP3ISP_AF_NUM_COEF 11
234
235enum omap3isp_h3a_af_fvmode {
236 OMAP3ISP_AF_MODE_SUMMED = 0,
237 OMAP3ISP_AF_MODE_PEAK = 1
238};
239
240/* Red, Green, and blue pixel location in the AF windows */
241enum omap3isp_h3a_af_rgbpos {
242 OMAP3ISP_AF_GR_GB_BAYER = 0, /* GR and GB as Bayer pattern */
243 OMAP3ISP_AF_RG_GB_BAYER = 1, /* RG and GB as Bayer pattern */
244 OMAP3ISP_AF_GR_BG_BAYER = 2, /* GR and BG as Bayer pattern */
245 OMAP3ISP_AF_RG_BG_BAYER = 3, /* RG and BG as Bayer pattern */
246 OMAP3ISP_AF_GG_RB_CUSTOM = 4, /* GG and RB as custom pattern */
247 OMAP3ISP_AF_RB_GG_CUSTOM = 5 /* RB and GG as custom pattern */
248};
249
250/* Contains the information regarding the Horizontal Median Filter */
251struct omap3isp_h3a_af_hmf {
252 __u8 enable; /* Status of Horizontal Median Filter */
253 __u8 threshold; /* Threshhold Value for Horizontal Median Filter */
254};
255
256/* Contains the information regarding the IIR Filters */
257struct omap3isp_h3a_af_iir {
258 __u16 h_start; /* IIR horizontal start */
259 __u16 coeff_set0[OMAP3ISP_AF_NUM_COEF]; /* Filter coefficient, set 0 */
260 __u16 coeff_set1[OMAP3ISP_AF_NUM_COEF]; /* Filter coefficient, set 1 */
261};
262
263/* Contains the information regarding the Paxels Structure in AF Engine */
264struct omap3isp_h3a_af_paxel {
265 __u16 h_start; /* Horizontal Start Position */
266 __u16 v_start; /* Vertical Start Position */
267 __u8 width; /* Width of the Paxel */
268 __u8 height; /* Height of the Paxel */
269 __u8 h_cnt; /* Horizontal Count */
270 __u8 v_cnt; /* vertical Count */
271 __u8 line_inc; /* Line Increment */
272};
273
274/* Contains the parameters required for hardware set up of AF Engine */
275struct omap3isp_h3a_af_config {
276 /*
277 * Common fields.
278 * They should be the first ones and must be in the same order as in
279 * ispstat_generic_config struct.
280 */
281 __u32 buf_size;
282 __u16 config_counter;
283
284 struct omap3isp_h3a_af_hmf hmf; /* HMF configurations */
285 struct omap3isp_h3a_af_iir iir; /* IIR filter configurations */
286 struct omap3isp_h3a_af_paxel paxel; /* Paxel parameters */
287 enum omap3isp_h3a_af_rgbpos rgb_pos; /* RGB Positions */
288 enum omap3isp_h3a_af_fvmode fvmode; /* Accumulator mode */
289 __u8 alaw_enable; /* AF ALAW status */
290};
291
292/* ISP CCDC structs */
293
294/* Abstraction layer CCDC configurations */
295#define OMAP3ISP_CCDC_ALAW (1 << 0)
296#define OMAP3ISP_CCDC_LPF (1 << 1)
297#define OMAP3ISP_CCDC_BLCLAMP (1 << 2)
298#define OMAP3ISP_CCDC_BCOMP (1 << 3)
299#define OMAP3ISP_CCDC_FPC (1 << 4)
300#define OMAP3ISP_CCDC_CULL (1 << 5)
301#define OMAP3ISP_CCDC_CONFIG_LSC (1 << 7)
302#define OMAP3ISP_CCDC_TBL_LSC (1 << 8)
303
304#define OMAP3ISP_RGB_MAX 3
305
306/* Enumeration constants for Alaw input width */
307enum omap3isp_alaw_ipwidth {
308 OMAP3ISP_ALAW_BIT12_3 = 0x3,
309 OMAP3ISP_ALAW_BIT11_2 = 0x4,
310 OMAP3ISP_ALAW_BIT10_1 = 0x5,
311 OMAP3ISP_ALAW_BIT9_0 = 0x6
312};
313
314/**
315 * struct omap3isp_ccdc_lsc_config - LSC configuration
316 * @offset: Table Offset of the gain table.
317 * @gain_mode_n: Vertical dimension of a paxel in LSC configuration.
318 * @gain_mode_m: Horizontal dimension of a paxel in LSC configuration.
319 * @gain_format: Gain table format.
320 * @fmtsph: Start pixel horizontal from start of the HS sync pulse.
321 * @fmtlnh: Number of pixels in horizontal direction to use for the data
322 * reformatter.
323 * @fmtslv: Start line from start of VS sync pulse for the data reformatter.
324 * @fmtlnv: Number of lines in vertical direction for the data reformatter.
325 * @initial_x: X position, in pixels, of the first active pixel in reference
326 * to the first active paxel. Must be an even number.
327 * @initial_y: Y position, in pixels, of the first active pixel in reference
328 * to the first active paxel. Must be an even number.
329 * @size: Size of LSC gain table. Filled when loaded from userspace.
330 */
331struct omap3isp_ccdc_lsc_config {
332 __u16 offset;
333 __u8 gain_mode_n;
334 __u8 gain_mode_m;
335 __u8 gain_format;
336 __u16 fmtsph;
337 __u16 fmtlnh;
338 __u16 fmtslv;
339 __u16 fmtlnv;
340 __u8 initial_x;
341 __u8 initial_y;
342 __u32 size;
343};
344
345/**
346 * struct omap3isp_ccdc_bclamp - Optical & Digital black clamp subtract
347 * @obgain: Optical black average gain.
348 * @obstpixel: Start Pixel w.r.t. HS pulse in Optical black sample.
349 * @oblines: Optical Black Sample lines.
350 * @oblen: Optical Black Sample Length.
351 * @dcsubval: Digital Black Clamp subtract value.
352 */
353struct omap3isp_ccdc_bclamp {
354 __u8 obgain;
355 __u8 obstpixel;
356 __u8 oblines;
357 __u8 oblen;
358 __u16 dcsubval;
359};
360
361/**
362 * struct omap3isp_ccdc_fpc - Faulty Pixels Correction
363 * @fpnum: Number of faulty pixels to be corrected in the frame.
364 * @fpcaddr: Memory address of the FPC Table
365 */
366struct omap3isp_ccdc_fpc {
367 __u16 fpnum;
368 __u32 fpcaddr;
369};
370
371/**
372 * struct omap3isp_ccdc_blcomp - Black Level Compensation parameters
373 * @b_mg: B/Mg pixels. 2's complement. -128 to +127.
374 * @gb_g: Gb/G pixels. 2's complement. -128 to +127.
375 * @gr_cy: Gr/Cy pixels. 2's complement. -128 to +127.
376 * @r_ye: R/Ye pixels. 2's complement. -128 to +127.
377 */
378struct omap3isp_ccdc_blcomp {
379 __u8 b_mg;
380 __u8 gb_g;
381 __u8 gr_cy;
382 __u8 r_ye;
383};
384
385/**
386 * omap3isp_ccdc_culling - Culling parameters
387 * @v_pattern: Vertical culling pattern.
388 * @h_odd: Horizontal Culling pattern for odd lines.
389 * @h_even: Horizontal Culling pattern for even lines.
390 */
391struct omap3isp_ccdc_culling {
392 __u8 v_pattern;
393 __u16 h_odd;
394 __u16 h_even;
395};
396
397/**
398 * omap3isp_ccdc_update_config - CCDC configuration
399 * @update: Specifies which CCDC registers should be updated.
400 * @flag: Specifies which CCDC functions should be enabled.
401 * @alawip: Enable/Disable A-Law compression.
402 * @bclamp: Black clamp control register.
403 * @blcomp: Black level compensation value for RGrGbB Pixels. 2's complement.
404 * @fpc: Number of faulty pixels corrected in the frame, address of FPC table.
405 * @cull: Cull control register.
406 * @lsc: Pointer to LSC gain table.
407 */
408struct omap3isp_ccdc_update_config {
409 __u16 update;
410 __u16 flag;
411 enum omap3isp_alaw_ipwidth alawip;
412 struct omap3isp_ccdc_bclamp __user *bclamp;
413 struct omap3isp_ccdc_blcomp __user *blcomp;
414 struct omap3isp_ccdc_fpc __user *fpc;
415 struct omap3isp_ccdc_lsc_config __user *lsc_cfg;
416 struct omap3isp_ccdc_culling __user *cull;
417 __u8 __user *lsc;
418};
419
420/* Preview configurations */
421#define OMAP3ISP_PREV_LUMAENH (1 << 0)
422#define OMAP3ISP_PREV_INVALAW (1 << 1)
423#define OMAP3ISP_PREV_HRZ_MED (1 << 2)
424#define OMAP3ISP_PREV_CFA (1 << 3)
425#define OMAP3ISP_PREV_CHROMA_SUPP (1 << 4)
426#define OMAP3ISP_PREV_WB (1 << 5)
427#define OMAP3ISP_PREV_BLKADJ (1 << 6)
428#define OMAP3ISP_PREV_RGB2RGB (1 << 7)
429#define OMAP3ISP_PREV_COLOR_CONV (1 << 8)
430#define OMAP3ISP_PREV_YC_LIMIT (1 << 9)
431#define OMAP3ISP_PREV_DEFECT_COR (1 << 10)
432#define OMAP3ISP_PREV_GAMMABYPASS (1 << 11)
433#define OMAP3ISP_PREV_DRK_FRM_CAPTURE (1 << 12)
434#define OMAP3ISP_PREV_DRK_FRM_SUBTRACT (1 << 13)
435#define OMAP3ISP_PREV_LENS_SHADING (1 << 14)
436#define OMAP3ISP_PREV_NF (1 << 15)
437#define OMAP3ISP_PREV_GAMMA (1 << 16)
438
439#define OMAP3ISP_PREV_NF_TBL_SIZE 64
440#define OMAP3ISP_PREV_CFA_TBL_SIZE 576
441#define OMAP3ISP_PREV_GAMMA_TBL_SIZE 1024
442#define OMAP3ISP_PREV_YENH_TBL_SIZE 128
443
444#define OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS 4
445
446/**
447 * struct omap3isp_prev_hmed - Horizontal Median Filter
448 * @odddist: Distance between consecutive pixels of same color in the odd line.
449 * @evendist: Distance between consecutive pixels of same color in the even
450 * line.
451 * @thres: Horizontal median filter threshold.
452 */
453struct omap3isp_prev_hmed {
454 __u8 odddist;
455 __u8 evendist;
456 __u8 thres;
457};
458
459/*
460 * Enumeration for CFA Formats supported by preview
461 */
462enum omap3isp_cfa_fmt {
463 OMAP3ISP_CFAFMT_BAYER,
464 OMAP3ISP_CFAFMT_SONYVGA,
465 OMAP3ISP_CFAFMT_RGBFOVEON,
466 OMAP3ISP_CFAFMT_DNSPL,
467 OMAP3ISP_CFAFMT_HONEYCOMB,
468 OMAP3ISP_CFAFMT_RRGGBBFOVEON
469};
470
471/**
472 * struct omap3isp_prev_cfa - CFA Interpolation
473 * @format: CFA Format Enum value supported by preview.
474 * @gradthrs_vert: CFA Gradient Threshold - Vertical.
475 * @gradthrs_horz: CFA Gradient Threshold - Horizontal.
476 * @table: Pointer to the CFA table.
477 */
478struct omap3isp_prev_cfa {
479 enum omap3isp_cfa_fmt format;
480 __u8 gradthrs_vert;
481 __u8 gradthrs_horz;
482 __u32 table[OMAP3ISP_PREV_CFA_TBL_SIZE];
483};
484
485/**
486 * struct omap3isp_prev_csup - Chrominance Suppression
487 * @gain: Gain.
488 * @thres: Threshold.
489 * @hypf_en: Flag to enable/disable the High Pass Filter.
490 */
491struct omap3isp_prev_csup {
492 __u8 gain;
493 __u8 thres;
494 __u8 hypf_en;
495};
496
497/**
498 * struct omap3isp_prev_wbal - White Balance
499 * @dgain: Digital gain (U10Q8).
500 * @coef3: White balance gain - COEF 3 (U8Q5).
501 * @coef2: White balance gain - COEF 2 (U8Q5).
502 * @coef1: White balance gain - COEF 1 (U8Q5).
503 * @coef0: White balance gain - COEF 0 (U8Q5).
504 */
505struct omap3isp_prev_wbal {
506 __u16 dgain;
507 __u8 coef3;
508 __u8 coef2;
509 __u8 coef1;
510 __u8 coef0;
511};
512
513/**
514 * struct omap3isp_prev_blkadj - Black Level Adjustment
515 * @red: Black level offset adjustment for Red in 2's complement format
516 * @green: Black level offset adjustment for Green in 2's complement format
517 * @blue: Black level offset adjustment for Blue in 2's complement format
518 */
519struct omap3isp_prev_blkadj {
520 /*Black level offset adjustment for Red in 2's complement format */
521 __u8 red;
522 /*Black level offset adjustment for Green in 2's complement format */
523 __u8 green;
524 /* Black level offset adjustment for Blue in 2's complement format */
525 __u8 blue;
526};
527
528/**
529 * struct omap3isp_prev_rgbtorgb - RGB to RGB Blending
530 * @matrix: Blending values(S12Q8 format)
531 * [RR] [GR] [BR]
532 * [RG] [GG] [BG]
533 * [RB] [GB] [BB]
534 * @offset: Blending offset value for R,G,B in 2's complement integer format.
535 */
536struct omap3isp_prev_rgbtorgb {
537 __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX];
538 __u16 offset[OMAP3ISP_RGB_MAX];
539};
540
541/**
542 * struct omap3isp_prev_csc - Color Space Conversion from RGB-YCbYCr
543 * @matrix: Color space conversion coefficients(S10Q8)
544 * [CSCRY] [CSCGY] [CSCBY]
545 * [CSCRCB] [CSCGCB] [CSCBCB]
546 * [CSCRCR] [CSCGCR] [CSCBCR]
547 * @offset: CSC offset values for Y offset, CB offset and CR offset respectively
548 */
549struct omap3isp_prev_csc {
550 __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX];
551 __s16 offset[OMAP3ISP_RGB_MAX];
552};
553
554/**
555 * struct omap3isp_prev_yclimit - Y, C Value Limit
556 * @minC: Minimum C value
557 * @maxC: Maximum C value
558 * @minY: Minimum Y value
559 * @maxY: Maximum Y value
560 */
561struct omap3isp_prev_yclimit {
562 __u8 minC;
563 __u8 maxC;
564 __u8 minY;
565 __u8 maxY;
566};
567
568/**
569 * struct omap3isp_prev_dcor - Defect correction
570 * @couplet_mode_en: Flag to enable or disable the couplet dc Correction in NF
571 * @detect_correct: Thresholds for correction bit 0:10 detect 16:25 correct
572 */
573struct omap3isp_prev_dcor {
574 __u8 couplet_mode_en;
575 __u32 detect_correct[OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS];
576};
577
578/**
579 * struct omap3isp_prev_nf - Noise Filter
580 * @spread: Spread value to be used in Noise Filter
581 * @table: Pointer to the Noise Filter table
582 */
583struct omap3isp_prev_nf {
584 __u8 spread;
585 __u32 table[OMAP3ISP_PREV_NF_TBL_SIZE];
586};
587
588/**
589 * struct omap3isp_prev_gtables - Gamma correction tables
590 * @red: Array for red gamma table.
591 * @green: Array for green gamma table.
592 * @blue: Array for blue gamma table.
593 */
594struct omap3isp_prev_gtables {
595 __u32 red[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
596 __u32 green[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
597 __u32 blue[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
598};
599
600/**
601 * struct omap3isp_prev_luma - Luma enhancement
602 * @table: Array for luma enhancement table.
603 */
604struct omap3isp_prev_luma {
605 __u32 table[OMAP3ISP_PREV_YENH_TBL_SIZE];
606};
607
608/**
609 * struct omap3isp_prev_update_config - Preview engine configuration (user)
610 * @update: Specifies which ISP Preview registers should be updated.
611 * @flag: Specifies which ISP Preview functions should be enabled.
612 * @shading_shift: 3bit value of shift used in shading compensation.
613 * @luma: Pointer to luma enhancement structure.
614 * @hmed: Pointer to structure containing the odd and even distance.
615 * between the pixels in the image along with the filter threshold.
616 * @cfa: Pointer to structure containing the CFA interpolation table, CFA.
617 * format in the image, vertical and horizontal gradient threshold.
618 * @csup: Pointer to Structure for Chrominance Suppression coefficients.
619 * @wbal: Pointer to structure for White Balance.
620 * @blkadj: Pointer to structure for Black Adjustment.
621 * @rgb2rgb: Pointer to structure for RGB to RGB Blending.
622 * @csc: Pointer to structure for Color Space Conversion from RGB-YCbYCr.
623 * @yclimit: Pointer to structure for Y, C Value Limit.
624 * @dcor: Pointer to structure for defect correction.
625 * @nf: Pointer to structure for Noise Filter
626 * @gamma: Pointer to gamma structure.
627 */
628struct omap3isp_prev_update_config {
629 __u32 update;
630 __u32 flag;
631 __u32 shading_shift;
632 struct omap3isp_prev_luma __user *luma;
633 struct omap3isp_prev_hmed __user *hmed;
634 struct omap3isp_prev_cfa __user *cfa;
635 struct omap3isp_prev_csup __user *csup;
636 struct omap3isp_prev_wbal __user *wbal;
637 struct omap3isp_prev_blkadj __user *blkadj;
638 struct omap3isp_prev_rgbtorgb __user *rgb2rgb;
639 struct omap3isp_prev_csc __user *csc;
640 struct omap3isp_prev_yclimit __user *yclimit;
641 struct omap3isp_prev_dcor __user *dcor;
642 struct omap3isp_prev_nf __user *nf;
643 struct omap3isp_prev_gtables __user *gamma;
644};
645
646#endif /* OMAP3_ISP_USER_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 19:30:20 -0400