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authorFelix Fietkau <nbd@openwrt.org>2010-10-05 06:03:42 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-10-06 16:30:38 -0400
commit435c1610f46dc4d86a6633adb037b18109e6ffdc (patch)
tree1fed9f079db50cdd7305abe668848e53ef03223c
parent9dbebc7fd07ab66341dce8d001272db400c11e03 (diff)
ath9k_hw: clean up register write buffering
Throughout the code, DISABLE_REGWRITE_BUFFER is always called right after REGWRITE_BUFFER_FLUSH. Since that's unlikely to change any time soon, that makes keeping those ops separate rather pointless, as it only increases code size and line number counts. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/ath/ath.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c6
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c9
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_calib.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c12
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c14
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h10
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c4
12 files changed, 7 insertions, 61 deletions
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index 5894fcc2c628..cee0191704f5 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -102,14 +102,12 @@ enum ath_cipher {
102 * @read: Register read 102 * @read: Register read
103 * @write: Register write 103 * @write: Register write
104 * @enable_write_buffer: Enable multiple register writes 104 * @enable_write_buffer: Enable multiple register writes
105 * @disable_write_buffer: Disable multiple register writes 105 * @write_flush: flush buffered register writes and disable buffering
106 * @write_flush: Flush buffered register writes
107 */ 106 */
108struct ath_ops { 107struct ath_ops {
109 unsigned int (*read)(void *, u32 reg_offset); 108 unsigned int (*read)(void *, u32 reg_offset);
110 void (*write)(void *, u32 val, u32 reg_offset); 109 void (*write)(void *, u32 val, u32 reg_offset);
111 void (*enable_write_buffer)(void *); 110 void (*enable_write_buffer)(void *);
112 void (*disable_write_buffer)(void *);
113 void (*write_flush) (void *); 111 void (*write_flush) (void *);
114}; 112};
115 113
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 3fba81e3a61f..a1894d240773 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -180,7 +180,6 @@ static void ath9k_ani_restart_old(struct ath_hw *ah)
180 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 180 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
181 181
182 REGWRITE_BUFFER_FLUSH(ah); 182 REGWRITE_BUFFER_FLUSH(ah);
183 DISABLE_REGWRITE_BUFFER(ah);
184 183
185 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 184 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
186 185
@@ -215,7 +214,6 @@ static void ath9k_ani_restart_new(struct ath_hw *ah)
215 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 214 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
216 215
217 REGWRITE_BUFFER_FLUSH(ah); 216 REGWRITE_BUFFER_FLUSH(ah);
218 DISABLE_REGWRITE_BUFFER(ah);
219 217
220 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 218 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
221 219
@@ -643,7 +641,6 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
643 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 641 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
644 642
645 REGWRITE_BUFFER_FLUSH(ah); 643 REGWRITE_BUFFER_FLUSH(ah);
646 DISABLE_REGWRITE_BUFFER(ah);
647} 644}
648 645
649/* 646/*
@@ -737,7 +734,6 @@ static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
737 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 734 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
738 735
739 REGWRITE_BUFFER_FLUSH(ah); 736 REGWRITE_BUFFER_FLUSH(ah);
740 DISABLE_REGWRITE_BUFFER(ah);
741} 737}
742 738
743static void ath9k_hw_ani_monitor_old(struct ath_hw *ah, 739static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
@@ -991,7 +987,6 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
991 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 987 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
992 988
993 REGWRITE_BUFFER_FLUSH(ah); 989 REGWRITE_BUFFER_FLUSH(ah);
994 DISABLE_REGWRITE_BUFFER(ah);
995} 990}
996 991
997/* Freeze the MIB counters, get the stats and then clear them */ 992/* Freeze the MIB counters, get the stats and then clear them */
@@ -1261,7 +1256,6 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
1261 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); 1256 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
1262 1257
1263 REGWRITE_BUFFER_FLUSH(ah); 1258 REGWRITE_BUFFER_FLUSH(ah);
1264 DISABLE_REGWRITE_BUFFER(ah);
1265 1259
1266 ath9k_enable_mib_counters(ah); 1260 ath9k_enable_mib_counters(ah);
1267 1261
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index a11ca0247793..7b26292daf35 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -613,14 +613,11 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
613 rx_chainmask = ah->rxchainmask; 613 rx_chainmask = ah->rxchainmask;
614 tx_chainmask = ah->txchainmask; 614 tx_chainmask = ah->txchainmask;
615 615
616 ENABLE_REGWRITE_BUFFER(ah);
617 616
618 switch (rx_chainmask) { 617 switch (rx_chainmask) {
619 case 0x5: 618 case 0x5:
620 DISABLE_REGWRITE_BUFFER(ah);
621 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 619 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
622 AR_PHY_SWAP_ALT_CHAIN); 620 AR_PHY_SWAP_ALT_CHAIN);
623 ENABLE_REGWRITE_BUFFER(ah);
624 case 0x3: 621 case 0x3:
625 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 622 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
626 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 623 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
@@ -630,17 +627,18 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
630 case 0x1: 627 case 0x1:
631 case 0x2: 628 case 0x2:
632 case 0x7: 629 case 0x7:
630 ENABLE_REGWRITE_BUFFER(ah);
633 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 631 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
634 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 632 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
635 break; 633 break;
636 default: 634 default:
635 ENABLE_REGWRITE_BUFFER(ah);
637 break; 636 break;
638 } 637 }
639 638
640 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 639 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
641 640
642 REGWRITE_BUFFER_FLUSH(ah); 641 REGWRITE_BUFFER_FLUSH(ah);
643 DISABLE_REGWRITE_BUFFER(ah);
644 642
645 if (tx_chainmask == 0x5) { 643 if (tx_chainmask == 0x5) {
646 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 644 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
@@ -726,7 +724,6 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
726 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 724 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
727 725
728 REGWRITE_BUFFER_FLUSH(ah); 726 REGWRITE_BUFFER_FLUSH(ah);
729 DISABLE_REGWRITE_BUFFER(ah);
730} 727}
731 728
732 729
@@ -818,7 +815,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
818 } 815 }
819 816
820 REGWRITE_BUFFER_FLUSH(ah); 817 REGWRITE_BUFFER_FLUSH(ah);
821 DISABLE_REGWRITE_BUFFER(ah);
822 818
823 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 819 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
824 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 820 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
@@ -849,7 +845,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
849 } 845 }
850 846
851 REGWRITE_BUFFER_FLUSH(ah); 847 REGWRITE_BUFFER_FLUSH(ah);
852 DISABLE_REGWRITE_BUFFER(ah);
853 848
854 if (AR_SREV_9271(ah)) { 849 if (AR_SREV_9271(ah)) {
855 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1) 850 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
index f0525fb62a2c..15f62cd0cc38 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -522,7 +522,6 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
522 REG_WRITE(ah, regList[i][0], regList[i][1]); 522 REG_WRITE(ah, regList[i][0], regList[i][1]);
523 523
524 REGWRITE_BUFFER_FLUSH(ah); 524 REGWRITE_BUFFER_FLUSH(ah);
525 DISABLE_REGWRITE_BUFFER(ah);
526} 525}
527 526
528static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset) 527static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index fde45082a13b..78bdf0cec5f0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -371,7 +371,6 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
371 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 371 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
372 372
373 REGWRITE_BUFFER_FLUSH(ah); 373 REGWRITE_BUFFER_FLUSH(ah);
374 DISABLE_REGWRITE_BUFFER(ah);
375 } 374 }
376 375
377 udelay(1000); 376 udelay(1000);
@@ -468,7 +467,6 @@ static int ar9002_hw_get_radiorev(struct ath_hw *ah)
468 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 467 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
469 468
470 REGWRITE_BUFFER_FLUSH(ah); 469 REGWRITE_BUFFER_FLUSH(ah);
471 DISABLE_REGWRITE_BUFFER(ah);
472 470
473 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 471 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
474 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 472 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
@@ -627,6 +625,4 @@ void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
627 } 625 }
628 626
629 REGWRITE_BUFFER_FLUSH(ah); 627 REGWRITE_BUFFER_FLUSH(ah);
630 DISABLE_REGWRITE_BUFFER(ah);
631
632} 628}
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
index cd56c8692705..c00cdc67b55b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -415,7 +415,6 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
415 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 415 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
416 416
417 REGWRITE_BUFFER_FLUSH(ah); 417 REGWRITE_BUFFER_FLUSH(ah);
418 DISABLE_REGWRITE_BUFFER(ah);
419} 418}
420 419
421static void ar9002_olc_init(struct ath_hw *ah) 420static void ar9002_olc_init(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 6c38c72915c1..6d509484b5f6 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -300,7 +300,6 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
300 } 300 }
301 } 301 }
302 REGWRITE_BUFFER_FLUSH(ah); 302 REGWRITE_BUFFER_FLUSH(ah);
303 DISABLE_REGWRITE_BUFFER(ah);
304} 303}
305 304
306 305
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 872e75b0b574..4fa4d8e28c64 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -508,7 +508,6 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
508 } 508 }
509 509
510 REGWRITE_BUFFER_FLUSH(ah); 510 REGWRITE_BUFFER_FLUSH(ah);
511 DISABLE_REGWRITE_BUFFER(ah);
512 } 511 }
513 } 512 }
514 513
@@ -840,7 +839,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
840 } 839 }
841 840
842 REGWRITE_BUFFER_FLUSH(ah); 841 REGWRITE_BUFFER_FLUSH(ah);
843 DISABLE_REGWRITE_BUFFER(ah);
844} 842}
845 843
846static void ath9k_hw_4k_set_addac(struct ath_hw *ah, 844static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index b100db2766cf..bbb54bc28a44 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -380,15 +380,6 @@ static void ath9k_enable_regwrite_buffer(void *hw_priv)
380 atomic_inc(&priv->wmi->mwrite_cnt); 380 atomic_inc(&priv->wmi->mwrite_cnt);
381} 381}
382 382
383static void ath9k_disable_regwrite_buffer(void *hw_priv)
384{
385 struct ath_hw *ah = (struct ath_hw *) hw_priv;
386 struct ath_common *common = ath9k_hw_common(ah);
387 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
388
389 atomic_dec(&priv->wmi->mwrite_cnt);
390}
391
392static void ath9k_regwrite_flush(void *hw_priv) 383static void ath9k_regwrite_flush(void *hw_priv)
393{ 384{
394 struct ath_hw *ah = (struct ath_hw *) hw_priv; 385 struct ath_hw *ah = (struct ath_hw *) hw_priv;
@@ -397,6 +388,8 @@ static void ath9k_regwrite_flush(void *hw_priv)
397 u32 rsp_status; 388 u32 rsp_status;
398 int r; 389 int r;
399 390
391 atomic_dec(&priv->wmi->mwrite_cnt);
392
400 mutex_lock(&priv->wmi->multi_write_mutex); 393 mutex_lock(&priv->wmi->multi_write_mutex);
401 394
402 if (priv->wmi->multi_write_idx) { 395 if (priv->wmi->multi_write_idx) {
@@ -420,7 +413,6 @@ static const struct ath_ops ath9k_common_ops = {
420 .read = ath9k_regread, 413 .read = ath9k_regread,
421 .write = ath9k_regwrite, 414 .write = ath9k_regwrite,
422 .enable_write_buffer = ath9k_enable_regwrite_buffer, 415 .enable_write_buffer = ath9k_enable_regwrite_buffer,
423 .disable_write_buffer = ath9k_disable_regwrite_buffer,
424 .write_flush = ath9k_regwrite_flush, 416 .write_flush = ath9k_regwrite_flush,
425}; 417};
426 418
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 1b066043d6cb..98c97653c21b 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -299,7 +299,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
300 300
301 REGWRITE_BUFFER_FLUSH(ah); 301 REGWRITE_BUFFER_FLUSH(ah);
302 DISABLE_REGWRITE_BUFFER(ah);
303} 302}
304 303
305/* This should work for all families including legacy */ 304/* This should work for all families including legacy */
@@ -676,7 +675,6 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
676 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 675 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
677 676
678 REGWRITE_BUFFER_FLUSH(ah); 677 REGWRITE_BUFFER_FLUSH(ah);
679 DISABLE_REGWRITE_BUFFER(ah);
680} 678}
681 679
682static void ath9k_hw_init_pll(struct ath_hw *ah, 680static void ath9k_hw_init_pll(struct ath_hw *ah,
@@ -741,7 +739,6 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
741 } 739 }
742 740
743 REGWRITE_BUFFER_FLUSH(ah); 741 REGWRITE_BUFFER_FLUSH(ah);
744 DISABLE_REGWRITE_BUFFER(ah);
745 742
746 if (AR_SREV_9300_20_OR_LATER(ah)) { 743 if (AR_SREV_9300_20_OR_LATER(ah)) {
747 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 744 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
@@ -885,7 +882,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
885 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 882 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
886 883
887 REGWRITE_BUFFER_FLUSH(ah); 884 REGWRITE_BUFFER_FLUSH(ah);
888 DISABLE_REGWRITE_BUFFER(ah);
889 885
890 /* 886 /*
891 * Restore TX Trigger Level to its pre-reset value. 887 * Restore TX Trigger Level to its pre-reset value.
@@ -933,7 +929,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
933 } 929 }
934 930
935 REGWRITE_BUFFER_FLUSH(ah); 931 REGWRITE_BUFFER_FLUSH(ah);
936 DISABLE_REGWRITE_BUFFER(ah);
937 932
938 if (AR_SREV_9300_20_OR_LATER(ah)) 933 if (AR_SREV_9300_20_OR_LATER(ah))
939 ath9k_hw_reset_txstatus_ring(ah); 934 ath9k_hw_reset_txstatus_ring(ah);
@@ -1031,7 +1026,6 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1031 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1026 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1032 1027
1033 REGWRITE_BUFFER_FLUSH(ah); 1028 REGWRITE_BUFFER_FLUSH(ah);
1034 DISABLE_REGWRITE_BUFFER(ah);
1035 1029
1036 udelay(50); 1030 udelay(50);
1037 1031
@@ -1070,7 +1064,6 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1070 udelay(2); 1064 udelay(2);
1071 1065
1072 REGWRITE_BUFFER_FLUSH(ah); 1066 REGWRITE_BUFFER_FLUSH(ah);
1073 DISABLE_REGWRITE_BUFFER(ah);
1074 1067
1075 if (!AR_SREV_9300_20_OR_LATER(ah)) 1068 if (!AR_SREV_9300_20_OR_LATER(ah))
1076 udelay(2); 1069 udelay(2);
@@ -1374,7 +1367,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1374 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1367 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1375 1368
1376 REGWRITE_BUFFER_FLUSH(ah); 1369 REGWRITE_BUFFER_FLUSH(ah);
1377 DISABLE_REGWRITE_BUFFER(ah);
1378 1370
1379 r = ath9k_hw_rf_set_freq(ah, chan); 1371 r = ath9k_hw_rf_set_freq(ah, chan);
1380 if (r) 1372 if (r)
@@ -1386,7 +1378,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1386 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1378 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1387 1379
1388 REGWRITE_BUFFER_FLUSH(ah); 1380 REGWRITE_BUFFER_FLUSH(ah);
1389 DISABLE_REGWRITE_BUFFER(ah);
1390 1381
1391 ah->intr_txqs = 0; 1382 ah->intr_txqs = 0;
1392 for (i = 0; i < ah->caps.total_queues; i++) 1383 for (i = 0; i < ah->caps.total_queues; i++)
@@ -1434,7 +1425,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1434 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1425 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1435 1426
1436 REGWRITE_BUFFER_FLUSH(ah); 1427 REGWRITE_BUFFER_FLUSH(ah);
1437 DISABLE_REGWRITE_BUFFER(ah);
1438 1428
1439 /* 1429 /*
1440 * For big endian systems turn on swapping for descriptors 1430 * For big endian systems turn on swapping for descriptors
@@ -1684,7 +1674,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1684 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1674 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1685 1675
1686 REGWRITE_BUFFER_FLUSH(ah); 1676 REGWRITE_BUFFER_FLUSH(ah);
1687 DISABLE_REGWRITE_BUFFER(ah);
1688 1677
1689 beacon_period &= ~ATH9K_BEACON_ENA; 1678 beacon_period &= ~ATH9K_BEACON_ENA;
1690 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1679 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
@@ -1712,7 +1701,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1712 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1701 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1713 1702
1714 REGWRITE_BUFFER_FLUSH(ah); 1703 REGWRITE_BUFFER_FLUSH(ah);
1715 DISABLE_REGWRITE_BUFFER(ah);
1716 1704
1717 REG_RMW_FIELD(ah, AR_RSSI_THR, 1705 REG_RMW_FIELD(ah, AR_RSSI_THR,
1718 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1706 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
@@ -1758,7 +1746,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1758 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1746 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1759 1747
1760 REGWRITE_BUFFER_FLUSH(ah); 1748 REGWRITE_BUFFER_FLUSH(ah);
1761 DISABLE_REGWRITE_BUFFER(ah);
1762 1749
1763 REG_SET_BIT(ah, AR_TIMER_MODE, 1750 REG_SET_BIT(ah, AR_TIMER_MODE,
1764 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1751 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
@@ -2176,7 +2163,6 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2176 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2163 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2177 2164
2178 REGWRITE_BUFFER_FLUSH(ah); 2165 REGWRITE_BUFFER_FLUSH(ah);
2179 DISABLE_REGWRITE_BUFFER(ah);
2180} 2166}
2181EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2167EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2182 2168
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 87dbb8502469..d558c51236f9 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -70,19 +70,13 @@
70 70
71#define ENABLE_REGWRITE_BUFFER(_ah) \ 71#define ENABLE_REGWRITE_BUFFER(_ah) \
72 do { \ 72 do { \
73 if (AR_SREV_9271(_ah)) \ 73 if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \ 74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
75 } while (0) 75 } while (0)
76 76
77#define DISABLE_REGWRITE_BUFFER(_ah) \
78 do { \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
81 } while (0)
82
83#define REGWRITE_BUFFER_FLUSH(_ah) \ 77#define REGWRITE_BUFFER_FLUSH(_ah) \
84 do { \ 78 do { \
85 if (AR_SREV_9271(_ah)) \ 79 if (ath9k_hw_common(_ah)->ops->write_flush) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \ 80 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
87 } while (0) 81 } while (0)
88 82
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 3efda8a8a3c1..e5784595bd0f 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -40,7 +40,6 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
40 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 40 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
41 41
42 REGWRITE_BUFFER_FLUSH(ah); 42 REGWRITE_BUFFER_FLUSH(ah);
43 DISABLE_REGWRITE_BUFFER(ah);
44} 43}
45 44
46u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) 45u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
@@ -530,7 +529,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
530 } 529 }
531 530
532 REGWRITE_BUFFER_FLUSH(ah); 531 REGWRITE_BUFFER_FLUSH(ah);
533 DISABLE_REGWRITE_BUFFER(ah);
534 532
535 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 533 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
536 REG_WRITE(ah, AR_DMISC(q), 534 REG_WRITE(ah, AR_DMISC(q),
@@ -553,7 +551,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
553 | AR_D_MISC_POST_FR_BKOFF_DIS); 551 | AR_D_MISC_POST_FR_BKOFF_DIS);
554 552
555 REGWRITE_BUFFER_FLUSH(ah); 553 REGWRITE_BUFFER_FLUSH(ah);
556 DISABLE_REGWRITE_BUFFER(ah);
557 554
558 /* 555 /*
559 * cwmin and cwmax should be 0 for beacon queue 556 * cwmin and cwmax should be 0 for beacon queue
@@ -585,7 +582,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
585 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); 582 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
586 583
587 REGWRITE_BUFFER_FLUSH(ah); 584 REGWRITE_BUFFER_FLUSH(ah);
588 DISABLE_REGWRITE_BUFFER(ah);
589 585
590 break; 586 break;
591 case ATH9K_TX_QUEUE_PSPOLL: 587 case ATH9K_TX_QUEUE_PSPOLL: