diff options
| author | Borislav Petkov <petkovbb@googlemail.com> | 2010-02-04 03:51:28 -0500 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-02-04 04:01:38 -0500 |
| commit | 34d2819f20782feb60f9434470ecfb200875fd41 (patch) | |
| tree | b75561b2e41a9fb18a40980723546d8d7a073ee0 | |
| parent | 00097c4fdf117d9845d772f571a987ae95523f8c (diff) | |
x86, mtrr: Remove unused mtrr/state.c
The last reference to the helpers in
<arch/x86/kernel/cpu/mtrr/state.c> went away with
9a6b344ea967efa0bb5ca4cb5405f840652b66c4 leaving unused code.
Remove it.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <20100204085128.GA513@liondog.tnic>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
| -rw-r--r-- | arch/x86/kernel/cpu/mtrr/Makefile | 2 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/mtrr/state.c | 94 |
2 files changed, 1 insertions, 95 deletions
diff --git a/arch/x86/kernel/cpu/mtrr/Makefile b/arch/x86/kernel/cpu/mtrr/Makefile index f4361b56f8e9..ad9e5ed81181 100644 --- a/arch/x86/kernel/cpu/mtrr/Makefile +++ b/arch/x86/kernel/cpu/mtrr/Makefile | |||
| @@ -1,3 +1,3 @@ | |||
| 1 | obj-y := main.o if.o generic.o state.o cleanup.o | 1 | obj-y := main.o if.o generic.o cleanup.o |
| 2 | obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o | 2 | obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o |
| 3 | 3 | ||
diff --git a/arch/x86/kernel/cpu/mtrr/state.c b/arch/x86/kernel/cpu/mtrr/state.c deleted file mode 100644 index dfc80b4e6b0d..000000000000 --- a/arch/x86/kernel/cpu/mtrr/state.c +++ /dev/null | |||
| @@ -1,94 +0,0 @@ | |||
| 1 | #include <linux/init.h> | ||
| 2 | #include <linux/io.h> | ||
| 3 | #include <linux/mm.h> | ||
| 4 | |||
| 5 | #include <asm/processor-cyrix.h> | ||
| 6 | #include <asm/processor-flags.h> | ||
| 7 | #include <asm/mtrr.h> | ||
| 8 | #include <asm/msr.h> | ||
| 9 | |||
| 10 | #include "mtrr.h" | ||
| 11 | |||
| 12 | /* Put the processor into a state where MTRRs can be safely set */ | ||
| 13 | void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) | ||
| 14 | { | ||
| 15 | unsigned int cr0; | ||
| 16 | |||
| 17 | /* Disable interrupts locally */ | ||
| 18 | local_irq_save(ctxt->flags); | ||
| 19 | |||
| 20 | if (use_intel() || is_cpu(CYRIX)) { | ||
| 21 | |||
| 22 | /* Save value of CR4 and clear Page Global Enable (bit 7) */ | ||
| 23 | if (cpu_has_pge) { | ||
| 24 | ctxt->cr4val = read_cr4(); | ||
| 25 | write_cr4(ctxt->cr4val & ~X86_CR4_PGE); | ||
| 26 | } | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Disable and flush caches. Note that wbinvd flushes the TLBs | ||
| 30 | * as a side-effect | ||
| 31 | */ | ||
| 32 | cr0 = read_cr0() | X86_CR0_CD; | ||
| 33 | wbinvd(); | ||
| 34 | write_cr0(cr0); | ||
| 35 | wbinvd(); | ||
| 36 | |||
| 37 | if (use_intel()) { | ||
| 38 | /* Save MTRR state */ | ||
| 39 | rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi); | ||
| 40 | } else { | ||
| 41 | /* | ||
| 42 | * Cyrix ARRs - | ||
| 43 | * everything else were excluded at the top | ||
| 44 | */ | ||
| 45 | ctxt->ccr3 = getCx86(CX86_CCR3); | ||
| 46 | } | ||
| 47 | } | ||
| 48 | } | ||
| 49 | |||
| 50 | void set_mtrr_cache_disable(struct set_mtrr_context *ctxt) | ||
| 51 | { | ||
| 52 | if (use_intel()) { | ||
| 53 | /* Disable MTRRs, and set the default type to uncached */ | ||
| 54 | mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL, | ||
| 55 | ctxt->deftype_hi); | ||
| 56 | } else { | ||
| 57 | if (is_cpu(CYRIX)) { | ||
| 58 | /* Cyrix ARRs - everything else were excluded at the top */ | ||
| 59 | setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10); | ||
| 60 | } | ||
| 61 | } | ||
| 62 | } | ||
| 63 | |||
| 64 | /* Restore the processor after a set_mtrr_prepare */ | ||
| 65 | void set_mtrr_done(struct set_mtrr_context *ctxt) | ||
| 66 | { | ||
| 67 | if (use_intel() || is_cpu(CYRIX)) { | ||
| 68 | |||
| 69 | /* Flush caches and TLBs */ | ||
| 70 | wbinvd(); | ||
| 71 | |||
| 72 | /* Restore MTRRdefType */ | ||
| 73 | if (use_intel()) { | ||
| 74 | /* Intel (P6) standard MTRRs */ | ||
| 75 | mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo, | ||
| 76 | ctxt->deftype_hi); | ||
| 77 | } else { | ||
| 78 | /* | ||
| 79 | * Cyrix ARRs - | ||
| 80 | * everything else was excluded at the top | ||
| 81 | */ | ||
| 82 | setCx86(CX86_CCR3, ctxt->ccr3); | ||
| 83 | } | ||
| 84 | |||
| 85 | /* Enable caches */ | ||
| 86 | write_cr0(read_cr0() & 0xbfffffff); | ||
| 87 | |||
| 88 | /* Restore value of CR4 */ | ||
| 89 | if (cpu_has_pge) | ||
| 90 | write_cr4(ctxt->cr4val); | ||
| 91 | } | ||
| 92 | /* Re-enable interrupts locally (if enabled previously) */ | ||
| 93 | local_irq_restore(ctxt->flags); | ||
| 94 | } | ||
