diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-09-06 06:53:13 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-09-06 06:53:13 -0400 |
commit | 2f02a59c559c28f777ea7d198da87f634cc809c0 (patch) | |
tree | bc6194a304299d169239579fd3eaca5e511529f6 | |
parent | e6929378071a1ef68d1dc2f10c0b4a1bcc603f4c (diff) | |
parent | c776357e0adc2a25bd22eb75155030132c88a0dd (diff) |
Merge branch 'for-2.6.37' of git://git.kernel.org/pub/scm/linux/kernel/git/lrg/asoc-2.6 into for-2.6.37
-rw-r--r-- | arch/arm/mach-omap2/board-rx51-peripherals.c | 4 | ||||
-rw-r--r-- | sound/soc/codecs/tlv320aic3x.c | 528 | ||||
-rw-r--r-- | sound/soc/codecs/tlv320aic3x.h | 55 | ||||
-rw-r--r-- | sound/soc/omap/rx51.c | 4 |
4 files changed, 309 insertions, 282 deletions
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 897d960fe16f..11ce4b24befd 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
@@ -710,10 +710,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = { | |||
710 | .vio = &rx51_vio, | 710 | .vio = &rx51_vio, |
711 | }; | 711 | }; |
712 | 712 | ||
713 | static struct aic3x_pdata rx51_aic3x_data __initdata = { | ||
714 | .gpio_reset = 60, | ||
715 | }; | ||
716 | |||
717 | static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { | 713 | static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { |
718 | .id = TPA6130A2, | 714 | .id = TPA6130A2, |
719 | .power_gpio = 98, | 715 | .power_gpio = 98, |
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index c07465720cdb..b3175860bcb4 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c | |||
@@ -292,64 +292,102 @@ static const struct snd_kcontrol_new aic3x_snd_controls[] = { | |||
292 | SOC_DOUBLE_R_TLV("PCM Playback Volume", | 292 | SOC_DOUBLE_R_TLV("PCM Playback Volume", |
293 | LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), | 293 | LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), |
294 | 294 | ||
295 | /* | ||
296 | * Output controls that map to output mixer switches. Note these are | ||
297 | * only for swapped L-to-R and R-to-L routes. See below stereo controls | ||
298 | * for direct L-to-L and R-to-R routes. | ||
299 | */ | ||
300 | SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", | ||
301 | LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | ||
302 | SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", | ||
303 | PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | ||
304 | SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", | ||
305 | DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | ||
306 | |||
307 | SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", | ||
308 | LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | ||
309 | SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", | ||
310 | PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | ||
311 | SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", | ||
312 | DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | ||
313 | |||
314 | SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", | ||
315 | LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | ||
316 | SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", | ||
317 | PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | ||
318 | SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", | ||
319 | DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | ||
320 | |||
321 | SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", | ||
322 | LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | ||
323 | SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", | ||
324 | PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | ||
325 | SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", | ||
326 | DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | ||
327 | |||
328 | SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", | ||
329 | LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | ||
330 | SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", | ||
331 | PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | ||
332 | SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", | ||
333 | DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | ||
334 | |||
335 | SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", | ||
336 | LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | ||
337 | SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", | ||
338 | PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | ||
339 | SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", | ||
340 | DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | ||
341 | |||
342 | /* Stereo output controls for direct L-to-L and R-to-R routes */ | ||
343 | SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", | ||
344 | LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, | ||
345 | 0, 118, 1, output_stage_tlv), | ||
346 | SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", | ||
347 | PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, | ||
348 | 0, 118, 1, output_stage_tlv), | ||
295 | SOC_DOUBLE_R_TLV("Line DAC Playback Volume", | 349 | SOC_DOUBLE_R_TLV("Line DAC Playback Volume", |
296 | DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, | 350 | DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, |
297 | 0, 118, 1, output_stage_tlv), | 351 | 0, 118, 1, output_stage_tlv), |
298 | SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0), | 352 | |
299 | SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0), | 353 | SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", |
300 | SOC_DOUBLE_R_TLV("LineL DAC Playback Volume", | 354 | LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, |
301 | DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL, | ||
302 | 0, 118, 1, output_stage_tlv), | ||
303 | SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume", | ||
304 | PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | ||
305 | SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume", | ||
306 | PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | ||
307 | SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume", | ||
308 | LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL, | ||
309 | 0, 118, 1, output_stage_tlv), | 355 | 0, 118, 1, output_stage_tlv), |
310 | SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume", | 356 | SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", |
311 | LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL, | 357 | PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, |
312 | 0, 118, 1, output_stage_tlv), | 358 | 0, 118, 1, output_stage_tlv), |
313 | |||
314 | SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", | 359 | SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", |
315 | DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, | 360 | DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, |
316 | 0, 118, 1, output_stage_tlv), | 361 | 0, 118, 1, output_stage_tlv), |
317 | SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), | 362 | |
318 | SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume", | 363 | SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", |
319 | PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, | 364 | LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, |
320 | 0, 118, 1, output_stage_tlv), | 365 | 0, 118, 1, output_stage_tlv), |
321 | SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume", | 366 | SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", |
322 | LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, | 367 | PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, |
323 | 0, 118, 1, output_stage_tlv), | 368 | 0, 118, 1, output_stage_tlv), |
324 | |||
325 | SOC_DOUBLE_R_TLV("HP DAC Playback Volume", | 369 | SOC_DOUBLE_R_TLV("HP DAC Playback Volume", |
326 | DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, | 370 | DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, |
327 | 0, 118, 1, output_stage_tlv), | 371 | 0, 118, 1, output_stage_tlv), |
328 | SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, | 372 | |
329 | 0x01, 0), | 373 | SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", |
330 | SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume", | 374 | LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, |
331 | PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, | ||
332 | 0, 118, 1, output_stage_tlv), | 375 | 0, 118, 1, output_stage_tlv), |
333 | SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume", | 376 | SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", |
334 | PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | 377 | PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, |
335 | SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume", | ||
336 | PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | ||
337 | SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume", | ||
338 | LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, | ||
339 | 0, 118, 1, output_stage_tlv), | 378 | 0, 118, 1, output_stage_tlv), |
340 | |||
341 | SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", | 379 | SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", |
342 | DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, | 380 | DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, |
343 | 0, 118, 1, output_stage_tlv), | 381 | 0, 118, 1, output_stage_tlv), |
344 | SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, | 382 | |
383 | /* Output pin mute controls */ | ||
384 | SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, | ||
385 | 0x01, 0), | ||
386 | SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), | ||
387 | SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, | ||
388 | 0x01, 0), | ||
389 | SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, | ||
345 | 0x01, 0), | 390 | 0x01, 0), |
346 | SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume", | ||
347 | PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | ||
348 | SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume", | ||
349 | PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | ||
350 | SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume", | ||
351 | LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, | ||
352 | 0, 118, 1, output_stage_tlv), | ||
353 | 391 | ||
354 | /* | 392 | /* |
355 | * Note: enable Automatic input Gain Controller with care. It can | 393 | * Note: enable Automatic input Gain Controller with care. It can |
@@ -389,22 +427,74 @@ SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); | |||
389 | static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = | 427 | static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = |
390 | SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); | 428 | SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); |
391 | 429 | ||
392 | /* Left DAC_L1 Mixer */ | 430 | /* Left Line Mixer */ |
393 | static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = { | 431 | static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { |
394 | SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), | 432 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), |
395 | SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), | 433 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), |
396 | SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), | 434 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), |
397 | SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), | 435 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), |
398 | SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), | 436 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), |
437 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), | ||
438 | }; | ||
439 | |||
440 | /* Right Line Mixer */ | ||
441 | static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { | ||
442 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), | ||
443 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), | ||
444 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), | ||
445 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), | ||
446 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), | ||
447 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), | ||
448 | }; | ||
449 | |||
450 | /* Mono Mixer */ | ||
451 | static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { | ||
452 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), | ||
453 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), | ||
454 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), | ||
455 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), | ||
456 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), | ||
457 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), | ||
458 | }; | ||
459 | |||
460 | /* Left HP Mixer */ | ||
461 | static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { | ||
462 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), | ||
463 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), | ||
464 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), | ||
465 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), | ||
466 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), | ||
467 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), | ||
468 | }; | ||
469 | |||
470 | /* Right HP Mixer */ | ||
471 | static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { | ||
472 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), | ||
473 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), | ||
474 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), | ||
475 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), | ||
476 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), | ||
477 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), | ||
478 | }; | ||
479 | |||
480 | /* Left HPCOM Mixer */ | ||
481 | static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { | ||
482 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), | ||
483 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), | ||
484 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), | ||
485 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), | ||
486 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), | ||
487 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), | ||
399 | }; | 488 | }; |
400 | 489 | ||
401 | /* Right DAC_R1 Mixer */ | 490 | /* Right HPCOM Mixer */ |
402 | static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = { | 491 | static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { |
403 | SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), | 492 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), |
404 | SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), | 493 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), |
405 | SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), | 494 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), |
406 | SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), | 495 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), |
407 | SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), | 496 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), |
497 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), | ||
408 | }; | 498 | }; |
409 | 499 | ||
410 | /* Left PGA Mixer */ | 500 | /* Left PGA Mixer */ |
@@ -441,54 +531,11 @@ SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); | |||
441 | static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = | 531 | static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = |
442 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); | 532 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); |
443 | 533 | ||
444 | /* Left PGA Bypass Mixer */ | ||
445 | static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = { | ||
446 | SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), | ||
447 | SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), | ||
448 | SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), | ||
449 | SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), | ||
450 | SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), | ||
451 | SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), | ||
452 | SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), | ||
453 | }; | ||
454 | |||
455 | /* Right PGA Bypass Mixer */ | ||
456 | static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = { | ||
457 | SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), | ||
458 | SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), | ||
459 | SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), | ||
460 | SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), | ||
461 | SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), | ||
462 | SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), | ||
463 | SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), | ||
464 | }; | ||
465 | |||
466 | /* Left Line2 Bypass Mixer */ | ||
467 | static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = { | ||
468 | SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), | ||
469 | SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), | ||
470 | SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), | ||
471 | SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), | ||
472 | SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), | ||
473 | }; | ||
474 | |||
475 | /* Right Line2 Bypass Mixer */ | ||
476 | static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = { | ||
477 | SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), | ||
478 | SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), | ||
479 | SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), | ||
480 | SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), | ||
481 | SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), | ||
482 | }; | ||
483 | |||
484 | static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { | 534 | static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { |
485 | /* Left DAC to Left Outputs */ | 535 | /* Left DAC to Left Outputs */ |
486 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), | 536 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), |
487 | SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, | 537 | SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, |
488 | &aic3x_left_dac_mux_controls), | 538 | &aic3x_left_dac_mux_controls), |
489 | SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0, | ||
490 | &aic3x_left_dac_mixer_controls[0], | ||
491 | ARRAY_SIZE(aic3x_left_dac_mixer_controls)), | ||
492 | SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, | 539 | SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, |
493 | &aic3x_left_hpcom_mux_controls), | 540 | &aic3x_left_hpcom_mux_controls), |
494 | SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), | 541 | SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), |
@@ -499,9 +546,6 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { | |||
499 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), | 546 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), |
500 | SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, | 547 | SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, |
501 | &aic3x_right_dac_mux_controls), | 548 | &aic3x_right_dac_mux_controls), |
502 | SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0, | ||
503 | &aic3x_right_dac_mixer_controls[0], | ||
504 | ARRAY_SIZE(aic3x_right_dac_mixer_controls)), | ||
505 | SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, | 549 | SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, |
506 | &aic3x_right_hpcom_mux_controls), | 550 | &aic3x_right_hpcom_mux_controls), |
507 | SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), | 551 | SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), |
@@ -565,25 +609,28 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { | |||
565 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", | 609 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", |
566 | MICBIAS_CTRL, 6, 3, 3, 0), | 610 | MICBIAS_CTRL, 6, 3, 3, 0), |
567 | 611 | ||
568 | /* Left PGA to Left Output bypass */ | 612 | /* Output mixers */ |
569 | SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | 613 | SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, |
570 | &aic3x_left_pga_bp_mixer_controls[0], | 614 | &aic3x_left_line_mixer_controls[0], |
571 | ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)), | 615 | ARRAY_SIZE(aic3x_left_line_mixer_controls)), |
572 | 616 | SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, | |
573 | /* Right PGA to Right Output bypass */ | 617 | &aic3x_right_line_mixer_controls[0], |
574 | SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | 618 | ARRAY_SIZE(aic3x_right_line_mixer_controls)), |
575 | &aic3x_right_pga_bp_mixer_controls[0], | 619 | SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, |
576 | ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)), | 620 | &aic3x_mono_mixer_controls[0], |
577 | 621 | ARRAY_SIZE(aic3x_mono_mixer_controls)), | |
578 | /* Left Line2 to Left Output bypass */ | 622 | SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, |
579 | SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | 623 | &aic3x_left_hp_mixer_controls[0], |
580 | &aic3x_left_line2_bp_mixer_controls[0], | 624 | ARRAY_SIZE(aic3x_left_hp_mixer_controls)), |
581 | ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)), | 625 | SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, |
582 | 626 | &aic3x_right_hp_mixer_controls[0], | |
583 | /* Right Line2 to Right Output bypass */ | 627 | ARRAY_SIZE(aic3x_right_hp_mixer_controls)), |
584 | SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | 628 | SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, |
585 | &aic3x_right_line2_bp_mixer_controls[0], | 629 | &aic3x_left_hpcom_mixer_controls[0], |
586 | ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)), | 630 | ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), |
631 | SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, | ||
632 | &aic3x_right_hpcom_mixer_controls[0], | ||
633 | ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), | ||
587 | 634 | ||
588 | SND_SOC_DAPM_OUTPUT("LLOUT"), | 635 | SND_SOC_DAPM_OUTPUT("LLOUT"), |
589 | SND_SOC_DAPM_OUTPUT("RLOUT"), | 636 | SND_SOC_DAPM_OUTPUT("RLOUT"), |
@@ -611,66 +658,6 @@ static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { | |||
611 | }; | 658 | }; |
612 | 659 | ||
613 | static const struct snd_soc_dapm_route intercon[] = { | 660 | static const struct snd_soc_dapm_route intercon[] = { |
614 | /* Left Output */ | ||
615 | {"Left DAC Mux", "DAC_L1", "Left DAC"}, | ||
616 | {"Left DAC Mux", "DAC_L2", "Left DAC"}, | ||
617 | {"Left DAC Mux", "DAC_L3", "Left DAC"}, | ||
618 | |||
619 | {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"}, | ||
620 | {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"}, | ||
621 | {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"}, | ||
622 | {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"}, | ||
623 | {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"}, | ||
624 | {"Left Line Out", NULL, "Left DAC Mux"}, | ||
625 | {"Left HP Out", NULL, "Left DAC Mux"}, | ||
626 | |||
627 | {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"}, | ||
628 | {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"}, | ||
629 | {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"}, | ||
630 | |||
631 | {"Left Line Out", NULL, "Left DAC_L1 Mixer"}, | ||
632 | {"Mono Out", NULL, "Left DAC_L1 Mixer"}, | ||
633 | {"Left HP Out", NULL, "Left DAC_L1 Mixer"}, | ||
634 | {"Left HP Com", NULL, "Left HPCOM Mux"}, | ||
635 | |||
636 | {"LLOUT", NULL, "Left Line Out"}, | ||
637 | {"LLOUT", NULL, "Left Line Out"}, | ||
638 | {"HPLOUT", NULL, "Left HP Out"}, | ||
639 | {"HPLCOM", NULL, "Left HP Com"}, | ||
640 | |||
641 | /* Right Output */ | ||
642 | {"Right DAC Mux", "DAC_R1", "Right DAC"}, | ||
643 | {"Right DAC Mux", "DAC_R2", "Right DAC"}, | ||
644 | {"Right DAC Mux", "DAC_R3", "Right DAC"}, | ||
645 | |||
646 | {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"}, | ||
647 | {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"}, | ||
648 | {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"}, | ||
649 | {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"}, | ||
650 | {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"}, | ||
651 | {"Right Line Out", NULL, "Right DAC Mux"}, | ||
652 | {"Right HP Out", NULL, "Right DAC Mux"}, | ||
653 | |||
654 | {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"}, | ||
655 | {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"}, | ||
656 | {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"}, | ||
657 | {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"}, | ||
658 | {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"}, | ||
659 | |||
660 | {"Right Line Out", NULL, "Right DAC_R1 Mixer"}, | ||
661 | {"Mono Out", NULL, "Right DAC_R1 Mixer"}, | ||
662 | {"Right HP Out", NULL, "Right DAC_R1 Mixer"}, | ||
663 | {"Right HP Com", NULL, "Right HPCOM Mux"}, | ||
664 | |||
665 | {"RLOUT", NULL, "Right Line Out"}, | ||
666 | {"RLOUT", NULL, "Right Line Out"}, | ||
667 | {"HPROUT", NULL, "Right HP Out"}, | ||
668 | {"HPRCOM", NULL, "Right HP Com"}, | ||
669 | |||
670 | /* Mono Output */ | ||
671 | {"MONO_LOUT", NULL, "Mono Out"}, | ||
672 | {"MONO_LOUT", NULL, "Mono Out"}, | ||
673 | |||
674 | /* Left Input */ | 661 | /* Left Input */ |
675 | {"Left Line1L Mux", "single-ended", "LINE1L"}, | 662 | {"Left Line1L Mux", "single-ended", "LINE1L"}, |
676 | {"Left Line1L Mux", "differential", "LINE1L"}, | 663 | {"Left Line1L Mux", "differential", "LINE1L"}, |
@@ -703,74 +690,6 @@ static const struct snd_soc_dapm_route intercon[] = { | |||
703 | {"Right ADC", NULL, "Right PGA Mixer"}, | 690 | {"Right ADC", NULL, "Right PGA Mixer"}, |
704 | {"Right ADC", NULL, "GPIO1 dmic modclk"}, | 691 | {"Right ADC", NULL, "GPIO1 dmic modclk"}, |
705 | 692 | ||
706 | /* Left PGA Bypass */ | ||
707 | {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"}, | ||
708 | {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"}, | ||
709 | {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"}, | ||
710 | {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"}, | ||
711 | {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"}, | ||
712 | {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"}, | ||
713 | {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"}, | ||
714 | |||
715 | {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"}, | ||
716 | {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"}, | ||
717 | {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"}, | ||
718 | |||
719 | {"Left Line Out", NULL, "Left PGA Bypass Mixer"}, | ||
720 | {"Mono Out", NULL, "Left PGA Bypass Mixer"}, | ||
721 | {"Left HP Out", NULL, "Left PGA Bypass Mixer"}, | ||
722 | |||
723 | /* Right PGA Bypass */ | ||
724 | {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"}, | ||
725 | {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"}, | ||
726 | {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"}, | ||
727 | {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"}, | ||
728 | {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"}, | ||
729 | {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"}, | ||
730 | {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"}, | ||
731 | |||
732 | {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"}, | ||
733 | {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"}, | ||
734 | {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"}, | ||
735 | {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"}, | ||
736 | {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"}, | ||
737 | |||
738 | {"Right Line Out", NULL, "Right PGA Bypass Mixer"}, | ||
739 | {"Mono Out", NULL, "Right PGA Bypass Mixer"}, | ||
740 | {"Right HP Out", NULL, "Right PGA Bypass Mixer"}, | ||
741 | |||
742 | /* Left Line2 Bypass */ | ||
743 | {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"}, | ||
744 | {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"}, | ||
745 | {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"}, | ||
746 | {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"}, | ||
747 | {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"}, | ||
748 | |||
749 | {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"}, | ||
750 | {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"}, | ||
751 | {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"}, | ||
752 | |||
753 | {"Left Line Out", NULL, "Left Line2 Bypass Mixer"}, | ||
754 | {"Mono Out", NULL, "Left Line2 Bypass Mixer"}, | ||
755 | {"Left HP Out", NULL, "Left Line2 Bypass Mixer"}, | ||
756 | |||
757 | /* Right Line2 Bypass */ | ||
758 | {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"}, | ||
759 | {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"}, | ||
760 | {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"}, | ||
761 | {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"}, | ||
762 | {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"}, | ||
763 | |||
764 | {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"}, | ||
765 | {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"}, | ||
766 | {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"}, | ||
767 | {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"}, | ||
768 | {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"}, | ||
769 | |||
770 | {"Right Line Out", NULL, "Right Line2 Bypass Mixer"}, | ||
771 | {"Mono Out", NULL, "Right Line2 Bypass Mixer"}, | ||
772 | {"Right HP Out", NULL, "Right Line2 Bypass Mixer"}, | ||
773 | |||
774 | /* | 693 | /* |
775 | * Logical path between digital mic enable and GPIO1 modulator clock | 694 | * Logical path between digital mic enable and GPIO1 modulator clock |
776 | * output function | 695 | * output function |
@@ -778,6 +697,105 @@ static const struct snd_soc_dapm_route intercon[] = { | |||
778 | {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, | 697 | {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, |
779 | {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, | 698 | {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, |
780 | {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, | 699 | {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, |
700 | |||
701 | /* Left DAC Output */ | ||
702 | {"Left DAC Mux", "DAC_L1", "Left DAC"}, | ||
703 | {"Left DAC Mux", "DAC_L2", "Left DAC"}, | ||
704 | {"Left DAC Mux", "DAC_L3", "Left DAC"}, | ||
705 | |||
706 | /* Right DAC Output */ | ||
707 | {"Right DAC Mux", "DAC_R1", "Right DAC"}, | ||
708 | {"Right DAC Mux", "DAC_R2", "Right DAC"}, | ||
709 | {"Right DAC Mux", "DAC_R3", "Right DAC"}, | ||
710 | |||
711 | /* Left Line Output */ | ||
712 | {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | ||
713 | {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, | ||
714 | {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, | ||
715 | {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | ||
716 | {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, | ||
717 | {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, | ||
718 | |||
719 | {"Left Line Out", NULL, "Left Line Mixer"}, | ||
720 | {"Left Line Out", NULL, "Left DAC Mux"}, | ||
721 | {"LLOUT", NULL, "Left Line Out"}, | ||
722 | |||
723 | /* Right Line Output */ | ||
724 | {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | ||
725 | {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, | ||
726 | {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, | ||
727 | {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | ||
728 | {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, | ||
729 | {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, | ||
730 | |||
731 | {"Right Line Out", NULL, "Right Line Mixer"}, | ||
732 | {"Right Line Out", NULL, "Right DAC Mux"}, | ||
733 | {"RLOUT", NULL, "Right Line Out"}, | ||
734 | |||
735 | /* Mono Output */ | ||
736 | {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | ||
737 | {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, | ||
738 | {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, | ||
739 | {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | ||
740 | {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, | ||
741 | {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, | ||
742 | |||
743 | {"Mono Out", NULL, "Mono Mixer"}, | ||
744 | {"MONO_LOUT", NULL, "Mono Out"}, | ||
745 | |||
746 | /* Left HP Output */ | ||
747 | {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | ||
748 | {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, | ||
749 | {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, | ||
750 | {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | ||
751 | {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, | ||
752 | {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, | ||
753 | |||
754 | {"Left HP Out", NULL, "Left HP Mixer"}, | ||
755 | {"Left HP Out", NULL, "Left DAC Mux"}, | ||
756 | {"HPLOUT", NULL, "Left HP Out"}, | ||
757 | |||
758 | /* Right HP Output */ | ||
759 | {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | ||
760 | {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, | ||
761 | {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, | ||
762 | {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | ||
763 | {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, | ||
764 | {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, | ||
765 | |||
766 | {"Right HP Out", NULL, "Right HP Mixer"}, | ||
767 | {"Right HP Out", NULL, "Right DAC Mux"}, | ||
768 | {"HPROUT", NULL, "Right HP Out"}, | ||
769 | |||
770 | /* Left HPCOM Output */ | ||
771 | {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | ||
772 | {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, | ||
773 | {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, | ||
774 | {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | ||
775 | {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, | ||
776 | {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, | ||
777 | |||
778 | {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, | ||
779 | {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, | ||
780 | {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, | ||
781 | {"Left HP Com", NULL, "Left HPCOM Mux"}, | ||
782 | {"HPLCOM", NULL, "Left HP Com"}, | ||
783 | |||
784 | /* Right HPCOM Output */ | ||
785 | {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | ||
786 | {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, | ||
787 | {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, | ||
788 | {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | ||
789 | {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, | ||
790 | {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, | ||
791 | |||
792 | {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, | ||
793 | {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, | ||
794 | {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, | ||
795 | {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, | ||
796 | {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, | ||
797 | {"Right HP Com", NULL, "Right HPCOM Mux"}, | ||
798 | {"HPRCOM", NULL, "Right HP Com"}, | ||
781 | }; | 799 | }; |
782 | 800 | ||
783 | static const struct snd_soc_dapm_route intercon_3007[] = { | 801 | static const struct snd_soc_dapm_route intercon_3007[] = { |
@@ -1281,6 +1299,8 @@ static int aic3x_probe(struct snd_soc_codec *codec) | |||
1281 | codec->hw_write = (hw_write_t) i2c_master_send; | 1299 | codec->hw_write = (hw_write_t) i2c_master_send; |
1282 | codec->control_data = aic3x->control_data; | 1300 | codec->control_data = aic3x->control_data; |
1283 | 1301 | ||
1302 | aic3x_init(codec); | ||
1303 | |||
1284 | if (aic3x->setup) { | 1304 | if (aic3x->setup) { |
1285 | /* setup GPIO functions */ | 1305 | /* setup GPIO functions */ |
1286 | aic3x_write(codec, AIC3X_GPIO1_REG, | 1306 | aic3x_write(codec, AIC3X_GPIO1_REG, |
@@ -1289,8 +1309,6 @@ static int aic3x_probe(struct snd_soc_codec *codec) | |||
1289 | (aic3x->setup->gpio_func[1] & 0xf) << 4); | 1309 | (aic3x->setup->gpio_func[1] & 0xf) << 4); |
1290 | } | 1310 | } |
1291 | 1311 | ||
1292 | aic3x_init(codec); | ||
1293 | |||
1294 | snd_soc_add_controls(codec, aic3x_snd_controls, | 1312 | snd_soc_add_controls(codec, aic3x_snd_controls, |
1295 | ARRAY_SIZE(aic3x_snd_controls)); | 1313 | ARRAY_SIZE(aic3x_snd_controls)); |
1296 | if (aic3x->model == AIC3X_MODEL_3007) | 1314 | if (aic3x->model == AIC3X_MODEL_3007) |
@@ -1342,7 +1360,6 @@ static int aic3x_i2c_probe(struct i2c_client *i2c, | |||
1342 | const struct i2c_device_id *id) | 1360 | const struct i2c_device_id *id) |
1343 | { | 1361 | { |
1344 | struct aic3x_pdata *pdata = i2c->dev.platform_data; | 1362 | struct aic3x_pdata *pdata = i2c->dev.platform_data; |
1345 | struct aic3x_setup_data *setup = pdata->setup; | ||
1346 | struct aic3x_priv *aic3x; | 1363 | struct aic3x_priv *aic3x; |
1347 | int ret, i; | 1364 | int ret, i; |
1348 | const struct i2c_device_id *tbl; | 1365 | const struct i2c_device_id *tbl; |
@@ -1354,15 +1371,18 @@ static int aic3x_i2c_probe(struct i2c_client *i2c, | |||
1354 | } | 1371 | } |
1355 | 1372 | ||
1356 | aic3x->control_data = i2c; | 1373 | aic3x->control_data = i2c; |
1357 | aic3x->setup = setup; | ||
1358 | i2c_set_clientdata(i2c, aic3x); | 1374 | i2c_set_clientdata(i2c, aic3x); |
1375 | if (pdata) { | ||
1376 | aic3x->gpio_reset = pdata->gpio_reset; | ||
1377 | aic3x->setup = pdata->setup; | ||
1378 | } else { | ||
1379 | aic3x->gpio_reset = -1; | ||
1380 | } | ||
1359 | 1381 | ||
1360 | aic3x->gpio_reset = -1; | 1382 | if (aic3x->gpio_reset >= 0) { |
1361 | if (pdata && pdata->gpio_reset >= 0) { | 1383 | ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); |
1362 | ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset"); | ||
1363 | if (ret != 0) | 1384 | if (ret != 0) |
1364 | goto err_gpio; | 1385 | goto err_gpio; |
1365 | aic3x->gpio_reset = pdata->gpio_reset; | ||
1366 | gpio_direction_output(aic3x->gpio_reset, 0); | 1386 | gpio_direction_output(aic3x->gpio_reset, 0); |
1367 | } | 1387 | } |
1368 | 1388 | ||
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h index 98e44395b662..06a19784b162 100644 --- a/sound/soc/codecs/tlv320aic3x.h +++ b/sound/soc/codecs/tlv320aic3x.h | |||
@@ -81,52 +81,63 @@ | |||
81 | /* DAC Digital control registers */ | 81 | /* DAC Digital control registers */ |
82 | #define LDAC_VOL 43 | 82 | #define LDAC_VOL 43 |
83 | #define RDAC_VOL 44 | 83 | #define RDAC_VOL 44 |
84 | /* High Power Output control registers */ | 84 | /* Left High Power Output control registers */ |
85 | #define LINE2L_2_HPLOUT_VOL 45 | 85 | #define LINE2L_2_HPLOUT_VOL 45 |
86 | #define LINE2R_2_HPROUT_VOL 62 | ||
87 | #define PGAL_2_HPLOUT_VOL 46 | 86 | #define PGAL_2_HPLOUT_VOL 46 |
88 | #define PGAL_2_HPROUT_VOL 60 | ||
89 | #define PGAR_2_HPLOUT_VOL 49 | ||
90 | #define PGAR_2_HPROUT_VOL 63 | ||
91 | #define DACL1_2_HPLOUT_VOL 47 | 87 | #define DACL1_2_HPLOUT_VOL 47 |
92 | #define DACR1_2_HPROUT_VOL 64 | 88 | #define LINE2R_2_HPLOUT_VOL 48 |
89 | #define PGAR_2_HPLOUT_VOL 49 | ||
90 | #define DACR1_2_HPLOUT_VOL 50 | ||
93 | #define HPLOUT_CTRL 51 | 91 | #define HPLOUT_CTRL 51 |
94 | #define HPROUT_CTRL 65 | 92 | /* Left High Power COM control registers */ |
95 | /* High Power COM control registers */ | ||
96 | #define LINE2L_2_HPLCOM_VOL 52 | 93 | #define LINE2L_2_HPLCOM_VOL 52 |
97 | #define LINE2R_2_HPRCOM_VOL 69 | ||
98 | #define PGAL_2_HPLCOM_VOL 53 | 94 | #define PGAL_2_HPLCOM_VOL 53 |
95 | #define DACL1_2_HPLCOM_VOL 54 | ||
96 | #define LINE2R_2_HPLCOM_VOL 55 | ||
99 | #define PGAR_2_HPLCOM_VOL 56 | 97 | #define PGAR_2_HPLCOM_VOL 56 |
98 | #define DACR1_2_HPLCOM_VOL 57 | ||
99 | #define HPLCOM_CTRL 58 | ||
100 | /* Right High Power Output control registers */ | ||
101 | #define LINE2L_2_HPROUT_VOL 59 | ||
102 | #define PGAL_2_HPROUT_VOL 60 | ||
103 | #define DACL1_2_HPROUT_VOL 61 | ||
104 | #define LINE2R_2_HPROUT_VOL 62 | ||
105 | #define PGAR_2_HPROUT_VOL 63 | ||
106 | #define DACR1_2_HPROUT_VOL 64 | ||
107 | #define HPROUT_CTRL 65 | ||
108 | /* Right High Power COM control registers */ | ||
109 | #define LINE2L_2_HPRCOM_VOL 66 | ||
100 | #define PGAL_2_HPRCOM_VOL 67 | 110 | #define PGAL_2_HPRCOM_VOL 67 |
111 | #define DACL1_2_HPRCOM_VOL 68 | ||
112 | #define LINE2R_2_HPRCOM_VOL 69 | ||
101 | #define PGAR_2_HPRCOM_VOL 70 | 113 | #define PGAR_2_HPRCOM_VOL 70 |
102 | #define DACL1_2_HPLCOM_VOL 54 | ||
103 | #define DACR1_2_HPRCOM_VOL 71 | 114 | #define DACR1_2_HPRCOM_VOL 71 |
104 | #define HPLCOM_CTRL 58 | ||
105 | #define HPRCOM_CTRL 72 | 115 | #define HPRCOM_CTRL 72 |
106 | /* Mono Line Output Plus/Minus control registers */ | 116 | /* Mono Line Output Plus/Minus control registers */ |
107 | #define LINE2L_2_MONOLOPM_VOL 73 | 117 | #define LINE2L_2_MONOLOPM_VOL 73 |
108 | #define LINE2R_2_MONOLOPM_VOL 76 | ||
109 | #define PGAL_2_MONOLOPM_VOL 74 | 118 | #define PGAL_2_MONOLOPM_VOL 74 |
110 | #define PGAR_2_MONOLOPM_VOL 77 | ||
111 | #define DACL1_2_MONOLOPM_VOL 75 | 119 | #define DACL1_2_MONOLOPM_VOL 75 |
120 | #define LINE2R_2_MONOLOPM_VOL 76 | ||
121 | #define PGAR_2_MONOLOPM_VOL 77 | ||
112 | #define DACR1_2_MONOLOPM_VOL 78 | 122 | #define DACR1_2_MONOLOPM_VOL 78 |
113 | #define MONOLOPM_CTRL 79 | 123 | #define MONOLOPM_CTRL 79 |
114 | /* Class-D speaker driver on tlv320aic3007 */ | 124 | /* Class-D speaker driver on tlv320aic3007 */ |
115 | #define CLASSD_CTRL 73 | 125 | #define CLASSD_CTRL 73 |
116 | /* Line Output Plus/Minus control registers */ | 126 | /* Left Line Output Plus/Minus control registers */ |
117 | #define LINE2L_2_LLOPM_VOL 80 | 127 | #define LINE2L_2_LLOPM_VOL 80 |
118 | #define LINE2L_2_RLOPM_VOL 87 | ||
119 | #define LINE2R_2_LLOPM_VOL 83 | ||
120 | #define LINE2R_2_RLOPM_VOL 90 | ||
121 | #define PGAL_2_LLOPM_VOL 81 | 128 | #define PGAL_2_LLOPM_VOL 81 |
122 | #define PGAL_2_RLOPM_VOL 88 | ||
123 | #define PGAR_2_LLOPM_VOL 84 | ||
124 | #define PGAR_2_RLOPM_VOL 91 | ||
125 | #define DACL1_2_LLOPM_VOL 82 | 129 | #define DACL1_2_LLOPM_VOL 82 |
126 | #define DACL1_2_RLOPM_VOL 89 | 130 | #define LINE2R_2_LLOPM_VOL 83 |
127 | #define DACR1_2_RLOPM_VOL 92 | 131 | #define PGAR_2_LLOPM_VOL 84 |
128 | #define DACR1_2_LLOPM_VOL 85 | 132 | #define DACR1_2_LLOPM_VOL 85 |
129 | #define LLOPM_CTRL 86 | 133 | #define LLOPM_CTRL 86 |
134 | /* Right Line Output Plus/Minus control registers */ | ||
135 | #define LINE2L_2_RLOPM_VOL 87 | ||
136 | #define PGAL_2_RLOPM_VOL 88 | ||
137 | #define DACL1_2_RLOPM_VOL 89 | ||
138 | #define LINE2R_2_RLOPM_VOL 90 | ||
139 | #define PGAR_2_RLOPM_VOL 91 | ||
140 | #define DACR1_2_RLOPM_VOL 92 | ||
130 | #define RLOPM_CTRL 93 | 141 | #define RLOPM_CTRL 93 |
131 | /* GPIO/IRQ registers */ | 142 | /* GPIO/IRQ registers */ |
132 | #define AIC3X_STICKY_IRQ_FLAGS_REG 96 | 143 | #define AIC3X_STICKY_IRQ_FLAGS_REG 96 |
diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51.c index d1d8098923ce..04b5723bf89b 100644 --- a/sound/soc/omap/rx51.c +++ b/sound/soc/omap/rx51.c | |||
@@ -146,9 +146,9 @@ static int rx51_spk_event(struct snd_soc_dapm_widget *w, | |||
146 | struct snd_kcontrol *k, int event) | 146 | struct snd_kcontrol *k, int event) |
147 | { | 147 | { |
148 | if (SND_SOC_DAPM_EVENT_ON(event)) | 148 | if (SND_SOC_DAPM_EVENT_ON(event)) |
149 | gpio_set_value(RX51_SPEAKER_AMP_TWL_GPIO, 1); | 149 | gpio_set_value_cansleep(RX51_SPEAKER_AMP_TWL_GPIO, 1); |
150 | else | 150 | else |
151 | gpio_set_value(RX51_SPEAKER_AMP_TWL_GPIO, 0); | 151 | gpio_set_value_cansleep(RX51_SPEAKER_AMP_TWL_GPIO, 0); |
152 | 152 | ||
153 | return 0; | 153 | return 0; |
154 | } | 154 | } |