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authorLinus Torvalds <torvalds@linux-foundation.org>2009-11-30 16:54:10 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-11-30 16:54:10 -0500
commit23e041dbaa80eb1032f9d612433c6b9062da5afd (patch)
tree40783f4dff7c887e424c2466d7b74deb2c019a64
parentf50733450362182fd16d658751615635850a8bff (diff)
parent5349ef3127c77075ff70b2014f17ae0fbcaaf199 (diff)
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/fb: fix FBIOGET/PUT_VSCREENINFO pixel clock handling drm: make sure page protections are updated after changing vm_flags drm/radeon/kms: Report vga connector is connected according to ddc_probe drm: mm always protect change to unused_nodes with unused_lock spinlock drm/radeon/kms: Disable TV load detect on RS400,RC410,RS480 drm/radeon/kms: read back register before writing in IIO. drm/radeon/kms: fix handling of d1/d2 vga drm: work around EDIDs with bad htotal/vtotal values drm/radeon/kms: resume AGP by calling init.
-rw-r--r--drivers/gpu/drm/drm_edid.c6
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c6
-rw-r--r--drivers/gpu/drm/drm_gem.c2
-rw-r--r--drivers/gpu/drm/drm_mm.c9
-rw-r--r--drivers/gpu/drm/radeon/atom.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c12
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c2
-rw-r--r--drivers/gpu/drm/radeon/rv515.c9
10 files changed, 51 insertions, 13 deletions
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index cea665d86dd3..b54ba63d506e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -662,6 +662,12 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
662 return NULL; 662 return NULL;
663 } 663 }
664 664
665 /* Some EDIDs have bogus h/vtotal values */
666 if (mode->hsync_end > mode->htotal)
667 mode->htotal = mode->hsync_end + 1;
668 if (mode->vsync_end > mode->vtotal)
669 mode->vtotal = mode->vsync_end + 1;
670
665 drm_mode_set_name(mode); 671 drm_mode_set_name(mode);
666 672
667 if (pt->misc & DRM_EDID_PT_INTERLACED) 673 if (pt->misc & DRM_EDID_PT_INTERLACED)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index dc8e374a0b55..65ef011fa8ba 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -599,7 +599,7 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
599 struct drm_framebuffer *fb = fb_helper->fb; 599 struct drm_framebuffer *fb = fb_helper->fb;
600 int depth; 600 int depth;
601 601
602 if (var->pixclock == -1 || !var->pixclock) 602 if (var->pixclock != 0)
603 return -EINVAL; 603 return -EINVAL;
604 604
605 /* Need to resize the fb object !!! */ 605 /* Need to resize the fb object !!! */
@@ -691,7 +691,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
691 int ret; 691 int ret;
692 int i; 692 int i;
693 693
694 if (var->pixclock != -1) { 694 if (var->pixclock != 0) {
695 DRM_ERROR("PIXEL CLCOK SET\n"); 695 DRM_ERROR("PIXEL CLCOK SET\n");
696 return -EINVAL; 696 return -EINVAL;
697 } 697 }
@@ -904,7 +904,7 @@ int drm_fb_helper_single_fb_probe(struct drm_device *dev,
904 fb_helper->fb = fb; 904 fb_helper->fb = fb;
905 905
906 if (new_fb) { 906 if (new_fb) {
907 info->var.pixclock = -1; 907 info->var.pixclock = 0;
908 if (register_framebuffer(info) < 0) 908 if (register_framebuffer(info) < 0)
909 return -EINVAL; 909 return -EINVAL;
910 } else { 910 } else {
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 80391995bdec..e9dbb481c469 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -552,7 +552,7 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
552 vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND; 552 vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND;
553 vma->vm_ops = obj->dev->driver->gem_vm_ops; 553 vma->vm_ops = obj->dev->driver->gem_vm_ops;
554 vma->vm_private_data = map->handle; 554 vma->vm_private_data = map->handle;
555 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 555 vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
556 556
557 /* Take a ref for this mapping of the object, so that the fault 557 /* Take a ref for this mapping of the object, so that the fault
558 * handler can dereference the mmap offset's pointer to the object. 558 * handler can dereference the mmap offset's pointer to the object.
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index c861d80fd779..97dc5a4f0de4 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -103,6 +103,11 @@ static struct drm_mm_node *drm_mm_kmalloc(struct drm_mm *mm, int atomic)
103 return child; 103 return child;
104} 104}
105 105
106/* drm_mm_pre_get() - pre allocate drm_mm_node structure
107 * drm_mm: memory manager struct we are pre-allocating for
108 *
109 * Returns 0 on success or -ENOMEM if allocation fails.
110 */
106int drm_mm_pre_get(struct drm_mm *mm) 111int drm_mm_pre_get(struct drm_mm *mm)
107{ 112{
108 struct drm_mm_node *node; 113 struct drm_mm_node *node;
@@ -253,12 +258,14 @@ void drm_mm_put_block(struct drm_mm_node *cur)
253 prev_node->size += next_node->size; 258 prev_node->size += next_node->size;
254 list_del(&next_node->ml_entry); 259 list_del(&next_node->ml_entry);
255 list_del(&next_node->fl_entry); 260 list_del(&next_node->fl_entry);
261 spin_lock(&mm->unused_lock);
256 if (mm->num_unused < MM_UNUSED_TARGET) { 262 if (mm->num_unused < MM_UNUSED_TARGET) {
257 list_add(&next_node->fl_entry, 263 list_add(&next_node->fl_entry,
258 &mm->unused_nodes); 264 &mm->unused_nodes);
259 ++mm->num_unused; 265 ++mm->num_unused;
260 } else 266 } else
261 kfree(next_node); 267 kfree(next_node);
268 spin_unlock(&mm->unused_lock);
262 } else { 269 } else {
263 next_node->size += cur->size; 270 next_node->size += cur->size;
264 next_node->start = cur->start; 271 next_node->start = cur->start;
@@ -271,11 +278,13 @@ void drm_mm_put_block(struct drm_mm_node *cur)
271 list_add(&cur->fl_entry, &mm->fl_entry); 278 list_add(&cur->fl_entry, &mm->fl_entry);
272 } else { 279 } else {
273 list_del(&cur->ml_entry); 280 list_del(&cur->ml_entry);
281 spin_lock(&mm->unused_lock);
274 if (mm->num_unused < MM_UNUSED_TARGET) { 282 if (mm->num_unused < MM_UNUSED_TARGET) {
275 list_add(&cur->fl_entry, &mm->unused_nodes); 283 list_add(&cur->fl_entry, &mm->unused_nodes);
276 ++mm->num_unused; 284 ++mm->num_unused;
277 } else 285 } else
278 kfree(cur); 286 kfree(cur);
287 spin_unlock(&mm->unused_lock);
279 } 288 }
280} 289}
281 290
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 901befe03da2..d67c42555ab9 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -107,6 +107,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
107 base += 3; 107 base += 3;
108 break; 108 break;
109 case ATOM_IIO_WRITE: 109 case ATOM_IIO_WRITE:
110 (void)ctx->card->reg_read(ctx->card, CU16(base + 1));
110 ctx->card->reg_write(ctx->card, CU16(base + 1), temp); 111 ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
111 base += 3; 112 base += 3;
112 break; 113 break;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 757f5cd37744..224506a2f7b1 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -519,6 +519,7 @@ typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
519 * AGP 519 * AGP
520 */ 520 */
521int radeon_agp_init(struct radeon_device *rdev); 521int radeon_agp_init(struct radeon_device *rdev);
522void radeon_agp_resume(struct radeon_device *rdev);
522void radeon_agp_fini(struct radeon_device *rdev); 523void radeon_agp_fini(struct radeon_device *rdev);
523 524
524 525
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 23ea9955ac59..54bf49a6d676 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -237,6 +237,18 @@ int radeon_agp_init(struct radeon_device *rdev)
237#endif 237#endif
238} 238}
239 239
240void radeon_agp_resume(struct radeon_device *rdev)
241{
242#if __OS_HAS_AGP
243 int r;
244 if (rdev->flags & RADEON_IS_AGP) {
245 r = radeon_agp_init(rdev);
246 if (r)
247 dev_warn(rdev->dev, "radeon AGP reinit failed\n");
248 }
249#endif
250}
251
240void radeon_agp_fini(struct radeon_device *rdev) 252void radeon_agp_fini(struct radeon_device *rdev)
241{ 253{
242#if __OS_HAS_AGP 254#if __OS_HAS_AGP
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index fce4c4087fda..29763ceae3af 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -566,8 +566,9 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
566 radeon_i2c_do_lock(radeon_connector, 0); 566 radeon_i2c_do_lock(radeon_connector, 0);
567 567
568 if (!radeon_connector->edid) { 568 if (!radeon_connector->edid) {
569 DRM_ERROR("DDC responded but not EDID found for %s\n", 569 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
570 drm_get_connector_name(connector)); 570 drm_get_connector_name(connector));
571 ret = connector_status_connected;
571 } else { 572 } else {
572 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 573 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
573 574
@@ -720,8 +721,8 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
720 radeon_i2c_do_lock(radeon_connector, 0); 721 radeon_i2c_do_lock(radeon_connector, 0);
721 722
722 if (!radeon_connector->edid) { 723 if (!radeon_connector->edid) {
723 DRM_ERROR("DDC responded but not EDID found for %s\n", 724 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
724 drm_get_connector_name(connector)); 725 drm_get_connector_name(connector));
725 } else { 726 } else {
726 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 727 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
727 728
@@ -1149,6 +1150,13 @@ radeon_add_legacy_connector(struct drm_device *dev,
1149 if (ret) 1150 if (ret)
1150 goto failed; 1151 goto failed;
1151 radeon_connector->dac_load_detect = true; 1152 radeon_connector->dac_load_detect = true;
1153 /* RS400,RC410,RS480 chipset seems to report a lot
1154 * of false positive on load detect, we haven't yet
1155 * found a way to make load detect reliable on those
1156 * chipset, thus just disable it for TV.
1157 */
1158 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
1159 radeon_connector->dac_load_detect = false;
1152 drm_connector_attach_property(&radeon_connector->base, 1160 drm_connector_attach_property(&radeon_connector->base,
1153 rdev->mode_info.load_detect_property, 1161 rdev->mode_info.load_detect_property,
1154 1); 1162 1);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e3f9edfa40fe..41bb76fbe734 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -688,6 +688,8 @@ int radeon_resume_kms(struct drm_device *dev)
688 return -1; 688 return -1;
689 } 689 }
690 pci_set_master(dev->pdev); 690 pci_set_master(dev->pdev);
691 /* resume AGP if in use */
692 radeon_agp_resume(rdev);
691 radeon_resume(rdev); 693 radeon_resume(rdev);
692 radeon_restore_bios_scratch_regs(rdev); 694 radeon_restore_bios_scratch_regs(rdev);
693 fb_set_suspend(rdev->fbdev_info, 0); 695 fb_set_suspend(rdev->fbdev_info, 0);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 7935f793bf62..ba68c9fe90a1 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -137,8 +137,6 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev)
137 137
138void rv515_vga_render_disable(struct radeon_device *rdev) 138void rv515_vga_render_disable(struct radeon_device *rdev)
139{ 139{
140 WREG32(R_000330_D1VGA_CONTROL, 0);
141 WREG32(R_000338_D2VGA_CONTROL, 0);
142 WREG32(R_000300_VGA_RENDER_CONTROL, 140 WREG32(R_000300_VGA_RENDER_CONTROL,
143 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 141 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
144} 142}
@@ -382,7 +380,6 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
382 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); 380 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
383 381
384 /* Stop all video */ 382 /* Stop all video */
385 WREG32(R_000330_D1VGA_CONTROL, 0);
386 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 383 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
387 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 384 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
388 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 385 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
@@ -391,6 +388,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
391 WREG32(R_006880_D2CRTC_CONTROL, 0); 388 WREG32(R_006880_D2CRTC_CONTROL, 0);
392 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 389 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
393 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 390 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
391 WREG32(R_000330_D1VGA_CONTROL, 0);
392 WREG32(R_000338_D2VGA_CONTROL, 0);
394} 393}
395 394
396void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 395void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -404,14 +403,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
404 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 403 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
405 mdelay(1); 404 mdelay(1);
406 /* Restore video state */ 405 /* Restore video state */
406 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
407 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
407 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 408 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
408 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 409 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
409 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); 410 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
410 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); 411 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
411 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 412 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
412 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 413 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
413 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
414 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
415 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 414 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
416} 415}
417 416