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authorMark Lord <liml@rtr.ca>2008-01-26 18:33:59 -0500
committerJeff Garzik <jeff@garzik.org>2008-02-01 11:29:49 -0500
commit1fd2e1c242acb4a589d59c77853897bdbb599186 (patch)
tree3eb81a847aaf7101c6bc95bc8c4aa73bc121ba6c
parenta838b173c327890abc2059fc8b2d65f199622f48 (diff)
sata_mv ncq Comments and version bump
Remove some obsolete comments, and bump up the driver version number. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r--drivers/ata/sata_mv.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index d4634cf0fdc5..38d4d08283e2 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -29,7 +29,13 @@
29 I distinctly remember a couple workarounds (one related to PCI-X) 29 I distinctly remember a couple workarounds (one related to PCI-X)
30 are still needed. 30 are still needed.
31 31
32 4) Add NCQ support (easy to intermediate, once new-EH support appears) 32 2) Improve/fix IRQ and error handling sequences.
33
34 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35
36 4) Think about TCQ support here, and for libata in general
37 with controllers that suppport it via host-queuing hardware
38 (a software-only implementation could be a nightmare).
33 39
34 5) Investigate problems with PCI Message Signalled Interrupts (MSI). 40 5) Investigate problems with PCI Message Signalled Interrupts (MSI).
35 41
@@ -53,8 +59,6 @@
53 Target mode, for those without docs, is the ability to directly 59 Target mode, for those without docs, is the ability to directly
54 connect two SATA controllers. 60 connect two SATA controllers.
55 61
56 13) Verify that 7042 is fully supported. I only have a 6042.
57
58*/ 62*/
59 63
60 64
@@ -73,7 +77,7 @@
73#include <linux/libata.h> 77#include <linux/libata.h>
74 78
75#define DRV_NAME "sata_mv" 79#define DRV_NAME "sata_mv"
76#define DRV_VERSION "1.01" 80#define DRV_VERSION "1.20"
77 81
78enum { 82enum {
79 /* BAR's are enumerated in terms of pci_resource_start() terms */ 83 /* BAR's are enumerated in terms of pci_resource_start() terms */