diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2007-12-22 21:09:29 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-01-28 08:20:48 -0500 |
| commit | 1fb4e5611a9d0b524d85f0db4402aa439ebdb331 (patch) | |
| tree | a9682add37dfc15fe9654f88d76a5d5b5262fbe3 | |
| parent | 9b73e76f3cf63379dcf45fcd4f112f5812418d0a (diff) | |
[ARM] 4719/1: S3C2412: Update SPI register definitions for the S3C2412
Add S3C2412 register definitions.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | include/asm-arm/plat-s3c24xx/regs-spi.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h index 4a499a138256..960907f17914 100644 --- a/include/asm-arm/plat-s3c24xx/regs-spi.h +++ b/include/asm-arm/plat-s3c24xx/regs-spi.h | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | 17 | ||
| 18 | #define S3C2410_SPCON (0x00) | 18 | #define S3C2410_SPCON (0x00) |
| 19 | 19 | ||
| 20 | #define S3C2412_SPCON_DIRC_RX (1<<7) | ||
| 20 | #define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ | 21 | #define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ |
| 21 | #define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ | 22 | #define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ |
| 22 | #define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ | 23 | #define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ |
| @@ -37,7 +38,7 @@ | |||
| 37 | #define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ | 38 | #define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ |
| 38 | #define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ | 39 | #define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ |
| 39 | #define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ | 40 | #define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ |
| 40 | 41 | #define S3C2412_SPSTA_READY_ORG (1<<3) | |
| 41 | 42 | ||
| 42 | #define S3C2410_SPPIN (0x08) | 43 | #define S3C2410_SPPIN (0x08) |
| 43 | 44 | ||
| @@ -46,9 +47,13 @@ | |||
| 46 | #define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */ | 47 | #define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */ |
| 47 | #define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ | 48 | #define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ |
| 48 | 49 | ||
| 49 | |||
| 50 | #define S3C2410_SPPRE (0x0C) | 50 | #define S3C2410_SPPRE (0x0C) |
| 51 | #define S3C2410_SPTDAT (0x10) | 51 | #define S3C2410_SPTDAT (0x10) |
| 52 | #define S3C2410_SPRDAT (0x14) | 52 | #define S3C2410_SPRDAT (0x14) |
| 53 | 53 | ||
| 54 | #define S3C2412_TXFIFO (0x18) | ||
| 55 | #define S3C2412_RXFIFO (0x18) | ||
| 56 | #define S3C2412_SPFIC (0x24) | ||
| 57 | |||
| 58 | |||
| 54 | #endif /* __ASM_ARCH_REGS_SPI_H */ | 59 | #endif /* __ASM_ARCH_REGS_SPI_H */ |
