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authorDave Airlie <airlied@redhat.com>2010-12-21 18:48:04 -0500
committerDave Airlie <airlied@redhat.com>2010-12-21 18:48:04 -0500
commit1d99e5c57255d188773fb437391df24fe8faf575 (patch)
tree25300afe457342c6d694de18020c804486a10eac
parent880981e49b90568ebb53428e231b43b8c1049ef9 (diff)
parent183720b8af5301e2eab7f3163f03133c5a6ad6da (diff)
Merge remote branch 'nouveau/drm-nouveau-next' of /ssd/git/drm-nouveau-next into drm-core-next
* 'nouveau/drm-nouveau-next' of /ssd/git/drm-nouveau-next: drm/nvc0: accelerate ttm buffer moves drm/nvc0: initial support for tiled buffer objects drm/nvc0: implement fbcon acceleration drm/nvc0: implement pgraph engine hooks drm/nvc0: implement pfifo engine hooks drm/nvc0: implement fencing drm/nvc0: fix channel dma init paths drm/nvc0: skip dma object creation for drm channel drm/nvc0: implement channel structure initialisation drm/nvc0: gpuobj_new need only check validity and init the relevant engine drm/nvc0: reject the notifier_alloc ioctl drm/nvc0: create shared channel vm drm/nvc0: initial vm implementation, use for bar1/bar3 management drm/nvc0: import initial vm backend drm/nouveau: modify vm to accomodate dual page tables for nvc0 drm/nv50: add missing license header to nv50_fbcon.c drm/nv50: fix smatch warning in nv50_vram.c drm/nouveau: sizeof() vs ARRAY_SIZE()
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/Makefile10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c73
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c20
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.c22
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.h9
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h12
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c24
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.h6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fence.c28
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c7
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mm.h5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_notifier.c5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_object.c39
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c21
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_vm.c90
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_vm.h26
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c18
-rw-r--r--drivers/gpu/drm/nouveau/nv50_evo.c53
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fbcon.c24
-rw-r--r--drivers/gpu/drm/nouveau/nv50_instmem.c16
-rw-r--r--drivers/gpu/drm/nouveau/nv50_vm.c52
-rw-r--r--drivers/gpu/drm/nouveau/nv50_vram.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_fbcon.c271
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_fifo.c359
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.c709
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.h66
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grctx.c2854
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_instmem.c342
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_vm.c123
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_vram.c99
30 files changed, 5044 insertions, 341 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index b1d8941e04d8..e12c97fd8db8 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -18,17 +18,19 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
18 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o nvc0_fifo.o \ 18 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o nvc0_fifo.o \
19 nv04_graph.o nv10_graph.o nv20_graph.o \ 19 nv04_graph.o nv10_graph.o nv20_graph.o \
20 nv40_graph.o nv50_graph.o nvc0_graph.o \ 20 nv40_graph.o nv50_graph.o nvc0_graph.o \
21 nv40_grctx.o nv50_grctx.o \ 21 nv40_grctx.o nv50_grctx.o nvc0_grctx.o \
22 nv84_crypt.o \ 22 nv84_crypt.o \
23 nv04_instmem.o nv50_instmem.o nvc0_instmem.o \ 23 nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
24 nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \ 24 nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
25 nv50_cursor.o nv50_display.o nv50_fbcon.o \ 25 nv50_cursor.o nv50_display.o \
26 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ 26 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
27 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ 27 nv04_crtc.o nv04_display.o nv04_cursor.o \
28 nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o \
28 nv10_gpio.o nv50_gpio.o \ 29 nv10_gpio.o nv50_gpio.o \
29 nv50_calc.o \ 30 nv50_calc.o \
30 nv04_pm.o nv50_pm.o nva3_pm.o \ 31 nv04_pm.o nv50_pm.o nva3_pm.o \
31 nv50_vram.o nv50_vm.o 32 nv50_vram.o nvc0_vram.o \
33 nv50_vm.o nvc0_vm.o
32 34
33nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o 35nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
34nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o 36nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 42d1ad62b381..a7fae26f4654 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -413,7 +413,7 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
413 man->default_caching = TTM_PL_FLAG_CACHED; 413 man->default_caching = TTM_PL_FLAG_CACHED;
414 break; 414 break;
415 case TTM_PL_VRAM: 415 case TTM_PL_VRAM:
416 if (dev_priv->card_type == NV_50) { 416 if (dev_priv->card_type >= NV_50) {
417 man->func = &nouveau_vram_manager; 417 man->func = &nouveau_vram_manager;
418 man->io_reserve_fastpath = false; 418 man->io_reserve_fastpath = false;
419 man->use_io_reserve_lru = true; 419 man->use_io_reserve_lru = true;
@@ -515,6 +515,58 @@ nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
515} 515}
516 516
517static int 517static int
518nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
519 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
520{
521 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
522 struct nouveau_bo *nvbo = nouveau_bo(bo);
523 u64 src_offset = old_mem->start << PAGE_SHIFT;
524 u64 dst_offset = new_mem->start << PAGE_SHIFT;
525 u32 page_count = new_mem->num_pages;
526 int ret;
527
528 if (!nvbo->no_vm) {
529 if (old_mem->mem_type == TTM_PL_VRAM)
530 src_offset = nvbo->vma.offset;
531 else
532 src_offset += dev_priv->gart_info.aper_base;
533
534 if (new_mem->mem_type == TTM_PL_VRAM)
535 dst_offset = nvbo->vma.offset;
536 else
537 dst_offset += dev_priv->gart_info.aper_base;
538 }
539
540 page_count = new_mem->num_pages;
541 while (page_count) {
542 int line_count = (page_count > 2047) ? 2047 : page_count;
543
544 ret = RING_SPACE(chan, 12);
545 if (ret)
546 return ret;
547
548 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
549 OUT_RING (chan, upper_32_bits(dst_offset));
550 OUT_RING (chan, lower_32_bits(dst_offset));
551 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
552 OUT_RING (chan, upper_32_bits(src_offset));
553 OUT_RING (chan, lower_32_bits(src_offset));
554 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
555 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
556 OUT_RING (chan, PAGE_SIZE); /* line_length */
557 OUT_RING (chan, line_count);
558 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
559 OUT_RING (chan, 0x00100110);
560
561 page_count -= line_count;
562 src_offset += (PAGE_SIZE * line_count);
563 dst_offset += (PAGE_SIZE * line_count);
564 }
565
566 return 0;
567}
568
569static int
518nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 570nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
519 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) 571 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
520{ 572{
@@ -690,7 +742,10 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
690 if (dev_priv->card_type < NV_50) 742 if (dev_priv->card_type < NV_50)
691 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem); 743 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
692 else 744 else
745 if (dev_priv->card_type < NV_C0)
693 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem); 746 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
747 else
748 ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
694 if (ret == 0) { 749 if (ret == 0) {
695 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict, 750 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
696 no_wait_reserve, 751 no_wait_reserve,
@@ -901,6 +956,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
901 case TTM_PL_VRAM: 956 case TTM_PL_VRAM:
902 { 957 {
903 struct nouveau_vram *vram = mem->mm_node; 958 struct nouveau_vram *vram = mem->mm_node;
959 u8 page_shift;
904 960
905 if (!dev_priv->bar1_vm) { 961 if (!dev_priv->bar1_vm) {
906 mem->bus.offset = mem->start << PAGE_SHIFT; 962 mem->bus.offset = mem->start << PAGE_SHIFT;
@@ -909,8 +965,14 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
909 break; 965 break;
910 } 966 }
911 967
912 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size, 12, 968 if (dev_priv->card_type == NV_C0)
913 NV_MEM_ACCESS_RW, &vram->bar_vma); 969 page_shift = vram->page_shift;
970 else
971 page_shift = 12;
972
973 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
974 page_shift, NV_MEM_ACCESS_RW,
975 &vram->bar_vma);
914 if (ret) 976 if (ret)
915 return ret; 977 return ret;
916 978
@@ -920,8 +982,9 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
920 return ret; 982 return ret;
921 } 983 }
922 984
923 mem->bus.offset = vram->bar_vma.offset; 985 mem->bus.offset = vram->bar_vma.offset;
924 mem->bus.offset -= 0x0020000000ULL; 986 if (dev_priv->card_type == NV_50) /*XXX*/
987 mem->bus.offset -= 0x0020000000ULL;
925 mem->bus.base = pci_resource_start(dev->pdev, 1); 988 mem->bus.base = pci_resource_start(dev->pdev, 1);
926 mem->bus.is_iomem = true; 989 mem->bus.is_iomem = true;
927 } 990 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 6f37995aee2d..e37977d02463 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -38,9 +38,14 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
38 int ret; 38 int ret;
39 39
40 if (dev_priv->card_type >= NV_50) { 40 if (dev_priv->card_type >= NV_50) {
41 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0, 41 if (dev_priv->card_type < NV_C0) {
42 (1ULL << 40), NV_MEM_ACCESS_RO, 42 ret = nouveau_gpuobj_dma_new(chan,
43 NV_MEM_TARGET_VM, &pushbuf); 43 NV_CLASS_DMA_IN_MEMORY, 0,
44 (1ULL << 40),
45 NV_MEM_ACCESS_RO,
46 NV_MEM_TARGET_VM,
47 &pushbuf);
48 }
44 chan->pushbuf_base = pb->bo.offset; 49 chan->pushbuf_base = pb->bo.offset;
45 } else 50 } else
46 if (pb->bo.mem.mem_type == TTM_PL_TT) { 51 if (pb->bo.mem.mem_type == TTM_PL_TT) {
@@ -71,7 +76,7 @@ nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
71 76
72 nouveau_gpuobj_ref(pushbuf, &chan->pushbuf); 77 nouveau_gpuobj_ref(pushbuf, &chan->pushbuf);
73 nouveau_gpuobj_ref(NULL, &pushbuf); 78 nouveau_gpuobj_ref(NULL, &pushbuf);
74 return 0; 79 return ret;
75} 80}
76 81
77static struct nouveau_bo * 82static struct nouveau_bo *
@@ -99,6 +104,13 @@ nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
99 return NULL; 104 return NULL;
100 } 105 }
101 106
107 ret = nouveau_bo_map(pushbuf);
108 if (ret) {
109 nouveau_bo_unpin(pushbuf);
110 nouveau_bo_ref(NULL, &pushbuf);
111 return NULL;
112 }
113
102 return pushbuf; 114 return pushbuf;
103} 115}
104 116
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index 6ff77cedc008..65699bfaaaea 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -36,7 +36,7 @@ nouveau_dma_pre_init(struct nouveau_channel *chan)
36 struct drm_nouveau_private *dev_priv = chan->dev->dev_private; 36 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
37 struct nouveau_bo *pushbuf = chan->pushbuf_bo; 37 struct nouveau_bo *pushbuf = chan->pushbuf_bo;
38 38
39 if (dev_priv->card_type == NV_50) { 39 if (dev_priv->card_type >= NV_50) {
40 const int ib_size = pushbuf->bo.mem.size / 2; 40 const int ib_size = pushbuf->bo.mem.size / 2;
41 41
42 chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2; 42 chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
@@ -61,6 +61,21 @@ nouveau_dma_init(struct nouveau_channel *chan)
61 struct drm_nouveau_private *dev_priv = dev->dev_private; 61 struct drm_nouveau_private *dev_priv = dev->dev_private;
62 int ret, i; 62 int ret, i;
63 63
64 if (dev_priv->card_type >= NV_C0) {
65 ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
66 if (ret)
67 return ret;
68
69 ret = RING_SPACE(chan, 2);
70 if (ret)
71 return ret;
72
73 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0000, 1);
74 OUT_RING (chan, 0x00009039);
75 FIRE_RING (chan);
76 return 0;
77 }
78
64 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */ 79 /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
65 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, dev_priv->card_type < NV_50 ? 80 ret = nouveau_gpuobj_gr_new(chan, NvM2MF, dev_priv->card_type < NV_50 ?
66 0x0039 : 0x5039); 81 0x0039 : 0x5039);
@@ -72,11 +87,6 @@ nouveau_dma_init(struct nouveau_channel *chan)
72 if (ret) 87 if (ret)
73 return ret; 88 return ret;
74 89
75 /* Map push buffer */
76 ret = nouveau_bo_map(chan->pushbuf_bo);
77 if (ret)
78 return ret;
79
80 /* Insert NOPS for NOUVEAU_DMA_SKIPS */ 90 /* Insert NOPS for NOUVEAU_DMA_SKIPS */
81 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 91 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
82 if (ret) 92 if (ret)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
index d578c21d3c8d..c36f1763feaa 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.h
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
@@ -77,7 +77,8 @@ enum {
77 /* G80+ display objects */ 77 /* G80+ display objects */
78 NvEvoVRAM = 0x01000000, 78 NvEvoVRAM = 0x01000000,
79 NvEvoFB16 = 0x01000001, 79 NvEvoFB16 = 0x01000001,
80 NvEvoFB32 = 0x01000002 80 NvEvoFB32 = 0x01000002,
81 NvEvoVRAM_LP = 0x01000003
81}; 82};
82 83
83#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 84#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
@@ -125,6 +126,12 @@ extern void
125OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords); 126OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);
126 127
127static inline void 128static inline void
129BEGIN_NVC0(struct nouveau_channel *chan, int op, int subc, int mthd, int size)
130{
131 OUT_RING(chan, (op << 28) | (size << 16) | (subc << 13) | (mthd >> 2));
132}
133
134static inline void
128BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size) 135BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size)
129{ 136{
130 OUT_RING(chan, (subc << 13) | (size << 18) | mthd); 137 OUT_RING(chan, (subc << 13) | (size << 18) | mthd);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 8f13906185b2..e81575687354 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -69,6 +69,7 @@ struct nouveau_vram {
69 struct drm_device *dev; 69 struct drm_device *dev;
70 70
71 struct nouveau_vma bar_vma; 71 struct nouveau_vma bar_vma;
72 u8 page_shift;
72 73
73 struct list_head regions; 74 struct list_head regions;
74 u32 memtype; 75 u32 memtype;
@@ -239,6 +240,7 @@ struct nouveau_channel {
239 /* PFIFO context */ 240 /* PFIFO context */
240 struct nouveau_gpuobj *ramfc; 241 struct nouveau_gpuobj *ramfc;
241 struct nouveau_gpuobj *cache; 242 struct nouveau_gpuobj *cache;
243 void *fifo_priv;
242 244
243 /* PGRAPH context */ 245 /* PGRAPH context */
244 /* XXX may be merge 2 pointers as private data ??? */ 246 /* XXX may be merge 2 pointers as private data ??? */
@@ -336,6 +338,7 @@ struct nouveau_fb_engine {
336}; 338};
337 339
338struct nouveau_fifo_engine { 340struct nouveau_fifo_engine {
341 void *priv;
339 int channels; 342 int channels;
340 343
341 struct nouveau_gpuobj *playlist[2]; 344 struct nouveau_gpuobj *playlist[2];
@@ -362,6 +365,7 @@ struct nouveau_pgraph_engine {
362 bool accel_blocked; 365 bool accel_blocked;
363 bool registered; 366 bool registered;
364 int grctx_size; 367 int grctx_size;
368 void *priv;
365 369
366 /* NV2x/NV3x context table (0x400780) */ 370 /* NV2x/NV3x context table (0x400780) */
367 struct nouveau_gpuobj *ctx_table; 371 struct nouveau_gpuobj *ctx_table;
@@ -841,6 +845,9 @@ extern void nv10_mem_put_tile_region(struct drm_device *dev,
841 struct nouveau_fence *fence); 845 struct nouveau_fence *fence);
842extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 846extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
843 847
848/* nvc0_vram.c */
849extern const struct ttm_mem_type_manager_func nvc0_vram_manager;
850
844/* nouveau_notifier.c */ 851/* nouveau_notifier.c */
845extern int nouveau_notifier_init_channel(struct nouveau_channel *); 852extern int nouveau_notifier_init_channel(struct nouveau_channel *);
846extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 853extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
@@ -1228,11 +1235,6 @@ extern int nvc0_instmem_init(struct drm_device *);
1228extern void nvc0_instmem_takedown(struct drm_device *); 1235extern void nvc0_instmem_takedown(struct drm_device *);
1229extern int nvc0_instmem_suspend(struct drm_device *); 1236extern int nvc0_instmem_suspend(struct drm_device *);
1230extern void nvc0_instmem_resume(struct drm_device *); 1237extern void nvc0_instmem_resume(struct drm_device *);
1231extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1232extern void nvc0_instmem_put(struct nouveau_gpuobj *);
1233extern int nvc0_instmem_map(struct nouveau_gpuobj *);
1234extern void nvc0_instmem_unmap(struct nouveau_gpuobj *);
1235extern void nvc0_instmem_flush(struct drm_device *);
1236 1238
1237/* nv04_mc.c */ 1239/* nv04_mc.c */
1238extern int nv04_mc_init(struct drm_device *); 1240extern int nv04_mc_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 9dbe1eff2ae5..6d56a54b6e2e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -68,6 +68,8 @@ nouveau_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
68 else 68 else
69 if (dev_priv->card_type < NV_C0) 69 if (dev_priv->card_type < NV_C0)
70 ret = nv50_fbcon_fillrect(info, rect); 70 ret = nv50_fbcon_fillrect(info, rect);
71 else
72 ret = nvc0_fbcon_fillrect(info, rect);
71 mutex_unlock(&dev_priv->channel->mutex); 73 mutex_unlock(&dev_priv->channel->mutex);
72 } 74 }
73 75
@@ -98,6 +100,8 @@ nouveau_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *image)
98 else 100 else
99 if (dev_priv->card_type < NV_C0) 101 if (dev_priv->card_type < NV_C0)
100 ret = nv50_fbcon_copyarea(info, image); 102 ret = nv50_fbcon_copyarea(info, image);
103 else
104 ret = nvc0_fbcon_copyarea(info, image);
101 mutex_unlock(&dev_priv->channel->mutex); 105 mutex_unlock(&dev_priv->channel->mutex);
102 } 106 }
103 107
@@ -128,6 +132,8 @@ nouveau_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
128 else 132 else
129 if (dev_priv->card_type < NV_C0) 133 if (dev_priv->card_type < NV_C0)
130 ret = nv50_fbcon_imageblit(info, image); 134 ret = nv50_fbcon_imageblit(info, image);
135 else
136 ret = nvc0_fbcon_imageblit(info, image);
131 mutex_unlock(&dev_priv->channel->mutex); 137 mutex_unlock(&dev_priv->channel->mutex);
132 } 138 }
133 139
@@ -163,10 +169,18 @@ nouveau_fbcon_sync(struct fb_info *info)
163 return 0; 169 return 0;
164 } 170 }
165 171
166 BEGIN_RING(chan, 0, 0x0104, 1); 172 if (dev_priv->card_type >= NV_C0) {
167 OUT_RING(chan, 0); 173 BEGIN_NVC0(chan, 2, NvSub2D, 0x010c, 1);
168 BEGIN_RING(chan, 0, 0x0100, 1); 174 OUT_RING (chan, 0);
169 OUT_RING(chan, 0); 175 BEGIN_NVC0(chan, 2, NvSub2D, 0x0100, 1);
176 OUT_RING (chan, 0);
177 } else {
178 BEGIN_RING(chan, 0, 0x0104, 1);
179 OUT_RING (chan, 0);
180 BEGIN_RING(chan, 0, 0x0100, 1);
181 OUT_RING (chan, 0);
182 }
183
170 nouveau_bo_wr32(chan->notifier_bo, chan->m2mf_ntfy + 3, 0xffffffff); 184 nouveau_bo_wr32(chan->notifier_bo, chan->m2mf_ntfy + 3, 0xffffffff);
171 FIRE_RING(chan); 185 FIRE_RING(chan);
172 mutex_unlock(&chan->mutex); 186 mutex_unlock(&chan->mutex);
@@ -370,6 +384,8 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev,
370 else 384 else
371 if (dev_priv->card_type < NV_C0) 385 if (dev_priv->card_type < NV_C0)
372 ret = nv50_fbcon_accel_init(info); 386 ret = nv50_fbcon_accel_init(info);
387 else
388 ret = nvc0_fbcon_accel_init(info);
373 389
374 if (ret == 0) 390 if (ret == 0)
375 info->fbops = &nouveau_fbcon_ops; 391 info->fbops = &nouveau_fbcon_ops;
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index 6b933f2c3a5b..b73c29f87fc3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -44,11 +44,17 @@ int nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region);
44int nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect); 44int nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
45int nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image); 45int nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image);
46int nv04_fbcon_accel_init(struct fb_info *info); 46int nv04_fbcon_accel_init(struct fb_info *info);
47
47int nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect); 48int nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
48int nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region); 49int nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region);
49int nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image); 50int nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image);
50int nv50_fbcon_accel_init(struct fb_info *info); 51int nv50_fbcon_accel_init(struct fb_info *info);
51 52
53int nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
54int nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region);
55int nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image);
56int nvc0_fbcon_accel_init(struct fb_info *info);
57
52void nouveau_fbcon_gpu_lockup(struct fb_info *info); 58void nouveau_fbcon_gpu_lockup(struct fb_info *info);
53 59
54int nouveau_fbcon_init(struct drm_device *dev); 60int nouveau_fbcon_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 374a9793b85f..88b2f29ca3e4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -32,7 +32,8 @@
32#include "nouveau_dma.h" 32#include "nouveau_dma.h"
33 33
34#define USE_REFCNT(dev) (nouveau_private(dev)->chipset >= 0x10) 34#define USE_REFCNT(dev) (nouveau_private(dev)->chipset >= 0x10)
35#define USE_SEMA(dev) (nouveau_private(dev)->chipset >= 0x17) 35#define USE_SEMA(dev) (nouveau_private(dev)->chipset >= 0x17 && \
36 nouveau_private(dev)->card_type < NV_C0)
36 37
37struct nouveau_fence { 38struct nouveau_fence {
38 struct nouveau_channel *channel; 39 struct nouveau_channel *channel;
@@ -139,6 +140,7 @@ nouveau_fence_emit(struct nouveau_fence *fence)
139{ 140{
140 struct nouveau_channel *chan = fence->channel; 141 struct nouveau_channel *chan = fence->channel;
141 struct drm_device *dev = chan->dev; 142 struct drm_device *dev = chan->dev;
143 struct drm_nouveau_private *dev_priv = dev->dev_private;
142 int ret; 144 int ret;
143 145
144 ret = RING_SPACE(chan, 2); 146 ret = RING_SPACE(chan, 2);
@@ -159,8 +161,15 @@ nouveau_fence_emit(struct nouveau_fence *fence)
159 list_add_tail(&fence->entry, &chan->fence.pending); 161 list_add_tail(&fence->entry, &chan->fence.pending);
160 spin_unlock(&chan->fence.lock); 162 spin_unlock(&chan->fence.lock);
161 163
162 BEGIN_RING(chan, NvSubSw, USE_REFCNT(dev) ? 0x0050 : 0x0150, 1); 164 if (USE_REFCNT(dev)) {
163 OUT_RING(chan, fence->sequence); 165 if (dev_priv->card_type < NV_C0)
166 BEGIN_RING(chan, NvSubSw, 0x0050, 1);
167 else
168 BEGIN_NVC0(chan, 2, NvSubSw, 0x0050, 1);
169 } else {
170 BEGIN_RING(chan, NvSubSw, 0x0150, 1);
171 }
172 OUT_RING (chan, fence->sequence);
164 FIRE_RING(chan); 173 FIRE_RING(chan);
165 174
166 return 0; 175 return 0;
@@ -445,11 +454,14 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
445 if (ret) 454 if (ret)
446 return ret; 455 return ret;
447 456
448 ret = RING_SPACE(chan, 2); 457 /* we leave subchannel empty for nvc0 */
449 if (ret) 458 if (dev_priv->card_type < NV_C0) {
450 return ret; 459 ret = RING_SPACE(chan, 2);
451 BEGIN_RING(chan, NvSubSw, 0, 1); 460 if (ret)
452 OUT_RING(chan, NvSw); 461 return ret;
462 BEGIN_RING(chan, NvSubSw, 0, 1);
463 OUT_RING(chan, NvSw);
464 }
453 465
454 /* Create a DMA object for the shared cross-channel sync area. */ 466 /* Create a DMA object for the shared cross-channel sync area. */
455 if (USE_SEMA(dev)) { 467 if (USE_SEMA(dev)) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 224181193a1f..69044eb104bb 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -255,9 +255,6 @@ nouveau_mem_detect(struct drm_device *dev)
255 if (dev_priv->card_type < NV_50) { 255 if (dev_priv->card_type < NV_50) {
256 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); 256 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
257 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; 257 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
258 } else {
259 dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
260 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
261 } 258 }
262 259
263 if (dev_priv->vram_size) 260 if (dev_priv->vram_size)
@@ -731,6 +728,10 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
731 if (ret) 728 if (ret)
732 return ret; 729 return ret;
733 730
731 node->page_shift = 12;
732 if (nvbo->vma.node)
733 node->page_shift = nvbo->vma.node->type;
734
734 mem->mm_node = node; 735 mem->mm_node = node;
735 mem->start = node->offset >> PAGE_SHIFT; 736 mem->start = node->offset >> PAGE_SHIFT;
736 return 0; 737 return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_mm.h b/drivers/gpu/drm/nouveau/nouveau_mm.h
index 250e642de0a7..af3844933036 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_mm.h
@@ -59,4 +59,9 @@ int nv50_vram_new(struct drm_device *, u64 size, u32 align, u32 size_nc,
59void nv50_vram_del(struct drm_device *, struct nouveau_vram **); 59void nv50_vram_del(struct drm_device *, struct nouveau_vram **);
60bool nv50_vram_flags_valid(struct drm_device *, u32 tile_flags); 60bool nv50_vram_flags_valid(struct drm_device *, u32 tile_flags);
61 61
62int nvc0_vram_init(struct drm_device *);
63int nvc0_vram_new(struct drm_device *, u64 size, u32 align, u32 ncmin,
64 u32 memtype, struct nouveau_vram **);
65bool nvc0_vram_flags_valid(struct drm_device *, u32 tile_flags);
66
62#endif 67#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c
index a050b7b69782..fe29d604b820 100644
--- a/drivers/gpu/drm/nouveau/nouveau_notifier.c
+++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c
@@ -164,10 +164,15 @@ int
164nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data, 164nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data,
165 struct drm_file *file_priv) 165 struct drm_file *file_priv)
166{ 166{
167 struct drm_nouveau_private *dev_priv = dev->dev_private;
167 struct drm_nouveau_notifierobj_alloc *na = data; 168 struct drm_nouveau_notifierobj_alloc *na = data;
168 struct nouveau_channel *chan; 169 struct nouveau_channel *chan;
169 int ret; 170 int ret;
170 171
172 /* completely unnecessary for these chipsets... */
173 if (unlikely(dev_priv->card_type >= NV_C0))
174 return -EINVAL;
175
171 chan = nouveau_channel_get(dev, file_priv, na->channel); 176 chan = nouveau_channel_get(dev, file_priv, na->channel);
172 if (IS_ERR(chan)) 177 if (IS_ERR(chan))
173 return PTR_ERR(chan); 178 return PTR_ERR(chan);
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 55c9fdcfa67f..d77b1fcd19d4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -643,10 +643,13 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
643found: 643found:
644 switch (oc->engine) { 644 switch (oc->engine) {
645 case NVOBJ_ENGINE_SW: 645 case NVOBJ_ENGINE_SW:
646 ret = nouveau_gpuobj_sw_new(chan, class, &gpuobj); 646 if (dev_priv->card_type < NV_C0) {
647 if (ret) 647 ret = nouveau_gpuobj_sw_new(chan, class, &gpuobj);
648 return ret; 648 if (ret)
649 goto insert; 649 return ret;
650 goto insert;
651 }
652 break;
650 case NVOBJ_ENGINE_GR: 653 case NVOBJ_ENGINE_GR:
651 if (dev_priv->card_type >= NV_50 && !chan->ramin_grctx) { 654 if (dev_priv->card_type >= NV_50 && !chan->ramin_grctx) {
652 struct nouveau_pgraph_engine *pgraph = 655 struct nouveau_pgraph_engine *pgraph =
@@ -669,6 +672,10 @@ found:
669 break; 672 break;
670 } 673 }
671 674
675 /* we're done if this is fermi */
676 if (dev_priv->card_type >= NV_C0)
677 return 0;
678
672 ret = nouveau_gpuobj_new(dev, chan, 679 ret = nouveau_gpuobj_new(dev, chan,
673 nouveau_gpuobj_class_instmem_size(dev, class), 680 nouveau_gpuobj_class_instmem_size(dev, class),
674 16, 681 16,
@@ -772,6 +779,25 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
772 779
773 NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); 780 NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
774 781
782 if (dev_priv->card_type == NV_C0) {
783 struct nouveau_vm *vm = dev_priv->chan_vm;
784 struct nouveau_vm_pgd *vpgd;
785
786 ret = nouveau_gpuobj_new(dev, NULL, 4096, 0x1000, 0,
787 &chan->ramin);
788 if (ret)
789 return ret;
790
791 nouveau_vm_ref(vm, &chan->vm, NULL);
792
793 vpgd = list_first_entry(&vm->pgd_list, struct nouveau_vm_pgd, head);
794 nv_wo32(chan->ramin, 0x0200, lower_32_bits(vpgd->obj->vinst));
795 nv_wo32(chan->ramin, 0x0204, upper_32_bits(vpgd->obj->vinst));
796 nv_wo32(chan->ramin, 0x0208, 0xffffffff);
797 nv_wo32(chan->ramin, 0x020c, 0x000000ff);
798 return 0;
799 }
800
775 /* Allocate a chunk of memory for per-channel object storage */ 801 /* Allocate a chunk of memory for per-channel object storage */
776 ret = nouveau_gpuobj_channel_init_pramin(chan); 802 ret = nouveau_gpuobj_channel_init_pramin(chan);
777 if (ret) { 803 if (ret) {
@@ -779,7 +805,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
779 return ret; 805 return ret;
780 } 806 }
781 807
782 /* NV50/NVC0 VM 808 /* NV50 VM
783 * - Allocate per-channel page-directory 809 * - Allocate per-channel page-directory
784 * - Link with shared channel VM 810 * - Link with shared channel VM
785 */ 811 */
@@ -877,9 +903,6 @@ nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
877 903
878 NV_DEBUG(dev, "ch%d\n", chan->id); 904 NV_DEBUG(dev, "ch%d\n", chan->id);
879 905
880 if (!chan->ramht)
881 return;
882
883 nouveau_ramht_ref(NULL, &chan->ramht, chan); 906 nouveau_ramht_ref(NULL, &chan->ramht, chan);
884 907
885 nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd); 908 nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 8eac943e8fd2..d5b17b6ccd3a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -464,11 +464,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
464 engine->instmem.takedown = nvc0_instmem_takedown; 464 engine->instmem.takedown = nvc0_instmem_takedown;
465 engine->instmem.suspend = nvc0_instmem_suspend; 465 engine->instmem.suspend = nvc0_instmem_suspend;
466 engine->instmem.resume = nvc0_instmem_resume; 466 engine->instmem.resume = nvc0_instmem_resume;
467 engine->instmem.get = nvc0_instmem_get; 467 engine->instmem.get = nv50_instmem_get;
468 engine->instmem.put = nvc0_instmem_put; 468 engine->instmem.put = nv50_instmem_put;
469 engine->instmem.map = nvc0_instmem_map; 469 engine->instmem.map = nv50_instmem_map;
470 engine->instmem.unmap = nvc0_instmem_unmap; 470 engine->instmem.unmap = nv50_instmem_unmap;
471 engine->instmem.flush = nvc0_instmem_flush; 471 engine->instmem.flush = nv84_instmem_flush;
472 engine->mc.init = nv50_mc_init; 472 engine->mc.init = nv50_mc_init;
473 engine->mc.takedown = nv50_mc_takedown; 473 engine->mc.takedown = nv50_mc_takedown;
474 engine->timer.init = nv04_timer_init; 474 engine->timer.init = nv04_timer_init;
@@ -509,8 +509,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
509 engine->gpio.irq_enable = nv50_gpio_irq_enable; 509 engine->gpio.irq_enable = nv50_gpio_irq_enable;
510 engine->crypt.init = nouveau_stub_init; 510 engine->crypt.init = nouveau_stub_init;
511 engine->crypt.takedown = nouveau_stub_takedown; 511 engine->crypt.takedown = nouveau_stub_takedown;
512 engine->vram.init = nouveau_mem_detect; 512 engine->vram.init = nvc0_vram_init;
513 engine->vram.flags_valid = nouveau_mem_flags_valid; 513 engine->vram.get = nvc0_vram_new;
514 engine->vram.put = nv50_vram_del;
515 engine->vram.flags_valid = nvc0_vram_flags_valid;
514 break; 516 break;
515 default: 517 default:
516 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); 518 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
@@ -550,6 +552,10 @@ nouveau_card_init_channel(struct drm_device *dev)
550 if (ret) 552 if (ret)
551 return ret; 553 return ret;
552 554
555 /* no dma objects on fermi... */
556 if (dev_priv->card_type >= NV_C0)
557 goto out_done;
558
553 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY, 559 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
554 0, dev_priv->vram_size, 560 0, dev_priv->vram_size,
555 NV_MEM_ACCESS_RW, NV_MEM_TARGET_VRAM, 561 NV_MEM_ACCESS_RW, NV_MEM_TARGET_VRAM,
@@ -574,6 +580,7 @@ nouveau_card_init_channel(struct drm_device *dev)
574 if (ret) 580 if (ret)
575 goto out_err; 581 goto out_err;
576 582
583out_done:
577 mutex_unlock(&dev_priv->channel->mutex); 584 mutex_unlock(&dev_priv->channel->mutex);
578 return 0; 585 return 0;
579 586
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.c b/drivers/gpu/drm/nouveau/nouveau_vm.c
index 07ab1749cf7d..97d82aedf86b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_vm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_vm.c
@@ -32,6 +32,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_vram *vram)
32{ 32{
33 struct nouveau_vm *vm = vma->vm; 33 struct nouveau_vm *vm = vma->vm;
34 struct nouveau_mm_node *r; 34 struct nouveau_mm_node *r;
35 int big = vma->node->type != vm->spg_shift;
35 u32 offset = vma->node->offset + (delta >> 12); 36 u32 offset = vma->node->offset + (delta >> 12);
36 u32 bits = vma->node->type - 12; 37 u32 bits = vma->node->type - 12;
37 u32 pde = (offset >> vm->pgt_bits) - vm->fpde; 38 u32 pde = (offset >> vm->pgt_bits) - vm->fpde;
@@ -44,7 +45,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_vram *vram)
44 u32 num = r->length >> bits; 45 u32 num = r->length >> bits;
45 46
46 while (num) { 47 while (num) {
47 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj; 48 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
48 49
49 end = (pte + num); 50 end = (pte + num);
50 if (unlikely(end >= max)) 51 if (unlikely(end >= max))
@@ -76,6 +77,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
76 dma_addr_t *list) 77 dma_addr_t *list)
77{ 78{
78 struct nouveau_vm *vm = vma->vm; 79 struct nouveau_vm *vm = vma->vm;
80 int big = vma->node->type != vm->spg_shift;
79 u32 offset = vma->node->offset + (delta >> 12); 81 u32 offset = vma->node->offset + (delta >> 12);
80 u32 bits = vma->node->type - 12; 82 u32 bits = vma->node->type - 12;
81 u32 num = length >> vma->node->type; 83 u32 num = length >> vma->node->type;
@@ -85,7 +87,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
85 u32 end, len; 87 u32 end, len;
86 88
87 while (num) { 89 while (num) {
88 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj; 90 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
89 91
90 end = (pte + num); 92 end = (pte + num);
91 if (unlikely(end >= max)) 93 if (unlikely(end >= max))
@@ -110,6 +112,7 @@ void
110nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) 112nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
111{ 113{
112 struct nouveau_vm *vm = vma->vm; 114 struct nouveau_vm *vm = vma->vm;
115 int big = vma->node->type != vm->spg_shift;
113 u32 offset = vma->node->offset + (delta >> 12); 116 u32 offset = vma->node->offset + (delta >> 12);
114 u32 bits = vma->node->type - 12; 117 u32 bits = vma->node->type - 12;
115 u32 num = length >> vma->node->type; 118 u32 num = length >> vma->node->type;
@@ -119,7 +122,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
119 u32 end, len; 122 u32 end, len;
120 123
121 while (num) { 124 while (num) {
122 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj; 125 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big];
123 126
124 end = (pte + num); 127 end = (pte + num);
125 if (unlikely(end >= max)) 128 if (unlikely(end >= max))
@@ -146,7 +149,7 @@ nouveau_vm_unmap(struct nouveau_vma *vma)
146} 149}
147 150
148static void 151static void
149nouveau_vm_unmap_pgt(struct nouveau_vm *vm, u32 fpde, u32 lpde) 152nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
150{ 153{
151 struct nouveau_vm_pgd *vpgd; 154 struct nouveau_vm_pgd *vpgd;
152 struct nouveau_vm_pgt *vpgt; 155 struct nouveau_vm_pgt *vpgt;
@@ -155,16 +158,16 @@ nouveau_vm_unmap_pgt(struct nouveau_vm *vm, u32 fpde, u32 lpde)
155 158
156 for (pde = fpde; pde <= lpde; pde++) { 159 for (pde = fpde; pde <= lpde; pde++) {
157 vpgt = &vm->pgt[pde - vm->fpde]; 160 vpgt = &vm->pgt[pde - vm->fpde];
158 if (--vpgt->refcount) 161 if (--vpgt->refcount[big])
159 continue; 162 continue;
160 163
164 pgt = vpgt->obj[big];
165 vpgt->obj[big] = NULL;
166
161 list_for_each_entry(vpgd, &vm->pgd_list, head) { 167 list_for_each_entry(vpgd, &vm->pgd_list, head) {
162 vm->unmap_pgt(vpgd->obj, pde); 168 vm->map_pgt(vpgd->obj, pde, vpgt->obj);
163 } 169 }
164 170
165 pgt = vpgt->obj;
166 vpgt->obj = NULL;
167
168 mutex_unlock(&vm->mm->mutex); 171 mutex_unlock(&vm->mm->mutex);
169 nouveau_gpuobj_ref(NULL, &pgt); 172 nouveau_gpuobj_ref(NULL, &pgt);
170 mutex_lock(&vm->mm->mutex); 173 mutex_lock(&vm->mm->mutex);
@@ -177,6 +180,7 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
177 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; 180 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
178 struct nouveau_vm_pgd *vpgd; 181 struct nouveau_vm_pgd *vpgd;
179 struct nouveau_gpuobj *pgt; 182 struct nouveau_gpuobj *pgt;
183 int big = (type != vm->spg_shift);
180 u32 pgt_size; 184 u32 pgt_size;
181 int ret; 185 int ret;
182 186
@@ -191,19 +195,18 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
191 return ret; 195 return ret;
192 196
193 /* someone beat us to filling the PDE while we didn't have the lock */ 197 /* someone beat us to filling the PDE while we didn't have the lock */
194 if (unlikely(vpgt->refcount++)) { 198 if (unlikely(vpgt->refcount[big]++)) {
195 mutex_unlock(&vm->mm->mutex); 199 mutex_unlock(&vm->mm->mutex);
196 nouveau_gpuobj_ref(NULL, &pgt); 200 nouveau_gpuobj_ref(NULL, &pgt);
197 mutex_lock(&vm->mm->mutex); 201 mutex_lock(&vm->mm->mutex);
198 return 0; 202 return 0;
199 } 203 }
200 204
205 vpgt->obj[big] = pgt;
201 list_for_each_entry(vpgd, &vm->pgd_list, head) { 206 list_for_each_entry(vpgd, &vm->pgd_list, head) {
202 vm->map_pgt(vpgd->obj, type, pde, pgt); 207 vm->map_pgt(vpgd->obj, pde, vpgt->obj);
203 } 208 }
204 209
205 vpgt->page_shift = type;
206 vpgt->obj = pgt;
207 return 0; 210 return 0;
208} 211}
209 212
@@ -227,16 +230,17 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
227 lpde = (vma->node->offset + vma->node->length - 1) >> vm->pgt_bits; 230 lpde = (vma->node->offset + vma->node->length - 1) >> vm->pgt_bits;
228 for (pde = fpde; pde <= lpde; pde++) { 231 for (pde = fpde; pde <= lpde; pde++) {
229 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; 232 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
233 int big = (vma->node->type != vm->spg_shift);
230 234
231 if (likely(vpgt->refcount)) { 235 if (likely(vpgt->refcount[big])) {
232 vpgt->refcount++; 236 vpgt->refcount[big]++;
233 continue; 237 continue;
234 } 238 }
235 239
236 ret = nouveau_vm_map_pgt(vm, pde, vma->node->type); 240 ret = nouveau_vm_map_pgt(vm, pde, vma->node->type);
237 if (ret) { 241 if (ret) {
238 if (pde != fpde) 242 if (pde != fpde)
239 nouveau_vm_unmap_pgt(vm, fpde, pde - 1); 243 nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1);
240 nouveau_mm_put(vm->mm, vma->node); 244 nouveau_mm_put(vm->mm, vma->node);
241 mutex_unlock(&vm->mm->mutex); 245 mutex_unlock(&vm->mm->mutex);
242 vma->node = NULL; 246 vma->node = NULL;
@@ -263,21 +267,20 @@ nouveau_vm_put(struct nouveau_vma *vma)
263 lpde = (vma->node->offset + vma->node->length - 1) >> vm->pgt_bits; 267 lpde = (vma->node->offset + vma->node->length - 1) >> vm->pgt_bits;
264 268
265 mutex_lock(&vm->mm->mutex); 269 mutex_lock(&vm->mm->mutex);
270 nouveau_vm_unmap_pgt(vm, vma->node->type != vm->spg_shift, fpde, lpde);
266 nouveau_mm_put(vm->mm, vma->node); 271 nouveau_mm_put(vm->mm, vma->node);
267 vma->node = NULL; 272 vma->node = NULL;
268 nouveau_vm_unmap_pgt(vm, fpde, lpde);
269 mutex_unlock(&vm->mm->mutex); 273 mutex_unlock(&vm->mm->mutex);
270} 274}
271 275
272int 276int
273nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset, 277nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset,
274 u8 pgt_bits, u8 spg_shift, u8 lpg_shift,
275 struct nouveau_vm **pvm) 278 struct nouveau_vm **pvm)
276{ 279{
277 struct drm_nouveau_private *dev_priv = dev->dev_private; 280 struct drm_nouveau_private *dev_priv = dev->dev_private;
278 struct nouveau_vm *vm; 281 struct nouveau_vm *vm;
279 u64 mm_length = (offset + length) - mm_offset; 282 u64 mm_length = (offset + length) - mm_offset;
280 u32 block; 283 u32 block, pgt_bits;
281 int ret; 284 int ret;
282 285
283 vm = kzalloc(sizeof(*vm), GFP_KERNEL); 286 vm = kzalloc(sizeof(*vm), GFP_KERNEL);
@@ -286,11 +289,40 @@ nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset,
286 289
287 if (dev_priv->card_type == NV_50) { 290 if (dev_priv->card_type == NV_50) {
288 vm->map_pgt = nv50_vm_map_pgt; 291 vm->map_pgt = nv50_vm_map_pgt;
289 vm->unmap_pgt = nv50_vm_unmap_pgt;
290 vm->map = nv50_vm_map; 292 vm->map = nv50_vm_map;
291 vm->map_sg = nv50_vm_map_sg; 293 vm->map_sg = nv50_vm_map_sg;
292 vm->unmap = nv50_vm_unmap; 294 vm->unmap = nv50_vm_unmap;
293 vm->flush = nv50_vm_flush; 295 vm->flush = nv50_vm_flush;
296 vm->spg_shift = 12;
297 vm->lpg_shift = 16;
298
299 pgt_bits = 29;
300 block = (1 << pgt_bits);
301 if (length < block)
302 block = length;
303
304 } else
305 if (dev_priv->card_type == NV_C0) {
306 vm->map_pgt = nvc0_vm_map_pgt;
307 vm->map = nvc0_vm_map;
308 vm->map_sg = nvc0_vm_map_sg;
309 vm->unmap = nvc0_vm_unmap;
310 vm->flush = nvc0_vm_flush;
311 vm->spg_shift = 12;
312 vm->lpg_shift = 17;
313 pgt_bits = 27;
314
315 /* Should be 4096 everywhere, this is a hack that's
316 * currently necessary to avoid an elusive bug that
317 * causes corruption when mixing small/large pages
318 */
319 if (length < (1ULL << 40))
320 block = 4096;
321 else {
322 block = (1 << pgt_bits);
323 if (length < block)
324 block = length;
325 }
294 } else { 326 } else {
295 kfree(vm); 327 kfree(vm);
296 return -ENOSYS; 328 return -ENOSYS;
@@ -308,12 +340,6 @@ nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset,
308 vm->dev = dev; 340 vm->dev = dev;
309 vm->refcount = 1; 341 vm->refcount = 1;
310 vm->pgt_bits = pgt_bits - 12; 342 vm->pgt_bits = pgt_bits - 12;
311 vm->spg_shift = spg_shift;
312 vm->lpg_shift = lpg_shift;
313
314 block = (1 << pgt_bits);
315 if (length < block)
316 block = length;
317 343
318 ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, 344 ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
319 block >> 12); 345 block >> 12);
@@ -342,16 +368,8 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
342 nouveau_gpuobj_ref(pgd, &vpgd->obj); 368 nouveau_gpuobj_ref(pgd, &vpgd->obj);
343 369
344 mutex_lock(&vm->mm->mutex); 370 mutex_lock(&vm->mm->mutex);
345 for (i = vm->fpde; i <= vm->lpde; i++) { 371 for (i = vm->fpde; i <= vm->lpde; i++)
346 struct nouveau_vm_pgt *vpgt = &vm->pgt[i - vm->fpde]; 372 vm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
347
348 if (!vpgt->obj) {
349 vm->unmap_pgt(pgd, i);
350 continue;
351 }
352
353 vm->map_pgt(pgd, vpgt->page_shift, i, vpgt->obj);
354 }
355 list_add(&vpgd->head, &vm->pgd_list); 373 list_add(&vpgd->head, &vm->pgd_list);
356 mutex_unlock(&vm->mm->mutex); 374 mutex_unlock(&vm->mm->mutex);
357 return 0; 375 return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.h b/drivers/gpu/drm/nouveau/nouveau_vm.h
index b6755cfa7b71..e1193515771b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_vm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_vm.h
@@ -31,9 +31,8 @@
31#include "nouveau_mm.h" 31#include "nouveau_mm.h"
32 32
33struct nouveau_vm_pgt { 33struct nouveau_vm_pgt {
34 struct nouveau_gpuobj *obj; 34 struct nouveau_gpuobj *obj[2];
35 u32 page_shift; 35 u32 refcount[2];
36 u32 refcount;
37}; 36};
38 37
39struct nouveau_vm_pgd { 38struct nouveau_vm_pgd {
@@ -65,9 +64,8 @@ struct nouveau_vm {
65 u8 spg_shift; 64 u8 spg_shift;
66 u8 lpg_shift; 65 u8 lpg_shift;
67 66
68 void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 type, u32 pde, 67 void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
69 struct nouveau_gpuobj *pgt); 68 struct nouveau_gpuobj *pgt[2]);
70 void (*unmap_pgt)(struct nouveau_gpuobj *pgd, u32 pde);
71 void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, 69 void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *,
72 struct nouveau_vram *, u32 pte, u32 cnt, u64 phys); 70 struct nouveau_vram *, u32 pte, u32 cnt, u64 phys);
73 void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, 71 void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *,
@@ -78,7 +76,6 @@ struct nouveau_vm {
78 76
79/* nouveau_vm.c */ 77/* nouveau_vm.c */
80int nouveau_vm_new(struct drm_device *, u64 offset, u64 length, u64 mm_offset, 78int nouveau_vm_new(struct drm_device *, u64 offset, u64 length, u64 mm_offset,
81 u8 pgt_bits, u8 spg_shift, u8 lpg_shift,
82 struct nouveau_vm **); 79 struct nouveau_vm **);
83int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, 80int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **,
84 struct nouveau_gpuobj *pgd); 81 struct nouveau_gpuobj *pgd);
@@ -93,9 +90,8 @@ void nouveau_vm_map_sg(struct nouveau_vma *, u64 offset, u64 length,
93 dma_addr_t *); 90 dma_addr_t *);
94 91
95/* nv50_vm.c */ 92/* nv50_vm.c */
96void nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 type, u32 pde, 93void nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
97 struct nouveau_gpuobj *pgt); 94 struct nouveau_gpuobj *pgt[2]);
98void nv50_vm_unmap_pgt(struct nouveau_gpuobj *pgd, u32 pde);
99void nv50_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *, 95void nv50_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *,
100 struct nouveau_vram *, u32 pte, u32 cnt, u64 phys); 96 struct nouveau_vram *, u32 pte, u32 cnt, u64 phys);
101void nv50_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *, 97void nv50_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *,
@@ -104,4 +100,14 @@ void nv50_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
104void nv50_vm_flush(struct nouveau_vm *); 100void nv50_vm_flush(struct nouveau_vm *);
105void nv50_vm_flush_engine(struct drm_device *, int engine); 101void nv50_vm_flush_engine(struct drm_device *, int engine);
106 102
103/* nvc0_vm.c */
104void nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
105 struct nouveau_gpuobj *pgt[2]);
106void nvc0_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *,
107 struct nouveau_vram *, u32 pte, u32 cnt, u64 phys);
108void nvc0_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *,
109 u32 pte, dma_addr_t *, u32 cnt);
110void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
111void nvc0_vm_flush(struct nouveau_vm *);
112
107#endif 113#endif
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index 2c346f797285..9023c4dbb449 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -115,15 +115,16 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
115 OUT_RING(evo, 0); 115 OUT_RING(evo, 0);
116 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); 116 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
117 if (dev_priv->chipset != 0x50) 117 if (dev_priv->chipset != 0x50)
118 if (nv_crtc->fb.tile_flags == 0x7a00) 118 if (nv_crtc->fb.tile_flags == 0x7a00 ||
119 nv_crtc->fb.tile_flags == 0xfe00)
119 OUT_RING(evo, NvEvoFB32); 120 OUT_RING(evo, NvEvoFB32);
120 else 121 else
121 if (nv_crtc->fb.tile_flags == 0x7000) 122 if (nv_crtc->fb.tile_flags == 0x7000)
122 OUT_RING(evo, NvEvoFB16); 123 OUT_RING(evo, NvEvoFB16);
123 else 124 else
124 OUT_RING(evo, NvEvoVRAM); 125 OUT_RING(evo, NvEvoVRAM_LP);
125 else 126 else
126 OUT_RING(evo, NvEvoVRAM); 127 OUT_RING(evo, NvEvoVRAM_LP);
127 } 128 }
128 129
129 nv_crtc->fb.blanked = blanked; 130 nv_crtc->fb.blanked = blanked;
@@ -555,13 +556,14 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
555 return ret; 556 return ret;
556 557
557 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1); 558 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
558 if (nv_crtc->fb.tile_flags == 0x7a00) 559 if (nv_crtc->fb.tile_flags == 0x7a00 ||
560 nv_crtc->fb.tile_flags == 0xfe00)
559 OUT_RING(evo, NvEvoFB32); 561 OUT_RING(evo, NvEvoFB32);
560 else 562 else
561 if (nv_crtc->fb.tile_flags == 0x7000) 563 if (nv_crtc->fb.tile_flags == 0x7000)
562 OUT_RING(evo, NvEvoFB16); 564 OUT_RING(evo, NvEvoFB16);
563 else 565 else
564 OUT_RING(evo, NvEvoVRAM); 566 OUT_RING(evo, NvEvoVRAM_LP);
565 } 567 }
566 568
567 ret = RING_SPACE(evo, 12); 569 ret = RING_SPACE(evo, 12);
@@ -575,8 +577,10 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
575 if (!nv_crtc->fb.tile_flags) { 577 if (!nv_crtc->fb.tile_flags) {
576 OUT_RING(evo, drm_fb->pitch | (1 << 20)); 578 OUT_RING(evo, drm_fb->pitch | (1 << 20));
577 } else { 579 } else {
578 OUT_RING(evo, ((drm_fb->pitch / 4) << 4) | 580 u32 tile_mode = fb->nvbo->tile_mode;
579 fb->nvbo->tile_mode); 581 if (dev_priv->card_type >= NV_C0)
582 tile_mode >>= 4;
583 OUT_RING(evo, ((drm_fb->pitch / 4) << 4) | tile_mode);
580 } 584 }
581 if (dev_priv->chipset == 0x50) 585 if (dev_priv->chipset == 0x50)
582 OUT_RING(evo, (nv_crtc->fb.tile_flags << 8) | format); 586 OUT_RING(evo, (nv_crtc->fb.tile_flags << 8) | format);
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
index 887b2a97e2a2..14e24e906ee8 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.c
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -53,7 +53,8 @@ nv50_evo_channel_del(struct nouveau_channel **pevo)
53 53
54int 54int
55nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name, 55nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
56 u32 tile_flags, u32 magic_flags, u32 offset, u32 limit) 56 u32 tile_flags, u32 magic_flags, u32 offset, u32 limit,
57 u32 flags5)
57{ 58{
58 struct drm_nouveau_private *dev_priv = evo->dev->dev_private; 59 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
59 struct drm_device *dev = evo->dev; 60 struct drm_device *dev = evo->dev;
@@ -70,10 +71,7 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
70 nv_wo32(obj, 8, offset); 71 nv_wo32(obj, 8, offset);
71 nv_wo32(obj, 12, 0x00000000); 72 nv_wo32(obj, 12, 0x00000000);
72 nv_wo32(obj, 16, 0x00000000); 73 nv_wo32(obj, 16, 0x00000000);
73 if (dev_priv->card_type < NV_C0) 74 nv_wo32(obj, 20, flags5);
74 nv_wo32(obj, 20, 0x00010000);
75 else
76 nv_wo32(obj, 20, 0x00020000);
77 dev_priv->engine.instmem.flush(dev); 75 dev_priv->engine.instmem.flush(dev);
78 76
79 ret = nouveau_ramht_insert(evo, name, obj); 77 ret = nouveau_ramht_insert(evo, name, obj);
@@ -264,9 +262,31 @@ nv50_evo_create(struct drm_device *dev)
264 } 262 }
265 263
266 /* create some default objects for the scanout memtypes we support */ 264 /* create some default objects for the scanout memtypes we support */
265 if (dev_priv->card_type >= NV_C0) {
266 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0xfe, 0x19,
267 0, 0xffffffff, 0x00000000);
268 if (ret) {
269 nv50_evo_channel_del(&dev_priv->evo);
270 return ret;
271 }
272
273 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
274 0, dev_priv->vram_size, 0x00020000);
275 if (ret) {
276 nv50_evo_channel_del(&dev_priv->evo);
277 return ret;
278 }
279
280 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
281 0, dev_priv->vram_size, 0x00000000);
282 if (ret) {
283 nv50_evo_channel_del(&dev_priv->evo);
284 return ret;
285 }
286 } else
267 if (dev_priv->chipset != 0x50) { 287 if (dev_priv->chipset != 0x50) {
268 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19, 288 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
269 0, 0xffffffff); 289 0, 0xffffffff, 0x00010000);
270 if (ret) { 290 if (ret) {
271 nv50_evo_channel_del(&dev_priv->evo); 291 nv50_evo_channel_del(&dev_priv->evo);
272 return ret; 292 return ret;
@@ -274,18 +294,25 @@ nv50_evo_create(struct drm_device *dev)
274 294
275 295
276 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19, 296 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
277 0, 0xffffffff); 297 0, 0xffffffff, 0x00010000);
278 if (ret) { 298 if (ret) {
279 nv50_evo_channel_del(&dev_priv->evo); 299 nv50_evo_channel_del(&dev_priv->evo);
280 return ret; 300 return ret;
281 } 301 }
282 }
283 302
284 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19, 303 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
285 0, dev_priv->vram_size); 304 0, dev_priv->vram_size, 0x00010000);
286 if (ret) { 305 if (ret) {
287 nv50_evo_channel_del(&dev_priv->evo); 306 nv50_evo_channel_del(&dev_priv->evo);
288 return ret; 307 return ret;
308 }
309
310 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
311 0, dev_priv->vram_size, 0x00010000);
312 if (ret) {
313 nv50_evo_channel_del(&dev_priv->evo);
314 return ret;
315 }
289 } 316 }
290 317
291 return 0; 318 return 0;
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index 6d38cb1488ae..791ded1c5c6d 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -1,3 +1,27 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
1#include "drmP.h" 25#include "drmP.h"
2#include "nouveau_drv.h" 26#include "nouveau_drv.h"
3#include "nouveau_dma.h" 27#include "nouveau_dma.h"
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index adac4da98f7e..2e1b1cd19a4b 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -151,20 +151,19 @@ nv50_instmem_init(struct drm_device *dev)
151 151
152 /* BAR3 */ 152 /* BAR3 */
153 ret = nouveau_vm_new(dev, BAR3_VM_BASE, BAR3_VM_SIZE, BAR3_VM_BASE, 153 ret = nouveau_vm_new(dev, BAR3_VM_BASE, BAR3_VM_SIZE, BAR3_VM_BASE,
154 29, 12, 16, &dev_priv->bar3_vm); 154 &dev_priv->bar3_vm);
155 if (ret) 155 if (ret)
156 goto error; 156 goto error;
157 157
158 ret = nouveau_gpuobj_new(dev, NULL, (BAR3_VM_SIZE >> 12) * 8, 158 ret = nouveau_gpuobj_new(dev, NULL, (BAR3_VM_SIZE >> 12) * 8,
159 0x1000, NVOBJ_FLAG_DONT_MAP | 159 0x1000, NVOBJ_FLAG_DONT_MAP |
160 NVOBJ_FLAG_ZERO_ALLOC, 160 NVOBJ_FLAG_ZERO_ALLOC,
161 &dev_priv->bar3_vm->pgt[0].obj); 161 &dev_priv->bar3_vm->pgt[0].obj[0]);
162 if (ret) 162 if (ret)
163 goto error; 163 goto error;
164 dev_priv->bar3_vm->pgt[0].page_shift = 12; 164 dev_priv->bar3_vm->pgt[0].refcount[0] = 1;
165 dev_priv->bar3_vm->pgt[0].refcount = 1;
166 165
167 nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj); 166 nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj[0]);
168 167
169 ret = nv50_channel_new(dev, 128 * 1024, dev_priv->bar3_vm, &chan); 168 ret = nv50_channel_new(dev, 128 * 1024, dev_priv->bar3_vm, &chan);
170 if (ret) 169 if (ret)
@@ -195,8 +194,7 @@ nv50_instmem_init(struct drm_device *dev)
195 nv_wo32(chan->ramin, 0, tmp); 194 nv_wo32(chan->ramin, 0, tmp);
196 195
197 /* BAR1 */ 196 /* BAR1 */
198 ret = nouveau_vm_new(dev, BAR1_VM_BASE, BAR1_VM_SIZE, BAR1_VM_BASE, 197 ret = nouveau_vm_new(dev, BAR1_VM_BASE, BAR1_VM_SIZE, BAR1_VM_BASE, &vm);
199 29, 12, 16, &vm);
200 if (ret) 198 if (ret)
201 goto error; 199 goto error;
202 200
@@ -220,7 +218,7 @@ nv50_instmem_init(struct drm_device *dev)
220 * to catch "NULL pointer" references 218 * to catch "NULL pointer" references
221 */ 219 */
222 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL, 220 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
223 29, 12, 16, &dev_priv->chan_vm); 221 &dev_priv->chan_vm);
224 if (ret) 222 if (ret)
225 return ret; 223 return ret;
226 224
@@ -258,7 +256,7 @@ nv50_instmem_takedown(struct drm_device *dev)
258 dev_priv->channels.ptr[127] = 0; 256 dev_priv->channels.ptr[127] = 0;
259 nv50_channel_del(&dev_priv->channels.ptr[0]); 257 nv50_channel_del(&dev_priv->channels.ptr[0]);
260 258
261 nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj); 259 nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj[0]);
262 nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL); 260 nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL);
263 261
264 if (dev_priv->ramin_heap.free_stack.next) 262 if (dev_priv->ramin_heap.free_stack.next)
diff --git a/drivers/gpu/drm/nouveau/nv50_vm.c b/drivers/gpu/drm/nouveau/nv50_vm.c
index eebab95f59b2..38e523e10995 100644
--- a/drivers/gpu/drm/nouveau/nv50_vm.c
+++ b/drivers/gpu/drm/nouveau/nv50_vm.c
@@ -28,39 +28,40 @@
28#include "nouveau_vm.h" 28#include "nouveau_vm.h"
29 29
30void 30void
31nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 type, u32 pde, 31nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
32 struct nouveau_gpuobj *pgt) 32 struct nouveau_gpuobj *pgt[2])
33{ 33{
34 struct drm_nouveau_private *dev_priv = pgd->dev->dev_private; 34 struct drm_nouveau_private *dev_priv = pgd->dev->dev_private;
35 u32 coverage = (pgt->size >> 3) << type; 35 u64 phys = 0xdeadcafe00000000ULL;
36 u64 phys; 36 u32 coverage = 0;
37 37
38 phys = pgt->vinst; 38 if (pgt[0]) {
39 phys |= 0x01; /* present */ 39 phys = 0x00000003 | pgt[0]->vinst; /* present, 4KiB pages */
40 phys |= (type == 12) ? 0x02 : 0x00; /* 4KiB pages */ 40 coverage = (pgt[0]->size >> 3) << 12;
41 if (dev_priv->vram_sys_base) { 41 } else
42 phys += dev_priv->vram_sys_base; 42 if (pgt[1]) {
43 phys |= 0x30; 43 phys = 0x00000001 | pgt[1]->vinst; /* present */
44 coverage = (pgt[1]->size >> 3) << 16;
44 } 45 }
45 46
46 if (coverage <= 32 * 1024 * 1024) 47 if (phys & 1) {
47 phys |= 0x60; 48 if (dev_priv->vram_sys_base) {
48 else if (coverage <= 64 * 1024 * 1024) 49 phys += dev_priv->vram_sys_base;
49 phys |= 0x40; 50 phys |= 0x30;
50 else if (coverage < 128 * 1024 * 1024) 51 }
51 phys |= 0x20; 52
53 if (coverage <= 32 * 1024 * 1024)
54 phys |= 0x60;
55 else if (coverage <= 64 * 1024 * 1024)
56 phys |= 0x40;
57 else if (coverage < 128 * 1024 * 1024)
58 phys |= 0x20;
59 }
52 60
53 nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); 61 nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
54 nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); 62 nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
55} 63}
56 64
57void
58nv50_vm_unmap_pgt(struct nouveau_gpuobj *pgd, u32 pde)
59{
60 nv_wo32(pgd, (pde * 8) + 0, 0x00000000);
61 nv_wo32(pgd, (pde * 8) + 4, 0xdeadcafe);
62}
63
64static inline u64 65static inline u64
65nv50_vm_addr(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 66nv50_vm_addr(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
66 u64 phys, u32 memtype, u32 target) 67 u64 phys, u32 memtype, u32 target)
@@ -91,7 +92,8 @@ void
91nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 92nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
92 struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys) 93 struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
93{ 94{
94 u32 block, i; 95 u32 block;
96 int i;
95 97
96 phys = nv50_vm_addr(vma, pgt, phys, mem->memtype, 0); 98 phys = nv50_vm_addr(vma, pgt, phys, mem->memtype, 0);
97 pte <<= 3; 99 pte <<= 3;
diff --git a/drivers/gpu/drm/nouveau/nv50_vram.c b/drivers/gpu/drm/nouveau/nv50_vram.c
index 47489ed0a5a8..58e98ad36347 100644
--- a/drivers/gpu/drm/nouveau/nv50_vram.c
+++ b/drivers/gpu/drm/nouveau/nv50_vram.c
@@ -42,7 +42,7 @@ nv50_vram_flags_valid(struct drm_device *dev, u32 tile_flags)
42{ 42{
43 int type = (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) >> 8; 43 int type = (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) >> 8;
44 44
45 if (likely(type < sizeof(types) && types[type])) 45 if (likely(type < ARRAY_SIZE(types) && types[type]))
46 return true; 46 return true;
47 return false; 47 return false;
48} 48}
diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c
new file mode 100644
index 000000000000..cbb4a1ae20b1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c
@@ -0,0 +1,271 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_dma.h"
28#include "nouveau_ramht.h"
29#include "nouveau_fbcon.h"
30#include "nouveau_mm.h"
31
32int
33nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
34{
35 struct nouveau_fbdev *nfbdev = info->par;
36 struct drm_device *dev = nfbdev->dev;
37 struct drm_nouveau_private *dev_priv = dev->dev_private;
38 struct nouveau_channel *chan = dev_priv->channel;
39 int ret;
40
41 ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11);
42 if (ret)
43 return ret;
44
45 if (rect->rop != ROP_COPY) {
46 BEGIN_NVC0(chan, 2, NvSub2D, 0x02ac, 1);
47 OUT_RING (chan, 1);
48 }
49 BEGIN_NVC0(chan, 2, NvSub2D, 0x0588, 1);
50 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
51 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
52 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
53 else
54 OUT_RING (chan, rect->color);
55 BEGIN_NVC0(chan, 2, NvSub2D, 0x0600, 4);
56 OUT_RING (chan, rect->dx);
57 OUT_RING (chan, rect->dy);
58 OUT_RING (chan, rect->dx + rect->width);
59 OUT_RING (chan, rect->dy + rect->height);
60 if (rect->rop != ROP_COPY) {
61 BEGIN_NVC0(chan, 2, NvSub2D, 0x02ac, 1);
62 OUT_RING (chan, 3);
63 }
64 FIRE_RING(chan);
65 return 0;
66}
67
68int
69nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
70{
71 struct nouveau_fbdev *nfbdev = info->par;
72 struct drm_device *dev = nfbdev->dev;
73 struct drm_nouveau_private *dev_priv = dev->dev_private;
74 struct nouveau_channel *chan = dev_priv->channel;
75 int ret;
76
77 ret = RING_SPACE(chan, 12);
78 if (ret)
79 return ret;
80
81 BEGIN_NVC0(chan, 2, NvSub2D, 0x0110, 1);
82 OUT_RING (chan, 0);
83 BEGIN_NVC0(chan, 2, NvSub2D, 0x08b0, 4);
84 OUT_RING (chan, region->dx);
85 OUT_RING (chan, region->dy);
86 OUT_RING (chan, region->width);
87 OUT_RING (chan, region->height);
88 BEGIN_NVC0(chan, 2, NvSub2D, 0x08d0, 4);
89 OUT_RING (chan, 0);
90 OUT_RING (chan, region->sx);
91 OUT_RING (chan, 0);
92 OUT_RING (chan, region->sy);
93 FIRE_RING(chan);
94 return 0;
95}
96
97int
98nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
99{
100 struct nouveau_fbdev *nfbdev = info->par;
101 struct drm_device *dev = nfbdev->dev;
102 struct drm_nouveau_private *dev_priv = dev->dev_private;
103 struct nouveau_channel *chan = dev_priv->channel;
104 uint32_t width, dwords, *data = (uint32_t *)image->data;
105 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
106 uint32_t *palette = info->pseudo_palette;
107 int ret;
108
109 if (image->depth != 1)
110 return -ENODEV;
111
112 ret = RING_SPACE(chan, 11);
113 if (ret)
114 return ret;
115
116 width = ALIGN(image->width, 32);
117 dwords = (width * image->height) >> 5;
118
119 BEGIN_NVC0(chan, 2, NvSub2D, 0x0814, 2);
120 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
121 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
122 OUT_RING (chan, palette[image->bg_color] | mask);
123 OUT_RING (chan, palette[image->fg_color] | mask);
124 } else {
125 OUT_RING (chan, image->bg_color);
126 OUT_RING (chan, image->fg_color);
127 }
128 BEGIN_NVC0(chan, 2, NvSub2D, 0x0838, 2);
129 OUT_RING (chan, image->width);
130 OUT_RING (chan, image->height);
131 BEGIN_NVC0(chan, 2, NvSub2D, 0x0850, 4);
132 OUT_RING (chan, 0);
133 OUT_RING (chan, image->dx);
134 OUT_RING (chan, 0);
135 OUT_RING (chan, image->dy);
136
137 while (dwords) {
138 int push = dwords > 2047 ? 2047 : dwords;
139
140 ret = RING_SPACE(chan, push + 1);
141 if (ret)
142 return ret;
143
144 dwords -= push;
145
146 BEGIN_NVC0(chan, 6, NvSub2D, 0x0860, push);
147 OUT_RINGp(chan, data, push);
148 data += push;
149 }
150
151 FIRE_RING(chan);
152 return 0;
153}
154
155int
156nvc0_fbcon_accel_init(struct fb_info *info)
157{
158 struct nouveau_fbdev *nfbdev = info->par;
159 struct drm_device *dev = nfbdev->dev;
160 struct drm_nouveau_private *dev_priv = dev->dev_private;
161 struct nouveau_channel *chan = dev_priv->channel;
162 struct nouveau_bo *nvbo = nfbdev->nouveau_fb.nvbo;
163 int ret, format;
164
165 ret = nouveau_gpuobj_gr_new(chan, 0x902d, 0x902d);
166 if (ret)
167 return ret;
168
169 switch (info->var.bits_per_pixel) {
170 case 8:
171 format = 0xf3;
172 break;
173 case 15:
174 format = 0xf8;
175 break;
176 case 16:
177 format = 0xe8;
178 break;
179 case 32:
180 switch (info->var.transp.length) {
181 case 0: /* depth 24 */
182 case 8: /* depth 32, just use 24.. */
183 format = 0xe6;
184 break;
185 case 2: /* depth 30 */
186 format = 0xd1;
187 break;
188 default:
189 return -EINVAL;
190 }
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 ret = RING_SPACE(chan, 60);
197 if (ret) {
198 WARN_ON(1);
199 nouveau_fbcon_gpu_lockup(info);
200 return ret;
201 }
202
203 printk(KERN_ERR "fb vma 0x%010llx\n", nvbo->vma.offset);
204
205 BEGIN_NVC0(chan, 2, NvSub2D, 0x0000, 1);
206 OUT_RING (chan, 0x0000902d);
207 BEGIN_NVC0(chan, 2, NvSub2D, 0x0104, 2);
208 OUT_RING (chan, upper_32_bits(chan->notifier_bo->bo.offset));
209 OUT_RING (chan, lower_32_bits(chan->notifier_bo->bo.offset));
210 BEGIN_NVC0(chan, 2, NvSub2D, 0x0290, 1);
211 OUT_RING (chan, 0);
212 BEGIN_NVC0(chan, 2, NvSub2D, 0x0888, 1);
213 OUT_RING (chan, 1);
214 BEGIN_NVC0(chan, 2, NvSub2D, 0x02ac, 1);
215 OUT_RING (chan, 3);
216 BEGIN_NVC0(chan, 2, NvSub2D, 0x02a0, 1);
217 OUT_RING (chan, 0x55);
218 BEGIN_NVC0(chan, 2, NvSub2D, 0x08c0, 4);
219 OUT_RING (chan, 0);
220 OUT_RING (chan, 1);
221 OUT_RING (chan, 0);
222 OUT_RING (chan, 1);
223 BEGIN_NVC0(chan, 2, NvSub2D, 0x0580, 2);
224 OUT_RING (chan, 4);
225 OUT_RING (chan, format);
226 BEGIN_NVC0(chan, 2, NvSub2D, 0x02e8, 2);
227 OUT_RING (chan, 2);
228 OUT_RING (chan, 1);
229
230 BEGIN_NVC0(chan, 2, NvSub2D, 0x0804, 1);
231 OUT_RING (chan, format);
232 BEGIN_NVC0(chan, 2, NvSub2D, 0x0800, 1);
233 OUT_RING (chan, 1);
234 BEGIN_NVC0(chan, 2, NvSub2D, 0x0808, 3);
235 OUT_RING (chan, 0);
236 OUT_RING (chan, 0);
237 OUT_RING (chan, 1);
238 BEGIN_NVC0(chan, 2, NvSub2D, 0x081c, 1);
239 OUT_RING (chan, 1);
240 BEGIN_NVC0(chan, 2, NvSub2D, 0x0840, 4);
241 OUT_RING (chan, 0);
242 OUT_RING (chan, 1);
243 OUT_RING (chan, 0);
244 OUT_RING (chan, 1);
245 BEGIN_NVC0(chan, 2, NvSub2D, 0x0200, 10);
246 OUT_RING (chan, format);
247 OUT_RING (chan, 1);
248 OUT_RING (chan, 0);
249 OUT_RING (chan, 1);
250 OUT_RING (chan, 0);
251 OUT_RING (chan, info->fix.line_length);
252 OUT_RING (chan, info->var.xres_virtual);
253 OUT_RING (chan, info->var.yres_virtual);
254 OUT_RING (chan, upper_32_bits(nvbo->vma.offset));
255 OUT_RING (chan, lower_32_bits(nvbo->vma.offset));
256 BEGIN_NVC0(chan, 2, NvSub2D, 0x0230, 10);
257 OUT_RING (chan, format);
258 OUT_RING (chan, 1);
259 OUT_RING (chan, 0);
260 OUT_RING (chan, 1);
261 OUT_RING (chan, 0);
262 OUT_RING (chan, info->fix.line_length);
263 OUT_RING (chan, info->var.xres_virtual);
264 OUT_RING (chan, info->var.yres_virtual);
265 OUT_RING (chan, upper_32_bits(nvbo->vma.offset));
266 OUT_RING (chan, lower_32_bits(nvbo->vma.offset));
267 FIRE_RING (chan);
268
269 return 0;
270}
271
diff --git a/drivers/gpu/drm/nouveau/nvc0_fifo.c b/drivers/gpu/drm/nouveau/nvc0_fifo.c
index 890c2b95fbc1..82a4ded5dae8 100644
--- a/drivers/gpu/drm/nouveau/nvc0_fifo.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fifo.c
@@ -25,6 +25,48 @@
25#include "drmP.h" 25#include "drmP.h"
26 26
27#include "nouveau_drv.h" 27#include "nouveau_drv.h"
28#include "nouveau_mm.h"
29
30static void nvc0_fifo_isr(struct drm_device *);
31
32struct nvc0_fifo_priv {
33 struct nouveau_gpuobj *playlist[2];
34 int cur_playlist;
35 struct nouveau_vma user_vma;
36};
37
38struct nvc0_fifo_chan {
39 struct nouveau_bo *user;
40 struct nouveau_gpuobj *ramfc;
41};
42
43static void
44nvc0_fifo_playlist_update(struct drm_device *dev)
45{
46 struct drm_nouveau_private *dev_priv = dev->dev_private;
47 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
48 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
49 struct nvc0_fifo_priv *priv = pfifo->priv;
50 struct nouveau_gpuobj *cur;
51 int i, p;
52
53 cur = priv->playlist[priv->cur_playlist];
54 priv->cur_playlist = !priv->cur_playlist;
55
56 for (i = 0, p = 0; i < 128; i++) {
57 if (!(nv_rd32(dev, 0x3004 + (i * 8)) & 1))
58 continue;
59 nv_wo32(cur, p + 0, i);
60 nv_wo32(cur, p + 4, 0x00000004);
61 p += 8;
62 }
63 pinstmem->flush(dev);
64
65 nv_wr32(dev, 0x002270, cur->vinst >> 12);
66 nv_wr32(dev, 0x002274, 0x01f00000 | (p >> 3));
67 if (!nv_wait(dev, 0x00227c, 0x00100000, 0x00000000))
68 NV_ERROR(dev, "PFIFO - playlist update failed\n");
69}
28 70
29void 71void
30nvc0_fifo_disable(struct drm_device *dev) 72nvc0_fifo_disable(struct drm_device *dev)
@@ -57,12 +99,135 @@ nvc0_fifo_channel_id(struct drm_device *dev)
57int 99int
58nvc0_fifo_create_context(struct nouveau_channel *chan) 100nvc0_fifo_create_context(struct nouveau_channel *chan)
59{ 101{
102 struct drm_device *dev = chan->dev;
103 struct drm_nouveau_private *dev_priv = dev->dev_private;
104 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
105 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
106 struct nvc0_fifo_priv *priv = pfifo->priv;
107 struct nvc0_fifo_chan *fifoch;
108 u64 ib_virt, user_vinst;
109 int ret;
110
111 chan->fifo_priv = kzalloc(sizeof(*fifoch), GFP_KERNEL);
112 if (!chan->fifo_priv)
113 return -ENOMEM;
114 fifoch = chan->fifo_priv;
115
116 /* allocate vram for control regs, map into polling area */
117 ret = nouveau_bo_new(dev, NULL, 0x1000, 0, TTM_PL_FLAG_VRAM,
118 0, 0, true, true, &fifoch->user);
119 if (ret)
120 goto error;
121
122 ret = nouveau_bo_pin(fifoch->user, TTM_PL_FLAG_VRAM);
123 if (ret) {
124 nouveau_bo_ref(NULL, &fifoch->user);
125 goto error;
126 }
127
128 user_vinst = fifoch->user->bo.mem.start << PAGE_SHIFT;
129
130 ret = nouveau_bo_map(fifoch->user);
131 if (ret) {
132 nouveau_bo_unpin(fifoch->user);
133 nouveau_bo_ref(NULL, &fifoch->user);
134 goto error;
135 }
136
137 nouveau_vm_map_at(&priv->user_vma, chan->id * 0x1000,
138 fifoch->user->bo.mem.mm_node);
139
140 chan->user = ioremap_wc(pci_resource_start(dev->pdev, 1) +
141 priv->user_vma.offset + (chan->id * 0x1000),
142 PAGE_SIZE);
143 if (!chan->user) {
144 ret = -ENOMEM;
145 goto error;
146 }
147
148 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
149
150 /* zero channel regs */
151 nouveau_bo_wr32(fifoch->user, 0x0040/4, 0);
152 nouveau_bo_wr32(fifoch->user, 0x0044/4, 0);
153 nouveau_bo_wr32(fifoch->user, 0x0048/4, 0);
154 nouveau_bo_wr32(fifoch->user, 0x004c/4, 0);
155 nouveau_bo_wr32(fifoch->user, 0x0050/4, 0);
156 nouveau_bo_wr32(fifoch->user, 0x0058/4, 0);
157 nouveau_bo_wr32(fifoch->user, 0x005c/4, 0);
158 nouveau_bo_wr32(fifoch->user, 0x0060/4, 0);
159 nouveau_bo_wr32(fifoch->user, 0x0088/4, 0);
160 nouveau_bo_wr32(fifoch->user, 0x008c/4, 0);
161
162 /* ramfc */
163 ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
164 chan->ramin->vinst, 0x100,
165 NVOBJ_FLAG_ZERO_ALLOC, &fifoch->ramfc);
166 if (ret)
167 goto error;
168
169 nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(user_vinst));
170 nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(user_vinst));
171 nv_wo32(fifoch->ramfc, 0x10, 0x0000face);
172 nv_wo32(fifoch->ramfc, 0x30, 0xfffff902);
173 nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt));
174 nv_wo32(fifoch->ramfc, 0x4c, drm_order(chan->dma.ib_max + 1) << 16 |
175 upper_32_bits(ib_virt));
176 nv_wo32(fifoch->ramfc, 0x54, 0x00000002);
177 nv_wo32(fifoch->ramfc, 0x84, 0x20400000);
178 nv_wo32(fifoch->ramfc, 0x94, 0x30000001);
179 nv_wo32(fifoch->ramfc, 0x9c, 0x00000100);
180 nv_wo32(fifoch->ramfc, 0xa4, 0x1f1f1f1f);
181 nv_wo32(fifoch->ramfc, 0xa8, 0x1f1f1f1f);
182 nv_wo32(fifoch->ramfc, 0xac, 0x0000001f);
183 nv_wo32(fifoch->ramfc, 0xb8, 0xf8000000);
184 nv_wo32(fifoch->ramfc, 0xf8, 0x10003080); /* 0x002310 */
185 nv_wo32(fifoch->ramfc, 0xfc, 0x10000010); /* 0x002350 */
186 pinstmem->flush(dev);
187
188 nv_wr32(dev, 0x003000 + (chan->id * 8), 0xc0000000 |
189 (chan->ramin->vinst >> 12));
190 nv_wr32(dev, 0x003004 + (chan->id * 8), 0x001f0001);
191 nvc0_fifo_playlist_update(dev);
60 return 0; 192 return 0;
193
194error:
195 pfifo->destroy_context(chan);
196 return ret;
61} 197}
62 198
63void 199void
64nvc0_fifo_destroy_context(struct nouveau_channel *chan) 200nvc0_fifo_destroy_context(struct nouveau_channel *chan)
65{ 201{
202 struct drm_device *dev = chan->dev;
203 struct nvc0_fifo_chan *fifoch;
204
205 nv_mask(dev, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000);
206 nv_wr32(dev, 0x002634, chan->id);
207 if (!nv_wait(dev, 0x0002634, 0xffffffff, chan->id))
208 NV_WARN(dev, "0x2634 != chid: 0x%08x\n", nv_rd32(dev, 0x2634));
209
210 nvc0_fifo_playlist_update(dev);
211
212 nv_wr32(dev, 0x003000 + (chan->id * 8), 0x00000000);
213
214 if (chan->user) {
215 iounmap(chan->user);
216 chan->user = NULL;
217 }
218
219 fifoch = chan->fifo_priv;
220 chan->fifo_priv = NULL;
221 if (!fifoch)
222 return;
223
224 nouveau_gpuobj_ref(NULL, &fifoch->ramfc);
225 if (fifoch->user) {
226 nouveau_bo_unmap(fifoch->user);
227 nouveau_bo_unpin(fifoch->user);
228 nouveau_bo_ref(NULL, &fifoch->user);
229 }
230 kfree(fifoch);
66} 231}
67 232
68int 233int
@@ -77,14 +242,208 @@ nvc0_fifo_unload_context(struct drm_device *dev)
77 return 0; 242 return 0;
78} 243}
79 244
245static void
246nvc0_fifo_destroy(struct drm_device *dev)
247{
248 struct drm_nouveau_private *dev_priv = dev->dev_private;
249 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
250 struct nvc0_fifo_priv *priv;
251
252 priv = pfifo->priv;
253 if (!priv)
254 return;
255
256 nouveau_vm_put(&priv->user_vma);
257 nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
258 nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
259 kfree(priv);
260}
261
80void 262void
81nvc0_fifo_takedown(struct drm_device *dev) 263nvc0_fifo_takedown(struct drm_device *dev)
82{ 264{
265 nv_wr32(dev, 0x002140, 0x00000000);
266 nvc0_fifo_destroy(dev);
267}
268
269static int
270nvc0_fifo_create(struct drm_device *dev)
271{
272 struct drm_nouveau_private *dev_priv = dev->dev_private;
273 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
274 struct nvc0_fifo_priv *priv;
275 int ret;
276
277 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
278 if (!priv)
279 return -ENOMEM;
280 pfifo->priv = priv;
281
282 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,
283 &priv->playlist[0]);
284 if (ret)
285 goto error;
286
287 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000, 0,
288 &priv->playlist[1]);
289 if (ret)
290 goto error;
291
292 ret = nouveau_vm_get(dev_priv->bar1_vm, pfifo->channels * 0x1000,
293 12, NV_MEM_ACCESS_RW, &priv->user_vma);
294 if (ret)
295 goto error;
296
297 nouveau_irq_register(dev, 8, nvc0_fifo_isr);
298 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
299 return 0;
300
301error:
302 nvc0_fifo_destroy(dev);
303 return ret;
83} 304}
84 305
85int 306int
86nvc0_fifo_init(struct drm_device *dev) 307nvc0_fifo_init(struct drm_device *dev)
87{ 308{
309 struct drm_nouveau_private *dev_priv = dev->dev_private;
310 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
311 struct nvc0_fifo_priv *priv;
312 int ret, i;
313
314 if (!pfifo->priv) {
315 ret = nvc0_fifo_create(dev);
316 if (ret)
317 return ret;
318 }
319 priv = pfifo->priv;
320
321 /* reset PFIFO, enable all available PSUBFIFO areas */
322 nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
323 nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
324 nv_wr32(dev, 0x000204, 0xffffffff);
325 nv_wr32(dev, 0x002204, 0xffffffff);
326
327 /* assign engines to subfifos */
328 nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */
329 nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */
330 nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */
331 nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */
332 nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */
333 nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */
334
335 /* PSUBFIFO[n] */
336 for (i = 0; i < 3; i++) {
337 nv_mask(dev, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
338 nv_wr32(dev, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
339 nv_wr32(dev, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTR_EN */
340 }
341
342 nv_mask(dev, 0x002200, 0x00000001, 0x00000001);
343 nv_wr32(dev, 0x002254, 0x10000000 | priv->user_vma.offset >> 12);
344
345 nv_wr32(dev, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
346 nv_wr32(dev, 0x002100, 0xffffffff);
347 nv_wr32(dev, 0x002140, 0xbfffffff);
88 return 0; 348 return 0;
89} 349}
90 350
351struct nouveau_enum nvc0_fifo_fault_unit[] = {
352 { 0, "PGRAPH" },
353 { 3, "PEEPHOLE" },
354 { 4, "BAR1" },
355 { 5, "BAR3" },
356 { 7, "PFIFO" },
357 {}
358};
359
360struct nouveau_enum nvc0_fifo_fault_reason[] = {
361 { 0, "PT_NOT_PRESENT" },
362 { 1, "PT_TOO_SHORT" },
363 { 2, "PAGE_NOT_PRESENT" },
364 { 3, "VM_LIMIT_EXCEEDED" },
365 {}
366};
367
368struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = {
369/* { 0x00008000, "" } seen with null ib push */
370 { 0x00200000, "ILLEGAL_MTHD" },
371 { 0x00800000, "EMPTY_SUBC" },
372 {}
373};
374
375static void
376nvc0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
377{
378 u32 inst = nv_rd32(dev, 0x2800 + (unit * 0x10));
379 u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10));
380 u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10));
381 u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10));
382
383 NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [",
384 (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo);
385 nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
386 printk("] from ");
387 nouveau_enum_print(nvc0_fifo_fault_unit, unit);
388 printk(" on channel 0x%010llx\n", (u64)inst << 12);
389}
390
391static void
392nvc0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
393{
394 u32 stat = nv_rd32(dev, 0x040108 + (unit * 0x2000));
395 u32 addr = nv_rd32(dev, 0x0400c0 + (unit * 0x2000));
396 u32 data = nv_rd32(dev, 0x0400c4 + (unit * 0x2000));
397 u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
398 u32 subc = (addr & 0x00070000);
399 u32 mthd = (addr & 0x00003ffc);
400
401 NV_INFO(dev, "PSUBFIFO %d:", unit);
402 nouveau_bitfield_print(nvc0_fifo_subfifo_intr, stat);
403 NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
404 unit, chid, subc, mthd, data);
405
406 nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
407 nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);
408}
409
410static void
411nvc0_fifo_isr(struct drm_device *dev)
412{
413 u32 stat = nv_rd32(dev, 0x002100);
414
415 if (stat & 0x10000000) {
416 u32 units = nv_rd32(dev, 0x00259c);
417 u32 u = units;
418
419 while (u) {
420 int i = ffs(u) - 1;
421 nvc0_fifo_isr_vm_fault(dev, i);
422 u &= ~(1 << i);
423 }
424
425 nv_wr32(dev, 0x00259c, units);
426 stat &= ~0x10000000;
427 }
428
429 if (stat & 0x20000000) {
430 u32 units = nv_rd32(dev, 0x0025a0);
431 u32 u = units;
432
433 while (u) {
434 int i = ffs(u) - 1;
435 nvc0_fifo_isr_subfifo_intr(dev, i);
436 u &= ~(1 << i);
437 }
438
439 nv_wr32(dev, 0x0025a0, units);
440 stat &= ~0x20000000;
441 }
442
443 if (stat) {
444 NV_INFO(dev, "PFIFO: unhandled status 0x%08x\n", stat);
445 nv_wr32(dev, 0x002100, stat);
446 }
447
448 nv_wr32(dev, 0x2140, 0);
449}
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index 717a5177a8d8..cf2f6aa920b4 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -22,9 +22,16 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <linux/firmware.h>
26
25#include "drmP.h" 27#include "drmP.h"
26 28
27#include "nouveau_drv.h" 29#include "nouveau_drv.h"
30#include "nouveau_mm.h"
31#include "nvc0_graph.h"
32
33static void nvc0_graph_isr(struct drm_device *);
34static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan);
28 35
29void 36void
30nvc0_graph_fifo_access(struct drm_device *dev, bool enabled) 37nvc0_graph_fifo_access(struct drm_device *dev, bool enabled)
@@ -37,39 +44,739 @@ nvc0_graph_channel(struct drm_device *dev)
37 return NULL; 44 return NULL;
38} 45}
39 46
47static int
48nvc0_graph_construct_context(struct nouveau_channel *chan)
49{
50 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
51 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
52 struct nvc0_graph_chan *grch = chan->pgraph_ctx;
53 struct drm_device *dev = chan->dev;
54 int ret, i;
55 u32 *ctx;
56
57 ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
58 if (!ctx)
59 return -ENOMEM;
60
61 nvc0_graph_load_context(chan);
62
63 nv_wo32(grch->grctx, 0x1c, 1);
64 nv_wo32(grch->grctx, 0x20, 0);
65 nv_wo32(grch->grctx, 0x28, 0);
66 nv_wo32(grch->grctx, 0x2c, 0);
67 dev_priv->engine.instmem.flush(dev);
68
69 ret = nvc0_grctx_generate(chan);
70 if (ret) {
71 kfree(ctx);
72 return ret;
73 }
74
75 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
76 if (ret) {
77 kfree(ctx);
78 return ret;
79 }
80
81 for (i = 0; i < priv->grctx_size; i += 4)
82 ctx[i / 4] = nv_ro32(grch->grctx, i);
83
84 priv->grctx_vals = ctx;
85 return 0;
86}
87
88static int
89nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
90{
91 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
92 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
93 struct nvc0_graph_chan *grch = chan->pgraph_ctx;
94 struct drm_device *dev = chan->dev;
95 int i = 0, gpc, tp, ret;
96 u32 magic;
97
98 ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM,
99 &grch->unk408004);
100 if (ret)
101 return ret;
102
103 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM,
104 &grch->unk40800c);
105 if (ret)
106 return ret;
107
108 ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096, NVOBJ_FLAG_VM,
109 &grch->unk418810);
110 if (ret)
111 return ret;
112
113 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM,
114 &grch->mmio);
115 if (ret)
116 return ret;
117
118
119 nv_wo32(grch->mmio, i++ * 4, 0x00408004);
120 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
121 nv_wo32(grch->mmio, i++ * 4, 0x00408008);
122 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
123
124 nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
125 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
126 nv_wo32(grch->mmio, i++ * 4, 0x00408010);
127 nv_wo32(grch->mmio, i++ * 4, 0x80000000);
128
129 nv_wo32(grch->mmio, i++ * 4, 0x00418810);
130 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);
131 nv_wo32(grch->mmio, i++ * 4, 0x00419848);
132 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);
133
134 nv_wo32(grch->mmio, i++ * 4, 0x00419004);
135 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
136 nv_wo32(grch->mmio, i++ * 4, 0x00419008);
137 nv_wo32(grch->mmio, i++ * 4, 0x00000000);
138
139 nv_wo32(grch->mmio, i++ * 4, 0x00418808);
140 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
141 nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
142 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
143
144 magic = 0x02180000;
145 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
146 nv_wo32(grch->mmio, i++ * 4, magic);
147 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
148 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) {
149 u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
150 nv_wo32(grch->mmio, i++ * 4, reg);
151 nv_wo32(grch->mmio, i++ * 4, magic);
152 }
153 }
154
155 grch->mmio_nr = i / 2;
156 return 0;
157}
158
40int 159int
41nvc0_graph_create_context(struct nouveau_channel *chan) 160nvc0_graph_create_context(struct nouveau_channel *chan)
42{ 161{
162 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
163 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
164 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
165 struct nvc0_graph_priv *priv = pgraph->priv;
166 struct nvc0_graph_chan *grch;
167 struct drm_device *dev = chan->dev;
168 struct nouveau_gpuobj *grctx;
169 int ret, i;
170
171 chan->pgraph_ctx = kzalloc(sizeof(*grch), GFP_KERNEL);
172 if (!chan->pgraph_ctx)
173 return -ENOMEM;
174 grch = chan->pgraph_ctx;
175
176 ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
177 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
178 &grch->grctx);
179 if (ret)
180 goto error;
181 chan->ramin_grctx = grch->grctx;
182 grctx = grch->grctx;
183
184 ret = nvc0_graph_create_context_mmio_list(chan);
185 if (ret)
186 goto error;
187
188 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);
189 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));
190 pinstmem->flush(dev);
191
192 if (!priv->grctx_vals) {
193 ret = nvc0_graph_construct_context(chan);
194 if (ret)
195 goto error;
196 }
197
198 for (i = 0; i < priv->grctx_size; i += 4)
199 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
200
201 nv_wo32(grctx, 0xf4, 0);
202 nv_wo32(grctx, 0xf8, 0);
203 nv_wo32(grctx, 0x10, grch->mmio_nr);
204 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
205 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
206 nv_wo32(grctx, 0x1c, 1);
207 nv_wo32(grctx, 0x20, 0);
208 nv_wo32(grctx, 0x28, 0);
209 nv_wo32(grctx, 0x2c, 0);
210 pinstmem->flush(dev);
43 return 0; 211 return 0;
212
213error:
214 pgraph->destroy_context(chan);
215 return ret;
44} 216}
45 217
46void 218void
47nvc0_graph_destroy_context(struct nouveau_channel *chan) 219nvc0_graph_destroy_context(struct nouveau_channel *chan)
48{ 220{
221 struct nvc0_graph_chan *grch;
222
223 grch = chan->pgraph_ctx;
224 chan->pgraph_ctx = NULL;
225 if (!grch)
226 return;
227
228 nouveau_gpuobj_ref(NULL, &grch->mmio);
229 nouveau_gpuobj_ref(NULL, &grch->unk418810);
230 nouveau_gpuobj_ref(NULL, &grch->unk40800c);
231 nouveau_gpuobj_ref(NULL, &grch->unk408004);
232 nouveau_gpuobj_ref(NULL, &grch->grctx);
233 chan->ramin_grctx = NULL;
49} 234}
50 235
51int 236int
52nvc0_graph_load_context(struct nouveau_channel *chan) 237nvc0_graph_load_context(struct nouveau_channel *chan)
53{ 238{
239 struct drm_device *dev = chan->dev;
240
241 nv_wr32(dev, 0x409840, 0x00000030);
242 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
243 nv_wr32(dev, 0x409504, 0x00000003);
244 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
245 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
246
247 printk(KERN_ERR "load_ctx 0x%08x\n", nv_rd32(dev, 0x409b00));
248 return 0;
249}
250
251static int
252nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
253{
254 nv_wr32(dev, 0x409840, 0x00000003);
255 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
256 nv_wr32(dev, 0x409504, 0x00000009);
257 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
258 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
259 return -EBUSY;
260 }
261
54 return 0; 262 return 0;
55} 263}
56 264
57int 265int
58nvc0_graph_unload_context(struct drm_device *dev) 266nvc0_graph_unload_context(struct drm_device *dev)
59{ 267{
60 return 0; 268 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
269 return nvc0_graph_unload_context_to(dev, inst);
270}
271
272static void
273nvc0_graph_destroy(struct drm_device *dev)
274{
275 struct drm_nouveau_private *dev_priv = dev->dev_private;
276 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
277 struct nvc0_graph_priv *priv;
278
279 priv = pgraph->priv;
280 if (!priv)
281 return;
282
283 nouveau_irq_unregister(dev, 12);
284
285 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
286 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
287
288 if (priv->grctx_vals)
289 kfree(priv->grctx_vals);
290 kfree(priv);
61} 291}
62 292
63void 293void
64nvc0_graph_takedown(struct drm_device *dev) 294nvc0_graph_takedown(struct drm_device *dev)
65{ 295{
296 nvc0_graph_destroy(dev);
297}
298
299static int
300nvc0_graph_create(struct drm_device *dev)
301{
302 struct drm_nouveau_private *dev_priv = dev->dev_private;
303 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
304 struct nvc0_graph_priv *priv;
305 int ret, gpc, i;
306
307 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
308 if (!priv)
309 return -ENOMEM;
310 pgraph->priv = priv;
311
312 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
313 if (ret)
314 goto error;
315
316 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
317 if (ret)
318 goto error;
319
320 for (i = 0; i < 0x1000; i += 4) {
321 nv_wo32(priv->unk4188b4, i, 0x00000010);
322 nv_wo32(priv->unk4188b8, i, 0x00000010);
323 }
324
325 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
326 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
327 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
328 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
329 priv->tp_total += priv->tp_nr[gpc];
330 }
331
332 /*XXX: these need figuring out... */
333 switch (dev_priv->chipset) {
334 case 0xc0:
335 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
336 priv->magic_not_rop_nr = 0x07;
337 priv->magic419bd0 = 0x0a360000;
338 priv->magic419be4 = 0x04c33a54;
339 /* filled values up to tp_total, the rest 0 */
340 priv->magicgpc980[0] = 0x22111000;
341 priv->magicgpc980[1] = 0x00000233;
342 priv->magicgpc980[2] = 0x00000000;
343 priv->magicgpc980[3] = 0x00000000;
344 priv->magicgpc918 = 0x000ba2e9;
345 } else
346 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
347 priv->magic_not_rop_nr = 0x05;
348 priv->magic419bd0 = 0x043c0000;
349 priv->magic419be4 = 0x09041208;
350 priv->magicgpc980[0] = 0x11110000;
351 priv->magicgpc980[1] = 0x00233222;
352 priv->magicgpc980[2] = 0x00000000;
353 priv->magicgpc980[3] = 0x00000000;
354 priv->magicgpc918 = 0x00092493;
355 } else
356 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
357 priv->magic_not_rop_nr = 0x06;
358 priv->magic419bd0 = 0x023e0000;
359 priv->magic419be4 = 0x10414104;
360 priv->magicgpc980[0] = 0x11110000;
361 priv->magicgpc980[1] = 0x03332222;
362 priv->magicgpc980[2] = 0x00000000;
363 priv->magicgpc980[3] = 0x00000000;
364 priv->magicgpc918 = 0x00088889;
365 }
366 break;
367 case 0xc3: /* 450, 4/0/0/0, 2 */
368 priv->magic_not_rop_nr = 0x03;
369 priv->magic419bd0 = 0x00500000;
370 priv->magic419be4 = 0x00000000;
371 priv->magicgpc980[0] = 0x00003210;
372 priv->magicgpc980[1] = 0x00000000;
373 priv->magicgpc980[2] = 0x00000000;
374 priv->magicgpc980[3] = 0x00000000;
375 priv->magicgpc918 = 0x00200000;
376 break;
377 case 0xc4: /* 460, 3/4/0/0, 4 */
378 priv->magic_not_rop_nr = 0x01;
379 priv->magic419bd0 = 0x045c0000;
380 priv->magic419be4 = 0x09041208;
381 priv->magicgpc980[0] = 0x02321100;
382 priv->magicgpc980[1] = 0x00000000;
383 priv->magicgpc980[2] = 0x00000000;
384 priv->magicgpc980[3] = 0x00000000;
385 priv->magicgpc918 = 0x00124925;
386 break;
387 }
388
389 if (!priv->magic419bd0) {
390 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
391 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
392 priv->tp_nr[3], priv->rop_nr);
393 /* use 0xc3's values... */
394 priv->magic_not_rop_nr = 0x03;
395 priv->magic419bd0 = 0x00500000;
396 priv->magic419be4 = 0x00000000;
397 priv->magicgpc980[0] = 0x00003210;
398 priv->magicgpc980[1] = 0x00000000;
399 priv->magicgpc980[2] = 0x00000000;
400 priv->magicgpc980[3] = 0x00000000;
401 priv->magicgpc918 = 0x00200000;
402 }
403
404 nouveau_irq_register(dev, 12, nvc0_graph_isr);
405 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
406 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
407 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
408 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
409 return 0;
410
411error:
412 nvc0_graph_destroy(dev);
413 return ret;
414}
415
416static void
417nvc0_graph_init_obj418880(struct drm_device *dev)
418{
419 struct drm_nouveau_private *dev_priv = dev->dev_private;
420 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
421 struct nvc0_graph_priv *priv = pgraph->priv;
422 int i;
423
424 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
425 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
426 for (i = 0; i < 4; i++)
427 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
428 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
429 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
430}
431
432static void
433nvc0_graph_init_regs(struct drm_device *dev)
434{
435 nv_wr32(dev, 0x400080, 0x003083c2);
436 nv_wr32(dev, 0x400088, 0x00006fe7);
437 nv_wr32(dev, 0x40008c, 0x00000000);
438 nv_wr32(dev, 0x400090, 0x00000030);
439 nv_wr32(dev, 0x40013c, 0x013901f7);
440 nv_wr32(dev, 0x400140, 0x00000100);
441 nv_wr32(dev, 0x400144, 0x00000000);
442 nv_wr32(dev, 0x400148, 0x00000110);
443 nv_wr32(dev, 0x400138, 0x00000000);
444 nv_wr32(dev, 0x400130, 0x00000000);
445 nv_wr32(dev, 0x400134, 0x00000000);
446 nv_wr32(dev, 0x400124, 0x00000002);
447}
448
449static void
450nvc0_graph_init_gpc_0(struct drm_device *dev)
451{
452 struct drm_nouveau_private *dev_priv = dev->dev_private;
453 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
454 int gpc;
455
456 // TP ROP UNKVAL(magic_not_rop_nr)
457 // 450: 4/0/0/0 2 3
458 // 460: 3/4/0/0 4 1
459 // 465: 3/4/4/0 4 7
460 // 470: 3/3/4/4 5 5
461 // 480: 3/4/4/4 6 6
462
463 // magicgpc918
464 // 450: 00200000 00000000001000000000000000000000
465 // 460: 00124925 00000000000100100100100100100101
466 // 465: 000ba2e9 00000000000010111010001011101001
467 // 470: 00092493 00000000000010010010010010010011
468 // 480: 00088889 00000000000010001000100010001001
469
470 /* filled values up to tp_total, remainder 0 */
471 // 450: 00003210 00000000 00000000 00000000
472 // 460: 02321100 00000000 00000000 00000000
473 // 465: 22111000 00000233 00000000 00000000
474 // 470: 11110000 00233222 00000000 00000000
475 // 480: 11110000 03332222 00000000 00000000
476
477 nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]);
478 nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]);
479 nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]);
480 nv_wr32(dev, GPC_BCAST(0x098c), priv->magicgpc980[3]);
481
482 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
483 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
484 priv->tp_nr[gpc]);
485 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
486 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918);
487 }
488
489 nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918);
490 nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr);
491}
492
493static void
494nvc0_graph_init_units(struct drm_device *dev)
495{
496 nv_wr32(dev, 0x409c24, 0x000f0000);
497 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
498 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
499 nv_wr32(dev, 0x408030, 0xc0000000);
500 nv_wr32(dev, 0x40601c, 0xc0000000);
501 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
502 nv_wr32(dev, 0x406018, 0xc0000000);
503 nv_wr32(dev, 0x405840, 0xc0000000);
504 nv_wr32(dev, 0x405844, 0x00ffffff);
505 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
506 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
507}
508
509static void
510nvc0_graph_init_gpc_1(struct drm_device *dev)
511{
512 struct drm_nouveau_private *dev_priv = dev->dev_private;
513 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
514 int gpc, tp;
515
516 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
517 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
518 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
519 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
520 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
521 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
522 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
523 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
524 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
525 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
526 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
527 nv_wr32(dev, TP_UNIT(gpc, tp, 0xe44), 0x001ffffe);
528 nv_wr32(dev, TP_UNIT(gpc, tp, 0xe4c), 0x0000000f);
529 }
530 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
531 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
532 }
533}
534
535static void
536nvc0_graph_init_rop(struct drm_device *dev)
537{
538 struct drm_nouveau_private *dev_priv = dev->dev_private;
539 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
540 int rop;
541
542 for (rop = 0; rop < priv->rop_nr; rop++) {
543 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
544 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
545 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
546 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
547 }
548}
549
550static int
551nvc0_fuc_load_fw(struct drm_device *dev, u32 fuc_base,
552 const char *code_fw, const char *data_fw)
553{
554 const struct firmware *fw;
555 char name[32];
556 int ret, i;
557
558 snprintf(name, sizeof(name), "nouveau/%s", data_fw);
559 ret = request_firmware(&fw, name, &dev->pdev->dev);
560 if (ret) {
561 NV_ERROR(dev, "failed to load %s\n", data_fw);
562 return ret;
563 }
564
565 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
566 for (i = 0; i < fw->size / 4; i++)
567 nv_wr32(dev, fuc_base + 0x01c4, ((u32 *)fw->data)[i]);
568 release_firmware(fw);
569
570 snprintf(name, sizeof(name), "nouveau/%s", code_fw);
571 ret = request_firmware(&fw, name, &dev->pdev->dev);
572 if (ret) {
573 NV_ERROR(dev, "failed to load %s\n", code_fw);
574 return ret;
575 }
576
577 nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
578 for (i = 0; i < fw->size / 4; i++) {
579 if ((i & 0x3f) == 0)
580 nv_wr32(dev, fuc_base + 0x0188, i >> 6);
581 nv_wr32(dev, fuc_base + 0x0184, ((u32 *)fw->data)[i]);
582 }
583 release_firmware(fw);
584
585 return 0;
586}
587
588static int
589nvc0_graph_init_ctxctl(struct drm_device *dev)
590{
591 struct drm_nouveau_private *dev_priv = dev->dev_private;
592 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
593 u32 r000260;
594 int ret;
595
596 /* load fuc microcode */
597 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
598 ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d");
599 if (ret == 0)
600 nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad");
601 nv_wr32(dev, 0x000260, r000260);
602
603 if (ret)
604 return ret;
605
606 /* start both of them running */
607 nv_wr32(dev, 0x409840, 0xffffffff);
608 nv_wr32(dev, 0x41a10c, 0x00000000);
609 nv_wr32(dev, 0x40910c, 0x00000000);
610 nv_wr32(dev, 0x41a100, 0x00000002);
611 nv_wr32(dev, 0x409100, 0x00000002);
612 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
613 NV_INFO(dev, "0x409800 wait failed\n");
614
615 nv_wr32(dev, 0x409840, 0xffffffff);
616 nv_wr32(dev, 0x409500, 0x7fffffff);
617 nv_wr32(dev, 0x409504, 0x00000021);
618
619 nv_wr32(dev, 0x409840, 0xffffffff);
620 nv_wr32(dev, 0x409500, 0x00000000);
621 nv_wr32(dev, 0x409504, 0x00000010);
622 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
623 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
624 return -EBUSY;
625 }
626 priv->grctx_size = nv_rd32(dev, 0x409800);
627
628 nv_wr32(dev, 0x409840, 0xffffffff);
629 nv_wr32(dev, 0x409500, 0x00000000);
630 nv_wr32(dev, 0x409504, 0x00000016);
631 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
632 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
633 return -EBUSY;
634 }
635
636 nv_wr32(dev, 0x409840, 0xffffffff);
637 nv_wr32(dev, 0x409500, 0x00000000);
638 nv_wr32(dev, 0x409504, 0x00000025);
639 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
640 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
641 return -EBUSY;
642 }
643
644 return 0;
66} 645}
67 646
68int 647int
69nvc0_graph_init(struct drm_device *dev) 648nvc0_graph_init(struct drm_device *dev)
70{ 649{
71 struct drm_nouveau_private *dev_priv = dev->dev_private; 650 struct drm_nouveau_private *dev_priv = dev->dev_private;
651 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
652 struct nvc0_graph_priv *priv;
653 int ret;
654
72 dev_priv->engine.graph.accel_blocked = true; 655 dev_priv->engine.graph.accel_blocked = true;
656
657 switch (dev_priv->chipset) {
658 case 0xc0:
659 case 0xc3:
660 case 0xc4:
661 break;
662 default:
663 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
664 if (nouveau_noaccel != 0)
665 return 0;
666 break;
667 }
668
669 nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
670 nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
671
672 if (!pgraph->priv) {
673 ret = nvc0_graph_create(dev);
674 if (ret)
675 return ret;
676 }
677 priv = pgraph->priv;
678
679 nvc0_graph_init_obj418880(dev);
680 nvc0_graph_init_regs(dev);
681 //nvc0_graph_init_unitplemented_magics(dev);
682 nvc0_graph_init_gpc_0(dev);
683 //nvc0_graph_init_unitplemented_c242(dev);
684
685 nv_wr32(dev, 0x400500, 0x00010001);
686 nv_wr32(dev, 0x400100, 0xffffffff);
687 nv_wr32(dev, 0x40013c, 0xffffffff);
688
689 nvc0_graph_init_units(dev);
690 nvc0_graph_init_gpc_1(dev);
691 nvc0_graph_init_rop(dev);
692
693 nv_wr32(dev, 0x400108, 0xffffffff);
694 nv_wr32(dev, 0x400138, 0xffffffff);
695 nv_wr32(dev, 0x400118, 0xffffffff);
696 nv_wr32(dev, 0x400130, 0xffffffff);
697 nv_wr32(dev, 0x40011c, 0xffffffff);
698 nv_wr32(dev, 0x400134, 0xffffffff);
699 nv_wr32(dev, 0x400054, 0x34ce3464);
700
701 ret = nvc0_graph_init_ctxctl(dev);
702 if (ret)
703 return ret;
704
705 dev_priv->engine.graph.accel_blocked = false;
73 return 0; 706 return 0;
74} 707}
75 708
709static struct nouveau_enum nvc0_graph_data_error[] = {
710 { 5, "INVALID_ENUM" },
711 {}
712};
713
714static int
715nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
716{
717 struct drm_nouveau_private *dev_priv = dev->dev_private;
718 struct nouveau_channel *chan;
719 unsigned long flags;
720 int i;
721
722 spin_lock_irqsave(&dev_priv->channels.lock, flags);
723 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
724 chan = dev_priv->channels.ptr[i];
725 if (!chan || !chan->ramin)
726 continue;
727
728 if (inst == chan->ramin->vinst)
729 break;
730 }
731 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
732 return i;
733}
734
735static void
736nvc0_graph_isr(struct drm_device *dev)
737{
738 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
739 u32 chid = nvc0_graph_isr_chid(dev, inst);
740 u32 stat = nv_rd32(dev, 0x400100);
741 u32 addr = nv_rd32(dev, 0x400704);
742 u32 mthd = (addr & 0x00003ffc);
743 u32 subc = (addr & 0x00070000) >> 16;
744 u32 data = nv_rd32(dev, 0x400708);
745 u32 code = nv_rd32(dev, 0x400110);
746 u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
747
748 if (stat & 0x00000010) {
749 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] subc %d "
750 "class 0x%04x mthd 0x%04x data 0x%08x\n",
751 chid, inst, subc, class, mthd, data);
752 nv_wr32(dev, 0x400100, 0x00000010);
753 stat &= ~0x00000010;
754 }
755
756 if (stat & 0x00100000) {
757 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
758 nouveau_enum_print(nvc0_graph_data_error, code);
759 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
760 "mthd 0x%04x data 0x%08x\n",
761 chid, inst, subc, class, mthd, data);
762 nv_wr32(dev, 0x400100, 0x00100000);
763 stat &= ~0x00100000;
764 }
765
766 if (stat & 0x00080000) {
767 u32 ustat = nv_rd32(dev, 0x409c18);
768
769 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
770
771 nv_wr32(dev, 0x409c20, ustat);
772 nv_wr32(dev, 0x400100, 0x00080000);
773 stat &= ~0x00080000;
774 }
775
776 if (stat) {
777 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
778 nv_wr32(dev, 0x400100, stat);
779 }
780
781 nv_wr32(dev, 0x400500, 0x00010001);
782}
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.h b/drivers/gpu/drm/nouveau/nvc0_graph.h
new file mode 100644
index 000000000000..1e1f24f3fd34
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.h
@@ -0,0 +1,66 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifndef __NVC0_GRAPH_H__
26#define __NVC0_GRAPH_H__
27
28#define GPC_MAX 4
29#define TP_MAX 32
30
31#define ROP_BCAST(r) (0x408800 + (r))
32#define ROP_UNIT(u,r) (0x410000 + (u) * 0x400 + (r))
33#define GPC_BCAST(r) (0x418000 + (r))
34#define GPC_UNIT(t,r) (0x500000 + (t) * 0x8000 + (r))
35#define TP_UNIT(t,m,r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
36
37struct nvc0_graph_priv {
38 u8 gpc_nr;
39 u8 rop_nr;
40 u8 tp_nr[GPC_MAX];
41 u8 tp_total;
42
43 u32 grctx_size;
44 u32 *grctx_vals;
45 struct nouveau_gpuobj *unk4188b4;
46 struct nouveau_gpuobj *unk4188b8;
47
48 u8 magic_not_rop_nr;
49 u32 magic419bd0;
50 u32 magic419be4;
51 u32 magicgpc980[4];
52 u32 magicgpc918;
53};
54
55struct nvc0_graph_chan {
56 struct nouveau_gpuobj *grctx;
57 struct nouveau_gpuobj *unk408004; // 0x418810 too
58 struct nouveau_gpuobj *unk40800c; // 0x419004 too
59 struct nouveau_gpuobj *unk418810; // 0x419848 too
60 struct nouveau_gpuobj *mmio;
61 int mmio_nr;
62};
63
64int nvc0_grctx_generate(struct nouveau_channel *);
65
66#endif
diff --git a/drivers/gpu/drm/nouveau/nvc0_grctx.c b/drivers/gpu/drm/nouveau/nvc0_grctx.c
new file mode 100644
index 000000000000..88fa6211ac19
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_grctx.c
@@ -0,0 +1,2854 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_mm.h"
28#include "nvc0_graph.h"
29
30static void
31nv_icmd(struct drm_device *dev, u32 icmd, u32 data)
32{
33 nv_wr32(dev, 0x400204, data);
34 nv_wr32(dev, 0x400200, icmd);
35 while (nv_rd32(dev, 0x400700) & 2) {}
36}
37
38static void
39nv_mthd(struct drm_device *dev, u32 class, u32 mthd, u32 data)
40{
41 nv_wr32(dev, 0x40448c, data);
42 nv_wr32(dev, 0x404488, 0x80000000 | (mthd << 14) | class);
43}
44
45static void
46nvc0_grctx_generate_9097(struct drm_device *dev)
47{
48 nv_mthd(dev, 0x9097, 0x0800, 0x00000000);
49 nv_mthd(dev, 0x9097, 0x0840, 0x00000000);
50 nv_mthd(dev, 0x9097, 0x0880, 0x00000000);
51 nv_mthd(dev, 0x9097, 0x08c0, 0x00000000);
52 nv_mthd(dev, 0x9097, 0x0900, 0x00000000);
53 nv_mthd(dev, 0x9097, 0x0940, 0x00000000);
54 nv_mthd(dev, 0x9097, 0x0980, 0x00000000);
55 nv_mthd(dev, 0x9097, 0x09c0, 0x00000000);
56 nv_mthd(dev, 0x9097, 0x0804, 0x00000000);
57 nv_mthd(dev, 0x9097, 0x0844, 0x00000000);
58 nv_mthd(dev, 0x9097, 0x0884, 0x00000000);
59 nv_mthd(dev, 0x9097, 0x08c4, 0x00000000);
60 nv_mthd(dev, 0x9097, 0x0904, 0x00000000);
61 nv_mthd(dev, 0x9097, 0x0944, 0x00000000);
62 nv_mthd(dev, 0x9097, 0x0984, 0x00000000);
63 nv_mthd(dev, 0x9097, 0x09c4, 0x00000000);
64 nv_mthd(dev, 0x9097, 0x0808, 0x00000400);
65 nv_mthd(dev, 0x9097, 0x0848, 0x00000400);
66 nv_mthd(dev, 0x9097, 0x0888, 0x00000400);
67 nv_mthd(dev, 0x9097, 0x08c8, 0x00000400);
68 nv_mthd(dev, 0x9097, 0x0908, 0x00000400);
69 nv_mthd(dev, 0x9097, 0x0948, 0x00000400);
70 nv_mthd(dev, 0x9097, 0x0988, 0x00000400);
71 nv_mthd(dev, 0x9097, 0x09c8, 0x00000400);
72 nv_mthd(dev, 0x9097, 0x080c, 0x00000300);
73 nv_mthd(dev, 0x9097, 0x084c, 0x00000300);
74 nv_mthd(dev, 0x9097, 0x088c, 0x00000300);
75 nv_mthd(dev, 0x9097, 0x08cc, 0x00000300);
76 nv_mthd(dev, 0x9097, 0x090c, 0x00000300);
77 nv_mthd(dev, 0x9097, 0x094c, 0x00000300);
78 nv_mthd(dev, 0x9097, 0x098c, 0x00000300);
79 nv_mthd(dev, 0x9097, 0x09cc, 0x00000300);
80 nv_mthd(dev, 0x9097, 0x0810, 0x000000cf);
81 nv_mthd(dev, 0x9097, 0x0850, 0x00000000);
82 nv_mthd(dev, 0x9097, 0x0890, 0x00000000);
83 nv_mthd(dev, 0x9097, 0x08d0, 0x00000000);
84 nv_mthd(dev, 0x9097, 0x0910, 0x00000000);
85 nv_mthd(dev, 0x9097, 0x0950, 0x00000000);
86 nv_mthd(dev, 0x9097, 0x0990, 0x00000000);
87 nv_mthd(dev, 0x9097, 0x09d0, 0x00000000);
88 nv_mthd(dev, 0x9097, 0x0814, 0x00000040);
89 nv_mthd(dev, 0x9097, 0x0854, 0x00000040);
90 nv_mthd(dev, 0x9097, 0x0894, 0x00000040);
91 nv_mthd(dev, 0x9097, 0x08d4, 0x00000040);
92 nv_mthd(dev, 0x9097, 0x0914, 0x00000040);
93 nv_mthd(dev, 0x9097, 0x0954, 0x00000040);
94 nv_mthd(dev, 0x9097, 0x0994, 0x00000040);
95 nv_mthd(dev, 0x9097, 0x09d4, 0x00000040);
96 nv_mthd(dev, 0x9097, 0x0818, 0x00000001);
97 nv_mthd(dev, 0x9097, 0x0858, 0x00000001);
98 nv_mthd(dev, 0x9097, 0x0898, 0x00000001);
99 nv_mthd(dev, 0x9097, 0x08d8, 0x00000001);
100 nv_mthd(dev, 0x9097, 0x0918, 0x00000001);
101 nv_mthd(dev, 0x9097, 0x0958, 0x00000001);
102 nv_mthd(dev, 0x9097, 0x0998, 0x00000001);
103 nv_mthd(dev, 0x9097, 0x09d8, 0x00000001);
104 nv_mthd(dev, 0x9097, 0x081c, 0x00000000);
105 nv_mthd(dev, 0x9097, 0x085c, 0x00000000);
106 nv_mthd(dev, 0x9097, 0x089c, 0x00000000);
107 nv_mthd(dev, 0x9097, 0x08dc, 0x00000000);
108 nv_mthd(dev, 0x9097, 0x091c, 0x00000000);
109 nv_mthd(dev, 0x9097, 0x095c, 0x00000000);
110 nv_mthd(dev, 0x9097, 0x099c, 0x00000000);
111 nv_mthd(dev, 0x9097, 0x09dc, 0x00000000);
112 nv_mthd(dev, 0x9097, 0x0820, 0x00000000);
113 nv_mthd(dev, 0x9097, 0x0860, 0x00000000);
114 nv_mthd(dev, 0x9097, 0x08a0, 0x00000000);
115 nv_mthd(dev, 0x9097, 0x08e0, 0x00000000);
116 nv_mthd(dev, 0x9097, 0x0920, 0x00000000);
117 nv_mthd(dev, 0x9097, 0x0960, 0x00000000);
118 nv_mthd(dev, 0x9097, 0x09a0, 0x00000000);
119 nv_mthd(dev, 0x9097, 0x09e0, 0x00000000);
120 nv_mthd(dev, 0x9097, 0x2700, 0x00000000);
121 nv_mthd(dev, 0x9097, 0x2720, 0x00000000);
122 nv_mthd(dev, 0x9097, 0x2740, 0x00000000);
123 nv_mthd(dev, 0x9097, 0x2760, 0x00000000);
124 nv_mthd(dev, 0x9097, 0x2780, 0x00000000);
125 nv_mthd(dev, 0x9097, 0x27a0, 0x00000000);
126 nv_mthd(dev, 0x9097, 0x27c0, 0x00000000);
127 nv_mthd(dev, 0x9097, 0x27e0, 0x00000000);
128 nv_mthd(dev, 0x9097, 0x2704, 0x00000000);
129 nv_mthd(dev, 0x9097, 0x2724, 0x00000000);
130 nv_mthd(dev, 0x9097, 0x2744, 0x00000000);
131 nv_mthd(dev, 0x9097, 0x2764, 0x00000000);
132 nv_mthd(dev, 0x9097, 0x2784, 0x00000000);
133 nv_mthd(dev, 0x9097, 0x27a4, 0x00000000);
134 nv_mthd(dev, 0x9097, 0x27c4, 0x00000000);
135 nv_mthd(dev, 0x9097, 0x27e4, 0x00000000);
136 nv_mthd(dev, 0x9097, 0x2708, 0x00000000);
137 nv_mthd(dev, 0x9097, 0x2728, 0x00000000);
138 nv_mthd(dev, 0x9097, 0x2748, 0x00000000);
139 nv_mthd(dev, 0x9097, 0x2768, 0x00000000);
140 nv_mthd(dev, 0x9097, 0x2788, 0x00000000);
141 nv_mthd(dev, 0x9097, 0x27a8, 0x00000000);
142 nv_mthd(dev, 0x9097, 0x27c8, 0x00000000);
143 nv_mthd(dev, 0x9097, 0x27e8, 0x00000000);
144 nv_mthd(dev, 0x9097, 0x270c, 0x00000000);
145 nv_mthd(dev, 0x9097, 0x272c, 0x00000000);
146 nv_mthd(dev, 0x9097, 0x274c, 0x00000000);
147 nv_mthd(dev, 0x9097, 0x276c, 0x00000000);
148 nv_mthd(dev, 0x9097, 0x278c, 0x00000000);
149 nv_mthd(dev, 0x9097, 0x27ac, 0x00000000);
150 nv_mthd(dev, 0x9097, 0x27cc, 0x00000000);
151 nv_mthd(dev, 0x9097, 0x27ec, 0x00000000);
152 nv_mthd(dev, 0x9097, 0x2710, 0x00014000);
153 nv_mthd(dev, 0x9097, 0x2730, 0x00014000);
154 nv_mthd(dev, 0x9097, 0x2750, 0x00014000);
155 nv_mthd(dev, 0x9097, 0x2770, 0x00014000);
156 nv_mthd(dev, 0x9097, 0x2790, 0x00014000);
157 nv_mthd(dev, 0x9097, 0x27b0, 0x00014000);
158 nv_mthd(dev, 0x9097, 0x27d0, 0x00014000);
159 nv_mthd(dev, 0x9097, 0x27f0, 0x00014000);
160 nv_mthd(dev, 0x9097, 0x2714, 0x00000040);
161 nv_mthd(dev, 0x9097, 0x2734, 0x00000040);
162 nv_mthd(dev, 0x9097, 0x2754, 0x00000040);
163 nv_mthd(dev, 0x9097, 0x2774, 0x00000040);
164 nv_mthd(dev, 0x9097, 0x2794, 0x00000040);
165 nv_mthd(dev, 0x9097, 0x27b4, 0x00000040);
166 nv_mthd(dev, 0x9097, 0x27d4, 0x00000040);
167 nv_mthd(dev, 0x9097, 0x27f4, 0x00000040);
168 nv_mthd(dev, 0x9097, 0x1c00, 0x00000000);
169 nv_mthd(dev, 0x9097, 0x1c10, 0x00000000);
170 nv_mthd(dev, 0x9097, 0x1c20, 0x00000000);
171 nv_mthd(dev, 0x9097, 0x1c30, 0x00000000);
172 nv_mthd(dev, 0x9097, 0x1c40, 0x00000000);
173 nv_mthd(dev, 0x9097, 0x1c50, 0x00000000);
174 nv_mthd(dev, 0x9097, 0x1c60, 0x00000000);
175 nv_mthd(dev, 0x9097, 0x1c70, 0x00000000);
176 nv_mthd(dev, 0x9097, 0x1c80, 0x00000000);
177 nv_mthd(dev, 0x9097, 0x1c90, 0x00000000);
178 nv_mthd(dev, 0x9097, 0x1ca0, 0x00000000);
179 nv_mthd(dev, 0x9097, 0x1cb0, 0x00000000);
180 nv_mthd(dev, 0x9097, 0x1cc0, 0x00000000);
181 nv_mthd(dev, 0x9097, 0x1cd0, 0x00000000);
182 nv_mthd(dev, 0x9097, 0x1ce0, 0x00000000);
183 nv_mthd(dev, 0x9097, 0x1cf0, 0x00000000);
184 nv_mthd(dev, 0x9097, 0x1c04, 0x00000000);
185 nv_mthd(dev, 0x9097, 0x1c14, 0x00000000);
186 nv_mthd(dev, 0x9097, 0x1c24, 0x00000000);
187 nv_mthd(dev, 0x9097, 0x1c34, 0x00000000);
188 nv_mthd(dev, 0x9097, 0x1c44, 0x00000000);
189 nv_mthd(dev, 0x9097, 0x1c54, 0x00000000);
190 nv_mthd(dev, 0x9097, 0x1c64, 0x00000000);
191 nv_mthd(dev, 0x9097, 0x1c74, 0x00000000);
192 nv_mthd(dev, 0x9097, 0x1c84, 0x00000000);
193 nv_mthd(dev, 0x9097, 0x1c94, 0x00000000);
194 nv_mthd(dev, 0x9097, 0x1ca4, 0x00000000);
195 nv_mthd(dev, 0x9097, 0x1cb4, 0x00000000);
196 nv_mthd(dev, 0x9097, 0x1cc4, 0x00000000);
197 nv_mthd(dev, 0x9097, 0x1cd4, 0x00000000);
198 nv_mthd(dev, 0x9097, 0x1ce4, 0x00000000);
199 nv_mthd(dev, 0x9097, 0x1cf4, 0x00000000);
200 nv_mthd(dev, 0x9097, 0x1c08, 0x00000000);
201 nv_mthd(dev, 0x9097, 0x1c18, 0x00000000);
202 nv_mthd(dev, 0x9097, 0x1c28, 0x00000000);
203 nv_mthd(dev, 0x9097, 0x1c38, 0x00000000);
204 nv_mthd(dev, 0x9097, 0x1c48, 0x00000000);
205 nv_mthd(dev, 0x9097, 0x1c58, 0x00000000);
206 nv_mthd(dev, 0x9097, 0x1c68, 0x00000000);
207 nv_mthd(dev, 0x9097, 0x1c78, 0x00000000);
208 nv_mthd(dev, 0x9097, 0x1c88, 0x00000000);
209 nv_mthd(dev, 0x9097, 0x1c98, 0x00000000);
210 nv_mthd(dev, 0x9097, 0x1ca8, 0x00000000);
211 nv_mthd(dev, 0x9097, 0x1cb8, 0x00000000);
212 nv_mthd(dev, 0x9097, 0x1cc8, 0x00000000);
213 nv_mthd(dev, 0x9097, 0x1cd8, 0x00000000);
214 nv_mthd(dev, 0x9097, 0x1ce8, 0x00000000);
215 nv_mthd(dev, 0x9097, 0x1cf8, 0x00000000);
216 nv_mthd(dev, 0x9097, 0x1c0c, 0x00000000);
217 nv_mthd(dev, 0x9097, 0x1c1c, 0x00000000);
218 nv_mthd(dev, 0x9097, 0x1c2c, 0x00000000);
219 nv_mthd(dev, 0x9097, 0x1c3c, 0x00000000);
220 nv_mthd(dev, 0x9097, 0x1c4c, 0x00000000);
221 nv_mthd(dev, 0x9097, 0x1c5c, 0x00000000);
222 nv_mthd(dev, 0x9097, 0x1c6c, 0x00000000);
223 nv_mthd(dev, 0x9097, 0x1c7c, 0x00000000);
224 nv_mthd(dev, 0x9097, 0x1c8c, 0x00000000);
225 nv_mthd(dev, 0x9097, 0x1c9c, 0x00000000);
226 nv_mthd(dev, 0x9097, 0x1cac, 0x00000000);
227 nv_mthd(dev, 0x9097, 0x1cbc, 0x00000000);
228 nv_mthd(dev, 0x9097, 0x1ccc, 0x00000000);
229 nv_mthd(dev, 0x9097, 0x1cdc, 0x00000000);
230 nv_mthd(dev, 0x9097, 0x1cec, 0x00000000);
231 nv_mthd(dev, 0x9097, 0x1cfc, 0x00000000);
232 nv_mthd(dev, 0x9097, 0x1d00, 0x00000000);
233 nv_mthd(dev, 0x9097, 0x1d10, 0x00000000);
234 nv_mthd(dev, 0x9097, 0x1d20, 0x00000000);
235 nv_mthd(dev, 0x9097, 0x1d30, 0x00000000);
236 nv_mthd(dev, 0x9097, 0x1d40, 0x00000000);
237 nv_mthd(dev, 0x9097, 0x1d50, 0x00000000);
238 nv_mthd(dev, 0x9097, 0x1d60, 0x00000000);
239 nv_mthd(dev, 0x9097, 0x1d70, 0x00000000);
240 nv_mthd(dev, 0x9097, 0x1d80, 0x00000000);
241 nv_mthd(dev, 0x9097, 0x1d90, 0x00000000);
242 nv_mthd(dev, 0x9097, 0x1da0, 0x00000000);
243 nv_mthd(dev, 0x9097, 0x1db0, 0x00000000);
244 nv_mthd(dev, 0x9097, 0x1dc0, 0x00000000);
245 nv_mthd(dev, 0x9097, 0x1dd0, 0x00000000);
246 nv_mthd(dev, 0x9097, 0x1de0, 0x00000000);
247 nv_mthd(dev, 0x9097, 0x1df0, 0x00000000);
248 nv_mthd(dev, 0x9097, 0x1d04, 0x00000000);
249 nv_mthd(dev, 0x9097, 0x1d14, 0x00000000);
250 nv_mthd(dev, 0x9097, 0x1d24, 0x00000000);
251 nv_mthd(dev, 0x9097, 0x1d34, 0x00000000);
252 nv_mthd(dev, 0x9097, 0x1d44, 0x00000000);
253 nv_mthd(dev, 0x9097, 0x1d54, 0x00000000);
254 nv_mthd(dev, 0x9097, 0x1d64, 0x00000000);
255 nv_mthd(dev, 0x9097, 0x1d74, 0x00000000);
256 nv_mthd(dev, 0x9097, 0x1d84, 0x00000000);
257 nv_mthd(dev, 0x9097, 0x1d94, 0x00000000);
258 nv_mthd(dev, 0x9097, 0x1da4, 0x00000000);
259 nv_mthd(dev, 0x9097, 0x1db4, 0x00000000);
260 nv_mthd(dev, 0x9097, 0x1dc4, 0x00000000);
261 nv_mthd(dev, 0x9097, 0x1dd4, 0x00000000);
262 nv_mthd(dev, 0x9097, 0x1de4, 0x00000000);
263 nv_mthd(dev, 0x9097, 0x1df4, 0x00000000);
264 nv_mthd(dev, 0x9097, 0x1d08, 0x00000000);
265 nv_mthd(dev, 0x9097, 0x1d18, 0x00000000);
266 nv_mthd(dev, 0x9097, 0x1d28, 0x00000000);
267 nv_mthd(dev, 0x9097, 0x1d38, 0x00000000);
268 nv_mthd(dev, 0x9097, 0x1d48, 0x00000000);
269 nv_mthd(dev, 0x9097, 0x1d58, 0x00000000);
270 nv_mthd(dev, 0x9097, 0x1d68, 0x00000000);
271 nv_mthd(dev, 0x9097, 0x1d78, 0x00000000);
272 nv_mthd(dev, 0x9097, 0x1d88, 0x00000000);
273 nv_mthd(dev, 0x9097, 0x1d98, 0x00000000);
274 nv_mthd(dev, 0x9097, 0x1da8, 0x00000000);
275 nv_mthd(dev, 0x9097, 0x1db8, 0x00000000);
276 nv_mthd(dev, 0x9097, 0x1dc8, 0x00000000);
277 nv_mthd(dev, 0x9097, 0x1dd8, 0x00000000);
278 nv_mthd(dev, 0x9097, 0x1de8, 0x00000000);
279 nv_mthd(dev, 0x9097, 0x1df8, 0x00000000);
280 nv_mthd(dev, 0x9097, 0x1d0c, 0x00000000);
281 nv_mthd(dev, 0x9097, 0x1d1c, 0x00000000);
282 nv_mthd(dev, 0x9097, 0x1d2c, 0x00000000);
283 nv_mthd(dev, 0x9097, 0x1d3c, 0x00000000);
284 nv_mthd(dev, 0x9097, 0x1d4c, 0x00000000);
285 nv_mthd(dev, 0x9097, 0x1d5c, 0x00000000);
286 nv_mthd(dev, 0x9097, 0x1d6c, 0x00000000);
287 nv_mthd(dev, 0x9097, 0x1d7c, 0x00000000);
288 nv_mthd(dev, 0x9097, 0x1d8c, 0x00000000);
289 nv_mthd(dev, 0x9097, 0x1d9c, 0x00000000);
290 nv_mthd(dev, 0x9097, 0x1dac, 0x00000000);
291 nv_mthd(dev, 0x9097, 0x1dbc, 0x00000000);
292 nv_mthd(dev, 0x9097, 0x1dcc, 0x00000000);
293 nv_mthd(dev, 0x9097, 0x1ddc, 0x00000000);
294 nv_mthd(dev, 0x9097, 0x1dec, 0x00000000);
295 nv_mthd(dev, 0x9097, 0x1dfc, 0x00000000);
296 nv_mthd(dev, 0x9097, 0x1f00, 0x00000000);
297 nv_mthd(dev, 0x9097, 0x1f08, 0x00000000);
298 nv_mthd(dev, 0x9097, 0x1f10, 0x00000000);
299 nv_mthd(dev, 0x9097, 0x1f18, 0x00000000);
300 nv_mthd(dev, 0x9097, 0x1f20, 0x00000000);
301 nv_mthd(dev, 0x9097, 0x1f28, 0x00000000);
302 nv_mthd(dev, 0x9097, 0x1f30, 0x00000000);
303 nv_mthd(dev, 0x9097, 0x1f38, 0x00000000);
304 nv_mthd(dev, 0x9097, 0x1f40, 0x00000000);
305 nv_mthd(dev, 0x9097, 0x1f48, 0x00000000);
306 nv_mthd(dev, 0x9097, 0x1f50, 0x00000000);
307 nv_mthd(dev, 0x9097, 0x1f58, 0x00000000);
308 nv_mthd(dev, 0x9097, 0x1f60, 0x00000000);
309 nv_mthd(dev, 0x9097, 0x1f68, 0x00000000);
310 nv_mthd(dev, 0x9097, 0x1f70, 0x00000000);
311 nv_mthd(dev, 0x9097, 0x1f78, 0x00000000);
312 nv_mthd(dev, 0x9097, 0x1f04, 0x00000000);
313 nv_mthd(dev, 0x9097, 0x1f0c, 0x00000000);
314 nv_mthd(dev, 0x9097, 0x1f14, 0x00000000);
315 nv_mthd(dev, 0x9097, 0x1f1c, 0x00000000);
316 nv_mthd(dev, 0x9097, 0x1f24, 0x00000000);
317 nv_mthd(dev, 0x9097, 0x1f2c, 0x00000000);
318 nv_mthd(dev, 0x9097, 0x1f34, 0x00000000);
319 nv_mthd(dev, 0x9097, 0x1f3c, 0x00000000);
320 nv_mthd(dev, 0x9097, 0x1f44, 0x00000000);
321 nv_mthd(dev, 0x9097, 0x1f4c, 0x00000000);
322 nv_mthd(dev, 0x9097, 0x1f54, 0x00000000);
323 nv_mthd(dev, 0x9097, 0x1f5c, 0x00000000);
324 nv_mthd(dev, 0x9097, 0x1f64, 0x00000000);
325 nv_mthd(dev, 0x9097, 0x1f6c, 0x00000000);
326 nv_mthd(dev, 0x9097, 0x1f74, 0x00000000);
327 nv_mthd(dev, 0x9097, 0x1f7c, 0x00000000);
328 nv_mthd(dev, 0x9097, 0x1f80, 0x00000000);
329 nv_mthd(dev, 0x9097, 0x1f88, 0x00000000);
330 nv_mthd(dev, 0x9097, 0x1f90, 0x00000000);
331 nv_mthd(dev, 0x9097, 0x1f98, 0x00000000);
332 nv_mthd(dev, 0x9097, 0x1fa0, 0x00000000);
333 nv_mthd(dev, 0x9097, 0x1fa8, 0x00000000);
334 nv_mthd(dev, 0x9097, 0x1fb0, 0x00000000);
335 nv_mthd(dev, 0x9097, 0x1fb8, 0x00000000);
336 nv_mthd(dev, 0x9097, 0x1fc0, 0x00000000);
337 nv_mthd(dev, 0x9097, 0x1fc8, 0x00000000);
338 nv_mthd(dev, 0x9097, 0x1fd0, 0x00000000);
339 nv_mthd(dev, 0x9097, 0x1fd8, 0x00000000);
340 nv_mthd(dev, 0x9097, 0x1fe0, 0x00000000);
341 nv_mthd(dev, 0x9097, 0x1fe8, 0x00000000);
342 nv_mthd(dev, 0x9097, 0x1ff0, 0x00000000);
343 nv_mthd(dev, 0x9097, 0x1ff8, 0x00000000);
344 nv_mthd(dev, 0x9097, 0x1f84, 0x00000000);
345 nv_mthd(dev, 0x9097, 0x1f8c, 0x00000000);
346 nv_mthd(dev, 0x9097, 0x1f94, 0x00000000);
347 nv_mthd(dev, 0x9097, 0x1f9c, 0x00000000);
348 nv_mthd(dev, 0x9097, 0x1fa4, 0x00000000);
349 nv_mthd(dev, 0x9097, 0x1fac, 0x00000000);
350 nv_mthd(dev, 0x9097, 0x1fb4, 0x00000000);
351 nv_mthd(dev, 0x9097, 0x1fbc, 0x00000000);
352 nv_mthd(dev, 0x9097, 0x1fc4, 0x00000000);
353 nv_mthd(dev, 0x9097, 0x1fcc, 0x00000000);
354 nv_mthd(dev, 0x9097, 0x1fd4, 0x00000000);
355 nv_mthd(dev, 0x9097, 0x1fdc, 0x00000000);
356 nv_mthd(dev, 0x9097, 0x1fe4, 0x00000000);
357 nv_mthd(dev, 0x9097, 0x1fec, 0x00000000);
358 nv_mthd(dev, 0x9097, 0x1ff4, 0x00000000);
359 nv_mthd(dev, 0x9097, 0x1ffc, 0x00000000);
360 nv_mthd(dev, 0x9097, 0x2200, 0x00000022);
361 nv_mthd(dev, 0x9097, 0x2210, 0x00000022);
362 nv_mthd(dev, 0x9097, 0x2220, 0x00000022);
363 nv_mthd(dev, 0x9097, 0x2230, 0x00000022);
364 nv_mthd(dev, 0x9097, 0x2240, 0x00000022);
365 nv_mthd(dev, 0x9097, 0x2000, 0x00000000);
366 nv_mthd(dev, 0x9097, 0x2040, 0x00000011);
367 nv_mthd(dev, 0x9097, 0x2080, 0x00000020);
368 nv_mthd(dev, 0x9097, 0x20c0, 0x00000030);
369 nv_mthd(dev, 0x9097, 0x2100, 0x00000040);
370 nv_mthd(dev, 0x9097, 0x2140, 0x00000051);
371 nv_mthd(dev, 0x9097, 0x200c, 0x00000001);
372 nv_mthd(dev, 0x9097, 0x204c, 0x00000001);
373 nv_mthd(dev, 0x9097, 0x208c, 0x00000001);
374 nv_mthd(dev, 0x9097, 0x20cc, 0x00000001);
375 nv_mthd(dev, 0x9097, 0x210c, 0x00000001);
376 nv_mthd(dev, 0x9097, 0x214c, 0x00000001);
377 nv_mthd(dev, 0x9097, 0x2010, 0x00000000);
378 nv_mthd(dev, 0x9097, 0x2050, 0x00000000);
379 nv_mthd(dev, 0x9097, 0x2090, 0x00000001);
380 nv_mthd(dev, 0x9097, 0x20d0, 0x00000002);
381 nv_mthd(dev, 0x9097, 0x2110, 0x00000003);
382 nv_mthd(dev, 0x9097, 0x2150, 0x00000004);
383 nv_mthd(dev, 0x9097, 0x0380, 0x00000000);
384 nv_mthd(dev, 0x9097, 0x03a0, 0x00000000);
385 nv_mthd(dev, 0x9097, 0x03c0, 0x00000000);
386 nv_mthd(dev, 0x9097, 0x03e0, 0x00000000);
387 nv_mthd(dev, 0x9097, 0x0384, 0x00000000);
388 nv_mthd(dev, 0x9097, 0x03a4, 0x00000000);
389 nv_mthd(dev, 0x9097, 0x03c4, 0x00000000);
390 nv_mthd(dev, 0x9097, 0x03e4, 0x00000000);
391 nv_mthd(dev, 0x9097, 0x0388, 0x00000000);
392 nv_mthd(dev, 0x9097, 0x03a8, 0x00000000);
393 nv_mthd(dev, 0x9097, 0x03c8, 0x00000000);
394 nv_mthd(dev, 0x9097, 0x03e8, 0x00000000);
395 nv_mthd(dev, 0x9097, 0x038c, 0x00000000);
396 nv_mthd(dev, 0x9097, 0x03ac, 0x00000000);
397 nv_mthd(dev, 0x9097, 0x03cc, 0x00000000);
398 nv_mthd(dev, 0x9097, 0x03ec, 0x00000000);
399 nv_mthd(dev, 0x9097, 0x0700, 0x00000000);
400 nv_mthd(dev, 0x9097, 0x0710, 0x00000000);
401 nv_mthd(dev, 0x9097, 0x0720, 0x00000000);
402 nv_mthd(dev, 0x9097, 0x0730, 0x00000000);
403 nv_mthd(dev, 0x9097, 0x0704, 0x00000000);
404 nv_mthd(dev, 0x9097, 0x0714, 0x00000000);
405 nv_mthd(dev, 0x9097, 0x0724, 0x00000000);
406 nv_mthd(dev, 0x9097, 0x0734, 0x00000000);
407 nv_mthd(dev, 0x9097, 0x0708, 0x00000000);
408 nv_mthd(dev, 0x9097, 0x0718, 0x00000000);
409 nv_mthd(dev, 0x9097, 0x0728, 0x00000000);
410 nv_mthd(dev, 0x9097, 0x0738, 0x00000000);
411 nv_mthd(dev, 0x9097, 0x2800, 0x00000000);
412 nv_mthd(dev, 0x9097, 0x2804, 0x00000000);
413 nv_mthd(dev, 0x9097, 0x2808, 0x00000000);
414 nv_mthd(dev, 0x9097, 0x280c, 0x00000000);
415 nv_mthd(dev, 0x9097, 0x2810, 0x00000000);
416 nv_mthd(dev, 0x9097, 0x2814, 0x00000000);
417 nv_mthd(dev, 0x9097, 0x2818, 0x00000000);
418 nv_mthd(dev, 0x9097, 0x281c, 0x00000000);
419 nv_mthd(dev, 0x9097, 0x2820, 0x00000000);
420 nv_mthd(dev, 0x9097, 0x2824, 0x00000000);
421 nv_mthd(dev, 0x9097, 0x2828, 0x00000000);
422 nv_mthd(dev, 0x9097, 0x282c, 0x00000000);
423 nv_mthd(dev, 0x9097, 0x2830, 0x00000000);
424 nv_mthd(dev, 0x9097, 0x2834, 0x00000000);
425 nv_mthd(dev, 0x9097, 0x2838, 0x00000000);
426 nv_mthd(dev, 0x9097, 0x283c, 0x00000000);
427 nv_mthd(dev, 0x9097, 0x2840, 0x00000000);
428 nv_mthd(dev, 0x9097, 0x2844, 0x00000000);
429 nv_mthd(dev, 0x9097, 0x2848, 0x00000000);
430 nv_mthd(dev, 0x9097, 0x284c, 0x00000000);
431 nv_mthd(dev, 0x9097, 0x2850, 0x00000000);
432 nv_mthd(dev, 0x9097, 0x2854, 0x00000000);
433 nv_mthd(dev, 0x9097, 0x2858, 0x00000000);
434 nv_mthd(dev, 0x9097, 0x285c, 0x00000000);
435 nv_mthd(dev, 0x9097, 0x2860, 0x00000000);
436 nv_mthd(dev, 0x9097, 0x2864, 0x00000000);
437 nv_mthd(dev, 0x9097, 0x2868, 0x00000000);
438 nv_mthd(dev, 0x9097, 0x286c, 0x00000000);
439 nv_mthd(dev, 0x9097, 0x2870, 0x00000000);
440 nv_mthd(dev, 0x9097, 0x2874, 0x00000000);
441 nv_mthd(dev, 0x9097, 0x2878, 0x00000000);
442 nv_mthd(dev, 0x9097, 0x287c, 0x00000000);
443 nv_mthd(dev, 0x9097, 0x2880, 0x00000000);
444 nv_mthd(dev, 0x9097, 0x2884, 0x00000000);
445 nv_mthd(dev, 0x9097, 0x2888, 0x00000000);
446 nv_mthd(dev, 0x9097, 0x288c, 0x00000000);
447 nv_mthd(dev, 0x9097, 0x2890, 0x00000000);
448 nv_mthd(dev, 0x9097, 0x2894, 0x00000000);
449 nv_mthd(dev, 0x9097, 0x2898, 0x00000000);
450 nv_mthd(dev, 0x9097, 0x289c, 0x00000000);
451 nv_mthd(dev, 0x9097, 0x28a0, 0x00000000);
452 nv_mthd(dev, 0x9097, 0x28a4, 0x00000000);
453 nv_mthd(dev, 0x9097, 0x28a8, 0x00000000);
454 nv_mthd(dev, 0x9097, 0x28ac, 0x00000000);
455 nv_mthd(dev, 0x9097, 0x28b0, 0x00000000);
456 nv_mthd(dev, 0x9097, 0x28b4, 0x00000000);
457 nv_mthd(dev, 0x9097, 0x28b8, 0x00000000);
458 nv_mthd(dev, 0x9097, 0x28bc, 0x00000000);
459 nv_mthd(dev, 0x9097, 0x28c0, 0x00000000);
460 nv_mthd(dev, 0x9097, 0x28c4, 0x00000000);
461 nv_mthd(dev, 0x9097, 0x28c8, 0x00000000);
462 nv_mthd(dev, 0x9097, 0x28cc, 0x00000000);
463 nv_mthd(dev, 0x9097, 0x28d0, 0x00000000);
464 nv_mthd(dev, 0x9097, 0x28d4, 0x00000000);
465 nv_mthd(dev, 0x9097, 0x28d8, 0x00000000);
466 nv_mthd(dev, 0x9097, 0x28dc, 0x00000000);
467 nv_mthd(dev, 0x9097, 0x28e0, 0x00000000);
468 nv_mthd(dev, 0x9097, 0x28e4, 0x00000000);
469 nv_mthd(dev, 0x9097, 0x28e8, 0x00000000);
470 nv_mthd(dev, 0x9097, 0x28ec, 0x00000000);
471 nv_mthd(dev, 0x9097, 0x28f0, 0x00000000);
472 nv_mthd(dev, 0x9097, 0x28f4, 0x00000000);
473 nv_mthd(dev, 0x9097, 0x28f8, 0x00000000);
474 nv_mthd(dev, 0x9097, 0x28fc, 0x00000000);
475 nv_mthd(dev, 0x9097, 0x2900, 0x00000000);
476 nv_mthd(dev, 0x9097, 0x2904, 0x00000000);
477 nv_mthd(dev, 0x9097, 0x2908, 0x00000000);
478 nv_mthd(dev, 0x9097, 0x290c, 0x00000000);
479 nv_mthd(dev, 0x9097, 0x2910, 0x00000000);
480 nv_mthd(dev, 0x9097, 0x2914, 0x00000000);
481 nv_mthd(dev, 0x9097, 0x2918, 0x00000000);
482 nv_mthd(dev, 0x9097, 0x291c, 0x00000000);
483 nv_mthd(dev, 0x9097, 0x2920, 0x00000000);
484 nv_mthd(dev, 0x9097, 0x2924, 0x00000000);
485 nv_mthd(dev, 0x9097, 0x2928, 0x00000000);
486 nv_mthd(dev, 0x9097, 0x292c, 0x00000000);
487 nv_mthd(dev, 0x9097, 0x2930, 0x00000000);
488 nv_mthd(dev, 0x9097, 0x2934, 0x00000000);
489 nv_mthd(dev, 0x9097, 0x2938, 0x00000000);
490 nv_mthd(dev, 0x9097, 0x293c, 0x00000000);
491 nv_mthd(dev, 0x9097, 0x2940, 0x00000000);
492 nv_mthd(dev, 0x9097, 0x2944, 0x00000000);
493 nv_mthd(dev, 0x9097, 0x2948, 0x00000000);
494 nv_mthd(dev, 0x9097, 0x294c, 0x00000000);
495 nv_mthd(dev, 0x9097, 0x2950, 0x00000000);
496 nv_mthd(dev, 0x9097, 0x2954, 0x00000000);
497 nv_mthd(dev, 0x9097, 0x2958, 0x00000000);
498 nv_mthd(dev, 0x9097, 0x295c, 0x00000000);
499 nv_mthd(dev, 0x9097, 0x2960, 0x00000000);
500 nv_mthd(dev, 0x9097, 0x2964, 0x00000000);
501 nv_mthd(dev, 0x9097, 0x2968, 0x00000000);
502 nv_mthd(dev, 0x9097, 0x296c, 0x00000000);
503 nv_mthd(dev, 0x9097, 0x2970, 0x00000000);
504 nv_mthd(dev, 0x9097, 0x2974, 0x00000000);
505 nv_mthd(dev, 0x9097, 0x2978, 0x00000000);
506 nv_mthd(dev, 0x9097, 0x297c, 0x00000000);
507 nv_mthd(dev, 0x9097, 0x2980, 0x00000000);
508 nv_mthd(dev, 0x9097, 0x2984, 0x00000000);
509 nv_mthd(dev, 0x9097, 0x2988, 0x00000000);
510 nv_mthd(dev, 0x9097, 0x298c, 0x00000000);
511 nv_mthd(dev, 0x9097, 0x2990, 0x00000000);
512 nv_mthd(dev, 0x9097, 0x2994, 0x00000000);
513 nv_mthd(dev, 0x9097, 0x2998, 0x00000000);
514 nv_mthd(dev, 0x9097, 0x299c, 0x00000000);
515 nv_mthd(dev, 0x9097, 0x29a0, 0x00000000);
516 nv_mthd(dev, 0x9097, 0x29a4, 0x00000000);
517 nv_mthd(dev, 0x9097, 0x29a8, 0x00000000);
518 nv_mthd(dev, 0x9097, 0x29ac, 0x00000000);
519 nv_mthd(dev, 0x9097, 0x29b0, 0x00000000);
520 nv_mthd(dev, 0x9097, 0x29b4, 0x00000000);
521 nv_mthd(dev, 0x9097, 0x29b8, 0x00000000);
522 nv_mthd(dev, 0x9097, 0x29bc, 0x00000000);
523 nv_mthd(dev, 0x9097, 0x29c0, 0x00000000);
524 nv_mthd(dev, 0x9097, 0x29c4, 0x00000000);
525 nv_mthd(dev, 0x9097, 0x29c8, 0x00000000);
526 nv_mthd(dev, 0x9097, 0x29cc, 0x00000000);
527 nv_mthd(dev, 0x9097, 0x29d0, 0x00000000);
528 nv_mthd(dev, 0x9097, 0x29d4, 0x00000000);
529 nv_mthd(dev, 0x9097, 0x29d8, 0x00000000);
530 nv_mthd(dev, 0x9097, 0x29dc, 0x00000000);
531 nv_mthd(dev, 0x9097, 0x29e0, 0x00000000);
532 nv_mthd(dev, 0x9097, 0x29e4, 0x00000000);
533 nv_mthd(dev, 0x9097, 0x29e8, 0x00000000);
534 nv_mthd(dev, 0x9097, 0x29ec, 0x00000000);
535 nv_mthd(dev, 0x9097, 0x29f0, 0x00000000);
536 nv_mthd(dev, 0x9097, 0x29f4, 0x00000000);
537 nv_mthd(dev, 0x9097, 0x29f8, 0x00000000);
538 nv_mthd(dev, 0x9097, 0x29fc, 0x00000000);
539 nv_mthd(dev, 0x9097, 0x0a00, 0x00000000);
540 nv_mthd(dev, 0x9097, 0x0a20, 0x00000000);
541 nv_mthd(dev, 0x9097, 0x0a40, 0x00000000);
542 nv_mthd(dev, 0x9097, 0x0a60, 0x00000000);
543 nv_mthd(dev, 0x9097, 0x0a80, 0x00000000);
544 nv_mthd(dev, 0x9097, 0x0aa0, 0x00000000);
545 nv_mthd(dev, 0x9097, 0x0ac0, 0x00000000);
546 nv_mthd(dev, 0x9097, 0x0ae0, 0x00000000);
547 nv_mthd(dev, 0x9097, 0x0b00, 0x00000000);
548 nv_mthd(dev, 0x9097, 0x0b20, 0x00000000);
549 nv_mthd(dev, 0x9097, 0x0b40, 0x00000000);
550 nv_mthd(dev, 0x9097, 0x0b60, 0x00000000);
551 nv_mthd(dev, 0x9097, 0x0b80, 0x00000000);
552 nv_mthd(dev, 0x9097, 0x0ba0, 0x00000000);
553 nv_mthd(dev, 0x9097, 0x0bc0, 0x00000000);
554 nv_mthd(dev, 0x9097, 0x0be0, 0x00000000);
555 nv_mthd(dev, 0x9097, 0x0a04, 0x00000000);
556 nv_mthd(dev, 0x9097, 0x0a24, 0x00000000);
557 nv_mthd(dev, 0x9097, 0x0a44, 0x00000000);
558 nv_mthd(dev, 0x9097, 0x0a64, 0x00000000);
559 nv_mthd(dev, 0x9097, 0x0a84, 0x00000000);
560 nv_mthd(dev, 0x9097, 0x0aa4, 0x00000000);
561 nv_mthd(dev, 0x9097, 0x0ac4, 0x00000000);
562 nv_mthd(dev, 0x9097, 0x0ae4, 0x00000000);
563 nv_mthd(dev, 0x9097, 0x0b04, 0x00000000);
564 nv_mthd(dev, 0x9097, 0x0b24, 0x00000000);
565 nv_mthd(dev, 0x9097, 0x0b44, 0x00000000);
566 nv_mthd(dev, 0x9097, 0x0b64, 0x00000000);
567 nv_mthd(dev, 0x9097, 0x0b84, 0x00000000);
568 nv_mthd(dev, 0x9097, 0x0ba4, 0x00000000);
569 nv_mthd(dev, 0x9097, 0x0bc4, 0x00000000);
570 nv_mthd(dev, 0x9097, 0x0be4, 0x00000000);
571 nv_mthd(dev, 0x9097, 0x0a08, 0x00000000);
572 nv_mthd(dev, 0x9097, 0x0a28, 0x00000000);
573 nv_mthd(dev, 0x9097, 0x0a48, 0x00000000);
574 nv_mthd(dev, 0x9097, 0x0a68, 0x00000000);
575 nv_mthd(dev, 0x9097, 0x0a88, 0x00000000);
576 nv_mthd(dev, 0x9097, 0x0aa8, 0x00000000);
577 nv_mthd(dev, 0x9097, 0x0ac8, 0x00000000);
578 nv_mthd(dev, 0x9097, 0x0ae8, 0x00000000);
579 nv_mthd(dev, 0x9097, 0x0b08, 0x00000000);
580 nv_mthd(dev, 0x9097, 0x0b28, 0x00000000);
581 nv_mthd(dev, 0x9097, 0x0b48, 0x00000000);
582 nv_mthd(dev, 0x9097, 0x0b68, 0x00000000);
583 nv_mthd(dev, 0x9097, 0x0b88, 0x00000000);
584 nv_mthd(dev, 0x9097, 0x0ba8, 0x00000000);
585 nv_mthd(dev, 0x9097, 0x0bc8, 0x00000000);
586 nv_mthd(dev, 0x9097, 0x0be8, 0x00000000);
587 nv_mthd(dev, 0x9097, 0x0a0c, 0x00000000);
588 nv_mthd(dev, 0x9097, 0x0a2c, 0x00000000);
589 nv_mthd(dev, 0x9097, 0x0a4c, 0x00000000);
590 nv_mthd(dev, 0x9097, 0x0a6c, 0x00000000);
591 nv_mthd(dev, 0x9097, 0x0a8c, 0x00000000);
592 nv_mthd(dev, 0x9097, 0x0aac, 0x00000000);
593 nv_mthd(dev, 0x9097, 0x0acc, 0x00000000);
594 nv_mthd(dev, 0x9097, 0x0aec, 0x00000000);
595 nv_mthd(dev, 0x9097, 0x0b0c, 0x00000000);
596 nv_mthd(dev, 0x9097, 0x0b2c, 0x00000000);
597 nv_mthd(dev, 0x9097, 0x0b4c, 0x00000000);
598 nv_mthd(dev, 0x9097, 0x0b6c, 0x00000000);
599 nv_mthd(dev, 0x9097, 0x0b8c, 0x00000000);
600 nv_mthd(dev, 0x9097, 0x0bac, 0x00000000);
601 nv_mthd(dev, 0x9097, 0x0bcc, 0x00000000);
602 nv_mthd(dev, 0x9097, 0x0bec, 0x00000000);
603 nv_mthd(dev, 0x9097, 0x0a10, 0x00000000);
604 nv_mthd(dev, 0x9097, 0x0a30, 0x00000000);
605 nv_mthd(dev, 0x9097, 0x0a50, 0x00000000);
606 nv_mthd(dev, 0x9097, 0x0a70, 0x00000000);
607 nv_mthd(dev, 0x9097, 0x0a90, 0x00000000);
608 nv_mthd(dev, 0x9097, 0x0ab0, 0x00000000);
609 nv_mthd(dev, 0x9097, 0x0ad0, 0x00000000);
610 nv_mthd(dev, 0x9097, 0x0af0, 0x00000000);
611 nv_mthd(dev, 0x9097, 0x0b10, 0x00000000);
612 nv_mthd(dev, 0x9097, 0x0b30, 0x00000000);
613 nv_mthd(dev, 0x9097, 0x0b50, 0x00000000);
614 nv_mthd(dev, 0x9097, 0x0b70, 0x00000000);
615 nv_mthd(dev, 0x9097, 0x0b90, 0x00000000);
616 nv_mthd(dev, 0x9097, 0x0bb0, 0x00000000);
617 nv_mthd(dev, 0x9097, 0x0bd0, 0x00000000);
618 nv_mthd(dev, 0x9097, 0x0bf0, 0x00000000);
619 nv_mthd(dev, 0x9097, 0x0a14, 0x00000000);
620 nv_mthd(dev, 0x9097, 0x0a34, 0x00000000);
621 nv_mthd(dev, 0x9097, 0x0a54, 0x00000000);
622 nv_mthd(dev, 0x9097, 0x0a74, 0x00000000);
623 nv_mthd(dev, 0x9097, 0x0a94, 0x00000000);
624 nv_mthd(dev, 0x9097, 0x0ab4, 0x00000000);
625 nv_mthd(dev, 0x9097, 0x0ad4, 0x00000000);
626 nv_mthd(dev, 0x9097, 0x0af4, 0x00000000);
627 nv_mthd(dev, 0x9097, 0x0b14, 0x00000000);
628 nv_mthd(dev, 0x9097, 0x0b34, 0x00000000);
629 nv_mthd(dev, 0x9097, 0x0b54, 0x00000000);
630 nv_mthd(dev, 0x9097, 0x0b74, 0x00000000);
631 nv_mthd(dev, 0x9097, 0x0b94, 0x00000000);
632 nv_mthd(dev, 0x9097, 0x0bb4, 0x00000000);
633 nv_mthd(dev, 0x9097, 0x0bd4, 0x00000000);
634 nv_mthd(dev, 0x9097, 0x0bf4, 0x00000000);
635 nv_mthd(dev, 0x9097, 0x0c00, 0x00000000);
636 nv_mthd(dev, 0x9097, 0x0c10, 0x00000000);
637 nv_mthd(dev, 0x9097, 0x0c20, 0x00000000);
638 nv_mthd(dev, 0x9097, 0x0c30, 0x00000000);
639 nv_mthd(dev, 0x9097, 0x0c40, 0x00000000);
640 nv_mthd(dev, 0x9097, 0x0c50, 0x00000000);
641 nv_mthd(dev, 0x9097, 0x0c60, 0x00000000);
642 nv_mthd(dev, 0x9097, 0x0c70, 0x00000000);
643 nv_mthd(dev, 0x9097, 0x0c80, 0x00000000);
644 nv_mthd(dev, 0x9097, 0x0c90, 0x00000000);
645 nv_mthd(dev, 0x9097, 0x0ca0, 0x00000000);
646 nv_mthd(dev, 0x9097, 0x0cb0, 0x00000000);
647 nv_mthd(dev, 0x9097, 0x0cc0, 0x00000000);
648 nv_mthd(dev, 0x9097, 0x0cd0, 0x00000000);
649 nv_mthd(dev, 0x9097, 0x0ce0, 0x00000000);
650 nv_mthd(dev, 0x9097, 0x0cf0, 0x00000000);
651 nv_mthd(dev, 0x9097, 0x0c04, 0x00000000);
652 nv_mthd(dev, 0x9097, 0x0c14, 0x00000000);
653 nv_mthd(dev, 0x9097, 0x0c24, 0x00000000);
654 nv_mthd(dev, 0x9097, 0x0c34, 0x00000000);
655 nv_mthd(dev, 0x9097, 0x0c44, 0x00000000);
656 nv_mthd(dev, 0x9097, 0x0c54, 0x00000000);
657 nv_mthd(dev, 0x9097, 0x0c64, 0x00000000);
658 nv_mthd(dev, 0x9097, 0x0c74, 0x00000000);
659 nv_mthd(dev, 0x9097, 0x0c84, 0x00000000);
660 nv_mthd(dev, 0x9097, 0x0c94, 0x00000000);
661 nv_mthd(dev, 0x9097, 0x0ca4, 0x00000000);
662 nv_mthd(dev, 0x9097, 0x0cb4, 0x00000000);
663 nv_mthd(dev, 0x9097, 0x0cc4, 0x00000000);
664 nv_mthd(dev, 0x9097, 0x0cd4, 0x00000000);
665 nv_mthd(dev, 0x9097, 0x0ce4, 0x00000000);
666 nv_mthd(dev, 0x9097, 0x0cf4, 0x00000000);
667 nv_mthd(dev, 0x9097, 0x0c08, 0x00000000);
668 nv_mthd(dev, 0x9097, 0x0c18, 0x00000000);
669 nv_mthd(dev, 0x9097, 0x0c28, 0x00000000);
670 nv_mthd(dev, 0x9097, 0x0c38, 0x00000000);
671 nv_mthd(dev, 0x9097, 0x0c48, 0x00000000);
672 nv_mthd(dev, 0x9097, 0x0c58, 0x00000000);
673 nv_mthd(dev, 0x9097, 0x0c68, 0x00000000);
674 nv_mthd(dev, 0x9097, 0x0c78, 0x00000000);
675 nv_mthd(dev, 0x9097, 0x0c88, 0x00000000);
676 nv_mthd(dev, 0x9097, 0x0c98, 0x00000000);
677 nv_mthd(dev, 0x9097, 0x0ca8, 0x00000000);
678 nv_mthd(dev, 0x9097, 0x0cb8, 0x00000000);
679 nv_mthd(dev, 0x9097, 0x0cc8, 0x00000000);
680 nv_mthd(dev, 0x9097, 0x0cd8, 0x00000000);
681 nv_mthd(dev, 0x9097, 0x0ce8, 0x00000000);
682 nv_mthd(dev, 0x9097, 0x0cf8, 0x00000000);
683 nv_mthd(dev, 0x9097, 0x0c0c, 0x3f800000);
684 nv_mthd(dev, 0x9097, 0x0c1c, 0x3f800000);
685 nv_mthd(dev, 0x9097, 0x0c2c, 0x3f800000);
686 nv_mthd(dev, 0x9097, 0x0c3c, 0x3f800000);
687 nv_mthd(dev, 0x9097, 0x0c4c, 0x3f800000);
688 nv_mthd(dev, 0x9097, 0x0c5c, 0x3f800000);
689 nv_mthd(dev, 0x9097, 0x0c6c, 0x3f800000);
690 nv_mthd(dev, 0x9097, 0x0c7c, 0x3f800000);
691 nv_mthd(dev, 0x9097, 0x0c8c, 0x3f800000);
692 nv_mthd(dev, 0x9097, 0x0c9c, 0x3f800000);
693 nv_mthd(dev, 0x9097, 0x0cac, 0x3f800000);
694 nv_mthd(dev, 0x9097, 0x0cbc, 0x3f800000);
695 nv_mthd(dev, 0x9097, 0x0ccc, 0x3f800000);
696 nv_mthd(dev, 0x9097, 0x0cdc, 0x3f800000);
697 nv_mthd(dev, 0x9097, 0x0cec, 0x3f800000);
698 nv_mthd(dev, 0x9097, 0x0cfc, 0x3f800000);
699 nv_mthd(dev, 0x9097, 0x0d00, 0xffff0000);
700 nv_mthd(dev, 0x9097, 0x0d08, 0xffff0000);
701 nv_mthd(dev, 0x9097, 0x0d10, 0xffff0000);
702 nv_mthd(dev, 0x9097, 0x0d18, 0xffff0000);
703 nv_mthd(dev, 0x9097, 0x0d20, 0xffff0000);
704 nv_mthd(dev, 0x9097, 0x0d28, 0xffff0000);
705 nv_mthd(dev, 0x9097, 0x0d30, 0xffff0000);
706 nv_mthd(dev, 0x9097, 0x0d38, 0xffff0000);
707 nv_mthd(dev, 0x9097, 0x0d04, 0xffff0000);
708 nv_mthd(dev, 0x9097, 0x0d0c, 0xffff0000);
709 nv_mthd(dev, 0x9097, 0x0d14, 0xffff0000);
710 nv_mthd(dev, 0x9097, 0x0d1c, 0xffff0000);
711 nv_mthd(dev, 0x9097, 0x0d24, 0xffff0000);
712 nv_mthd(dev, 0x9097, 0x0d2c, 0xffff0000);
713 nv_mthd(dev, 0x9097, 0x0d34, 0xffff0000);
714 nv_mthd(dev, 0x9097, 0x0d3c, 0xffff0000);
715 nv_mthd(dev, 0x9097, 0x0e00, 0x00000000);
716 nv_mthd(dev, 0x9097, 0x0e10, 0x00000000);
717 nv_mthd(dev, 0x9097, 0x0e20, 0x00000000);
718 nv_mthd(dev, 0x9097, 0x0e30, 0x00000000);
719 nv_mthd(dev, 0x9097, 0x0e40, 0x00000000);
720 nv_mthd(dev, 0x9097, 0x0e50, 0x00000000);
721 nv_mthd(dev, 0x9097, 0x0e60, 0x00000000);
722 nv_mthd(dev, 0x9097, 0x0e70, 0x00000000);
723 nv_mthd(dev, 0x9097, 0x0e80, 0x00000000);
724 nv_mthd(dev, 0x9097, 0x0e90, 0x00000000);
725 nv_mthd(dev, 0x9097, 0x0ea0, 0x00000000);
726 nv_mthd(dev, 0x9097, 0x0eb0, 0x00000000);
727 nv_mthd(dev, 0x9097, 0x0ec0, 0x00000000);
728 nv_mthd(dev, 0x9097, 0x0ed0, 0x00000000);
729 nv_mthd(dev, 0x9097, 0x0ee0, 0x00000000);
730 nv_mthd(dev, 0x9097, 0x0ef0, 0x00000000);
731 nv_mthd(dev, 0x9097, 0x0e04, 0xffff0000);
732 nv_mthd(dev, 0x9097, 0x0e14, 0xffff0000);
733 nv_mthd(dev, 0x9097, 0x0e24, 0xffff0000);
734 nv_mthd(dev, 0x9097, 0x0e34, 0xffff0000);
735 nv_mthd(dev, 0x9097, 0x0e44, 0xffff0000);
736 nv_mthd(dev, 0x9097, 0x0e54, 0xffff0000);
737 nv_mthd(dev, 0x9097, 0x0e64, 0xffff0000);
738 nv_mthd(dev, 0x9097, 0x0e74, 0xffff0000);
739 nv_mthd(dev, 0x9097, 0x0e84, 0xffff0000);
740 nv_mthd(dev, 0x9097, 0x0e94, 0xffff0000);
741 nv_mthd(dev, 0x9097, 0x0ea4, 0xffff0000);
742 nv_mthd(dev, 0x9097, 0x0eb4, 0xffff0000);
743 nv_mthd(dev, 0x9097, 0x0ec4, 0xffff0000);
744 nv_mthd(dev, 0x9097, 0x0ed4, 0xffff0000);
745 nv_mthd(dev, 0x9097, 0x0ee4, 0xffff0000);
746 nv_mthd(dev, 0x9097, 0x0ef4, 0xffff0000);
747 nv_mthd(dev, 0x9097, 0x0e08, 0xffff0000);
748 nv_mthd(dev, 0x9097, 0x0e18, 0xffff0000);
749 nv_mthd(dev, 0x9097, 0x0e28, 0xffff0000);
750 nv_mthd(dev, 0x9097, 0x0e38, 0xffff0000);
751 nv_mthd(dev, 0x9097, 0x0e48, 0xffff0000);
752 nv_mthd(dev, 0x9097, 0x0e58, 0xffff0000);
753 nv_mthd(dev, 0x9097, 0x0e68, 0xffff0000);
754 nv_mthd(dev, 0x9097, 0x0e78, 0xffff0000);
755 nv_mthd(dev, 0x9097, 0x0e88, 0xffff0000);
756 nv_mthd(dev, 0x9097, 0x0e98, 0xffff0000);
757 nv_mthd(dev, 0x9097, 0x0ea8, 0xffff0000);
758 nv_mthd(dev, 0x9097, 0x0eb8, 0xffff0000);
759 nv_mthd(dev, 0x9097, 0x0ec8, 0xffff0000);
760 nv_mthd(dev, 0x9097, 0x0ed8, 0xffff0000);
761 nv_mthd(dev, 0x9097, 0x0ee8, 0xffff0000);
762 nv_mthd(dev, 0x9097, 0x0ef8, 0xffff0000);
763 nv_mthd(dev, 0x9097, 0x0d40, 0x00000000);
764 nv_mthd(dev, 0x9097, 0x0d48, 0x00000000);
765 nv_mthd(dev, 0x9097, 0x0d50, 0x00000000);
766 nv_mthd(dev, 0x9097, 0x0d58, 0x00000000);
767 nv_mthd(dev, 0x9097, 0x0d44, 0x00000000);
768 nv_mthd(dev, 0x9097, 0x0d4c, 0x00000000);
769 nv_mthd(dev, 0x9097, 0x0d54, 0x00000000);
770 nv_mthd(dev, 0x9097, 0x0d5c, 0x00000000);
771 nv_mthd(dev, 0x9097, 0x1e00, 0x00000001);
772 nv_mthd(dev, 0x9097, 0x1e20, 0x00000001);
773 nv_mthd(dev, 0x9097, 0x1e40, 0x00000001);
774 nv_mthd(dev, 0x9097, 0x1e60, 0x00000001);
775 nv_mthd(dev, 0x9097, 0x1e80, 0x00000001);
776 nv_mthd(dev, 0x9097, 0x1ea0, 0x00000001);
777 nv_mthd(dev, 0x9097, 0x1ec0, 0x00000001);
778 nv_mthd(dev, 0x9097, 0x1ee0, 0x00000001);
779 nv_mthd(dev, 0x9097, 0x1e04, 0x00000001);
780 nv_mthd(dev, 0x9097, 0x1e24, 0x00000001);
781 nv_mthd(dev, 0x9097, 0x1e44, 0x00000001);
782 nv_mthd(dev, 0x9097, 0x1e64, 0x00000001);
783 nv_mthd(dev, 0x9097, 0x1e84, 0x00000001);
784 nv_mthd(dev, 0x9097, 0x1ea4, 0x00000001);
785 nv_mthd(dev, 0x9097, 0x1ec4, 0x00000001);
786 nv_mthd(dev, 0x9097, 0x1ee4, 0x00000001);
787 nv_mthd(dev, 0x9097, 0x1e08, 0x00000002);
788 nv_mthd(dev, 0x9097, 0x1e28, 0x00000002);
789 nv_mthd(dev, 0x9097, 0x1e48, 0x00000002);
790 nv_mthd(dev, 0x9097, 0x1e68, 0x00000002);
791 nv_mthd(dev, 0x9097, 0x1e88, 0x00000002);
792 nv_mthd(dev, 0x9097, 0x1ea8, 0x00000002);
793 nv_mthd(dev, 0x9097, 0x1ec8, 0x00000002);
794 nv_mthd(dev, 0x9097, 0x1ee8, 0x00000002);
795 nv_mthd(dev, 0x9097, 0x1e0c, 0x00000001);
796 nv_mthd(dev, 0x9097, 0x1e2c, 0x00000001);
797 nv_mthd(dev, 0x9097, 0x1e4c, 0x00000001);
798 nv_mthd(dev, 0x9097, 0x1e6c, 0x00000001);
799 nv_mthd(dev, 0x9097, 0x1e8c, 0x00000001);
800 nv_mthd(dev, 0x9097, 0x1eac, 0x00000001);
801 nv_mthd(dev, 0x9097, 0x1ecc, 0x00000001);
802 nv_mthd(dev, 0x9097, 0x1eec, 0x00000001);
803 nv_mthd(dev, 0x9097, 0x1e10, 0x00000001);
804 nv_mthd(dev, 0x9097, 0x1e30, 0x00000001);
805 nv_mthd(dev, 0x9097, 0x1e50, 0x00000001);
806 nv_mthd(dev, 0x9097, 0x1e70, 0x00000001);
807 nv_mthd(dev, 0x9097, 0x1e90, 0x00000001);
808 nv_mthd(dev, 0x9097, 0x1eb0, 0x00000001);
809 nv_mthd(dev, 0x9097, 0x1ed0, 0x00000001);
810 nv_mthd(dev, 0x9097, 0x1ef0, 0x00000001);
811 nv_mthd(dev, 0x9097, 0x1e14, 0x00000002);
812 nv_mthd(dev, 0x9097, 0x1e34, 0x00000002);
813 nv_mthd(dev, 0x9097, 0x1e54, 0x00000002);
814 nv_mthd(dev, 0x9097, 0x1e74, 0x00000002);
815 nv_mthd(dev, 0x9097, 0x1e94, 0x00000002);
816 nv_mthd(dev, 0x9097, 0x1eb4, 0x00000002);
817 nv_mthd(dev, 0x9097, 0x1ed4, 0x00000002);
818 nv_mthd(dev, 0x9097, 0x1ef4, 0x00000002);
819 nv_mthd(dev, 0x9097, 0x1e18, 0x00000001);
820 nv_mthd(dev, 0x9097, 0x1e38, 0x00000001);
821 nv_mthd(dev, 0x9097, 0x1e58, 0x00000001);
822 nv_mthd(dev, 0x9097, 0x1e78, 0x00000001);
823 nv_mthd(dev, 0x9097, 0x1e98, 0x00000001);
824 nv_mthd(dev, 0x9097, 0x1eb8, 0x00000001);
825 nv_mthd(dev, 0x9097, 0x1ed8, 0x00000001);
826 nv_mthd(dev, 0x9097, 0x1ef8, 0x00000001);
827 nv_mthd(dev, 0x9097, 0x3400, 0x00000000);
828 nv_mthd(dev, 0x9097, 0x3404, 0x00000000);
829 nv_mthd(dev, 0x9097, 0x3408, 0x00000000);
830 nv_mthd(dev, 0x9097, 0x340c, 0x00000000);
831 nv_mthd(dev, 0x9097, 0x3410, 0x00000000);
832 nv_mthd(dev, 0x9097, 0x3414, 0x00000000);
833 nv_mthd(dev, 0x9097, 0x3418, 0x00000000);
834 nv_mthd(dev, 0x9097, 0x341c, 0x00000000);
835 nv_mthd(dev, 0x9097, 0x3420, 0x00000000);
836 nv_mthd(dev, 0x9097, 0x3424, 0x00000000);
837 nv_mthd(dev, 0x9097, 0x3428, 0x00000000);
838 nv_mthd(dev, 0x9097, 0x342c, 0x00000000);
839 nv_mthd(dev, 0x9097, 0x3430, 0x00000000);
840 nv_mthd(dev, 0x9097, 0x3434, 0x00000000);
841 nv_mthd(dev, 0x9097, 0x3438, 0x00000000);
842 nv_mthd(dev, 0x9097, 0x343c, 0x00000000);
843 nv_mthd(dev, 0x9097, 0x3440, 0x00000000);
844 nv_mthd(dev, 0x9097, 0x3444, 0x00000000);
845 nv_mthd(dev, 0x9097, 0x3448, 0x00000000);
846 nv_mthd(dev, 0x9097, 0x344c, 0x00000000);
847 nv_mthd(dev, 0x9097, 0x3450, 0x00000000);
848 nv_mthd(dev, 0x9097, 0x3454, 0x00000000);
849 nv_mthd(dev, 0x9097, 0x3458, 0x00000000);
850 nv_mthd(dev, 0x9097, 0x345c, 0x00000000);
851 nv_mthd(dev, 0x9097, 0x3460, 0x00000000);
852 nv_mthd(dev, 0x9097, 0x3464, 0x00000000);
853 nv_mthd(dev, 0x9097, 0x3468, 0x00000000);
854 nv_mthd(dev, 0x9097, 0x346c, 0x00000000);
855 nv_mthd(dev, 0x9097, 0x3470, 0x00000000);
856 nv_mthd(dev, 0x9097, 0x3474, 0x00000000);
857 nv_mthd(dev, 0x9097, 0x3478, 0x00000000);
858 nv_mthd(dev, 0x9097, 0x347c, 0x00000000);
859 nv_mthd(dev, 0x9097, 0x3480, 0x00000000);
860 nv_mthd(dev, 0x9097, 0x3484, 0x00000000);
861 nv_mthd(dev, 0x9097, 0x3488, 0x00000000);
862 nv_mthd(dev, 0x9097, 0x348c, 0x00000000);
863 nv_mthd(dev, 0x9097, 0x3490, 0x00000000);
864 nv_mthd(dev, 0x9097, 0x3494, 0x00000000);
865 nv_mthd(dev, 0x9097, 0x3498, 0x00000000);
866 nv_mthd(dev, 0x9097, 0x349c, 0x00000000);
867 nv_mthd(dev, 0x9097, 0x34a0, 0x00000000);
868 nv_mthd(dev, 0x9097, 0x34a4, 0x00000000);
869 nv_mthd(dev, 0x9097, 0x34a8, 0x00000000);
870 nv_mthd(dev, 0x9097, 0x34ac, 0x00000000);
871 nv_mthd(dev, 0x9097, 0x34b0, 0x00000000);
872 nv_mthd(dev, 0x9097, 0x34b4, 0x00000000);
873 nv_mthd(dev, 0x9097, 0x34b8, 0x00000000);
874 nv_mthd(dev, 0x9097, 0x34bc, 0x00000000);
875 nv_mthd(dev, 0x9097, 0x34c0, 0x00000000);
876 nv_mthd(dev, 0x9097, 0x34c4, 0x00000000);
877 nv_mthd(dev, 0x9097, 0x34c8, 0x00000000);
878 nv_mthd(dev, 0x9097, 0x34cc, 0x00000000);
879 nv_mthd(dev, 0x9097, 0x34d0, 0x00000000);
880 nv_mthd(dev, 0x9097, 0x34d4, 0x00000000);
881 nv_mthd(dev, 0x9097, 0x34d8, 0x00000000);
882 nv_mthd(dev, 0x9097, 0x34dc, 0x00000000);
883 nv_mthd(dev, 0x9097, 0x34e0, 0x00000000);
884 nv_mthd(dev, 0x9097, 0x34e4, 0x00000000);
885 nv_mthd(dev, 0x9097, 0x34e8, 0x00000000);
886 nv_mthd(dev, 0x9097, 0x34ec, 0x00000000);
887 nv_mthd(dev, 0x9097, 0x34f0, 0x00000000);
888 nv_mthd(dev, 0x9097, 0x34f4, 0x00000000);
889 nv_mthd(dev, 0x9097, 0x34f8, 0x00000000);
890 nv_mthd(dev, 0x9097, 0x34fc, 0x00000000);
891 nv_mthd(dev, 0x9097, 0x3500, 0x00000000);
892 nv_mthd(dev, 0x9097, 0x3504, 0x00000000);
893 nv_mthd(dev, 0x9097, 0x3508, 0x00000000);
894 nv_mthd(dev, 0x9097, 0x350c, 0x00000000);
895 nv_mthd(dev, 0x9097, 0x3510, 0x00000000);
896 nv_mthd(dev, 0x9097, 0x3514, 0x00000000);
897 nv_mthd(dev, 0x9097, 0x3518, 0x00000000);
898 nv_mthd(dev, 0x9097, 0x351c, 0x00000000);
899 nv_mthd(dev, 0x9097, 0x3520, 0x00000000);
900 nv_mthd(dev, 0x9097, 0x3524, 0x00000000);
901 nv_mthd(dev, 0x9097, 0x3528, 0x00000000);
902 nv_mthd(dev, 0x9097, 0x352c, 0x00000000);
903 nv_mthd(dev, 0x9097, 0x3530, 0x00000000);
904 nv_mthd(dev, 0x9097, 0x3534, 0x00000000);
905 nv_mthd(dev, 0x9097, 0x3538, 0x00000000);
906 nv_mthd(dev, 0x9097, 0x353c, 0x00000000);
907 nv_mthd(dev, 0x9097, 0x3540, 0x00000000);
908 nv_mthd(dev, 0x9097, 0x3544, 0x00000000);
909 nv_mthd(dev, 0x9097, 0x3548, 0x00000000);
910 nv_mthd(dev, 0x9097, 0x354c, 0x00000000);
911 nv_mthd(dev, 0x9097, 0x3550, 0x00000000);
912 nv_mthd(dev, 0x9097, 0x3554, 0x00000000);
913 nv_mthd(dev, 0x9097, 0x3558, 0x00000000);
914 nv_mthd(dev, 0x9097, 0x355c, 0x00000000);
915 nv_mthd(dev, 0x9097, 0x3560, 0x00000000);
916 nv_mthd(dev, 0x9097, 0x3564, 0x00000000);
917 nv_mthd(dev, 0x9097, 0x3568, 0x00000000);
918 nv_mthd(dev, 0x9097, 0x356c, 0x00000000);
919 nv_mthd(dev, 0x9097, 0x3570, 0x00000000);
920 nv_mthd(dev, 0x9097, 0x3574, 0x00000000);
921 nv_mthd(dev, 0x9097, 0x3578, 0x00000000);
922 nv_mthd(dev, 0x9097, 0x357c, 0x00000000);
923 nv_mthd(dev, 0x9097, 0x3580, 0x00000000);
924 nv_mthd(dev, 0x9097, 0x3584, 0x00000000);
925 nv_mthd(dev, 0x9097, 0x3588, 0x00000000);
926 nv_mthd(dev, 0x9097, 0x358c, 0x00000000);
927 nv_mthd(dev, 0x9097, 0x3590, 0x00000000);
928 nv_mthd(dev, 0x9097, 0x3594, 0x00000000);
929 nv_mthd(dev, 0x9097, 0x3598, 0x00000000);
930 nv_mthd(dev, 0x9097, 0x359c, 0x00000000);
931 nv_mthd(dev, 0x9097, 0x35a0, 0x00000000);
932 nv_mthd(dev, 0x9097, 0x35a4, 0x00000000);
933 nv_mthd(dev, 0x9097, 0x35a8, 0x00000000);
934 nv_mthd(dev, 0x9097, 0x35ac, 0x00000000);
935 nv_mthd(dev, 0x9097, 0x35b0, 0x00000000);
936 nv_mthd(dev, 0x9097, 0x35b4, 0x00000000);
937 nv_mthd(dev, 0x9097, 0x35b8, 0x00000000);
938 nv_mthd(dev, 0x9097, 0x35bc, 0x00000000);
939 nv_mthd(dev, 0x9097, 0x35c0, 0x00000000);
940 nv_mthd(dev, 0x9097, 0x35c4, 0x00000000);
941 nv_mthd(dev, 0x9097, 0x35c8, 0x00000000);
942 nv_mthd(dev, 0x9097, 0x35cc, 0x00000000);
943 nv_mthd(dev, 0x9097, 0x35d0, 0x00000000);
944 nv_mthd(dev, 0x9097, 0x35d4, 0x00000000);
945 nv_mthd(dev, 0x9097, 0x35d8, 0x00000000);
946 nv_mthd(dev, 0x9097, 0x35dc, 0x00000000);
947 nv_mthd(dev, 0x9097, 0x35e0, 0x00000000);
948 nv_mthd(dev, 0x9097, 0x35e4, 0x00000000);
949 nv_mthd(dev, 0x9097, 0x35e8, 0x00000000);
950 nv_mthd(dev, 0x9097, 0x35ec, 0x00000000);
951 nv_mthd(dev, 0x9097, 0x35f0, 0x00000000);
952 nv_mthd(dev, 0x9097, 0x35f4, 0x00000000);
953 nv_mthd(dev, 0x9097, 0x35f8, 0x00000000);
954 nv_mthd(dev, 0x9097, 0x35fc, 0x00000000);
955 nv_mthd(dev, 0x9097, 0x030c, 0x00000001);
956 nv_mthd(dev, 0x9097, 0x1944, 0x00000000);
957 nv_mthd(dev, 0x9097, 0x1514, 0x00000000);
958 nv_mthd(dev, 0x9097, 0x0d68, 0x0000ffff);
959 nv_mthd(dev, 0x9097, 0x121c, 0x0fac6881);
960 nv_mthd(dev, 0x9097, 0x0fac, 0x00000001);
961 nv_mthd(dev, 0x9097, 0x1538, 0x00000001);
962 nv_mthd(dev, 0x9097, 0x0fe0, 0x00000000);
963 nv_mthd(dev, 0x9097, 0x0fe4, 0x00000000);
964 nv_mthd(dev, 0x9097, 0x0fe8, 0x00000014);
965 nv_mthd(dev, 0x9097, 0x0fec, 0x00000040);
966 nv_mthd(dev, 0x9097, 0x0ff0, 0x00000000);
967 nv_mthd(dev, 0x9097, 0x179c, 0x00000000);
968 nv_mthd(dev, 0x9097, 0x1228, 0x00000400);
969 nv_mthd(dev, 0x9097, 0x122c, 0x00000300);
970 nv_mthd(dev, 0x9097, 0x1230, 0x00010001);
971 nv_mthd(dev, 0x9097, 0x07f8, 0x00000000);
972 nv_mthd(dev, 0x9097, 0x15b4, 0x00000001);
973 nv_mthd(dev, 0x9097, 0x15cc, 0x00000000);
974 nv_mthd(dev, 0x9097, 0x1534, 0x00000000);
975 nv_mthd(dev, 0x9097, 0x0fb0, 0x00000000);
976 nv_mthd(dev, 0x9097, 0x15d0, 0x00000000);
977 nv_mthd(dev, 0x9097, 0x153c, 0x00000000);
978 nv_mthd(dev, 0x9097, 0x16b4, 0x00000003);
979 nv_mthd(dev, 0x9097, 0x0fbc, 0x0000ffff);
980 nv_mthd(dev, 0x9097, 0x0fc0, 0x0000ffff);
981 nv_mthd(dev, 0x9097, 0x0fc4, 0x0000ffff);
982 nv_mthd(dev, 0x9097, 0x0fc8, 0x0000ffff);
983 nv_mthd(dev, 0x9097, 0x0df8, 0x00000000);
984 nv_mthd(dev, 0x9097, 0x0dfc, 0x00000000);
985 nv_mthd(dev, 0x9097, 0x1948, 0x00000000);
986 nv_mthd(dev, 0x9097, 0x1970, 0x00000001);
987 nv_mthd(dev, 0x9097, 0x161c, 0x000009f0);
988 nv_mthd(dev, 0x9097, 0x0dcc, 0x00000010);
989 nv_mthd(dev, 0x9097, 0x163c, 0x00000000);
990 nv_mthd(dev, 0x9097, 0x15e4, 0x00000000);
991 nv_mthd(dev, 0x9097, 0x1160, 0x25e00040);
992 nv_mthd(dev, 0x9097, 0x1164, 0x25e00040);
993 nv_mthd(dev, 0x9097, 0x1168, 0x25e00040);
994 nv_mthd(dev, 0x9097, 0x116c, 0x25e00040);
995 nv_mthd(dev, 0x9097, 0x1170, 0x25e00040);
996 nv_mthd(dev, 0x9097, 0x1174, 0x25e00040);
997 nv_mthd(dev, 0x9097, 0x1178, 0x25e00040);
998 nv_mthd(dev, 0x9097, 0x117c, 0x25e00040);
999 nv_mthd(dev, 0x9097, 0x1180, 0x25e00040);
1000 nv_mthd(dev, 0x9097, 0x1184, 0x25e00040);
1001 nv_mthd(dev, 0x9097, 0x1188, 0x25e00040);
1002 nv_mthd(dev, 0x9097, 0x118c, 0x25e00040);
1003 nv_mthd(dev, 0x9097, 0x1190, 0x25e00040);
1004 nv_mthd(dev, 0x9097, 0x1194, 0x25e00040);
1005 nv_mthd(dev, 0x9097, 0x1198, 0x25e00040);
1006 nv_mthd(dev, 0x9097, 0x119c, 0x25e00040);
1007 nv_mthd(dev, 0x9097, 0x11a0, 0x25e00040);
1008 nv_mthd(dev, 0x9097, 0x11a4, 0x25e00040);
1009 nv_mthd(dev, 0x9097, 0x11a8, 0x25e00040);
1010 nv_mthd(dev, 0x9097, 0x11ac, 0x25e00040);
1011 nv_mthd(dev, 0x9097, 0x11b0, 0x25e00040);
1012 nv_mthd(dev, 0x9097, 0x11b4, 0x25e00040);
1013 nv_mthd(dev, 0x9097, 0x11b8, 0x25e00040);
1014 nv_mthd(dev, 0x9097, 0x11bc, 0x25e00040);
1015 nv_mthd(dev, 0x9097, 0x11c0, 0x25e00040);
1016 nv_mthd(dev, 0x9097, 0x11c4, 0x25e00040);
1017 nv_mthd(dev, 0x9097, 0x11c8, 0x25e00040);
1018 nv_mthd(dev, 0x9097, 0x11cc, 0x25e00040);
1019 nv_mthd(dev, 0x9097, 0x11d0, 0x25e00040);
1020 nv_mthd(dev, 0x9097, 0x11d4, 0x25e00040);
1021 nv_mthd(dev, 0x9097, 0x11d8, 0x25e00040);
1022 nv_mthd(dev, 0x9097, 0x11dc, 0x25e00040);
1023 nv_mthd(dev, 0x9097, 0x1880, 0x00000000);
1024 nv_mthd(dev, 0x9097, 0x1884, 0x00000000);
1025 nv_mthd(dev, 0x9097, 0x1888, 0x00000000);
1026 nv_mthd(dev, 0x9097, 0x188c, 0x00000000);
1027 nv_mthd(dev, 0x9097, 0x1890, 0x00000000);
1028 nv_mthd(dev, 0x9097, 0x1894, 0x00000000);
1029 nv_mthd(dev, 0x9097, 0x1898, 0x00000000);
1030 nv_mthd(dev, 0x9097, 0x189c, 0x00000000);
1031 nv_mthd(dev, 0x9097, 0x18a0, 0x00000000);
1032 nv_mthd(dev, 0x9097, 0x18a4, 0x00000000);
1033 nv_mthd(dev, 0x9097, 0x18a8, 0x00000000);
1034 nv_mthd(dev, 0x9097, 0x18ac, 0x00000000);
1035 nv_mthd(dev, 0x9097, 0x18b0, 0x00000000);
1036 nv_mthd(dev, 0x9097, 0x18b4, 0x00000000);
1037 nv_mthd(dev, 0x9097, 0x18b8, 0x00000000);
1038 nv_mthd(dev, 0x9097, 0x18bc, 0x00000000);
1039 nv_mthd(dev, 0x9097, 0x18c0, 0x00000000);
1040 nv_mthd(dev, 0x9097, 0x18c4, 0x00000000);
1041 nv_mthd(dev, 0x9097, 0x18c8, 0x00000000);
1042 nv_mthd(dev, 0x9097, 0x18cc, 0x00000000);
1043 nv_mthd(dev, 0x9097, 0x18d0, 0x00000000);
1044 nv_mthd(dev, 0x9097, 0x18d4, 0x00000000);
1045 nv_mthd(dev, 0x9097, 0x18d8, 0x00000000);
1046 nv_mthd(dev, 0x9097, 0x18dc, 0x00000000);
1047 nv_mthd(dev, 0x9097, 0x18e0, 0x00000000);
1048 nv_mthd(dev, 0x9097, 0x18e4, 0x00000000);
1049 nv_mthd(dev, 0x9097, 0x18e8, 0x00000000);
1050 nv_mthd(dev, 0x9097, 0x18ec, 0x00000000);
1051 nv_mthd(dev, 0x9097, 0x18f0, 0x00000000);
1052 nv_mthd(dev, 0x9097, 0x18f4, 0x00000000);
1053 nv_mthd(dev, 0x9097, 0x18f8, 0x00000000);
1054 nv_mthd(dev, 0x9097, 0x18fc, 0x00000000);
1055 nv_mthd(dev, 0x9097, 0x0f84, 0x00000000);
1056 nv_mthd(dev, 0x9097, 0x0f88, 0x00000000);
1057 nv_mthd(dev, 0x9097, 0x17c8, 0x00000000);
1058 nv_mthd(dev, 0x9097, 0x17cc, 0x00000000);
1059 nv_mthd(dev, 0x9097, 0x17d0, 0x000000ff);
1060 nv_mthd(dev, 0x9097, 0x17d4, 0xffffffff);
1061 nv_mthd(dev, 0x9097, 0x17d8, 0x00000002);
1062 nv_mthd(dev, 0x9097, 0x17dc, 0x00000000);
1063 nv_mthd(dev, 0x9097, 0x15f4, 0x00000000);
1064 nv_mthd(dev, 0x9097, 0x15f8, 0x00000000);
1065 nv_mthd(dev, 0x9097, 0x1434, 0x00000000);
1066 nv_mthd(dev, 0x9097, 0x1438, 0x00000000);
1067 nv_mthd(dev, 0x9097, 0x0d74, 0x00000000);
1068 nv_mthd(dev, 0x9097, 0x0dec, 0x00000001);
1069 nv_mthd(dev, 0x9097, 0x13a4, 0x00000000);
1070 nv_mthd(dev, 0x9097, 0x1318, 0x00000001);
1071 nv_mthd(dev, 0x9097, 0x1644, 0x00000000);
1072 nv_mthd(dev, 0x9097, 0x0748, 0x00000000);
1073 nv_mthd(dev, 0x9097, 0x0de8, 0x00000000);
1074 nv_mthd(dev, 0x9097, 0x1648, 0x00000000);
1075 nv_mthd(dev, 0x9097, 0x12a4, 0x00000000);
1076 nv_mthd(dev, 0x9097, 0x1120, 0x00000000);
1077 nv_mthd(dev, 0x9097, 0x1124, 0x00000000);
1078 nv_mthd(dev, 0x9097, 0x1128, 0x00000000);
1079 nv_mthd(dev, 0x9097, 0x112c, 0x00000000);
1080 nv_mthd(dev, 0x9097, 0x1118, 0x00000000);
1081 nv_mthd(dev, 0x9097, 0x164c, 0x00000000);
1082 nv_mthd(dev, 0x9097, 0x1658, 0x00000000);
1083 nv_mthd(dev, 0x9097, 0x1910, 0x00000290);
1084 nv_mthd(dev, 0x9097, 0x1518, 0x00000000);
1085 nv_mthd(dev, 0x9097, 0x165c, 0x00000001);
1086 nv_mthd(dev, 0x9097, 0x1520, 0x00000000);
1087 nv_mthd(dev, 0x9097, 0x1604, 0x00000000);
1088 nv_mthd(dev, 0x9097, 0x1570, 0x00000000);
1089 nv_mthd(dev, 0x9097, 0x13b0, 0x3f800000);
1090 nv_mthd(dev, 0x9097, 0x13b4, 0x3f800000);
1091 nv_mthd(dev, 0x9097, 0x020c, 0x00000000);
1092 nv_mthd(dev, 0x9097, 0x1670, 0x30201000);
1093 nv_mthd(dev, 0x9097, 0x1674, 0x70605040);
1094 nv_mthd(dev, 0x9097, 0x1678, 0xb8a89888);
1095 nv_mthd(dev, 0x9097, 0x167c, 0xf8e8d8c8);
1096 nv_mthd(dev, 0x9097, 0x166c, 0x00000000);
1097 nv_mthd(dev, 0x9097, 0x1680, 0x00ffff00);
1098 nv_mthd(dev, 0x9097, 0x12d0, 0x00000003);
1099 nv_mthd(dev, 0x9097, 0x12d4, 0x00000002);
1100 nv_mthd(dev, 0x9097, 0x1684, 0x00000000);
1101 nv_mthd(dev, 0x9097, 0x1688, 0x00000000);
1102 nv_mthd(dev, 0x9097, 0x0dac, 0x00001b02);
1103 nv_mthd(dev, 0x9097, 0x0db0, 0x00001b02);
1104 nv_mthd(dev, 0x9097, 0x0db4, 0x00000000);
1105 nv_mthd(dev, 0x9097, 0x168c, 0x00000000);
1106 nv_mthd(dev, 0x9097, 0x15bc, 0x00000000);
1107 nv_mthd(dev, 0x9097, 0x156c, 0x00000000);
1108 nv_mthd(dev, 0x9097, 0x187c, 0x00000000);
1109 nv_mthd(dev, 0x9097, 0x1110, 0x00000001);
1110 nv_mthd(dev, 0x9097, 0x0dc0, 0x00000000);
1111 nv_mthd(dev, 0x9097, 0x0dc4, 0x00000000);
1112 nv_mthd(dev, 0x9097, 0x0dc8, 0x00000000);
1113 nv_mthd(dev, 0x9097, 0x1234, 0x00000000);
1114 nv_mthd(dev, 0x9097, 0x1690, 0x00000000);
1115 nv_mthd(dev, 0x9097, 0x12ac, 0x00000001);
1116 nv_mthd(dev, 0x9097, 0x02c4, 0x00000000);
1117 nv_mthd(dev, 0x9097, 0x0790, 0x00000000);
1118 nv_mthd(dev, 0x9097, 0x0794, 0x00000000);
1119 nv_mthd(dev, 0x9097, 0x0798, 0x00000000);
1120 nv_mthd(dev, 0x9097, 0x079c, 0x00000000);
1121 nv_mthd(dev, 0x9097, 0x07a0, 0x00000000);
1122 nv_mthd(dev, 0x9097, 0x077c, 0x00000000);
1123 nv_mthd(dev, 0x9097, 0x1000, 0x00000010);
1124 nv_mthd(dev, 0x9097, 0x10fc, 0x00000000);
1125 nv_mthd(dev, 0x9097, 0x1290, 0x00000000);
1126 nv_mthd(dev, 0x9097, 0x0218, 0x00000010);
1127 nv_mthd(dev, 0x9097, 0x12d8, 0x00000000);
1128 nv_mthd(dev, 0x9097, 0x12dc, 0x00000010);
1129 nv_mthd(dev, 0x9097, 0x0d94, 0x00000001);
1130 nv_mthd(dev, 0x9097, 0x155c, 0x00000000);
1131 nv_mthd(dev, 0x9097, 0x1560, 0x00000000);
1132 nv_mthd(dev, 0x9097, 0x1564, 0x00001fff);
1133 nv_mthd(dev, 0x9097, 0x1574, 0x00000000);
1134 nv_mthd(dev, 0x9097, 0x1578, 0x00000000);
1135 nv_mthd(dev, 0x9097, 0x157c, 0x003fffff);
1136 nv_mthd(dev, 0x9097, 0x1354, 0x00000000);
1137 nv_mthd(dev, 0x9097, 0x1664, 0x00000000);
1138 nv_mthd(dev, 0x9097, 0x1610, 0x00000012);
1139 nv_mthd(dev, 0x9097, 0x1608, 0x00000000);
1140 nv_mthd(dev, 0x9097, 0x160c, 0x00000000);
1141 nv_mthd(dev, 0x9097, 0x162c, 0x00000003);
1142 nv_mthd(dev, 0x9097, 0x0210, 0x00000000);
1143 nv_mthd(dev, 0x9097, 0x0320, 0x00000000);
1144 nv_mthd(dev, 0x9097, 0x0324, 0x3f800000);
1145 nv_mthd(dev, 0x9097, 0x0328, 0x3f800000);
1146 nv_mthd(dev, 0x9097, 0x032c, 0x3f800000);
1147 nv_mthd(dev, 0x9097, 0x0330, 0x3f800000);
1148 nv_mthd(dev, 0x9097, 0x0334, 0x3f800000);
1149 nv_mthd(dev, 0x9097, 0x0338, 0x3f800000);
1150 nv_mthd(dev, 0x9097, 0x0750, 0x00000000);
1151 nv_mthd(dev, 0x9097, 0x0760, 0x39291909);
1152 nv_mthd(dev, 0x9097, 0x0764, 0x79695949);
1153 nv_mthd(dev, 0x9097, 0x0768, 0xb9a99989);
1154 nv_mthd(dev, 0x9097, 0x076c, 0xf9e9d9c9);
1155 nv_mthd(dev, 0x9097, 0x0770, 0x30201000);
1156 nv_mthd(dev, 0x9097, 0x0774, 0x70605040);
1157 nv_mthd(dev, 0x9097, 0x0778, 0x00009080);
1158 nv_mthd(dev, 0x9097, 0x0780, 0x39291909);
1159 nv_mthd(dev, 0x9097, 0x0784, 0x79695949);
1160 nv_mthd(dev, 0x9097, 0x0788, 0xb9a99989);
1161 nv_mthd(dev, 0x9097, 0x078c, 0xf9e9d9c9);
1162 nv_mthd(dev, 0x9097, 0x07d0, 0x30201000);
1163 nv_mthd(dev, 0x9097, 0x07d4, 0x70605040);
1164 nv_mthd(dev, 0x9097, 0x07d8, 0x00009080);
1165 nv_mthd(dev, 0x9097, 0x037c, 0x00000001);
1166 nv_mthd(dev, 0x9097, 0x0740, 0x00000000);
1167 nv_mthd(dev, 0x9097, 0x0744, 0x00000000);
1168 nv_mthd(dev, 0x9097, 0x2600, 0x00000000);
1169 nv_mthd(dev, 0x9097, 0x1918, 0x00000000);
1170 nv_mthd(dev, 0x9097, 0x191c, 0x00000900);
1171 nv_mthd(dev, 0x9097, 0x1920, 0x00000405);
1172 nv_mthd(dev, 0x9097, 0x1308, 0x00000001);
1173 nv_mthd(dev, 0x9097, 0x1924, 0x00000000);
1174 nv_mthd(dev, 0x9097, 0x13ac, 0x00000000);
1175 nv_mthd(dev, 0x9097, 0x192c, 0x00000001);
1176 nv_mthd(dev, 0x9097, 0x193c, 0x00002c1c);
1177 nv_mthd(dev, 0x9097, 0x0d7c, 0x00000000);
1178 nv_mthd(dev, 0x9097, 0x0f8c, 0x00000000);
1179 nv_mthd(dev, 0x9097, 0x02c0, 0x00000001);
1180 nv_mthd(dev, 0x9097, 0x1510, 0x00000000);
1181 nv_mthd(dev, 0x9097, 0x1940, 0x00000000);
1182 nv_mthd(dev, 0x9097, 0x0ff4, 0x00000000);
1183 nv_mthd(dev, 0x9097, 0x0ff8, 0x00000000);
1184 nv_mthd(dev, 0x9097, 0x194c, 0x00000000);
1185 nv_mthd(dev, 0x9097, 0x1950, 0x00000000);
1186 nv_mthd(dev, 0x9097, 0x1968, 0x00000000);
1187 nv_mthd(dev, 0x9097, 0x1590, 0x0000003f);
1188 nv_mthd(dev, 0x9097, 0x07e8, 0x00000000);
1189 nv_mthd(dev, 0x9097, 0x07ec, 0x00000000);
1190 nv_mthd(dev, 0x9097, 0x07f0, 0x00000000);
1191 nv_mthd(dev, 0x9097, 0x07f4, 0x00000000);
1192 nv_mthd(dev, 0x9097, 0x196c, 0x00000011);
1193 nv_mthd(dev, 0x9097, 0x197c, 0x00000000);
1194 nv_mthd(dev, 0x9097, 0x0fcc, 0x00000000);
1195 nv_mthd(dev, 0x9097, 0x0fd0, 0x00000000);
1196 nv_mthd(dev, 0x9097, 0x02d8, 0x00000040);
1197 nv_mthd(dev, 0x9097, 0x1980, 0x00000080);
1198 nv_mthd(dev, 0x9097, 0x1504, 0x00000080);
1199 nv_mthd(dev, 0x9097, 0x1984, 0x00000000);
1200 nv_mthd(dev, 0x9097, 0x0300, 0x00000001);
1201 nv_mthd(dev, 0x9097, 0x13a8, 0x00000000);
1202 nv_mthd(dev, 0x9097, 0x12ec, 0x00000000);
1203 nv_mthd(dev, 0x9097, 0x1310, 0x00000000);
1204 nv_mthd(dev, 0x9097, 0x1314, 0x00000001);
1205 nv_mthd(dev, 0x9097, 0x1380, 0x00000000);
1206 nv_mthd(dev, 0x9097, 0x1384, 0x00000001);
1207 nv_mthd(dev, 0x9097, 0x1388, 0x00000001);
1208 nv_mthd(dev, 0x9097, 0x138c, 0x00000001);
1209 nv_mthd(dev, 0x9097, 0x1390, 0x00000001);
1210 nv_mthd(dev, 0x9097, 0x1394, 0x00000000);
1211 nv_mthd(dev, 0x9097, 0x139c, 0x00000000);
1212 nv_mthd(dev, 0x9097, 0x1398, 0x00000000);
1213 nv_mthd(dev, 0x9097, 0x1594, 0x00000000);
1214 nv_mthd(dev, 0x9097, 0x1598, 0x00000001);
1215 nv_mthd(dev, 0x9097, 0x159c, 0x00000001);
1216 nv_mthd(dev, 0x9097, 0x15a0, 0x00000001);
1217 nv_mthd(dev, 0x9097, 0x15a4, 0x00000001);
1218 nv_mthd(dev, 0x9097, 0x0f54, 0x00000000);
1219 nv_mthd(dev, 0x9097, 0x0f58, 0x00000000);
1220 nv_mthd(dev, 0x9097, 0x0f5c, 0x00000000);
1221 nv_mthd(dev, 0x9097, 0x19bc, 0x00000000);
1222 nv_mthd(dev, 0x9097, 0x0f9c, 0x00000000);
1223 nv_mthd(dev, 0x9097, 0x0fa0, 0x00000000);
1224 nv_mthd(dev, 0x9097, 0x12cc, 0x00000000);
1225 nv_mthd(dev, 0x9097, 0x12e8, 0x00000000);
1226 nv_mthd(dev, 0x9097, 0x130c, 0x00000001);
1227 nv_mthd(dev, 0x9097, 0x1360, 0x00000000);
1228 nv_mthd(dev, 0x9097, 0x1364, 0x00000000);
1229 nv_mthd(dev, 0x9097, 0x1368, 0x00000000);
1230 nv_mthd(dev, 0x9097, 0x136c, 0x00000000);
1231 nv_mthd(dev, 0x9097, 0x1370, 0x00000000);
1232 nv_mthd(dev, 0x9097, 0x1374, 0x00000000);
1233 nv_mthd(dev, 0x9097, 0x1378, 0x00000000);
1234 nv_mthd(dev, 0x9097, 0x137c, 0x00000000);
1235 nv_mthd(dev, 0x9097, 0x133c, 0x00000001);
1236 nv_mthd(dev, 0x9097, 0x1340, 0x00000001);
1237 nv_mthd(dev, 0x9097, 0x1344, 0x00000002);
1238 nv_mthd(dev, 0x9097, 0x1348, 0x00000001);
1239 nv_mthd(dev, 0x9097, 0x134c, 0x00000001);
1240 nv_mthd(dev, 0x9097, 0x1350, 0x00000002);
1241 nv_mthd(dev, 0x9097, 0x1358, 0x00000001);
1242 nv_mthd(dev, 0x9097, 0x12e4, 0x00000000);
1243 nv_mthd(dev, 0x9097, 0x131c, 0x00000000);
1244 nv_mthd(dev, 0x9097, 0x1320, 0x00000000);
1245 nv_mthd(dev, 0x9097, 0x1324, 0x00000000);
1246 nv_mthd(dev, 0x9097, 0x1328, 0x00000000);
1247 nv_mthd(dev, 0x9097, 0x19c0, 0x00000000);
1248 nv_mthd(dev, 0x9097, 0x1140, 0x00000000);
1249 nv_mthd(dev, 0x9097, 0x19c4, 0x00000000);
1250 nv_mthd(dev, 0x9097, 0x19c8, 0x00001500);
1251 nv_mthd(dev, 0x9097, 0x135c, 0x00000000);
1252 nv_mthd(dev, 0x9097, 0x0f90, 0x00000000);
1253 nv_mthd(dev, 0x9097, 0x19e0, 0x00000001);
1254 nv_mthd(dev, 0x9097, 0x19e4, 0x00000001);
1255 nv_mthd(dev, 0x9097, 0x19e8, 0x00000001);
1256 nv_mthd(dev, 0x9097, 0x19ec, 0x00000001);
1257 nv_mthd(dev, 0x9097, 0x19f0, 0x00000001);
1258 nv_mthd(dev, 0x9097, 0x19f4, 0x00000001);
1259 nv_mthd(dev, 0x9097, 0x19f8, 0x00000001);
1260 nv_mthd(dev, 0x9097, 0x19fc, 0x00000001);
1261 nv_mthd(dev, 0x9097, 0x19cc, 0x00000001);
1262 nv_mthd(dev, 0x9097, 0x15b8, 0x00000000);
1263 nv_mthd(dev, 0x9097, 0x1a00, 0x00001111);
1264 nv_mthd(dev, 0x9097, 0x1a04, 0x00000000);
1265 nv_mthd(dev, 0x9097, 0x1a08, 0x00000000);
1266 nv_mthd(dev, 0x9097, 0x1a0c, 0x00000000);
1267 nv_mthd(dev, 0x9097, 0x1a10, 0x00000000);
1268 nv_mthd(dev, 0x9097, 0x1a14, 0x00000000);
1269 nv_mthd(dev, 0x9097, 0x1a18, 0x00000000);
1270 nv_mthd(dev, 0x9097, 0x1a1c, 0x00000000);
1271 nv_mthd(dev, 0x9097, 0x0d6c, 0xffff0000);
1272 nv_mthd(dev, 0x9097, 0x0d70, 0xffff0000);
1273 nv_mthd(dev, 0x9097, 0x10f8, 0x00001010);
1274 nv_mthd(dev, 0x9097, 0x0d80, 0x00000000);
1275 nv_mthd(dev, 0x9097, 0x0d84, 0x00000000);
1276 nv_mthd(dev, 0x9097, 0x0d88, 0x00000000);
1277 nv_mthd(dev, 0x9097, 0x0d8c, 0x00000000);
1278 nv_mthd(dev, 0x9097, 0x0d90, 0x00000000);
1279 nv_mthd(dev, 0x9097, 0x0da0, 0x00000000);
1280 nv_mthd(dev, 0x9097, 0x1508, 0x80000000);
1281 nv_mthd(dev, 0x9097, 0x150c, 0x40000000);
1282 nv_mthd(dev, 0x9097, 0x1668, 0x00000000);
1283 nv_mthd(dev, 0x9097, 0x0318, 0x00000008);
1284 nv_mthd(dev, 0x9097, 0x031c, 0x00000008);
1285 nv_mthd(dev, 0x9097, 0x0d9c, 0x00000001);
1286 nv_mthd(dev, 0x9097, 0x07dc, 0x00000000);
1287 nv_mthd(dev, 0x9097, 0x074c, 0x00000055);
1288 nv_mthd(dev, 0x9097, 0x1420, 0x00000003);
1289 nv_mthd(dev, 0x9097, 0x17bc, 0x00000000);
1290 nv_mthd(dev, 0x9097, 0x17c0, 0x00000000);
1291 nv_mthd(dev, 0x9097, 0x17c4, 0x00000001);
1292 nv_mthd(dev, 0x9097, 0x1008, 0x00000008);
1293 nv_mthd(dev, 0x9097, 0x100c, 0x00000040);
1294 nv_mthd(dev, 0x9097, 0x1010, 0x0000012c);
1295 nv_mthd(dev, 0x9097, 0x0d60, 0x00000040);
1296 nv_mthd(dev, 0x9097, 0x075c, 0x00000003);
1297 nv_mthd(dev, 0x9097, 0x1018, 0x00000020);
1298 nv_mthd(dev, 0x9097, 0x101c, 0x00000001);
1299 nv_mthd(dev, 0x9097, 0x1020, 0x00000020);
1300 nv_mthd(dev, 0x9097, 0x1024, 0x00000001);
1301 nv_mthd(dev, 0x9097, 0x1444, 0x00000000);
1302 nv_mthd(dev, 0x9097, 0x1448, 0x00000000);
1303 nv_mthd(dev, 0x9097, 0x144c, 0x00000000);
1304 nv_mthd(dev, 0x9097, 0x0360, 0x20164010);
1305 nv_mthd(dev, 0x9097, 0x0364, 0x00000020);
1306 nv_mthd(dev, 0x9097, 0x0368, 0x00000000);
1307 nv_mthd(dev, 0x9097, 0x0de4, 0x00000000);
1308 nv_mthd(dev, 0x9097, 0x0204, 0x00000006);
1309 nv_mthd(dev, 0x9097, 0x0208, 0x00000000);
1310 nv_mthd(dev, 0x9097, 0x02cc, 0x003fffff);
1311 nv_mthd(dev, 0x9097, 0x02d0, 0x00000c48);
1312 nv_mthd(dev, 0x9097, 0x1220, 0x00000005);
1313 nv_mthd(dev, 0x9097, 0x0fdc, 0x00000000);
1314 nv_mthd(dev, 0x9097, 0x0f98, 0x00300008);
1315 nv_mthd(dev, 0x9097, 0x1284, 0x04000080);
1316 nv_mthd(dev, 0x9097, 0x1450, 0x00300008);
1317 nv_mthd(dev, 0x9097, 0x1454, 0x04000080);
1318 nv_mthd(dev, 0x9097, 0x0214, 0x00000000);
1319 /* in trace, right after 0x90c0, not here */
1320 nv_mthd(dev, 0x9097, 0x3410, 0x80002006);
1321}
1322
1323static void
1324nvc0_grctx_generate_902d(struct drm_device *dev)
1325{
1326 nv_mthd(dev, 0x902d, 0x0200, 0x000000cf);
1327 nv_mthd(dev, 0x902d, 0x0204, 0x00000001);
1328 nv_mthd(dev, 0x902d, 0x0208, 0x00000020);
1329 nv_mthd(dev, 0x902d, 0x020c, 0x00000001);
1330 nv_mthd(dev, 0x902d, 0x0210, 0x00000000);
1331 nv_mthd(dev, 0x902d, 0x0214, 0x00000080);
1332 nv_mthd(dev, 0x902d, 0x0218, 0x00000100);
1333 nv_mthd(dev, 0x902d, 0x021c, 0x00000100);
1334 nv_mthd(dev, 0x902d, 0x0220, 0x00000000);
1335 nv_mthd(dev, 0x902d, 0x0224, 0x00000000);
1336 nv_mthd(dev, 0x902d, 0x0230, 0x000000cf);
1337 nv_mthd(dev, 0x902d, 0x0234, 0x00000001);
1338 nv_mthd(dev, 0x902d, 0x0238, 0x00000020);
1339 nv_mthd(dev, 0x902d, 0x023c, 0x00000001);
1340 nv_mthd(dev, 0x902d, 0x0244, 0x00000080);
1341 nv_mthd(dev, 0x902d, 0x0248, 0x00000100);
1342 nv_mthd(dev, 0x902d, 0x024c, 0x00000100);
1343}
1344
1345static void
1346nvc0_grctx_generate_9039(struct drm_device *dev)
1347{
1348 nv_mthd(dev, 0x9039, 0x030c, 0x00000000);
1349 nv_mthd(dev, 0x9039, 0x0310, 0x00000000);
1350 nv_mthd(dev, 0x9039, 0x0314, 0x00000000);
1351 nv_mthd(dev, 0x9039, 0x0320, 0x00000000);
1352 nv_mthd(dev, 0x9039, 0x0238, 0x00000000);
1353 nv_mthd(dev, 0x9039, 0x023c, 0x00000000);
1354 nv_mthd(dev, 0x9039, 0x0318, 0x00000000);
1355 nv_mthd(dev, 0x9039, 0x031c, 0x00000000);
1356}
1357
1358static void
1359nvc0_grctx_generate_90c0(struct drm_device *dev)
1360{
1361 nv_mthd(dev, 0x90c0, 0x270c, 0x00000000);
1362 nv_mthd(dev, 0x90c0, 0x272c, 0x00000000);
1363 nv_mthd(dev, 0x90c0, 0x274c, 0x00000000);
1364 nv_mthd(dev, 0x90c0, 0x276c, 0x00000000);
1365 nv_mthd(dev, 0x90c0, 0x278c, 0x00000000);
1366 nv_mthd(dev, 0x90c0, 0x27ac, 0x00000000);
1367 nv_mthd(dev, 0x90c0, 0x27cc, 0x00000000);
1368 nv_mthd(dev, 0x90c0, 0x27ec, 0x00000000);
1369 nv_mthd(dev, 0x90c0, 0x030c, 0x00000001);
1370 nv_mthd(dev, 0x90c0, 0x1944, 0x00000000);
1371 nv_mthd(dev, 0x90c0, 0x0758, 0x00000100);
1372 nv_mthd(dev, 0x90c0, 0x02c4, 0x00000000);
1373 nv_mthd(dev, 0x90c0, 0x0790, 0x00000000);
1374 nv_mthd(dev, 0x90c0, 0x0794, 0x00000000);
1375 nv_mthd(dev, 0x90c0, 0x0798, 0x00000000);
1376 nv_mthd(dev, 0x90c0, 0x079c, 0x00000000);
1377 nv_mthd(dev, 0x90c0, 0x07a0, 0x00000000);
1378 nv_mthd(dev, 0x90c0, 0x077c, 0x00000000);
1379 nv_mthd(dev, 0x90c0, 0x0204, 0x00000000);
1380 nv_mthd(dev, 0x90c0, 0x0208, 0x00000000);
1381 nv_mthd(dev, 0x90c0, 0x020c, 0x00000000);
1382 nv_mthd(dev, 0x90c0, 0x0214, 0x00000000);
1383 nv_mthd(dev, 0x90c0, 0x024c, 0x00000000);
1384 nv_mthd(dev, 0x90c0, 0x0d94, 0x00000001);
1385 nv_mthd(dev, 0x90c0, 0x1608, 0x00000000);
1386 nv_mthd(dev, 0x90c0, 0x160c, 0x00000000);
1387 nv_mthd(dev, 0x90c0, 0x1664, 0x00000000);
1388}
1389
1390static void
1391nvc0_grctx_generate_dispatch(struct drm_device *dev)
1392{
1393 int i;
1394
1395 nv_wr32(dev, 0x404004, 0x00000000);
1396 nv_wr32(dev, 0x404008, 0x00000000);
1397 nv_wr32(dev, 0x40400c, 0x00000000);
1398 nv_wr32(dev, 0x404010, 0x00000000);
1399 nv_wr32(dev, 0x404014, 0x00000000);
1400 nv_wr32(dev, 0x404018, 0x00000000);
1401 nv_wr32(dev, 0x40401c, 0x00000000);
1402 nv_wr32(dev, 0x404020, 0x00000000);
1403 nv_wr32(dev, 0x404024, 0x00000000);
1404 nv_wr32(dev, 0x404028, 0x00000000);
1405 nv_wr32(dev, 0x40402c, 0x00000000);
1406 nv_wr32(dev, 0x404044, 0x00000000);
1407 nv_wr32(dev, 0x404094, 0x00000000);
1408 nv_wr32(dev, 0x404098, 0x00000000);
1409 nv_wr32(dev, 0x40409c, 0x00000000);
1410 nv_wr32(dev, 0x4040a0, 0x00000000);
1411 nv_wr32(dev, 0x4040a4, 0x00000000);
1412 nv_wr32(dev, 0x4040a8, 0x00000000);
1413 nv_wr32(dev, 0x4040ac, 0x00000000);
1414 nv_wr32(dev, 0x4040b0, 0x00000000);
1415 nv_wr32(dev, 0x4040b4, 0x00000000);
1416 nv_wr32(dev, 0x4040b8, 0x00000000);
1417 nv_wr32(dev, 0x4040bc, 0x00000000);
1418 nv_wr32(dev, 0x4040c0, 0x00000000);
1419 nv_wr32(dev, 0x4040c4, 0x00000000);
1420 nv_wr32(dev, 0x4040c8, 0xf0000087);
1421 nv_wr32(dev, 0x4040d4, 0x00000000);
1422 nv_wr32(dev, 0x4040d8, 0x00000000);
1423 nv_wr32(dev, 0x4040dc, 0x00000000);
1424 nv_wr32(dev, 0x4040e0, 0x00000000);
1425 nv_wr32(dev, 0x4040e4, 0x00000000);
1426 nv_wr32(dev, 0x4040e8, 0x00001000);
1427 nv_wr32(dev, 0x4040f8, 0x00000000);
1428 nv_wr32(dev, 0x404130, 0x00000000);
1429 nv_wr32(dev, 0x404134, 0x00000000);
1430 nv_wr32(dev, 0x404138, 0x20000040);
1431 nv_wr32(dev, 0x404150, 0x0000002e);
1432 nv_wr32(dev, 0x404154, 0x00000400);
1433 nv_wr32(dev, 0x404158, 0x00000200);
1434 nv_wr32(dev, 0x404164, 0x00000055);
1435 nv_wr32(dev, 0x404168, 0x00000000);
1436 nv_wr32(dev, 0x404174, 0x00000000);
1437 nv_wr32(dev, 0x404178, 0x00000000);
1438 nv_wr32(dev, 0x40417c, 0x00000000);
1439 for (i = 0; i < 8; i++)
1440 nv_wr32(dev, 0x404200 + (i * 4), 0x00000000); /* subc */
1441}
1442
1443static void
1444nvc0_grctx_generate_macro(struct drm_device *dev)
1445{
1446 nv_wr32(dev, 0x404404, 0x00000000);
1447 nv_wr32(dev, 0x404408, 0x00000000);
1448 nv_wr32(dev, 0x40440c, 0x00000000);
1449 nv_wr32(dev, 0x404410, 0x00000000);
1450 nv_wr32(dev, 0x404414, 0x00000000);
1451 nv_wr32(dev, 0x404418, 0x00000000);
1452 nv_wr32(dev, 0x40441c, 0x00000000);
1453 nv_wr32(dev, 0x404420, 0x00000000);
1454 nv_wr32(dev, 0x404424, 0x00000000);
1455 nv_wr32(dev, 0x404428, 0x00000000);
1456 nv_wr32(dev, 0x40442c, 0x00000000);
1457 nv_wr32(dev, 0x404430, 0x00000000);
1458 nv_wr32(dev, 0x404434, 0x00000000);
1459 nv_wr32(dev, 0x404438, 0x00000000);
1460 nv_wr32(dev, 0x404460, 0x00000000);
1461 nv_wr32(dev, 0x404464, 0x00000000);
1462 nv_wr32(dev, 0x404468, 0x00ffffff);
1463 nv_wr32(dev, 0x40446c, 0x00000000);
1464 nv_wr32(dev, 0x404480, 0x00000001);
1465 nv_wr32(dev, 0x404498, 0x00000001);
1466}
1467
1468static void
1469nvc0_grctx_generate_m2mf(struct drm_device *dev)
1470{
1471 nv_wr32(dev, 0x404604, 0x00000015);
1472 nv_wr32(dev, 0x404608, 0x00000000);
1473 nv_wr32(dev, 0x40460c, 0x00002e00);
1474 nv_wr32(dev, 0x404610, 0x00000100);
1475 nv_wr32(dev, 0x404618, 0x00000000);
1476 nv_wr32(dev, 0x40461c, 0x00000000);
1477 nv_wr32(dev, 0x404620, 0x00000000);
1478 nv_wr32(dev, 0x404624, 0x00000000);
1479 nv_wr32(dev, 0x404628, 0x00000000);
1480 nv_wr32(dev, 0x40462c, 0x00000000);
1481 nv_wr32(dev, 0x404630, 0x00000000);
1482 nv_wr32(dev, 0x404634, 0x00000000);
1483 nv_wr32(dev, 0x404638, 0x00000004);
1484 nv_wr32(dev, 0x40463c, 0x00000000);
1485 nv_wr32(dev, 0x404640, 0x00000000);
1486 nv_wr32(dev, 0x404644, 0x00000000);
1487 nv_wr32(dev, 0x404648, 0x00000000);
1488 nv_wr32(dev, 0x40464c, 0x00000000);
1489 nv_wr32(dev, 0x404650, 0x00000000);
1490 nv_wr32(dev, 0x404654, 0x00000000);
1491 nv_wr32(dev, 0x404658, 0x00000000);
1492 nv_wr32(dev, 0x40465c, 0x007f0100);
1493 nv_wr32(dev, 0x404660, 0x00000000);
1494 nv_wr32(dev, 0x404664, 0x00000000);
1495 nv_wr32(dev, 0x404668, 0x00000000);
1496 nv_wr32(dev, 0x40466c, 0x00000000);
1497 nv_wr32(dev, 0x404670, 0x00000000);
1498 nv_wr32(dev, 0x404674, 0x00000000);
1499 nv_wr32(dev, 0x404678, 0x00000000);
1500 nv_wr32(dev, 0x40467c, 0x00000002);
1501 nv_wr32(dev, 0x404680, 0x00000000);
1502 nv_wr32(dev, 0x404684, 0x00000000);
1503 nv_wr32(dev, 0x404688, 0x00000000);
1504 nv_wr32(dev, 0x40468c, 0x00000000);
1505 nv_wr32(dev, 0x404690, 0x00000000);
1506 nv_wr32(dev, 0x404694, 0x00000000);
1507 nv_wr32(dev, 0x404698, 0x00000000);
1508 nv_wr32(dev, 0x40469c, 0x00000000);
1509 nv_wr32(dev, 0x4046a0, 0x007f0080);
1510 nv_wr32(dev, 0x4046a4, 0x00000000);
1511 nv_wr32(dev, 0x4046a8, 0x00000000);
1512 nv_wr32(dev, 0x4046ac, 0x00000000);
1513 nv_wr32(dev, 0x4046b0, 0x00000000);
1514 nv_wr32(dev, 0x4046b4, 0x00000000);
1515 nv_wr32(dev, 0x4046b8, 0x00000000);
1516 nv_wr32(dev, 0x4046bc, 0x00000000);
1517 nv_wr32(dev, 0x4046c0, 0x00000000);
1518 nv_wr32(dev, 0x4046c4, 0x00000000);
1519 nv_wr32(dev, 0x4046c8, 0x00000000);
1520 nv_wr32(dev, 0x4046cc, 0x00000000);
1521 nv_wr32(dev, 0x4046d0, 0x00000000);
1522 nv_wr32(dev, 0x4046d4, 0x00000000);
1523 nv_wr32(dev, 0x4046d8, 0x00000000);
1524 nv_wr32(dev, 0x4046dc, 0x00000000);
1525 nv_wr32(dev, 0x4046e0, 0x00000000);
1526 nv_wr32(dev, 0x4046e4, 0x00000000);
1527 nv_wr32(dev, 0x4046e8, 0x00000000);
1528 nv_wr32(dev, 0x4046f0, 0x00000000);
1529 nv_wr32(dev, 0x4046f4, 0x00000000);
1530}
1531
1532static void
1533nvc0_grctx_generate_unk47xx(struct drm_device *dev)
1534{
1535 nv_wr32(dev, 0x404700, 0x00000000);
1536 nv_wr32(dev, 0x404704, 0x00000000);
1537 nv_wr32(dev, 0x404708, 0x00000000);
1538 nv_wr32(dev, 0x40470c, 0x00000000);
1539 nv_wr32(dev, 0x404710, 0x00000000);
1540 nv_wr32(dev, 0x404714, 0x00000000);
1541 nv_wr32(dev, 0x404718, 0x00000000);
1542 nv_wr32(dev, 0x40471c, 0x00000000);
1543 nv_wr32(dev, 0x404720, 0x00000000);
1544 nv_wr32(dev, 0x404724, 0x00000000);
1545 nv_wr32(dev, 0x404728, 0x00000000);
1546 nv_wr32(dev, 0x40472c, 0x00000000);
1547 nv_wr32(dev, 0x404730, 0x00000000);
1548 nv_wr32(dev, 0x404734, 0x00000100);
1549 nv_wr32(dev, 0x404738, 0x00000000);
1550 nv_wr32(dev, 0x40473c, 0x00000000);
1551 nv_wr32(dev, 0x404740, 0x00000000);
1552 nv_wr32(dev, 0x404744, 0x00000000);
1553 nv_wr32(dev, 0x404748, 0x00000000);
1554 nv_wr32(dev, 0x40474c, 0x00000000);
1555 nv_wr32(dev, 0x404750, 0x00000000);
1556 nv_wr32(dev, 0x404754, 0x00000000);
1557}
1558
1559static void
1560nvc0_grctx_generate_unk58xx(struct drm_device *dev)
1561{
1562 nv_wr32(dev, 0x405800, 0x078000bf);
1563 nv_wr32(dev, 0x405830, 0x02180000);
1564 nv_wr32(dev, 0x405834, 0x00000000);
1565 nv_wr32(dev, 0x405838, 0x00000000);
1566 nv_wr32(dev, 0x405854, 0x00000000);
1567 nv_wr32(dev, 0x405870, 0x00000001);
1568 nv_wr32(dev, 0x405874, 0x00000001);
1569 nv_wr32(dev, 0x405878, 0x00000001);
1570 nv_wr32(dev, 0x40587c, 0x00000001);
1571 nv_wr32(dev, 0x405a00, 0x00000000);
1572 nv_wr32(dev, 0x405a04, 0x00000000);
1573 nv_wr32(dev, 0x405a18, 0x00000000);
1574}
1575
1576static void
1577nvc0_grctx_generate_unk60xx(struct drm_device *dev)
1578{
1579 nv_wr32(dev, 0x406020, 0x000103c1);
1580 nv_wr32(dev, 0x406028, 0x00000001);
1581 nv_wr32(dev, 0x40602c, 0x00000001);
1582 nv_wr32(dev, 0x406030, 0x00000001);
1583 nv_wr32(dev, 0x406034, 0x00000001);
1584}
1585
1586static void
1587nvc0_grctx_generate_unk64xx(struct drm_device *dev)
1588{
1589 nv_wr32(dev, 0x4064a8, 0x00000000);
1590 nv_wr32(dev, 0x4064ac, 0x00003fff);
1591 nv_wr32(dev, 0x4064b4, 0x00000000);
1592 nv_wr32(dev, 0x4064b8, 0x00000000);
1593}
1594
1595static void
1596nvc0_grctx_generate_unk78xx(struct drm_device *dev)
1597{
1598 nv_wr32(dev, 0x407804, 0x00000023);
1599 nv_wr32(dev, 0x40780c, 0x0a418820);
1600 nv_wr32(dev, 0x407810, 0x062080e6);
1601 nv_wr32(dev, 0x407814, 0x020398a4);
1602 nv_wr32(dev, 0x407818, 0x0e629062);
1603 nv_wr32(dev, 0x40781c, 0x0a418820);
1604 nv_wr32(dev, 0x407820, 0x000000e6);
1605 nv_wr32(dev, 0x4078bc, 0x00000103);
1606}
1607
1608static void
1609nvc0_grctx_generate_unk80xx(struct drm_device *dev)
1610{
1611 nv_wr32(dev, 0x408000, 0x00000000);
1612 nv_wr32(dev, 0x408004, 0x00000000);
1613 nv_wr32(dev, 0x408008, 0x00000018);
1614 nv_wr32(dev, 0x40800c, 0x00000000);
1615 nv_wr32(dev, 0x408010, 0x00000000);
1616 nv_wr32(dev, 0x408014, 0x00000069);
1617 nv_wr32(dev, 0x408018, 0xe100e100);
1618 nv_wr32(dev, 0x408064, 0x00000000);
1619}
1620
1621static void
1622nvc0_grctx_generate_rop(struct drm_device *dev)
1623{
1624 struct drm_nouveau_private *dev_priv = dev->dev_private;
1625
1626 // ROPC_BROADCAST
1627 nv_wr32(dev, 0x408800, 0x02802a3c);
1628 nv_wr32(dev, 0x408804, 0x00000040);
1629 nv_wr32(dev, 0x408808, 0x0003e00d);
1630 switch (dev_priv->chipset) {
1631 case 0xc0:
1632 nv_wr32(dev, 0x408900, 0x0080b801);
1633 break;
1634 case 0xc3:
1635 case 0xc4:
1636 nv_wr32(dev, 0x408900, 0x3080b801);
1637 break;
1638 }
1639 nv_wr32(dev, 0x408904, 0x02000001);
1640 nv_wr32(dev, 0x408908, 0x00c80929);
1641 nv_wr32(dev, 0x40890c, 0x00000000);
1642 nv_wr32(dev, 0x408980, 0x0000011d);
1643}
1644
1645static void
1646nvc0_grctx_generate_gpc(struct drm_device *dev)
1647{
1648 int i;
1649
1650 // GPC_BROADCAST
1651 nv_wr32(dev, 0x418380, 0x00000016);
1652 nv_wr32(dev, 0x418400, 0x38004e00);
1653 nv_wr32(dev, 0x418404, 0x71e0ffff);
1654 nv_wr32(dev, 0x418408, 0x00000000);
1655 nv_wr32(dev, 0x41840c, 0x00001008);
1656 nv_wr32(dev, 0x418410, 0x0fff0fff);
1657 nv_wr32(dev, 0x418414, 0x00200fff);
1658 nv_wr32(dev, 0x418450, 0x00000000);
1659 nv_wr32(dev, 0x418454, 0x00000000);
1660 nv_wr32(dev, 0x418458, 0x00000000);
1661 nv_wr32(dev, 0x41845c, 0x00000000);
1662 nv_wr32(dev, 0x418460, 0x00000000);
1663 nv_wr32(dev, 0x418464, 0x00000000);
1664 nv_wr32(dev, 0x418468, 0x00000001);
1665 nv_wr32(dev, 0x41846c, 0x00000000);
1666 nv_wr32(dev, 0x418470, 0x00000000);
1667 nv_wr32(dev, 0x418600, 0x0000001f);
1668 nv_wr32(dev, 0x418684, 0x0000000f);
1669 nv_wr32(dev, 0x418700, 0x00000002);
1670 nv_wr32(dev, 0x418704, 0x00000080);
1671 nv_wr32(dev, 0x418708, 0x00000000);
1672 nv_wr32(dev, 0x41870c, 0x07c80000);
1673 nv_wr32(dev, 0x418710, 0x00000000);
1674 nv_wr32(dev, 0x418800, 0x0006860a);
1675 nv_wr32(dev, 0x418808, 0x00000000);
1676 nv_wr32(dev, 0x41880c, 0x00000000);
1677 nv_wr32(dev, 0x418810, 0x00000000);
1678 nv_wr32(dev, 0x418828, 0x00008442);
1679 nv_wr32(dev, 0x418830, 0x00000001);
1680 nv_wr32(dev, 0x4188d8, 0x00000008);
1681 nv_wr32(dev, 0x4188e0, 0x01000000);
1682 nv_wr32(dev, 0x4188e8, 0x00000000);
1683 nv_wr32(dev, 0x4188ec, 0x00000000);
1684 nv_wr32(dev, 0x4188f0, 0x00000000);
1685 nv_wr32(dev, 0x4188f4, 0x00000000);
1686 nv_wr32(dev, 0x4188f8, 0x00000000);
1687 nv_wr32(dev, 0x4188fc, 0x00100000);
1688 nv_wr32(dev, 0x41891c, 0x00ff00ff);
1689 nv_wr32(dev, 0x418924, 0x00000000);
1690 nv_wr32(dev, 0x418928, 0x00ffff00);
1691 nv_wr32(dev, 0x41892c, 0x0000ff00);
1692 for (i = 0; i < 8; i++) {
1693 nv_wr32(dev, 0x418a00 + (i * 0x20), 0x00000000);
1694 nv_wr32(dev, 0x418a04 + (i * 0x20), 0x00000000);
1695 nv_wr32(dev, 0x418a08 + (i * 0x20), 0x00000000);
1696 nv_wr32(dev, 0x418a0c + (i * 0x20), 0x00010000);
1697 nv_wr32(dev, 0x418a10 + (i * 0x20), 0x00000000);
1698 nv_wr32(dev, 0x418a14 + (i * 0x20), 0x00000000);
1699 nv_wr32(dev, 0x418a18 + (i * 0x20), 0x00000000);
1700 }
1701 nv_wr32(dev, 0x418b00, 0x00000000);
1702 nv_wr32(dev, 0x418b08, 0x0a418820);
1703 nv_wr32(dev, 0x418b0c, 0x062080e6);
1704 nv_wr32(dev, 0x418b10, 0x020398a4);
1705 nv_wr32(dev, 0x418b14, 0x0e629062);
1706 nv_wr32(dev, 0x418b18, 0x0a418820);
1707 nv_wr32(dev, 0x418b1c, 0x000000e6);
1708 nv_wr32(dev, 0x418bb8, 0x00000103);
1709 nv_wr32(dev, 0x418c08, 0x00000001);
1710 nv_wr32(dev, 0x418c10, 0x00000000);
1711 nv_wr32(dev, 0x418c14, 0x00000000);
1712 nv_wr32(dev, 0x418c18, 0x00000000);
1713 nv_wr32(dev, 0x418c1c, 0x00000000);
1714 nv_wr32(dev, 0x418c20, 0x00000000);
1715 nv_wr32(dev, 0x418c24, 0x00000000);
1716 nv_wr32(dev, 0x418c28, 0x00000000);
1717 nv_wr32(dev, 0x418c2c, 0x00000000);
1718 nv_wr32(dev, 0x418c80, 0x20200004);
1719 nv_wr32(dev, 0x418c8c, 0x00000001);
1720 nv_wr32(dev, 0x419000, 0x00000780);
1721 nv_wr32(dev, 0x419004, 0x00000000);
1722 nv_wr32(dev, 0x419008, 0x00000000);
1723 nv_wr32(dev, 0x419014, 0x00000004);
1724}
1725
1726static void
1727nvc0_grctx_generate_tp(struct drm_device *dev)
1728{
1729 struct drm_nouveau_private *dev_priv = dev->dev_private;
1730
1731 // GPC_BROADCAST.TP_BROADCAST
1732 nv_wr32(dev, 0x419848, 0x00000000);
1733 nv_wr32(dev, 0x419864, 0x0000012a);
1734 nv_wr32(dev, 0x419888, 0x00000000);
1735 nv_wr32(dev, 0x419a00, 0x000001f0);
1736 nv_wr32(dev, 0x419a04, 0x00000001);
1737 nv_wr32(dev, 0x419a08, 0x00000023);
1738 nv_wr32(dev, 0x419a0c, 0x00020000);
1739 nv_wr32(dev, 0x419a10, 0x00000000);
1740 nv_wr32(dev, 0x419a14, 0x00000200);
1741 nv_wr32(dev, 0x419a1c, 0x00000000);
1742 nv_wr32(dev, 0x419a20, 0x00000800);
1743 if (dev_priv->chipset != 0xc0)
1744 nv_wr32(dev, 0x00419ac4, 0x0007f440); // 0xc3
1745 nv_wr32(dev, 0x419b00, 0x0a418820);
1746 nv_wr32(dev, 0x419b04, 0x062080e6);
1747 nv_wr32(dev, 0x419b08, 0x020398a4);
1748 nv_wr32(dev, 0x419b0c, 0x0e629062);
1749 nv_wr32(dev, 0x419b10, 0x0a418820);
1750 nv_wr32(dev, 0x419b14, 0x000000e6);
1751 nv_wr32(dev, 0x419bd0, 0x00900103);
1752 nv_wr32(dev, 0x419be0, 0x00000001);
1753 nv_wr32(dev, 0x419be4, 0x00000000);
1754 nv_wr32(dev, 0x419c00, 0x00000002);
1755 nv_wr32(dev, 0x419c04, 0x00000006);
1756 nv_wr32(dev, 0x419c08, 0x00000002);
1757 nv_wr32(dev, 0x419c20, 0x00000000);
1758 nv_wr32(dev, 0x419cbc, 0x28137606);
1759 nv_wr32(dev, 0x419ce8, 0x00000000);
1760 nv_wr32(dev, 0x419cf4, 0x00000183);
1761 nv_wr32(dev, 0x419d20, 0x02180000);
1762 nv_wr32(dev, 0x419d24, 0x00001fff);
1763 nv_wr32(dev, 0x419e04, 0x00000000);
1764 nv_wr32(dev, 0x419e08, 0x00000000);
1765 nv_wr32(dev, 0x419e0c, 0x00000000);
1766 nv_wr32(dev, 0x419e10, 0x00000002);
1767 nv_wr32(dev, 0x419e44, 0x001beff2);
1768 nv_wr32(dev, 0x419e48, 0x00000000);
1769 nv_wr32(dev, 0x419e4c, 0x0000000f);
1770 nv_wr32(dev, 0x419e50, 0x00000000);
1771 nv_wr32(dev, 0x419e54, 0x00000000);
1772 nv_wr32(dev, 0x419e58, 0x00000000);
1773 nv_wr32(dev, 0x419e5c, 0x00000000);
1774 nv_wr32(dev, 0x419e60, 0x00000000);
1775 nv_wr32(dev, 0x419e64, 0x00000000);
1776 nv_wr32(dev, 0x419e68, 0x00000000);
1777 nv_wr32(dev, 0x419e6c, 0x00000000);
1778 nv_wr32(dev, 0x419e70, 0x00000000);
1779 nv_wr32(dev, 0x419e74, 0x00000000);
1780 nv_wr32(dev, 0x419e78, 0x00000000);
1781 nv_wr32(dev, 0x419e7c, 0x00000000);
1782 nv_wr32(dev, 0x419e80, 0x00000000);
1783 nv_wr32(dev, 0x419e84, 0x00000000);
1784 nv_wr32(dev, 0x419e88, 0x00000000);
1785 nv_wr32(dev, 0x419e8c, 0x00000000);
1786 nv_wr32(dev, 0x419e90, 0x00000000);
1787 nv_wr32(dev, 0x419e98, 0x00000000);
1788 if (dev_priv->chipset != 0xc0)
1789 nv_wr32(dev, 0x419ee0, 0x00011110);
1790 nv_wr32(dev, 0x419f50, 0x00000000);
1791 nv_wr32(dev, 0x419f54, 0x00000000);
1792 if (dev_priv->chipset != 0xc0)
1793 nv_wr32(dev, 0x419f58, 0x00000000);
1794}
1795
1796int
1797nvc0_grctx_generate(struct nouveau_channel *chan)
1798{
1799 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
1800 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
1801 struct nvc0_graph_chan *grch = chan->pgraph_ctx;
1802 struct drm_device *dev = chan->dev;
1803 int i, gpc, tp, id;
1804 u32 r000260;
1805
1806 r000260 = nv_rd32(dev, 0x000260);
1807 nv_wr32(dev, 0x000260, r000260 & ~1);
1808 nv_wr32(dev, 0x400208, 0x00000000);
1809
1810 nvc0_grctx_generate_dispatch(dev);
1811 nvc0_grctx_generate_macro(dev);
1812 nvc0_grctx_generate_m2mf(dev);
1813 nvc0_grctx_generate_unk47xx(dev);
1814 nvc0_grctx_generate_unk58xx(dev);
1815 nvc0_grctx_generate_unk60xx(dev);
1816 nvc0_grctx_generate_unk64xx(dev);
1817 nvc0_grctx_generate_unk78xx(dev);
1818 nvc0_grctx_generate_unk80xx(dev);
1819 nvc0_grctx_generate_rop(dev);
1820 nvc0_grctx_generate_gpc(dev);
1821 nvc0_grctx_generate_tp(dev);
1822
1823 nv_wr32(dev, 0x404154, 0x00000000);
1824
1825 /* fuc "mmio list" writes */
1826 for (i = 0; i < grch->mmio_nr * 8; i += 8) {
1827 u32 reg = nv_ro32(grch->mmio, i + 0);
1828 nv_wr32(dev, reg, nv_ro32(grch->mmio, i + 4));
1829 }
1830
1831 for (tp = 0, id = 0; tp < 4; tp++) {
1832 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
1833 if (tp <= priv->tp_nr[gpc]) {
1834 nv_wr32(dev, TP_UNIT(gpc, tp, 0x698), id);
1835 nv_wr32(dev, TP_UNIT(gpc, tp, 0x4e8), id);
1836 nv_wr32(dev, GPC_UNIT(gpc, 0x0c10 + tp * 4), id);
1837 nv_wr32(dev, TP_UNIT(gpc, tp, 0x088), id);
1838 id++;
1839 }
1840
1841 nv_wr32(dev, GPC_UNIT(gpc, 0x0c08), priv->tp_nr[gpc]);
1842 nv_wr32(dev, GPC_UNIT(gpc, 0x0c8c), priv->tp_nr[gpc]);
1843 }
1844 }
1845
1846 nv_wr32(dev, 0x406028, 0x00000443);
1847 nv_wr32(dev, 0x405870, 0x00000443);
1848 nv_wr32(dev, 0x40602c, 0x00000000);
1849 nv_wr32(dev, 0x405874, 0x00000000);
1850 nv_wr32(dev, 0x406030, 0x00000000);
1851 nv_wr32(dev, 0x405878, 0x00000000);
1852 nv_wr32(dev, 0x406034, 0x00000000);
1853 nv_wr32(dev, 0x40587c, 0x00000000);
1854
1855 if (1) {
1856 const u8 chipset_tp_max[] = { 16, 0, 0, 4, 8 };
1857 u8 max = chipset_tp_max[dev_priv->chipset & 0x0f];
1858 u8 tpnr[GPC_MAX];
1859 u8 data[32];
1860
1861 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
1862 memset(data, 0x1f, sizeof(data));
1863
1864 gpc = -1;
1865 for (tp = 0; tp < priv->tp_total; tp++) {
1866 do {
1867 gpc = (gpc + 1) % priv->gpc_nr;
1868 } while (!tpnr[gpc]);
1869 tpnr[gpc]--;
1870 data[tp] = gpc;
1871 }
1872
1873 for (i = 0; i < max / 4; i++)
1874 nv_wr32(dev, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
1875 }
1876
1877 if (1) {
1878 u32 data[6] = {};
1879 u8 tpnr[GPC_MAX];
1880
1881 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
1882
1883 for (tp = 0; tp < priv->tp_total; tp++) {
1884 do {
1885 gpc = (gpc + 1) % priv->gpc_nr;
1886 } while (!tpnr[gpc]);
1887 tpnr[gpc]--;
1888
1889 data[tp / 6] |= gpc << ((tp % 6) * 5);
1890 }
1891
1892 for (; tp < 32; tp++)
1893 data[tp / 6] |= 7 << ((tp % 6) * 5);
1894
1895 // GPC_BROADCAST
1896 nv_wr32(dev, 0x418bb8, (priv->tp_total << 8) |
1897 priv->magic_not_rop_nr);
1898 for (i = 0; i < 6; i++)
1899 nv_wr32(dev, 0x418b08 + (i * 4), data[i]);
1900
1901 // GPC_BROADCAST.TP_BROADCAST
1902 nv_wr32(dev, 0x419bd0, (priv->tp_total << 8) |
1903 priv->magic_not_rop_nr |
1904 priv->magic419bd0);
1905 nv_wr32(dev, 0x419be4, priv->magic419be4);
1906 for (i = 0; i < 6; i++)
1907 nv_wr32(dev, 0x419b00 + (i * 4), data[i]);
1908
1909 // UNK78xx
1910 nv_wr32(dev, 0x4078bc, (priv->tp_total << 8) |
1911 priv->magic_not_rop_nr);
1912 for (i = 0; i < 6; i++)
1913 nv_wr32(dev, 0x40780c + (i * 4), data[i]);
1914 }
1915
1916 if (1) {
1917 u32 tp_mask = 0, tp_set = 0;
1918 u8 tpnr[GPC_MAX];
1919
1920 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
1921 for (gpc = 0; gpc < priv->gpc_nr; gpc++)
1922 tp_mask |= ((1 << priv->tp_nr[gpc]) - 1) << (gpc * 8);
1923
1924 gpc = -1;
1925 for (i = 0, gpc = -1; i < 32; i++) {
1926 int ltp = i * (priv->tp_total - 1) / 32;
1927
1928 do {
1929 gpc = (gpc + 1) % priv->gpc_nr;
1930 } while (!tpnr[gpc]);
1931 tp = priv->tp_nr[gpc] - tpnr[gpc]--;
1932
1933 tp_set |= 1 << ((gpc * 8) + tp);
1934
1935 do {
1936 nv_wr32(dev, 0x406800 + (i * 0x20), tp_set);
1937 tp_set ^= tp_mask;
1938 nv_wr32(dev, 0x406c00 + (i * 0x20), tp_set);
1939 tp_set ^= tp_mask;
1940 } while (ltp == (++i * (priv->tp_total - 1) / 32));
1941 i--;
1942 }
1943 }
1944
1945 nv_wr32(dev, 0x400208, 0x80000000);
1946
1947 nv_icmd(dev, 0x00001000, 0x00000004);
1948 nv_icmd(dev, 0x000000a9, 0x0000ffff);
1949 nv_icmd(dev, 0x00000038, 0x0fac6881);
1950 nv_icmd(dev, 0x0000003d, 0x00000001);
1951 nv_icmd(dev, 0x000000e8, 0x00000400);
1952 nv_icmd(dev, 0x000000e9, 0x00000400);
1953 nv_icmd(dev, 0x000000ea, 0x00000400);
1954 nv_icmd(dev, 0x000000eb, 0x00000400);
1955 nv_icmd(dev, 0x000000ec, 0x00000400);
1956 nv_icmd(dev, 0x000000ed, 0x00000400);
1957 nv_icmd(dev, 0x000000ee, 0x00000400);
1958 nv_icmd(dev, 0x000000ef, 0x00000400);
1959 nv_icmd(dev, 0x00000078, 0x00000300);
1960 nv_icmd(dev, 0x00000079, 0x00000300);
1961 nv_icmd(dev, 0x0000007a, 0x00000300);
1962 nv_icmd(dev, 0x0000007b, 0x00000300);
1963 nv_icmd(dev, 0x0000007c, 0x00000300);
1964 nv_icmd(dev, 0x0000007d, 0x00000300);
1965 nv_icmd(dev, 0x0000007e, 0x00000300);
1966 nv_icmd(dev, 0x0000007f, 0x00000300);
1967 nv_icmd(dev, 0x00000050, 0x00000011);
1968 nv_icmd(dev, 0x00000058, 0x00000008);
1969 nv_icmd(dev, 0x00000059, 0x00000008);
1970 nv_icmd(dev, 0x0000005a, 0x00000008);
1971 nv_icmd(dev, 0x0000005b, 0x00000008);
1972 nv_icmd(dev, 0x0000005c, 0x00000008);
1973 nv_icmd(dev, 0x0000005d, 0x00000008);
1974 nv_icmd(dev, 0x0000005e, 0x00000008);
1975 nv_icmd(dev, 0x0000005f, 0x00000008);
1976 nv_icmd(dev, 0x00000208, 0x00000001);
1977 nv_icmd(dev, 0x00000209, 0x00000001);
1978 nv_icmd(dev, 0x0000020a, 0x00000001);
1979 nv_icmd(dev, 0x0000020b, 0x00000001);
1980 nv_icmd(dev, 0x0000020c, 0x00000001);
1981 nv_icmd(dev, 0x0000020d, 0x00000001);
1982 nv_icmd(dev, 0x0000020e, 0x00000001);
1983 nv_icmd(dev, 0x0000020f, 0x00000001);
1984 nv_icmd(dev, 0x00000081, 0x00000001);
1985 nv_icmd(dev, 0x00000085, 0x00000004);
1986 nv_icmd(dev, 0x00000088, 0x00000400);
1987 nv_icmd(dev, 0x00000090, 0x00000300);
1988 nv_icmd(dev, 0x00000098, 0x00001001);
1989 nv_icmd(dev, 0x000000e3, 0x00000001);
1990 nv_icmd(dev, 0x000000da, 0x00000001);
1991 nv_icmd(dev, 0x000000f8, 0x00000003);
1992 nv_icmd(dev, 0x000000fa, 0x00000001);
1993 nv_icmd(dev, 0x0000009f, 0x0000ffff);
1994 nv_icmd(dev, 0x000000a0, 0x0000ffff);
1995 nv_icmd(dev, 0x000000a1, 0x0000ffff);
1996 nv_icmd(dev, 0x000000a2, 0x0000ffff);
1997 nv_icmd(dev, 0x000000b1, 0x00000001);
1998 nv_icmd(dev, 0x000000b2, 0x00000000);
1999 nv_icmd(dev, 0x000000b3, 0x00000000);
2000 nv_icmd(dev, 0x000000b4, 0x00000000);
2001 nv_icmd(dev, 0x000000b5, 0x00000000);
2002 nv_icmd(dev, 0x000000b6, 0x00000000);
2003 nv_icmd(dev, 0x000000b7, 0x00000000);
2004 nv_icmd(dev, 0x000000b8, 0x00000000);
2005 nv_icmd(dev, 0x000000b9, 0x00000000);
2006 nv_icmd(dev, 0x000000ba, 0x00000000);
2007 nv_icmd(dev, 0x000000bb, 0x00000000);
2008 nv_icmd(dev, 0x000000bc, 0x00000000);
2009 nv_icmd(dev, 0x000000bd, 0x00000000);
2010 nv_icmd(dev, 0x000000be, 0x00000000);
2011 nv_icmd(dev, 0x000000bf, 0x00000000);
2012 nv_icmd(dev, 0x000000c0, 0x00000000);
2013 nv_icmd(dev, 0x000000c1, 0x00000000);
2014 nv_icmd(dev, 0x000000c2, 0x00000000);
2015 nv_icmd(dev, 0x000000c3, 0x00000000);
2016 nv_icmd(dev, 0x000000c4, 0x00000000);
2017 nv_icmd(dev, 0x000000c5, 0x00000000);
2018 nv_icmd(dev, 0x000000c6, 0x00000000);
2019 nv_icmd(dev, 0x000000c7, 0x00000000);
2020 nv_icmd(dev, 0x000000c8, 0x00000000);
2021 nv_icmd(dev, 0x000000c9, 0x00000000);
2022 nv_icmd(dev, 0x000000ca, 0x00000000);
2023 nv_icmd(dev, 0x000000cb, 0x00000000);
2024 nv_icmd(dev, 0x000000cc, 0x00000000);
2025 nv_icmd(dev, 0x000000cd, 0x00000000);
2026 nv_icmd(dev, 0x000000ce, 0x00000000);
2027 nv_icmd(dev, 0x000000cf, 0x00000000);
2028 nv_icmd(dev, 0x000000d0, 0x00000000);
2029 nv_icmd(dev, 0x000000d1, 0x00000000);
2030 nv_icmd(dev, 0x000000d2, 0x00000000);
2031 nv_icmd(dev, 0x000000d3, 0x00000000);
2032 nv_icmd(dev, 0x000000d4, 0x00000000);
2033 nv_icmd(dev, 0x000000d5, 0x00000000);
2034 nv_icmd(dev, 0x000000d6, 0x00000000);
2035 nv_icmd(dev, 0x000000d7, 0x00000000);
2036 nv_icmd(dev, 0x000000d8, 0x00000000);
2037 nv_icmd(dev, 0x000000d9, 0x00000000);
2038 nv_icmd(dev, 0x00000210, 0x00000040);
2039 nv_icmd(dev, 0x00000211, 0x00000040);
2040 nv_icmd(dev, 0x00000212, 0x00000040);
2041 nv_icmd(dev, 0x00000213, 0x00000040);
2042 nv_icmd(dev, 0x00000214, 0x00000040);
2043 nv_icmd(dev, 0x00000215, 0x00000040);
2044 nv_icmd(dev, 0x00000216, 0x00000040);
2045 nv_icmd(dev, 0x00000217, 0x00000040);
2046 nv_icmd(dev, 0x00000218, 0x0000c080);
2047 nv_icmd(dev, 0x00000219, 0x0000c080);
2048 nv_icmd(dev, 0x0000021a, 0x0000c080);
2049 nv_icmd(dev, 0x0000021b, 0x0000c080);
2050 nv_icmd(dev, 0x0000021c, 0x0000c080);
2051 nv_icmd(dev, 0x0000021d, 0x0000c080);
2052 nv_icmd(dev, 0x0000021e, 0x0000c080);
2053 nv_icmd(dev, 0x0000021f, 0x0000c080);
2054 nv_icmd(dev, 0x000000ad, 0x0000013e);
2055 nv_icmd(dev, 0x000000e1, 0x00000010);
2056 nv_icmd(dev, 0x00000290, 0x00000000);
2057 nv_icmd(dev, 0x00000291, 0x00000000);
2058 nv_icmd(dev, 0x00000292, 0x00000000);
2059 nv_icmd(dev, 0x00000293, 0x00000000);
2060 nv_icmd(dev, 0x00000294, 0x00000000);
2061 nv_icmd(dev, 0x00000295, 0x00000000);
2062 nv_icmd(dev, 0x00000296, 0x00000000);
2063 nv_icmd(dev, 0x00000297, 0x00000000);
2064 nv_icmd(dev, 0x00000298, 0x00000000);
2065 nv_icmd(dev, 0x00000299, 0x00000000);
2066 nv_icmd(dev, 0x0000029a, 0x00000000);
2067 nv_icmd(dev, 0x0000029b, 0x00000000);
2068 nv_icmd(dev, 0x0000029c, 0x00000000);
2069 nv_icmd(dev, 0x0000029d, 0x00000000);
2070 nv_icmd(dev, 0x0000029e, 0x00000000);
2071 nv_icmd(dev, 0x0000029f, 0x00000000);
2072 nv_icmd(dev, 0x000003b0, 0x00000000);
2073 nv_icmd(dev, 0x000003b1, 0x00000000);
2074 nv_icmd(dev, 0x000003b2, 0x00000000);
2075 nv_icmd(dev, 0x000003b3, 0x00000000);
2076 nv_icmd(dev, 0x000003b4, 0x00000000);
2077 nv_icmd(dev, 0x000003b5, 0x00000000);
2078 nv_icmd(dev, 0x000003b6, 0x00000000);
2079 nv_icmd(dev, 0x000003b7, 0x00000000);
2080 nv_icmd(dev, 0x000003b8, 0x00000000);
2081 nv_icmd(dev, 0x000003b9, 0x00000000);
2082 nv_icmd(dev, 0x000003ba, 0x00000000);
2083 nv_icmd(dev, 0x000003bb, 0x00000000);
2084 nv_icmd(dev, 0x000003bc, 0x00000000);
2085 nv_icmd(dev, 0x000003bd, 0x00000000);
2086 nv_icmd(dev, 0x000003be, 0x00000000);
2087 nv_icmd(dev, 0x000003bf, 0x00000000);
2088 nv_icmd(dev, 0x000002a0, 0x00000000);
2089 nv_icmd(dev, 0x000002a1, 0x00000000);
2090 nv_icmd(dev, 0x000002a2, 0x00000000);
2091 nv_icmd(dev, 0x000002a3, 0x00000000);
2092 nv_icmd(dev, 0x000002a4, 0x00000000);
2093 nv_icmd(dev, 0x000002a5, 0x00000000);
2094 nv_icmd(dev, 0x000002a6, 0x00000000);
2095 nv_icmd(dev, 0x000002a7, 0x00000000);
2096 nv_icmd(dev, 0x000002a8, 0x00000000);
2097 nv_icmd(dev, 0x000002a9, 0x00000000);
2098 nv_icmd(dev, 0x000002aa, 0x00000000);
2099 nv_icmd(dev, 0x000002ab, 0x00000000);
2100 nv_icmd(dev, 0x000002ac, 0x00000000);
2101 nv_icmd(dev, 0x000002ad, 0x00000000);
2102 nv_icmd(dev, 0x000002ae, 0x00000000);
2103 nv_icmd(dev, 0x000002af, 0x00000000);
2104 nv_icmd(dev, 0x00000420, 0x00000000);
2105 nv_icmd(dev, 0x00000421, 0x00000000);
2106 nv_icmd(dev, 0x00000422, 0x00000000);
2107 nv_icmd(dev, 0x00000423, 0x00000000);
2108 nv_icmd(dev, 0x00000424, 0x00000000);
2109 nv_icmd(dev, 0x00000425, 0x00000000);
2110 nv_icmd(dev, 0x00000426, 0x00000000);
2111 nv_icmd(dev, 0x00000427, 0x00000000);
2112 nv_icmd(dev, 0x00000428, 0x00000000);
2113 nv_icmd(dev, 0x00000429, 0x00000000);
2114 nv_icmd(dev, 0x0000042a, 0x00000000);
2115 nv_icmd(dev, 0x0000042b, 0x00000000);
2116 nv_icmd(dev, 0x0000042c, 0x00000000);
2117 nv_icmd(dev, 0x0000042d, 0x00000000);
2118 nv_icmd(dev, 0x0000042e, 0x00000000);
2119 nv_icmd(dev, 0x0000042f, 0x00000000);
2120 nv_icmd(dev, 0x000002b0, 0x00000000);
2121 nv_icmd(dev, 0x000002b1, 0x00000000);
2122 nv_icmd(dev, 0x000002b2, 0x00000000);
2123 nv_icmd(dev, 0x000002b3, 0x00000000);
2124 nv_icmd(dev, 0x000002b4, 0x00000000);
2125 nv_icmd(dev, 0x000002b5, 0x00000000);
2126 nv_icmd(dev, 0x000002b6, 0x00000000);
2127 nv_icmd(dev, 0x000002b7, 0x00000000);
2128 nv_icmd(dev, 0x000002b8, 0x00000000);
2129 nv_icmd(dev, 0x000002b9, 0x00000000);
2130 nv_icmd(dev, 0x000002ba, 0x00000000);
2131 nv_icmd(dev, 0x000002bb, 0x00000000);
2132 nv_icmd(dev, 0x000002bc, 0x00000000);
2133 nv_icmd(dev, 0x000002bd, 0x00000000);
2134 nv_icmd(dev, 0x000002be, 0x00000000);
2135 nv_icmd(dev, 0x000002bf, 0x00000000);
2136 nv_icmd(dev, 0x00000430, 0x00000000);
2137 nv_icmd(dev, 0x00000431, 0x00000000);
2138 nv_icmd(dev, 0x00000432, 0x00000000);
2139 nv_icmd(dev, 0x00000433, 0x00000000);
2140 nv_icmd(dev, 0x00000434, 0x00000000);
2141 nv_icmd(dev, 0x00000435, 0x00000000);
2142 nv_icmd(dev, 0x00000436, 0x00000000);
2143 nv_icmd(dev, 0x00000437, 0x00000000);
2144 nv_icmd(dev, 0x00000438, 0x00000000);
2145 nv_icmd(dev, 0x00000439, 0x00000000);
2146 nv_icmd(dev, 0x0000043a, 0x00000000);
2147 nv_icmd(dev, 0x0000043b, 0x00000000);
2148 nv_icmd(dev, 0x0000043c, 0x00000000);
2149 nv_icmd(dev, 0x0000043d, 0x00000000);
2150 nv_icmd(dev, 0x0000043e, 0x00000000);
2151 nv_icmd(dev, 0x0000043f, 0x00000000);
2152 nv_icmd(dev, 0x000002c0, 0x00000000);
2153 nv_icmd(dev, 0x000002c1, 0x00000000);
2154 nv_icmd(dev, 0x000002c2, 0x00000000);
2155 nv_icmd(dev, 0x000002c3, 0x00000000);
2156 nv_icmd(dev, 0x000002c4, 0x00000000);
2157 nv_icmd(dev, 0x000002c5, 0x00000000);
2158 nv_icmd(dev, 0x000002c6, 0x00000000);
2159 nv_icmd(dev, 0x000002c7, 0x00000000);
2160 nv_icmd(dev, 0x000002c8, 0x00000000);
2161 nv_icmd(dev, 0x000002c9, 0x00000000);
2162 nv_icmd(dev, 0x000002ca, 0x00000000);
2163 nv_icmd(dev, 0x000002cb, 0x00000000);
2164 nv_icmd(dev, 0x000002cc, 0x00000000);
2165 nv_icmd(dev, 0x000002cd, 0x00000000);
2166 nv_icmd(dev, 0x000002ce, 0x00000000);
2167 nv_icmd(dev, 0x000002cf, 0x00000000);
2168 nv_icmd(dev, 0x000004d0, 0x00000000);
2169 nv_icmd(dev, 0x000004d1, 0x00000000);
2170 nv_icmd(dev, 0x000004d2, 0x00000000);
2171 nv_icmd(dev, 0x000004d3, 0x00000000);
2172 nv_icmd(dev, 0x000004d4, 0x00000000);
2173 nv_icmd(dev, 0x000004d5, 0x00000000);
2174 nv_icmd(dev, 0x000004d6, 0x00000000);
2175 nv_icmd(dev, 0x000004d7, 0x00000000);
2176 nv_icmd(dev, 0x000004d8, 0x00000000);
2177 nv_icmd(dev, 0x000004d9, 0x00000000);
2178 nv_icmd(dev, 0x000004da, 0x00000000);
2179 nv_icmd(dev, 0x000004db, 0x00000000);
2180 nv_icmd(dev, 0x000004dc, 0x00000000);
2181 nv_icmd(dev, 0x000004dd, 0x00000000);
2182 nv_icmd(dev, 0x000004de, 0x00000000);
2183 nv_icmd(dev, 0x000004df, 0x00000000);
2184 nv_icmd(dev, 0x00000720, 0x00000000);
2185 nv_icmd(dev, 0x00000721, 0x00000000);
2186 nv_icmd(dev, 0x00000722, 0x00000000);
2187 nv_icmd(dev, 0x00000723, 0x00000000);
2188 nv_icmd(dev, 0x00000724, 0x00000000);
2189 nv_icmd(dev, 0x00000725, 0x00000000);
2190 nv_icmd(dev, 0x00000726, 0x00000000);
2191 nv_icmd(dev, 0x00000727, 0x00000000);
2192 nv_icmd(dev, 0x00000728, 0x00000000);
2193 nv_icmd(dev, 0x00000729, 0x00000000);
2194 nv_icmd(dev, 0x0000072a, 0x00000000);
2195 nv_icmd(dev, 0x0000072b, 0x00000000);
2196 nv_icmd(dev, 0x0000072c, 0x00000000);
2197 nv_icmd(dev, 0x0000072d, 0x00000000);
2198 nv_icmd(dev, 0x0000072e, 0x00000000);
2199 nv_icmd(dev, 0x0000072f, 0x00000000);
2200 nv_icmd(dev, 0x000008c0, 0x00000000);
2201 nv_icmd(dev, 0x000008c1, 0x00000000);
2202 nv_icmd(dev, 0x000008c2, 0x00000000);
2203 nv_icmd(dev, 0x000008c3, 0x00000000);
2204 nv_icmd(dev, 0x000008c4, 0x00000000);
2205 nv_icmd(dev, 0x000008c5, 0x00000000);
2206 nv_icmd(dev, 0x000008c6, 0x00000000);
2207 nv_icmd(dev, 0x000008c7, 0x00000000);
2208 nv_icmd(dev, 0x000008c8, 0x00000000);
2209 nv_icmd(dev, 0x000008c9, 0x00000000);
2210 nv_icmd(dev, 0x000008ca, 0x00000000);
2211 nv_icmd(dev, 0x000008cb, 0x00000000);
2212 nv_icmd(dev, 0x000008cc, 0x00000000);
2213 nv_icmd(dev, 0x000008cd, 0x00000000);
2214 nv_icmd(dev, 0x000008ce, 0x00000000);
2215 nv_icmd(dev, 0x000008cf, 0x00000000);
2216 nv_icmd(dev, 0x00000890, 0x00000000);
2217 nv_icmd(dev, 0x00000891, 0x00000000);
2218 nv_icmd(dev, 0x00000892, 0x00000000);
2219 nv_icmd(dev, 0x00000893, 0x00000000);
2220 nv_icmd(dev, 0x00000894, 0x00000000);
2221 nv_icmd(dev, 0x00000895, 0x00000000);
2222 nv_icmd(dev, 0x00000896, 0x00000000);
2223 nv_icmd(dev, 0x00000897, 0x00000000);
2224 nv_icmd(dev, 0x00000898, 0x00000000);
2225 nv_icmd(dev, 0x00000899, 0x00000000);
2226 nv_icmd(dev, 0x0000089a, 0x00000000);
2227 nv_icmd(dev, 0x0000089b, 0x00000000);
2228 nv_icmd(dev, 0x0000089c, 0x00000000);
2229 nv_icmd(dev, 0x0000089d, 0x00000000);
2230 nv_icmd(dev, 0x0000089e, 0x00000000);
2231 nv_icmd(dev, 0x0000089f, 0x00000000);
2232 nv_icmd(dev, 0x000008e0, 0x00000000);
2233 nv_icmd(dev, 0x000008e1, 0x00000000);
2234 nv_icmd(dev, 0x000008e2, 0x00000000);
2235 nv_icmd(dev, 0x000008e3, 0x00000000);
2236 nv_icmd(dev, 0x000008e4, 0x00000000);
2237 nv_icmd(dev, 0x000008e5, 0x00000000);
2238 nv_icmd(dev, 0x000008e6, 0x00000000);
2239 nv_icmd(dev, 0x000008e7, 0x00000000);
2240 nv_icmd(dev, 0x000008e8, 0x00000000);
2241 nv_icmd(dev, 0x000008e9, 0x00000000);
2242 nv_icmd(dev, 0x000008ea, 0x00000000);
2243 nv_icmd(dev, 0x000008eb, 0x00000000);
2244 nv_icmd(dev, 0x000008ec, 0x00000000);
2245 nv_icmd(dev, 0x000008ed, 0x00000000);
2246 nv_icmd(dev, 0x000008ee, 0x00000000);
2247 nv_icmd(dev, 0x000008ef, 0x00000000);
2248 nv_icmd(dev, 0x000008a0, 0x00000000);
2249 nv_icmd(dev, 0x000008a1, 0x00000000);
2250 nv_icmd(dev, 0x000008a2, 0x00000000);
2251 nv_icmd(dev, 0x000008a3, 0x00000000);
2252 nv_icmd(dev, 0x000008a4, 0x00000000);
2253 nv_icmd(dev, 0x000008a5, 0x00000000);
2254 nv_icmd(dev, 0x000008a6, 0x00000000);
2255 nv_icmd(dev, 0x000008a7, 0x00000000);
2256 nv_icmd(dev, 0x000008a8, 0x00000000);
2257 nv_icmd(dev, 0x000008a9, 0x00000000);
2258 nv_icmd(dev, 0x000008aa, 0x00000000);
2259 nv_icmd(dev, 0x000008ab, 0x00000000);
2260 nv_icmd(dev, 0x000008ac, 0x00000000);
2261 nv_icmd(dev, 0x000008ad, 0x00000000);
2262 nv_icmd(dev, 0x000008ae, 0x00000000);
2263 nv_icmd(dev, 0x000008af, 0x00000000);
2264 nv_icmd(dev, 0x000008f0, 0x00000000);
2265 nv_icmd(dev, 0x000008f1, 0x00000000);
2266 nv_icmd(dev, 0x000008f2, 0x00000000);
2267 nv_icmd(dev, 0x000008f3, 0x00000000);
2268 nv_icmd(dev, 0x000008f4, 0x00000000);
2269 nv_icmd(dev, 0x000008f5, 0x00000000);
2270 nv_icmd(dev, 0x000008f6, 0x00000000);
2271 nv_icmd(dev, 0x000008f7, 0x00000000);
2272 nv_icmd(dev, 0x000008f8, 0x00000000);
2273 nv_icmd(dev, 0x000008f9, 0x00000000);
2274 nv_icmd(dev, 0x000008fa, 0x00000000);
2275 nv_icmd(dev, 0x000008fb, 0x00000000);
2276 nv_icmd(dev, 0x000008fc, 0x00000000);
2277 nv_icmd(dev, 0x000008fd, 0x00000000);
2278 nv_icmd(dev, 0x000008fe, 0x00000000);
2279 nv_icmd(dev, 0x000008ff, 0x00000000);
2280 nv_icmd(dev, 0x0000094c, 0x000000ff);
2281 nv_icmd(dev, 0x0000094d, 0xffffffff);
2282 nv_icmd(dev, 0x0000094e, 0x00000002);
2283 nv_icmd(dev, 0x000002ec, 0x00000001);
2284 nv_icmd(dev, 0x00000303, 0x00000001);
2285 nv_icmd(dev, 0x000002e6, 0x00000001);
2286 nv_icmd(dev, 0x00000466, 0x00000052);
2287 nv_icmd(dev, 0x00000301, 0x3f800000);
2288 nv_icmd(dev, 0x00000304, 0x30201000);
2289 nv_icmd(dev, 0x00000305, 0x70605040);
2290 nv_icmd(dev, 0x00000306, 0xb8a89888);
2291 nv_icmd(dev, 0x00000307, 0xf8e8d8c8);
2292 nv_icmd(dev, 0x0000030a, 0x00ffff00);
2293 nv_icmd(dev, 0x0000030b, 0x0000001a);
2294 nv_icmd(dev, 0x0000030c, 0x00000001);
2295 nv_icmd(dev, 0x00000318, 0x00000001);
2296 nv_icmd(dev, 0x00000340, 0x00000000);
2297 nv_icmd(dev, 0x00000375, 0x00000001);
2298 nv_icmd(dev, 0x00000351, 0x00000100);
2299 nv_icmd(dev, 0x0000037d, 0x00000006);
2300 nv_icmd(dev, 0x000003a0, 0x00000002);
2301 nv_icmd(dev, 0x000003aa, 0x00000001);
2302 nv_icmd(dev, 0x000003a9, 0x00000001);
2303 nv_icmd(dev, 0x00000380, 0x00000001);
2304 nv_icmd(dev, 0x00000360, 0x00000040);
2305 nv_icmd(dev, 0x00000366, 0x00000000);
2306 nv_icmd(dev, 0x00000367, 0x00000000);
2307 nv_icmd(dev, 0x00000368, 0x00001fff);
2308 nv_icmd(dev, 0x00000370, 0x00000000);
2309 nv_icmd(dev, 0x00000371, 0x00000000);
2310 nv_icmd(dev, 0x00000372, 0x003fffff);
2311 nv_icmd(dev, 0x0000037a, 0x00000012);
2312 nv_icmd(dev, 0x000005e0, 0x00000022);
2313 nv_icmd(dev, 0x000005e1, 0x00000022);
2314 nv_icmd(dev, 0x000005e2, 0x00000022);
2315 nv_icmd(dev, 0x000005e3, 0x00000022);
2316 nv_icmd(dev, 0x000005e4, 0x00000022);
2317 nv_icmd(dev, 0x00000619, 0x00000003);
2318 nv_icmd(dev, 0x00000811, 0x00000003);
2319 nv_icmd(dev, 0x00000812, 0x00000004);
2320 nv_icmd(dev, 0x00000813, 0x00000006);
2321 nv_icmd(dev, 0x00000814, 0x00000008);
2322 nv_icmd(dev, 0x00000815, 0x0000000b);
2323 nv_icmd(dev, 0x00000800, 0x00000001);
2324 nv_icmd(dev, 0x00000801, 0x00000001);
2325 nv_icmd(dev, 0x00000802, 0x00000001);
2326 nv_icmd(dev, 0x00000803, 0x00000001);
2327 nv_icmd(dev, 0x00000804, 0x00000001);
2328 nv_icmd(dev, 0x00000805, 0x00000001);
2329 nv_icmd(dev, 0x00000632, 0x00000001);
2330 nv_icmd(dev, 0x00000633, 0x00000002);
2331 nv_icmd(dev, 0x00000634, 0x00000003);
2332 nv_icmd(dev, 0x00000635, 0x00000004);
2333 nv_icmd(dev, 0x00000654, 0x3f800000);
2334 nv_icmd(dev, 0x00000657, 0x3f800000);
2335 nv_icmd(dev, 0x00000655, 0x3f800000);
2336 nv_icmd(dev, 0x00000656, 0x3f800000);
2337 nv_icmd(dev, 0x000006cd, 0x3f800000);
2338 nv_icmd(dev, 0x000007f5, 0x3f800000);
2339 nv_icmd(dev, 0x000007dc, 0x39291909);
2340 nv_icmd(dev, 0x000007dd, 0x79695949);
2341 nv_icmd(dev, 0x000007de, 0xb9a99989);
2342 nv_icmd(dev, 0x000007df, 0xf9e9d9c9);
2343 nv_icmd(dev, 0x000007e8, 0x00003210);
2344 nv_icmd(dev, 0x000007e9, 0x00007654);
2345 nv_icmd(dev, 0x000007ea, 0x00000098);
2346 nv_icmd(dev, 0x000007ec, 0x39291909);
2347 nv_icmd(dev, 0x000007ed, 0x79695949);
2348 nv_icmd(dev, 0x000007ee, 0xb9a99989);
2349 nv_icmd(dev, 0x000007ef, 0xf9e9d9c9);
2350 nv_icmd(dev, 0x000007f0, 0x00003210);
2351 nv_icmd(dev, 0x000007f1, 0x00007654);
2352 nv_icmd(dev, 0x000007f2, 0x00000098);
2353 nv_icmd(dev, 0x000005a5, 0x00000001);
2354 nv_icmd(dev, 0x00000980, 0x00000000);
2355 nv_icmd(dev, 0x00000981, 0x00000000);
2356 nv_icmd(dev, 0x00000982, 0x00000000);
2357 nv_icmd(dev, 0x00000983, 0x00000000);
2358 nv_icmd(dev, 0x00000984, 0x00000000);
2359 nv_icmd(dev, 0x00000985, 0x00000000);
2360 nv_icmd(dev, 0x00000986, 0x00000000);
2361 nv_icmd(dev, 0x00000987, 0x00000000);
2362 nv_icmd(dev, 0x00000988, 0x00000000);
2363 nv_icmd(dev, 0x00000989, 0x00000000);
2364 nv_icmd(dev, 0x0000098a, 0x00000000);
2365 nv_icmd(dev, 0x0000098b, 0x00000000);
2366 nv_icmd(dev, 0x0000098c, 0x00000000);
2367 nv_icmd(dev, 0x0000098d, 0x00000000);
2368 nv_icmd(dev, 0x0000098e, 0x00000000);
2369 nv_icmd(dev, 0x0000098f, 0x00000000);
2370 nv_icmd(dev, 0x00000990, 0x00000000);
2371 nv_icmd(dev, 0x00000991, 0x00000000);
2372 nv_icmd(dev, 0x00000992, 0x00000000);
2373 nv_icmd(dev, 0x00000993, 0x00000000);
2374 nv_icmd(dev, 0x00000994, 0x00000000);
2375 nv_icmd(dev, 0x00000995, 0x00000000);
2376 nv_icmd(dev, 0x00000996, 0x00000000);
2377 nv_icmd(dev, 0x00000997, 0x00000000);
2378 nv_icmd(dev, 0x00000998, 0x00000000);
2379 nv_icmd(dev, 0x00000999, 0x00000000);
2380 nv_icmd(dev, 0x0000099a, 0x00000000);
2381 nv_icmd(dev, 0x0000099b, 0x00000000);
2382 nv_icmd(dev, 0x0000099c, 0x00000000);
2383 nv_icmd(dev, 0x0000099d, 0x00000000);
2384 nv_icmd(dev, 0x0000099e, 0x00000000);
2385 nv_icmd(dev, 0x0000099f, 0x00000000);
2386 nv_icmd(dev, 0x000009a0, 0x00000000);
2387 nv_icmd(dev, 0x000009a1, 0x00000000);
2388 nv_icmd(dev, 0x000009a2, 0x00000000);
2389 nv_icmd(dev, 0x000009a3, 0x00000000);
2390 nv_icmd(dev, 0x000009a4, 0x00000000);
2391 nv_icmd(dev, 0x000009a5, 0x00000000);
2392 nv_icmd(dev, 0x000009a6, 0x00000000);
2393 nv_icmd(dev, 0x000009a7, 0x00000000);
2394 nv_icmd(dev, 0x000009a8, 0x00000000);
2395 nv_icmd(dev, 0x000009a9, 0x00000000);
2396 nv_icmd(dev, 0x000009aa, 0x00000000);
2397 nv_icmd(dev, 0x000009ab, 0x00000000);
2398 nv_icmd(dev, 0x000009ac, 0x00000000);
2399 nv_icmd(dev, 0x000009ad, 0x00000000);
2400 nv_icmd(dev, 0x000009ae, 0x00000000);
2401 nv_icmd(dev, 0x000009af, 0x00000000);
2402 nv_icmd(dev, 0x000009b0, 0x00000000);
2403 nv_icmd(dev, 0x000009b1, 0x00000000);
2404 nv_icmd(dev, 0x000009b2, 0x00000000);
2405 nv_icmd(dev, 0x000009b3, 0x00000000);
2406 nv_icmd(dev, 0x000009b4, 0x00000000);
2407 nv_icmd(dev, 0x000009b5, 0x00000000);
2408 nv_icmd(dev, 0x000009b6, 0x00000000);
2409 nv_icmd(dev, 0x000009b7, 0x00000000);
2410 nv_icmd(dev, 0x000009b8, 0x00000000);
2411 nv_icmd(dev, 0x000009b9, 0x00000000);
2412 nv_icmd(dev, 0x000009ba, 0x00000000);
2413 nv_icmd(dev, 0x000009bb, 0x00000000);
2414 nv_icmd(dev, 0x000009bc, 0x00000000);
2415 nv_icmd(dev, 0x000009bd, 0x00000000);
2416 nv_icmd(dev, 0x000009be, 0x00000000);
2417 nv_icmd(dev, 0x000009bf, 0x00000000);
2418 nv_icmd(dev, 0x000009c0, 0x00000000);
2419 nv_icmd(dev, 0x000009c1, 0x00000000);
2420 nv_icmd(dev, 0x000009c2, 0x00000000);
2421 nv_icmd(dev, 0x000009c3, 0x00000000);
2422 nv_icmd(dev, 0x000009c4, 0x00000000);
2423 nv_icmd(dev, 0x000009c5, 0x00000000);
2424 nv_icmd(dev, 0x000009c6, 0x00000000);
2425 nv_icmd(dev, 0x000009c7, 0x00000000);
2426 nv_icmd(dev, 0x000009c8, 0x00000000);
2427 nv_icmd(dev, 0x000009c9, 0x00000000);
2428 nv_icmd(dev, 0x000009ca, 0x00000000);
2429 nv_icmd(dev, 0x000009cb, 0x00000000);
2430 nv_icmd(dev, 0x000009cc, 0x00000000);
2431 nv_icmd(dev, 0x000009cd, 0x00000000);
2432 nv_icmd(dev, 0x000009ce, 0x00000000);
2433 nv_icmd(dev, 0x000009cf, 0x00000000);
2434 nv_icmd(dev, 0x000009d0, 0x00000000);
2435 nv_icmd(dev, 0x000009d1, 0x00000000);
2436 nv_icmd(dev, 0x000009d2, 0x00000000);
2437 nv_icmd(dev, 0x000009d3, 0x00000000);
2438 nv_icmd(dev, 0x000009d4, 0x00000000);
2439 nv_icmd(dev, 0x000009d5, 0x00000000);
2440 nv_icmd(dev, 0x000009d6, 0x00000000);
2441 nv_icmd(dev, 0x000009d7, 0x00000000);
2442 nv_icmd(dev, 0x000009d8, 0x00000000);
2443 nv_icmd(dev, 0x000009d9, 0x00000000);
2444 nv_icmd(dev, 0x000009da, 0x00000000);
2445 nv_icmd(dev, 0x000009db, 0x00000000);
2446 nv_icmd(dev, 0x000009dc, 0x00000000);
2447 nv_icmd(dev, 0x000009dd, 0x00000000);
2448 nv_icmd(dev, 0x000009de, 0x00000000);
2449 nv_icmd(dev, 0x000009df, 0x00000000);
2450 nv_icmd(dev, 0x000009e0, 0x00000000);
2451 nv_icmd(dev, 0x000009e1, 0x00000000);
2452 nv_icmd(dev, 0x000009e2, 0x00000000);
2453 nv_icmd(dev, 0x000009e3, 0x00000000);
2454 nv_icmd(dev, 0x000009e4, 0x00000000);
2455 nv_icmd(dev, 0x000009e5, 0x00000000);
2456 nv_icmd(dev, 0x000009e6, 0x00000000);
2457 nv_icmd(dev, 0x000009e7, 0x00000000);
2458 nv_icmd(dev, 0x000009e8, 0x00000000);
2459 nv_icmd(dev, 0x000009e9, 0x00000000);
2460 nv_icmd(dev, 0x000009ea, 0x00000000);
2461 nv_icmd(dev, 0x000009eb, 0x00000000);
2462 nv_icmd(dev, 0x000009ec, 0x00000000);
2463 nv_icmd(dev, 0x000009ed, 0x00000000);
2464 nv_icmd(dev, 0x000009ee, 0x00000000);
2465 nv_icmd(dev, 0x000009ef, 0x00000000);
2466 nv_icmd(dev, 0x000009f0, 0x00000000);
2467 nv_icmd(dev, 0x000009f1, 0x00000000);
2468 nv_icmd(dev, 0x000009f2, 0x00000000);
2469 nv_icmd(dev, 0x000009f3, 0x00000000);
2470 nv_icmd(dev, 0x000009f4, 0x00000000);
2471 nv_icmd(dev, 0x000009f5, 0x00000000);
2472 nv_icmd(dev, 0x000009f6, 0x00000000);
2473 nv_icmd(dev, 0x000009f7, 0x00000000);
2474 nv_icmd(dev, 0x000009f8, 0x00000000);
2475 nv_icmd(dev, 0x000009f9, 0x00000000);
2476 nv_icmd(dev, 0x000009fa, 0x00000000);
2477 nv_icmd(dev, 0x000009fb, 0x00000000);
2478 nv_icmd(dev, 0x000009fc, 0x00000000);
2479 nv_icmd(dev, 0x000009fd, 0x00000000);
2480 nv_icmd(dev, 0x000009fe, 0x00000000);
2481 nv_icmd(dev, 0x000009ff, 0x00000000);
2482 nv_icmd(dev, 0x00000468, 0x00000004);
2483 nv_icmd(dev, 0x0000046c, 0x00000001);
2484 nv_icmd(dev, 0x00000470, 0x00000000);
2485 nv_icmd(dev, 0x00000471, 0x00000000);
2486 nv_icmd(dev, 0x00000472, 0x00000000);
2487 nv_icmd(dev, 0x00000473, 0x00000000);
2488 nv_icmd(dev, 0x00000474, 0x00000000);
2489 nv_icmd(dev, 0x00000475, 0x00000000);
2490 nv_icmd(dev, 0x00000476, 0x00000000);
2491 nv_icmd(dev, 0x00000477, 0x00000000);
2492 nv_icmd(dev, 0x00000478, 0x00000000);
2493 nv_icmd(dev, 0x00000479, 0x00000000);
2494 nv_icmd(dev, 0x0000047a, 0x00000000);
2495 nv_icmd(dev, 0x0000047b, 0x00000000);
2496 nv_icmd(dev, 0x0000047c, 0x00000000);
2497 nv_icmd(dev, 0x0000047d, 0x00000000);
2498 nv_icmd(dev, 0x0000047e, 0x00000000);
2499 nv_icmd(dev, 0x0000047f, 0x00000000);
2500 nv_icmd(dev, 0x00000480, 0x00000000);
2501 nv_icmd(dev, 0x00000481, 0x00000000);
2502 nv_icmd(dev, 0x00000482, 0x00000000);
2503 nv_icmd(dev, 0x00000483, 0x00000000);
2504 nv_icmd(dev, 0x00000484, 0x00000000);
2505 nv_icmd(dev, 0x00000485, 0x00000000);
2506 nv_icmd(dev, 0x00000486, 0x00000000);
2507 nv_icmd(dev, 0x00000487, 0x00000000);
2508 nv_icmd(dev, 0x00000488, 0x00000000);
2509 nv_icmd(dev, 0x00000489, 0x00000000);
2510 nv_icmd(dev, 0x0000048a, 0x00000000);
2511 nv_icmd(dev, 0x0000048b, 0x00000000);
2512 nv_icmd(dev, 0x0000048c, 0x00000000);
2513 nv_icmd(dev, 0x0000048d, 0x00000000);
2514 nv_icmd(dev, 0x0000048e, 0x00000000);
2515 nv_icmd(dev, 0x0000048f, 0x00000000);
2516 nv_icmd(dev, 0x00000490, 0x00000000);
2517 nv_icmd(dev, 0x00000491, 0x00000000);
2518 nv_icmd(dev, 0x00000492, 0x00000000);
2519 nv_icmd(dev, 0x00000493, 0x00000000);
2520 nv_icmd(dev, 0x00000494, 0x00000000);
2521 nv_icmd(dev, 0x00000495, 0x00000000);
2522 nv_icmd(dev, 0x00000496, 0x00000000);
2523 nv_icmd(dev, 0x00000497, 0x00000000);
2524 nv_icmd(dev, 0x00000498, 0x00000000);
2525 nv_icmd(dev, 0x00000499, 0x00000000);
2526 nv_icmd(dev, 0x0000049a, 0x00000000);
2527 nv_icmd(dev, 0x0000049b, 0x00000000);
2528 nv_icmd(dev, 0x0000049c, 0x00000000);
2529 nv_icmd(dev, 0x0000049d, 0x00000000);
2530 nv_icmd(dev, 0x0000049e, 0x00000000);
2531 nv_icmd(dev, 0x0000049f, 0x00000000);
2532 nv_icmd(dev, 0x000004a0, 0x00000000);
2533 nv_icmd(dev, 0x000004a1, 0x00000000);
2534 nv_icmd(dev, 0x000004a2, 0x00000000);
2535 nv_icmd(dev, 0x000004a3, 0x00000000);
2536 nv_icmd(dev, 0x000004a4, 0x00000000);
2537 nv_icmd(dev, 0x000004a5, 0x00000000);
2538 nv_icmd(dev, 0x000004a6, 0x00000000);
2539 nv_icmd(dev, 0x000004a7, 0x00000000);
2540 nv_icmd(dev, 0x000004a8, 0x00000000);
2541 nv_icmd(dev, 0x000004a9, 0x00000000);
2542 nv_icmd(dev, 0x000004aa, 0x00000000);
2543 nv_icmd(dev, 0x000004ab, 0x00000000);
2544 nv_icmd(dev, 0x000004ac, 0x00000000);
2545 nv_icmd(dev, 0x000004ad, 0x00000000);
2546 nv_icmd(dev, 0x000004ae, 0x00000000);
2547 nv_icmd(dev, 0x000004af, 0x00000000);
2548 nv_icmd(dev, 0x000004b0, 0x00000000);
2549 nv_icmd(dev, 0x000004b1, 0x00000000);
2550 nv_icmd(dev, 0x000004b2, 0x00000000);
2551 nv_icmd(dev, 0x000004b3, 0x00000000);
2552 nv_icmd(dev, 0x000004b4, 0x00000000);
2553 nv_icmd(dev, 0x000004b5, 0x00000000);
2554 nv_icmd(dev, 0x000004b6, 0x00000000);
2555 nv_icmd(dev, 0x000004b7, 0x00000000);
2556 nv_icmd(dev, 0x000004b8, 0x00000000);
2557 nv_icmd(dev, 0x000004b9, 0x00000000);
2558 nv_icmd(dev, 0x000004ba, 0x00000000);
2559 nv_icmd(dev, 0x000004bb, 0x00000000);
2560 nv_icmd(dev, 0x000004bc, 0x00000000);
2561 nv_icmd(dev, 0x000004bd, 0x00000000);
2562 nv_icmd(dev, 0x000004be, 0x00000000);
2563 nv_icmd(dev, 0x000004bf, 0x00000000);
2564 nv_icmd(dev, 0x000004c0, 0x00000000);
2565 nv_icmd(dev, 0x000004c1, 0x00000000);
2566 nv_icmd(dev, 0x000004c2, 0x00000000);
2567 nv_icmd(dev, 0x000004c3, 0x00000000);
2568 nv_icmd(dev, 0x000004c4, 0x00000000);
2569 nv_icmd(dev, 0x000004c5, 0x00000000);
2570 nv_icmd(dev, 0x000004c6, 0x00000000);
2571 nv_icmd(dev, 0x000004c7, 0x00000000);
2572 nv_icmd(dev, 0x000004c8, 0x00000000);
2573 nv_icmd(dev, 0x000004c9, 0x00000000);
2574 nv_icmd(dev, 0x000004ca, 0x00000000);
2575 nv_icmd(dev, 0x000004cb, 0x00000000);
2576 nv_icmd(dev, 0x000004cc, 0x00000000);
2577 nv_icmd(dev, 0x000004cd, 0x00000000);
2578 nv_icmd(dev, 0x000004ce, 0x00000000);
2579 nv_icmd(dev, 0x000004cf, 0x00000000);
2580 nv_icmd(dev, 0x00000510, 0x3f800000);
2581 nv_icmd(dev, 0x00000511, 0x3f800000);
2582 nv_icmd(dev, 0x00000512, 0x3f800000);
2583 nv_icmd(dev, 0x00000513, 0x3f800000);
2584 nv_icmd(dev, 0x00000514, 0x3f800000);
2585 nv_icmd(dev, 0x00000515, 0x3f800000);
2586 nv_icmd(dev, 0x00000516, 0x3f800000);
2587 nv_icmd(dev, 0x00000517, 0x3f800000);
2588 nv_icmd(dev, 0x00000518, 0x3f800000);
2589 nv_icmd(dev, 0x00000519, 0x3f800000);
2590 nv_icmd(dev, 0x0000051a, 0x3f800000);
2591 nv_icmd(dev, 0x0000051b, 0x3f800000);
2592 nv_icmd(dev, 0x0000051c, 0x3f800000);
2593 nv_icmd(dev, 0x0000051d, 0x3f800000);
2594 nv_icmd(dev, 0x0000051e, 0x3f800000);
2595 nv_icmd(dev, 0x0000051f, 0x3f800000);
2596 nv_icmd(dev, 0x00000520, 0x000002b6);
2597 nv_icmd(dev, 0x00000529, 0x00000001);
2598 nv_icmd(dev, 0x00000530, 0xffff0000);
2599 nv_icmd(dev, 0x00000531, 0xffff0000);
2600 nv_icmd(dev, 0x00000532, 0xffff0000);
2601 nv_icmd(dev, 0x00000533, 0xffff0000);
2602 nv_icmd(dev, 0x00000534, 0xffff0000);
2603 nv_icmd(dev, 0x00000535, 0xffff0000);
2604 nv_icmd(dev, 0x00000536, 0xffff0000);
2605 nv_icmd(dev, 0x00000537, 0xffff0000);
2606 nv_icmd(dev, 0x00000538, 0xffff0000);
2607 nv_icmd(dev, 0x00000539, 0xffff0000);
2608 nv_icmd(dev, 0x0000053a, 0xffff0000);
2609 nv_icmd(dev, 0x0000053b, 0xffff0000);
2610 nv_icmd(dev, 0x0000053c, 0xffff0000);
2611 nv_icmd(dev, 0x0000053d, 0xffff0000);
2612 nv_icmd(dev, 0x0000053e, 0xffff0000);
2613 nv_icmd(dev, 0x0000053f, 0xffff0000);
2614 nv_icmd(dev, 0x00000585, 0x0000003f);
2615 nv_icmd(dev, 0x00000576, 0x00000003);
2616 nv_icmd(dev, 0x00000586, 0x00000040);
2617 nv_icmd(dev, 0x00000582, 0x00000080);
2618 nv_icmd(dev, 0x00000583, 0x00000080);
2619 nv_icmd(dev, 0x000005c2, 0x00000001);
2620 nv_icmd(dev, 0x00000638, 0x00000001);
2621 nv_icmd(dev, 0x00000639, 0x00000001);
2622 nv_icmd(dev, 0x0000063a, 0x00000002);
2623 nv_icmd(dev, 0x0000063b, 0x00000001);
2624 nv_icmd(dev, 0x0000063c, 0x00000001);
2625 nv_icmd(dev, 0x0000063d, 0x00000002);
2626 nv_icmd(dev, 0x0000063e, 0x00000001);
2627 nv_icmd(dev, 0x000008b8, 0x00000001);
2628 nv_icmd(dev, 0x000008b9, 0x00000001);
2629 nv_icmd(dev, 0x000008ba, 0x00000001);
2630 nv_icmd(dev, 0x000008bb, 0x00000001);
2631 nv_icmd(dev, 0x000008bc, 0x00000001);
2632 nv_icmd(dev, 0x000008bd, 0x00000001);
2633 nv_icmd(dev, 0x000008be, 0x00000001);
2634 nv_icmd(dev, 0x000008bf, 0x00000001);
2635 nv_icmd(dev, 0x00000900, 0x00000001);
2636 nv_icmd(dev, 0x00000901, 0x00000001);
2637 nv_icmd(dev, 0x00000902, 0x00000001);
2638 nv_icmd(dev, 0x00000903, 0x00000001);
2639 nv_icmd(dev, 0x00000904, 0x00000001);
2640 nv_icmd(dev, 0x00000905, 0x00000001);
2641 nv_icmd(dev, 0x00000906, 0x00000001);
2642 nv_icmd(dev, 0x00000907, 0x00000001);
2643 nv_icmd(dev, 0x00000908, 0x00000002);
2644 nv_icmd(dev, 0x00000909, 0x00000002);
2645 nv_icmd(dev, 0x0000090a, 0x00000002);
2646 nv_icmd(dev, 0x0000090b, 0x00000002);
2647 nv_icmd(dev, 0x0000090c, 0x00000002);
2648 nv_icmd(dev, 0x0000090d, 0x00000002);
2649 nv_icmd(dev, 0x0000090e, 0x00000002);
2650 nv_icmd(dev, 0x0000090f, 0x00000002);
2651 nv_icmd(dev, 0x00000910, 0x00000001);
2652 nv_icmd(dev, 0x00000911, 0x00000001);
2653 nv_icmd(dev, 0x00000912, 0x00000001);
2654 nv_icmd(dev, 0x00000913, 0x00000001);
2655 nv_icmd(dev, 0x00000914, 0x00000001);
2656 nv_icmd(dev, 0x00000915, 0x00000001);
2657 nv_icmd(dev, 0x00000916, 0x00000001);
2658 nv_icmd(dev, 0x00000917, 0x00000001);
2659 nv_icmd(dev, 0x00000918, 0x00000001);
2660 nv_icmd(dev, 0x00000919, 0x00000001);
2661 nv_icmd(dev, 0x0000091a, 0x00000001);
2662 nv_icmd(dev, 0x0000091b, 0x00000001);
2663 nv_icmd(dev, 0x0000091c, 0x00000001);
2664 nv_icmd(dev, 0x0000091d, 0x00000001);
2665 nv_icmd(dev, 0x0000091e, 0x00000001);
2666 nv_icmd(dev, 0x0000091f, 0x00000001);
2667 nv_icmd(dev, 0x00000920, 0x00000002);
2668 nv_icmd(dev, 0x00000921, 0x00000002);
2669 nv_icmd(dev, 0x00000922, 0x00000002);
2670 nv_icmd(dev, 0x00000923, 0x00000002);
2671 nv_icmd(dev, 0x00000924, 0x00000002);
2672 nv_icmd(dev, 0x00000925, 0x00000002);
2673 nv_icmd(dev, 0x00000926, 0x00000002);
2674 nv_icmd(dev, 0x00000927, 0x00000002);
2675 nv_icmd(dev, 0x00000928, 0x00000001);
2676 nv_icmd(dev, 0x00000929, 0x00000001);
2677 nv_icmd(dev, 0x0000092a, 0x00000001);
2678 nv_icmd(dev, 0x0000092b, 0x00000001);
2679 nv_icmd(dev, 0x0000092c, 0x00000001);
2680 nv_icmd(dev, 0x0000092d, 0x00000001);
2681 nv_icmd(dev, 0x0000092e, 0x00000001);
2682 nv_icmd(dev, 0x0000092f, 0x00000001);
2683 nv_icmd(dev, 0x00000648, 0x00000001);
2684 nv_icmd(dev, 0x00000649, 0x00000001);
2685 nv_icmd(dev, 0x0000064a, 0x00000001);
2686 nv_icmd(dev, 0x0000064b, 0x00000001);
2687 nv_icmd(dev, 0x0000064c, 0x00000001);
2688 nv_icmd(dev, 0x0000064d, 0x00000001);
2689 nv_icmd(dev, 0x0000064e, 0x00000001);
2690 nv_icmd(dev, 0x0000064f, 0x00000001);
2691 nv_icmd(dev, 0x00000650, 0x00000001);
2692 nv_icmd(dev, 0x00000658, 0x0000000f);
2693 nv_icmd(dev, 0x000007ff, 0x0000000a);
2694 nv_icmd(dev, 0x0000066a, 0x40000000);
2695 nv_icmd(dev, 0x0000066b, 0x10000000);
2696 nv_icmd(dev, 0x0000066c, 0xffff0000);
2697 nv_icmd(dev, 0x0000066d, 0xffff0000);
2698 nv_icmd(dev, 0x000007af, 0x00000008);
2699 nv_icmd(dev, 0x000007b0, 0x00000008);
2700 nv_icmd(dev, 0x000007f6, 0x00000001);
2701 nv_icmd(dev, 0x000006b2, 0x00000055);
2702 nv_icmd(dev, 0x000007ad, 0x00000003);
2703 nv_icmd(dev, 0x00000937, 0x00000001);
2704 nv_icmd(dev, 0x00000971, 0x00000008);
2705 nv_icmd(dev, 0x00000972, 0x00000040);
2706 nv_icmd(dev, 0x00000973, 0x0000012c);
2707 nv_icmd(dev, 0x0000097c, 0x00000040);
2708 nv_icmd(dev, 0x00000979, 0x00000003);
2709 nv_icmd(dev, 0x00000975, 0x00000020);
2710 nv_icmd(dev, 0x00000976, 0x00000001);
2711 nv_icmd(dev, 0x00000977, 0x00000020);
2712 nv_icmd(dev, 0x00000978, 0x00000001);
2713 nv_icmd(dev, 0x00000957, 0x00000003);
2714 nv_icmd(dev, 0x0000095e, 0x20164010);
2715 nv_icmd(dev, 0x0000095f, 0x00000020);
2716 nv_icmd(dev, 0x00000683, 0x00000006);
2717 nv_icmd(dev, 0x00000685, 0x003fffff);
2718 nv_icmd(dev, 0x00000687, 0x00000c48);
2719 nv_icmd(dev, 0x000006a0, 0x00000005);
2720 nv_icmd(dev, 0x00000840, 0x00300008);
2721 nv_icmd(dev, 0x00000841, 0x04000080);
2722 nv_icmd(dev, 0x00000842, 0x00300008);
2723 nv_icmd(dev, 0x00000843, 0x04000080);
2724 nv_icmd(dev, 0x00000818, 0x00000000);
2725 nv_icmd(dev, 0x00000819, 0x00000000);
2726 nv_icmd(dev, 0x0000081a, 0x00000000);
2727 nv_icmd(dev, 0x0000081b, 0x00000000);
2728 nv_icmd(dev, 0x0000081c, 0x00000000);
2729 nv_icmd(dev, 0x0000081d, 0x00000000);
2730 nv_icmd(dev, 0x0000081e, 0x00000000);
2731 nv_icmd(dev, 0x0000081f, 0x00000000);
2732 nv_icmd(dev, 0x00000848, 0x00000000);
2733 nv_icmd(dev, 0x00000849, 0x00000000);
2734 nv_icmd(dev, 0x0000084a, 0x00000000);
2735 nv_icmd(dev, 0x0000084b, 0x00000000);
2736 nv_icmd(dev, 0x0000084c, 0x00000000);
2737 nv_icmd(dev, 0x0000084d, 0x00000000);
2738 nv_icmd(dev, 0x0000084e, 0x00000000);
2739 nv_icmd(dev, 0x0000084f, 0x00000000);
2740 nv_icmd(dev, 0x00000850, 0x00000000);
2741 nv_icmd(dev, 0x00000851, 0x00000000);
2742 nv_icmd(dev, 0x00000852, 0x00000000);
2743 nv_icmd(dev, 0x00000853, 0x00000000);
2744 nv_icmd(dev, 0x00000854, 0x00000000);
2745 nv_icmd(dev, 0x00000855, 0x00000000);
2746 nv_icmd(dev, 0x00000856, 0x00000000);
2747 nv_icmd(dev, 0x00000857, 0x00000000);
2748 nv_icmd(dev, 0x00000738, 0x00000000);
2749 nv_icmd(dev, 0x000006aa, 0x00000001);
2750 nv_icmd(dev, 0x000006ab, 0x00000002);
2751 nv_icmd(dev, 0x000006ac, 0x00000080);
2752 nv_icmd(dev, 0x000006ad, 0x00000100);
2753 nv_icmd(dev, 0x000006ae, 0x00000100);
2754 nv_icmd(dev, 0x000006b1, 0x00000011);
2755 nv_icmd(dev, 0x000006bb, 0x000000cf);
2756 nv_icmd(dev, 0x000006ce, 0x2a712488);
2757 nv_icmd(dev, 0x00000739, 0x4085c000);
2758 nv_icmd(dev, 0x0000073a, 0x00000080);
2759 nv_icmd(dev, 0x00000786, 0x80000100);
2760 nv_icmd(dev, 0x0000073c, 0x00010100);
2761 nv_icmd(dev, 0x0000073d, 0x02800000);
2762 nv_icmd(dev, 0x00000787, 0x000000cf);
2763 nv_icmd(dev, 0x0000078c, 0x00000008);
2764 nv_icmd(dev, 0x00000792, 0x00000001);
2765 nv_icmd(dev, 0x00000794, 0x00000001);
2766 nv_icmd(dev, 0x00000795, 0x00000001);
2767 nv_icmd(dev, 0x00000796, 0x00000001);
2768 nv_icmd(dev, 0x00000797, 0x000000cf);
2769 nv_icmd(dev, 0x00000836, 0x00000001);
2770 nv_icmd(dev, 0x0000079a, 0x00000002);
2771 nv_icmd(dev, 0x00000833, 0x04444480);
2772 nv_icmd(dev, 0x000007a1, 0x00000001);
2773 nv_icmd(dev, 0x000007a3, 0x00000001);
2774 nv_icmd(dev, 0x000007a4, 0x00000001);
2775 nv_icmd(dev, 0x000007a5, 0x00000001);
2776 nv_icmd(dev, 0x00000831, 0x00000004);
2777 nv_icmd(dev, 0x0000080c, 0x00000002);
2778 nv_icmd(dev, 0x0000080d, 0x00000100);
2779 nv_icmd(dev, 0x0000080e, 0x00000100);
2780 nv_icmd(dev, 0x0000080f, 0x00000001);
2781 nv_icmd(dev, 0x00000823, 0x00000002);
2782 nv_icmd(dev, 0x00000824, 0x00000100);
2783 nv_icmd(dev, 0x00000825, 0x00000100);
2784 nv_icmd(dev, 0x00000826, 0x00000001);
2785 nv_icmd(dev, 0x0000095d, 0x00000001);
2786 nv_icmd(dev, 0x0000082b, 0x00000004);
2787 nv_icmd(dev, 0x00000942, 0x00010001);
2788 nv_icmd(dev, 0x00000943, 0x00000001);
2789 nv_icmd(dev, 0x00000944, 0x00000022);
2790 nv_icmd(dev, 0x000007c5, 0x00010001);
2791 nv_icmd(dev, 0x00000834, 0x00000001);
2792 nv_icmd(dev, 0x000007c7, 0x00000001);
2793 nv_icmd(dev, 0x0000c1b0, 0x0000000f);
2794 nv_icmd(dev, 0x0000c1b1, 0x0000000f);
2795 nv_icmd(dev, 0x0000c1b2, 0x0000000f);
2796 nv_icmd(dev, 0x0000c1b3, 0x0000000f);
2797 nv_icmd(dev, 0x0000c1b4, 0x0000000f);
2798 nv_icmd(dev, 0x0000c1b5, 0x0000000f);
2799 nv_icmd(dev, 0x0000c1b6, 0x0000000f);
2800 nv_icmd(dev, 0x0000c1b7, 0x0000000f);
2801 nv_icmd(dev, 0x0000c1b8, 0x0fac6881);
2802 nv_icmd(dev, 0x0000c1b9, 0x00fac688);
2803 nv_icmd(dev, 0x0001e100, 0x00000001);
2804 nv_icmd(dev, 0x00001000, 0x00000002);
2805 nv_icmd(dev, 0x000006aa, 0x00000001);
2806 nv_icmd(dev, 0x000006ad, 0x00000100);
2807 nv_icmd(dev, 0x000006ae, 0x00000100);
2808 nv_icmd(dev, 0x000006b1, 0x00000011);
2809 nv_icmd(dev, 0x0000078c, 0x00000008);
2810 nv_icmd(dev, 0x00000792, 0x00000001);
2811 nv_icmd(dev, 0x00000794, 0x00000001);
2812 nv_icmd(dev, 0x00000795, 0x00000001);
2813 nv_icmd(dev, 0x00000796, 0x00000001);
2814 nv_icmd(dev, 0x00000797, 0x000000cf);
2815 nv_icmd(dev, 0x0000079a, 0x00000002);
2816 nv_icmd(dev, 0x00000833, 0x04444480);
2817 nv_icmd(dev, 0x000007a1, 0x00000001);
2818 nv_icmd(dev, 0x000007a3, 0x00000001);
2819 nv_icmd(dev, 0x000007a4, 0x00000001);
2820 nv_icmd(dev, 0x000007a5, 0x00000001);
2821 nv_icmd(dev, 0x00000831, 0x00000004);
2822 nv_icmd(dev, 0x0001e100, 0x00000001);
2823 nv_icmd(dev, 0x00001000, 0x00000014);
2824 nv_icmd(dev, 0x00000351, 0x00000100);
2825 nv_icmd(dev, 0x00000957, 0x00000003);
2826 nv_icmd(dev, 0x0000095d, 0x00000001);
2827 nv_icmd(dev, 0x0000082b, 0x00000004);
2828 nv_icmd(dev, 0x00000942, 0x00010001);
2829 nv_icmd(dev, 0x00000943, 0x00000001);
2830 nv_icmd(dev, 0x000007c5, 0x00010001);
2831 nv_icmd(dev, 0x00000834, 0x00000001);
2832 nv_icmd(dev, 0x000007c7, 0x00000001);
2833 nv_icmd(dev, 0x0001e100, 0x00000001);
2834 nv_icmd(dev, 0x00001000, 0x00000001);
2835 nv_icmd(dev, 0x0000080c, 0x00000002);
2836 nv_icmd(dev, 0x0000080d, 0x00000100);
2837 nv_icmd(dev, 0x0000080e, 0x00000100);
2838 nv_icmd(dev, 0x0000080f, 0x00000001);
2839 nv_icmd(dev, 0x00000823, 0x00000002);
2840 nv_icmd(dev, 0x00000824, 0x00000100);
2841 nv_icmd(dev, 0x00000825, 0x00000100);
2842 nv_icmd(dev, 0x00000826, 0x00000001);
2843 nv_icmd(dev, 0x0001e100, 0x00000001);
2844 nv_wr32(dev, 0x400208, 0x00000000);
2845 nv_wr32(dev, 0x404154, 0x00000400);
2846
2847 nvc0_grctx_generate_9097(dev);
2848 nvc0_grctx_generate_902d(dev);
2849 nvc0_grctx_generate_9039(dev);
2850 nvc0_grctx_generate_90c0(dev);
2851
2852 nv_wr32(dev, 0x000260, r000260);
2853 return 0;
2854}
diff --git a/drivers/gpu/drm/nouveau/nvc0_instmem.c b/drivers/gpu/drm/nouveau/nvc0_instmem.c
index 39232085193d..c09091749054 100644
--- a/drivers/gpu/drm/nouveau/nvc0_instmem.c
+++ b/drivers/gpu/drm/nouveau/nvc0_instmem.c
@@ -25,233 +25,207 @@
25#include "drmP.h" 25#include "drmP.h"
26 26
27#include "nouveau_drv.h" 27#include "nouveau_drv.h"
28 28#include "nouveau_vm.h"
29struct nvc0_gpuobj_node { 29
30 struct nouveau_bo *vram; 30struct nvc0_instmem_priv {
31 struct drm_mm_node *ramin; 31 struct nouveau_gpuobj *bar1_pgd;
32 u32 align; 32 struct nouveau_channel *bar1;
33 struct nouveau_gpuobj *bar3_pgd;
34 struct nouveau_channel *bar3;
35 struct nouveau_gpuobj *chan_pgd;
33}; 36};
34 37
35int 38int
36nvc0_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align) 39nvc0_instmem_suspend(struct drm_device *dev)
37{ 40{
38 struct drm_device *dev = gpuobj->dev; 41 struct drm_nouveau_private *dev_priv = dev->dev_private;
39 struct nvc0_gpuobj_node *node = NULL;
40 int ret;
41
42 node = kzalloc(sizeof(*node), GFP_KERNEL);
43 if (!node)
44 return -ENOMEM;
45 node->align = align;
46
47 ret = nouveau_bo_new(dev, NULL, size, align, TTM_PL_FLAG_VRAM,
48 0, 0x0000, true, false, &node->vram);
49 if (ret) {
50 NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
51 return ret;
52 }
53
54 ret = nouveau_bo_pin(node->vram, TTM_PL_FLAG_VRAM);
55 if (ret) {
56 NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
57 nouveau_bo_ref(NULL, &node->vram);
58 return ret;
59 }
60 42
61 gpuobj->vinst = node->vram->bo.mem.start << PAGE_SHIFT; 43 dev_priv->ramin_available = false;
62 gpuobj->size = node->vram->bo.mem.num_pages << PAGE_SHIFT;
63 gpuobj->node = node;
64 return 0; 44 return 0;
65} 45}
66 46
67void 47void
68nvc0_instmem_put(struct nouveau_gpuobj *gpuobj) 48nvc0_instmem_resume(struct drm_device *dev)
69{ 49{
70 struct nvc0_gpuobj_node *node; 50 struct drm_nouveau_private *dev_priv = dev->dev_private;
71 51 struct nvc0_instmem_priv *priv = dev_priv->engine.instmem.priv;
72 node = gpuobj->node;
73 gpuobj->node = NULL;
74 52
75 nouveau_bo_unpin(node->vram); 53 nv_mask(dev, 0x100c80, 0x00000001, 0x00000000);
76 nouveau_bo_ref(NULL, &node->vram); 54 nv_wr32(dev, 0x001704, 0x80000000 | priv->bar1->ramin->vinst >> 12);
77 kfree(node); 55 nv_wr32(dev, 0x001714, 0xc0000000 | priv->bar3->ramin->vinst >> 12);
56 dev_priv->ramin_available = true;
78} 57}
79 58
80int 59static void
81nvc0_instmem_map(struct nouveau_gpuobj *gpuobj) 60nvc0_channel_del(struct nouveau_channel **pchan)
82{ 61{
83 struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; 62 struct nouveau_channel *chan;
84 struct nvc0_gpuobj_node *node = gpuobj->node;
85 struct drm_device *dev = gpuobj->dev;
86 struct drm_mm_node *ramin = NULL;
87 u32 pte, pte_end;
88 u64 vram;
89
90 do {
91 if (drm_mm_pre_get(&dev_priv->ramin_heap))
92 return -ENOMEM;
93
94 spin_lock(&dev_priv->ramin_lock);
95 ramin = drm_mm_search_free(&dev_priv->ramin_heap, gpuobj->size,
96 node->align, 0);
97 if (ramin == NULL) {
98 spin_unlock(&dev_priv->ramin_lock);
99 return -ENOMEM;
100 }
101
102 ramin = drm_mm_get_block_atomic(ramin, gpuobj->size, node->align);
103 spin_unlock(&dev_priv->ramin_lock);
104 } while (ramin == NULL);
105
106 pte = (ramin->start >> 12) << 1;
107 pte_end = ((ramin->size >> 12) << 1) + pte;
108 vram = gpuobj->vinst;
109
110 NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
111 ramin->start, pte, pte_end);
112 NV_DEBUG(dev, "first vram page: 0x%010llx\n", gpuobj->vinst);
113
114 while (pte < pte_end) {
115 nv_wr32(dev, 0x702000 + (pte * 8), (vram >> 8) | 1);
116 nv_wr32(dev, 0x702004 + (pte * 8), 0);
117 vram += 4096;
118 pte++;
119 }
120 dev_priv->engine.instmem.flush(dev);
121 63
122 if (1) { 64 chan = *pchan;
123 u32 chan = nv_rd32(dev, 0x1700) << 16; 65 *pchan = NULL;
124 nv_wr32(dev, 0x100cb8, (chan + 0x1000) >> 8); 66 if (!chan)
125 nv_wr32(dev, 0x100cbc, 0x80000005); 67 return;
126 }
127 68
128 node->ramin = ramin; 69 nouveau_vm_ref(NULL, &chan->vm, NULL);
129 gpuobj->pinst = ramin->start; 70 if (chan->ramin_heap.free_stack.next)
130 return 0; 71 drm_mm_takedown(&chan->ramin_heap);
72 nouveau_gpuobj_ref(NULL, &chan->ramin);
73 kfree(chan);
131} 74}
132 75
133void 76static int
134nvc0_instmem_unmap(struct nouveau_gpuobj *gpuobj) 77nvc0_channel_new(struct drm_device *dev, u32 size, struct nouveau_vm *vm,
78 struct nouveau_channel **pchan,
79 struct nouveau_gpuobj *pgd, u64 vm_size)
135{ 80{
136 struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; 81 struct nouveau_channel *chan;
137 struct nvc0_gpuobj_node *node = gpuobj->node; 82 int ret;
138 u32 pte, pte_end;
139 83
140 if (!node->ramin || !dev_priv->ramin_available) 84 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
141 return; 85 if (!chan)
86 return -ENOMEM;
87 chan->dev = dev;
142 88
143 pte = (node->ramin->start >> 12) << 1; 89 ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
144 pte_end = ((node->ramin->size >> 12) << 1) + pte; 90 if (ret) {
91 nvc0_channel_del(&chan);
92 return ret;
93 }
145 94
146 while (pte < pte_end) { 95 ret = drm_mm_init(&chan->ramin_heap, 0x1000, size - 0x1000);
147 nv_wr32(gpuobj->dev, 0x702000 + (pte * 8), 0); 96 if (ret) {
148 nv_wr32(gpuobj->dev, 0x702004 + (pte * 8), 0); 97 nvc0_channel_del(&chan);
149 pte++; 98 return ret;
150 } 99 }
151 dev_priv->engine.instmem.flush(gpuobj->dev);
152 100
153 spin_lock(&dev_priv->ramin_lock); 101 ret = nouveau_vm_ref(vm, &chan->vm, NULL);
154 drm_mm_put_block(node->ramin); 102 if (ret) {
155 node->ramin = NULL; 103 nvc0_channel_del(&chan);
156 spin_unlock(&dev_priv->ramin_lock); 104 return ret;
157} 105 }
158 106
159void 107 nv_wo32(chan->ramin, 0x0200, lower_32_bits(pgd->vinst));
160nvc0_instmem_flush(struct drm_device *dev) 108 nv_wo32(chan->ramin, 0x0204, upper_32_bits(pgd->vinst));
161{ 109 nv_wo32(chan->ramin, 0x0208, lower_32_bits(vm_size - 1));
162 nv_wr32(dev, 0x070000, 1); 110 nv_wo32(chan->ramin, 0x020c, upper_32_bits(vm_size - 1));
163 if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000)) 111
164 NV_ERROR(dev, "PRAMIN flush timeout\n"); 112 *pchan = chan;
113 return 0;
165} 114}
166 115
167int 116int
168nvc0_instmem_suspend(struct drm_device *dev) 117nvc0_instmem_init(struct drm_device *dev)
169{ 118{
170 struct drm_nouveau_private *dev_priv = dev->dev_private; 119 struct drm_nouveau_private *dev_priv = dev->dev_private;
171 u32 *buf; 120 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
172 int i; 121 struct pci_dev *pdev = dev->pdev;
122 struct nvc0_instmem_priv *priv;
123 struct nouveau_vm *vm = NULL;
124 int ret;
173 125
174 dev_priv->susres.ramin_copy = vmalloc(65536); 126 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
175 if (!dev_priv->susres.ramin_copy) 127 if (!priv)
176 return -ENOMEM; 128 return -ENOMEM;
177 buf = dev_priv->susres.ramin_copy; 129 pinstmem->priv = priv;
178 130
179 for (i = 0; i < 65536; i += 4) 131 /* BAR3 VM */
180 buf[i/4] = nv_rd32(dev, NV04_PRAMIN + i); 132 ret = nouveau_vm_new(dev, 0, pci_resource_len(pdev, 3), 0,
133 &dev_priv->bar3_vm);
134 if (ret)
135 goto error;
136
137 ret = nouveau_gpuobj_new(dev, NULL,
138 (pci_resource_len(pdev, 3) >> 12) * 8, 0,
139 NVOBJ_FLAG_DONT_MAP |
140 NVOBJ_FLAG_ZERO_ALLOC,
141 &dev_priv->bar3_vm->pgt[0].obj[0]);
142 if (ret)
143 goto error;
144 dev_priv->bar3_vm->pgt[0].refcount[0] = 1;
145
146 nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj[0]);
147
148 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096,
149 NVOBJ_FLAG_ZERO_ALLOC, &priv->bar3_pgd);
150 if (ret)
151 goto error;
152
153 ret = nouveau_vm_ref(dev_priv->bar3_vm, &vm, priv->bar3_pgd);
154 if (ret)
155 goto error;
156 nouveau_vm_ref(NULL, &vm, NULL);
157
158 ret = nvc0_channel_new(dev, 8192, dev_priv->bar3_vm, &priv->bar3,
159 priv->bar3_pgd, pci_resource_len(dev->pdev, 3));
160 if (ret)
161 goto error;
162
163 /* BAR1 VM */
164 ret = nouveau_vm_new(dev, 0, pci_resource_len(pdev, 1), 0, &vm);
165 if (ret)
166 goto error;
167
168 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096,
169 NVOBJ_FLAG_ZERO_ALLOC, &priv->bar1_pgd);
170 if (ret)
171 goto error;
172
173 ret = nouveau_vm_ref(vm, &dev_priv->bar1_vm, priv->bar1_pgd);
174 if (ret)
175 goto error;
176 nouveau_vm_ref(NULL, &vm, NULL);
177
178 ret = nvc0_channel_new(dev, 8192, dev_priv->bar1_vm, &priv->bar1,
179 priv->bar1_pgd, pci_resource_len(dev->pdev, 1));
180 if (ret)
181 goto error;
182
183 /* channel vm */
184 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL, &vm);
185 if (ret)
186 goto error;
187
188 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096, 0, &priv->chan_pgd);
189 if (ret)
190 goto error;
191
192 nouveau_vm_ref(vm, &dev_priv->chan_vm, priv->chan_pgd);
193 nouveau_vm_ref(NULL, &vm, NULL);
194
195 nvc0_instmem_resume(dev);
181 return 0; 196 return 0;
197error:
198 nvc0_instmem_takedown(dev);
199 return ret;
182} 200}
183 201
184void 202void
185nvc0_instmem_resume(struct drm_device *dev) 203nvc0_instmem_takedown(struct drm_device *dev)
186{ 204{
187 struct drm_nouveau_private *dev_priv = dev->dev_private; 205 struct drm_nouveau_private *dev_priv = dev->dev_private;
188 u32 *buf = dev_priv->susres.ramin_copy; 206 struct nvc0_instmem_priv *priv = dev_priv->engine.instmem.priv;
189 u64 chan; 207 struct nouveau_vm *vm = NULL;
190 int i;
191 208
192 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram; 209 nvc0_instmem_suspend(dev);
193 nv_wr32(dev, 0x001700, chan >> 16);
194 210
195 for (i = 0; i < 65536; i += 4) 211 nv_wr32(dev, 0x1704, 0x00000000);
196 nv_wr32(dev, NV04_PRAMIN + i, buf[i/4]); 212 nv_wr32(dev, 0x1714, 0x00000000);
197 vfree(dev_priv->susres.ramin_copy);
198 dev_priv->susres.ramin_copy = NULL;
199 213
200 nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12)); 214 nouveau_vm_ref(NULL, &dev_priv->chan_vm, priv->chan_pgd);
201} 215 nouveau_gpuobj_ref(NULL, &priv->chan_pgd);
202 216
203int 217 nvc0_channel_del(&priv->bar1);
204nvc0_instmem_init(struct drm_device *dev) 218 nouveau_vm_ref(NULL, &dev_priv->bar1_vm, priv->bar1_pgd);
205{ 219 nouveau_gpuobj_ref(NULL, &priv->bar1_pgd);
206 struct drm_nouveau_private *dev_priv = dev->dev_private;
207 u64 chan, pgt3, imem, lim3 = dev_priv->ramin_size - 1;
208 int ret, i;
209
210 dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;
211 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
212 imem = 4096 + 4096 + 32768;
213
214 nv_wr32(dev, 0x001700, chan >> 16);
215
216 /* channel setup */
217 nv_wr32(dev, 0x700200, lower_32_bits(chan + 0x1000));
218 nv_wr32(dev, 0x700204, upper_32_bits(chan + 0x1000));
219 nv_wr32(dev, 0x700208, lower_32_bits(lim3));
220 nv_wr32(dev, 0x70020c, upper_32_bits(lim3));
221
222 /* point pgd -> pgt */
223 nv_wr32(dev, 0x701000, 0);
224 nv_wr32(dev, 0x701004, ((chan + 0x2000) >> 8) | 1);
225
226 /* point pgt -> physical vram for channel */
227 pgt3 = 0x2000;
228 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4096, pgt3 += 8) {
229 nv_wr32(dev, 0x700000 + pgt3, ((chan + i) >> 8) | 1);
230 nv_wr32(dev, 0x700004 + pgt3, 0);
231 }
232
233 /* clear rest of pgt */
234 for (; i < dev_priv->ramin_size; i += 4096, pgt3 += 8) {
235 nv_wr32(dev, 0x700000 + pgt3, 0);
236 nv_wr32(dev, 0x700004 + pgt3, 0);
237 }
238 220
239 /* point bar3 at the channel */ 221 nvc0_channel_del(&priv->bar3);
240 nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12)); 222 nouveau_vm_ref(dev_priv->bar3_vm, &vm, NULL);
223 nouveau_vm_ref(NULL, &vm, priv->bar3_pgd);
224 nouveau_gpuobj_ref(NULL, &priv->bar3_pgd);
225 nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj[0]);
226 nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL);
241 227
242 /* Global PRAMIN heap */ 228 dev_priv->engine.instmem.priv = NULL;
243 ret = drm_mm_init(&dev_priv->ramin_heap, imem, 229 kfree(priv);
244 dev_priv->ramin_size - imem);
245 if (ret) {
246 NV_ERROR(dev, "Failed to init RAMIN heap\n");
247 return -ENOMEM;
248 }
249
250 return 0;
251}
252
253void
254nvc0_instmem_takedown(struct drm_device *dev)
255{
256} 230}
257 231
diff --git a/drivers/gpu/drm/nouveau/nvc0_vm.c b/drivers/gpu/drm/nouveau/nvc0_vm.c
new file mode 100644
index 000000000000..4b9251bb0ff4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_vm.c
@@ -0,0 +1,123 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_vm.h"
29
30void
31nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
32 struct nouveau_gpuobj *pgt[2])
33{
34 u32 pde[2] = { 0, 0 };
35
36 if (pgt[0])
37 pde[1] = 0x00000001 | (pgt[0]->vinst >> 8);
38 if (pgt[1])
39 pde[0] = 0x00000001 | (pgt[1]->vinst >> 8);
40
41 nv_wo32(pgd, (index * 8) + 0, pde[0]);
42 nv_wo32(pgd, (index * 8) + 4, pde[1]);
43}
44
45static inline u64
46nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
47{
48 phys >>= 8;
49
50 phys |= 0x00000001; /* present */
51// if (vma->access & NV_MEM_ACCESS_SYS)
52// phys |= 0x00000002;
53
54 phys |= ((u64)target << 32);
55 phys |= ((u64)memtype << 36);
56
57 return phys;
58}
59
60void
61nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
62 struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
63{
64 u32 next = 1 << (vma->node->type - 8);
65
66 phys = nvc0_vm_addr(vma, phys, mem->memtype, 0);
67 pte <<= 3;
68 while (cnt--) {
69 nv_wo32(pgt, pte + 0, lower_32_bits(phys));
70 nv_wo32(pgt, pte + 4, upper_32_bits(phys));
71 phys += next;
72 pte += 8;
73 }
74}
75
76void
77nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
78 u32 pte, dma_addr_t *list, u32 cnt)
79{
80 pte <<= 3;
81 while (cnt--) {
82 u64 phys = nvc0_vm_addr(vma, *list++, 0, 5);
83 nv_wo32(pgt, pte + 0, lower_32_bits(phys));
84 nv_wo32(pgt, pte + 4, upper_32_bits(phys));
85 pte += 8;
86 }
87}
88
89void
90nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
91{
92 pte <<= 3;
93 while (cnt--) {
94 nv_wo32(pgt, pte + 0, 0x00000000);
95 nv_wo32(pgt, pte + 4, 0x00000000);
96 pte += 8;
97 }
98}
99
100void
101nvc0_vm_flush(struct nouveau_vm *vm)
102{
103 struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
104 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
105 struct drm_device *dev = vm->dev;
106 struct nouveau_vm_pgd *vpgd;
107 u32 r100c80, engine;
108
109 pinstmem->flush(vm->dev);
110
111 if (vm == dev_priv->chan_vm)
112 engine = 1;
113 else
114 engine = 5;
115
116 list_for_each_entry(vpgd, &vm->pgd_list, head) {
117 r100c80 = nv_rd32(dev, 0x100c80);
118 nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
119 nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
120 if (!nv_wait(dev, 0x100c80, 0xffffffff, r100c80))
121 NV_ERROR(dev, "vm flush timeout eng %d\n", engine);
122 }
123}
diff --git a/drivers/gpu/drm/nouveau/nvc0_vram.c b/drivers/gpu/drm/nouveau/nvc0_vram.c
new file mode 100644
index 000000000000..858eda5dedd1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_vram.c
@@ -0,0 +1,99 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_mm.h"
28
29bool
30nvc0_vram_flags_valid(struct drm_device *dev, u32 tile_flags)
31{
32 switch (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) {
33 case 0x0000:
34 case 0xfe00:
35 case 0xdb00:
36 case 0x1100:
37 return true;
38 default:
39 break;
40 }
41
42 return false;
43}
44
45int
46nvc0_vram_new(struct drm_device *dev, u64 size, u32 align, u32 ncmin,
47 u32 type, struct nouveau_vram **pvram)
48{
49 struct drm_nouveau_private *dev_priv = dev->dev_private;
50 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
51 struct ttm_mem_type_manager *man = &bdev->man[TTM_PL_VRAM];
52 struct nouveau_mm *mm = man->priv;
53 struct nouveau_mm_node *r;
54 struct nouveau_vram *vram;
55 int ret;
56
57 size >>= 12;
58 align >>= 12;
59 ncmin >>= 12;
60
61 vram = kzalloc(sizeof(*vram), GFP_KERNEL);
62 if (!vram)
63 return -ENOMEM;
64
65 INIT_LIST_HEAD(&vram->regions);
66 vram->dev = dev_priv->dev;
67 vram->memtype = type;
68 vram->size = size;
69
70 mutex_lock(&mm->mutex);
71 do {
72 ret = nouveau_mm_get(mm, 1, size, ncmin, align, &r);
73 if (ret) {
74 mutex_unlock(&mm->mutex);
75 nv50_vram_del(dev, &vram);
76 return ret;
77 }
78
79 list_add_tail(&r->rl_entry, &vram->regions);
80 size -= r->length;
81 } while (size);
82 mutex_unlock(&mm->mutex);
83
84 r = list_first_entry(&vram->regions, struct nouveau_mm_node, rl_entry);
85 vram->offset = (u64)r->offset << 12;
86 *pvram = vram;
87 return 0;
88}
89
90int
91nvc0_vram_init(struct drm_device *dev)
92{
93 struct drm_nouveau_private *dev_priv = dev->dev_private;
94
95 dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
96 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
97 dev_priv->vram_rblock_size = 4096;
98 return 0;
99}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 01:44:06 -0400